1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printMandatoryPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops rGPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant
53 // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>;
56 // t2_so_imm_not - Match an immediate that is a complement
58 def t2_so_imm_not : Operand<i32>,
60 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
61 }], t2_so_imm_not_XFORM>;
63 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
64 def t2_so_imm_neg : Operand<i32>,
66 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
67 }], t2_so_imm_neg_XFORM>;
69 // Break t2_so_imm's up into two pieces. This handles immediates with up to 16
70 // bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
71 // to get the first/second pieces.
72 def t2_so_imm2part : Operand<i32>,
74 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
78 def t2_so_imm2part_1 : SDNodeXForm<imm, [{
79 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
80 return CurDAG->getTargetConstant(V, MVT::i32);
83 def t2_so_imm2part_2 : SDNodeXForm<imm, [{
84 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
85 return CurDAG->getTargetConstant(V, MVT::i32);
88 def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
89 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
93 def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
94 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
95 return CurDAG->getTargetConstant(V, MVT::i32);
98 def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
99 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
100 return CurDAG->getTargetConstant(V, MVT::i32);
103 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
104 def imm1_31 : PatLeaf<(i32 imm), [{
105 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
108 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
109 def imm0_4095 : Operand<i32>,
110 PatLeaf<(i32 imm), [{
111 return (uint32_t)N->getZExtValue() < 4096;
114 def imm0_4095_neg : PatLeaf<(i32 imm), [{
115 return (uint32_t)(-N->getZExtValue()) < 4096;
118 def imm0_255_neg : PatLeaf<(i32 imm), [{
119 return (uint32_t)(-N->getZExtValue()) < 255;
122 def imm0_255_not : PatLeaf<(i32 imm), [{
123 return (uint32_t)(~N->getZExtValue()) < 255;
126 // Define Thumb2 specific addressing modes.
128 // t2addrmode_imm12 := reg + imm12
129 def t2addrmode_imm12 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
131 let PrintMethod = "printT2AddrModeImm12Operand";
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
135 // t2addrmode_imm8 := reg +/- imm8
136 def t2addrmode_imm8 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
138 let PrintMethod = "printT2AddrModeImm8Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 def t2am_imm8_offset : Operand<i32>,
143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
144 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
147 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
148 def t2addrmode_imm8s4 : Operand<i32>,
149 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
150 let PrintMethod = "printT2AddrModeImm8s4Operand";
151 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
154 def t2am_imm8s4_offset : Operand<i32> {
155 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
158 // t2addrmode_so_reg := reg + (reg << imm2)
159 def t2addrmode_so_reg : Operand<i32>,
160 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
161 let PrintMethod = "printT2AddrModeSoRegOperand";
162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
166 //===----------------------------------------------------------------------===//
167 // Multiclass helpers...
170 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
171 /// unary operation that produces a value. These are predicable and can be
172 /// changed to modify CPSR.
173 multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
174 bit Cheap = 0, bit ReMat = 0> {
176 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
178 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
179 let isAsCheapAsAMove = Cheap;
180 let isReMaterializable = ReMat;
181 let Inst{31-27} = 0b11110;
183 let Inst{24-21} = opcod;
184 let Inst{20} = ?; // The S bit.
185 let Inst{19-16} = 0b1111; // Rn
189 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
190 opc, ".w\t$dst, $src",
191 [(set rGPR:$dst, (opnode rGPR:$src))]> {
192 let Inst{31-27} = 0b11101;
193 let Inst{26-25} = 0b01;
194 let Inst{24-21} = opcod;
195 let Inst{20} = ?; // The S bit.
196 let Inst{19-16} = 0b1111; // Rn
197 let Inst{14-12} = 0b000; // imm3
198 let Inst{7-6} = 0b00; // imm2
199 let Inst{5-4} = 0b00; // type
202 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
203 opc, ".w\t$dst, $src",
204 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
205 let Inst{31-27} = 0b11101;
206 let Inst{26-25} = 0b01;
207 let Inst{24-21} = opcod;
208 let Inst{20} = ?; // The S bit.
209 let Inst{19-16} = 0b1111; // Rn
213 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
214 /// binary operation that produces a value. These are predicable and can be
215 /// changed to modify CPSR.
216 multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
217 bit Commutable = 0, string wide = ""> {
219 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
220 opc, "\t$dst, $lhs, $rhs",
221 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
222 let Inst{31-27} = 0b11110;
224 let Inst{24-21} = opcod;
225 let Inst{20} = ?; // The S bit.
229 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
230 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
231 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
232 let isCommutable = Commutable;
233 let Inst{31-27} = 0b11101;
234 let Inst{26-25} = 0b01;
235 let Inst{24-21} = opcod;
236 let Inst{20} = ?; // The S bit.
237 let Inst{14-12} = 0b000; // imm3
238 let Inst{7-6} = 0b00; // imm2
239 let Inst{5-4} = 0b00; // type
242 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
243 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
244 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
245 let Inst{31-27} = 0b11101;
246 let Inst{26-25} = 0b01;
247 let Inst{24-21} = opcod;
248 let Inst{20} = ?; // The S bit.
252 /// T2I_bin_cpsr_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for
253 /// a binary operation that produces a value. These are predicable and modify
255 multiclass T2I_bin_cpsr_irs<bits<4> opcod, string opc, PatFrag opnode,
256 bit Commutable = 0, string wide = ""> {
258 def ri : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs),
259 IIC_iALUi, opc, "\t$dst, $lhs, $rhs",
260 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
261 let Inst{31-27} = 0b11110;
263 let Inst{24-21} = opcod;
264 let Inst{20} = 1; // The S bit.
268 def rr : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs),
269 IIC_iALUr, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
270 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
271 let isCommutable = Commutable;
272 let Inst{31-27} = 0b11101;
273 let Inst{26-25} = 0b01;
274 let Inst{24-21} = opcod;
275 let Inst{20} = 1; // The S bit.
276 let Inst{14-12} = 0b000; // imm3
277 let Inst{7-6} = 0b00; // imm2
278 let Inst{5-4} = 0b00; // type
281 def rs : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs),
282 IIC_iALUsi, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
283 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
284 let Inst{31-27} = 0b11101;
285 let Inst{26-25} = 0b01;
286 let Inst{24-21} = opcod;
287 let Inst{20} = 1; // The S bit.
291 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
292 // the ".w" prefix to indicate that they are wide.
293 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode,
294 bit Commutable = 0> :
295 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
297 /// T2I_bin_sw_irs - Same as T2I_bin_w_irs except these operations set
299 multiclass T2I_bin_sw_irs<bits<4> opcod, string opc, PatFrag opnode,
300 bit Commutable = 0> :
301 T2I_bin_cpsr_irs<opcod, opc, opnode, Commutable, ".w">;
303 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
304 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
305 /// it is equivalent to the T2I_bin_irs counterpart.
306 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
308 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
309 opc, ".w\t$dst, $rhs, $lhs",
310 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
311 let Inst{31-27} = 0b11110;
313 let Inst{24-21} = opcod;
314 let Inst{20} = ?; // The S bit.
318 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
319 opc, "\t$dst, $rhs, $lhs",
320 [/* For disassembly only; pattern left blank */]> {
321 let Inst{31-27} = 0b11101;
322 let Inst{26-25} = 0b01;
323 let Inst{24-21} = opcod;
324 let Inst{20} = ?; // The S bit.
325 let Inst{14-12} = 0b000; // imm3
326 let Inst{7-6} = 0b00; // imm2
327 let Inst{5-4} = 0b00; // type
330 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
331 opc, "\t$dst, $rhs, $lhs",
332 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
333 let Inst{31-27} = 0b11101;
334 let Inst{26-25} = 0b01;
335 let Inst{24-21} = opcod;
336 let Inst{20} = ?; // The S bit.
340 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
341 /// instruction modifies the CPSR register.
342 let Defs = [CPSR] in {
343 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
344 bit Commutable = 0> {
346 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
347 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
348 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
349 let Inst{31-27} = 0b11110;
351 let Inst{24-21} = opcod;
352 let Inst{20} = 1; // The S bit.
356 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
357 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
358 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
359 let isCommutable = Commutable;
360 let Inst{31-27} = 0b11101;
361 let Inst{26-25} = 0b01;
362 let Inst{24-21} = opcod;
363 let Inst{20} = 1; // The S bit.
364 let Inst{14-12} = 0b000; // imm3
365 let Inst{7-6} = 0b00; // imm2
366 let Inst{5-4} = 0b00; // type
369 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
370 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
371 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
372 let Inst{31-27} = 0b11101;
373 let Inst{26-25} = 0b01;
374 let Inst{24-21} = opcod;
375 let Inst{20} = 1; // The S bit.
380 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
381 /// patterns for a binary operation that produces a value.
382 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
383 bit Commutable = 0> {
385 // The register-immediate version is re-materializable. This is useful
386 // in particular for taking the address of a local.
387 let isReMaterializable = 1 in {
388 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
389 opc, ".w\t$dst, $lhs, $rhs",
390 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
391 let Inst{31-27} = 0b11110;
394 let Inst{23-21} = op23_21;
395 let Inst{20} = 0; // The S bit.
400 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
401 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
402 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
403 let Inst{31-27} = 0b11110;
406 let Inst{23-21} = op23_21;
407 let Inst{20} = 0; // The S bit.
411 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
412 opc, ".w\t$dst, $lhs, $rhs",
413 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
414 let isCommutable = Commutable;
415 let Inst{31-27} = 0b11101;
416 let Inst{26-25} = 0b01;
418 let Inst{23-21} = op23_21;
419 let Inst{20} = 0; // The S bit.
420 let Inst{14-12} = 0b000; // imm3
421 let Inst{7-6} = 0b00; // imm2
422 let Inst{5-4} = 0b00; // type
425 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
426 opc, ".w\t$dst, $lhs, $rhs",
427 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
428 let Inst{31-27} = 0b11101;
429 let Inst{26-25} = 0b01;
431 let Inst{23-21} = op23_21;
432 let Inst{20} = 0; // The S bit.
436 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
437 /// for a binary operation that produces a value and use the carry
438 /// bit. It's not predicable.
439 let Uses = [CPSR] in {
440 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
441 bit Commutable = 0> {
443 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
444 opc, "\t$dst, $lhs, $rhs",
445 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
446 Requires<[IsThumb2]> {
447 let Inst{31-27} = 0b11110;
449 let Inst{24-21} = opcod;
450 let Inst{20} = 0; // The S bit.
454 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
455 opc, ".w\t$dst, $lhs, $rhs",
456 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
457 Requires<[IsThumb2]> {
458 let isCommutable = Commutable;
459 let Inst{31-27} = 0b11101;
460 let Inst{26-25} = 0b01;
461 let Inst{24-21} = opcod;
462 let Inst{20} = 0; // The S bit.
463 let Inst{14-12} = 0b000; // imm3
464 let Inst{7-6} = 0b00; // imm2
465 let Inst{5-4} = 0b00; // type
468 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
469 opc, ".w\t$dst, $lhs, $rhs",
470 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
471 Requires<[IsThumb2]> {
472 let Inst{31-27} = 0b11101;
473 let Inst{26-25} = 0b01;
474 let Inst{24-21} = opcod;
475 let Inst{20} = 0; // The S bit.
479 // Carry setting variants
480 let Defs = [CPSR] in {
481 multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
482 bit Commutable = 0> {
484 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
485 opc, "\t$dst, $lhs, $rhs",
486 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
487 Requires<[IsThumb2]> {
488 let Inst{31-27} = 0b11110;
490 let Inst{24-21} = opcod;
491 let Inst{20} = 1; // The S bit.
495 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
496 opc, ".w\t$dst, $lhs, $rhs",
497 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
498 Requires<[IsThumb2]> {
499 let isCommutable = Commutable;
500 let Inst{31-27} = 0b11101;
501 let Inst{26-25} = 0b01;
502 let Inst{24-21} = opcod;
503 let Inst{20} = 1; // The S bit.
504 let Inst{14-12} = 0b000; // imm3
505 let Inst{7-6} = 0b00; // imm2
506 let Inst{5-4} = 0b00; // type
509 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
510 opc, ".w\t$dst, $lhs, $rhs",
511 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
512 Requires<[IsThumb2]> {
513 let Inst{31-27} = 0b11101;
514 let Inst{26-25} = 0b01;
515 let Inst{24-21} = opcod;
516 let Inst{20} = 1; // The S bit.
522 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
523 /// version is not needed since this is only for codegen.
524 let Defs = [CPSR] in {
525 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
527 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
528 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
529 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
530 let Inst{31-27} = 0b11110;
532 let Inst{24-21} = opcod;
533 let Inst{20} = 1; // The S bit.
537 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
538 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
539 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
540 let Inst{31-27} = 0b11101;
541 let Inst{26-25} = 0b01;
542 let Inst{24-21} = opcod;
543 let Inst{20} = 1; // The S bit.
548 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
549 // rotate operation that produces a value.
550 multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
552 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
553 opc, ".w\t$dst, $lhs, $rhs",
554 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
555 let Inst{31-27} = 0b11101;
556 let Inst{26-21} = 0b010010;
557 let Inst{19-16} = 0b1111; // Rn
558 let Inst{5-4} = opcod;
561 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
562 opc, ".w\t$dst, $lhs, $rhs",
563 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
564 let Inst{31-27} = 0b11111;
565 let Inst{26-23} = 0b0100;
566 let Inst{22-21} = opcod;
567 let Inst{15-12} = 0b1111;
568 let Inst{7-4} = 0b0000;
572 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
573 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
574 /// a explicit result, only implicitly set CPSR.
575 let isCompare = 1, Defs = [CPSR] in {
576 multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
578 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
579 opc, ".w\t$lhs, $rhs",
580 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> {
581 let Inst{31-27} = 0b11110;
583 let Inst{24-21} = opcod;
584 let Inst{20} = 1; // The S bit.
586 let Inst{11-8} = 0b1111; // Rd
589 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
590 opc, ".w\t$lhs, $rhs",
591 [(opnode GPR:$lhs, rGPR:$rhs)]> {
592 let Inst{31-27} = 0b11101;
593 let Inst{26-25} = 0b01;
594 let Inst{24-21} = opcod;
595 let Inst{20} = 1; // The S bit.
596 let Inst{14-12} = 0b000; // imm3
597 let Inst{11-8} = 0b1111; // Rd
598 let Inst{7-6} = 0b00; // imm2
599 let Inst{5-4} = 0b00; // type
602 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
603 opc, ".w\t$lhs, $rhs",
604 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> {
605 let Inst{31-27} = 0b11101;
606 let Inst{26-25} = 0b01;
607 let Inst{24-21} = opcod;
608 let Inst{20} = 1; // The S bit.
609 let Inst{11-8} = 0b1111; // Rd
614 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
615 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> {
616 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
617 opc, ".w\t$dst, $addr",
618 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
619 let Inst{31-27} = 0b11111;
620 let Inst{26-25} = 0b00;
621 let Inst{24} = signed;
623 let Inst{22-21} = opcod;
624 let Inst{20} = 1; // load
626 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
627 opc, "\t$dst, $addr",
628 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> {
629 let Inst{31-27} = 0b11111;
630 let Inst{26-25} = 0b00;
631 let Inst{24} = signed;
633 let Inst{22-21} = opcod;
634 let Inst{20} = 1; // load
636 // Offset: index==TRUE, wback==FALSE
637 let Inst{10} = 1; // The P bit.
638 let Inst{8} = 0; // The W bit.
640 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
641 opc, ".w\t$dst, $addr",
642 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
643 let Inst{31-27} = 0b11111;
644 let Inst{26-25} = 0b00;
645 let Inst{24} = signed;
647 let Inst{22-21} = opcod;
648 let Inst{20} = 1; // load
649 let Inst{11-6} = 0b000000;
651 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
652 opc, ".w\t$dst, $addr",
653 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
654 let isReMaterializable = 1;
655 let Inst{31-27} = 0b11111;
656 let Inst{26-25} = 0b00;
657 let Inst{24} = signed;
658 let Inst{23} = ?; // add = (U == '1')
659 let Inst{22-21} = opcod;
660 let Inst{20} = 1; // load
661 let Inst{19-16} = 0b1111; // Rn
665 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
666 multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> {
667 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
668 opc, ".w\t$src, $addr",
669 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
670 let Inst{31-27} = 0b11111;
671 let Inst{26-23} = 0b0001;
672 let Inst{22-21} = opcod;
673 let Inst{20} = 0; // !load
675 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
676 opc, "\t$src, $addr",
677 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> {
678 let Inst{31-27} = 0b11111;
679 let Inst{26-23} = 0b0000;
680 let Inst{22-21} = opcod;
681 let Inst{20} = 0; // !load
683 // Offset: index==TRUE, wback==FALSE
684 let Inst{10} = 1; // The P bit.
685 let Inst{8} = 0; // The W bit.
687 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
688 opc, ".w\t$src, $addr",
689 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
690 let Inst{31-27} = 0b11111;
691 let Inst{26-23} = 0b0000;
692 let Inst{22-21} = opcod;
693 let Inst{20} = 0; // !load
694 let Inst{11-6} = 0b000000;
698 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
699 /// register and one whose operand is a register rotated by 8/16/24.
700 multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
701 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
702 opc, ".w\t$dst, $src",
703 [(set rGPR:$dst, (opnode rGPR:$src))]> {
704 let Inst{31-27} = 0b11111;
705 let Inst{26-23} = 0b0100;
706 let Inst{22-20} = opcod;
707 let Inst{19-16} = 0b1111; // Rn
708 let Inst{15-12} = 0b1111;
710 let Inst{5-4} = 0b00; // rotate
712 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
713 opc, ".w\t$dst, $src, ror $rot",
714 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
715 let Inst{31-27} = 0b11111;
716 let Inst{26-23} = 0b0100;
717 let Inst{22-20} = opcod;
718 let Inst{19-16} = 0b1111; // Rn
719 let Inst{15-12} = 0b1111;
721 let Inst{5-4} = {?,?}; // rotate
725 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
726 multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
727 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
729 [(set rGPR:$dst, (opnode rGPR:$src))]>,
730 Requires<[HasT2ExtractPack]> {
731 let Inst{31-27} = 0b11111;
732 let Inst{26-23} = 0b0100;
733 let Inst{22-20} = opcod;
734 let Inst{19-16} = 0b1111; // Rn
735 let Inst{15-12} = 0b1111;
737 let Inst{5-4} = 0b00; // rotate
739 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
740 opc, "\t$dst, $src, ror $rot",
741 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
742 Requires<[HasT2ExtractPack]> {
743 let Inst{31-27} = 0b11111;
744 let Inst{26-23} = 0b0100;
745 let Inst{22-20} = opcod;
746 let Inst{19-16} = 0b1111; // Rn
747 let Inst{15-12} = 0b1111;
749 let Inst{5-4} = {?,?}; // rotate
753 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
755 multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
756 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
757 opc, "\t$dst, $src", []> {
758 let Inst{31-27} = 0b11111;
759 let Inst{26-23} = 0b0100;
760 let Inst{22-20} = opcod;
761 let Inst{19-16} = 0b1111; // Rn
762 let Inst{15-12} = 0b1111;
764 let Inst{5-4} = 0b00; // rotate
766 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
767 opc, "\t$dst, $src, ror $rot", []> {
768 let Inst{31-27} = 0b11111;
769 let Inst{26-23} = 0b0100;
770 let Inst{22-20} = opcod;
771 let Inst{19-16} = 0b1111; // Rn
772 let Inst{15-12} = 0b1111;
774 let Inst{5-4} = {?,?}; // rotate
778 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
779 /// register and one whose operand is a register rotated by 8/16/24.
780 multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
781 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
782 opc, "\t$dst, $LHS, $RHS",
783 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
784 Requires<[HasT2ExtractPack]> {
785 let Inst{31-27} = 0b11111;
786 let Inst{26-23} = 0b0100;
787 let Inst{22-20} = opcod;
788 let Inst{15-12} = 0b1111;
790 let Inst{5-4} = 0b00; // rotate
792 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
793 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
794 [(set rGPR:$dst, (opnode rGPR:$LHS,
795 (rotr rGPR:$RHS, rot_imm:$rot)))]>,
796 Requires<[HasT2ExtractPack]> {
797 let Inst{31-27} = 0b11111;
798 let Inst{26-23} = 0b0100;
799 let Inst{22-20} = opcod;
800 let Inst{15-12} = 0b1111;
802 let Inst{5-4} = {?,?}; // rotate
806 // DO variant - disassembly only, no pattern
808 multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
809 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
810 opc, "\t$dst, $LHS, $RHS", []> {
811 let Inst{31-27} = 0b11111;
812 let Inst{26-23} = 0b0100;
813 let Inst{22-20} = opcod;
814 let Inst{15-12} = 0b1111;
816 let Inst{5-4} = 0b00; // rotate
818 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
819 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
820 let Inst{31-27} = 0b11111;
821 let Inst{26-23} = 0b0100;
822 let Inst{22-20} = opcod;
823 let Inst{15-12} = 0b1111;
825 let Inst{5-4} = {?,?}; // rotate
829 //===----------------------------------------------------------------------===//
831 //===----------------------------------------------------------------------===//
833 //===----------------------------------------------------------------------===//
834 // Miscellaneous Instructions.
837 // LEApcrel - Load a pc-relative address into a register without offending the
839 let neverHasSideEffects = 1 in {
840 let isReMaterializable = 1 in
841 def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
842 "adr${p}.w\t$dst, #$label", []> {
843 let Inst{31-27} = 0b11110;
844 let Inst{25-24} = 0b10;
845 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
848 let Inst{19-16} = 0b1111; // Rn
851 } // neverHasSideEffects
852 def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
853 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
854 "adr${p}.w\t$dst, #${label}_${id}", []> {
855 let Inst{31-27} = 0b11110;
856 let Inst{25-24} = 0b10;
857 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
860 let Inst{19-16} = 0b1111; // Rn
864 // ADD r, sp, {so_imm|i12}
865 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
866 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> {
867 let Inst{31-27} = 0b11110;
869 let Inst{24-21} = 0b1000;
870 let Inst{20} = ?; // The S bit.
871 let Inst{19-16} = 0b1101; // Rn = sp
874 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
875 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> {
876 let Inst{31-27} = 0b11110;
878 let Inst{24-21} = 0b0000;
879 let Inst{20} = 0; // The S bit.
880 let Inst{19-16} = 0b1101; // Rn = sp
885 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
886 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> {
887 let Inst{31-27} = 0b11101;
888 let Inst{26-25} = 0b01;
889 let Inst{24-21} = 0b1000;
890 let Inst{20} = ?; // The S bit.
891 let Inst{19-16} = 0b1101; // Rn = sp
895 // SUB r, sp, {so_imm|i12}
896 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
897 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> {
898 let Inst{31-27} = 0b11110;
900 let Inst{24-21} = 0b1101;
901 let Inst{20} = ?; // The S bit.
902 let Inst{19-16} = 0b1101; // Rn = sp
905 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
906 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> {
907 let Inst{31-27} = 0b11110;
909 let Inst{24-21} = 0b0101;
910 let Inst{20} = 0; // The S bit.
911 let Inst{19-16} = 0b1101; // Rn = sp
916 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
918 "sub", "\t$dst, $sp, $rhs", []> {
919 let Inst{31-27} = 0b11101;
920 let Inst{26-25} = 0b01;
921 let Inst{24-21} = 0b1101;
922 let Inst{20} = ?; // The S bit.
923 let Inst{19-16} = 0b1101; // Rn = sp
927 // Signed and unsigned division on v7-M
928 def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
929 "sdiv", "\t$dst, $a, $b",
930 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
931 Requires<[HasDivide]> {
932 let Inst{31-27} = 0b11111;
933 let Inst{26-21} = 0b011100;
935 let Inst{15-12} = 0b1111;
936 let Inst{7-4} = 0b1111;
939 def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
940 "udiv", "\t$dst, $a, $b",
941 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
942 Requires<[HasDivide]> {
943 let Inst{31-27} = 0b11111;
944 let Inst{26-21} = 0b011101;
946 let Inst{15-12} = 0b1111;
947 let Inst{7-4} = 0b1111;
950 //===----------------------------------------------------------------------===//
951 // Load / store Instructions.
955 let canFoldAsLoad = 1, isReMaterializable = 1 in
956 defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>;
958 // Loads with zero extension
959 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
960 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
962 // Loads with sign extension
963 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
964 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
966 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
968 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
969 (ins t2addrmode_imm8s4:$addr),
970 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
971 def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
972 (ins i32imm:$addr), IIC_iLoadi,
973 "ldrd", "\t$dst1, $addr", []> {
974 let Inst{19-16} = 0b1111; // Rn
976 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
978 // zextload i1 -> zextload i8
979 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
980 (t2LDRBi12 t2addrmode_imm12:$addr)>;
981 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
982 (t2LDRBi8 t2addrmode_imm8:$addr)>;
983 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
984 (t2LDRBs t2addrmode_so_reg:$addr)>;
985 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
986 (t2LDRBpci tconstpool:$addr)>;
988 // extload -> zextload
989 // FIXME: Reduce the number of patterns by legalizing extload to zextload
991 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
992 (t2LDRBi12 t2addrmode_imm12:$addr)>;
993 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
994 (t2LDRBi8 t2addrmode_imm8:$addr)>;
995 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
996 (t2LDRBs t2addrmode_so_reg:$addr)>;
997 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
998 (t2LDRBpci tconstpool:$addr)>;
1000 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1001 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1002 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1003 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1004 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1005 (t2LDRBs t2addrmode_so_reg:$addr)>;
1006 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1007 (t2LDRBpci tconstpool:$addr)>;
1009 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1010 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1011 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1012 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1013 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1014 (t2LDRHs t2addrmode_so_reg:$addr)>;
1015 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1016 (t2LDRHpci tconstpool:$addr)>;
1018 // FIXME: The destination register of the loads and stores can't be PC, but
1019 // can be SP. We need another regclass (similar to rGPR) to represent
1020 // that. Not a pressing issue since these are selected manually,
1024 let mayLoad = 1, neverHasSideEffects = 1 in {
1025 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1026 (ins t2addrmode_imm8:$addr),
1027 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1028 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb",
1031 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1032 (ins GPR:$base, t2am_imm8_offset:$offset),
1033 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1034 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb",
1037 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1038 (ins t2addrmode_imm8:$addr),
1039 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1040 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb",
1042 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1043 (ins GPR:$base, t2am_imm8_offset:$offset),
1044 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1045 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb",
1048 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1049 (ins t2addrmode_imm8:$addr),
1050 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1051 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb",
1053 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1054 (ins GPR:$base, t2am_imm8_offset:$offset),
1055 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1056 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb",
1059 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1060 (ins t2addrmode_imm8:$addr),
1061 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1062 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb",
1064 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1065 (ins GPR:$base, t2am_imm8_offset:$offset),
1066 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1067 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb",
1070 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb),
1071 (ins t2addrmode_imm8:$addr),
1072 AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
1073 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb",
1075 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1076 (ins GPR:$base, t2am_imm8_offset:$offset),
1077 AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
1078 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb",
1080 } // mayLoad = 1, neverHasSideEffects = 1
1082 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1083 // for disassembly only.
1084 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1085 class T2IldT<bit signed, bits<2> type, string opc>
1086 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc,
1087 "\t$dst, $addr", []> {
1088 let Inst{31-27} = 0b11111;
1089 let Inst{26-25} = 0b00;
1090 let Inst{24} = signed;
1092 let Inst{22-21} = type;
1093 let Inst{20} = 1; // load
1095 let Inst{10-8} = 0b110; // PUW.
1098 def t2LDRT : T2IldT<0, 0b10, "ldrt">;
1099 def t2LDRBT : T2IldT<0, 0b00, "ldrbt">;
1100 def t2LDRHT : T2IldT<0, 0b01, "ldrht">;
1101 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">;
1102 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">;
1105 defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
1106 defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1107 defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1110 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1111 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1112 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
1113 IIC_iStorer, "strd", "\t$src1, $addr", []>;
1116 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1117 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1118 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1119 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1121 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1123 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1124 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1125 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1126 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1128 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1130 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1131 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1132 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1133 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1135 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1137 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1138 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1139 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1140 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1142 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1144 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1145 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1146 AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
1147 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1149 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1151 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1152 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
1153 AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
1154 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1156 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
1158 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1160 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1161 class T2IstT<bits<2> type, string opc>
1162 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc,
1163 "\t$src, $addr", []> {
1164 let Inst{31-27} = 0b11111;
1165 let Inst{26-25} = 0b00;
1166 let Inst{24} = 0; // not signed
1168 let Inst{22-21} = type;
1169 let Inst{20} = 0; // store
1171 let Inst{10-8} = 0b110; // PUW
1174 def t2STRT : T2IstT<0b10, "strt">;
1175 def t2STRBT : T2IstT<0b00, "strbt">;
1176 def t2STRHT : T2IstT<0b01, "strht">;
1178 // ldrd / strd pre / post variants
1179 // For disassembly only.
1181 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1182 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1183 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
1185 def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
1186 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary,
1187 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
1189 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
1190 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1191 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
1193 def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1194 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
1195 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>;
1197 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1198 // data/instruction access. These are for disassembly only.
1200 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
1201 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
1202 multiclass T2Ipl<bit instr, bit write, string opc> {
1204 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc,
1205 "\t[$base, $imm]", []> {
1206 let Inst{31-25} = 0b1111100;
1207 let Inst{24} = instr;
1208 let Inst{23} = 1; // U = 1
1210 let Inst{21} = write;
1212 let Inst{15-12} = 0b1111;
1215 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1216 "\t[$base, $imm]", []> {
1217 let Inst{31-25} = 0b1111100;
1218 let Inst{24} = instr;
1219 let Inst{23} = 0; // U = 0
1221 let Inst{21} = write;
1223 let Inst{15-12} = 0b1111;
1224 let Inst{11-8} = 0b1100;
1227 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc,
1228 "\t[pc, $imm]", []> {
1229 let Inst{31-25} = 0b1111100;
1230 let Inst{24} = instr;
1231 let Inst{23} = ?; // add = (U == 1)
1233 let Inst{21} = write;
1235 let Inst{19-16} = 0b1111; // Rn = 0b1111
1236 let Inst{15-12} = 0b1111;
1239 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc,
1240 "\t[$base, $a]", []> {
1241 let Inst{31-25} = 0b1111100;
1242 let Inst{24} = instr;
1243 let Inst{23} = 0; // add = TRUE for T1
1245 let Inst{21} = write;
1247 let Inst{15-12} = 0b1111;
1248 let Inst{11-6} = 0000000;
1249 let Inst{5-4} = 0b00; // no shift is applied
1252 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc,
1253 "\t[$base, $a, lsl $shamt]", []> {
1254 let Inst{31-25} = 0b1111100;
1255 let Inst{24} = instr;
1256 let Inst{23} = 0; // add = TRUE for T1
1258 let Inst{21} = write;
1260 let Inst{15-12} = 0b1111;
1261 let Inst{11-6} = 0000000;
1265 defm t2PLD : T2Ipl<0, 0, "pld">;
1266 defm t2PLDW : T2Ipl<0, 1, "pldw">;
1267 defm t2PLI : T2Ipl<1, 0, "pli">;
1269 //===----------------------------------------------------------------------===//
1270 // Load / store multiple Instructions.
1273 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1274 def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1275 reglist:$dsts, variable_ops), IIC_iLoadm,
1276 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
1277 let Inst{31-27} = 0b11101;
1278 let Inst{26-25} = 0b00;
1279 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1281 let Inst{21} = 0; // The W bit.
1282 let Inst{20} = 1; // Load
1285 def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1286 reglist:$dsts, variable_ops), IIC_iLoadm,
1287 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
1288 "$addr.addr = $wb", []> {
1289 let Inst{31-27} = 0b11101;
1290 let Inst{26-25} = 0b00;
1291 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1293 let Inst{21} = 1; // The W bit.
1294 let Inst{20} = 1; // Load
1296 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1298 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1299 def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
1300 reglist:$srcs, variable_ops), IIC_iStorem,
1301 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
1302 let Inst{31-27} = 0b11101;
1303 let Inst{26-25} = 0b00;
1304 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1306 let Inst{21} = 0; // The W bit.
1307 let Inst{20} = 0; // Store
1310 def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1311 reglist:$srcs, variable_ops),
1313 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs",
1314 "$addr.addr = $wb", []> {
1315 let Inst{31-27} = 0b11101;
1316 let Inst{26-25} = 0b00;
1317 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
1319 let Inst{21} = 1; // The W bit.
1320 let Inst{20} = 0; // Store
1322 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1324 //===----------------------------------------------------------------------===//
1325 // Move Instructions.
1328 let neverHasSideEffects = 1 in
1329 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1330 "mov", ".w\t$dst, $src", []> {
1331 let Inst{31-27} = 0b11101;
1332 let Inst{26-25} = 0b01;
1333 let Inst{24-21} = 0b0010;
1334 let Inst{20} = ?; // The S bit.
1335 let Inst{19-16} = 0b1111; // Rn
1336 let Inst{14-12} = 0b000;
1337 let Inst{7-4} = 0b0000;
1340 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1341 let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
1342 def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
1343 "mov", ".w\t$dst, $src",
1344 [(set rGPR:$dst, t2_so_imm:$src)]> {
1345 let Inst{31-27} = 0b11110;
1347 let Inst{24-21} = 0b0010;
1348 let Inst{20} = ?; // The S bit.
1349 let Inst{19-16} = 0b1111; // Rn
1353 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1354 def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
1355 "movw", "\t$dst, $src",
1356 [(set rGPR:$dst, imm0_65535:$src)]> {
1357 let Inst{31-27} = 0b11110;
1359 let Inst{24-21} = 0b0010;
1360 let Inst{20} = 0; // The S bit.
1364 let Constraints = "$src = $dst" in
1365 def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1366 "movt", "\t$dst, $imm",
1368 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1369 let Inst{31-27} = 0b11110;
1371 let Inst{24-21} = 0b0110;
1372 let Inst{20} = 0; // The S bit.
1376 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1378 //===----------------------------------------------------------------------===//
1379 // Extend Instructions.
1384 defm t2SXTB : T2I_unary_rrot<0b100, "sxtb",
1385 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1386 defm t2SXTH : T2I_unary_rrot<0b000, "sxth",
1387 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1388 defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">;
1390 defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab",
1391 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1392 defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah",
1393 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1394 defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">;
1396 // TODO: SXT(A){B|H}16 - done for disassembly only
1400 let AddedComplexity = 16 in {
1401 defm t2UXTB : T2I_unary_rrot<0b101, "uxtb",
1402 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1403 defm t2UXTH : T2I_unary_rrot<0b001, "uxth",
1404 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1405 defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
1406 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1408 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1409 // The transformation should probably be done as a combiner action
1410 // instead so we can include a check for masking back in the upper
1411 // eight bits of the source into the lower eight bits of the result.
1412 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1413 // (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
1414 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1415 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
1417 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
1418 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1419 defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah",
1420 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1421 defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">;
1424 //===----------------------------------------------------------------------===//
1425 // Arithmetic Instructions.
1428 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1429 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1430 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1431 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1433 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1434 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1435 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1436 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1437 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1439 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1440 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1441 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1442 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1443 defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1444 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1445 defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1446 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1449 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1450 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1451 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1452 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1454 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1455 // The assume-no-carry-in form uses the negation of the input since add/sub
1456 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1457 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1459 // The AddedComplexity preferences the first variant over the others since
1460 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1461 let AddedComplexity = 1 in
1462 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1463 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1464 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1465 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1466 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1467 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1468 let AddedComplexity = 1 in
1469 def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
1470 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1471 def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
1472 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1473 // The with-carry-in form matches bitwise not instead of the negation.
1474 // Effectively, the inverse interpretation of the carry flag already accounts
1475 // for part of the negation.
1476 let AddedComplexity = 1 in
1477 def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
1478 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
1479 def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
1480 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
1482 // Select Bytes -- for disassembly only
1484 def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel",
1485 "\t$dst, $a, $b", []> {
1486 let Inst{31-27} = 0b11111;
1487 let Inst{26-24} = 0b010;
1489 let Inst{22-20} = 0b010;
1490 let Inst{15-12} = 0b1111;
1492 let Inst{6-4} = 0b000;
1495 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1496 // And Miscellaneous operations -- for disassembly only
1497 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1498 list<dag> pat = [/* For disassembly only; pattern left blank */]>
1499 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
1500 "\t$dst, $a, $b", pat> {
1501 let Inst{31-27} = 0b11111;
1502 let Inst{26-23} = 0b0101;
1503 let Inst{22-20} = op22_20;
1504 let Inst{15-12} = 0b1111;
1505 let Inst{7-4} = op7_4;
1508 // Saturating add/subtract -- for disassembly only
1510 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1511 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
1512 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1513 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1514 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1515 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
1516 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
1517 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1518 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1519 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
1520 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1521 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1522 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1523 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1524 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1525 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1526 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1527 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1529 // Signed/Unsigned add/subtract -- for disassembly only
1531 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1532 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1533 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1534 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1535 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1536 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1537 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1538 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1539 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1540 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1541 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1542 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1544 // Signed/Unsigned halving add/subtract -- for disassembly only
1546 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1547 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1548 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1549 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1550 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1551 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1552 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1553 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1554 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1555 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1556 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1557 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1559 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1561 def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1562 (ins rGPR:$a, rGPR:$b),
1563 NoItinerary, "usad8", "\t$dst, $a, $b", []> {
1564 let Inst{15-12} = 0b1111;
1566 def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
1567 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
1568 "\t$dst, $a, $b, $acc", []>;
1570 // Signed/Unsigned saturate -- for disassembly only
1572 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1573 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1574 [/* For disassembly only; pattern left blank */]> {
1575 let Inst{31-27} = 0b11110;
1576 let Inst{25-22} = 0b1100;
1581 def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1582 "ssat16", "\t$dst, $bit_pos, $a",
1583 [/* For disassembly only; pattern left blank */]> {
1584 let Inst{31-27} = 0b11110;
1585 let Inst{25-22} = 0b1100;
1588 let Inst{21} = 1; // sh = '1'
1589 let Inst{14-12} = 0b000; // imm3 = '000'
1590 let Inst{7-6} = 0b00; // imm2 = '00'
1593 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
1594 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1595 [/* For disassembly only; pattern left blank */]> {
1596 let Inst{31-27} = 0b11110;
1597 let Inst{25-22} = 0b1110;
1602 def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
1603 "usat16", "\t$dst, $bit_pos, $a",
1604 [/* For disassembly only; pattern left blank */]> {
1605 let Inst{31-27} = 0b11110;
1606 let Inst{25-22} = 0b1110;
1609 let Inst{21} = 1; // sh = '1'
1610 let Inst{14-12} = 0b000; // imm3 = '000'
1611 let Inst{7-6} = 0b00; // imm2 = '00'
1614 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1615 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1617 //===----------------------------------------------------------------------===//
1618 // Shift and rotate Instructions.
1621 defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1622 defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1623 defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1624 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1626 let Uses = [CPSR] in {
1627 def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1628 "rrx", "\t$dst, $src",
1629 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
1630 let Inst{31-27} = 0b11101;
1631 let Inst{26-25} = 0b01;
1632 let Inst{24-21} = 0b0010;
1633 let Inst{20} = ?; // The S bit.
1634 let Inst{19-16} = 0b1111; // Rn
1635 let Inst{14-12} = 0b000;
1636 let Inst{7-4} = 0b0011;
1640 let Defs = [CPSR] in {
1641 def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1642 "lsrs", ".w\t$dst, $src, #1",
1643 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
1644 let Inst{31-27} = 0b11101;
1645 let Inst{26-25} = 0b01;
1646 let Inst{24-21} = 0b0010;
1647 let Inst{20} = 1; // The S bit.
1648 let Inst{19-16} = 0b1111; // Rn
1649 let Inst{5-4} = 0b01; // Shift type.
1650 // Shift amount = Inst{14-12:7-6} = 1.
1651 let Inst{14-12} = 0b000;
1652 let Inst{7-6} = 0b01;
1654 def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
1655 "asrs", ".w\t$dst, $src, #1",
1656 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
1657 let Inst{31-27} = 0b11101;
1658 let Inst{26-25} = 0b01;
1659 let Inst{24-21} = 0b0010;
1660 let Inst{20} = 1; // The S bit.
1661 let Inst{19-16} = 0b1111; // Rn
1662 let Inst{5-4} = 0b10; // Shift type.
1663 // Shift amount = Inst{14-12:7-6} = 1.
1664 let Inst{14-12} = 0b000;
1665 let Inst{7-6} = 0b01;
1669 //===----------------------------------------------------------------------===//
1670 // Bitwise Instructions.
1673 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1674 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1675 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1676 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1677 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1678 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1680 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1681 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1683 //let Defs = [CPSR] in
1684 defm t2ANDS : T2I_bin_sw_irs<0b0000, "and",
1685 BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>;
1687 let Constraints = "$src = $dst" in
1688 def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1689 IIC_iUNAsi, "bfc", "\t$dst, $imm",
1690 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
1691 let Inst{31-27} = 0b11110;
1693 let Inst{24-20} = 0b10110;
1694 let Inst{19-16} = 0b1111; // Rn
1698 def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1699 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
1700 let Inst{31-27} = 0b11110;
1702 let Inst{24-20} = 0b10100;
1706 def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
1707 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
1708 let Inst{31-27} = 0b11110;
1710 let Inst{24-20} = 0b11100;
1714 // A8.6.18 BFI - Bitfield insert (Encoding T1)
1715 let Constraints = "$src = $dst" in
1716 def t2BFI : T2I<(outs rGPR:$dst),
1717 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
1718 IIC_iALUi, "bfi", "\t$dst, $val, $imm",
1719 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
1720 bf_inv_mask_imm:$imm))]> {
1721 let Inst{31-27} = 0b11110;
1723 let Inst{24-20} = 0b10110;
1727 defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS,
1728 (not node:$RHS))>, 0, "">;
1730 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
1731 let AddedComplexity = 1 in
1732 defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
1735 let AddedComplexity = 1 in
1736 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
1737 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
1739 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
1740 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
1741 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
1742 Requires<[IsThumb2]>;
1744 def : T2Pat<(t2_so_imm_not:$src),
1745 (t2MVNi t2_so_imm_not:$src)>;
1747 //===----------------------------------------------------------------------===//
1748 // Multiply Instructions.
1750 let isCommutable = 1 in
1751 def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1752 "mul", "\t$dst, $a, $b",
1753 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
1754 let Inst{31-27} = 0b11111;
1755 let Inst{26-23} = 0b0110;
1756 let Inst{22-20} = 0b000;
1757 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1758 let Inst{7-4} = 0b0000; // Multiply
1761 def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1762 "mla", "\t$dst, $a, $b, $c",
1763 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
1764 let Inst{31-27} = 0b11111;
1765 let Inst{26-23} = 0b0110;
1766 let Inst{22-20} = 0b000;
1767 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1768 let Inst{7-4} = 0b0000; // Multiply
1771 def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1772 "mls", "\t$dst, $a, $b, $c",
1773 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
1774 let Inst{31-27} = 0b11111;
1775 let Inst{26-23} = 0b0110;
1776 let Inst{22-20} = 0b000;
1777 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1778 let Inst{7-4} = 0b0001; // Multiply and Subtract
1781 // Extra precision multiplies with low / high results
1782 let neverHasSideEffects = 1 in {
1783 let isCommutable = 1 in {
1784 def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1785 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1786 "smull", "\t$ldst, $hdst, $a, $b", []> {
1787 let Inst{31-27} = 0b11111;
1788 let Inst{26-23} = 0b0111;
1789 let Inst{22-20} = 0b000;
1790 let Inst{7-4} = 0b0000;
1793 def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1794 (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
1795 "umull", "\t$ldst, $hdst, $a, $b", []> {
1796 let Inst{31-27} = 0b11111;
1797 let Inst{26-23} = 0b0111;
1798 let Inst{22-20} = 0b010;
1799 let Inst{7-4} = 0b0000;
1803 // Multiply + accumulate
1804 def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1805 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1806 "smlal", "\t$ldst, $hdst, $a, $b", []>{
1807 let Inst{31-27} = 0b11111;
1808 let Inst{26-23} = 0b0111;
1809 let Inst{22-20} = 0b100;
1810 let Inst{7-4} = 0b0000;
1813 def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1814 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1815 "umlal", "\t$ldst, $hdst, $a, $b", []>{
1816 let Inst{31-27} = 0b11111;
1817 let Inst{26-23} = 0b0111;
1818 let Inst{22-20} = 0b110;
1819 let Inst{7-4} = 0b0000;
1822 def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst),
1823 (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
1824 "umaal", "\t$ldst, $hdst, $a, $b", []>{
1825 let Inst{31-27} = 0b11111;
1826 let Inst{26-23} = 0b0111;
1827 let Inst{22-20} = 0b110;
1828 let Inst{7-4} = 0b0110;
1830 } // neverHasSideEffects
1832 // Rounding variants of the below included for disassembly only
1834 // Most significant word multiply
1835 def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1836 "smmul", "\t$dst, $a, $b",
1837 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
1838 let Inst{31-27} = 0b11111;
1839 let Inst{26-23} = 0b0110;
1840 let Inst{22-20} = 0b101;
1841 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1842 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1845 def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1846 "smmulr", "\t$dst, $a, $b", []> {
1847 let Inst{31-27} = 0b11111;
1848 let Inst{26-23} = 0b0110;
1849 let Inst{22-20} = 0b101;
1850 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1851 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1854 def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1855 "smmla", "\t$dst, $a, $b, $c",
1856 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
1857 let Inst{31-27} = 0b11111;
1858 let Inst{26-23} = 0b0110;
1859 let Inst{22-20} = 0b101;
1860 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1861 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1864 def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1865 "smmlar", "\t$dst, $a, $b, $c", []> {
1866 let Inst{31-27} = 0b11111;
1867 let Inst{26-23} = 0b0110;
1868 let Inst{22-20} = 0b101;
1869 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1870 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1873 def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1874 "smmls", "\t$dst, $a, $b, $c",
1875 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
1876 let Inst{31-27} = 0b11111;
1877 let Inst{26-23} = 0b0110;
1878 let Inst{22-20} = 0b110;
1879 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1880 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
1883 def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
1884 "smmlsr", "\t$dst, $a, $b, $c", []> {
1885 let Inst{31-27} = 0b11111;
1886 let Inst{26-23} = 0b0110;
1887 let Inst{22-20} = 0b110;
1888 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1889 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
1892 multiclass T2I_smul<string opc, PatFrag opnode> {
1893 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1894 !strconcat(opc, "bb"), "\t$dst, $a, $b",
1895 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1896 (sext_inreg rGPR:$b, i16)))]> {
1897 let Inst{31-27} = 0b11111;
1898 let Inst{26-23} = 0b0110;
1899 let Inst{22-20} = 0b001;
1900 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1901 let Inst{7-6} = 0b00;
1902 let Inst{5-4} = 0b00;
1905 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1906 !strconcat(opc, "bt"), "\t$dst, $a, $b",
1907 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
1908 (sra rGPR:$b, (i32 16))))]> {
1909 let Inst{31-27} = 0b11111;
1910 let Inst{26-23} = 0b0110;
1911 let Inst{22-20} = 0b001;
1912 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1913 let Inst{7-6} = 0b00;
1914 let Inst{5-4} = 0b01;
1917 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1918 !strconcat(opc, "tb"), "\t$dst, $a, $b",
1919 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1920 (sext_inreg rGPR:$b, i16)))]> {
1921 let Inst{31-27} = 0b11111;
1922 let Inst{26-23} = 0b0110;
1923 let Inst{22-20} = 0b001;
1924 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1925 let Inst{7-6} = 0b00;
1926 let Inst{5-4} = 0b10;
1929 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
1930 !strconcat(opc, "tt"), "\t$dst, $a, $b",
1931 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
1932 (sra rGPR:$b, (i32 16))))]> {
1933 let Inst{31-27} = 0b11111;
1934 let Inst{26-23} = 0b0110;
1935 let Inst{22-20} = 0b001;
1936 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1937 let Inst{7-6} = 0b00;
1938 let Inst{5-4} = 0b11;
1941 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1942 !strconcat(opc, "wb"), "\t$dst, $a, $b",
1943 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1944 (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
1945 let Inst{31-27} = 0b11111;
1946 let Inst{26-23} = 0b0110;
1947 let Inst{22-20} = 0b011;
1948 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1949 let Inst{7-6} = 0b00;
1950 let Inst{5-4} = 0b00;
1953 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
1954 !strconcat(opc, "wt"), "\t$dst, $a, $b",
1955 [(set rGPR:$dst, (sra (opnode rGPR:$a,
1956 (sra rGPR:$b, (i32 16))), (i32 16)))]> {
1957 let Inst{31-27} = 0b11111;
1958 let Inst{26-23} = 0b0110;
1959 let Inst{22-20} = 0b011;
1960 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
1961 let Inst{7-6} = 0b00;
1962 let Inst{5-4} = 0b01;
1967 multiclass T2I_smla<string opc, PatFrag opnode> {
1968 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1969 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1970 [(set rGPR:$dst, (add rGPR:$acc,
1971 (opnode (sext_inreg rGPR:$a, i16),
1972 (sext_inreg rGPR:$b, i16))))]> {
1973 let Inst{31-27} = 0b11111;
1974 let Inst{26-23} = 0b0110;
1975 let Inst{22-20} = 0b001;
1976 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1977 let Inst{7-6} = 0b00;
1978 let Inst{5-4} = 0b00;
1981 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1982 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1983 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
1984 (sra rGPR:$b, (i32 16)))))]> {
1985 let Inst{31-27} = 0b11111;
1986 let Inst{26-23} = 0b0110;
1987 let Inst{22-20} = 0b001;
1988 let Inst{15-12} = {?, ?, ?, ?}; // Ra
1989 let Inst{7-6} = 0b00;
1990 let Inst{5-4} = 0b01;
1993 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
1994 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1995 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
1996 (sext_inreg rGPR:$b, i16))))]> {
1997 let Inst{31-27} = 0b11111;
1998 let Inst{26-23} = 0b0110;
1999 let Inst{22-20} = 0b001;
2000 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2001 let Inst{7-6} = 0b00;
2002 let Inst{5-4} = 0b10;
2005 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
2006 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
2007 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
2008 (sra rGPR:$b, (i32 16)))))]> {
2009 let Inst{31-27} = 0b11111;
2010 let Inst{26-23} = 0b0110;
2011 let Inst{22-20} = 0b001;
2012 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2013 let Inst{7-6} = 0b00;
2014 let Inst{5-4} = 0b11;
2017 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
2018 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
2019 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
2020 (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
2021 let Inst{31-27} = 0b11111;
2022 let Inst{26-23} = 0b0110;
2023 let Inst{22-20} = 0b011;
2024 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2025 let Inst{7-6} = 0b00;
2026 let Inst{5-4} = 0b00;
2029 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
2030 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
2031 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
2032 (sra rGPR:$b, (i32 16))), (i32 16))))]> {
2033 let Inst{31-27} = 0b11111;
2034 let Inst{26-23} = 0b0110;
2035 let Inst{22-20} = 0b011;
2036 let Inst{15-12} = {?, ?, ?, ?}; // Ra
2037 let Inst{7-6} = 0b00;
2038 let Inst{5-4} = 0b01;
2042 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2043 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2045 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2046 def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
2047 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2048 [/* For disassembly only; pattern left blank */]>;
2049 def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
2050 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2051 [/* For disassembly only; pattern left blank */]>;
2052 def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
2053 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2054 [/* For disassembly only; pattern left blank */]>;
2055 def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
2056 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2057 [/* For disassembly only; pattern left blank */]>;
2059 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2060 // These are for disassembly only.
2062 def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2063 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
2064 let Inst{15-12} = 0b1111;
2066 def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2067 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
2068 let Inst{15-12} = 0b1111;
2070 def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2071 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
2072 let Inst{15-12} = 0b1111;
2074 def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
2075 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
2076 let Inst{15-12} = 0b1111;
2078 def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
2079 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
2080 "\t$dst, $a, $b, $acc", []>;
2081 def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
2082 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
2083 "\t$dst, $a, $b, $acc", []>;
2084 def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
2085 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
2086 "\t$dst, $a, $b, $acc", []>;
2087 def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
2088 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
2089 "\t$dst, $a, $b, $acc", []>;
2090 def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2091 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
2092 "\t$ldst, $hdst, $a, $b", []>;
2093 def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2094 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
2095 "\t$ldst, $hdst, $a, $b", []>;
2096 def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
2097 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
2098 "\t$ldst, $hdst, $a, $b", []>;
2099 def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
2100 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
2101 "\t$ldst, $hdst, $a, $b", []>;
2103 //===----------------------------------------------------------------------===//
2104 // Misc. Arithmetic Instructions.
2107 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2108 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2109 : T2I<oops, iops, itin, opc, asm, pattern> {
2110 let Inst{31-27} = 0b11111;
2111 let Inst{26-22} = 0b01010;
2112 let Inst{21-20} = op1;
2113 let Inst{15-12} = 0b1111;
2114 let Inst{7-6} = 0b10;
2115 let Inst{5-4} = op2;
2118 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2119 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
2121 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2122 "rbit", "\t$dst, $src",
2123 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
2125 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2126 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
2128 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2129 "rev16", ".w\t$dst, $src",
2131 (or (and (srl rGPR:$src, (i32 8)), 0xFF),
2132 (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
2133 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
2134 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
2136 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
2137 "revsh", ".w\t$dst, $src",
2140 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
2141 (shl rGPR:$src, (i32 8))), i16))]>;
2143 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2144 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
2145 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2146 (and (shl rGPR:$src2, lsl_amt:$sh),
2148 Requires<[HasT2ExtractPack]> {
2149 let Inst{31-27} = 0b11101;
2150 let Inst{26-25} = 0b01;
2151 let Inst{24-20} = 0b01100;
2152 let Inst{5} = 0; // BT form
2156 // Alternate cases for PKHBT where identities eliminate some nodes.
2157 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2158 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2159 Requires<[HasT2ExtractPack]>;
2160 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2161 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2162 Requires<[HasT2ExtractPack]>;
2164 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2165 // will match the pattern below.
2166 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2167 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
2168 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2169 (and (sra rGPR:$src2, asr_amt:$sh),
2171 Requires<[HasT2ExtractPack]> {
2172 let Inst{31-27} = 0b11101;
2173 let Inst{26-25} = 0b01;
2174 let Inst{24-20} = 0b01100;
2175 let Inst{5} = 1; // TB form
2179 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2180 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2181 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2182 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2183 Requires<[HasT2ExtractPack]>;
2184 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2185 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2186 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2187 Requires<[HasT2ExtractPack]>;
2189 //===----------------------------------------------------------------------===//
2190 // Comparison Instructions...
2192 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2193 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2194 defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2195 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2197 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2198 // Compare-to-zero still works out, just not the relationals
2199 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2200 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2201 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2202 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2204 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2205 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2207 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2208 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2210 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2211 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
2212 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2213 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
2215 // Conditional moves
2216 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2217 // a two-value operand where a dag node expects two operands. :(
2218 let neverHasSideEffects = 1 in {
2219 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
2220 "mov", ".w\t$dst, $true",
2221 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
2222 RegConstraint<"$false = $dst"> {
2223 let Inst{31-27} = 0b11101;
2224 let Inst{26-25} = 0b01;
2225 let Inst{24-21} = 0b0010;
2226 let Inst{20} = 0; // The S bit.
2227 let Inst{19-16} = 0b1111; // Rn
2228 let Inst{14-12} = 0b000;
2229 let Inst{7-4} = 0b0000;
2232 def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
2233 IIC_iCMOVi, "mov", ".w\t$dst, $true",
2234 [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2235 RegConstraint<"$false = $dst"> {
2236 let Inst{31-27} = 0b11110;
2238 let Inst{24-21} = 0b0010;
2239 let Inst{20} = 0; // The S bit.
2240 let Inst{19-16} = 0b1111; // Rn
2244 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2245 string opc, string asm, list<dag> pattern>
2246 : T2I<oops, iops, itin, opc, asm, pattern> {
2247 let Inst{31-27} = 0b11101;
2248 let Inst{26-25} = 0b01;
2249 let Inst{24-21} = 0b0010;
2250 let Inst{20} = 0; // The S bit.
2251 let Inst{19-16} = 0b1111; // Rn
2252 let Inst{5-4} = opcod; // Shift type.
2254 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
2255 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2256 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
2257 RegConstraint<"$false = $dst">;
2258 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
2259 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2260 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
2261 RegConstraint<"$false = $dst">;
2262 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
2263 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2264 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
2265 RegConstraint<"$false = $dst">;
2266 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
2267 (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
2268 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
2269 RegConstraint<"$false = $dst">;
2270 } // neverHasSideEffects
2272 //===----------------------------------------------------------------------===//
2273 // Atomic operations intrinsics
2276 // memory barriers protect the atomic sequences
2277 let hasSideEffects = 1 in {
2278 def t2DMBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dmb", "",
2279 [(ARMMemBarrier)]>, Requires<[IsThumb, HasDB]> {
2280 let Inst{31-4} = 0xF3BF8F5;
2281 // FIXME: add support for options other than a full system DMB
2282 let Inst{3-0} = 0b1111;
2285 def t2DSBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dsb", "",
2286 [(ARMSyncBarrier)]>, Requires<[IsThumb, HasDB]> {
2287 let Inst{31-4} = 0xF3BF8F4;
2288 // FIXME: add support for options other than a full system DSB
2289 let Inst{3-0} = 0b1111;
2293 // Helper class for multiclass T2MemB -- for disassembly only
2294 class T2I_memb<string opc, string asm>
2295 : T2I<(outs), (ins), NoItinerary, opc, asm,
2296 [/* For disassembly only; pattern left blank */]>,
2297 Requires<[IsThumb2, HasV7]> {
2298 let Inst{31-20} = 0xf3b;
2299 let Inst{15-14} = 0b10;
2303 multiclass T2MemB<bits<4> op7_4, string opc> {
2305 def st : T2I_memb<opc, "\tst"> {
2306 let Inst{7-4} = op7_4;
2307 let Inst{3-0} = 0b1110;
2310 def ish : T2I_memb<opc, "\tish"> {
2311 let Inst{7-4} = op7_4;
2312 let Inst{3-0} = 0b1011;
2315 def ishst : T2I_memb<opc, "\tishst"> {
2316 let Inst{7-4} = op7_4;
2317 let Inst{3-0} = 0b1010;
2320 def nsh : T2I_memb<opc, "\tnsh"> {
2321 let Inst{7-4} = op7_4;
2322 let Inst{3-0} = 0b0111;
2325 def nshst : T2I_memb<opc, "\tnshst"> {
2326 let Inst{7-4} = op7_4;
2327 let Inst{3-0} = 0b0110;
2330 def osh : T2I_memb<opc, "\tosh"> {
2331 let Inst{7-4} = op7_4;
2332 let Inst{3-0} = 0b0011;
2335 def oshst : T2I_memb<opc, "\toshst"> {
2336 let Inst{7-4} = op7_4;
2337 let Inst{3-0} = 0b0010;
2341 // These DMB variants are for disassembly only.
2342 defm t2DMB : T2MemB<0b0101, "dmb">;
2344 // These DSB variants are for disassembly only.
2345 defm t2DSB : T2MemB<0b0100, "dsb">;
2347 // ISB has only full system option -- for disassembly only
2348 def t2ISBsy : T2I_memb<"isb", ""> {
2349 let Inst{7-4} = 0b0110;
2350 let Inst{3-0} = 0b1111;
2353 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2354 InstrItinClass itin, string opc, string asm, string cstr,
2355 list<dag> pattern, bits<4> rt2 = 0b1111>
2356 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2357 let Inst{31-27} = 0b11101;
2358 let Inst{26-20} = 0b0001101;
2359 let Inst{11-8} = rt2;
2360 let Inst{7-6} = 0b01;
2361 let Inst{5-4} = opcod;
2362 let Inst{3-0} = 0b1111;
2364 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2365 InstrItinClass itin, string opc, string asm, string cstr,
2366 list<dag> pattern, bits<4> rt2 = 0b1111>
2367 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2368 let Inst{31-27} = 0b11101;
2369 let Inst{26-20} = 0b0001100;
2370 let Inst{11-8} = rt2;
2371 let Inst{7-6} = 0b01;
2372 let Inst{5-4} = opcod;
2375 let mayLoad = 1 in {
2376 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2377 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
2379 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2380 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
2382 def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
2383 Size4Bytes, NoItinerary,
2384 "ldrex", "\t$dest, [$ptr]", "",
2386 let Inst{31-27} = 0b11101;
2387 let Inst{26-20} = 0b0000101;
2388 let Inst{11-8} = 0b1111;
2389 let Inst{7-0} = 0b00000000; // imm8 = 0
2391 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
2392 AddrModeNone, Size4Bytes, NoItinerary,
2393 "ldrexd", "\t$dest, $dest2, [$ptr]", "",
2397 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2398 def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2399 AddrModeNone, Size4Bytes, NoItinerary,
2400 "strexb", "\t$success, $src, [$ptr]", "", []>;
2401 def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2402 AddrModeNone, Size4Bytes, NoItinerary,
2403 "strexh", "\t$success, $src, [$ptr]", "", []>;
2404 def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
2405 AddrModeNone, Size4Bytes, NoItinerary,
2406 "strex", "\t$success, $src, [$ptr]", "",
2408 let Inst{31-27} = 0b11101;
2409 let Inst{26-20} = 0b0000100;
2410 let Inst{7-0} = 0b00000000; // imm8 = 0
2412 def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
2413 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
2414 AddrModeNone, Size4Bytes, NoItinerary,
2415 "strexd", "\t$success, $src, $src2, [$ptr]", "", [],
2419 // Clear-Exclusive is for disassembly only.
2420 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2421 [/* For disassembly only; pattern left blank */]>,
2422 Requires<[IsARM, HasV7]> {
2423 let Inst{31-20} = 0xf3b;
2424 let Inst{15-14} = 0b10;
2426 let Inst{7-4} = 0b0010;
2429 //===----------------------------------------------------------------------===//
2433 // __aeabi_read_tp preserves the registers r1-r3.
2435 Defs = [R0, R12, LR, CPSR] in {
2436 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2437 "bl\t__aeabi_read_tp",
2438 [(set R0, ARMthread_pointer)]> {
2439 let Inst{31-27} = 0b11110;
2440 let Inst{15-14} = 0b11;
2445 //===----------------------------------------------------------------------===//
2446 // SJLJ Exception handling intrinsics
2447 // eh_sjlj_setjmp() is an instruction sequence to store the return
2448 // address and save #0 in R0 for the non-longjmp case.
2449 // Since by its nature we may be coming from some other function to get
2450 // here, and we're using the stack frame for the containing function to
2451 // save/restore registers, we can't keep anything live in regs across
2452 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2453 // when we get here from a longjmp(). We force everthing out of registers
2454 // except for our own input by listing the relevant registers in Defs. By
2455 // doing so, we also cause the prologue/epilogue code to actively preserve
2456 // all of the callee-saved resgisters, which is exactly what we want.
2457 // $val is a scratch register for our use.
2459 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2460 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2461 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2462 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2463 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2464 AddrModeNone, SizeSpecial, NoItinerary,
2465 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2466 "adds\t$val, #7\n\t"
2467 "str\t$val, [$src, #4]\n\t"
2470 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2472 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2473 Requires<[IsThumb2, HasVFP2]>;
2477 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2478 hasSideEffects = 1, isBarrier = 1 in {
2479 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2480 AddrModeNone, SizeSpecial, NoItinerary,
2481 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
2482 "adds\t$val, #7\n\t"
2483 "str\t$val, [$src, #4]\n\t"
2486 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
2488 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2489 Requires<[IsThumb2, NoVFP]>;
2493 //===----------------------------------------------------------------------===//
2494 // Control-Flow Instructions
2497 // FIXME: remove when we have a way to marking a MI with these properties.
2498 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2500 // FIXME: Should pc be an implicit operand like PICADD, etc?
2501 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2502 hasExtraDefRegAllocReq = 1 in
2503 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
2504 reglist:$dsts, variable_ops), IIC_Br,
2505 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
2506 "$addr.addr = $wb", []> {
2507 let Inst{31-27} = 0b11101;
2508 let Inst{26-25} = 0b00;
2509 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
2511 let Inst{21} = 1; // The W bit.
2512 let Inst{20} = 1; // Load
2515 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2516 let isPredicable = 1 in
2517 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2519 [(br bb:$target)]> {
2520 let Inst{31-27} = 0b11110;
2521 let Inst{15-14} = 0b10;
2525 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2528 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
2529 IIC_Br, "mov\tpc, $target$jt",
2530 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
2531 let Inst{31-27} = 0b11101;
2532 let Inst{26-20} = 0b0100100;
2533 let Inst{19-16} = 0b1111;
2534 let Inst{14-12} = 0b000;
2535 let Inst{11-8} = 0b1111; // Rd = pc
2536 let Inst{7-4} = 0b0000;
2539 // FIXME: Add a non-pc based case that can be predicated.
2542 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2543 IIC_Br, "tbb\t$index$jt", []> {
2544 let Inst{31-27} = 0b11101;
2545 let Inst{26-20} = 0b0001101;
2546 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2547 let Inst{15-8} = 0b11110000;
2548 let Inst{7-4} = 0b0000; // B form
2553 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
2554 IIC_Br, "tbh\t$index$jt", []> {
2555 let Inst{31-27} = 0b11101;
2556 let Inst{26-20} = 0b0001101;
2557 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
2558 let Inst{15-8} = 0b11110000;
2559 let Inst{7-4} = 0b0001; // H form
2562 // Generic versions of the above two instructions, for disassembly only
2564 def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2565 "tbb", "\t[$a, $b]", []>{
2566 let Inst{31-27} = 0b11101;
2567 let Inst{26-20} = 0b0001101;
2568 let Inst{15-8} = 0b11110000;
2569 let Inst{7-4} = 0b0000; // B form
2572 def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
2573 "tbh", "\t[$a, $b, lsl #1]", []> {
2574 let Inst{31-27} = 0b11101;
2575 let Inst{26-20} = 0b0001101;
2576 let Inst{15-8} = 0b11110000;
2577 let Inst{7-4} = 0b0001; // H form
2579 } // isNotDuplicable, isIndirectBranch
2581 } // isBranch, isTerminator, isBarrier
2583 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2584 // a two-value operand where a dag node expects two operands. :(
2585 let isBranch = 1, isTerminator = 1 in
2586 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2588 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2589 let Inst{31-27} = 0b11110;
2590 let Inst{15-14} = 0b10;
2596 let Defs = [ITSTATE] in
2597 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
2598 AddrModeNone, Size2Bytes, IIC_iALUx,
2599 "it$mask\t$cc", "", []> {
2600 // 16-bit instruction.
2601 let Inst{31-16} = 0x0000;
2602 let Inst{15-8} = 0b10111111;
2605 // Branch and Exchange Jazelle -- for disassembly only
2607 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
2608 [/* For disassembly only; pattern left blank */]> {
2609 let Inst{31-27} = 0b11110;
2611 let Inst{25-20} = 0b111100;
2612 let Inst{15-14} = 0b10;
2616 // Change Processor State is a system instruction -- for disassembly only.
2617 // The singleton $opt operand contains the following information:
2618 // opt{4-0} = mode from Inst{4-0}
2619 // opt{5} = changemode from Inst{17}
2620 // opt{8-6} = AIF from Inst{8-6}
2621 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2622 def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
2623 [/* For disassembly only; pattern left blank */]> {
2624 let Inst{31-27} = 0b11110;
2626 let Inst{25-20} = 0b111010;
2627 let Inst{15-14} = 0b10;
2631 // A6.3.4 Branches and miscellaneous control
2632 // Table A6-14 Change Processor State, and hint instructions
2633 // Helper class for disassembly only.
2634 class T2I_hint<bits<8> op7_0, string opc, string asm>
2635 : T2I<(outs), (ins), NoItinerary, opc, asm,
2636 [/* For disassembly only; pattern left blank */]> {
2637 let Inst{31-20} = 0xf3a;
2638 let Inst{15-14} = 0b10;
2640 let Inst{10-8} = 0b000;
2641 let Inst{7-0} = op7_0;
2644 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
2645 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
2646 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
2647 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
2648 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
2650 def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
2651 [/* For disassembly only; pattern left blank */]> {
2652 let Inst{31-20} = 0xf3a;
2653 let Inst{15-14} = 0b10;
2655 let Inst{10-8} = 0b000;
2656 let Inst{7-4} = 0b1111;
2659 // Secure Monitor Call is a system instruction -- for disassembly only
2660 // Option = Inst{19-16}
2661 def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
2662 [/* For disassembly only; pattern left blank */]> {
2663 let Inst{31-27} = 0b11110;
2664 let Inst{26-20} = 0b1111111;
2665 let Inst{15-12} = 0b1000;
2668 // Store Return State is a system instruction -- for disassembly only
2669 def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
2670 [/* For disassembly only; pattern left blank */]> {
2671 let Inst{31-27} = 0b11101;
2672 let Inst{26-20} = 0b0000010; // W = 1
2675 def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
2676 [/* For disassembly only; pattern left blank */]> {
2677 let Inst{31-27} = 0b11101;
2678 let Inst{26-20} = 0b0000000; // W = 0
2681 def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
2682 [/* For disassembly only; pattern left blank */]> {
2683 let Inst{31-27} = 0b11101;
2684 let Inst{26-20} = 0b0011010; // W = 1
2687 def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
2688 [/* For disassembly only; pattern left blank */]> {
2689 let Inst{31-27} = 0b11101;
2690 let Inst{26-20} = 0b0011000; // W = 0
2693 // Return From Exception is a system instruction -- for disassembly only
2694 def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
2695 [/* For disassembly only; pattern left blank */]> {
2696 let Inst{31-27} = 0b11101;
2697 let Inst{26-20} = 0b0000011; // W = 1
2700 def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
2701 [/* For disassembly only; pattern left blank */]> {
2702 let Inst{31-27} = 0b11101;
2703 let Inst{26-20} = 0b0000001; // W = 0
2706 def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
2707 [/* For disassembly only; pattern left blank */]> {
2708 let Inst{31-27} = 0b11101;
2709 let Inst{26-20} = 0b0011011; // W = 1
2712 def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
2713 [/* For disassembly only; pattern left blank */]> {
2714 let Inst{31-27} = 0b11101;
2715 let Inst{26-20} = 0b0011001; // W = 0
2718 //===----------------------------------------------------------------------===//
2719 // Non-Instruction Patterns
2722 // Two piece so_imms.
2723 def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
2724 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2725 (t2_so_imm2part_2 imm:$RHS))>;
2726 def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
2727 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2728 (t2_so_imm2part_2 imm:$RHS))>;
2729 def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
2730 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
2731 (t2_so_imm2part_2 imm:$RHS))>;
2732 def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
2733 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
2734 (t2_so_neg_imm2part_2 imm:$RHS))>;
2736 // 32-bit immediate using movw + movt.
2737 // This is a single pseudo instruction to make it re-materializable. Remove
2738 // when we can do generalized remat.
2739 let isReMaterializable = 1 in
2740 def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
2741 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2742 [(set rGPR:$dst, (i32 imm:$src))]>;
2744 // ConstantPool, GlobalAddress, and JumpTable
2745 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
2746 Requires<[IsThumb2, DontUseMovt]>;
2747 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
2748 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
2749 Requires<[IsThumb2, UseMovt]>;
2751 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2752 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
2754 // Pseudo instruction that combines ldr from constpool and add pc. This should
2755 // be expanded into two instructions late to allow if-conversion and
2757 let canFoldAsLoad = 1, isReMaterializable = 1 in
2758 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
2760 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
2761 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
2763 Requires<[IsThumb2]>;
2765 //===----------------------------------------------------------------------===//
2766 // Move between special register and ARM core register -- for disassembly only
2770 def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
2771 [/* For disassembly only; pattern left blank */]> {
2772 let Inst{31-27} = 0b11110;
2774 let Inst{25-21} = 0b11111;
2775 let Inst{20} = 0; // The R bit.
2776 let Inst{15-14} = 0b10;
2781 def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
2782 [/* For disassembly only; pattern left blank */]> {
2783 let Inst{31-27} = 0b11110;
2785 let Inst{25-21} = 0b11111;
2786 let Inst{20} = 1; // The R bit.
2787 let Inst{15-14} = 0b10;
2792 def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2793 "\tcpsr$mask, $src",
2794 [/* For disassembly only; pattern left blank */]> {
2795 let Inst{31-27} = 0b11110;
2797 let Inst{25-21} = 0b11100;
2798 let Inst{20} = 0; // The R bit.
2799 let Inst{15-14} = 0b10;
2804 def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
2805 "\tspsr$mask, $src",
2806 [/* For disassembly only; pattern left blank */]> {
2807 let Inst{31-27} = 0b11110;
2809 let Inst{25-21} = 0b11100;
2810 let Inst{20} = 1; // The R bit.
2811 let Inst{15-14} = 0b10;