1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",
19 let PrintMethod = "printSOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
129 //===----------------------------------------------------------------------===//
130 // Thumb2 to cover the functionality of the ARM instruction set.
133 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
134 // unary operation that produces a value.
135 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
137 def i : T2I<(outs GPR:$dst), (ins t2_so_imm:$src),
138 !strconcat(opc, " $dst, $src"),
139 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
140 let isAsCheapAsAMove = Cheap;
141 let isReMaterializable = ReMat;
144 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
145 !strconcat(opc, " $dst, $src"),
146 [(set GPR:$dst, (opnode GPR:$src))]>;
148 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
149 !strconcat(opc, " $dst, $src"),
150 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
153 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
154 // binary operation that produces a value.
155 multiclass T2I_bin_irs<string opc, PatFrag opnode> {
157 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
158 !strconcat(opc, " $dst, $lhs, $rhs"),
159 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
161 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
162 !strconcat(opc, " $dst, $lhs, $rhs"),
163 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
165 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
166 !strconcat(opc, " $dst, $lhs, $rhs"),
167 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
170 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are reversed.
171 multiclass T2I_rbin_irs<string opc, PatFrag opnode> {
173 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
174 !strconcat(opc, " $dst, $rhs, $lhs"),
175 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
177 def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
178 !strconcat(opc, " $dst, $rhs, $lhs"),
179 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
181 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
182 !strconcat(opc, " $dst, $rhs, $lhs"),
183 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
186 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
187 /// instruction modifies the CPSR register.
188 let Defs = [CPSR] in {
189 multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
191 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
192 !strconcat(opc, "s $dst, $lhs, $rhs"),
193 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
195 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
196 !strconcat(opc, " $dst, $lhs, $rhs"),
197 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
199 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
200 !strconcat(opc, "s $dst, $lhs, $rhs"),
201 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
205 /// T2I_rbin_s_irs - Same as T2I_bin_s_irs except the order of operands are
207 let Defs = [CPSR] in {
208 multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> {
210 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
211 !strconcat(opc, "s $dst, $rhs, $lhs"),
212 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
214 def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
215 !strconcat(opc, " $dst, $rhs, $lhs"),
216 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
218 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
219 !strconcat(opc, "s $dst, $rhs, $lhs"),
220 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
224 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
225 /// patterns for a binary operation that produces a value.
226 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
228 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
229 !strconcat(opc, " $dst, $lhs, $rhs"),
230 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
232 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
233 !strconcat(opc, "w $dst, $lhs, $rhs"),
234 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
236 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
237 !strconcat(opc, " $dst, $lhs, $rhs"),
238 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
240 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
241 !strconcat(opc, " $dst, $lhs, $rhs"),
242 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
245 /// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
246 // binary operation that produces a value and set the carry bit. It can also
247 /// optionally set CPSR.
248 let Uses = [CPSR] in {
249 multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
251 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
252 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
253 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
255 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
256 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
257 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
259 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
260 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
261 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
265 /// T2I_rbin_c_irs - Same as T2I_bin_c_irs except the order of operands are
267 let Uses = [CPSR] in {
268 multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> {
270 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
271 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
272 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
274 def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s),
275 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
276 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
278 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
279 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
280 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
284 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
285 // rotate operation that produces a value.
286 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
288 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
289 !strconcat(opc, " $dst, $lhs, $rhs"),
290 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
292 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
293 !strconcat(opc, " $dst, $lhs, $rhs"),
294 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
297 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
298 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
299 /// a explicit result, only implicitly set CPSR.
300 let Uses = [CPSR] in {
301 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
303 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
304 !strconcat(opc, " $lhs, $rhs"),
305 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
307 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
308 !strconcat(opc, " $lhs, $rhs"),
309 [(opnode GPR:$lhs, GPR:$rhs)]>;
311 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
312 !strconcat(opc, " $lhs, $rhs"),
313 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
317 //===----------------------------------------------------------------------===//
318 // Miscellaneous Instructions.
321 let isNotDuplicable = 1 in
322 def t2PICADD : T2I<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
323 "$cp:\n\tadd $dst, pc",
324 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
327 // LEApcrel - Load a pc-relative address into a register without offending the
329 def t2LEApcrel : T2I<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
330 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
331 "${:private}PCRELL${:uid}+8))\n"),
332 !strconcat("${:private}PCRELL${:uid}:\n\t",
333 "add$p $dst, pc, #PCRELV${:uid}")),
336 def t2LEApcrelJT : T2I<(outs GPR:$dst),
337 (ins i32imm:$label, i32imm:$id, pred:$p),
338 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
339 "${:private}PCRELL${:uid}+8))\n"),
340 !strconcat("${:private}PCRELL${:uid}:\n\t",
341 "add$p $dst, pc, #PCRELV${:uid}")),
344 //===----------------------------------------------------------------------===//
345 // Arithmetic Instructions.
348 //===----------------------------------------------------------------------===//
349 // Move Instructions.
352 let neverHasSideEffects = 1 in
353 def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src),
354 "mov $dst, $src", []>;
356 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
357 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
359 [(set GPR:$dst, imm0_65535:$src)]>;
361 // FIXME: Also available in ARM mode.
362 let Constraints = "$src = $dst" in
363 def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
366 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
368 //===----------------------------------------------------------------------===//
369 // Arithmetic Instructions.
372 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
373 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
375 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
376 defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
377 defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
379 // FIXME: predication support
380 defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
381 defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
384 defm t2RSB : T2I_rbin_irs <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
385 defm t2RSBS : T2I_rbin_c_irs<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
386 defm t2RSC : T2I_rbin_s_irs<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
388 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
389 def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
390 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
391 def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
392 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
395 //===----------------------------------------------------------------------===//
396 // Shift and rotate Instructions.
399 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
400 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
401 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
402 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
404 def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src),
405 "mov $dst, $src, rrx",
406 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
408 //===----------------------------------------------------------------------===//
409 // Bitwise Instructions.
412 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
413 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
414 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
416 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
418 def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
419 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
421 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
423 def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
424 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
426 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
428 // A8.6.17 BFC - Bitfield clear
429 // FIXME: Also available in ARM mode.
430 let Constraints = "$src = $dst" in
431 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
433 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
435 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
437 //===----------------------------------------------------------------------===//
438 // Multiply Instructions.
440 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
442 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
444 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
445 "mla $dst, $a, $b, $c",
446 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
448 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
449 "mls $dst, $a, $b, $c",
450 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
452 // FIXME: SMULL, etc.
454 //===----------------------------------------------------------------------===//
455 // Misc. Arithmetic Instructions.
461 // FIXME not firing? but ARM version does...
462 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
464 [(set GPR:$dst, (ctlz GPR:$src))]>;
466 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
468 [(set GPR:$dst, (bswap GPR:$src))]>;
470 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
473 (or (and (srl GPR:$src, (i32 8)), 0xFF),
474 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
475 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
476 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
481 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
485 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
486 (shl GPR:$src, (i32 8))), i16))]>;
490 //===----------------------------------------------------------------------===//
491 // Comparison Instructions...
494 defm t2CMP : T2I_cmp_is<"cmp",
495 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
496 defm t2CMPnz : T2I_cmp_is<"cmp",
497 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
499 defm t2CMN : T2I_cmp_is<"cmn",
500 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
501 defm t2CMNnz : T2I_cmp_is<"cmn",
502 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
504 def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
505 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
507 def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
508 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
510 // FIXME: TST, TEQ, etc.
512 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
513 // Short range conditional branch. Looks awesome for loops. Need to figure
514 // out how to use this one.
516 // FIXME: Conditional moves
519 //===----------------------------------------------------------------------===//
520 // Non-Instruction Patterns
523 // ConstantPool, GlobalAddress, and JumpTable
524 def : Thumb2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
525 def : Thumb2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
526 def : Thumb2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
527 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
529 // Large immediate handling.
531 def : Thumb2Pat<(i32 imm:$src),
532 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
533 (t2_hi16 imm:$src))>;