1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
22 let DecoderMethod = "DecodeITCond";
25 // IT block condition mask
26 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
27 def it_mask : Operand<i32> {
28 let PrintMethod = "printThumbITMask";
29 let ParserMatchClass = it_mask_asmoperand;
30 let DecoderMethod = "DecodeITMask";
33 // Shifted operands. No register controlled shifts for Thumb2.
34 // Note: We do not support rrx shifted operands yet.
35 def t2_so_reg : Operand<i32>, // reg imm
36 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
38 let EncoderMethod = "getT2SORegOpValue";
39 let PrintMethod = "printT2SOOperand";
40 let MIOperandInfo = (ops rGPR, i32imm);
41 let DecoderMethod = "DecodeSORegImmOperand";
44 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
45 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
46 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
49 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
50 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
51 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
54 // t2_so_imm - Match a 32-bit immediate operand, which is an
55 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
56 // immediate splatted into multiple bytes of the word.
57 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
58 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
59 return ARM_AM::getT2SOImmVal(Imm) != -1;
61 let ParserMatchClass = t2_so_imm_asmoperand;
62 let EncoderMethod = "getT2SOImmOpValue";
63 let DecoderMethod = "DecodeT2SOImm";
66 // t2_so_imm_not - Match an immediate that is a complement
68 def t2_so_imm_not : Operand<i32>,
70 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
71 }], t2_so_imm_not_XFORM>;
73 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
74 def t2_so_imm_neg : Operand<i32>,
76 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
77 }], t2_so_imm_neg_XFORM>;
79 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
80 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{
81 return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
84 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
85 def imm0_4095 : Operand<i32>,
87 return Imm >= 0 && Imm < 4096;
90 def imm0_4095_neg : PatLeaf<(i32 imm), [{
91 return (uint32_t)(-N->getZExtValue()) < 4096;
94 def imm0_255_neg : PatLeaf<(i32 imm), [{
95 return (uint32_t)(-N->getZExtValue()) < 255;
98 def imm0_255_not : PatLeaf<(i32 imm), [{
99 return (uint32_t)(~N->getZExtValue()) < 255;
102 def lo5AllOne : PatLeaf<(i32 imm), [{
103 // Returns true if all low 5-bits are 1.
104 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
107 // Define Thumb2 specific addressing modes.
109 // t2addrmode_imm12 := reg + imm12
110 def t2addrmode_imm12 : Operand<i32>,
111 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
112 let PrintMethod = "printAddrModeImm12Operand";
113 let EncoderMethod = "getAddrModeImm12OpValue";
114 let DecoderMethod = "DecodeT2AddrModeImm12";
115 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
118 // t2ldrlabel := imm12
119 def t2ldrlabel : Operand<i32> {
120 let EncoderMethod = "getAddrModeImm12OpValue";
124 // ADR instruction labels.
125 def t2adrlabel : Operand<i32> {
126 let EncoderMethod = "getT2AdrLabelOpValue";
130 // t2addrmode_imm8 := reg +/- imm8
131 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
132 def t2addrmode_imm8 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
134 let PrintMethod = "printT2AddrModeImm8Operand";
135 let EncoderMethod = "getT2AddrModeImm8OpValue";
136 let DecoderMethod = "DecodeT2AddrModeImm8";
137 let ParserMatchClass = MemImm8OffsetAsmOperand;
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 def t2am_imm8_offset : Operand<i32>,
142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
143 [], [SDNPWantRoot]> {
144 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
145 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
146 let DecoderMethod = "DecodeT2Imm8";
149 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
150 def t2addrmode_imm8s4 : Operand<i32> {
151 let PrintMethod = "printT2AddrModeImm8s4Operand";
152 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
153 let DecoderMethod = "DecodeT2AddrModeImm8s4";
154 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 def t2am_imm8s4_offset : Operand<i32> {
158 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
159 let DecoderMethod = "DecodeT2Imm8S4";
162 // t2addrmode_so_reg := reg + (reg << imm2)
163 def t2addrmode_so_reg : Operand<i32>,
164 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
165 let PrintMethod = "printT2AddrModeSoRegOperand";
166 let EncoderMethod = "getT2AddrModeSORegOpValue";
167 let DecoderMethod = "DecodeT2AddrModeSOReg";
168 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
171 // t2addrmode_reg := reg
172 // Used by load/store exclusive instructions. Useful to enable right assembly
173 // parsing and printing. Not used for any codegen matching.
175 def t2addrmode_reg : Operand<i32> {
176 let PrintMethod = "printAddrMode7Operand";
177 let DecoderMethod = "DecodeGPRRegisterClass";
178 let MIOperandInfo = (ops GPR);
181 //===----------------------------------------------------------------------===//
182 // Multiclass helpers...
186 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
187 string opc, string asm, list<dag> pattern>
188 : T2I<oops, iops, itin, opc, asm, pattern> {
193 let Inst{26} = imm{11};
194 let Inst{14-12} = imm{10-8};
195 let Inst{7-0} = imm{7-0};
199 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
200 string opc, string asm, list<dag> pattern>
201 : T2sI<oops, iops, itin, opc, asm, pattern> {
207 let Inst{26} = imm{11};
208 let Inst{14-12} = imm{10-8};
209 let Inst{7-0} = imm{7-0};
212 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
213 string opc, string asm, list<dag> pattern>
214 : T2I<oops, iops, itin, opc, asm, pattern> {
218 let Inst{19-16} = Rn;
219 let Inst{26} = imm{11};
220 let Inst{14-12} = imm{10-8};
221 let Inst{7-0} = imm{7-0};
225 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
226 string opc, string asm, list<dag> pattern>
227 : T2I<oops, iops, itin, opc, asm, pattern> {
232 let Inst{3-0} = ShiftedRm{3-0};
233 let Inst{5-4} = ShiftedRm{6-5};
234 let Inst{14-12} = ShiftedRm{11-9};
235 let Inst{7-6} = ShiftedRm{8-7};
238 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
239 string opc, string asm, list<dag> pattern>
240 : T2sI<oops, iops, itin, opc, asm, pattern> {
245 let Inst{3-0} = ShiftedRm{3-0};
246 let Inst{5-4} = ShiftedRm{6-5};
247 let Inst{14-12} = ShiftedRm{11-9};
248 let Inst{7-6} = ShiftedRm{8-7};
251 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
252 string opc, string asm, list<dag> pattern>
253 : T2I<oops, iops, itin, opc, asm, pattern> {
257 let Inst{19-16} = Rn;
258 let Inst{3-0} = ShiftedRm{3-0};
259 let Inst{5-4} = ShiftedRm{6-5};
260 let Inst{14-12} = ShiftedRm{11-9};
261 let Inst{7-6} = ShiftedRm{8-7};
264 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : T2I<oops, iops, itin, opc, asm, pattern> {
274 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
275 string opc, string asm, list<dag> pattern>
276 : T2sI<oops, iops, itin, opc, asm, pattern> {
284 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
285 string opc, string asm, list<dag> pattern>
286 : T2I<oops, iops, itin, opc, asm, pattern> {
290 let Inst{19-16} = Rn;
295 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
296 string opc, string asm, list<dag> pattern>
297 : T2I<oops, iops, itin, opc, asm, pattern> {
303 let Inst{19-16} = Rn;
304 let Inst{26} = imm{11};
305 let Inst{14-12} = imm{10-8};
306 let Inst{7-0} = imm{7-0};
309 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
310 string opc, string asm, list<dag> pattern>
311 : T2sI<oops, iops, itin, opc, asm, pattern> {
317 let Inst{19-16} = Rn;
318 let Inst{26} = imm{11};
319 let Inst{14-12} = imm{10-8};
320 let Inst{7-0} = imm{7-0};
323 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : T2I<oops, iops, itin, opc, asm, pattern> {
332 let Inst{14-12} = imm{4-2};
333 let Inst{7-6} = imm{1-0};
336 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : T2sI<oops, iops, itin, opc, asm, pattern> {
345 let Inst{14-12} = imm{4-2};
346 let Inst{7-6} = imm{1-0};
349 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2I<oops, iops, itin, opc, asm, pattern> {
357 let Inst{19-16} = Rn;
361 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
362 string opc, string asm, list<dag> pattern>
363 : T2sI<oops, iops, itin, opc, asm, pattern> {
369 let Inst{19-16} = Rn;
373 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
374 string opc, string asm, list<dag> pattern>
375 : T2I<oops, iops, itin, opc, asm, pattern> {
381 let Inst{19-16} = Rn;
382 let Inst{3-0} = ShiftedRm{3-0};
383 let Inst{5-4} = ShiftedRm{6-5};
384 let Inst{14-12} = ShiftedRm{11-9};
385 let Inst{7-6} = ShiftedRm{8-7};
388 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2sI<oops, iops, itin, opc, asm, pattern> {
396 let Inst{19-16} = Rn;
397 let Inst{3-0} = ShiftedRm{3-0};
398 let Inst{5-4} = ShiftedRm{6-5};
399 let Inst{14-12} = ShiftedRm{11-9};
400 let Inst{7-6} = ShiftedRm{8-7};
403 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
404 string opc, string asm, list<dag> pattern>
405 : T2I<oops, iops, itin, opc, asm, pattern> {
411 let Inst{19-16} = Rn;
412 let Inst{15-12} = Ra;
417 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
418 dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : T2I<oops, iops, itin, opc, asm, pattern> {
426 let Inst{31-23} = 0b111110111;
427 let Inst{22-20} = opc22_20;
428 let Inst{19-16} = Rn;
429 let Inst{15-12} = RdLo;
430 let Inst{11-8} = RdHi;
431 let Inst{7-4} = opc7_4;
436 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
437 /// unary operation that produces a value. These are predicable and can be
438 /// changed to modify CPSR.
439 multiclass T2I_un_irs<bits<4> opcod, string opc,
440 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
441 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
443 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
445 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
446 let isAsCheapAsAMove = Cheap;
447 let isReMaterializable = ReMat;
448 let Inst{31-27} = 0b11110;
450 let Inst{24-21} = opcod;
451 let Inst{19-16} = 0b1111; // Rn
455 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
457 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
458 let Inst{31-27} = 0b11101;
459 let Inst{26-25} = 0b01;
460 let Inst{24-21} = opcod;
461 let Inst{19-16} = 0b1111; // Rn
462 let Inst{14-12} = 0b000; // imm3
463 let Inst{7-6} = 0b00; // imm2
464 let Inst{5-4} = 0b00; // type
467 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
468 opc, ".w\t$Rd, $ShiftedRm",
469 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
470 let Inst{31-27} = 0b11101;
471 let Inst{26-25} = 0b01;
472 let Inst{24-21} = opcod;
473 let Inst{19-16} = 0b1111; // Rn
477 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
478 /// binary operation that produces a value. These are predicable and can be
479 /// changed to modify CPSR.
480 multiclass T2I_bin_irs<bits<4> opcod, string opc,
481 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
482 PatFrag opnode, string baseOpc, bit Commutable = 0,
485 def ri : T2sTwoRegImm<
486 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
487 opc, "\t$Rd, $Rn, $imm",
488 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
489 let Inst{31-27} = 0b11110;
491 let Inst{24-21} = opcod;
495 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
496 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
497 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
498 let isCommutable = Commutable;
499 let Inst{31-27} = 0b11101;
500 let Inst{26-25} = 0b01;
501 let Inst{24-21} = opcod;
502 let Inst{14-12} = 0b000; // imm3
503 let Inst{7-6} = 0b00; // imm2
504 let Inst{5-4} = 0b00; // type
507 def rs : T2sTwoRegShiftedReg<
508 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
509 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
510 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
511 let Inst{31-27} = 0b11101;
512 let Inst{26-25} = 0b01;
513 let Inst{24-21} = opcod;
515 // Assembly aliases for optional destination operand when it's the same
516 // as the source operand.
517 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
518 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
519 t2_so_imm:$imm, pred:$p,
521 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
522 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
525 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
526 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
527 t2_so_reg:$shift, pred:$p,
531 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
532 // the ".w" suffix to indicate that they are wide.
533 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
534 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
535 PatFrag opnode, string baseOpc, bit Commutable = 0> :
536 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
538 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
539 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
540 /// it is equivalent to the T2I_bin_irs counterpart.
541 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
543 def ri : T2sTwoRegImm<
544 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
545 opc, ".w\t$Rd, $Rn, $imm",
546 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
547 let Inst{31-27} = 0b11110;
549 let Inst{24-21} = opcod;
553 def rr : T2sThreeReg<
554 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
555 opc, "\t$Rd, $Rn, $Rm",
556 [/* For disassembly only; pattern left blank */]> {
557 let Inst{31-27} = 0b11101;
558 let Inst{26-25} = 0b01;
559 let Inst{24-21} = opcod;
560 let Inst{14-12} = 0b000; // imm3
561 let Inst{7-6} = 0b00; // imm2
562 let Inst{5-4} = 0b00; // type
565 def rs : T2sTwoRegShiftedReg<
566 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
567 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
568 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
569 let Inst{31-27} = 0b11101;
570 let Inst{26-25} = 0b01;
571 let Inst{24-21} = opcod;
575 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
576 /// instruction modifies the CPSR register.
577 let isCodeGenOnly = 1, Defs = [CPSR] in {
578 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
579 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
580 PatFrag opnode, bit Commutable = 0> {
582 def ri : T2TwoRegImm<
583 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
584 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
585 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
586 let Inst{31-27} = 0b11110;
588 let Inst{24-21} = opcod;
589 let Inst{20} = 1; // The S bit.
594 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
595 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
596 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
597 let isCommutable = Commutable;
598 let Inst{31-27} = 0b11101;
599 let Inst{26-25} = 0b01;
600 let Inst{24-21} = opcod;
601 let Inst{20} = 1; // The S bit.
602 let Inst{14-12} = 0b000; // imm3
603 let Inst{7-6} = 0b00; // imm2
604 let Inst{5-4} = 0b00; // type
607 def rs : T2TwoRegShiftedReg<
608 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
609 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
610 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
611 let Inst{31-27} = 0b11101;
612 let Inst{26-25} = 0b01;
613 let Inst{24-21} = opcod;
614 let Inst{20} = 1; // The S bit.
619 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
620 /// patterns for a binary operation that produces a value.
621 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
622 bit Commutable = 0> {
624 // The register-immediate version is re-materializable. This is useful
625 // in particular for taking the address of a local.
626 let isReMaterializable = 1 in {
627 def ri : T2sTwoRegImm<
628 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
629 opc, ".w\t$Rd, $Rn, $imm",
630 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
631 let Inst{31-27} = 0b11110;
634 let Inst{23-21} = op23_21;
640 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
641 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
642 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
646 let Inst{31-27} = 0b11110;
647 let Inst{26} = imm{11};
648 let Inst{25-24} = 0b10;
649 let Inst{23-21} = op23_21;
650 let Inst{20} = 0; // The S bit.
651 let Inst{19-16} = Rn;
653 let Inst{14-12} = imm{10-8};
655 let Inst{7-0} = imm{7-0};
658 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
659 opc, ".w\t$Rd, $Rn, $Rm",
660 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
661 let isCommutable = Commutable;
662 let Inst{31-27} = 0b11101;
663 let Inst{26-25} = 0b01;
665 let Inst{23-21} = op23_21;
666 let Inst{14-12} = 0b000; // imm3
667 let Inst{7-6} = 0b00; // imm2
668 let Inst{5-4} = 0b00; // type
671 def rs : T2sTwoRegShiftedReg<
672 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
673 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
674 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
675 let Inst{31-27} = 0b11101;
676 let Inst{26-25} = 0b01;
678 let Inst{23-21} = op23_21;
682 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
683 /// for a binary operation that produces a value and use the carry
684 /// bit. It's not predicable.
685 let Defs = [CPSR], Uses = [CPSR] in {
686 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
687 bit Commutable = 0> {
689 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
690 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
691 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
692 Requires<[IsThumb2]> {
693 let Inst{31-27} = 0b11110;
695 let Inst{24-21} = opcod;
699 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
700 opc, ".w\t$Rd, $Rn, $Rm",
701 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
702 Requires<[IsThumb2]> {
703 let isCommutable = Commutable;
704 let Inst{31-27} = 0b11101;
705 let Inst{26-25} = 0b01;
706 let Inst{24-21} = opcod;
707 let Inst{14-12} = 0b000; // imm3
708 let Inst{7-6} = 0b00; // imm2
709 let Inst{5-4} = 0b00; // type
712 def rs : T2sTwoRegShiftedReg<
713 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
714 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
715 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
716 Requires<[IsThumb2]> {
717 let Inst{31-27} = 0b11101;
718 let Inst{26-25} = 0b01;
719 let Inst{24-21} = opcod;
724 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
725 /// version is not needed since this is only for codegen.
726 let isCodeGenOnly = 1, Defs = [CPSR] in {
727 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
729 def ri : T2TwoRegImm<
730 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
731 !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
732 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
733 let Inst{31-27} = 0b11110;
735 let Inst{24-21} = opcod;
736 let Inst{20} = 1; // The S bit.
740 def rs : T2TwoRegShiftedReg<
741 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
742 IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
744 let Inst{31-27} = 0b11101;
745 let Inst{26-25} = 0b01;
746 let Inst{24-21} = opcod;
747 let Inst{20} = 1; // The S bit.
752 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
753 // rotate operation that produces a value.
754 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
756 def ri : T2sTwoRegShiftImm<
757 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
758 opc, ".w\t$Rd, $Rm, $imm",
759 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
760 let Inst{31-27} = 0b11101;
761 let Inst{26-21} = 0b010010;
762 let Inst{19-16} = 0b1111; // Rn
763 let Inst{5-4} = opcod;
766 def rr : T2sThreeReg<
767 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
768 opc, ".w\t$Rd, $Rn, $Rm",
769 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
770 let Inst{31-27} = 0b11111;
771 let Inst{26-23} = 0b0100;
772 let Inst{22-21} = opcod;
773 let Inst{15-12} = 0b1111;
774 let Inst{7-4} = 0b0000;
778 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
779 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
780 /// a explicit result, only implicitly set CPSR.
781 let isCompare = 1, Defs = [CPSR] in {
782 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
783 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
786 def ri : T2OneRegCmpImm<
787 (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
788 opc, ".w\t$Rn, $imm",
789 [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
790 let Inst{31-27} = 0b11110;
792 let Inst{24-21} = opcod;
793 let Inst{20} = 1; // The S bit.
795 let Inst{11-8} = 0b1111; // Rd
798 def rr : T2TwoRegCmp<
799 (outs), (ins GPR:$Rn, rGPR:$Rm), iir,
801 [(opnode GPR:$Rn, rGPR:$Rm)]> {
802 let Inst{31-27} = 0b11101;
803 let Inst{26-25} = 0b01;
804 let Inst{24-21} = opcod;
805 let Inst{20} = 1; // The S bit.
806 let Inst{14-12} = 0b000; // imm3
807 let Inst{11-8} = 0b1111; // Rd
808 let Inst{7-6} = 0b00; // imm2
809 let Inst{5-4} = 0b00; // type
812 def rs : T2OneRegCmpShiftedReg<
813 (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
814 opc, ".w\t$Rn, $ShiftedRm",
815 [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
816 let Inst{31-27} = 0b11101;
817 let Inst{26-25} = 0b01;
818 let Inst{24-21} = opcod;
819 let Inst{20} = 1; // The S bit.
820 let Inst{11-8} = 0b1111; // Rd
825 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
826 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
827 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
829 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
830 opc, ".w\t$Rt, $addr",
831 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
832 let Inst{31-27} = 0b11111;
833 let Inst{26-25} = 0b00;
834 let Inst{24} = signed;
836 let Inst{22-21} = opcod;
837 let Inst{20} = 1; // load
840 let Inst{15-12} = Rt;
843 let addr{12} = 1; // add = TRUE
844 let Inst{19-16} = addr{16-13}; // Rn
845 let Inst{23} = addr{12}; // U
846 let Inst{11-0} = addr{11-0}; // imm
848 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
850 [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
851 let Inst{31-27} = 0b11111;
852 let Inst{26-25} = 0b00;
853 let Inst{24} = signed;
855 let Inst{22-21} = opcod;
856 let Inst{20} = 1; // load
858 // Offset: index==TRUE, wback==FALSE
859 let Inst{10} = 1; // The P bit.
860 let Inst{8} = 0; // The W bit.
863 let Inst{15-12} = Rt;
866 let Inst{19-16} = addr{12-9}; // Rn
867 let Inst{9} = addr{8}; // U
868 let Inst{7-0} = addr{7-0}; // imm
870 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
871 opc, ".w\t$Rt, $addr",
872 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
873 let Inst{31-27} = 0b11111;
874 let Inst{26-25} = 0b00;
875 let Inst{24} = signed;
877 let Inst{22-21} = opcod;
878 let Inst{20} = 1; // load
879 let Inst{11-6} = 0b000000;
882 let Inst{15-12} = Rt;
885 let Inst{19-16} = addr{9-6}; // Rn
886 let Inst{3-0} = addr{5-2}; // Rm
887 let Inst{5-4} = addr{1-0}; // imm
889 let DecoderMethod = "DecodeT2LoadShift";
892 // FIXME: Is the pci variant actually needed?
893 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
894 opc, ".w\t$Rt, $addr",
895 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
896 let isReMaterializable = 1;
897 let Inst{31-27} = 0b11111;
898 let Inst{26-25} = 0b00;
899 let Inst{24} = signed;
900 let Inst{23} = ?; // add = (U == '1')
901 let Inst{22-21} = opcod;
902 let Inst{20} = 1; // load
903 let Inst{19-16} = 0b1111; // Rn
906 let Inst{15-12} = Rt{3-0};
907 let Inst{11-0} = addr{11-0};
911 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
912 multiclass T2I_st<bits<2> opcod, string opc,
913 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
915 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
916 opc, ".w\t$Rt, $addr",
917 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
918 let Inst{31-27} = 0b11111;
919 let Inst{26-23} = 0b0001;
920 let Inst{22-21} = opcod;
921 let Inst{20} = 0; // !load
924 let Inst{15-12} = Rt;
927 let addr{12} = 1; // add = TRUE
928 let Inst{19-16} = addr{16-13}; // Rn
929 let Inst{23} = addr{12}; // U
930 let Inst{11-0} = addr{11-0}; // imm
932 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
934 [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
935 let Inst{31-27} = 0b11111;
936 let Inst{26-23} = 0b0000;
937 let Inst{22-21} = opcod;
938 let Inst{20} = 0; // !load
940 // Offset: index==TRUE, wback==FALSE
941 let Inst{10} = 1; // The P bit.
942 let Inst{8} = 0; // The W bit.
945 let Inst{15-12} = Rt;
948 let Inst{19-16} = addr{12-9}; // Rn
949 let Inst{9} = addr{8}; // U
950 let Inst{7-0} = addr{7-0}; // imm
952 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
953 opc, ".w\t$Rt, $addr",
954 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
955 let Inst{31-27} = 0b11111;
956 let Inst{26-23} = 0b0000;
957 let Inst{22-21} = opcod;
958 let Inst{20} = 0; // !load
959 let Inst{11-6} = 0b000000;
962 let Inst{15-12} = Rt;
965 let Inst{19-16} = addr{9-6}; // Rn
966 let Inst{3-0} = addr{5-2}; // Rm
967 let Inst{5-4} = addr{1-0}; // imm
971 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
972 /// register and one whose operand is a register rotated by 8/16/24.
973 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
974 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
975 opc, ".w\t$Rd, $Rm$rot",
976 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
977 Requires<[IsThumb2]> {
978 let Inst{31-27} = 0b11111;
979 let Inst{26-23} = 0b0100;
980 let Inst{22-20} = opcod;
981 let Inst{19-16} = 0b1111; // Rn
982 let Inst{15-12} = 0b1111;
986 let Inst{5-4} = rot{1-0}; // rotate
989 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
990 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
991 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
992 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
993 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
994 Requires<[HasT2ExtractPack, IsThumb2]> {
996 let Inst{31-27} = 0b11111;
997 let Inst{26-23} = 0b0100;
998 let Inst{22-20} = opcod;
999 let Inst{19-16} = 0b1111; // Rn
1000 let Inst{15-12} = 0b1111;
1002 let Inst{5-4} = rot;
1005 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1007 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1008 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1009 opc, "\t$Rd, $Rm$rot", []>,
1010 Requires<[IsThumb2, HasT2ExtractPack]> {
1012 let Inst{31-27} = 0b11111;
1013 let Inst{26-23} = 0b0100;
1014 let Inst{22-20} = opcod;
1015 let Inst{19-16} = 0b1111; // Rn
1016 let Inst{15-12} = 0b1111;
1018 let Inst{5-4} = rot;
1021 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1022 /// register and one whose operand is a register rotated by 8/16/24.
1023 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1024 : T2ThreeReg<(outs rGPR:$Rd),
1025 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1026 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1027 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1028 Requires<[HasT2ExtractPack, IsThumb2]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0100;
1032 let Inst{22-20} = opcod;
1033 let Inst{15-12} = 0b1111;
1035 let Inst{5-4} = rot;
1038 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1039 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1040 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1042 let Inst{31-27} = 0b11111;
1043 let Inst{26-23} = 0b0100;
1044 let Inst{22-20} = opcod;
1045 let Inst{15-12} = 0b1111;
1047 let Inst{5-4} = rot;
1050 //===----------------------------------------------------------------------===//
1052 //===----------------------------------------------------------------------===//
1054 //===----------------------------------------------------------------------===//
1055 // Miscellaneous Instructions.
1058 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1059 string asm, list<dag> pattern>
1060 : T2XI<oops, iops, itin, asm, pattern> {
1064 let Inst{11-8} = Rd;
1065 let Inst{26} = label{11};
1066 let Inst{14-12} = label{10-8};
1067 let Inst{7-0} = label{7-0};
1070 // LEApcrel - Load a pc-relative address into a register without offending the
1072 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1073 (ins t2adrlabel:$addr, pred:$p),
1074 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1075 let Inst{31-27} = 0b11110;
1076 let Inst{25-24} = 0b10;
1077 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1080 let Inst{19-16} = 0b1111; // Rn
1085 let Inst{11-8} = Rd;
1086 let Inst{23} = addr{12};
1087 let Inst{21} = addr{12};
1088 let Inst{26} = addr{11};
1089 let Inst{14-12} = addr{10-8};
1090 let Inst{7-0} = addr{7-0};
1093 let neverHasSideEffects = 1, isReMaterializable = 1 in
1094 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1096 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1097 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1102 //===----------------------------------------------------------------------===//
1103 // Load / store Instructions.
1107 let canFoldAsLoad = 1, isReMaterializable = 1 in
1108 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1109 UnOpFrag<(load node:$Src)>>;
1111 // Loads with zero extension
1112 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1113 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1114 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1115 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1117 // Loads with sign extension
1118 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1119 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1120 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1121 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1123 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1125 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1126 (ins t2addrmode_imm8s4:$addr),
1127 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1128 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1130 // zextload i1 -> zextload i8
1131 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1132 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1133 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1134 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1135 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1136 (t2LDRBs t2addrmode_so_reg:$addr)>;
1137 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1138 (t2LDRBpci tconstpool:$addr)>;
1140 // extload -> zextload
1141 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1143 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1144 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1145 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1146 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1147 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1148 (t2LDRBs t2addrmode_so_reg:$addr)>;
1149 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1150 (t2LDRBpci tconstpool:$addr)>;
1152 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1153 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1154 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1155 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1156 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1157 (t2LDRBs t2addrmode_so_reg:$addr)>;
1158 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1159 (t2LDRBpci tconstpool:$addr)>;
1161 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1162 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1163 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1164 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1165 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1166 (t2LDRHs t2addrmode_so_reg:$addr)>;
1167 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1168 (t2LDRHpci tconstpool:$addr)>;
1170 // FIXME: The destination register of the loads and stores can't be PC, but
1171 // can be SP. We need another regclass (similar to rGPR) to represent
1172 // that. Not a pressing issue since these are selected manually,
1177 let mayLoad = 1, neverHasSideEffects = 1 in {
1178 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1179 (ins t2addrmode_imm8:$addr),
1180 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1181 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1184 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1185 (ins GPR:$base, t2am_imm8_offset:$addr),
1186 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1187 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1190 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1191 (ins t2addrmode_imm8:$addr),
1192 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1193 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1195 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1196 (ins GPR:$base, t2am_imm8_offset:$addr),
1197 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1198 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1201 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1202 (ins t2addrmode_imm8:$addr),
1203 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1204 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1206 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1207 (ins GPR:$base, t2am_imm8_offset:$addr),
1208 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1209 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1212 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1213 (ins t2addrmode_imm8:$addr),
1214 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1215 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1217 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1218 (ins GPR:$base, t2am_imm8_offset:$addr),
1219 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1220 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1223 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1224 (ins t2addrmode_imm8:$addr),
1225 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1226 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1228 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1229 (ins GPR:$base, t2am_imm8_offset:$addr),
1230 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1231 "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1233 } // mayLoad = 1, neverHasSideEffects = 1
1235 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1236 // for disassembly only.
1237 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1238 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1239 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1240 "\t$Rt, $addr", []> {
1241 let Inst{31-27} = 0b11111;
1242 let Inst{26-25} = 0b00;
1243 let Inst{24} = signed;
1245 let Inst{22-21} = type;
1246 let Inst{20} = 1; // load
1248 let Inst{10-8} = 0b110; // PUW.
1252 let Inst{15-12} = Rt;
1253 let Inst{19-16} = addr{12-9};
1254 let Inst{7-0} = addr{7-0};
1257 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1258 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1259 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1260 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1261 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1264 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1265 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1266 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1267 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1268 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1269 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1272 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1273 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1274 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1275 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1278 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1279 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1280 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1281 "str", "\t$Rt, [$Rn, $addr]!",
1282 "$Rn = $base_wb,@earlyclobber $base_wb",
1283 [(set GPRnopc:$base_wb,
1284 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1286 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1287 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1288 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1289 "str", "\t$Rt, [$Rn], $addr",
1290 "$Rn = $base_wb,@earlyclobber $base_wb",
1291 [(set GPRnopc:$base_wb,
1292 (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1294 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1295 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1296 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1297 "strh", "\t$Rt, [$Rn, $addr]!",
1298 "$Rn = $base_wb,@earlyclobber $base_wb",
1299 [(set GPRnopc:$base_wb,
1300 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1302 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1303 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1304 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1305 "strh", "\t$Rt, [$Rn], $addr",
1306 "$Rn = $base_wb,@earlyclobber $base_wb",
1307 [(set GPRnopc:$base_wb,
1308 (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1310 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1311 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1312 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1313 "strb", "\t$Rt, [$Rn, $addr]!",
1314 "$Rn = $base_wb,@earlyclobber $base_wb",
1315 [(set GPRnopc:$base_wb,
1316 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1318 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1319 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1320 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1321 "strb", "\t$Rt, [$Rn], $addr",
1322 "$Rn = $base_wb,@earlyclobber $base_wb",
1323 [(set GPRnopc:$base_wb,
1324 (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1326 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1328 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1329 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1330 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1331 "\t$Rt, $addr", []> {
1332 let Inst{31-27} = 0b11111;
1333 let Inst{26-25} = 0b00;
1334 let Inst{24} = 0; // not signed
1336 let Inst{22-21} = type;
1337 let Inst{20} = 0; // store
1339 let Inst{10-8} = 0b110; // PUW
1343 let Inst{15-12} = Rt;
1344 let Inst{19-16} = addr{12-9};
1345 let Inst{7-0} = addr{7-0};
1348 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1349 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1350 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1352 // ldrd / strd pre / post variants
1353 // For disassembly only.
1355 def t2LDRD_PRE : T2Ii8s4Tied<1, 1, 1,
1356 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1357 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1358 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1360 def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1361 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1362 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1363 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1365 def t2STRD_PRE : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1366 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1367 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1369 def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1370 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1371 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1373 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1374 // data/instruction access. These are for disassembly only.
1375 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1376 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1377 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1379 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1381 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1382 let Inst{31-25} = 0b1111100;
1383 let Inst{24} = instr;
1385 let Inst{21} = write;
1387 let Inst{15-12} = 0b1111;
1390 let addr{12} = 1; // add = TRUE
1391 let Inst{19-16} = addr{16-13}; // Rn
1392 let Inst{23} = addr{12}; // U
1393 let Inst{11-0} = addr{11-0}; // imm12
1396 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1398 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1399 let Inst{31-25} = 0b1111100;
1400 let Inst{24} = instr;
1401 let Inst{23} = 0; // U = 0
1403 let Inst{21} = write;
1405 let Inst{15-12} = 0b1111;
1406 let Inst{11-8} = 0b1100;
1409 let Inst{19-16} = addr{12-9}; // Rn
1410 let Inst{7-0} = addr{7-0}; // imm8
1413 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1415 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1416 let Inst{31-25} = 0b1111100;
1417 let Inst{24} = instr;
1418 let Inst{23} = 0; // add = TRUE for T1
1420 let Inst{21} = write;
1422 let Inst{15-12} = 0b1111;
1423 let Inst{11-6} = 0000000;
1426 let Inst{19-16} = addr{9-6}; // Rn
1427 let Inst{3-0} = addr{5-2}; // Rm
1428 let Inst{5-4} = addr{1-0}; // imm2
1430 let DecoderMethod = "DecodeT2LoadShift";
1434 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1435 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1436 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1438 //===----------------------------------------------------------------------===//
1439 // Load / store multiple Instructions.
1442 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1443 InstrItinClass itin_upd, bit L_bit> {
1445 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1446 itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1450 let Inst{31-27} = 0b11101;
1451 let Inst{26-25} = 0b00;
1452 let Inst{24-23} = 0b01; // Increment After
1454 let Inst{21} = 0; // No writeback
1455 let Inst{20} = L_bit;
1456 let Inst{19-16} = Rn;
1457 let Inst{15-0} = regs;
1460 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1461 itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1465 let Inst{31-27} = 0b11101;
1466 let Inst{26-25} = 0b00;
1467 let Inst{24-23} = 0b01; // Increment After
1469 let Inst{21} = 1; // Writeback
1470 let Inst{20} = L_bit;
1471 let Inst{19-16} = Rn;
1472 let Inst{15-0} = regs;
1475 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1476 itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1480 let Inst{31-27} = 0b11101;
1481 let Inst{26-25} = 0b00;
1482 let Inst{24-23} = 0b10; // Decrement Before
1484 let Inst{21} = 0; // No writeback
1485 let Inst{20} = L_bit;
1486 let Inst{19-16} = Rn;
1487 let Inst{15-0} = regs;
1490 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1491 itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1495 let Inst{31-27} = 0b11101;
1496 let Inst{26-25} = 0b00;
1497 let Inst{24-23} = 0b10; // Decrement Before
1499 let Inst{21} = 1; // Writeback
1500 let Inst{20} = L_bit;
1501 let Inst{19-16} = Rn;
1502 let Inst{15-0} = regs;
1506 let neverHasSideEffects = 1 in {
1508 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1509 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1511 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1512 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1514 } // neverHasSideEffects
1517 //===----------------------------------------------------------------------===//
1518 // Move Instructions.
1521 let neverHasSideEffects = 1 in
1522 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1523 "mov", ".w\t$Rd, $Rm", []> {
1524 let Inst{31-27} = 0b11101;
1525 let Inst{26-25} = 0b01;
1526 let Inst{24-21} = 0b0010;
1527 let Inst{19-16} = 0b1111; // Rn
1528 let Inst{14-12} = 0b000;
1529 let Inst{7-4} = 0b0000;
1532 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1533 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1534 AddedComplexity = 1 in
1535 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1536 "mov", ".w\t$Rd, $imm",
1537 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1538 let Inst{31-27} = 0b11110;
1540 let Inst{24-21} = 0b0010;
1541 let Inst{19-16} = 0b1111; // Rn
1545 def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1546 pred:$p, cc_out:$s)>;
1548 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1549 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1550 "movw", "\t$Rd, $imm",
1551 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1552 let Inst{31-27} = 0b11110;
1554 let Inst{24-21} = 0b0010;
1555 let Inst{20} = 0; // The S bit.
1561 let Inst{11-8} = Rd;
1562 let Inst{19-16} = imm{15-12};
1563 let Inst{26} = imm{11};
1564 let Inst{14-12} = imm{10-8};
1565 let Inst{7-0} = imm{7-0};
1568 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1569 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1571 let Constraints = "$src = $Rd" in {
1572 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1573 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1574 "movt", "\t$Rd, $imm",
1576 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1577 let Inst{31-27} = 0b11110;
1579 let Inst{24-21} = 0b0110;
1580 let Inst{20} = 0; // The S bit.
1586 let Inst{11-8} = Rd;
1587 let Inst{19-16} = imm{15-12};
1588 let Inst{26} = imm{11};
1589 let Inst{14-12} = imm{10-8};
1590 let Inst{7-0} = imm{7-0};
1593 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1594 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1597 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1599 //===----------------------------------------------------------------------===//
1600 // Extend Instructions.
1605 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1606 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1607 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1608 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1609 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1611 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1612 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1613 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1614 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1615 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1617 // TODO: SXT(A){B|H}16
1621 let AddedComplexity = 16 in {
1622 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1623 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1624 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1625 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1626 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1627 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1629 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1630 // The transformation should probably be done as a combiner action
1631 // instead so we can include a check for masking back in the upper
1632 // eight bits of the source into the lower eight bits of the result.
1633 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1634 // (t2UXTB16 rGPR:$Src, 3)>,
1635 // Requires<[HasT2ExtractPack, IsThumb2]>;
1636 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1637 (t2UXTB16 rGPR:$Src, 1)>,
1638 Requires<[HasT2ExtractPack, IsThumb2]>;
1640 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1641 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1642 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1643 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1644 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1647 //===----------------------------------------------------------------------===//
1648 // Arithmetic Instructions.
1651 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1652 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1653 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1654 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1656 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1657 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1658 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1659 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1660 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1661 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1662 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1664 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1665 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1666 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1667 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1670 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1671 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1672 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1673 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1675 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1676 // The assume-no-carry-in form uses the negation of the input since add/sub
1677 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1678 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1680 // The AddedComplexity preferences the first variant over the others since
1681 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1682 let AddedComplexity = 1 in
1683 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1684 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1685 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1686 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1687 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1688 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1689 let AddedComplexity = 1 in
1690 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1691 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1692 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1693 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1694 // The with-carry-in form matches bitwise not instead of the negation.
1695 // Effectively, the inverse interpretation of the carry flag already accounts
1696 // for part of the negation.
1697 let AddedComplexity = 1 in
1698 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1699 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1700 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1701 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1703 // Select Bytes -- for disassembly only
1705 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1706 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1707 Requires<[IsThumb2, HasThumb2DSP]> {
1708 let Inst{31-27} = 0b11111;
1709 let Inst{26-24} = 0b010;
1711 let Inst{22-20} = 0b010;
1712 let Inst{15-12} = 0b1111;
1714 let Inst{6-4} = 0b000;
1717 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1718 // And Miscellaneous operations -- for disassembly only
1719 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1720 list<dag> pat = [/* For disassembly only; pattern left blank */],
1721 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1722 string asm = "\t$Rd, $Rn, $Rm">
1723 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1724 Requires<[IsThumb2, HasThumb2DSP]> {
1725 let Inst{31-27} = 0b11111;
1726 let Inst{26-23} = 0b0101;
1727 let Inst{22-20} = op22_20;
1728 let Inst{15-12} = 0b1111;
1729 let Inst{7-4} = op7_4;
1735 let Inst{11-8} = Rd;
1736 let Inst{19-16} = Rn;
1740 // Saturating add/subtract -- for disassembly only
1742 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1743 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1744 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1745 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1746 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1747 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1748 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1749 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1750 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1751 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1752 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1753 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1754 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1755 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1756 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1757 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1758 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1759 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1760 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1761 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1762 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1763 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1765 // Signed/Unsigned add/subtract -- for disassembly only
1767 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1768 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1769 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1770 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1771 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1772 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1773 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1774 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1775 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1776 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1777 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1778 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1780 // Signed/Unsigned halving add/subtract -- for disassembly only
1782 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1783 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1784 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1785 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1786 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1787 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1788 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1789 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1790 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1791 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1792 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1793 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1795 // Helper class for disassembly only
1796 // A6.3.16 & A6.3.17
1797 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1798 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1799 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1800 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1801 let Inst{31-27} = 0b11111;
1802 let Inst{26-24} = 0b011;
1803 let Inst{23} = long;
1804 let Inst{22-20} = op22_20;
1805 let Inst{7-4} = op7_4;
1808 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1809 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1810 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1811 let Inst{31-27} = 0b11111;
1812 let Inst{26-24} = 0b011;
1813 let Inst{23} = long;
1814 let Inst{22-20} = op22_20;
1815 let Inst{7-4} = op7_4;
1818 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1820 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1821 (ins rGPR:$Rn, rGPR:$Rm),
1822 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1823 Requires<[IsThumb2, HasThumb2DSP]> {
1824 let Inst{15-12} = 0b1111;
1826 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1827 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1828 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1829 Requires<[IsThumb2, HasThumb2DSP]>;
1831 // Signed/Unsigned saturate -- for disassembly only
1833 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1834 string opc, string asm, list<dag> pattern>
1835 : T2I<oops, iops, itin, opc, asm, pattern> {
1841 let Inst{11-8} = Rd;
1842 let Inst{19-16} = Rn;
1843 let Inst{4-0} = sat_imm;
1844 let Inst{21} = sh{5};
1845 let Inst{14-12} = sh{4-2};
1846 let Inst{7-6} = sh{1-0};
1850 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1851 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1852 [/* For disassembly only; pattern left blank */]> {
1853 let Inst{31-27} = 0b11110;
1854 let Inst{25-22} = 0b1100;
1859 def t2SSAT16: T2SatI<
1860 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1861 "ssat16", "\t$Rd, $sat_imm, $Rn",
1862 [/* For disassembly only; pattern left blank */]>,
1863 Requires<[IsThumb2, HasThumb2DSP]> {
1864 let Inst{31-27} = 0b11110;
1865 let Inst{25-22} = 0b1100;
1868 let Inst{21} = 1; // sh = '1'
1869 let Inst{14-12} = 0b000; // imm3 = '000'
1870 let Inst{7-6} = 0b00; // imm2 = '00'
1874 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1875 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1876 [/* For disassembly only; pattern left blank */]> {
1877 let Inst{31-27} = 0b11110;
1878 let Inst{25-22} = 0b1110;
1883 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1885 "usat16", "\t$Rd, $sat_imm, $Rn",
1886 [/* For disassembly only; pattern left blank */]>,
1887 Requires<[IsThumb2, HasThumb2DSP]> {
1888 let Inst{31-27} = 0b11110;
1889 let Inst{25-22} = 0b1110;
1892 let Inst{21} = 1; // sh = '1'
1893 let Inst{14-12} = 0b000; // imm3 = '000'
1894 let Inst{7-6} = 0b00; // imm2 = '00'
1897 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1898 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1900 //===----------------------------------------------------------------------===//
1901 // Shift and rotate Instructions.
1904 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, BinOpFrag<(shl node:$LHS, node:$RHS)>>;
1905 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, BinOpFrag<(srl node:$LHS, node:$RHS)>>;
1906 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, BinOpFrag<(sra node:$LHS, node:$RHS)>>;
1907 defm t2ROR : T2I_sh_ir<0b11, "ror", imm1_31, BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1909 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1910 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1911 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1913 let Uses = [CPSR] in {
1914 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1915 "rrx", "\t$Rd, $Rm",
1916 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1917 let Inst{31-27} = 0b11101;
1918 let Inst{26-25} = 0b01;
1919 let Inst{24-21} = 0b0010;
1920 let Inst{19-16} = 0b1111; // Rn
1921 let Inst{14-12} = 0b000;
1922 let Inst{7-4} = 0b0011;
1926 let isCodeGenOnly = 1, Defs = [CPSR] in {
1927 def t2MOVsrl_flag : T2TwoRegShiftImm<
1928 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1929 "lsrs", ".w\t$Rd, $Rm, #1",
1930 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1931 let Inst{31-27} = 0b11101;
1932 let Inst{26-25} = 0b01;
1933 let Inst{24-21} = 0b0010;
1934 let Inst{20} = 1; // The S bit.
1935 let Inst{19-16} = 0b1111; // Rn
1936 let Inst{5-4} = 0b01; // Shift type.
1937 // Shift amount = Inst{14-12:7-6} = 1.
1938 let Inst{14-12} = 0b000;
1939 let Inst{7-6} = 0b01;
1941 def t2MOVsra_flag : T2TwoRegShiftImm<
1942 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1943 "asrs", ".w\t$Rd, $Rm, #1",
1944 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
1945 let Inst{31-27} = 0b11101;
1946 let Inst{26-25} = 0b01;
1947 let Inst{24-21} = 0b0010;
1948 let Inst{20} = 1; // The S bit.
1949 let Inst{19-16} = 0b1111; // Rn
1950 let Inst{5-4} = 0b10; // Shift type.
1951 // Shift amount = Inst{14-12:7-6} = 1.
1952 let Inst{14-12} = 0b000;
1953 let Inst{7-6} = 0b01;
1957 //===----------------------------------------------------------------------===//
1958 // Bitwise Instructions.
1961 defm t2AND : T2I_bin_w_irs<0b0000, "and",
1962 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1963 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
1964 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
1965 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1966 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
1967 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
1968 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1969 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
1971 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
1972 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1973 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
1976 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
1977 string opc, string asm, list<dag> pattern>
1978 : T2I<oops, iops, itin, opc, asm, pattern> {
1983 let Inst{11-8} = Rd;
1984 let Inst{4-0} = msb{4-0};
1985 let Inst{14-12} = lsb{4-2};
1986 let Inst{7-6} = lsb{1-0};
1989 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
1990 string opc, string asm, list<dag> pattern>
1991 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
1994 let Inst{19-16} = Rn;
1997 let Constraints = "$src = $Rd" in
1998 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
1999 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2000 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2001 let Inst{31-27} = 0b11110;
2002 let Inst{26} = 0; // should be 0.
2004 let Inst{24-20} = 0b10110;
2005 let Inst{19-16} = 0b1111; // Rn
2007 let Inst{5} = 0; // should be 0.
2010 let msb{4-0} = imm{9-5};
2011 let lsb{4-0} = imm{4-0};
2014 def t2SBFX: T2TwoRegBitFI<
2015 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2016 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2017 let Inst{31-27} = 0b11110;
2019 let Inst{24-20} = 0b10100;
2023 def t2UBFX: T2TwoRegBitFI<
2024 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2025 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2026 let Inst{31-27} = 0b11110;
2028 let Inst{24-20} = 0b11100;
2032 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2033 let Constraints = "$src = $Rd" in {
2034 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2035 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2036 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2037 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2038 bf_inv_mask_imm:$imm))]> {
2039 let Inst{31-27} = 0b11110;
2040 let Inst{26} = 0; // should be 0.
2042 let Inst{24-20} = 0b10110;
2044 let Inst{5} = 0; // should be 0.
2047 let msb{4-0} = imm{9-5};
2048 let lsb{4-0} = imm{4-0};
2051 // GNU as only supports this form of bfi (w/ 4 arguments)
2052 let isAsmParserOnly = 1 in
2053 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2054 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2056 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2058 let Inst{31-27} = 0b11110;
2059 let Inst{26} = 0; // should be 0.
2061 let Inst{24-20} = 0b10110;
2063 let Inst{5} = 0; // should be 0.
2067 let msb{4-0} = width; // Custom encoder => lsb+width-1
2068 let lsb{4-0} = lsbit;
2072 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2073 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2074 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2077 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2078 let AddedComplexity = 1 in
2079 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2080 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2081 UnOpFrag<(not node:$Src)>, 1, 1>;
2084 let AddedComplexity = 1 in
2085 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2086 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2088 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2089 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2090 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2091 Requires<[IsThumb2]>;
2093 def : T2Pat<(t2_so_imm_not:$src),
2094 (t2MVNi t2_so_imm_not:$src)>;
2096 //===----------------------------------------------------------------------===//
2097 // Multiply Instructions.
2099 let isCommutable = 1 in
2100 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2101 "mul", "\t$Rd, $Rn, $Rm",
2102 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2103 let Inst{31-27} = 0b11111;
2104 let Inst{26-23} = 0b0110;
2105 let Inst{22-20} = 0b000;
2106 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2107 let Inst{7-4} = 0b0000; // Multiply
2110 def t2MLA: T2FourReg<
2111 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2112 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2113 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2114 let Inst{31-27} = 0b11111;
2115 let Inst{26-23} = 0b0110;
2116 let Inst{22-20} = 0b000;
2117 let Inst{7-4} = 0b0000; // Multiply
2120 def t2MLS: T2FourReg<
2121 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2122 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2123 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2124 let Inst{31-27} = 0b11111;
2125 let Inst{26-23} = 0b0110;
2126 let Inst{22-20} = 0b000;
2127 let Inst{7-4} = 0b0001; // Multiply and Subtract
2130 // Extra precision multiplies with low / high results
2131 let neverHasSideEffects = 1 in {
2132 let isCommutable = 1 in {
2133 def t2SMULL : T2MulLong<0b000, 0b0000,
2134 (outs rGPR:$RdLo, rGPR:$RdHi),
2135 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2136 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2138 def t2UMULL : T2MulLong<0b010, 0b0000,
2139 (outs rGPR:$RdLo, rGPR:$RdHi),
2140 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2141 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2144 // Multiply + accumulate
2145 def t2SMLAL : T2MulLong<0b100, 0b0000,
2146 (outs rGPR:$RdLo, rGPR:$RdHi),
2147 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2148 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2150 def t2UMLAL : T2MulLong<0b110, 0b0000,
2151 (outs rGPR:$RdLo, rGPR:$RdHi),
2152 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2153 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2155 def t2UMAAL : T2MulLong<0b110, 0b0110,
2156 (outs rGPR:$RdLo, rGPR:$RdHi),
2157 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2158 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2159 Requires<[IsThumb2, HasThumb2DSP]>;
2160 } // neverHasSideEffects
2162 // Rounding variants of the below included for disassembly only
2164 // Most significant word multiply
2165 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2166 "smmul", "\t$Rd, $Rn, $Rm",
2167 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2168 Requires<[IsThumb2, HasThumb2DSP]> {
2169 let Inst{31-27} = 0b11111;
2170 let Inst{26-23} = 0b0110;
2171 let Inst{22-20} = 0b101;
2172 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2173 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2176 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2177 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2178 Requires<[IsThumb2, HasThumb2DSP]> {
2179 let Inst{31-27} = 0b11111;
2180 let Inst{26-23} = 0b0110;
2181 let Inst{22-20} = 0b101;
2182 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2183 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2186 def t2SMMLA : T2FourReg<
2187 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2188 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2189 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2190 Requires<[IsThumb2, HasThumb2DSP]> {
2191 let Inst{31-27} = 0b11111;
2192 let Inst{26-23} = 0b0110;
2193 let Inst{22-20} = 0b101;
2194 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2197 def t2SMMLAR: T2FourReg<
2198 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2199 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2200 Requires<[IsThumb2, HasThumb2DSP]> {
2201 let Inst{31-27} = 0b11111;
2202 let Inst{26-23} = 0b0110;
2203 let Inst{22-20} = 0b101;
2204 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2207 def t2SMMLS: T2FourReg<
2208 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2209 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2210 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2211 Requires<[IsThumb2, HasThumb2DSP]> {
2212 let Inst{31-27} = 0b11111;
2213 let Inst{26-23} = 0b0110;
2214 let Inst{22-20} = 0b110;
2215 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2218 def t2SMMLSR:T2FourReg<
2219 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2220 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2221 Requires<[IsThumb2, HasThumb2DSP]> {
2222 let Inst{31-27} = 0b11111;
2223 let Inst{26-23} = 0b0110;
2224 let Inst{22-20} = 0b110;
2225 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2228 multiclass T2I_smul<string opc, PatFrag opnode> {
2229 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2230 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2231 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2232 (sext_inreg rGPR:$Rm, i16)))]>,
2233 Requires<[IsThumb2, HasThumb2DSP]> {
2234 let Inst{31-27} = 0b11111;
2235 let Inst{26-23} = 0b0110;
2236 let Inst{22-20} = 0b001;
2237 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2238 let Inst{7-6} = 0b00;
2239 let Inst{5-4} = 0b00;
2242 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2243 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2244 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2245 (sra rGPR:$Rm, (i32 16))))]>,
2246 Requires<[IsThumb2, HasThumb2DSP]> {
2247 let Inst{31-27} = 0b11111;
2248 let Inst{26-23} = 0b0110;
2249 let Inst{22-20} = 0b001;
2250 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2251 let Inst{7-6} = 0b00;
2252 let Inst{5-4} = 0b01;
2255 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2256 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2257 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2258 (sext_inreg rGPR:$Rm, i16)))]>,
2259 Requires<[IsThumb2, HasThumb2DSP]> {
2260 let Inst{31-27} = 0b11111;
2261 let Inst{26-23} = 0b0110;
2262 let Inst{22-20} = 0b001;
2263 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2264 let Inst{7-6} = 0b00;
2265 let Inst{5-4} = 0b10;
2268 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2269 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2270 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2271 (sra rGPR:$Rm, (i32 16))))]>,
2272 Requires<[IsThumb2, HasThumb2DSP]> {
2273 let Inst{31-27} = 0b11111;
2274 let Inst{26-23} = 0b0110;
2275 let Inst{22-20} = 0b001;
2276 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2277 let Inst{7-6} = 0b00;
2278 let Inst{5-4} = 0b11;
2281 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2282 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2283 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2284 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2285 Requires<[IsThumb2, HasThumb2DSP]> {
2286 let Inst{31-27} = 0b11111;
2287 let Inst{26-23} = 0b0110;
2288 let Inst{22-20} = 0b011;
2289 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2290 let Inst{7-6} = 0b00;
2291 let Inst{5-4} = 0b00;
2294 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2295 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2296 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2297 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2298 Requires<[IsThumb2, HasThumb2DSP]> {
2299 let Inst{31-27} = 0b11111;
2300 let Inst{26-23} = 0b0110;
2301 let Inst{22-20} = 0b011;
2302 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2303 let Inst{7-6} = 0b00;
2304 let Inst{5-4} = 0b01;
2309 multiclass T2I_smla<string opc, PatFrag opnode> {
2311 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2312 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2313 [(set rGPR:$Rd, (add rGPR:$Ra,
2314 (opnode (sext_inreg rGPR:$Rn, i16),
2315 (sext_inreg rGPR:$Rm, i16))))]>,
2316 Requires<[IsThumb2, HasThumb2DSP]> {
2317 let Inst{31-27} = 0b11111;
2318 let Inst{26-23} = 0b0110;
2319 let Inst{22-20} = 0b001;
2320 let Inst{7-6} = 0b00;
2321 let Inst{5-4} = 0b00;
2325 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2326 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2327 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2328 (sra rGPR:$Rm, (i32 16)))))]>,
2329 Requires<[IsThumb2, HasThumb2DSP]> {
2330 let Inst{31-27} = 0b11111;
2331 let Inst{26-23} = 0b0110;
2332 let Inst{22-20} = 0b001;
2333 let Inst{7-6} = 0b00;
2334 let Inst{5-4} = 0b01;
2338 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2339 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2340 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2341 (sext_inreg rGPR:$Rm, i16))))]>,
2342 Requires<[IsThumb2, HasThumb2DSP]> {
2343 let Inst{31-27} = 0b11111;
2344 let Inst{26-23} = 0b0110;
2345 let Inst{22-20} = 0b001;
2346 let Inst{7-6} = 0b00;
2347 let Inst{5-4} = 0b10;
2351 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2352 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2353 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2354 (sra rGPR:$Rm, (i32 16)))))]>,
2355 Requires<[IsThumb2, HasThumb2DSP]> {
2356 let Inst{31-27} = 0b11111;
2357 let Inst{26-23} = 0b0110;
2358 let Inst{22-20} = 0b001;
2359 let Inst{7-6} = 0b00;
2360 let Inst{5-4} = 0b11;
2364 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2365 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2366 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2367 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2368 Requires<[IsThumb2, HasThumb2DSP]> {
2369 let Inst{31-27} = 0b11111;
2370 let Inst{26-23} = 0b0110;
2371 let Inst{22-20} = 0b011;
2372 let Inst{7-6} = 0b00;
2373 let Inst{5-4} = 0b00;
2377 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2378 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2379 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2380 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2381 Requires<[IsThumb2, HasThumb2DSP]> {
2382 let Inst{31-27} = 0b11111;
2383 let Inst{26-23} = 0b0110;
2384 let Inst{22-20} = 0b011;
2385 let Inst{7-6} = 0b00;
2386 let Inst{5-4} = 0b01;
2390 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2391 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2393 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2394 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2395 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2396 [/* For disassembly only; pattern left blank */]>,
2397 Requires<[IsThumb2, HasThumb2DSP]>;
2398 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2399 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2400 [/* For disassembly only; pattern left blank */]>,
2401 Requires<[IsThumb2, HasThumb2DSP]>;
2402 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2403 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2404 [/* For disassembly only; pattern left blank */]>,
2405 Requires<[IsThumb2, HasThumb2DSP]>;
2406 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2407 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2408 [/* For disassembly only; pattern left blank */]>,
2409 Requires<[IsThumb2, HasThumb2DSP]>;
2411 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2412 // These are for disassembly only.
2414 def t2SMUAD: T2ThreeReg_mac<
2415 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2416 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2417 Requires<[IsThumb2, HasThumb2DSP]> {
2418 let Inst{15-12} = 0b1111;
2420 def t2SMUADX:T2ThreeReg_mac<
2421 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2422 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2423 Requires<[IsThumb2, HasThumb2DSP]> {
2424 let Inst{15-12} = 0b1111;
2426 def t2SMUSD: T2ThreeReg_mac<
2427 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2428 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2429 Requires<[IsThumb2, HasThumb2DSP]> {
2430 let Inst{15-12} = 0b1111;
2432 def t2SMUSDX:T2ThreeReg_mac<
2433 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2434 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2435 Requires<[IsThumb2, HasThumb2DSP]> {
2436 let Inst{15-12} = 0b1111;
2438 def t2SMLAD : T2FourReg_mac<
2439 0, 0b010, 0b0000, (outs rGPR:$Rd),
2440 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2441 "\t$Rd, $Rn, $Rm, $Ra", []>,
2442 Requires<[IsThumb2, HasThumb2DSP]>;
2443 def t2SMLADX : T2FourReg_mac<
2444 0, 0b010, 0b0001, (outs rGPR:$Rd),
2445 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2446 "\t$Rd, $Rn, $Rm, $Ra", []>,
2447 Requires<[IsThumb2, HasThumb2DSP]>;
2448 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2449 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2450 "\t$Rd, $Rn, $Rm, $Ra", []>,
2451 Requires<[IsThumb2, HasThumb2DSP]>;
2452 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2453 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2454 "\t$Rd, $Rn, $Rm, $Ra", []>,
2455 Requires<[IsThumb2, HasThumb2DSP]>;
2456 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2457 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2458 "\t$Ra, $Rd, $Rm, $Rn", []>,
2459 Requires<[IsThumb2, HasThumb2DSP]>;
2460 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2461 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2462 "\t$Ra, $Rd, $Rm, $Rn", []>,
2463 Requires<[IsThumb2, HasThumb2DSP]>;
2464 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2465 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2466 "\t$Ra, $Rd, $Rm, $Rn", []>,
2467 Requires<[IsThumb2, HasThumb2DSP]>;
2468 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2469 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2470 "\t$Ra, $Rd, $Rm, $Rn", []>,
2471 Requires<[IsThumb2, HasThumb2DSP]>;
2473 //===----------------------------------------------------------------------===//
2474 // Division Instructions.
2475 // Signed and unsigned division on v7-M
2477 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2478 "sdiv", "\t$Rd, $Rn, $Rm",
2479 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2480 Requires<[HasDivide, IsThumb2]> {
2481 let Inst{31-27} = 0b11111;
2482 let Inst{26-21} = 0b011100;
2484 let Inst{15-12} = 0b1111;
2485 let Inst{7-4} = 0b1111;
2488 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2489 "udiv", "\t$Rd, $Rn, $Rm",
2490 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2491 Requires<[HasDivide, IsThumb2]> {
2492 let Inst{31-27} = 0b11111;
2493 let Inst{26-21} = 0b011101;
2495 let Inst{15-12} = 0b1111;
2496 let Inst{7-4} = 0b1111;
2499 //===----------------------------------------------------------------------===//
2500 // Misc. Arithmetic Instructions.
2503 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2504 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2505 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2506 let Inst{31-27} = 0b11111;
2507 let Inst{26-22} = 0b01010;
2508 let Inst{21-20} = op1;
2509 let Inst{15-12} = 0b1111;
2510 let Inst{7-6} = 0b10;
2511 let Inst{5-4} = op2;
2515 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2516 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2518 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2519 "rbit", "\t$Rd, $Rm",
2520 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2522 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2523 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2525 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2526 "rev16", ".w\t$Rd, $Rm",
2527 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2529 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2530 "revsh", ".w\t$Rd, $Rm",
2531 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2533 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2534 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2535 (t2REVSH rGPR:$Rm)>;
2537 def t2PKHBT : T2ThreeReg<
2538 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2539 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2540 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2541 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2543 Requires<[HasT2ExtractPack, IsThumb2]> {
2544 let Inst{31-27} = 0b11101;
2545 let Inst{26-25} = 0b01;
2546 let Inst{24-20} = 0b01100;
2547 let Inst{5} = 0; // BT form
2551 let Inst{14-12} = sh{4-2};
2552 let Inst{7-6} = sh{1-0};
2555 // Alternate cases for PKHBT where identities eliminate some nodes.
2556 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2557 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2558 Requires<[HasT2ExtractPack, IsThumb2]>;
2559 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2560 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2561 Requires<[HasT2ExtractPack, IsThumb2]>;
2563 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2564 // will match the pattern below.
2565 def t2PKHTB : T2ThreeReg<
2566 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2567 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2568 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2569 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2571 Requires<[HasT2ExtractPack, IsThumb2]> {
2572 let Inst{31-27} = 0b11101;
2573 let Inst{26-25} = 0b01;
2574 let Inst{24-20} = 0b01100;
2575 let Inst{5} = 1; // TB form
2579 let Inst{14-12} = sh{4-2};
2580 let Inst{7-6} = sh{1-0};
2583 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2584 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2585 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2586 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2587 Requires<[HasT2ExtractPack, IsThumb2]>;
2588 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2589 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2590 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2591 Requires<[HasT2ExtractPack, IsThumb2]>;
2593 //===----------------------------------------------------------------------===//
2594 // Comparison Instructions...
2596 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2597 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2598 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2600 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
2601 (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
2602 def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
2603 (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
2604 def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
2605 (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
2607 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2608 // Compare-to-zero still works out, just not the relationals
2609 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2610 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2611 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2612 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2613 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2615 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2616 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2618 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
2619 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2621 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2622 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2623 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2624 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2625 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2626 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2628 // Conditional moves
2629 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2630 // a two-value operand where a dag node expects two operands. :(
2631 let neverHasSideEffects = 1 in {
2632 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2633 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2635 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2636 RegConstraint<"$false = $Rd">;
2638 let isMoveImm = 1 in
2639 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2640 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2642 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2643 RegConstraint<"$false = $Rd">;
2645 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2646 let isCodeGenOnly = 1 in {
2647 let isMoveImm = 1 in
2648 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2650 "movw", "\t$Rd, $imm", []>,
2651 RegConstraint<"$false = $Rd"> {
2652 let Inst{31-27} = 0b11110;
2654 let Inst{24-21} = 0b0010;
2655 let Inst{20} = 0; // The S bit.
2661 let Inst{11-8} = Rd;
2662 let Inst{19-16} = imm{15-12};
2663 let Inst{26} = imm{11};
2664 let Inst{14-12} = imm{10-8};
2665 let Inst{7-0} = imm{7-0};
2668 let isMoveImm = 1 in
2669 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2670 (ins rGPR:$false, i32imm:$src, pred:$p),
2671 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2673 let isMoveImm = 1 in
2674 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2675 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2676 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2677 imm:$cc, CCR:$ccr))*/]>,
2678 RegConstraint<"$false = $Rd"> {
2679 let Inst{31-27} = 0b11110;
2681 let Inst{24-21} = 0b0011;
2682 let Inst{20} = 0; // The S bit.
2683 let Inst{19-16} = 0b1111; // Rn
2687 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2688 string opc, string asm, list<dag> pattern>
2689 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2690 let Inst{31-27} = 0b11101;
2691 let Inst{26-25} = 0b01;
2692 let Inst{24-21} = 0b0010;
2693 let Inst{20} = 0; // The S bit.
2694 let Inst{19-16} = 0b1111; // Rn
2695 let Inst{5-4} = opcod; // Shift type.
2697 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2698 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2699 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2700 RegConstraint<"$false = $Rd">;
2701 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2702 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2703 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2704 RegConstraint<"$false = $Rd">;
2705 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2706 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2707 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2708 RegConstraint<"$false = $Rd">;
2709 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2710 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2711 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2712 RegConstraint<"$false = $Rd">;
2713 } // isCodeGenOnly = 1
2714 } // neverHasSideEffects
2716 //===----------------------------------------------------------------------===//
2717 // Atomic operations intrinsics
2720 // memory barriers protect the atomic sequences
2721 let hasSideEffects = 1 in {
2722 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2723 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2724 Requires<[IsThumb, HasDB]> {
2726 let Inst{31-4} = 0xf3bf8f5;
2727 let Inst{3-0} = opt;
2731 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2733 [/* For disassembly only; pattern left blank */]>,
2734 Requires<[IsThumb, HasDB]> {
2736 let Inst{31-4} = 0xf3bf8f4;
2737 let Inst{3-0} = opt;
2740 // ISB has only full system option -- for disassembly only
2741 def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2742 [/* For disassembly only; pattern left blank */]>,
2743 Requires<[IsThumb2, HasV7]> {
2744 let Inst{31-4} = 0xf3bf8f6;
2745 let Inst{3-0} = 0b1111;
2748 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2749 InstrItinClass itin, string opc, string asm, string cstr,
2750 list<dag> pattern, bits<4> rt2 = 0b1111>
2751 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2752 let Inst{31-27} = 0b11101;
2753 let Inst{26-20} = 0b0001101;
2754 let Inst{11-8} = rt2;
2755 let Inst{7-6} = 0b01;
2756 let Inst{5-4} = opcod;
2757 let Inst{3-0} = 0b1111;
2761 let Inst{19-16} = addr;
2762 let Inst{15-12} = Rt;
2764 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2765 InstrItinClass itin, string opc, string asm, string cstr,
2766 list<dag> pattern, bits<4> rt2 = 0b1111>
2767 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2768 let Inst{31-27} = 0b11101;
2769 let Inst{26-20} = 0b0001100;
2770 let Inst{11-8} = rt2;
2771 let Inst{7-6} = 0b01;
2772 let Inst{5-4} = opcod;
2778 let Inst{19-16} = addr;
2779 let Inst{15-12} = Rt;
2782 let mayLoad = 1 in {
2783 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2784 AddrModeNone, 4, NoItinerary,
2785 "ldrexb", "\t$Rt, $addr", "", []>;
2786 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2787 AddrModeNone, 4, NoItinerary,
2788 "ldrexh", "\t$Rt, $addr", "", []>;
2789 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2790 AddrModeNone, 4, NoItinerary,
2791 "ldrex", "\t$Rt, $addr", "", []> {
2792 let Inst{31-27} = 0b11101;
2793 let Inst{26-20} = 0b0000101;
2794 let Inst{11-8} = 0b1111;
2795 let Inst{7-0} = 0b00000000; // imm8 = 0
2799 let Inst{19-16} = addr;
2800 let Inst{15-12} = Rt;
2802 let hasExtraDefRegAllocReq = 1 in
2803 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2804 (ins t2addrmode_reg:$addr),
2805 AddrModeNone, 4, NoItinerary,
2806 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2809 let Inst{11-8} = Rt2;
2813 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2814 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2815 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2816 AddrModeNone, 4, NoItinerary,
2817 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2818 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2819 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2820 AddrModeNone, 4, NoItinerary,
2821 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2822 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2823 AddrModeNone, 4, NoItinerary,
2824 "strex", "\t$Rd, $Rt, $addr", "",
2826 let Inst{31-27} = 0b11101;
2827 let Inst{26-20} = 0b0000100;
2828 let Inst{7-0} = 0b00000000; // imm8 = 0
2833 let Inst{11-8} = Rd;
2834 let Inst{19-16} = addr;
2835 let Inst{15-12} = Rt;
2839 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2840 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2841 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2842 AddrModeNone, 4, NoItinerary,
2843 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2846 let Inst{11-8} = Rt2;
2849 // Clear-Exclusive is for disassembly only.
2850 def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2851 [/* For disassembly only; pattern left blank */]>,
2852 Requires<[IsThumb2, HasV7]> {
2853 let Inst{31-16} = 0xf3bf;
2854 let Inst{15-14} = 0b10;
2857 let Inst{11-8} = 0b1111;
2858 let Inst{7-4} = 0b0010;
2859 let Inst{3-0} = 0b1111;
2862 //===----------------------------------------------------------------------===//
2863 // SJLJ Exception handling intrinsics
2864 // eh_sjlj_setjmp() is an instruction sequence to store the return
2865 // address and save #0 in R0 for the non-longjmp case.
2866 // Since by its nature we may be coming from some other function to get
2867 // here, and we're using the stack frame for the containing function to
2868 // save/restore registers, we can't keep anything live in regs across
2869 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2870 // when we get here from a longjmp(). We force everything out of registers
2871 // except for our own input by listing the relevant registers in Defs. By
2872 // doing so, we also cause the prologue/epilogue code to actively preserve
2873 // all of the callee-saved resgisters, which is exactly what we want.
2874 // $val is a scratch register for our use.
2876 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2877 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2878 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2879 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2880 AddrModeNone, 0, NoItinerary, "", "",
2881 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2882 Requires<[IsThumb2, HasVFP2]>;
2886 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2887 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2888 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2889 AddrModeNone, 0, NoItinerary, "", "",
2890 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2891 Requires<[IsThumb2, NoVFP]>;
2895 //===----------------------------------------------------------------------===//
2896 // Control-Flow Instructions
2899 // FIXME: remove when we have a way to marking a MI with these properties.
2900 // FIXME: Should pc be an implicit operand like PICADD, etc?
2901 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2902 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2903 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2904 reglist:$regs, variable_ops),
2905 4, IIC_iLoad_mBr, [],
2906 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2907 RegConstraint<"$Rn = $wb">;
2909 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2910 let isPredicable = 1 in
2911 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2913 [(br bb:$target)]> {
2914 let Inst{31-27} = 0b11110;
2915 let Inst{15-14} = 0b10;
2919 let Inst{26} = target{19};
2920 let Inst{11} = target{18};
2921 let Inst{13} = target{17};
2922 let Inst{21-16} = target{16-11};
2923 let Inst{10-0} = target{10-0};
2926 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2927 def t2BR_JT : t2PseudoInst<(outs),
2928 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2930 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2932 // FIXME: Add a non-pc based case that can be predicated.
2933 def t2TBB_JT : t2PseudoInst<(outs),
2934 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2937 def t2TBH_JT : t2PseudoInst<(outs),
2938 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2941 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2942 "tbb", "\t[$Rn, $Rm]", []> {
2945 let Inst{31-20} = 0b111010001101;
2946 let Inst{19-16} = Rn;
2947 let Inst{15-5} = 0b11110000000;
2948 let Inst{4} = 0; // B form
2952 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2953 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
2956 let Inst{31-20} = 0b111010001101;
2957 let Inst{19-16} = Rn;
2958 let Inst{15-5} = 0b11110000000;
2959 let Inst{4} = 1; // H form
2962 } // isNotDuplicable, isIndirectBranch
2964 } // isBranch, isTerminator, isBarrier
2966 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2967 // a two-value operand where a dag node expects two operands. :(
2968 let isBranch = 1, isTerminator = 1 in
2969 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2971 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2972 let Inst{31-27} = 0b11110;
2973 let Inst{15-14} = 0b10;
2977 let Inst{25-22} = p;
2980 let Inst{26} = target{20};
2981 let Inst{11} = target{19};
2982 let Inst{13} = target{18};
2983 let Inst{21-16} = target{17-12};
2984 let Inst{10-0} = target{11-1};
2986 let DecoderMethod = "DecodeThumb2BCCInstruction";
2989 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
2991 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2993 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2995 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
2997 (t2B uncondbrtarget:$dst)>,
2998 Requires<[IsThumb2, IsDarwin]>;
3002 let Defs = [ITSTATE] in
3003 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3004 AddrModeNone, 2, IIC_iALUx,
3005 "it$mask\t$cc", "", []> {
3006 // 16-bit instruction.
3007 let Inst{31-16} = 0x0000;
3008 let Inst{15-8} = 0b10111111;
3013 let Inst{3-0} = mask;
3016 // Branch and Exchange Jazelle -- for disassembly only
3018 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3019 [/* For disassembly only; pattern left blank */]> {
3020 let Inst{31-27} = 0b11110;
3022 let Inst{25-20} = 0b111100;
3023 let Inst{15-14} = 0b10;
3027 let Inst{19-16} = func;
3030 // Compare and branch on zero / non-zero
3031 let isBranch = 1, isTerminator = 1 in {
3032 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3033 "cbz\t$Rn, $target", []>,
3034 T1Misc<{0,0,?,1,?,?,?}>,
3035 Requires<[IsThumb2]> {
3039 let Inst{9} = target{5};
3040 let Inst{7-3} = target{4-0};
3044 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3045 "cbnz\t$Rn, $target", []>,
3046 T1Misc<{1,0,?,1,?,?,?}>,
3047 Requires<[IsThumb2]> {
3051 let Inst{9} = target{5};
3052 let Inst{7-3} = target{4-0};
3058 // Change Processor State is a system instruction -- for disassembly and
3060 // FIXME: Since the asm parser has currently no clean way to handle optional
3061 // operands, create 3 versions of the same instruction. Once there's a clean
3062 // framework to represent optional operands, change this behavior.
3063 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3064 !strconcat("cps", asm_op),
3065 [/* For disassembly only; pattern left blank */]> {
3071 let Inst{31-27} = 0b11110;
3073 let Inst{25-20} = 0b111010;
3074 let Inst{19-16} = 0b1111;
3075 let Inst{15-14} = 0b10;
3077 let Inst{10-9} = imod;
3079 let Inst{7-5} = iflags;
3080 let Inst{4-0} = mode;
3081 let DecoderMethod = "DecodeT2CPSInstruction";
3085 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3086 "$imod.w\t$iflags, $mode">;
3087 let mode = 0, M = 0 in
3088 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3089 "$imod.w\t$iflags">;
3090 let imod = 0, iflags = 0, M = 1 in
3091 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3093 // A6.3.4 Branches and miscellaneous control
3094 // Table A6-14 Change Processor State, and hint instructions
3095 // Helper class for disassembly only.
3096 class T2I_hint<bits<8> op7_0, string opc, string asm>
3097 : T2I<(outs), (ins), NoItinerary, opc, asm,
3098 [/* For disassembly only; pattern left blank */]> {
3099 let Inst{31-20} = 0xf3a;
3100 let Inst{19-16} = 0b1111;
3101 let Inst{15-14} = 0b10;
3103 let Inst{10-8} = 0b000;
3104 let Inst{7-0} = op7_0;
3107 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3108 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3109 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3110 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3111 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3113 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3114 let Inst{31-20} = 0xf3a;
3115 let Inst{15-14} = 0b10;
3117 let Inst{10-8} = 0b000;
3118 let Inst{7-4} = 0b1111;
3121 let Inst{3-0} = opt;
3124 // Secure Monitor Call is a system instruction -- for disassembly only
3125 // Option = Inst{19-16}
3126 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3127 [/* For disassembly only; pattern left blank */]> {
3128 let Inst{31-27} = 0b11110;
3129 let Inst{26-20} = 0b1111111;
3130 let Inst{15-12} = 0b1000;
3133 let Inst{19-16} = opt;
3136 class T2SRS<bits<12> op31_20,
3137 dag oops, dag iops, InstrItinClass itin,
3138 string opc, string asm, list<dag> pattern>
3139 : T2I<oops, iops, itin, opc, asm, pattern> {
3140 let Inst{31-20} = op31_20{11-0};
3143 let Inst{4-0} = mode{4-0};
3146 // Store Return State is a system instruction -- for disassembly only
3147 def t2SRSDBW : T2SRS<0b111010000010,
3148 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3149 [/* For disassembly only; pattern left blank */]>;
3150 def t2SRSDB : T2SRS<0b111010000000,
3151 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3152 [/* For disassembly only; pattern left blank */]>;
3153 def t2SRSIAW : T2SRS<0b111010011010,
3154 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3155 [/* For disassembly only; pattern left blank */]>;
3156 def t2SRSIA : T2SRS<0b111010011000,
3157 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3158 [/* For disassembly only; pattern left blank */]>;
3160 // Return From Exception is a system instruction -- for disassembly only
3162 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3163 string opc, string asm, list<dag> pattern>
3164 : T2I<oops, iops, itin, opc, asm, pattern> {
3165 let Inst{31-20} = op31_20{11-0};
3168 let Inst{19-16} = Rn;
3169 let Inst{15-0} = 0xc000;
3172 def t2RFEDBW : T2RFE<0b111010000011,
3173 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3174 [/* For disassembly only; pattern left blank */]>;
3175 def t2RFEDB : T2RFE<0b111010000001,
3176 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3177 [/* For disassembly only; pattern left blank */]>;
3178 def t2RFEIAW : T2RFE<0b111010011011,
3179 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3180 [/* For disassembly only; pattern left blank */]>;
3181 def t2RFEIA : T2RFE<0b111010011001,
3182 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3183 [/* For disassembly only; pattern left blank */]>;
3185 //===----------------------------------------------------------------------===//
3186 // Non-Instruction Patterns
3189 // 32-bit immediate using movw + movt.
3190 // This is a single pseudo instruction to make it re-materializable.
3191 // FIXME: Remove this when we can do generalized remat.
3192 let isReMaterializable = 1, isMoveImm = 1 in
3193 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3194 [(set rGPR:$dst, (i32 imm:$src))]>,
3195 Requires<[IsThumb, HasV6T2]>;
3197 // Pseudo instruction that combines movw + movt + add pc (if pic).
3198 // It also makes it possible to rematerialize the instructions.
3199 // FIXME: Remove this when we can do generalized remat and when machine licm
3200 // can properly the instructions.
3201 let isReMaterializable = 1 in {
3202 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3204 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3205 Requires<[IsThumb2, UseMovt]>;
3207 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3209 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3210 Requires<[IsThumb2, UseMovt]>;
3213 // ConstantPool, GlobalAddress, and JumpTable
3214 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3215 Requires<[IsThumb2, DontUseMovt]>;
3216 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3217 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3218 Requires<[IsThumb2, UseMovt]>;
3220 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3221 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3223 // Pseudo instruction that combines ldr from constpool and add pc. This should
3224 // be expanded into two instructions late to allow if-conversion and
3226 let canFoldAsLoad = 1, isReMaterializable = 1 in
3227 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3229 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3231 Requires<[IsThumb2]>;
3233 //===----------------------------------------------------------------------===//
3234 // Move between special register and ARM core register -- for disassembly only
3237 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3238 dag oops, dag iops, InstrItinClass itin,
3239 string opc, string asm, list<dag> pattern>
3240 : T2I<oops, iops, itin, opc, asm, pattern> {
3241 let Inst{31-20} = op31_20{11-0};
3242 let Inst{15-14} = op15_14{1-0};
3243 let Inst{12} = op12{0};
3246 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3247 dag oops, dag iops, InstrItinClass itin,
3248 string opc, string asm, list<dag> pattern>
3249 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3251 let Inst{11-8} = Rd;
3252 let Inst{19-16} = 0b1111;
3255 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3256 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3257 [/* For disassembly only; pattern left blank */]>;
3258 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3259 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3260 [/* For disassembly only; pattern left blank */]>;
3262 // Move from ARM core register to Special Register
3264 // No need to have both system and application versions, the encodings are the
3265 // same and the assembly parser has no way to distinguish between them. The mask
3266 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3267 // the mask with the fields to be accessed in the special register.
3268 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3269 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3270 NoItinerary, "msr", "\t$mask, $Rn",
3271 [/* For disassembly only; pattern left blank */]> {
3274 let Inst{19-16} = Rn;
3275 let Inst{20} = mask{4}; // R Bit
3277 let Inst{11-8} = mask{3-0};
3280 //===----------------------------------------------------------------------===//
3281 // Move between coprocessor and ARM core register
3284 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3286 : T2Cop<Op, oops, iops,
3287 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3289 let Inst{27-24} = 0b1110;
3290 let Inst{20} = direction;
3300 let Inst{15-12} = Rt;
3301 let Inst{11-8} = cop;
3302 let Inst{23-21} = opc1;
3303 let Inst{7-5} = opc2;
3304 let Inst{3-0} = CRm;
3305 let Inst{19-16} = CRn;
3308 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3309 list<dag> pattern = []>
3311 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3312 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3313 let Inst{27-24} = 0b1100;
3314 let Inst{23-21} = 0b010;
3315 let Inst{20} = direction;
3323 let Inst{15-12} = Rt;
3324 let Inst{19-16} = Rt2;
3325 let Inst{11-8} = cop;
3326 let Inst{7-4} = opc1;
3327 let Inst{3-0} = CRm;
3330 /* from ARM core register to coprocessor */
3331 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3333 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3334 c_imm:$CRm, imm0_7:$opc2),
3335 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3336 imm:$CRm, imm:$opc2)]>;
3337 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3338 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3339 c_imm:$CRm, imm0_7:$opc2),
3340 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3341 imm:$CRm, imm:$opc2)]>;
3343 /* from coprocessor to ARM core register */
3344 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3345 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3346 c_imm:$CRm, imm0_7:$opc2), []>;
3348 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3349 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3350 c_imm:$CRm, imm0_7:$opc2), []>;
3352 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3353 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3355 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3356 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3359 /* from ARM core register to coprocessor */
3360 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3361 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3363 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3364 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3365 GPR:$Rt2, imm:$CRm)]>;
3366 /* from coprocessor to ARM core register */
3367 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3369 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3371 //===----------------------------------------------------------------------===//
3372 // Other Coprocessor Instructions.
3375 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3376 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3377 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3378 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3379 imm:$CRm, imm:$opc2)]> {
3380 let Inst{27-24} = 0b1110;
3389 let Inst{3-0} = CRm;
3391 let Inst{7-5} = opc2;
3392 let Inst{11-8} = cop;
3393 let Inst{15-12} = CRd;
3394 let Inst{19-16} = CRn;
3395 let Inst{23-20} = opc1;
3398 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3399 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3400 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3401 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3402 imm:$CRm, imm:$opc2)]> {
3403 let Inst{27-24} = 0b1110;
3412 let Inst{3-0} = CRm;
3414 let Inst{7-5} = opc2;
3415 let Inst{11-8} = cop;
3416 let Inst{15-12} = CRd;
3417 let Inst{19-16} = CRn;
3418 let Inst{23-20} = opc1;
3423 //===----------------------------------------------------------------------===//
3424 // Non-Instruction Patterns
3427 // SXT/UXT with no rotate
3428 let AddedComplexity = 16 in {
3429 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3430 Requires<[IsThumb2]>;
3431 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3432 Requires<[IsThumb2]>;
3433 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3434 Requires<[HasT2ExtractPack, IsThumb2]>;
3435 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3436 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3437 Requires<[HasT2ExtractPack, IsThumb2]>;
3438 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3439 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3440 Requires<[HasT2ExtractPack, IsThumb2]>;
3443 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3444 Requires<[IsThumb2]>;
3445 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3446 Requires<[IsThumb2]>;
3447 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3448 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3449 Requires<[HasT2ExtractPack, IsThumb2]>;
3450 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3451 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3452 Requires<[HasT2ExtractPack, IsThumb2]>;
3454 // Atomic load/store patterns
3455 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3456 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3457 def : T2Pat<(atomic_load_8 t2addrmode_imm8:$addr),
3458 (t2LDRBi8 t2addrmode_imm8:$addr)>;
3459 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3460 (t2LDRBs t2addrmode_so_reg:$addr)>;
3461 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3462 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3463 def : T2Pat<(atomic_load_16 t2addrmode_imm8:$addr),
3464 (t2LDRHi8 t2addrmode_imm8:$addr)>;
3465 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3466 (t2LDRHs t2addrmode_so_reg:$addr)>;
3467 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3468 (t2LDRi12 t2addrmode_imm12:$addr)>;
3469 def : T2Pat<(atomic_load_32 t2addrmode_imm8:$addr),
3470 (t2LDRi8 t2addrmode_imm8:$addr)>;
3471 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3472 (t2LDRs t2addrmode_so_reg:$addr)>;
3473 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3474 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3475 def : T2Pat<(atomic_store_8 t2addrmode_imm8:$addr, GPR:$val),
3476 (t2STRBi8 GPR:$val, t2addrmode_imm8:$addr)>;
3477 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3478 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3479 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3480 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3481 def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val),
3482 (t2STRHi8 GPR:$val, t2addrmode_imm8:$addr)>;
3483 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3484 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3485 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3486 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3487 def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
3488 (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>;
3489 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3490 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;