1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Shifted operands. No register controlled shifts for Thumb2.
25 // Note: We do not support rrx shifted operands yet.
26 def t2_so_reg : Operand<i32>, // reg imm
27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
29 let PrintMethod = "printT2SOOperand";
30 let MIOperandInfo = (ops GPR, i32imm);
33 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
34 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
38 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
39 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
43 // t2_so_imm - Match a 32-bit immediate operand, which is an
44 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
45 // immediate splatted into multiple bytes of the word. t2_so_imm values are
46 // represented in the imm field in the same 12-bit form that they are encoded
47 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
48 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
49 def t2_so_imm : Operand<i32>,
51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
54 // t2_so_imm_not - Match an immediate that is a complement
56 def t2_so_imm_not : Operand<i32>,
58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59 }], t2_so_imm_not_XFORM>;
61 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62 def t2_so_imm_neg : Operand<i32>,
64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
65 }], t2_so_imm_neg_XFORM>;
67 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
68 def imm1_31 : PatLeaf<(i32 imm), [{
69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
72 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
73 def imm0_4095 : PatLeaf<(i32 imm), [{
74 return (uint32_t)N->getZExtValue() < 4096;
77 def imm0_4095_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)(-N->getZExtValue()) < 4096;
81 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
83 def imm0_65535 : PatLeaf<(i32 imm), [{
84 return (uint32_t)N->getZExtValue() < 65536;
87 /// Split a 32-bit immediate into two 16 bit parts.
88 def t2_lo16 : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
93 def t2_hi16 : SDNodeXForm<imm, [{
94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
97 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
98 // Returns true if all low 16-bits are 0.
99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
103 // Define Thumb2 specific addressing modes.
105 // t2addrmode_imm12 := reg + imm12
106 def t2addrmode_imm12 : Operand<i32>,
107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
108 let PrintMethod = "printT2AddrModeImm12Operand";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2addrmode_imm8 := reg - imm8
113 def t2addrmode_imm8 : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
115 let PrintMethod = "printT2AddrModeImm8Operand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 def t2am_imm8_offset : Operand<i32>,
120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
121 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
124 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
125 def t2addrmode_imm8s4 : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
127 let PrintMethod = "printT2AddrModeImm8s4Operand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
131 // t2addrmode_so_reg := reg + (reg << imm2)
132 def t2addrmode_so_reg : Operand<i32>,
133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
134 let PrintMethod = "printT2AddrModeSoRegOperand";
135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
139 //===----------------------------------------------------------------------===//
140 // Multiclass helpers...
143 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
144 /// unary operation that produces a value. These are predicable and can be
145 /// changed to modify CPSR.
146 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
151 let isAsCheapAsAMove = Cheap;
152 let isReMaterializable = ReMat;
155 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
157 [(set GPR:$dst, (opnode GPR:$src))]>;
159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
164 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
165 // binary operation that produces a value. These are predicable and can be
166 /// changed to modify CPSR.
167 multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
169 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
170 opc, " $dst, $lhs, $rhs",
171 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
173 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
174 opc, " $dst, $lhs, $rhs",
175 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
176 let isCommutable = Commutable;
179 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
180 opc, " $dst, $lhs, $rhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
184 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
185 /// reversed. It doesn't define the 'rr' form since it's handled by its
186 /// T2I_bin_irs counterpart.
187 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
189 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
190 opc, " $dst, $rhs, $lhs",
191 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
193 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
194 opc, " $dst, $rhs, $lhs",
195 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
198 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
199 /// instruction modifies the CPSR register.
200 let Defs = [CPSR] in {
201 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
203 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
204 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
205 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
207 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
208 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
209 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
210 let isCommutable = Commutable;
213 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
214 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
219 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
220 /// patterns for a binary operation that produces a value.
221 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
223 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
224 opc, " $dst, $lhs, $rhs",
225 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
227 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
228 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
229 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
231 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
232 opc, " $dst, $lhs, $rhs",
233 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
234 let isCommutable = Commutable;
237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
238 opc, " $dst, $lhs, $rhs",
239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
242 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
243 /// binary operation that produces a value and use and define the carry bit.
244 /// It's not predicable.
245 let Uses = [CPSR] in {
246 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
248 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
249 opc, " $dst, $lhs, $rhs",
250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
251 Requires<[IsThumb2, CarryDefIsUnused]>;
253 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
254 opc, " $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
256 Requires<[IsThumb2, CarryDefIsUnused]> {
257 let isCommutable = Commutable;
260 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
261 opc, " $dst, $lhs, $rhs",
262 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
263 Requires<[IsThumb2, CarryDefIsUnused]>;
264 // Carry setting variants
266 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
267 !strconcat(opc, "s $dst, $lhs, $rhs"),
268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
269 Requires<[IsThumb2, CarryDefIsUsed]> {
273 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
274 !strconcat(opc, "s $dst, $lhs, $rhs"),
275 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
276 Requires<[IsThumb2, CarryDefIsUsed]> {
278 let isCommutable = Commutable;
281 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
282 !strconcat(opc, "s $dst, $lhs, $rhs"),
283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
284 Requires<[IsThumb2, CarryDefIsUsed]> {
290 /// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
291 /// reversed. It doesn't define the 'rr' form since it's handled by its
292 /// T2I_adde_sube_irs counterpart.
293 let Defs = [CPSR], Uses = [CPSR] in {
294 multiclass T2I_rsc_is<string opc, PatFrag opnode> {
296 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
297 opc, " $dst, $rhs, $lhs",
298 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
299 Requires<[IsThumb2, CarryDefIsUnused]>;
301 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
302 opc, " $dst, $rhs, $lhs",
303 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
304 Requires<[IsThumb2, CarryDefIsUnused]>;
306 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
307 !strconcat(opc, "s $dst, $rhs, $lhs"),
308 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
309 Requires<[IsThumb2, CarryDefIsUsed]> {
313 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
314 !strconcat(opc, "s $dst, $rhs, $lhs"),
315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
316 Requires<[IsThumb2, CarryDefIsUsed]> {
322 /// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
323 /// reversed. It doesn't define the 'rr' form since it's handled by its
324 /// T2I_bin_s_irs counterpart.
325 let Defs = [CPSR] in {
326 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
328 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
329 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
330 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
332 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
333 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
334 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
338 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
339 // rotate operation that produces a value.
340 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
342 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
343 opc, " $dst, $lhs, $rhs",
344 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
346 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
347 opc, " $dst, $lhs, $rhs",
348 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
351 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
352 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
353 /// a explicit result, only implicitly set CPSR.
354 let Uses = [CPSR] in {
355 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
357 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
359 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
361 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
363 [(opnode GPR:$lhs, GPR:$rhs)]>;
365 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
367 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
371 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
372 multiclass T2I_ld<string opc, PatFrag opnode> {
373 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
375 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
376 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
378 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
379 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
381 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
382 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
384 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
387 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
388 multiclass T2I_st<string opc, PatFrag opnode> {
389 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
391 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
392 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
394 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
395 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
397 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
400 /// T2I_picld - Defines the PIC load pattern.
401 class T2I_picld<string opc, PatFrag opnode> :
402 T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
403 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
404 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
406 /// T2I_picst - Defines the PIC store pattern.
407 class T2I_picst<string opc, PatFrag opnode> :
408 T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
409 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
410 [(opnode GPR:$src, addrmodepc:$addr)]>;
413 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
414 /// register and one whose operand is a register rotated by 8/16/24.
415 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
416 def r : T2I<(outs GPR:$dst), (ins GPR:$Src),
418 [(set GPR:$dst, (opnode GPR:$Src))]>;
419 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
420 opc, " $dst, $Src, ror $rot",
421 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
424 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
425 /// register and one whose operand is a register rotated by 8/16/24.
426 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
427 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
428 opc, " $dst, $LHS, $RHS",
429 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
430 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
431 opc, " $dst, $LHS, $RHS, ror $rot",
432 [(set GPR:$dst, (opnode GPR:$LHS,
433 (rotr GPR:$RHS, rot_imm:$rot)))]>;
436 //===----------------------------------------------------------------------===//
438 //===----------------------------------------------------------------------===//
440 //===----------------------------------------------------------------------===//
441 // Miscellaneous Instructions.
444 let isNotDuplicable = 1 in
445 def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
446 "$cp:\n\tadd $dst, pc",
447 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
450 // LEApcrel - Load a pc-relative address into a register without offending the
452 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
453 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
454 "${:private}PCRELL${:uid}+8))\n"),
455 !strconcat("${:private}PCRELL${:uid}:\n\t",
456 "add$p $dst, pc, #PCRELV${:uid}")),
459 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
460 (ins i32imm:$label, i32imm:$id, pred:$p),
461 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
462 "${:private}PCRELL${:uid}+8))\n"),
463 !strconcat("${:private}PCRELL${:uid}:\n\t",
464 "add$p $dst, pc, #PCRELV${:uid}")),
467 // ADD rd, sp, #so_imm
468 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
469 "add $dst, $sp, $imm",
472 // ADD rd, sp, #imm12
473 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
474 "addw $dst, $sp, $imm",
477 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
478 "addw $dst, $sp, $rhs",
482 //===----------------------------------------------------------------------===//
483 // Load / store Instructions.
487 let canFoldAsLoad = 1 in
488 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
490 // Loads with zero extension
491 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
492 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
494 // Loads with sign extension
495 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
496 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
500 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
501 "ldrd", " $dst, $addr", []>;
502 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
503 "ldrd", " $dst, $addr", []>;
506 // zextload i1 -> zextload i8
507 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
508 (t2LDRBi12 t2addrmode_imm12:$addr)>;
509 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
510 (t2LDRBi8 t2addrmode_imm8:$addr)>;
511 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
512 (t2LDRBs t2addrmode_so_reg:$addr)>;
513 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
514 (t2LDRBpci tconstpool:$addr)>;
516 // extload -> zextload
517 // FIXME: Reduce the number of patterns by legalizing extload to zextload
519 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
520 (t2LDRBi12 t2addrmode_imm12:$addr)>;
521 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
522 (t2LDRBi8 t2addrmode_imm8:$addr)>;
523 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
524 (t2LDRBs t2addrmode_so_reg:$addr)>;
525 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
526 (t2LDRBpci tconstpool:$addr)>;
528 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
529 (t2LDRBi12 t2addrmode_imm12:$addr)>;
530 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
531 (t2LDRBi8 t2addrmode_imm8:$addr)>;
532 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
533 (t2LDRBs t2addrmode_so_reg:$addr)>;
534 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
535 (t2LDRBpci tconstpool:$addr)>;
537 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
538 (t2LDRHi12 t2addrmode_imm12:$addr)>;
539 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
540 (t2LDRHi8 t2addrmode_imm8:$addr)>;
541 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
542 (t2LDRHs t2addrmode_so_reg:$addr)>;
543 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
544 (t2LDRHpci tconstpool:$addr)>;
548 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
549 (ins t2addrmode_imm8:$addr),
550 AddrModeT2_i8, IndexModePre,
551 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
554 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
555 (ins GPR:$base, t2am_imm8_offset:$offset),
556 AddrModeT2_i8, IndexModePost,
557 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
560 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
561 (ins t2addrmode_imm8:$addr),
562 AddrModeT2_i8, IndexModePre,
563 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
565 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
566 (ins GPR:$base, t2am_imm8_offset:$offset),
567 AddrModeT2_i8, IndexModePost,
568 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
571 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
572 (ins t2addrmode_imm8:$addr),
573 AddrModeT2_i8, IndexModePre,
574 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
576 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
577 (ins GPR:$base, t2am_imm8_offset:$offset),
578 AddrModeT2_i8, IndexModePost,
579 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
582 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
583 (ins t2addrmode_imm8:$addr),
584 AddrModeT2_i8, IndexModePre,
585 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
587 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
588 (ins GPR:$base, t2am_imm8_offset:$offset),
589 AddrModeT2_i8, IndexModePost,
590 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
593 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
594 (ins t2addrmode_imm8:$addr),
595 AddrModeT2_i8, IndexModePre,
596 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
598 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
599 (ins GPR:$base, t2am_imm8_offset:$offset),
600 AddrModeT2_i8, IndexModePost,
601 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
606 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
607 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
608 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
612 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
613 "strd", " $src, $addr", []>;
616 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
617 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
618 AddrModeT2_i8, IndexModePre,
619 "str", " $src, [$base, $offset]!", "$base = $base_wb",
621 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
623 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
624 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
625 AddrModeT2_i8, IndexModePost,
626 "str", " $src, [$base], $offset", "$base = $base_wb",
628 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
630 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
631 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
632 AddrModeT2_i8, IndexModePre,
633 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
635 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
637 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
638 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
639 AddrModeT2_i8, IndexModePost,
640 "strh", " $src, [$base], $offset", "$base = $base_wb",
642 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
644 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
645 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
646 AddrModeT2_i8, IndexModePre,
647 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
649 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
651 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
652 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
653 AddrModeT2_i8, IndexModePost,
654 "strb", " $src, [$base], $offset", "$base = $base_wb",
656 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
659 // Address computation and loads and stores in PIC mode.
660 let isNotDuplicable = 1, AddedComplexity = 10 in {
661 let canFoldAsLoad = 1 in
662 def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
664 def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
665 def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
666 def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
667 def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
669 def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
670 def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
671 def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
672 } // isNotDuplicable = 1, AddedComplexity = 10
674 // FIXME: ldrd / strd pre / post variants
676 //===----------------------------------------------------------------------===//
677 // Load / store multiple Instructions.
681 def t2LDM : T2XI<(outs),
682 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
683 "ldm${addr:submode}${p} $addr, $dst1", []>;
686 def t2STM : T2XI<(outs),
687 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
688 "stm${addr:submode}${p} $addr, $src1", []>;
690 //===----------------------------------------------------------------------===//
691 // Move Instructions.
694 let neverHasSideEffects = 1 in
695 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
696 "mov", " $dst, $src", []>;
698 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
699 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
700 "mov", " $dst, $src",
701 [(set GPR:$dst, t2_so_imm:$src)]>;
703 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
704 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
705 "movw", " $dst, $src",
706 [(set GPR:$dst, imm0_65535:$src)]>;
708 // FIXME: Also available in ARM mode.
709 let Constraints = "$src = $dst" in
710 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
711 "movt", " $dst, $imm",
713 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
715 //===----------------------------------------------------------------------===//
716 // Extend Instructions.
721 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
722 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
724 defm t2SXTAB : T2I_bin_rrot<"sxtab",
725 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
726 defm t2SXTAH : T2I_bin_rrot<"sxtah",
727 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
729 // TODO: SXT(A){B|H}16
733 let AddedComplexity = 16 in {
734 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
735 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
736 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
738 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
739 (t2UXTB16r_rot GPR:$Src, 24)>;
740 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
741 (t2UXTB16r_rot GPR:$Src, 8)>;
743 defm t2UXTAB : T2I_bin_rrot<"uxtab",
744 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
745 defm t2UXTAH : T2I_bin_rrot<"uxtah",
746 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
749 //===----------------------------------------------------------------------===//
750 // Arithmetic Instructions.
753 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
754 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
756 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
757 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
758 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
760 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
761 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
764 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
765 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
766 defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
768 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
769 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
770 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
771 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
772 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
775 //===----------------------------------------------------------------------===//
776 // Shift and rotate Instructions.
779 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
780 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
781 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
782 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
784 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
785 "mov", " $dst, $src, rrx",
786 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
788 //===----------------------------------------------------------------------===//
789 // Bitwise Instructions.
792 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
793 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
794 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
796 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
798 let Constraints = "$src = $dst" in
799 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
800 "bfc", " $dst, $imm",
801 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
803 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
805 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
807 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
808 let AddedComplexity = 1 in
809 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
812 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
813 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
815 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
816 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
818 def : T2Pat<(t2_so_imm_not:$src),
819 (t2MVNi t2_so_imm_not:$src)>;
821 //===----------------------------------------------------------------------===//
822 // Multiply Instructions.
824 let isCommutable = 1 in
825 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
826 "mul", " $dst, $a, $b",
827 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
829 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
830 "mla", " $dst, $a, $b, $c",
831 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
833 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
834 "mls", " $dst, $a, $b, $c",
835 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
837 // Extra precision multiplies with low / high results
838 let neverHasSideEffects = 1 in {
839 let isCommutable = 1 in {
840 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
841 "smull", " $ldst, $hdst, $a, $b", []>;
843 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
844 "umull", " $ldst, $hdst, $a, $b", []>;
847 // Multiply + accumulate
848 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
849 "smlal", " $ldst, $hdst, $a, $b", []>;
851 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
852 "umlal", " $ldst, $hdst, $a, $b", []>;
854 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
855 "umaal", " $ldst, $hdst, $a, $b", []>;
856 } // neverHasSideEffects
858 // Most significant word multiply
859 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
860 "smmul", " $dst, $a, $b",
861 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
863 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
864 "smmla", " $dst, $a, $b, $c",
865 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
868 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
869 "smmls", " $dst, $a, $b, $c",
870 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
872 multiclass T2I_smul<string opc, PatFrag opnode> {
873 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
874 !strconcat(opc, "bb"), " $dst, $a, $b",
875 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
876 (sext_inreg GPR:$b, i16)))]>;
878 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
879 !strconcat(opc, "bt"), " $dst, $a, $b",
880 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
881 (sra GPR:$b, (i32 16))))]>;
883 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
884 !strconcat(opc, "tb"), " $dst, $a, $b",
885 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
886 (sext_inreg GPR:$b, i16)))]>;
888 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
889 !strconcat(opc, "tt"), " $dst, $a, $b",
890 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
891 (sra GPR:$b, (i32 16))))]>;
893 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
894 !strconcat(opc, "wb"), " $dst, $a, $b",
895 [(set GPR:$dst, (sra (opnode GPR:$a,
896 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
898 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
899 !strconcat(opc, "wt"), " $dst, $a, $b",
900 [(set GPR:$dst, (sra (opnode GPR:$a,
901 (sra GPR:$b, (i32 16))), (i32 16)))]>;
905 multiclass T2I_smla<string opc, PatFrag opnode> {
906 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
907 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
908 [(set GPR:$dst, (add GPR:$acc,
909 (opnode (sext_inreg GPR:$a, i16),
910 (sext_inreg GPR:$b, i16))))]>;
912 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
913 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
914 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
915 (sra GPR:$b, (i32 16)))))]>;
917 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
918 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
919 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
920 (sext_inreg GPR:$b, i16))))]>;
922 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
923 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
924 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
925 (sra GPR:$b, (i32 16)))))]>;
927 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
928 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
929 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
930 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
932 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
933 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
934 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
935 (sra GPR:$b, (i32 16))), (i32 16))))]>;
938 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
939 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
941 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
942 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
945 //===----------------------------------------------------------------------===//
946 // Misc. Arithmetic Instructions.
949 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
950 "clz", " $dst, $src",
951 [(set GPR:$dst, (ctlz GPR:$src))]>;
953 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
954 "rev", " $dst, $src",
955 [(set GPR:$dst, (bswap GPR:$src))]>;
957 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
958 "rev16", " $dst, $src",
960 (or (and (srl GPR:$src, (i32 8)), 0xFF),
961 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
962 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
963 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
965 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
966 "revsh", " $dst, $src",
969 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
970 (shl GPR:$src, (i32 8))), i16))]>;
972 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
973 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
974 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
975 (and (shl GPR:$src2, (i32 imm:$shamt)),
978 // Alternate cases for PKHBT where identities eliminate some nodes.
979 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
980 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
981 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
982 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
984 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
985 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
986 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
987 (and (sra GPR:$src2, imm16_31:$shamt),
990 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
991 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
992 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
993 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
994 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
995 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
996 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
998 //===----------------------------------------------------------------------===//
999 // Comparison Instructions...
1002 defm t2CMP : T2I_cmp_is<"cmp",
1003 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1004 defm t2CMPz : T2I_cmp_is<"cmp",
1005 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1007 defm t2CMN : T2I_cmp_is<"cmn",
1008 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1009 defm t2CMNz : T2I_cmp_is<"cmn",
1010 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1012 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
1013 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1015 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1016 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1018 defm t2TST : T2I_cmp_is<"tst",
1019 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1020 defm t2TEQ : T2I_cmp_is<"teq",
1021 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1023 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1024 // Short range conditional branch. Looks awesome for loops. Need to figure
1025 // out how to use this one.
1028 // Conditional moves
1029 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1030 // a two-value operand where a dag node expects two operands. :(
1031 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
1032 "mov", " $dst, $true",
1033 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1034 RegConstraint<"$false = $dst">;
1036 def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true),
1037 "mov", " $dst, $true",
1038 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1039 RegConstraint<"$false = $dst">;
1041 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
1042 "mov", " $dst, $true",
1043 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1044 RegConstraint<"$false = $dst">;
1046 //===----------------------------------------------------------------------===//
1050 // __aeabi_read_tp preserves the registers r1-r3.
1052 Defs = [R0, R12, LR, CPSR] in {
1053 def t2TPsoft : T2XI<(outs), (ins),
1054 "bl __aeabi_read_tp",
1055 [(set R0, ARMthread_pointer)]>;
1058 //===----------------------------------------------------------------------===//
1059 // Control-Flow Instructions
1062 // FIXME: remove when we have a way to marking a MI with these properties.
1063 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1065 // FIXME: Should pc be an implicit operand like PICADD, etc?
1066 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1067 def t2LDM_RET : T2XI<(outs),
1068 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1069 "ldm${addr:submode}${p} $addr, $dst1",
1072 // On non-Darwin platforms R9 is callee-saved.
1074 Defs = [R0, R1, R2, R3, R12, LR,
1075 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1076 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1078 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1080 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1082 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1085 // On Darwin R9 is call-clobbered.
1087 Defs = [R0, R1, R2, R3, R9, R12, LR,
1088 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1089 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1091 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1093 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1095 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1098 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1099 let isPredicable = 1 in
1100 def t2B : T2XI<(outs), (ins brtarget:$target),
1104 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1105 def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1106 "mov pc, $target \n$jt",
1107 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1111 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
1112 "ldr pc, $target \n$jt",
1113 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
1118 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1119 "add pc, $target, $idx \n$jt",
1120 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
1121 } // isNotDuplicate, isIndirectBranch
1122 } // isBranch, isTerminator, isBarrier
1124 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1125 // a two-value operand where a dag node expects two operands. :(
1126 let isBranch = 1, isTerminator = 1 in
1127 def t2Bcc : T2I<(outs), (ins brtarget:$target),
1129 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1133 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1134 AddrModeNone, Size2Bytes,
1135 "it$mask $cc", "", []>;
1137 //===----------------------------------------------------------------------===//
1138 // Non-Instruction Patterns
1141 // ConstantPool, GlobalAddress, and JumpTable
1142 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1143 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1144 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1145 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1147 // Large immediate handling.
1149 def : T2Pat<(i32 imm:$src),
1150 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;