1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Scaled 4 immediate.
70 def t_imm_s4 : Operand<i32> {
71 let PrintMethod = "printThumbS4ImmOperand";
74 // Define Thumb specific addressing modes.
76 // t_addrmode_rr := reg + reg
78 def t_addrmode_rr : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
80 let PrintMethod = "printThumbAddrModeRROperand";
81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
84 // t_addrmode_s4 := reg + reg
87 def t_addrmode_s4 : Operand<i32>,
88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
89 let PrintMethod = "printThumbAddrModeS4Operand";
90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
93 // t_addrmode_s2 := reg + reg
96 def t_addrmode_s2 : Operand<i32>,
97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
98 let PrintMethod = "printThumbAddrModeS2Operand";
99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
102 // t_addrmode_s1 := reg + reg
105 def t_addrmode_s1 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
107 let PrintMethod = "printThumbAddrModeS1Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
111 // t_addrmode_sp := sp + imm8 * 4
113 def t_addrmode_sp : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
115 let PrintMethod = "printThumbAddrModeSPOperand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions.
123 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
124 // from removing one half of the matched pairs. That breaks PEI, which assumes
125 // these will always be in pairs, and asserts if it finds otherwise. Better way?
126 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
127 def tADJCALLSTACKUP :
128 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
129 "@ tADJCALLSTACKUP $amt1",
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
132 def tADJCALLSTACKDOWN :
133 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
134 "@ tADJCALLSTACKDOWN $amt",
135 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
138 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
139 [/* For disassembly only; pattern left blank */]>,
140 T1Encoding<0b101111> {
141 let Inst{9-8} = 0b11;
142 let Inst{7-0} = 0b00000000;
145 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
146 [/* For disassembly only; pattern left blank */]>,
147 T1Encoding<0b101111> {
148 let Inst{9-8} = 0b11;
149 let Inst{7-0} = 0b00010000;
152 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
153 [/* For disassembly only; pattern left blank */]>,
154 T1Encoding<0b101111> {
155 let Inst{9-8} = 0b11;
156 let Inst{7-0} = 0b00100000;
159 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
160 [/* For disassembly only; pattern left blank */]>,
161 T1Encoding<0b101111> {
162 let Inst{9-8} = 0b11;
163 let Inst{7-0} = 0b00110000;
166 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
167 [/* For disassembly only; pattern left blank */]>,
168 T1Encoding<0b101111> {
169 let Inst{9-8} = 0b11;
170 let Inst{7-0} = 0b01000000;
173 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
174 [/* For disassembly only; pattern left blank */]>,
175 T1Encoding<0b101101> {
176 let Inst{9-5} = 0b10010;
180 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
181 [/* For disassembly only; pattern left blank */]>,
182 T1Encoding<0b101101> {
183 let Inst{9-5} = 0b10010;
187 // The i32imm operand $val can be used by a debugger to store more information
188 // about the breakpoint.
189 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
190 [/* For disassembly only; pattern left blank */]>,
191 T1Encoding<0b101111> {
192 let Inst{9-8} = 0b10;
195 // Change Processor State is a system instruction -- for disassembly only.
196 // The singleton $opt operand contains the following information:
197 // opt{4-0} = mode ==> don't care
198 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
199 // opt{8-6} = AIF from Inst{2-0}
200 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
202 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
203 // CPS which has more options.
204 def tCPS : T1I<(outs), (ins i32imm:$opt), NoItinerary, "cps${opt:cps}",
205 [/* For disassembly only; pattern left blank */]>,
208 // For both thumb1 and thumb2.
209 let isNotDuplicable = 1 in
210 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
211 "\n$cp:\n\tadd\t$dst, pc",
212 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
213 T1Special<{0,0,?,?}> {
214 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
218 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
219 "add\t$dst, pc, $rhs", []>,
220 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
223 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
224 "add\t$dst, $sp, $rhs", []>,
225 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
228 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
229 "add\t$dst, $rhs", []>,
230 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
233 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
234 "sub\t$dst, $rhs", []>,
235 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
238 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
239 "add\t$dst, $rhs", []>,
240 T1Special<{0,0,?,?}> {
241 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
245 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
246 "add\t$dst, $rhs", []>,
247 T1Special<{0,0,?,?}> {
248 // A8.6.9 Encoding T2
250 let Inst{2-0} = 0b101;
253 // Pseudo instruction that will expand into a tSUBspi + a copy.
254 let usesCustomInserter = 1 in { // Expanded after instruction selection.
255 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
256 NoItinerary, "@ sub\t$dst, $rhs", []>;
258 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
259 NoItinerary, "@ add\t$dst, $rhs", []>;
262 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
263 NoItinerary, "@ and\t$dst, $rhs", []>;
264 } // usesCustomInserter
266 //===----------------------------------------------------------------------===//
267 // Control Flow Instructions.
270 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
271 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
272 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
273 let Inst{6-3} = 0b1110; // Rm = lr
275 // Alternative return instruction used by vararg functions.
276 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
277 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
281 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
282 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
284 T1Special<{1,0,1,?}> {
285 // <Rd> = Inst{7:2-0} = pc
286 let Inst{2-0} = 0b111;
290 // FIXME: remove when we have a way to marking a MI with these properties.
291 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
292 hasExtraDefRegAllocReq = 1 in
293 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
295 T1Misc<{1,1,0,?,?,?,?}>;
298 Defs = [R0, R1, R2, R3, R12, LR,
299 D0, D1, D2, D3, D4, D5, D6, D7,
300 D16, D17, D18, D19, D20, D21, D22, D23,
301 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
302 // Also used for Thumb2
303 def tBL : TIx2<0b11110, 0b11, 1,
304 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
306 [(ARMtcall tglobaladdr:$func)]>,
307 Requires<[IsThumb, IsNotDarwin]>;
309 // ARMv5T and above, also used for Thumb2
310 def tBLXi : TIx2<0b11110, 0b11, 0,
311 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
313 [(ARMcall tglobaladdr:$func)]>,
314 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
316 // Also used for Thumb2
317 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
319 [(ARMtcall GPR:$func)]>,
320 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
321 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
324 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
325 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
326 "mov\tlr, pc\n\tbx\t$func",
327 [(ARMcall_nolink tGPR:$func)]>,
328 Requires<[IsThumb1Only, IsNotDarwin]>;
331 // On Darwin R9 is call-clobbered.
333 Defs = [R0, R1, R2, R3, R9, R12, LR,
334 D0, D1, D2, D3, D4, D5, D6, D7,
335 D16, D17, D18, D19, D20, D21, D22, D23,
336 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
337 // Also used for Thumb2
338 def tBLr9 : TIx2<0b11110, 0b11, 1,
339 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
341 [(ARMtcall tglobaladdr:$func)]>,
342 Requires<[IsThumb, IsDarwin]>;
344 // ARMv5T and above, also used for Thumb2
345 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
346 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
348 [(ARMcall tglobaladdr:$func)]>,
349 Requires<[IsThumb, HasV5T, IsDarwin]>;
351 // Also used for Thumb2
352 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
354 [(ARMtcall GPR:$func)]>,
355 Requires<[IsThumb, HasV5T, IsDarwin]>,
356 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
359 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
360 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
361 "mov\tlr, pc\n\tbx\t$func",
362 [(ARMcall_nolink tGPR:$func)]>,
363 Requires<[IsThumb1Only, IsDarwin]>;
366 let isBranch = 1, isTerminator = 1 in {
367 let isBarrier = 1 in {
368 let isPredicable = 1 in
369 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
370 "b\t$target", [(br bb:$target)]>,
371 T1Encoding<{1,1,1,0,0,?}>;
375 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
376 "bl\t$target\t@ far jump",[]>;
378 def tBR_JTr : T1JTI<(outs),
379 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
380 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
381 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
383 let Inst{15-7} = 0b010001101;
384 let Inst{2-0} = 0b111;
389 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
390 // a two-value operand where a dag node expects two operands. :(
391 let isBranch = 1, isTerminator = 1 in
392 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
394 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
395 T1Encoding<{1,1,0,1,?,?}>;
397 // Compare and branch on zero / non-zero
398 let isBranch = 1, isTerminator = 1 in {
399 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
400 "cbz\t$cmp, $target", []>,
401 T1Misc<{0,0,?,1,?,?,?}>;
403 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
404 "cbnz\t$cmp, $target", []>,
405 T1Misc<{1,0,?,1,?,?,?}>;
408 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
409 // A8.6.16 B: Encoding T1
410 // If Inst{11-8} == 0b1111 then SEE SVC
412 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
414 let Inst{15-12} = 0b1101;
415 let Inst{11-8} = 0b1111;
419 // A8.6.16 B: Encoding T1 -- for disassembly only
420 // If Inst{11-8} == 0b1110 then UNDEFINED
421 def tTRAP : T1I<(outs), (ins), IIC_Br, "trap", []>, Encoding16 {
422 let Inst{15-12} = 0b1101;
423 let Inst{11-8} = 0b1110;
426 //===----------------------------------------------------------------------===//
427 // Load Store Instructions.
430 let canFoldAsLoad = 1, isReMaterializable = 1 in
431 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
432 "ldr", "\t$dst, $addr",
433 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
435 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
436 "ldr", "\t$dst, $addr",
440 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
441 "ldrb", "\t$dst, $addr",
442 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
444 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
445 "ldrb", "\t$dst, $addr",
449 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
450 "ldrh", "\t$dst, $addr",
451 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
453 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
454 "ldrh", "\t$dst, $addr",
458 let AddedComplexity = 10 in
459 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
460 "ldrsb", "\t$dst, $addr",
461 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
464 let AddedComplexity = 10 in
465 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
466 "ldrsh", "\t$dst, $addr",
467 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
470 let canFoldAsLoad = 1 in
471 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
472 "ldr", "\t$dst, $addr",
473 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
476 // Special instruction for restore. It cannot clobber condition register
477 // when it's expanded by eliminateCallFramePseudoInstr().
478 let canFoldAsLoad = 1, mayLoad = 1 in
479 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
480 "ldr", "\t$dst, $addr", []>,
484 // FIXME: Use ldr.n to work around a Darwin assembler bug.
485 let canFoldAsLoad = 1, isReMaterializable = 1 in
486 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
487 "ldr", ".n\t$dst, $addr",
488 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
489 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
491 // Special LDR for loads from non-pc-relative constpools.
492 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
493 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
494 "ldr", "\t$dst, $addr", []>,
497 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
498 "str", "\t$src, $addr",
499 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
501 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
502 "str", "\t$src, $addr",
506 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
507 "strb", "\t$src, $addr",
508 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
510 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
511 "strb", "\t$src, $addr",
515 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
516 "strh", "\t$src, $addr",
517 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
519 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
520 "strh", "\t$src, $addr",
524 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
525 "str", "\t$src, $addr",
526 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
529 let mayStore = 1 in {
530 // Special instruction for spill. It cannot clobber condition register
531 // when it's expanded by eliminateCallFramePseudoInstr().
532 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
533 "str", "\t$src, $addr", []>,
537 //===----------------------------------------------------------------------===//
538 // Load / store multiple Instructions.
541 // These requires base address to be written back or one of the loaded regs.
542 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
543 def tLDM : T1I<(outs),
544 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
546 "ldm${addr:submode}${p}\t$addr, $wb", []>,
547 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
549 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
550 def tSTM : T1I<(outs),
551 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
553 "stm${addr:submode}${p}\t$addr, $wb", []>,
554 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
556 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
557 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
559 T1Misc<{1,1,0,?,?,?,?}>;
561 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
562 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
563 "push${p}\t$wb", []>,
564 T1Misc<{0,1,0,?,?,?,?}>;
566 //===----------------------------------------------------------------------===//
567 // Arithmetic Instructions.
570 // Add with carry register
571 let isCommutable = 1, Uses = [CPSR] in
572 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
573 "adc", "\t$dst, $rhs",
574 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
575 T1DataProcessing<0b0101>;
578 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
579 "add", "\t$dst, $lhs, $rhs",
580 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
583 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
584 "add", "\t$dst, $rhs",
585 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
586 T1General<{1,1,0,?,?}>;
589 let isCommutable = 1 in
590 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
591 "add", "\t$dst, $lhs, $rhs",
592 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
595 let neverHasSideEffects = 1 in
596 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
597 "add", "\t$dst, $rhs", []>,
598 T1Special<{0,0,?,?}>;
601 let isCommutable = 1 in
602 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
603 "and", "\t$dst, $rhs",
604 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
605 T1DataProcessing<0b0000>;
608 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
609 "asr", "\t$dst, $lhs, $rhs",
610 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
611 T1General<{0,1,0,?,?}>;
614 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
615 "asr", "\t$dst, $rhs",
616 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
617 T1DataProcessing<0b0100>;
620 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
621 "bic", "\t$dst, $rhs",
622 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
623 T1DataProcessing<0b1110>;
626 let Defs = [CPSR] in {
627 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
628 // Compare-to-zero still works out, just not the relationals
629 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
630 // "cmn", "\t$lhs, $rhs",
631 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
632 // T1DataProcessing<0b1011>;
633 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
634 "cmn", "\t$lhs, $rhs",
635 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
636 T1DataProcessing<0b1011>;
640 let Defs = [CPSR] in {
641 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
642 "cmp", "\t$lhs, $rhs",
643 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
644 T1General<{1,0,1,?,?}>;
645 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
646 "cmp", "\t$lhs, $rhs",
647 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
648 T1General<{1,0,1,?,?}>;
652 let Defs = [CPSR] in {
653 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
654 "cmp", "\t$lhs, $rhs",
655 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
656 T1DataProcessing<0b1010>;
657 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
658 "cmp", "\t$lhs, $rhs",
659 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
660 T1DataProcessing<0b1010>;
662 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
663 "cmp", "\t$lhs, $rhs", []>,
664 T1Special<{0,1,?,?}>;
665 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
666 "cmp", "\t$lhs, $rhs", []>,
667 T1Special<{0,1,?,?}>;
672 let isCommutable = 1 in
673 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
674 "eor", "\t$dst, $rhs",
675 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
676 T1DataProcessing<0b0001>;
679 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
680 "lsl", "\t$dst, $lhs, $rhs",
681 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
682 T1General<{0,0,0,?,?}>;
685 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
686 "lsl", "\t$dst, $rhs",
687 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
688 T1DataProcessing<0b0010>;
691 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
692 "lsr", "\t$dst, $lhs, $rhs",
693 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
694 T1General<{0,0,1,?,?}>;
697 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
698 "lsr", "\t$dst, $rhs",
699 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
700 T1DataProcessing<0b0011>;
703 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
704 "mov", "\t$dst, $src",
705 [(set tGPR:$dst, imm0_255:$src)]>,
706 T1General<{1,0,0,?,?}>;
708 // TODO: A7-73: MOV(2) - mov setting flag.
711 let neverHasSideEffects = 1 in {
712 // FIXME: Make this predicable.
713 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
714 "mov\t$dst, $src", []>,
717 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
718 "movs\t$dst, $src", []>, Encoding16 {
719 let Inst{15-6} = 0b0000000000;
722 // FIXME: Make these predicable.
723 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
724 "mov\t$dst, $src", []>,
725 T1Special<{1,0,0,?}>;
726 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
727 "mov\t$dst, $src", []>,
728 T1Special<{1,0,?,0}>;
729 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
730 "mov\t$dst, $src", []>,
731 T1Special<{1,0,?,?}>;
732 } // neverHasSideEffects
735 let isCommutable = 1 in
736 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
737 "mul", "\t$dst, $rhs",
738 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
739 T1DataProcessing<0b1101>;
741 // move inverse register
742 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
743 "mvn", "\t$dst, $src",
744 [(set tGPR:$dst, (not tGPR:$src))]>,
745 T1DataProcessing<0b1111>;
747 // bitwise or register
748 let isCommutable = 1 in
749 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
750 "orr", "\t$dst, $rhs",
751 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
752 T1DataProcessing<0b1100>;
755 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
756 "rev", "\t$dst, $src",
757 [(set tGPR:$dst, (bswap tGPR:$src))]>,
758 Requires<[IsThumb1Only, HasV6]>,
759 T1Misc<{1,0,1,0,0,0,?}>;
761 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
762 "rev16", "\t$dst, $src",
764 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
765 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
766 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
767 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
768 Requires<[IsThumb1Only, HasV6]>,
769 T1Misc<{1,0,1,0,0,1,?}>;
771 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
772 "revsh", "\t$dst, $src",
775 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
776 (shl tGPR:$src, (i32 8))), i16))]>,
777 Requires<[IsThumb1Only, HasV6]>,
778 T1Misc<{1,0,1,0,1,1,?}>;
780 // rotate right register
781 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
782 "ror", "\t$dst, $rhs",
783 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
784 T1DataProcessing<0b0111>;
787 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
788 "rsb", "\t$dst, $src, #0",
789 [(set tGPR:$dst, (ineg tGPR:$src))]>,
790 T1DataProcessing<0b1001>;
792 // Subtract with carry register
794 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
795 "sbc", "\t$dst, $rhs",
796 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
797 T1DataProcessing<0b0110>;
799 // Subtract immediate
800 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
801 "sub", "\t$dst, $lhs, $rhs",
802 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
805 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
806 "sub", "\t$dst, $rhs",
807 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
808 T1General<{1,1,1,?,?}>;
811 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
812 "sub", "\t$dst, $lhs, $rhs",
813 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
816 // TODO: A7-96: STMIA - store multiple.
819 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
820 "sxtb", "\t$dst, $src",
821 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
822 Requires<[IsThumb1Only, HasV6]>,
823 T1Misc<{0,0,1,0,0,1,?}>;
826 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
827 "sxth", "\t$dst, $src",
828 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
829 Requires<[IsThumb1Only, HasV6]>,
830 T1Misc<{0,0,1,0,0,0,?}>;
833 let isCommutable = 1, Defs = [CPSR] in
834 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
835 "tst", "\t$lhs, $rhs",
836 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
837 T1DataProcessing<0b1000>;
840 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
841 "uxtb", "\t$dst, $src",
842 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
843 Requires<[IsThumb1Only, HasV6]>,
844 T1Misc<{0,0,1,0,1,1,?}>;
847 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
848 "uxth", "\t$dst, $src",
849 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
850 Requires<[IsThumb1Only, HasV6]>,
851 T1Misc<{0,0,1,0,1,0,?}>;
854 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
855 // Expanded after instruction selection into a branch sequence.
856 let usesCustomInserter = 1 in // Expanded after instruction selection.
858 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
859 NoItinerary, "@ tMOVCCr $cc",
860 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
863 // 16-bit movcc in IT blocks for Thumb2.
864 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
865 "mov", "\t$dst, $rhs", []>,
866 T1Special<{1,0,?,?}>;
868 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
869 "mov", "\t$dst, $rhs", []>,
870 T1General<{1,0,0,?,?}>;
872 // tLEApcrel - Load a pc-relative address into a register without offending the
874 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
875 "adr$p\t$dst, #$label", []>,
876 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
878 def tLEApcrelJT : T1I<(outs tGPR:$dst),
879 (ins i32imm:$label, nohash_imm:$id, pred:$p),
880 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
881 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
883 //===----------------------------------------------------------------------===//
887 // __aeabi_read_tp preserves the registers r1-r3.
890 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
891 "bl\t__aeabi_read_tp",
892 [(set R0, ARMthread_pointer)]>;
895 // SJLJ Exception handling intrinsics
896 // eh_sjlj_setjmp() is an instruction sequence to store the return
897 // address and save #0 in R0 for the non-longjmp case.
898 // Since by its nature we may be coming from some other function to get
899 // here, and we're using the stack frame for the containing function to
900 // save/restore registers, we can't keep anything live in regs across
901 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
902 // when we get here from a longjmp(). We force everthing out of registers
903 // except for our own input by listing the relevant registers in Defs. By
904 // doing so, we also cause the prologue/epilogue code to actively preserve
905 // all of the callee-saved resgisters, which is exactly what we want.
906 // The current SP is passed in $val, and we reuse the reg as a scratch.
908 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
909 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
910 AddrModeNone, SizeSpecial, NoItinerary,
911 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
914 "\tstr\t$val, [$src, #4]\n"
917 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
919 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
921 //===----------------------------------------------------------------------===//
922 // Non-Instruction Patterns
926 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
927 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
928 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
929 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
930 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
931 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
933 // Subtract with carry
934 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
935 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
936 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
937 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
938 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
939 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
941 // ConstantPool, GlobalAddress
942 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
943 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
946 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
947 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
950 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
951 Requires<[IsThumb, IsNotDarwin]>;
952 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
953 Requires<[IsThumb, IsDarwin]>;
955 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
956 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
957 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
958 Requires<[IsThumb, HasV5T, IsDarwin]>;
960 // Indirect calls to ARM routines
961 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
962 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
963 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
964 Requires<[IsThumb, HasV5T, IsDarwin]>;
966 // zextload i1 -> zextload i8
967 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
968 (tLDRB t_addrmode_s1:$addr)>;
970 // extload -> zextload
971 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
972 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
973 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
975 // If it's impossible to use [r,r] address mode for sextload, select to
976 // ldr{b|h} + sxt{b|h} instead.
977 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
978 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
979 Requires<[IsThumb1Only, HasV6]>;
980 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
981 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
982 Requires<[IsThumb1Only, HasV6]>;
984 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
985 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
986 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
987 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
989 // Large immediate handling.
992 def : T1Pat<(i32 thumb_immshifted:$src),
993 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
994 (thumb_immshifted_shamt imm:$src))>;
996 def : T1Pat<(i32 imm0_255_comp:$src),
997 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
999 // Pseudo instruction that combines ldr from constpool and add pc. This should
1000 // be expanded into two instructions late to allow if-conversion and
1002 let isReMaterializable = 1 in
1003 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1004 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
1005 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1007 Requires<[IsThumb1Only]>;