1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 def imm0_7_neg : PatLeaf<(i32 imm), [{
30 return (uint32_t)-N->getZExtValue() < 8;
33 def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
34 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
35 let ParserMatchClass = imm0_255_asmoperand;
37 def imm0_255_comp : PatLeaf<(i32 imm), [{
38 return ~((uint32_t)N->getZExtValue()) < 256;
41 def imm8_255 : ImmLeaf<i32, [{
42 return Imm >= 8 && Imm < 256;
44 def imm8_255_neg : PatLeaf<(i32 imm), [{
45 unsigned Val = -N->getZExtValue();
46 return Val >= 8 && Val < 256;
49 // Break imm's up into two pieces: an immediate + a left shift. This uses
50 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
51 // to get the val/shift pieces.
52 def thumb_immshifted : PatLeaf<(imm), [{
53 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
56 def thumb_immshifted_val : SDNodeXForm<imm, [{
57 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
58 return CurDAG->getTargetConstant(V, MVT::i32);
61 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
62 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
63 return CurDAG->getTargetConstant(V, MVT::i32);
66 // ADR instruction labels.
67 def t_adrlabel : Operand<i32> {
68 let EncoderMethod = "getThumbAdrLabelOpValue";
71 // Scaled 4 immediate.
72 def t_imm_s4 : Operand<i32> {
73 let PrintMethod = "printThumbS4ImmOperand";
76 // Define Thumb specific addressing modes.
78 def t_brtarget : Operand<OtherVT> {
79 let EncoderMethod = "getThumbBRTargetOpValue";
82 def t_bcctarget : Operand<i32> {
83 let EncoderMethod = "getThumbBCCTargetOpValue";
86 def t_cbtarget : Operand<i32> {
87 let EncoderMethod = "getThumbCBTargetOpValue";
90 def t_bltarget : Operand<i32> {
91 let EncoderMethod = "getThumbBLTargetOpValue";
94 def t_blxtarget : Operand<i32> {
95 let EncoderMethod = "getThumbBLXTargetOpValue";
98 def MemModeRegThumbAsmOperand : AsmOperandClass {
99 let Name = "MemModeRegThumb";
100 let SuperClasses = [];
103 def MemModeImmThumbAsmOperand : AsmOperandClass {
104 let Name = "MemModeImmThumb";
105 let SuperClasses = [];
108 // t_addrmode_rr := reg + reg
110 def t_addrmode_rr : Operand<i32>,
111 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
112 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
113 let PrintMethod = "printThumbAddrModeRROperand";
114 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
117 // t_addrmode_rrs := reg + reg
119 def t_addrmode_rrs1 : Operand<i32>,
120 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
121 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
122 let PrintMethod = "printThumbAddrModeRROperand";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
124 let ParserMatchClass = MemModeRegThumbAsmOperand;
126 def t_addrmode_rrs2 : Operand<i32>,
127 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
128 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
129 let PrintMethod = "printThumbAddrModeRROperand";
130 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
131 let ParserMatchClass = MemModeRegThumbAsmOperand;
133 def t_addrmode_rrs4 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
138 let ParserMatchClass = MemModeRegThumbAsmOperand;
141 // t_addrmode_is4 := reg + imm5 * 4
143 def t_addrmode_is4 : Operand<i32>,
144 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
145 let EncoderMethod = "getAddrModeISOpValue";
146 let PrintMethod = "printThumbAddrModeImm5S4Operand";
147 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
148 let ParserMatchClass = MemModeImmThumbAsmOperand;
151 // t_addrmode_is2 := reg + imm5 * 2
153 def t_addrmode_is2 : Operand<i32>,
154 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
155 let EncoderMethod = "getAddrModeISOpValue";
156 let PrintMethod = "printThumbAddrModeImm5S2Operand";
157 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
158 let ParserMatchClass = MemModeImmThumbAsmOperand;
161 // t_addrmode_is1 := reg + imm5
163 def t_addrmode_is1 : Operand<i32>,
164 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
165 let EncoderMethod = "getAddrModeISOpValue";
166 let PrintMethod = "printThumbAddrModeImm5S1Operand";
167 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
168 let ParserMatchClass = MemModeImmThumbAsmOperand;
171 // t_addrmode_sp := sp + imm8 * 4
173 def t_addrmode_sp : Operand<i32>,
174 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
175 let EncoderMethod = "getAddrModeThumbSPOpValue";
176 let PrintMethod = "printThumbAddrModeSPOperand";
177 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
178 let ParserMatchClass = MemModeImmThumbAsmOperand;
181 // t_addrmode_pc := <label> => pc + imm8 * 4
183 def t_addrmode_pc : Operand<i32> {
184 let EncoderMethod = "getAddrModePCOpValue";
185 let ParserMatchClass = MemModeImmThumbAsmOperand;
188 //===----------------------------------------------------------------------===//
189 // Miscellaneous Instructions.
192 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
193 // from removing one half of the matched pairs. That breaks PEI, which assumes
194 // these will always be in pairs, and asserts if it finds otherwise. Better way?
195 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
196 def tADJCALLSTACKUP :
197 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
198 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
199 Requires<[IsThumb, IsThumb1Only]>;
201 def tADJCALLSTACKDOWN :
202 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
203 [(ARMcallseq_start imm:$amt)]>,
204 Requires<[IsThumb, IsThumb1Only]>;
207 // T1Disassembly - A simple class to make encoding some disassembly patterns
208 // easier and less verbose.
209 class T1Disassembly<bits<2> op1, bits<8> op2>
210 : T1Encoding<0b101111> {
215 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
216 [/* For disassembly only; pattern left blank */]>,
217 T1Disassembly<0b11, 0x00>; // A8.6.110
219 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
220 [/* For disassembly only; pattern left blank */]>,
221 T1Disassembly<0b11, 0x10>; // A8.6.410
223 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
224 [/* For disassembly only; pattern left blank */]>,
225 T1Disassembly<0b11, 0x20>; // A8.6.408
227 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
228 [/* For disassembly only; pattern left blank */]>,
229 T1Disassembly<0b11, 0x30>; // A8.6.409
231 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
232 [/* For disassembly only; pattern left blank */]>,
233 T1Disassembly<0b11, 0x40>; // A8.6.157
235 // The i32imm operand $val can be used by a debugger to store more information
236 // about the breakpoint.
237 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
238 [/* For disassembly only; pattern left blank */]>,
239 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
245 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
246 [/* For disassembly only; pattern left blank */]>,
247 T1Encoding<0b101101> {
249 let Inst{9-5} = 0b10010;
251 let Inst{3} = 1; // Big-Endian
252 let Inst{2-0} = 0b000;
255 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
256 [/* For disassembly only; pattern left blank */]>,
257 T1Encoding<0b101101> {
259 let Inst{9-5} = 0b10010;
261 let Inst{3} = 0; // Little-Endian
262 let Inst{2-0} = 0b000;
265 // Change Processor State is a system instruction -- for disassembly only.
266 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
267 NoItinerary, "cps$imod $iflags",
268 [/* For disassembly only; pattern left blank */]>,
276 let Inst{2-0} = iflags;
279 // For both thumb1 and thumb2.
280 let isNotDuplicable = 1, isCodeGenOnly = 1 in
281 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
282 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
283 T1Special<{0,0,?,?}> {
286 let Inst{6-3} = 0b1111; // Rm = pc
290 // PC relative add (ADR).
291 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
292 "add\t$dst, pc, $rhs", []>,
293 T1Encoding<{1,0,1,0,0,?}> {
297 let Inst{10-8} = dst;
301 // ADD <Rd>, sp, #<imm8>
302 // This is rematerializable, which is particularly useful for taking the
303 // address of locals.
304 let isReMaterializable = 1 in
305 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
306 "add\t$dst, $sp, $rhs", []>,
307 T1Encoding<{1,0,1,0,1,?}> {
311 let Inst{10-8} = dst;
315 // ADD sp, sp, #<imm7>
316 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
317 "add\t$dst, $rhs", []>,
318 T1Misc<{0,0,0,0,0,?,?}> {
324 // SUB sp, sp, #<imm7>
325 // FIXME: The encoding and the ASM string don't match up.
326 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
327 "sub\t$dst, $rhs", []>,
328 T1Misc<{0,0,0,0,1,?,?}> {
335 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
336 "add\t$dst, $rhs", []>,
337 T1Special<{0,0,?,?}> {
338 // A8.6.9 Encoding T1
340 let Inst{7} = dst{3};
341 let Inst{6-3} = 0b1101;
342 let Inst{2-0} = dst{2-0};
346 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
347 "add\t$dst, $rhs", []>,
348 T1Special<{0,0,?,?}> {
349 // A8.6.9 Encoding T2
353 let Inst{2-0} = 0b101;
356 //===----------------------------------------------------------------------===//
357 // Control Flow Instructions.
361 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
362 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
363 T1Special<{1,1,0,?}> {
367 let Inst{2-0} = 0b000;
371 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
372 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br,
373 [(ARMretflag)], (tBX LR, pred:$p)>;
375 // Alternative return instruction used by vararg functions.
376 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
377 Size2Bytes, IIC_Br, [],
378 (tBX GPR:$Rm, pred:$p)>;
381 // All calls clobber the non-callee saved registers. SP is marked as a use to
382 // prevent stack-pointer assignments that appear immediately before calls from
383 // potentially appearing dead.
385 // On non-Darwin platforms R9 is callee-saved.
386 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
388 // Also used for Thumb2
389 def tBL : TIx2<0b11110, 0b11, 1,
390 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
392 [(ARMtcall tglobaladdr:$func)]>,
393 Requires<[IsThumb, IsNotDarwin]> {
395 let Inst{25-16} = func{20-11};
398 let Inst{10-0} = func{10-0};
401 // ARMv5T and above, also used for Thumb2
402 def tBLXi : TIx2<0b11110, 0b11, 0,
403 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
405 [(ARMcall tglobaladdr:$func)]>,
406 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
408 let Inst{25-16} = func{20-11};
411 let Inst{10-1} = func{10-1};
412 let Inst{0} = 0; // func{0} is assumed zero
415 // Also used for Thumb2
416 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
418 [(ARMtcall GPR:$func)]>,
419 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
420 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
422 let Inst{6-3} = func;
423 let Inst{2-0} = 0b000;
427 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
429 [(ARMcall_nolink tGPR:$func)]>,
430 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
434 // On Darwin R9 is call-clobbered.
435 // R7 is marked as a use to prevent frame-pointer assignments from being
436 // moved above / below calls.
437 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
439 // Also used for Thumb2
440 def tBLr9 : TIx2<0b11110, 0b11, 1,
441 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
442 IIC_Br, "bl${p}\t$func",
443 [(ARMtcall tglobaladdr:$func)]>,
444 Requires<[IsThumb, IsDarwin]> {
446 let Inst{25-16} = func{20-11};
449 let Inst{10-0} = func{10-0};
452 // ARMv5T and above, also used for Thumb2
453 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
454 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
455 IIC_Br, "blx${p}\t$func",
456 [(ARMcall tglobaladdr:$func)]>,
457 Requires<[IsThumb, HasV5T, IsDarwin]> {
459 let Inst{25-16} = func{20-11};
462 let Inst{10-1} = func{10-1};
463 let Inst{0} = 0; // func{0} is assumed zero
466 // Also used for Thumb2
467 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
469 [(ARMtcall GPR:$func)]>,
470 Requires<[IsThumb, HasV5T, IsDarwin]>,
471 T1Special<{1,1,1,?}> {
474 let Inst{6-3} = func;
475 let Inst{2-0} = 0b000;
479 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
481 [(ARMcall_nolink tGPR:$func)]>,
482 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
485 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
486 let isPredicable = 1 in
487 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
488 "b\t$target", [(br bb:$target)]>,
489 T1Encoding<{1,1,1,0,0,?}> {
491 let Inst{10-0} = target;
495 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
496 // the clobber of LR.
498 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target),
499 Size4Bytes, IIC_Br, [], (tBL t_bltarget:$target)>;
501 def tBR_JTr : tPseudoInst<(outs),
502 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
504 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
505 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
509 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
510 // a two-value operand where a dag node expects two operands. :(
511 let isBranch = 1, isTerminator = 1 in
512 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
514 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
515 T1BranchCond<{1,1,0,1}> {
519 let Inst{7-0} = target;
522 // Compare and branch on zero / non-zero
523 let isBranch = 1, isTerminator = 1 in {
524 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
525 "cbz\t$Rn, $target", []>,
526 T1Misc<{0,0,?,1,?,?,?}> {
530 let Inst{9} = target{5};
531 let Inst{7-3} = target{4-0};
535 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
536 "cbnz\t$cmp, $target", []>,
537 T1Misc<{1,0,?,1,?,?,?}> {
541 let Inst{9} = target{5};
542 let Inst{7-3} = target{4-0};
548 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
550 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
552 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
553 // on Darwin), so it's in ARMInstrThumb2.td.
554 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
555 Size4Bytes, IIC_Br, [],
556 (tBX GPR:$dst, (ops 14, zero_reg))>,
557 Requires<[IsThumb, IsDarwin]>;
559 // Non-Darwin versions (the difference is R9).
560 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
562 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
563 Size4Bytes, IIC_Br, [],
564 (tB t_brtarget:$dst)>,
565 Requires<[IsThumb, IsNotDarwin]>;
566 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
567 Size4Bytes, IIC_Br, [],
568 (tBX GPR:$dst, (ops 14, zero_reg))>,
569 Requires<[IsThumb, IsNotDarwin]>;
574 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
575 // A8.6.16 B: Encoding T1
576 // If Inst{11-8} == 0b1111 then SEE SVC
577 let isCall = 1, Uses = [SP] in
578 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
579 "svc", "\t$imm", []>, Encoding16 {
581 let Inst{15-12} = 0b1101;
582 let Inst{11-8} = 0b1111;
586 // The assembler uses 0xDEFE for a trap instruction.
587 let isBarrier = 1, isTerminator = 1 in
588 def tTRAP : TI<(outs), (ins), IIC_Br,
589 "trap", [(trap)]>, Encoding16 {
593 //===----------------------------------------------------------------------===//
594 // Load Store Instructions.
597 // Loads: reg/reg and reg/imm5
598 let canFoldAsLoad = 1, isReMaterializable = 1 in
599 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
600 Operand AddrMode_r, Operand AddrMode_i,
601 AddrMode am, InstrItinClass itin_r,
602 InstrItinClass itin_i, string asm,
605 T1pILdStEncode<reg_opc,
606 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
607 am, itin_r, asm, "\t$Rt, $addr",
608 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
610 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
611 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
612 am, itin_i, asm, "\t$Rt, $addr",
613 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
615 // Stores: reg/reg and reg/imm5
616 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
617 Operand AddrMode_r, Operand AddrMode_i,
618 AddrMode am, InstrItinClass itin_r,
619 InstrItinClass itin_i, string asm,
622 T1pILdStEncode<reg_opc,
623 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
624 am, itin_r, asm, "\t$Rt, $addr",
625 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
627 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
628 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
629 am, itin_i, asm, "\t$Rt, $addr",
630 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
634 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
635 t_addrmode_is4, AddrModeT1_4,
636 IIC_iLoad_r, IIC_iLoad_i, "ldr",
637 UnOpFrag<(load node:$Src)>>;
640 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
641 t_addrmode_is1, AddrModeT1_1,
642 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
643 UnOpFrag<(zextloadi8 node:$Src)>>;
646 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
647 t_addrmode_is2, AddrModeT1_2,
648 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
649 UnOpFrag<(zextloadi16 node:$Src)>>;
651 let AddedComplexity = 10 in
652 def tLDRSB : // A8.6.80
653 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
654 AddrModeT1_1, IIC_iLoad_bh_r,
655 "ldrsb", "\t$dst, $addr",
656 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
658 let AddedComplexity = 10 in
659 def tLDRSH : // A8.6.84
660 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
661 AddrModeT1_2, IIC_iLoad_bh_r,
662 "ldrsh", "\t$dst, $addr",
663 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
665 let canFoldAsLoad = 1 in
666 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
667 "ldr", "\t$Rt, $addr",
668 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
673 let Inst{7-0} = addr;
677 // FIXME: Use ldr.n to work around a Darwin assembler bug.
678 let canFoldAsLoad = 1, isReMaterializable = 1 in
679 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
680 "ldr", ".n\t$Rt, $addr",
681 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
682 T1Encoding<{0,1,0,0,1,?}> {
687 let Inst{7-0} = addr;
690 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
691 // For disassembly use only.
692 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
693 "ldr", "\t$Rt, $addr",
694 [/* disassembly only */]>,
695 T1Encoding<{0,1,0,0,1,?}> {
700 let Inst{7-0} = addr;
703 // A8.6.194 & A8.6.192
704 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
705 t_addrmode_is4, AddrModeT1_4,
706 IIC_iStore_r, IIC_iStore_i, "str",
707 BinOpFrag<(store node:$LHS, node:$RHS)>>;
709 // A8.6.197 & A8.6.195
710 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
711 t_addrmode_is1, AddrModeT1_1,
712 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
713 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
715 // A8.6.207 & A8.6.205
716 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
717 t_addrmode_is2, AddrModeT1_2,
718 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
719 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
722 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
723 "str", "\t$Rt, $addr",
724 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
729 let Inst{7-0} = addr;
732 //===----------------------------------------------------------------------===//
733 // Load / store multiple Instructions.
736 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
737 InstrItinClass itin_upd, bits<6> T1Enc,
740 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
741 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
746 let Inst{7-0} = regs;
749 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
750 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
755 let Inst{7-0} = regs;
759 // These require base address to be written back or one of the loaded regs.
760 let neverHasSideEffects = 1 in {
762 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
763 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
766 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
767 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
770 } // neverHasSideEffects
772 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
773 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
775 "pop${p}\t$regs", []>,
776 T1Misc<{1,1,0,?,?,?,?}> {
778 let Inst{8} = regs{15};
779 let Inst{7-0} = regs{7-0};
782 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
783 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
785 "push${p}\t$regs", []>,
786 T1Misc<{0,1,0,?,?,?,?}> {
788 let Inst{8} = regs{14};
789 let Inst{7-0} = regs{7-0};
792 //===----------------------------------------------------------------------===//
793 // Arithmetic Instructions.
796 // Helper classes for encoding T1pI patterns:
797 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
798 string opc, string asm, list<dag> pattern>
799 : T1pI<oops, iops, itin, opc, asm, pattern>,
800 T1DataProcessing<opA> {
806 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
807 string opc, string asm, list<dag> pattern>
808 : T1pI<oops, iops, itin, opc, asm, pattern>,
816 // Helper classes for encoding T1sI patterns:
817 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
818 string opc, string asm, list<dag> pattern>
819 : T1sI<oops, iops, itin, opc, asm, pattern>,
820 T1DataProcessing<opA> {
826 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
827 string opc, string asm, list<dag> pattern>
828 : T1sI<oops, iops, itin, opc, asm, pattern>,
837 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
838 string opc, string asm, list<dag> pattern>
839 : T1sI<oops, iops, itin, opc, asm, pattern>,
847 // Helper classes for encoding T1sIt patterns:
848 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
849 string opc, string asm, list<dag> pattern>
850 : T1sIt<oops, iops, itin, opc, asm, pattern>,
851 T1DataProcessing<opA> {
857 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
858 string opc, string asm, list<dag> pattern>
859 : T1sIt<oops, iops, itin, opc, asm, pattern>,
863 let Inst{10-8} = Rdn;
864 let Inst{7-0} = imm8;
867 // Add with carry register
868 let isCommutable = 1, Uses = [CPSR] in
870 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
871 "adc", "\t$Rdn, $Rm",
872 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
875 def tADDi3 : // A8.6.4 T1
876 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
878 "add", "\t$Rd, $Rm, $imm3",
879 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
881 let Inst{8-6} = imm3;
884 def tADDi8 : // A8.6.4 T2
885 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
887 "add", "\t$Rdn, $imm8",
888 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
891 let isCommutable = 1 in
892 def tADDrr : // A8.6.6 T1
893 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
895 "add", "\t$Rd, $Rn, $Rm",
896 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
898 let neverHasSideEffects = 1 in
899 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
900 "add", "\t$Rdn, $Rm", []>,
901 T1Special<{0,0,?,?}> {
905 let Inst{7} = Rdn{3};
907 let Inst{2-0} = Rdn{2-0};
911 let isCommutable = 1 in
912 def tAND : // A8.6.12
913 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
915 "and", "\t$Rdn, $Rm",
916 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
919 def tASRri : // A8.6.14
920 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
922 "asr", "\t$Rd, $Rm, $imm5",
923 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
925 let Inst{10-6} = imm5;
929 def tASRrr : // A8.6.15
930 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
932 "asr", "\t$Rdn, $Rm",
933 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
936 def tBIC : // A8.6.20
937 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
939 "bic", "\t$Rdn, $Rm",
940 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
943 let isCompare = 1, Defs = [CPSR] in {
944 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
945 // Compare-to-zero still works out, just not the relationals
946 //def tCMN : // A8.6.33
947 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
949 // "cmn", "\t$lhs, $rhs",
950 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
952 def tCMNz : // A8.6.33
953 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
956 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
958 } // isCompare = 1, Defs = [CPSR]
961 let isCompare = 1, Defs = [CPSR] in {
962 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
963 "cmp", "\t$Rn, $imm8",
964 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
965 T1General<{1,0,1,?,?}> {
970 let Inst{7-0} = imm8;
974 def tCMPr : // A8.6.36 T1
975 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
978 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
980 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
981 "cmp", "\t$Rn, $Rm", []>,
982 T1Special<{0,1,?,?}> {
988 let Inst{2-0} = Rn{2-0};
990 } // isCompare = 1, Defs = [CPSR]
994 let isCommutable = 1 in
995 def tEOR : // A8.6.45
996 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
998 "eor", "\t$Rdn, $Rm",
999 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1002 def tLSLri : // A8.6.88
1003 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1005 "lsl", "\t$Rd, $Rm, $imm5",
1006 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1008 let Inst{10-6} = imm5;
1012 def tLSLrr : // A8.6.89
1013 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1015 "lsl", "\t$Rdn, $Rm",
1016 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1019 def tLSRri : // A8.6.90
1020 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1022 "lsr", "\t$Rd, $Rm, $imm5",
1023 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1025 let Inst{10-6} = imm5;
1029 def tLSRrr : // A8.6.91
1030 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1032 "lsr", "\t$Rdn, $Rm",
1033 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1036 let isMoveImm = 1 in
1037 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1038 "mov", "\t$Rd, $imm8",
1039 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1040 T1General<{1,0,0,?,?}> {
1044 let Inst{10-8} = Rd;
1045 let Inst{7-0} = imm8;
1048 // A7-73: MOV(2) - mov setting flag.
1050 let neverHasSideEffects = 1 in {
1051 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1052 Size2Bytes, IIC_iMOVr,
1053 "mov", "\t$Rd, $Rm", "", []>,
1054 T1Special<{1,0,?,?}> {
1058 let Inst{7} = Rd{3};
1060 let Inst{2-0} = Rd{2-0};
1062 let Defs = [CPSR] in
1063 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1064 "movs\t$Rd, $Rm", []>, Encoding16 {
1068 let Inst{15-6} = 0b0000000000;
1072 } // neverHasSideEffects
1074 // Multiply register
1075 let isCommutable = 1 in
1076 def tMUL : // A8.6.105 T1
1077 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1079 "mul", "\t$Rdn, $Rm, $Rdn",
1080 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1082 // Move inverse register
1083 def tMVN : // A8.6.107
1084 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1085 "mvn", "\t$Rd, $Rn",
1086 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1088 // Bitwise or register
1089 let isCommutable = 1 in
1090 def tORR : // A8.6.114
1091 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1093 "orr", "\t$Rdn, $Rm",
1094 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1097 def tREV : // A8.6.134
1098 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1100 "rev", "\t$Rd, $Rm",
1101 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1102 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1104 def tREV16 : // A8.6.135
1105 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1107 "rev16", "\t$Rd, $Rm",
1108 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1109 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1111 def tREVSH : // A8.6.136
1112 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1114 "revsh", "\t$Rd, $Rm",
1115 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1116 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1118 // Rotate right register
1119 def tROR : // A8.6.139
1120 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1122 "ror", "\t$Rdn, $Rm",
1123 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1126 def tRSB : // A8.6.141
1127 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1129 "rsb", "\t$Rd, $Rn, #0",
1130 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1132 // Subtract with carry register
1133 let Uses = [CPSR] in
1134 def tSBC : // A8.6.151
1135 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1137 "sbc", "\t$Rdn, $Rm",
1138 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1140 // Subtract immediate
1141 def tSUBi3 : // A8.6.210 T1
1142 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1144 "sub", "\t$Rd, $Rm, $imm3",
1145 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1147 let Inst{8-6} = imm3;
1150 def tSUBi8 : // A8.6.210 T2
1151 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1153 "sub", "\t$Rdn, $imm8",
1154 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1156 // Subtract register
1157 def tSUBrr : // A8.6.212
1158 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1160 "sub", "\t$Rd, $Rn, $Rm",
1161 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1163 // TODO: A7-96: STMIA - store multiple.
1166 def tSXTB : // A8.6.222
1167 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1169 "sxtb", "\t$Rd, $Rm",
1170 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1171 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173 // Sign-extend short
1174 def tSXTH : // A8.6.224
1175 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "sxth", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1182 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1183 def tTST : // A8.6.230
1184 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1185 "tst", "\t$Rn, $Rm",
1186 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1189 def tUXTB : // A8.6.262
1190 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1192 "uxtb", "\t$Rd, $Rm",
1193 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1194 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1196 // Zero-extend short
1197 def tUXTH : // A8.6.264
1198 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1200 "uxth", "\t$Rd, $Rm",
1201 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1202 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1204 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1205 // Expanded after instruction selection into a branch sequence.
1206 let usesCustomInserter = 1 in // Expanded after instruction selection.
1207 def tMOVCCr_pseudo :
1208 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1210 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1212 // tLEApcrel - Load a pc-relative address into a register without offending the
1215 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1216 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1217 T1Encoding<{1,0,1,0,0,?}> {
1220 let Inst{10-8} = Rd;
1221 let Inst{7-0} = addr;
1224 let neverHasSideEffects = 1, isReMaterializable = 1 in
1225 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1226 Size2Bytes, IIC_iALUi, []>;
1228 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1229 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1230 Size2Bytes, IIC_iALUi, []>;
1232 //===----------------------------------------------------------------------===//
1236 // __aeabi_read_tp preserves the registers r1-r3.
1237 // This is a pseudo inst so that we can get the encoding right,
1238 // complete with fixup for the aeabi_read_tp function.
1239 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1240 def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br,
1241 [(set R0, ARMthread_pointer)]>;
1243 //===----------------------------------------------------------------------===//
1244 // SJLJ Exception handling intrinsics
1247 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1248 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1249 // from some other function to get here, and we're using the stack frame for the
1250 // containing function to save/restore registers, we can't keep anything live in
1251 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1252 // tromped upon when we get here from a longjmp(). We force everything out of
1253 // registers except for our own input by listing the relevant registers in
1254 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1255 // preserve all of the callee-saved resgisters, which is exactly what we want.
1256 // $val is a scratch register for our use.
1257 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1258 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1259 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1260 AddrModeNone, SizeSpecial, NoItinerary, "","",
1261 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1263 // FIXME: Non-Darwin version(s)
1264 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1265 Defs = [ R7, LR, SP ] in
1266 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1267 AddrModeNone, SizeSpecial, IndexModeNone,
1268 Pseudo, NoItinerary, "", "",
1269 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1270 Requires<[IsThumb, IsDarwin]>;
1272 //===----------------------------------------------------------------------===//
1273 // Non-Instruction Patterns
1277 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1278 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1279 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1280 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1283 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1284 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1285 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1286 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1287 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1288 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1290 // Subtract with carry
1291 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1292 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1293 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1294 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1295 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1296 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1298 // ConstantPool, GlobalAddress
1299 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1300 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1303 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1304 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1307 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1308 Requires<[IsThumb, IsNotDarwin]>;
1309 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1310 Requires<[IsThumb, IsDarwin]>;
1312 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1313 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1314 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1315 Requires<[IsThumb, HasV5T, IsDarwin]>;
1317 // Indirect calls to ARM routines
1318 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1319 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1320 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1321 Requires<[IsThumb, HasV5T, IsDarwin]>;
1323 // zextload i1 -> zextload i8
1324 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1325 (tLDRBr t_addrmode_rrs1:$addr)>;
1326 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1327 (tLDRBi t_addrmode_is1:$addr)>;
1329 // extload -> zextload
1330 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1331 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1332 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1333 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1334 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1335 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1337 // If it's impossible to use [r,r] address mode for sextload, select to
1338 // ldr{b|h} + sxt{b|h} instead.
1339 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1340 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1341 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1342 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1343 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1344 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1345 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1346 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1347 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1348 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1349 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1350 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1352 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1353 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1354 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1355 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1356 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1357 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1358 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1359 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1361 // Large immediate handling.
1364 def : T1Pat<(i32 thumb_immshifted:$src),
1365 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1366 (thumb_immshifted_shamt imm:$src))>;
1368 def : T1Pat<(i32 imm0_255_comp:$src),
1369 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1371 // Pseudo instruction that combines ldr from constpool and add pc. This should
1372 // be expanded into two instructions late to allow if-conversion and
1374 let isReMaterializable = 1 in
1375 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1377 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1379 Requires<[IsThumb, IsThumb1Only]>;
1381 // Pseudo-instruction for merged POP and return.
1382 // FIXME: remove when we have a way to marking a MI with these properties.
1383 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1384 hasExtraDefRegAllocReq = 1 in
1385 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1386 Size2Bytes, IIC_iPop_Br, [],
1387 (tPOP pred:$p, reglist:$regs)>;
1389 // Indirect branch using "mov pc, $Rm"
1390 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1391 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1392 Size2Bytes, IIC_Br, [(brind GPR:$Rm)],
1393 (tMOVr PC, GPR:$Rm, pred:$p)>;