1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, ops, asm, cstr> {
36 let Pattern = pattern;
37 list<Predicate> Predicates = [IsThumb];
40 class TI<dag ops, string asm, list<dag> pattern>
41 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
42 class TI1<dag ops, string asm, list<dag> pattern>
43 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
44 class TI2<dag ops, string asm, list<dag> pattern>
45 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
46 class TI4<dag ops, string asm, list<dag> pattern>
47 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
48 class TIs<dag ops, string asm, list<dag> pattern>
49 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
51 // Two-address instructions
52 class TIt<dag ops, string asm, list<dag> pattern>
53 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
55 // BL, BLX(1) are translated by assembler into two instructions
56 class TIx2<dag ops, string asm, list<dag> pattern>
57 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
60 class TJTI<dag ops, string asm, list<dag> pattern>
61 : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
63 def imm_neg_XFORM : SDNodeXForm<imm, [{
64 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
66 def imm_comp_XFORM : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
71 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
72 def imm0_7 : PatLeaf<(i32 imm), [{
73 return (uint32_t)N->getValue() < 8;
75 def imm0_7_neg : PatLeaf<(i32 imm), [{
76 return (uint32_t)-N->getValue() < 8;
79 def imm0_255 : PatLeaf<(i32 imm), [{
80 return (uint32_t)N->getValue() < 256;
82 def imm0_255_comp : PatLeaf<(i32 imm), [{
83 return ~((uint32_t)N->getValue()) < 256;
86 def imm8_255 : PatLeaf<(i32 imm), [{
87 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
89 def imm8_255_neg : PatLeaf<(i32 imm), [{
90 unsigned Val = -N->getValue();
91 return Val >= 8 && Val < 256;
94 // Break imm's up into two pieces: an immediate + a left shift.
95 // This uses thumb_immshifted to match and thumb_immshifted_val and
96 // thumb_immshifted_shamt to get the val/shift pieces.
97 def thumb_immshifted : PatLeaf<(imm), [{
98 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
101 def thumb_immshifted_val : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
107 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
108 return CurDAG->getTargetConstant(V, MVT::i32);
111 // Define Thumb specific addressing modes.
113 // t_addrmode_rr := reg + reg
115 def t_addrmode_rr : Operand<i32>,
116 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
117 let PrintMethod = "printThumbAddrModeRROperand";
118 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
121 // t_addrmode_s4 := reg + reg
124 def t_addrmode_s4 : Operand<i32>,
125 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
126 let PrintMethod = "printThumbAddrModeS4Operand";
127 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
130 // t_addrmode_s2 := reg + reg
133 def t_addrmode_s2 : Operand<i32>,
134 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
135 let PrintMethod = "printThumbAddrModeS2Operand";
136 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
139 // t_addrmode_s1 := reg + reg
142 def t_addrmode_s1 : Operand<i32>,
143 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
144 let PrintMethod = "printThumbAddrModeS1Operand";
145 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
148 // t_addrmode_sp := sp + imm8 * 4
150 def t_addrmode_sp : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
152 let PrintMethod = "printThumbAddrModeSPOperand";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 //===----------------------------------------------------------------------===//
157 // Miscellaneous Instructions.
160 def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
161 "$cp:\n\tadd $dst, pc",
162 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
164 //===----------------------------------------------------------------------===//
165 // Control Flow Instructions.
168 let isReturn = 1, isTerminator = 1 in {
169 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
170 // Alternative return instruction used by vararg functions.
171 def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
174 // FIXME: remove when we have a way to marking a MI with these properties.
175 let isLoad = 1, isReturn = 1, isTerminator = 1 in
176 def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
179 let isCall = 1, noResults = 1,
180 Defs = [R0, R1, R2, R3, LR,
181 D0, D1, D2, D3, D4, D5, D6, D7] in {
182 def tBL : TIx2<(ops i32imm:$func, variable_ops),
184 [(ARMtcall tglobaladdr:$func)]>;
186 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
188 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
189 def tBLXr : TI<(ops GPR:$dst, variable_ops),
191 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
193 def tBX : TIx2<(ops GPR:$dst, variable_ops),
194 "cpy lr, pc\n\tbx $dst",
195 [(ARMcall_nolink GPR:$dst)]>;
198 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
199 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
202 def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
204 def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
205 "cpy pc, $dst \n\t.align\t2\n$jt",
206 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
209 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
210 def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
211 [(ARMbrcond bb:$dst, imm:$cc)]>;
213 //===----------------------------------------------------------------------===//
214 // Load Store Instructions.
218 def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
220 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
222 def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
224 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
226 def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
228 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
230 def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
232 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
234 def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
236 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
238 def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
240 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
242 // Special instruction for restore. It cannot clobber condition register
243 // when it's expanded by eliminateCallFramePseudoInstr().
244 def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
245 "ldr $dst, $addr", []>;
248 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
250 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
252 // Special LDR for loads from non-pc-relative constpools.
253 let isReMaterializable = 1 in
254 def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
255 "ldr $dst, $addr", []>;
259 def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
261 [(store GPR:$src, t_addrmode_s4:$addr)]>;
263 def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
265 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
267 def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
269 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
271 def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
273 [(store GPR:$src, t_addrmode_sp:$addr)]>;
275 // Special instruction for spill. It cannot clobber condition register
276 // when it's expanded by eliminateCallFramePseudoInstr().
277 def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
278 "str $src, $addr", []>;
281 //===----------------------------------------------------------------------===//
282 // Load / store multiple Instructions.
285 // TODO: A7-44: LDMIA - load multiple
288 def tPOP : TI<(ops reglist:$dst1, variable_ops),
292 def tPUSH : TI<(ops reglist:$src1, variable_ops),
295 //===----------------------------------------------------------------------===//
296 // Arithmetic Instructions.
300 def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
302 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
304 def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
305 "add $dst, $lhs, $rhs",
306 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
309 def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
310 "add $dst, $lhs, $rhs",
311 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
313 def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
315 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
317 def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
318 "add $dst, $lhs, $rhs",
319 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
321 def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
322 "add $dst, $rhs", []>;
324 def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
325 "add $dst, pc, $rhs * 4", []>;
326 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
327 "add $dst, $sp, $rhs * 4", []>;
328 def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
329 "add $dst, $rhs * 4", []>;
331 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
333 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
335 def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
336 "asr $dst, $lhs, $rhs",
337 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
339 def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
341 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
343 def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
345 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
348 def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
350 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
352 def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
354 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
356 def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
358 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
360 // TODO: A7-37: CMP(3) - cmp hi regs
362 def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
364 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
366 def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
367 "lsl $dst, $lhs, $rhs",
368 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
370 def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
372 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
374 def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
375 "lsr $dst, $lhs, $rhs",
376 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
378 def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
380 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
382 // FIXME: This is not rematerializable because mov changes the condition code.
383 def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
385 [(set GPR:$dst, imm0_255:$src)]>;
387 // TODO: A7-73: MOV(2) - mov setting flag.
390 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
391 // which is MOV(3). This also supports high registers.
392 def tMOVr : TI<(ops GPR:$dst, GPR:$src),
393 "cpy $dst, $src", []>;
395 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
397 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
399 def tMVN : TI<(ops GPR:$dst, GPR:$src),
401 [(set GPR:$dst, (not GPR:$src))]>;
403 def tNEG : TI<(ops GPR:$dst, GPR:$src),
405 [(set GPR:$dst, (ineg GPR:$src))]>;
407 def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
409 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
412 def tREV : TI<(ops GPR:$dst, GPR:$src),
414 [(set GPR:$dst, (bswap GPR:$src))]>,
415 Requires<[IsThumb, HasV6]>;
417 def tREV16 : TI<(ops GPR:$dst, GPR:$src),
420 (or (and (srl GPR:$src, 8), 0xFF),
421 (or (and (shl GPR:$src, 8), 0xFF00),
422 (or (and (srl GPR:$src, 8), 0xFF0000),
423 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
424 Requires<[IsThumb, HasV6]>;
426 def tREVSH : TI<(ops GPR:$dst, GPR:$src),
430 (or (srl (and GPR:$src, 0xFFFF), 8),
431 (shl GPR:$src, 8)), i16))]>,
432 Requires<[IsThumb, HasV6]>;
434 def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
436 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
439 // Subtract with carry
440 def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
442 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
444 def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
445 "sub $dst, $lhs, $rhs",
446 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
449 // TODO: A7-96: STMIA - store multiple.
451 def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
452 "sub $dst, $lhs, $rhs",
453 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
455 def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
457 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
459 def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
460 "sub $dst, $lhs, $rhs",
461 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
463 def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
464 "sub $dst, $rhs * 4", []>;
466 def tSXTB : TI<(ops GPR:$dst, GPR:$src),
468 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
469 Requires<[IsThumb, HasV6]>;
470 def tSXTH : TI<(ops GPR:$dst, GPR:$src),
472 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
473 Requires<[IsThumb, HasV6]>;
475 // TODO: A7-122: TST - test.
477 def tUXTB : TI<(ops GPR:$dst, GPR:$src),
479 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
480 Requires<[IsThumb, HasV6]>;
481 def tUXTH : TI<(ops GPR:$dst, GPR:$src),
483 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
484 Requires<[IsThumb, HasV6]>;
487 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
488 // Expanded by the scheduler into a branch sequence.
489 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
491 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
493 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
495 // tLEApcrel - Load a pc-relative address into a register without offending the
497 def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
498 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
499 "${:private}PCRELL${:uid}+6))\n"),
500 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
501 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
504 def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
505 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
506 "${:private}PCRELL${:uid}+4))\n"),
507 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
508 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
511 //===----------------------------------------------------------------------===//
512 // Non-Instruction Patterns
515 // ConstantPool, GlobalAddress
516 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
517 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
520 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
521 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
524 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
525 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
527 // Indirect calls to ARM routines
528 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
530 // zextload i1 -> zextload i8
531 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
532 (tLDRB t_addrmode_s1:$addr)>;
534 // extload -> zextload
535 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
536 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
537 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
539 // truncstore i1 -> truncstore i8
540 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
541 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
543 // Large immediate handling.
546 def : ThumbPat<(i32 thumb_immshifted:$src),
547 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
548 (thumb_immshifted_shamt imm:$src))>;
550 def : ThumbPat<(i32 imm0_255_comp:$src),
551 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;