1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 // For both thumb1 and thumb2.
131 let isNotDuplicable = 1 in
132 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALU,
133 "$cp:\n\tadd $dst, pc",
134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
137 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALU,
138 "add $dst, pc, $rhs * 4", []>;
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALU,
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
146 "add $dst, $rhs * 4", []>;
149 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
150 "sub $dst, $rhs * 4", []>;
153 def tADDrSPr : TI<(outs GPR:$dst), (ins GPR:$sp, GPR:$rhs), IIC_iALU,
154 "add $dst, $sp, $rhs", []>;
157 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
158 "add $dst, $rhs", []>;
160 // Pseudo instruction that will expand into a tSUBspi + a copy.
161 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
162 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
163 NoItinerary, "@ sub $dst, $rhs * 4", []>;
165 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
166 NoItinerary, "@ add $dst, $rhs", []>;
169 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
170 NoItinerary, "@ and $dst, $rhs", []>;
171 } // usesCustomDAGSchedInserter
173 //===----------------------------------------------------------------------===//
174 // Control Flow Instructions.
177 let isReturn = 1, isTerminator = 1 in {
178 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx lr", [(ARMretflag)]>;
179 // Alternative return instruction used by vararg functions.
180 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx $target", []>;
183 // FIXME: remove when we have a way to marking a MI with these properties.
184 let isReturn = 1, isTerminator = 1 in
185 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
189 Defs = [R0, R1, R2, R3, R12, LR,
190 D0, D1, D2, D3, D4, D5, D6, D7,
191 D16, D17, D18, D19, D20, D21, D22, D23,
192 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
193 // Also used for Thumb2
194 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
196 [(ARMtcall tglobaladdr:$func)]>,
197 Requires<[IsThumb, IsNotDarwin]>;
199 // ARMv5T and above, also used for Thumb2
200 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
202 [(ARMcall tglobaladdr:$func)]>,
203 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
205 // Also used for Thumb2
206 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
208 [(ARMtcall GPR:$func)]>,
209 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
212 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
213 "mov lr, pc\n\tbx $func",
214 [(ARMcall_nolink tGPR:$func)]>,
215 Requires<[IsThumb1Only, IsNotDarwin]>;
218 // On Darwin R9 is call-clobbered.
220 Defs = [R0, R1, R2, R3, R9, R12, LR,
221 D0, D1, D2, D3, D4, D5, D6, D7,
222 D16, D17, D18, D19, D20, D21, D22, D23,
223 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
224 // Also used for Thumb2
225 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
227 [(ARMtcall tglobaladdr:$func)]>,
228 Requires<[IsThumb, IsDarwin]>;
230 // ARMv5T and above, also used for Thumb2
231 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
233 [(ARMcall tglobaladdr:$func)]>,
234 Requires<[IsThumb, HasV5T, IsDarwin]>;
236 // Also used for Thumb2
237 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
239 [(ARMtcall GPR:$func)]>,
240 Requires<[IsThumb, HasV5T, IsDarwin]>;
243 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
244 "mov lr, pc\n\tbx $func",
245 [(ARMcall_nolink tGPR:$func)]>,
246 Requires<[IsThumb1Only, IsDarwin]>;
249 let isBranch = 1, isTerminator = 1 in {
250 let isBarrier = 1 in {
251 let isPredicable = 1 in
252 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
253 "b $target", [(br bb:$target)]>;
257 def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
258 "bl $target\t@ far jump",[]>;
260 def tBR_JTr : T1JTI<(outs),
261 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
262 IIC_Br, "mov pc, $target\n\t.align\t2\n$jt",
263 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
267 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
268 // a two-value operand where a dag node expects two operands. :(
269 let isBranch = 1, isTerminator = 1 in
270 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
272 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
274 //===----------------------------------------------------------------------===//
275 // Load Store Instructions.
278 let canFoldAsLoad = 1 in
279 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad,
280 "ldr", " $dst, $addr",
281 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
283 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad,
284 "ldrb", " $dst, $addr",
285 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
287 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad,
288 "ldrh", " $dst, $addr",
289 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
291 let AddedComplexity = 10 in
292 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
293 "ldrsb", " $dst, $addr",
294 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
296 let AddedComplexity = 10 in
297 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
298 "ldrsh", " $dst, $addr",
299 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
301 let canFoldAsLoad = 1 in
302 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
303 "ldr", " $dst, $addr",
304 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
306 // Special instruction for restore. It cannot clobber condition register
307 // when it's expanded by eliminateCallFramePseudoInstr().
308 let canFoldAsLoad = 1, mayLoad = 1 in
309 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
310 "ldr", " $dst, $addr", []>;
313 let canFoldAsLoad = 1 in
314 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
315 "ldr", " $dst, $addr",
316 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
318 // Special LDR for loads from non-pc-relative constpools.
319 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
320 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
321 "ldr", " $dst, $addr", []>;
323 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore,
324 "str", " $src, $addr",
325 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
327 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore,
328 "strb", " $src, $addr",
329 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
331 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore,
332 "strh", " $src, $addr",
333 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
335 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
336 "str", " $src, $addr",
337 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
339 let mayStore = 1 in {
340 // Special instruction for spill. It cannot clobber condition register
341 // when it's expanded by eliminateCallFramePseudoInstr().
342 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
343 "str", " $src, $addr", []>;
346 //===----------------------------------------------------------------------===//
347 // Load / store multiple Instructions.
350 // TODO: A7-44: LDMIA - load multiple
351 // TODO: Allow these to be predicated
354 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
358 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops), IIC_Br,
361 //===----------------------------------------------------------------------===//
362 // Arithmetic Instructions.
365 // Add with carry register
366 let isCommutable = 1, Uses = [CPSR] in
367 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
368 "adc", " $dst, $rhs",
369 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
372 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
373 "add", " $dst, $lhs, $rhs",
374 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
376 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
377 "add", " $dst, $rhs",
378 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
381 let isCommutable = 1 in
382 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
383 "add", " $dst, $lhs, $rhs",
384 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
386 let neverHasSideEffects = 1 in
387 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
388 "add", " $dst, $rhs @ addhirr", []>;
391 let isCommutable = 1 in
392 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
393 "and", " $dst, $rhs",
394 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
397 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
398 "asr", " $dst, $lhs, $rhs",
399 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
402 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
403 "asr", " $dst, $rhs",
404 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
407 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
408 "bic", " $dst, $rhs",
409 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
412 let Defs = [CPSR] in {
413 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
414 "cmn", " $lhs, $rhs",
415 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
416 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
417 "cmn", " $lhs, $rhs",
418 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
422 let Defs = [CPSR] in {
423 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
424 "cmp", " $lhs, $rhs",
425 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
426 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
427 "cmp", " $lhs, $rhs",
428 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
433 let Defs = [CPSR] in {
434 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
435 "cmp", " $lhs, $rhs",
436 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
437 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
438 "cmp", " $lhs, $rhs",
439 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
441 // TODO: Make use of the followings cmp hi regs
442 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
443 "cmp", " $lhs, $rhs", []>;
444 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
445 "cmp", " $lhs, $rhs", []>;
450 let isCommutable = 1 in
451 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
452 "eor", " $dst, $rhs",
453 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
456 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
457 "lsl", " $dst, $lhs, $rhs",
458 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
461 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
462 "lsl", " $dst, $rhs",
463 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
466 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
467 "lsr", " $dst, $lhs, $rhs",
468 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
471 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
472 "lsr", " $dst, $rhs",
473 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
476 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iALU,
477 "mov", " $dst, $src",
478 [(set tGPR:$dst, imm0_255:$src)]>;
480 // TODO: A7-73: MOV(2) - mov setting flag.
483 let neverHasSideEffects = 1 in {
484 // FIXME: Make this predicable.
485 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
486 "mov $dst, $src", []>;
488 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
489 "movs $dst, $src", []>;
491 // FIXME: Make these predicable.
492 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iALU,
493 "mov $dst, $src\t@ hir2lor", []>;
494 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iALU,
495 "mov $dst, $src\t@ lor2hir", []>;
496 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
497 "mov $dst, $src\t@ hir2hir", []>;
498 } // neverHasSideEffects
501 let isCommutable = 1 in
502 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
503 "mul", " $dst, $rhs",
504 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
506 // move inverse register
507 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
508 "mvn", " $dst, $src",
509 [(set tGPR:$dst, (not tGPR:$src))]>;
511 // bitwise or register
512 let isCommutable = 1 in
513 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
514 "orr", " $dst, $rhs",
515 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
518 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
519 "rev", " $dst, $src",
520 [(set tGPR:$dst, (bswap tGPR:$src))]>,
521 Requires<[IsThumb1Only, HasV6]>;
523 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
524 "rev16", " $dst, $src",
526 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
527 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
528 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
529 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
530 Requires<[IsThumb1Only, HasV6]>;
532 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
533 "revsh", " $dst, $src",
536 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
537 (shl tGPR:$src, (i32 8))), i16))]>,
538 Requires<[IsThumb1Only, HasV6]>;
540 // rotate right register
541 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
542 "ror", " $dst, $rhs",
543 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
546 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
547 "rsb", " $dst, $src, #0",
548 [(set tGPR:$dst, (ineg tGPR:$src))]>;
550 // Subtract with carry register
552 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
553 "sbc", " $dst, $rhs",
554 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
556 // Subtract immediate
557 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
558 "sub", " $dst, $lhs, $rhs",
559 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
561 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
562 "sub", " $dst, $rhs",
563 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
566 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
567 "sub", " $dst, $lhs, $rhs",
568 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
570 // TODO: A7-96: STMIA - store multiple.
573 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
574 "sxtb", " $dst, $src",
575 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
576 Requires<[IsThumb1Only, HasV6]>;
579 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
580 "sxth", " $dst, $src",
581 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
582 Requires<[IsThumb1Only, HasV6]>;
585 let isCommutable = 1, Defs = [CPSR] in
586 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
587 "tst", " $lhs, $rhs",
588 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
591 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
592 "uxtb", " $dst, $src",
593 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
594 Requires<[IsThumb1Only, HasV6]>;
597 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
598 "uxth", " $dst, $src",
599 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
600 Requires<[IsThumb1Only, HasV6]>;
603 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
604 // Expanded by the scheduler into a branch sequence.
605 // FIXME: Add actual movcc in IT blocks for Thumb2.
606 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
608 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), IIC_iALU,
610 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
612 // tLEApcrel - Load a pc-relative address into a register without offending the
614 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
615 "adr $dst, #$label", []>;
617 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), IIC_iALU,
618 "adr $dst, #${label}_${id:no_hash}", []>;
620 //===----------------------------------------------------------------------===//
624 // __aeabi_read_tp preserves the registers r1-r3.
627 def tTPsoft : TIx2<(outs), (ins), IIC_Br,
628 "bl __aeabi_read_tp",
629 [(set R0, ARMthread_pointer)]>;
632 //===----------------------------------------------------------------------===//
633 // Non-Instruction Patterns
637 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
638 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
639 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
640 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
641 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
642 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
644 // Subtract with carry
645 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
646 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
647 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
648 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
649 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
650 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
652 // ConstantPool, GlobalAddress
653 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
654 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
657 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
658 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
661 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
662 Requires<[IsThumb, IsNotDarwin]>;
663 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
664 Requires<[IsThumb, IsDarwin]>;
666 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
667 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
668 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
669 Requires<[IsThumb, HasV5T, IsDarwin]>;
671 // Indirect calls to ARM routines
672 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
673 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
674 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
675 Requires<[IsThumb, HasV5T, IsDarwin]>;
677 // zextload i1 -> zextload i8
678 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
679 (tLDRB t_addrmode_s1:$addr)>;
681 // extload -> zextload
682 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
683 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
684 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
686 // If it's possible to use [r,r] address mode for sextload, select to
687 // ldr{b|h} + sxt{b|h} instead.
688 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
689 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
690 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
691 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
694 // Large immediate handling.
697 def : T1Pat<(i32 thumb_immshifted:$src),
698 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
699 (thumb_immshifted_shamt imm:$src))>;
701 def : T1Pat<(i32 imm0_255_comp:$src),
702 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;