1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, ops, asm, cstr> {
36 let Pattern = pattern;
37 list<Predicate> Predicates = [IsThumb];
40 class TI<dag ops, string asm, list<dag> pattern>
41 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
42 class TI1<dag ops, string asm, list<dag> pattern>
43 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
44 class TI2<dag ops, string asm, list<dag> pattern>
45 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
46 class TI4<dag ops, string asm, list<dag> pattern>
47 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
48 class TIs<dag ops, string asm, list<dag> pattern>
49 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
51 // Two-address instructions
52 class TIt<dag ops, string asm, list<dag> pattern>
53 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
55 // BL, BLX(1) are translated by assembler into two instructions
56 class TIx2<dag ops, string asm, list<dag> pattern>
57 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
59 def imm_neg_XFORM : SDNodeXForm<imm, [{
60 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
62 def imm_comp_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
67 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
68 def imm0_7 : PatLeaf<(i32 imm), [{
69 return (uint32_t)N->getValue() < 8;
71 def imm0_7_neg : PatLeaf<(i32 imm), [{
72 return (uint32_t)-N->getValue() < 8;
75 def imm0_255 : PatLeaf<(i32 imm), [{
76 return (uint32_t)N->getValue() < 256;
78 def imm0_255_comp : PatLeaf<(i32 imm), [{
79 return ~((uint32_t)N->getValue()) < 256;
82 def imm8_255 : PatLeaf<(i32 imm), [{
83 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
85 def imm8_255_neg : PatLeaf<(i32 imm), [{
86 unsigned Val = -N->getValue();
87 return Val >= 8 && Val < 256;
90 // Break imm's up into two pieces: an immediate + a left shift.
91 // This uses thumb_immshifted to match and thumb_immshifted_val and
92 // thumb_immshifted_shamt to get the val/shift pieces.
93 def thumb_immshifted : PatLeaf<(imm), [{
94 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
97 def thumb_immshifted_val : SDNodeXForm<imm, [{
98 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
99 return CurDAG->getTargetConstant(V, MVT::i32);
102 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
103 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
104 return CurDAG->getTargetConstant(V, MVT::i32);
107 // Define Thumb specific addressing modes.
109 // t_addrmode_rr := reg + reg
111 def t_addrmode_rr : Operand<i32>,
112 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
113 let PrintMethod = "printThumbAddrModeRROperand";
114 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
117 // t_addrmode_s4 := reg + reg
120 def t_addrmode_s4 : Operand<i32>,
121 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
122 let PrintMethod = "printThumbAddrModeS4Operand";
123 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
126 // t_addrmode_s2 := reg + reg
129 def t_addrmode_s2 : Operand<i32>,
130 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
131 let PrintMethod = "printThumbAddrModeS2Operand";
132 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
135 // t_addrmode_s1 := reg + reg
138 def t_addrmode_s1 : Operand<i32>,
139 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
140 let PrintMethod = "printThumbAddrModeS1Operand";
141 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
144 // t_addrmode_sp := sp + imm8 * 4
146 def t_addrmode_sp : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
148 let PrintMethod = "printThumbAddrModeSPOperand";
149 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
152 //===----------------------------------------------------------------------===//
153 // Miscellaneous Instructions.
156 def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
157 "\n$cp:\n\tadd $dst, pc",
158 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
160 //===----------------------------------------------------------------------===//
161 // Control Flow Instructions.
164 let isReturn = 1, isTerminator = 1 in
165 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
167 // FIXME: remove when we have a way to marking a MI with these properties.
168 let isLoad = 1, isReturn = 1, isTerminator = 1 in
169 def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
172 let isCall = 1, noResults = 1,
173 Defs = [R0, R1, R2, R3, LR,
174 D0, D1, D2, D3, D4, D5, D6, D7] in {
175 def tBL : TIx2<(ops i32imm:$func, variable_ops),
177 [(ARMtcall tglobaladdr:$func)]>;
179 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
181 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
182 def tBLXr : TI<(ops GPR:$dst, variable_ops),
184 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
186 def tBX : TIx2<(ops GPR:$dst, variable_ops),
187 "cpy lr, pc\n\tbx $dst",
188 [(ARMcall_nolink GPR:$dst)]>;
191 let isBranch = 1, isTerminator = 1, isBarrier = 1 in
192 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
194 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
195 def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
196 [(ARMbrcond bb:$dst, imm:$cc)]>;
198 //===----------------------------------------------------------------------===//
199 // Load Store Instructions.
203 def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
205 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
207 def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
209 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
211 def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
213 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
215 def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
217 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
219 def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
221 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
223 def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
225 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
228 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
230 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
234 def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
236 [(store GPR:$src, t_addrmode_s4:$addr)]>;
238 def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
240 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
242 def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
244 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
246 def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
248 [(store GPR:$src, t_addrmode_sp:$addr)]>;
251 //===----------------------------------------------------------------------===//
252 // Load / store multiple Instructions.
255 // TODO: A7-44: LDMIA - load multiple
258 def tPOP : TI<(ops reglist:$dst1, variable_ops),
262 def tPUSH : TI<(ops reglist:$src1, variable_ops),
265 //===----------------------------------------------------------------------===//
266 // Arithmetic Instructions.
269 def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
270 "add $dst, $lhs, $rhs",
271 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
273 def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
275 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
277 def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
278 "add $dst, $lhs, $rhs",
279 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
281 def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
282 "add $dst, $rhs", []>;
284 def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
285 "add $dst, pc, $rhs * 4", []>;
286 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
287 "add $dst, $sp, $rhs * 4", []>;
288 def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
289 "add $dst, $rhs * 4", []>;
292 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
294 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
296 def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
297 "asr $dst, $lhs, $rhs",
298 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
300 def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
302 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
304 def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
306 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
309 def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
311 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
313 def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
315 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
317 def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
319 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
321 // TODO: A7-37: CMP(3) - cmp hi regs
323 def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
325 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
327 def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
328 "lsl $dst, $lhs, $rhs",
329 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
331 def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
333 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
335 def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
336 "lsr $dst, $lhs, $rhs",
337 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
339 def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
341 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
343 def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
345 [(set GPR:$dst, imm0_255:$src)]>;
347 // TODO: A7-73: MOV(2) - mov setting flag.
350 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
351 // which is MOV(3). This also supports high registers.
352 def tMOVrr : TI<(ops GPR:$dst, GPR:$src),
353 "cpy $dst, $src", []>;
355 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
357 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
359 def tMVN : TI<(ops GPR:$dst, GPR:$src),
361 [(set GPR:$dst, (not GPR:$src))]>;
363 def tNEG : TI<(ops GPR:$dst, GPR:$src),
365 [(set GPR:$dst, (ineg GPR:$src))]>;
367 def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
369 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
372 def tREV : TI<(ops GPR:$dst, GPR:$src),
374 [(set GPR:$dst, (bswap GPR:$src))]>,
375 Requires<[IsThumb, HasV6]>;
377 def tREV16 : TI<(ops GPR:$dst, GPR:$src),
380 (or (and (srl GPR:$src, 8), 0xFF),
381 (or (and (shl GPR:$src, 8), 0xFF00),
382 (or (and (srl GPR:$src, 8), 0xFF0000),
383 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
384 Requires<[IsThumb, HasV6]>;
386 def tREVSH : TI<(ops GPR:$dst, GPR:$src),
390 (or (srl (and GPR:$src, 0xFFFF), 8),
391 (shl GPR:$src, 8)), i16))]>,
392 Requires<[IsThumb, HasV6]>;
394 def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
396 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
398 def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
400 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
402 // TODO: A7-96: STMIA - store multiple.
404 def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
405 "sub $dst, $lhs, $rhs",
406 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
408 def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
410 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
412 def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
413 "sub $dst, $lhs, $rhs",
414 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
416 def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
417 "sub $dst, $rhs * 4", []>;
419 def tSXTB : TI<(ops GPR:$dst, GPR:$src),
421 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
422 Requires<[IsThumb, HasV6]>;
423 def tSXTH : TI<(ops GPR:$dst, GPR:$src),
425 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
426 Requires<[IsThumb, HasV6]>;
428 // TODO: A7-122: TST - test.
430 def tUXTB : TI<(ops GPR:$dst, GPR:$src),
432 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
433 Requires<[IsThumb, HasV6]>;
434 def tUXTH : TI<(ops GPR:$dst, GPR:$src),
436 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
437 Requires<[IsThumb, HasV6]>;
440 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
441 // Expanded by the scheduler into a branch sequence.
442 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
444 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
446 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
448 // tLEApcrel - Load a pc-relative address into a register without offending the
450 def tLEApcrel : TI<(ops GPR:$dst, i32imm:$label),
451 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
452 "${:private}PCRELL${:uid}+4))\n"),
453 !strconcat("${:private}PCRELL${:uid}:\n\t",
454 "add $dst, pc, #PCRELV${:uid}")),
457 def tLEApcrelCall : TI<(ops GPR:$dst, i32imm:$label),
458 !strconcat(!strconcat(".set PCRELV${:uid}, (${label:call}-(",
459 "${:private}PCRELL${:uid}+4))\n"),
460 !strconcat("${:private}PCRELL${:uid}:\n\t",
461 "add $dst, pc, #PCRELV${:uid}")),
464 //===----------------------------------------------------------------------===//
465 // Non-Instruction Patterns
468 // ConstantPool, GlobalAddress
469 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
470 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
471 def : ThumbPat<(ARMWrapperCall tglobaladdr :$dst),
472 (tLEApcrelCall tglobaladdr :$dst)>;
473 def : ThumbPat<(ARMWrapperCall texternalsym:$dst),
474 (tLEApcrelCall texternalsym:$dst)>;
477 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
478 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
480 // Indirect calls to ARM routines
481 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
483 // zextload i1 -> zextload i8
484 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
485 (tLDRB t_addrmode_s1:$addr)>;
487 // extload -> zextload
488 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
489 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
490 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
492 // truncstore i1 -> truncstore i8
493 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
494 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
496 // Large immediate handling.
499 def : ThumbPat<(i32 thumb_immshifted:$src),
500 (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)),
501 (thumb_immshifted_shamt imm:$src))>;
503 def : ThumbPat<(i32 imm0_255_comp:$src),
504 (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>;