1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
126 // t_addrmode_rrs := reg + reg
128 def t_addrmode_rrs1 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
130 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
131 let PrintMethod = "printThumbAddrModeRROperand";
132 let DecoderMethod = "DecodeThumbAddrModeRR";
133 let ParserMatchClass = t_addrmode_rr_asm_operand;
134 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
136 def t_addrmode_rrs2 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let DecoderMethod = "DecodeThumbAddrModeRR";
140 let PrintMethod = "printThumbAddrModeRROperand";
141 let ParserMatchClass = t_addrmode_rr_asm_operand;
142 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
144 def t_addrmode_rrs4 : Operand<i32>,
145 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
146 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
147 let DecoderMethod = "DecodeThumbAddrModeRR";
148 let PrintMethod = "printThumbAddrModeRROperand";
149 let ParserMatchClass = t_addrmode_rr_asm_operand;
150 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
153 // t_addrmode_is4 := reg + imm5 * 4
155 def t_addrmode_is4 : Operand<i32>,
156 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
157 let EncoderMethod = "getAddrModeISOpValue";
158 let DecoderMethod = "DecodeThumbAddrModeIS";
159 let PrintMethod = "printThumbAddrModeImm5S4Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
163 // t_addrmode_is2 := reg + imm5 * 2
165 def t_addrmode_is2 : Operand<i32>,
166 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
167 let EncoderMethod = "getAddrModeISOpValue";
168 let DecoderMethod = "DecodeThumbAddrModeIS";
169 let PrintMethod = "printThumbAddrModeImm5S2Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
173 // t_addrmode_is1 := reg + imm5
175 def t_addrmode_is1 : Operand<i32>,
176 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
177 let EncoderMethod = "getAddrModeISOpValue";
178 let DecoderMethod = "DecodeThumbAddrModeIS";
179 let PrintMethod = "printThumbAddrModeImm5S1Operand";
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_sp := sp + imm8 * 4
185 def t_addrmode_sp : Operand<i32>,
186 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
187 let EncoderMethod = "getAddrModeThumbSPOpValue";
188 let DecoderMethod = "DecodeThumbAddrModeSP";
189 let PrintMethod = "printThumbAddrModeSPOperand";
190 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
193 // t_addrmode_pc := <label> => pc + imm8 * 4
195 def t_addrmode_pc : Operand<i32> {
196 let EncoderMethod = "getAddrModePCOpValue";
197 let DecoderMethod = "DecodeThumbAddrModePC";
200 //===----------------------------------------------------------------------===//
201 // Miscellaneous Instructions.
204 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
205 // from removing one half of the matched pairs. That breaks PEI, which assumes
206 // these will always be in pairs, and asserts if it finds otherwise. Better way?
207 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
208 def tADJCALLSTACKUP :
209 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
210 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
211 Requires<[IsThumb, IsThumb1Only]>;
213 def tADJCALLSTACKDOWN :
214 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
215 [(ARMcallseq_start imm:$amt)]>,
216 Requires<[IsThumb, IsThumb1Only]>;
219 class T1SystemEncoding<bits<8> opc>
220 : T1Encoding<0b101111> {
221 let Inst{9-8} = 0b11;
225 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
226 T1SystemEncoding<0x00>; // A8.6.110
228 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
229 T1SystemEncoding<0x10>; // A8.6.410
231 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
232 T1SystemEncoding<0x20>; // A8.6.408
234 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
235 T1SystemEncoding<0x30>; // A8.6.409
237 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
238 T1SystemEncoding<0x40>; // A8.6.157
240 // The imm operand $val can be used by a debugger to store more information
241 // about the breakpoint.
242 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
244 T1Encoding<0b101111> {
245 let Inst{9-8} = 0b10;
251 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
252 []>, T1Encoding<0b101101> {
255 let Inst{9-5} = 0b10010;
258 let Inst{2-0} = 0b000;
261 // Change Processor State is a system instruction -- for disassembly only.
262 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
263 NoItinerary, "cps$imod $iflags",
264 [/* For disassembly only; pattern left blank */]>,
272 let Inst{2-0} = iflags;
273 let DecoderMethod = "DecodeThumbCPS";
276 // For both thumb1 and thumb2.
277 let isNotDuplicable = 1, isCodeGenOnly = 1 in
278 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
279 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
280 T1Special<{0,0,?,?}> {
283 let Inst{6-3} = 0b1111; // Rm = pc
287 // ADD <Rd>, sp, #<imm8>
288 // This is rematerializable, which is particularly useful for taking the
289 // address of locals.
290 let isReMaterializable = 1 in
291 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
292 "add\t$dst, $sp, $rhs", []>,
293 T1Encoding<{1,0,1,0,1,?}> {
297 let Inst{10-8} = dst;
299 let DecoderMethod = "DecodeThumbAddSpecialReg";
302 // ADD sp, sp, #<imm7>
303 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
304 "add\t$dst, $rhs", []>,
305 T1Misc<{0,0,0,0,0,?,?}> {
309 let DecoderMethod = "DecodeThumbAddSPImm";
312 // SUB sp, sp, #<imm7>
313 // FIXME: The encoding and the ASM string don't match up.
314 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
315 "sub\t$dst, $rhs", []>,
316 T1Misc<{0,0,0,0,1,?,?}> {
320 let DecoderMethod = "DecodeThumbAddSPImm";
324 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
325 "add\t$dst, $rhs", []>,
326 T1Special<{0,0,?,?}> {
327 // A8.6.9 Encoding T1
329 let Inst{7} = dst{3};
330 let Inst{6-3} = 0b1101;
331 let Inst{2-0} = dst{2-0};
332 let DecoderMethod = "DecodeThumbAddSPReg";
336 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
337 "add\t$dst, $rhs", []>,
338 T1Special<{0,0,?,?}> {
339 // A8.6.9 Encoding T2
343 let Inst{2-0} = 0b101;
344 let DecoderMethod = "DecodeThumbAddSPReg";
347 //===----------------------------------------------------------------------===//
348 // Control Flow Instructions.
352 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
353 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
354 T1Special<{1,1,0,?}> {
358 let Inst{2-0} = 0b000;
362 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
363 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
364 [(ARMretflag)], (tBX LR, pred:$p)>;
366 // Alternative return instruction used by vararg functions.
367 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
369 (tBX GPR:$Rm, pred:$p)>;
372 // All calls clobber the non-callee saved registers. SP is marked as a use to
373 // prevent stack-pointer assignments that appear immediately before calls from
374 // potentially appearing dead.
376 // On non-Darwin platforms R9 is callee-saved.
377 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
379 // Also used for Thumb2
380 def tBL : TIx2<0b11110, 0b11, 1,
381 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
383 [(ARMtcall tglobaladdr:$func)]>,
384 Requires<[IsThumb, IsNotDarwin]> {
386 let Inst{26} = func{21};
387 let Inst{25-16} = func{20-11};
390 let Inst{10-0} = func{10-0};
393 // ARMv5T and above, also used for Thumb2
394 def tBLXi : TIx2<0b11110, 0b11, 0,
395 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
397 [(ARMcall tglobaladdr:$func)]>,
398 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
400 let Inst{25-16} = func{20-11};
403 let Inst{10-1} = func{10-1};
404 let Inst{0} = 0; // func{0} is assumed zero
407 // Also used for Thumb2
408 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
410 [(ARMtcall GPR:$func)]>,
411 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
412 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
414 let Inst{6-3} = func;
415 let Inst{2-0} = 0b000;
419 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
421 [(ARMcall_nolink tGPR:$func)]>,
422 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
426 // On Darwin R9 is call-clobbered.
427 // R7 is marked as a use to prevent frame-pointer assignments from being
428 // moved above / below calls.
429 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
431 // Also used for Thumb2
432 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
433 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
434 (tBL pred:$p, t_bltarget:$func)>,
435 Requires<[IsThumb, IsDarwin]>;
437 // ARMv5T and above, also used for Thumb2
438 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
439 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
440 (tBLXi pred:$p, t_blxtarget:$func)>,
441 Requires<[IsThumb, HasV5T, IsDarwin]>;
443 // Also used for Thumb2
444 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
445 2, IIC_Br, [(ARMtcall GPR:$func)],
446 (tBLXr pred:$p, GPR:$func)>,
447 Requires<[IsThumb, HasV5T, IsDarwin]>;
450 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
452 [(ARMcall_nolink tGPR:$func)]>,
453 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
456 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
457 let isPredicable = 1 in
458 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
459 "b\t$target", [(br bb:$target)]>,
460 T1Encoding<{1,1,1,0,0,?}> {
462 let Inst{10-0} = target;
466 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
467 // the clobber of LR.
469 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
470 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
472 def tBR_JTr : tPseudoInst<(outs),
473 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
475 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
476 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
480 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
481 // a two-value operand where a dag node expects two operands. :(
482 let isBranch = 1, isTerminator = 1 in
483 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
485 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
486 T1BranchCond<{1,1,0,1}> {
490 let Inst{7-0} = target;
494 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
496 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
498 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
499 // on Darwin), so it's in ARMInstrThumb2.td.
500 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
502 (tBX GPR:$dst, (ops 14, zero_reg))>,
503 Requires<[IsThumb, IsDarwin]>;
505 // Non-Darwin versions (the difference is R9).
506 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
508 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
510 (tB t_brtarget:$dst)>,
511 Requires<[IsThumb, IsNotDarwin]>;
512 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
514 (tBX GPR:$dst, (ops 14, zero_reg))>,
515 Requires<[IsThumb, IsNotDarwin]>;
520 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
521 // A8.6.16 B: Encoding T1
522 // If Inst{11-8} == 0b1111 then SEE SVC
523 let isCall = 1, Uses = [SP] in
524 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
525 "svc", "\t$imm", []>, Encoding16 {
527 let Inst{15-12} = 0b1101;
528 let Inst{11-8} = 0b1111;
532 // The assembler uses 0xDEFE for a trap instruction.
533 let isBarrier = 1, isTerminator = 1 in
534 def tTRAP : TI<(outs), (ins), IIC_Br,
535 "trap", [(trap)]>, Encoding16 {
539 //===----------------------------------------------------------------------===//
540 // Load Store Instructions.
543 // Loads: reg/reg and reg/imm5
544 let canFoldAsLoad = 1, isReMaterializable = 1 in
545 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
546 Operand AddrMode_r, Operand AddrMode_i,
547 AddrMode am, InstrItinClass itin_r,
548 InstrItinClass itin_i, string asm,
551 T1pILdStEncode<reg_opc,
552 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
553 am, itin_r, asm, "\t$Rt, $addr",
554 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
556 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
557 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
558 am, itin_i, asm, "\t$Rt, $addr",
559 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
561 // Stores: reg/reg and reg/imm5
562 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
563 Operand AddrMode_r, Operand AddrMode_i,
564 AddrMode am, InstrItinClass itin_r,
565 InstrItinClass itin_i, string asm,
568 T1pILdStEncode<reg_opc,
569 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
570 am, itin_r, asm, "\t$Rt, $addr",
571 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
573 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
574 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
575 am, itin_i, asm, "\t$Rt, $addr",
576 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
580 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
581 t_addrmode_is4, AddrModeT1_4,
582 IIC_iLoad_r, IIC_iLoad_i, "ldr",
583 UnOpFrag<(load node:$Src)>>;
586 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
587 t_addrmode_is1, AddrModeT1_1,
588 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
589 UnOpFrag<(zextloadi8 node:$Src)>>;
592 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
593 t_addrmode_is2, AddrModeT1_2,
594 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
595 UnOpFrag<(zextloadi16 node:$Src)>>;
597 let AddedComplexity = 10 in
598 def tLDRSB : // A8.6.80
599 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
600 AddrModeT1_1, IIC_iLoad_bh_r,
601 "ldrsb", "\t$Rt, $addr",
602 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
604 let AddedComplexity = 10 in
605 def tLDRSH : // A8.6.84
606 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
607 AddrModeT1_2, IIC_iLoad_bh_r,
608 "ldrsh", "\t$Rt, $addr",
609 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
611 let canFoldAsLoad = 1 in
612 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
613 "ldr", "\t$Rt, $addr",
614 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
619 let Inst{7-0} = addr;
623 // FIXME: Use ldr.n to work around a Darwin assembler bug.
624 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
625 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
626 "ldr", ".n\t$Rt, $addr",
627 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
628 T1Encoding<{0,1,0,0,1,?}> {
633 let Inst{7-0} = addr;
636 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
637 // For disassembly use only.
638 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
639 "ldr", "\t$Rt, $addr",
640 [/* disassembly only */]>,
641 T1Encoding<{0,1,0,0,1,?}> {
646 let Inst{7-0} = addr;
649 // A8.6.194 & A8.6.192
650 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
651 t_addrmode_is4, AddrModeT1_4,
652 IIC_iStore_r, IIC_iStore_i, "str",
653 BinOpFrag<(store node:$LHS, node:$RHS)>>;
655 // A8.6.197 & A8.6.195
656 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
657 t_addrmode_is1, AddrModeT1_1,
658 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
659 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
661 // A8.6.207 & A8.6.205
662 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
663 t_addrmode_is2, AddrModeT1_2,
664 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
665 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
668 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
669 "str", "\t$Rt, $addr",
670 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
675 let Inst{7-0} = addr;
678 //===----------------------------------------------------------------------===//
679 // Load / store multiple Instructions.
682 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
683 InstrItinClass itin_upd, bits<6> T1Enc,
684 bit L_bit, string baseOpc> {
686 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
687 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
692 let Inst{7-0} = regs;
696 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
697 "$Rn = $wb", itin_upd>,
698 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
699 GPR:$Rn, pred:$p, reglist:$regs)> {
701 let OutOperandList = (outs GPR:$wb);
702 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
704 let isCodeGenOnly = 1;
706 list<Predicate> Predicates = [IsThumb];
710 // These require base address to be written back or one of the loaded regs.
711 let neverHasSideEffects = 1 in {
713 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
714 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
715 {1,1,0,0,1,?}, 1, "tLDM">;
717 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
718 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
719 {1,1,0,0,0,?}, 0, "tSTM">;
721 } // neverHasSideEffects
723 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
724 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
726 "pop${p}\t$regs", []>,
727 T1Misc<{1,1,0,?,?,?,?}> {
729 let Inst{8} = regs{15};
730 let Inst{7-0} = regs{7-0};
733 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
734 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
736 "push${p}\t$regs", []>,
737 T1Misc<{0,1,0,?,?,?,?}> {
739 let Inst{8} = regs{14};
740 let Inst{7-0} = regs{7-0};
743 //===----------------------------------------------------------------------===//
744 // Arithmetic Instructions.
747 // Helper classes for encoding T1pI patterns:
748 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
749 string opc, string asm, list<dag> pattern>
750 : T1pI<oops, iops, itin, opc, asm, pattern>,
751 T1DataProcessing<opA> {
757 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
758 string opc, string asm, list<dag> pattern>
759 : T1pI<oops, iops, itin, opc, asm, pattern>,
767 // Helper classes for encoding T1sI patterns:
768 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
769 string opc, string asm, list<dag> pattern>
770 : T1sI<oops, iops, itin, opc, asm, pattern>,
771 T1DataProcessing<opA> {
777 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
778 string opc, string asm, list<dag> pattern>
779 : T1sI<oops, iops, itin, opc, asm, pattern>,
788 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : T1sI<oops, iops, itin, opc, asm, pattern>,
798 // Helper classes for encoding T1sIt patterns:
799 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
800 string opc, string asm, list<dag> pattern>
801 : T1sIt<oops, iops, itin, opc, asm, pattern>,
802 T1DataProcessing<opA> {
808 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : T1sIt<oops, iops, itin, opc, asm, pattern>,
814 let Inst{10-8} = Rdn;
815 let Inst{7-0} = imm8;
818 // Add with carry register
819 let isCommutable = 1, Uses = [CPSR] in
821 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
822 "adc", "\t$Rdn, $Rm",
823 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
826 def tADDi3 : // A8.6.4 T1
827 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
829 "add", "\t$Rd, $Rm, $imm3",
830 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
832 let Inst{8-6} = imm3;
835 def tADDi8 : // A8.6.4 T2
836 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
837 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
838 "add", "\t$Rdn, $imm8",
839 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
842 let isCommutable = 1 in
843 def tADDrr : // A8.6.6 T1
844 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
846 "add", "\t$Rd, $Rn, $Rm",
847 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
849 let neverHasSideEffects = 1 in
850 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
851 "add", "\t$Rdn, $Rm", []>,
852 T1Special<{0,0,?,?}> {
856 let Inst{7} = Rdn{3};
858 let Inst{2-0} = Rdn{2-0};
862 let isCommutable = 1 in
863 def tAND : // A8.6.12
864 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
866 "and", "\t$Rdn, $Rm",
867 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
870 def tASRri : // A8.6.14
871 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
873 "asr", "\t$Rd, $Rm, $imm5",
874 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
876 let Inst{10-6} = imm5;
880 def tASRrr : // A8.6.15
881 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
883 "asr", "\t$Rdn, $Rm",
884 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
887 def tBIC : // A8.6.20
888 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
890 "bic", "\t$Rdn, $Rm",
891 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
894 let isCompare = 1, Defs = [CPSR] in {
895 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
896 // Compare-to-zero still works out, just not the relationals
897 //def tCMN : // A8.6.33
898 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
900 // "cmn", "\t$lhs, $rhs",
901 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
903 def tCMNz : // A8.6.33
904 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
907 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
909 } // isCompare = 1, Defs = [CPSR]
912 let isCompare = 1, Defs = [CPSR] in {
913 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
914 "cmp", "\t$Rn, $imm8",
915 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
916 T1General<{1,0,1,?,?}> {
921 let Inst{7-0} = imm8;
925 def tCMPr : // A8.6.36 T1
926 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
929 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
931 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
932 "cmp", "\t$Rn, $Rm", []>,
933 T1Special<{0,1,?,?}> {
939 let Inst{2-0} = Rn{2-0};
941 } // isCompare = 1, Defs = [CPSR]
945 let isCommutable = 1 in
946 def tEOR : // A8.6.45
947 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
949 "eor", "\t$Rdn, $Rm",
950 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
953 def tLSLri : // A8.6.88
954 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
956 "lsl", "\t$Rd, $Rm, $imm5",
957 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
959 let Inst{10-6} = imm5;
963 def tLSLrr : // A8.6.89
964 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
966 "lsl", "\t$Rdn, $Rm",
967 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
970 def tLSRri : // A8.6.90
971 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
973 "lsr", "\t$Rd, $Rm, $imm5",
974 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
976 let Inst{10-6} = imm5;
980 def tLSRrr : // A8.6.91
981 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
983 "lsr", "\t$Rdn, $Rm",
984 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
988 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
989 "mov", "\t$Rd, $imm8",
990 [(set tGPR:$Rd, imm0_255:$imm8)]>,
991 T1General<{1,0,0,?,?}> {
996 let Inst{7-0} = imm8;
999 // A7-73: MOV(2) - mov setting flag.
1001 let neverHasSideEffects = 1 in {
1002 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1004 "mov", "\t$Rd, $Rm", "", []>,
1005 T1Special<{1,0,?,?}> {
1009 let Inst{7} = Rd{3};
1011 let Inst{2-0} = Rd{2-0};
1013 let Defs = [CPSR] in
1014 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1015 "movs\t$Rd, $Rm", []>, Encoding16 {
1019 let Inst{15-6} = 0b0000000000;
1023 } // neverHasSideEffects
1025 // Multiply register
1026 let isCommutable = 1 in
1027 def tMUL : // A8.6.105 T1
1028 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1030 "mul", "\t$Rdn, $Rm, $Rdn",
1031 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1033 // Move inverse register
1034 def tMVN : // A8.6.107
1035 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1036 "mvn", "\t$Rd, $Rn",
1037 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1039 // Bitwise or register
1040 let isCommutable = 1 in
1041 def tORR : // A8.6.114
1042 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1044 "orr", "\t$Rdn, $Rm",
1045 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1048 def tREV : // A8.6.134
1049 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1051 "rev", "\t$Rd, $Rm",
1052 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1053 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1055 def tREV16 : // A8.6.135
1056 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1058 "rev16", "\t$Rd, $Rm",
1059 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1060 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1062 def tREVSH : // A8.6.136
1063 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1065 "revsh", "\t$Rd, $Rm",
1066 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1067 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1069 // Rotate right register
1070 def tROR : // A8.6.139
1071 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1073 "ror", "\t$Rdn, $Rm",
1074 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1077 def tRSB : // A8.6.141
1078 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1080 "rsb", "\t$Rd, $Rn, #0",
1081 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1083 // Subtract with carry register
1084 let Uses = [CPSR] in
1085 def tSBC : // A8.6.151
1086 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1088 "sbc", "\t$Rdn, $Rm",
1089 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1091 // Subtract immediate
1092 def tSUBi3 : // A8.6.210 T1
1093 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1095 "sub", "\t$Rd, $Rm, $imm3",
1096 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1098 let Inst{8-6} = imm3;
1101 def tSUBi8 : // A8.6.210 T2
1102 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1104 "sub", "\t$Rdn, $imm8",
1105 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1107 // Subtract register
1108 def tSUBrr : // A8.6.212
1109 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1111 "sub", "\t$Rd, $Rn, $Rm",
1112 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1114 // TODO: A7-96: STMIA - store multiple.
1117 def tSXTB : // A8.6.222
1118 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1120 "sxtb", "\t$Rd, $Rm",
1121 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1122 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1124 // Sign-extend short
1125 def tSXTH : // A8.6.224
1126 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1128 "sxth", "\t$Rd, $Rm",
1129 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1130 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1133 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1134 def tTST : // A8.6.230
1135 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1136 "tst", "\t$Rn, $Rm",
1137 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1140 def tUXTB : // A8.6.262
1141 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1143 "uxtb", "\t$Rd, $Rm",
1144 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1145 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1147 // Zero-extend short
1148 def tUXTH : // A8.6.264
1149 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1151 "uxth", "\t$Rd, $Rm",
1152 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1153 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1155 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1156 // Expanded after instruction selection into a branch sequence.
1157 let usesCustomInserter = 1 in // Expanded after instruction selection.
1158 def tMOVCCr_pseudo :
1159 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1161 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1163 // tLEApcrel - Load a pc-relative address into a register without offending the
1166 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1167 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1168 T1Encoding<{1,0,1,0,0,?}> {
1171 let Inst{10-8} = Rd;
1172 let Inst{7-0} = addr;
1173 let DecoderMethod = "DecodeThumbAddSpecialReg";
1176 let neverHasSideEffects = 1, isReMaterializable = 1 in
1177 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1180 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1181 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1184 //===----------------------------------------------------------------------===//
1188 // __aeabi_read_tp preserves the registers r1-r3.
1189 // This is a pseudo inst so that we can get the encoding right,
1190 // complete with fixup for the aeabi_read_tp function.
1191 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1192 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1193 [(set R0, ARMthread_pointer)]>;
1195 //===----------------------------------------------------------------------===//
1196 // SJLJ Exception handling intrinsics
1199 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1200 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1201 // from some other function to get here, and we're using the stack frame for the
1202 // containing function to save/restore registers, we can't keep anything live in
1203 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1204 // tromped upon when we get here from a longjmp(). We force everything out of
1205 // registers except for our own input by listing the relevant registers in
1206 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1207 // preserve all of the callee-saved resgisters, which is exactly what we want.
1208 // $val is a scratch register for our use.
1209 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1210 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1211 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1212 AddrModeNone, 0, NoItinerary, "","",
1213 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1215 // FIXME: Non-Darwin version(s)
1216 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1217 Defs = [ R7, LR, SP ] in
1218 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1219 AddrModeNone, 0, IndexModeNone,
1220 Pseudo, NoItinerary, "", "",
1221 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1222 Requires<[IsThumb, IsDarwin]>;
1224 //===----------------------------------------------------------------------===//
1225 // Non-Instruction Patterns
1229 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1230 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1231 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1232 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1235 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1236 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1237 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1238 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1239 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1240 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1242 // Subtract with carry
1243 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1244 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1245 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1246 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1247 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1248 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1250 // ConstantPool, GlobalAddress
1251 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1252 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1255 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1256 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1259 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1260 Requires<[IsThumb, IsNotDarwin]>;
1261 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1262 Requires<[IsThumb, IsDarwin]>;
1264 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1265 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1266 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1267 Requires<[IsThumb, HasV5T, IsDarwin]>;
1269 // Indirect calls to ARM routines
1270 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1271 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1272 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1273 Requires<[IsThumb, HasV5T, IsDarwin]>;
1275 // zextload i1 -> zextload i8
1276 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1277 (tLDRBr t_addrmode_rrs1:$addr)>;
1278 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1279 (tLDRBi t_addrmode_is1:$addr)>;
1281 // extload -> zextload
1282 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1283 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1284 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1285 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1286 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1287 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1289 // If it's impossible to use [r,r] address mode for sextload, select to
1290 // ldr{b|h} + sxt{b|h} instead.
1291 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1292 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1293 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1294 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1295 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1296 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1297 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1298 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1299 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1300 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1301 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1302 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1304 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1305 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1306 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1307 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1308 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1309 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1310 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1311 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1313 // Large immediate handling.
1316 def : T1Pat<(i32 thumb_immshifted:$src),
1317 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1318 (thumb_immshifted_shamt imm:$src))>;
1320 def : T1Pat<(i32 imm0_255_comp:$src),
1321 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1323 // Pseudo instruction that combines ldr from constpool and add pc. This should
1324 // be expanded into two instructions late to allow if-conversion and
1326 let isReMaterializable = 1 in
1327 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1329 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1331 Requires<[IsThumb, IsThumb1Only]>;
1333 // Pseudo-instruction for merged POP and return.
1334 // FIXME: remove when we have a way to marking a MI with these properties.
1335 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1336 hasExtraDefRegAllocReq = 1 in
1337 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1339 (tPOP pred:$p, reglist:$regs)>;
1341 // Indirect branch using "mov pc, $Rm"
1342 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1343 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1344 2, IIC_Br, [(brind GPR:$Rm)],
1345 (tMOVr PC, GPR:$Rm, pred:$p)>;