1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
82 def t_imm0_1020s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_1020s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
89 def t_imm0_508s4 : Operand<i32> {
90 let PrintMethod = "printThumbS4ImmOperand";
91 let ParserMatchClass = t_imm0_508s4_asmoperand;
92 let OperandType = "OPERAND_IMMEDIATE";
94 // Alias use only, so no printer is necessary.
95 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
96 def t_imm0_508s4_neg : Operand<i32> {
97 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
98 let OperandType = "OPERAND_IMMEDIATE";
101 // Define Thumb specific addressing modes.
103 let OperandType = "OPERAND_PCREL" in {
104 def t_brtarget : Operand<OtherVT> {
105 let EncoderMethod = "getThumbBRTargetOpValue";
106 let DecoderMethod = "DecodeThumbBROperand";
109 def t_bcctarget : Operand<i32> {
110 let EncoderMethod = "getThumbBCCTargetOpValue";
111 let DecoderMethod = "DecodeThumbBCCTargetOperand";
114 def t_cbtarget : Operand<i32> {
115 let EncoderMethod = "getThumbCBTargetOpValue";
116 let DecoderMethod = "DecodeThumbCmpBROperand";
119 def t_bltarget : Operand<i32> {
120 let EncoderMethod = "getThumbBLTargetOpValue";
121 let DecoderMethod = "DecodeThumbBLTargetOperand";
124 def t_blxtarget : Operand<i32> {
125 let EncoderMethod = "getThumbBLXTargetOpValue";
126 let DecoderMethod = "DecodeThumbBLXOffset";
130 // t_addrmode_rr := reg + reg
132 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
133 def t_addrmode_rr : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let DecoderMethod = "DecodeThumbAddrModeRR";
138 let ParserMatchClass = t_addrmode_rr_asm_operand;
139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 // t_addrmode_rrs := reg + reg
144 // We use separate scaled versions because the Select* functions need
145 // to explicitly check for a matching constant and return false here so that
146 // the reg+imm forms will match instead. This is a horrible way to do that,
147 // as it forces tight coupling between the methods, but it's how selectiondag
149 def t_addrmode_rrs1 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
151 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
152 let PrintMethod = "printThumbAddrModeRROperand";
153 let DecoderMethod = "DecodeThumbAddrModeRR";
154 let ParserMatchClass = t_addrmode_rr_asm_operand;
155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
157 def t_addrmode_rrs2 : Operand<i32>,
158 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
159 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let PrintMethod = "printThumbAddrModeRROperand";
162 let ParserMatchClass = t_addrmode_rr_asm_operand;
163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
165 def t_addrmode_rrs4 : Operand<i32>,
166 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
167 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
168 let DecoderMethod = "DecodeThumbAddrModeRR";
169 let PrintMethod = "printThumbAddrModeRROperand";
170 let ParserMatchClass = t_addrmode_rr_asm_operand;
171 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
174 // t_addrmode_is4 := reg + imm5 * 4
176 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
177 def t_addrmode_is4 : Operand<i32>,
178 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
179 let EncoderMethod = "getAddrModeISOpValue";
180 let DecoderMethod = "DecodeThumbAddrModeIS";
181 let PrintMethod = "printThumbAddrModeImm5S4Operand";
182 let ParserMatchClass = t_addrmode_is4_asm_operand;
183 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
186 // t_addrmode_is2 := reg + imm5 * 2
188 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
189 def t_addrmode_is2 : Operand<i32>,
190 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
191 let EncoderMethod = "getAddrModeISOpValue";
192 let DecoderMethod = "DecodeThumbAddrModeIS";
193 let PrintMethod = "printThumbAddrModeImm5S2Operand";
194 let ParserMatchClass = t_addrmode_is2_asm_operand;
195 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
198 // t_addrmode_is1 := reg + imm5
200 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
201 def t_addrmode_is1 : Operand<i32>,
202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
203 let EncoderMethod = "getAddrModeISOpValue";
204 let DecoderMethod = "DecodeThumbAddrModeIS";
205 let PrintMethod = "printThumbAddrModeImm5S1Operand";
206 let ParserMatchClass = t_addrmode_is1_asm_operand;
207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
210 // t_addrmode_sp := sp + imm8 * 4
212 // FIXME: This really shouldn't have an explicit SP operand at all. It should
213 // be implicit, just like in the instruction encoding itself.
214 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
215 def t_addrmode_sp : Operand<i32>,
216 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
217 let EncoderMethod = "getAddrModeThumbSPOpValue";
218 let DecoderMethod = "DecodeThumbAddrModeSP";
219 let PrintMethod = "printThumbAddrModeSPOperand";
220 let ParserMatchClass = t_addrmode_sp_asm_operand;
221 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
224 // t_addrmode_pc := <label> => pc + imm8 * 4
226 def t_addrmode_pc : Operand<i32> {
227 let EncoderMethod = "getAddrModePCOpValue";
228 let DecoderMethod = "DecodeThumbAddrModePC";
231 //===----------------------------------------------------------------------===//
232 // Miscellaneous Instructions.
235 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
236 // from removing one half of the matched pairs. That breaks PEI, which assumes
237 // these will always be in pairs, and asserts if it finds otherwise. Better way?
238 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
239 def tADJCALLSTACKUP :
240 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
241 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
242 Requires<[IsThumb, IsThumb1Only]>;
244 def tADJCALLSTACKDOWN :
245 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
246 [(ARMcallseq_start imm:$amt)]>,
247 Requires<[IsThumb, IsThumb1Only]>;
250 class T1SystemEncoding<bits<8> opc>
251 : T1Encoding<0b101111> {
252 let Inst{9-8} = 0b11;
256 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
257 T1SystemEncoding<0x00>, // A8.6.110
258 Requires<[IsThumb2]>;
260 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
261 T1SystemEncoding<0x10>; // A8.6.410
263 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
264 T1SystemEncoding<0x20>; // A8.6.408
266 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
267 T1SystemEncoding<0x30>; // A8.6.409
269 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
270 T1SystemEncoding<0x40>; // A8.6.157
272 // The imm operand $val can be used by a debugger to store more information
273 // about the breakpoint.
274 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
276 T1Encoding<0b101111> {
277 let Inst{9-8} = 0b10;
283 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
284 []>, T1Encoding<0b101101> {
287 let Inst{9-5} = 0b10010;
290 let Inst{2-0} = 0b000;
293 // Change Processor State is a system instruction -- for disassembly only.
294 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
295 NoItinerary, "cps$imod $iflags", []>,
303 let Inst{2-0} = iflags;
304 let DecoderMethod = "DecodeThumbCPS";
307 // For both thumb1 and thumb2.
308 let isNotDuplicable = 1, isCodeGenOnly = 1 in
309 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
310 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
311 T1Special<{0,0,?,?}> {
314 let Inst{6-3} = 0b1111; // Rm = pc
318 // ADD <Rd>, sp, #<imm8>
319 // FIXME: This should not be marked as having side effects, and it should be
320 // rematerializable. Clearing the side effect bit causes miscompilations,
321 // probably because the instruction can be moved around.
322 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
323 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
324 T1Encoding<{1,0,1,0,1,?}> {
328 let Inst{10-8} = dst;
330 let DecoderMethod = "DecodeThumbAddSpecialReg";
333 // ADD sp, sp, #<imm7>
334 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
335 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
336 T1Misc<{0,0,0,0,0,?,?}> {
340 let DecoderMethod = "DecodeThumbAddSPImm";
343 // SUB sp, sp, #<imm7>
344 // FIXME: The encoding and the ASM string don't match up.
345 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
346 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
347 T1Misc<{0,0,0,0,1,?,?}> {
351 let DecoderMethod = "DecodeThumbAddSPImm";
354 def : tInstAlias<"add${p} sp, $imm",
355 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
356 def : tInstAlias<"add${p} sp, sp, $imm",
357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
359 // Can optionally specify SP as a three operand instruction.
360 def : tInstAlias<"add${p} sp, sp, $imm",
361 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
362 def : tInstAlias<"sub${p} sp, sp, $imm",
363 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
366 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
367 "add", "\t$Rdn, $sp, $Rn", []>,
368 T1Special<{0,0,?,?}> {
369 // A8.6.9 Encoding T1
371 let Inst{7} = Rdn{3};
372 let Inst{6-3} = 0b1101;
373 let Inst{2-0} = Rdn{2-0};
374 let DecoderMethod = "DecodeThumbAddSPReg";
378 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
379 "add", "\t$Rdn, $Rm", []>,
380 T1Special<{0,0,?,?}> {
381 // A8.6.9 Encoding T2
385 let Inst{2-0} = 0b101;
386 let DecoderMethod = "DecodeThumbAddSPReg";
389 //===----------------------------------------------------------------------===//
390 // Control Flow Instructions.
394 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
395 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
396 T1Special<{1,1,0,?}> {
400 let Inst{2-0} = 0b000;
401 let Unpredictable{2-0} = 0b111;
405 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
406 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
407 [(ARMretflag)], (tBX LR, pred:$p)>;
409 // Alternative return instruction used by vararg functions.
410 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
412 (tBX GPR:$Rm, pred:$p)>;
415 // All calls clobber the non-callee saved registers. SP is marked as a use to
416 // prevent stack-pointer assignments that appear immediately before calls from
417 // potentially appearing dead.
419 Defs = [LR], Uses = [SP] in {
420 // Also used for Thumb2
421 def tBL : TIx2<0b11110, 0b11, 1,
422 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
424 [(ARMtcall tglobaladdr:$func)]>,
425 Requires<[IsThumb]> {
427 let Inst{26} = func{21};
428 let Inst{25-16} = func{20-11};
431 let Inst{10-0} = func{10-0};
434 // ARMv5T and above, also used for Thumb2
435 def tBLXi : TIx2<0b11110, 0b11, 0,
436 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
438 [(ARMcall tglobaladdr:$func)]>,
439 Requires<[IsThumb, HasV5T]> {
441 let Inst{25-16} = func{20-11};
444 let Inst{10-1} = func{10-1};
445 let Inst{0} = 0; // func{0} is assumed zero
448 // Also used for Thumb2
449 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
451 [(ARMtcall GPR:$func)]>,
452 Requires<[IsThumb, HasV5T]>,
453 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
455 let Inst{6-3} = func;
456 let Inst{2-0} = 0b000;
460 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
462 [(ARMcall_nolink tGPR:$func)]>,
463 Requires<[IsThumb, IsThumb1Only]>;
466 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
467 let isPredicable = 1 in
468 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
469 "b", "\t$target", [(br bb:$target)]>,
470 T1Encoding<{1,1,1,0,0,?}> {
472 let Inst{10-0} = target;
476 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
477 // the clobber of LR.
479 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
480 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
482 def tBR_JTr : tPseudoInst<(outs),
483 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
485 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
486 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
490 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
491 // a two-value operand where a dag node expects two operands. :(
492 let isBranch = 1, isTerminator = 1 in
493 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
495 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
496 T1BranchCond<{1,1,0,1}> {
500 let Inst{7-0} = target;
504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
507 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
508 // on IOS), so it's in ARMInstrThumb2.td.
509 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
511 (tBX GPR:$dst, (ops 14, zero_reg))>,
512 Requires<[IsThumb, IsIOS]>;
514 // Non-IOS versions (the difference is R9).
516 def tTAILJMPdND : tPseudoExpand<(outs),
517 (ins t_brtarget:$dst, pred:$p, variable_ops),
519 (tB t_brtarget:$dst, pred:$p)>,
520 Requires<[IsThumb, IsNotIOS]>;
521 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
523 (tBX GPR:$dst, (ops 14, zero_reg))>,
524 Requires<[IsThumb, IsNotIOS]>;
529 // A8.6.218 Supervisor Call (Software Interrupt)
530 // A8.6.16 B: Encoding T1
531 // If Inst{11-8} == 0b1111 then SEE SVC
532 let isCall = 1, Uses = [SP] in
533 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
534 "svc", "\t$imm", []>, Encoding16 {
536 let Inst{15-12} = 0b1101;
537 let Inst{11-8} = 0b1111;
541 // The assembler uses 0xDEFE for a trap instruction.
542 let isBarrier = 1, isTerminator = 1 in
543 def tTRAP : TI<(outs), (ins), IIC_Br,
544 "trap", [(trap)]>, Encoding16 {
548 //===----------------------------------------------------------------------===//
549 // Load Store Instructions.
552 // Loads: reg/reg and reg/imm5
553 let canFoldAsLoad = 1, isReMaterializable = 1 in
554 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
555 Operand AddrMode_r, Operand AddrMode_i,
556 AddrMode am, InstrItinClass itin_r,
557 InstrItinClass itin_i, string asm,
560 T1pILdStEncode<reg_opc,
561 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
562 am, itin_r, asm, "\t$Rt, $addr",
563 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
565 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
566 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
567 am, itin_i, asm, "\t$Rt, $addr",
568 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
570 // Stores: reg/reg and reg/imm5
571 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
572 Operand AddrMode_r, Operand AddrMode_i,
573 AddrMode am, InstrItinClass itin_r,
574 InstrItinClass itin_i, string asm,
577 T1pILdStEncode<reg_opc,
578 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
579 am, itin_r, asm, "\t$Rt, $addr",
580 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
582 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
583 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
584 am, itin_i, asm, "\t$Rt, $addr",
585 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
589 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
590 t_addrmode_is4, AddrModeT1_4,
591 IIC_iLoad_r, IIC_iLoad_i, "ldr",
592 UnOpFrag<(load node:$Src)>>;
595 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
596 t_addrmode_is1, AddrModeT1_1,
597 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
598 UnOpFrag<(zextloadi8 node:$Src)>>;
601 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
602 t_addrmode_is2, AddrModeT1_2,
603 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
604 UnOpFrag<(zextloadi16 node:$Src)>>;
606 let AddedComplexity = 10 in
607 def tLDRSB : // A8.6.80
608 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
609 AddrModeT1_1, IIC_iLoad_bh_r,
610 "ldrsb", "\t$Rt, $addr",
611 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
613 let AddedComplexity = 10 in
614 def tLDRSH : // A8.6.84
615 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
616 AddrModeT1_2, IIC_iLoad_bh_r,
617 "ldrsh", "\t$Rt, $addr",
618 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
620 let canFoldAsLoad = 1 in
621 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
622 "ldr", "\t$Rt, $addr",
623 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
628 let Inst{7-0} = addr;
632 // FIXME: Use ldr.n to work around a darwin assembler bug.
633 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
634 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
635 "ldr", ".n\t$Rt, $addr",
636 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
637 T1Encoding<{0,1,0,0,1,?}> {
642 let Inst{7-0} = addr;
645 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
646 // For assembly/disassembly use only.
647 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
648 "ldr", "\t$Rt, $addr", []>,
649 T1Encoding<{0,1,0,0,1,?}> {
654 let Inst{7-0} = addr;
657 // A8.6.194 & A8.6.192
658 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
659 t_addrmode_is4, AddrModeT1_4,
660 IIC_iStore_r, IIC_iStore_i, "str",
661 BinOpFrag<(store node:$LHS, node:$RHS)>>;
663 // A8.6.197 & A8.6.195
664 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
665 t_addrmode_is1, AddrModeT1_1,
666 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
667 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
669 // A8.6.207 & A8.6.205
670 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
671 t_addrmode_is2, AddrModeT1_2,
672 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
673 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
676 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
677 "str", "\t$Rt, $addr",
678 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
683 let Inst{7-0} = addr;
686 //===----------------------------------------------------------------------===//
687 // Load / store multiple Instructions.
690 // These require base address to be written back or one of the loaded regs.
691 let neverHasSideEffects = 1 in {
693 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
694 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
695 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
699 let Inst{7-0} = regs;
702 // Writeback version is just a pseudo, as there's no encoding difference.
703 // Writeback happens iff the base register is not in the destination register
706 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
707 "$Rn = $wb", IIC_iLoad_mu>,
708 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
710 let OutOperandList = (outs GPR:$wb);
711 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
713 let isCodeGenOnly = 1;
715 list<Predicate> Predicates = [IsThumb];
718 // There is no non-writeback version of STM for Thumb.
719 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
720 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
721 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
722 AddrModeNone, 2, IIC_iStore_mu,
723 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
724 T1Encoding<{1,1,0,0,0,?}> {
728 let Inst{7-0} = regs;
731 } // neverHasSideEffects
733 def : InstAlias<"ldm${p} $Rn!, $regs",
734 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
735 Requires<[IsThumb, IsThumb1Only]>;
737 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
738 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
740 "pop${p}\t$regs", []>,
741 T1Misc<{1,1,0,?,?,?,?}> {
743 let Inst{8} = regs{15};
744 let Inst{7-0} = regs{7-0};
747 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
748 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
750 "push${p}\t$regs", []>,
751 T1Misc<{0,1,0,?,?,?,?}> {
753 let Inst{8} = regs{14};
754 let Inst{7-0} = regs{7-0};
757 //===----------------------------------------------------------------------===//
758 // Arithmetic Instructions.
761 // Helper classes for encoding T1pI patterns:
762 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
763 string opc, string asm, list<dag> pattern>
764 : T1pI<oops, iops, itin, opc, asm, pattern>,
765 T1DataProcessing<opA> {
771 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
772 string opc, string asm, list<dag> pattern>
773 : T1pI<oops, iops, itin, opc, asm, pattern>,
781 // Helper classes for encoding T1sI patterns:
782 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
783 string opc, string asm, list<dag> pattern>
784 : T1sI<oops, iops, itin, opc, asm, pattern>,
785 T1DataProcessing<opA> {
791 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
792 string opc, string asm, list<dag> pattern>
793 : T1sI<oops, iops, itin, opc, asm, pattern>,
802 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
803 string opc, string asm, list<dag> pattern>
804 : T1sI<oops, iops, itin, opc, asm, pattern>,
812 // Helper classes for encoding T1sIt patterns:
813 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
814 string opc, string asm, list<dag> pattern>
815 : T1sIt<oops, iops, itin, opc, asm, pattern>,
816 T1DataProcessing<opA> {
822 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
823 string opc, string asm, list<dag> pattern>
824 : T1sIt<oops, iops, itin, opc, asm, pattern>,
828 let Inst{10-8} = Rdn;
829 let Inst{7-0} = imm8;
832 // Add with carry register
833 let isCommutable = 1, Uses = [CPSR] in
835 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
836 "adc", "\t$Rdn, $Rm",
837 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
840 def tADDi3 : // A8.6.4 T1
841 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
843 "add", "\t$Rd, $Rm, $imm3",
844 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
846 let Inst{8-6} = imm3;
849 def tADDi8 : // A8.6.4 T2
850 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
851 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
852 "add", "\t$Rdn, $imm8",
853 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
856 let isCommutable = 1 in
857 def tADDrr : // A8.6.6 T1
858 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
860 "add", "\t$Rd, $Rn, $Rm",
861 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
863 let neverHasSideEffects = 1 in
864 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
865 "add", "\t$Rdn, $Rm", []>,
866 T1Special<{0,0,?,?}> {
870 let Inst{7} = Rdn{3};
872 let Inst{2-0} = Rdn{2-0};
876 let isCommutable = 1 in
877 def tAND : // A8.6.12
878 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
880 "and", "\t$Rdn, $Rm",
881 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
884 def tASRri : // A8.6.14
885 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
887 "asr", "\t$Rd, $Rm, $imm5",
888 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
890 let Inst{10-6} = imm5;
894 def tASRrr : // A8.6.15
895 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
897 "asr", "\t$Rdn, $Rm",
898 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
901 def tBIC : // A8.6.20
902 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
904 "bic", "\t$Rdn, $Rm",
905 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
908 let isCompare = 1, Defs = [CPSR] in {
909 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
910 // Compare-to-zero still works out, just not the relationals
911 //def tCMN : // A8.6.33
912 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
914 // "cmn", "\t$lhs, $rhs",
915 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
917 def tCMNz : // A8.6.33
918 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
921 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
923 } // isCompare = 1, Defs = [CPSR]
926 let isCompare = 1, Defs = [CPSR] in {
927 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
928 "cmp", "\t$Rn, $imm8",
929 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
930 T1General<{1,0,1,?,?}> {
935 let Inst{7-0} = imm8;
939 def tCMPr : // A8.6.36 T1
940 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
943 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
945 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
946 "cmp", "\t$Rn, $Rm", []>,
947 T1Special<{0,1,?,?}> {
953 let Inst{2-0} = Rn{2-0};
955 } // isCompare = 1, Defs = [CPSR]
959 let isCommutable = 1 in
960 def tEOR : // A8.6.45
961 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
963 "eor", "\t$Rdn, $Rm",
964 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
967 def tLSLri : // A8.6.88
968 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
970 "lsl", "\t$Rd, $Rm, $imm5",
971 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
973 let Inst{10-6} = imm5;
977 def tLSLrr : // A8.6.89
978 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
980 "lsl", "\t$Rdn, $Rm",
981 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
984 def tLSRri : // A8.6.90
985 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
987 "lsr", "\t$Rd, $Rm, $imm5",
988 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
990 let Inst{10-6} = imm5;
994 def tLSRrr : // A8.6.91
995 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
997 "lsr", "\t$Rdn, $Rm",
998 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1001 let isMoveImm = 1 in
1002 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1003 "mov", "\t$Rd, $imm8",
1004 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1005 T1General<{1,0,0,?,?}> {
1009 let Inst{10-8} = Rd;
1010 let Inst{7-0} = imm8;
1012 // Because we have an explicit tMOVSr below, we need an alias to handle
1013 // the immediate "movs" form here. Blech.
1014 def : tInstAlias <"movs $Rdn, $imm",
1015 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1017 // A7-73: MOV(2) - mov setting flag.
1019 let neverHasSideEffects = 1 in {
1020 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1022 "mov", "\t$Rd, $Rm", "", []>,
1023 T1Special<{1,0,?,?}> {
1027 let Inst{7} = Rd{3};
1029 let Inst{2-0} = Rd{2-0};
1031 let Defs = [CPSR] in
1032 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1033 "movs\t$Rd, $Rm", []>, Encoding16 {
1037 let Inst{15-6} = 0b0000000000;
1041 } // neverHasSideEffects
1043 // Multiply register
1044 let isCommutable = 1 in
1045 def tMUL : // A8.6.105 T1
1046 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1047 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1048 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1049 T1DataProcessing<0b1101> {
1054 let AsmMatchConverter = "cvtThumbMultiply";
1057 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1060 // Move inverse register
1061 def tMVN : // A8.6.107
1062 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1063 "mvn", "\t$Rd, $Rn",
1064 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1066 // Bitwise or register
1067 let isCommutable = 1 in
1068 def tORR : // A8.6.114
1069 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1071 "orr", "\t$Rdn, $Rm",
1072 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1075 def tREV : // A8.6.134
1076 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1078 "rev", "\t$Rd, $Rm",
1079 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1080 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1082 def tREV16 : // A8.6.135
1083 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1085 "rev16", "\t$Rd, $Rm",
1086 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1087 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1089 def tREVSH : // A8.6.136
1090 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1092 "revsh", "\t$Rd, $Rm",
1093 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1094 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1096 // Rotate right register
1097 def tROR : // A8.6.139
1098 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1100 "ror", "\t$Rdn, $Rm",
1101 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1104 def tRSB : // A8.6.141
1105 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1107 "rsb", "\t$Rd, $Rn, #0",
1108 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1110 // Subtract with carry register
1111 let Uses = [CPSR] in
1112 def tSBC : // A8.6.151
1113 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1115 "sbc", "\t$Rdn, $Rm",
1116 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1118 // Subtract immediate
1119 def tSUBi3 : // A8.6.210 T1
1120 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1122 "sub", "\t$Rd, $Rm, $imm3",
1123 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1125 let Inst{8-6} = imm3;
1128 def tSUBi8 : // A8.6.210 T2
1129 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1130 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1131 "sub", "\t$Rdn, $imm8",
1132 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1134 // Subtract register
1135 def tSUBrr : // A8.6.212
1136 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1138 "sub", "\t$Rd, $Rn, $Rm",
1139 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1142 def tSXTB : // A8.6.222
1143 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1145 "sxtb", "\t$Rd, $Rm",
1146 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1147 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1149 // Sign-extend short
1150 def tSXTH : // A8.6.224
1151 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1153 "sxth", "\t$Rd, $Rm",
1154 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1155 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1158 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1159 def tTST : // A8.6.230
1160 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1161 "tst", "\t$Rn, $Rm",
1162 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1165 def tUXTB : // A8.6.262
1166 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1168 "uxtb", "\t$Rd, $Rm",
1169 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1170 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1172 // Zero-extend short
1173 def tUXTH : // A8.6.264
1174 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1176 "uxth", "\t$Rd, $Rm",
1177 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1178 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1180 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1181 // Expanded after instruction selection into a branch sequence.
1182 let usesCustomInserter = 1 in // Expanded after instruction selection.
1183 def tMOVCCr_pseudo :
1184 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1186 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1188 // tLEApcrel - Load a pc-relative address into a register without offending the
1191 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1192 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1193 T1Encoding<{1,0,1,0,0,?}> {
1196 let Inst{10-8} = Rd;
1197 let Inst{7-0} = addr;
1198 let DecoderMethod = "DecodeThumbAddSpecialReg";
1201 let neverHasSideEffects = 1, isReMaterializable = 1 in
1202 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1205 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1206 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1209 //===----------------------------------------------------------------------===//
1213 // __aeabi_read_tp preserves the registers r1-r3.
1214 // This is a pseudo inst so that we can get the encoding right,
1215 // complete with fixup for the aeabi_read_tp function.
1216 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1217 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1218 [(set R0, ARMthread_pointer)]>;
1220 //===----------------------------------------------------------------------===//
1221 // SJLJ Exception handling intrinsics
1224 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1225 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1226 // from some other function to get here, and we're using the stack frame for the
1227 // containing function to save/restore registers, we can't keep anything live in
1228 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1229 // tromped upon when we get here from a longjmp(). We force everything out of
1230 // registers except for our own input by listing the relevant registers in
1231 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1232 // preserve all of the callee-saved resgisters, which is exactly what we want.
1233 // $val is a scratch register for our use.
1234 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1235 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1236 usesCustomInserter = 1 in
1237 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1238 AddrModeNone, 0, NoItinerary, "","",
1239 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1241 // FIXME: Non-IOS version(s)
1242 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1243 Defs = [ R7, LR, SP ] in
1244 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1245 AddrModeNone, 0, IndexModeNone,
1246 Pseudo, NoItinerary, "", "",
1247 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1248 Requires<[IsThumb, IsIOS]>;
1250 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1252 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
1254 //===----------------------------------------------------------------------===//
1255 // Non-Instruction Patterns
1259 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1260 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1261 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1262 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1265 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1266 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1267 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1268 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1269 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1270 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1272 // Subtract with carry
1273 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1274 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1275 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1276 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1277 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1278 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1280 // ConstantPool, GlobalAddress
1281 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1282 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1285 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1286 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1289 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1290 Requires<[IsThumb]>;
1292 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1293 Requires<[IsThumb, HasV5T]>;
1295 // Indirect calls to ARM routines
1296 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1297 Requires<[IsThumb, HasV5T]>;
1299 // zextload i1 -> zextload i8
1300 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1301 (tLDRBr t_addrmode_rrs1:$addr)>;
1302 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1303 (tLDRBi t_addrmode_is1:$addr)>;
1305 // extload -> zextload
1306 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1307 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1308 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1309 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1310 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1311 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1313 // If it's impossible to use [r,r] address mode for sextload, select to
1314 // ldr{b|h} + sxt{b|h} instead.
1315 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1316 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1317 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1318 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1319 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1320 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1321 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1322 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1323 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1324 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1325 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1326 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1328 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1329 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1330 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1331 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1332 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1333 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1334 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1335 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1337 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1338 (tLDRBi t_addrmode_is1:$src)>;
1339 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1340 (tLDRBr t_addrmode_rrs1:$src)>;
1341 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1342 (tLDRHi t_addrmode_is2:$src)>;
1343 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1344 (tLDRHr t_addrmode_rrs2:$src)>;
1345 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1346 (tLDRi t_addrmode_is4:$src)>;
1347 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1348 (tLDRr t_addrmode_rrs4:$src)>;
1349 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1350 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1351 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1352 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1353 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1354 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1355 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1356 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1357 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1358 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1359 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1360 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1362 // Large immediate handling.
1365 def : T1Pat<(i32 thumb_immshifted:$src),
1366 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1367 (thumb_immshifted_shamt imm:$src))>;
1369 def : T1Pat<(i32 imm0_255_comp:$src),
1370 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1372 // Pseudo instruction that combines ldr from constpool and add pc. This should
1373 // be expanded into two instructions late to allow if-conversion and
1375 let isReMaterializable = 1 in
1376 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1378 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1380 Requires<[IsThumb, IsThumb1Only]>;
1382 // Pseudo-instruction for merged POP and return.
1383 // FIXME: remove when we have a way to marking a MI with these properties.
1384 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1385 hasExtraDefRegAllocReq = 1 in
1386 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1388 (tPOP pred:$p, reglist:$regs)>;
1390 // Indirect branch using "mov pc, $Rm"
1391 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1392 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1393 2, IIC_Br, [(brind GPR:$Rm)],
1394 (tMOVr PC, GPR:$Rm, pred:$p)>;
1398 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1399 // encoding is available on ARMv6K, but we don't differentiate that finely.
1400 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1403 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1404 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1405 // a useful extention and assembles to defined behaviour (the insn does
1407 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1408 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1410 // "neg" is and alias for "rsb rd, rn, #0"
1411 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1412 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;