1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Scaled 4 immediate.
70 def t_imm_s4 : Operand<i32> {
71 let PrintMethod = "printThumbS4ImmOperand";
74 // Define Thumb specific addressing modes.
76 // t_addrmode_rr := reg + reg
78 def t_addrmode_rr : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
80 let PrintMethod = "printThumbAddrModeRROperand";
81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
84 // t_addrmode_s4 := reg + reg
87 def t_addrmode_s4 : Operand<i32>,
88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
89 let PrintMethod = "printThumbAddrModeS4Operand";
90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
93 // t_addrmode_s2 := reg + reg
96 def t_addrmode_s2 : Operand<i32>,
97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
98 let PrintMethod = "printThumbAddrModeS2Operand";
99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
102 // t_addrmode_s1 := reg + reg
105 def t_addrmode_s1 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
107 let PrintMethod = "printThumbAddrModeS1Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
111 // t_addrmode_sp := sp + imm8 * 4
113 def t_addrmode_sp : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
115 let PrintMethod = "printThumbAddrModeSPOperand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions.
123 let Defs = [SP], Uses = [SP] in {
124 def tADJCALLSTACKUP :
125 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
126 "@ tADJCALLSTACKUP $amt1",
127 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
129 def tADJCALLSTACKDOWN :
130 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
131 "@ tADJCALLSTACKDOWN $amt",
132 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
135 // The i32imm operand $val can be used by a debugger to store more information
136 // about the breakpoint.
137 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
138 [/* For disassembly only; pattern left blank */]>,
139 T1Encoding<0b101111> {
140 let Inst{9-8} = 0b10;
143 // For both thumb1 and thumb2.
144 let isNotDuplicable = 1 in
145 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
146 "\n$cp:\n\tadd\t$dst, pc",
147 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
148 T1Special<{0,0,?,?}> {
149 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
153 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
154 "add\t$dst, pc, $rhs", []>,
155 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
158 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
159 "add\t$dst, $sp, $rhs", []>,
160 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
163 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
164 "add\t$dst, $rhs", []>,
165 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
168 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
169 "sub\t$dst, $rhs", []>,
170 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
173 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
174 "add\t$dst, $rhs", []>,
175 T1Special<{0,0,?,?}> {
176 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
180 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
181 "add\t$dst, $rhs", []>,
182 T1Special<{0,0,?,?}> {
183 // A8.6.9 Encoding T2
185 let Inst{2-0} = 0b101;
188 // Pseudo instruction that will expand into a tSUBspi + a copy.
189 let usesCustomInserter = 1 in { // Expanded after instruction selection.
190 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
191 NoItinerary, "@ sub\t$dst, $rhs", []>;
193 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
194 NoItinerary, "@ add\t$dst, $rhs", []>;
197 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
198 NoItinerary, "@ and\t$dst, $rhs", []>;
199 } // usesCustomInserter
201 //===----------------------------------------------------------------------===//
202 // Control Flow Instructions.
205 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
206 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
207 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
208 let Inst{6-3} = 0b1110; // Rm = lr
210 // Alternative return instruction used by vararg functions.
211 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>,
212 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
216 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
217 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
219 T1Special<{1,0,1,?}> {
220 // <Rd> = Inst{7:2-0} = pc
221 let Inst{2-0} = 0b111;
225 // FIXME: remove when we have a way to marking a MI with these properties.
226 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
227 hasExtraDefRegAllocReq = 1 in
228 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
230 T1Misc<{1,1,0,?,?,?,?}>;
233 Defs = [R0, R1, R2, R3, R12, LR,
234 D0, D1, D2, D3, D4, D5, D6, D7,
235 D16, D17, D18, D19, D20, D21, D22, D23,
236 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
237 // Also used for Thumb2
238 def tBL : TIx2<0b11110, 0b11, 1,
239 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
241 [(ARMtcall tglobaladdr:$func)]>,
242 Requires<[IsThumb, IsNotDarwin]>;
244 // ARMv5T and above, also used for Thumb2
245 def tBLXi : TIx2<0b11110, 0b11, 0,
246 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
248 [(ARMcall tglobaladdr:$func)]>,
249 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
251 // Also used for Thumb2
252 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
254 [(ARMtcall GPR:$func)]>,
255 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
256 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
259 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
260 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
261 "mov\tlr, pc\n\tbx\t$func",
262 [(ARMcall_nolink tGPR:$func)]>,
263 Requires<[IsThumb1Only, IsNotDarwin]>;
266 // On Darwin R9 is call-clobbered.
268 Defs = [R0, R1, R2, R3, R9, R12, LR,
269 D0, D1, D2, D3, D4, D5, D6, D7,
270 D16, D17, D18, D19, D20, D21, D22, D23,
271 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
272 // Also used for Thumb2
273 def tBLr9 : TIx2<0b11110, 0b11, 1,
274 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
276 [(ARMtcall tglobaladdr:$func)]>,
277 Requires<[IsThumb, IsDarwin]>;
279 // ARMv5T and above, also used for Thumb2
280 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
281 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
283 [(ARMcall tglobaladdr:$func)]>,
284 Requires<[IsThumb, HasV5T, IsDarwin]>;
286 // Also used for Thumb2
287 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
289 [(ARMtcall GPR:$func)]>,
290 Requires<[IsThumb, HasV5T, IsDarwin]>,
291 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
294 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
295 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
296 "mov\tlr, pc\n\tbx\t$func",
297 [(ARMcall_nolink tGPR:$func)]>,
298 Requires<[IsThumb1Only, IsDarwin]>;
301 let isBranch = 1, isTerminator = 1 in {
302 let isBarrier = 1 in {
303 let isPredicable = 1 in
304 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
305 "b\t$target", [(br bb:$target)]>,
306 T1Encoding<{1,1,1,0,0,?}>;
310 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
311 "bl\t$target\t@ far jump",[]>;
313 def tBR_JTr : T1JTI<(outs),
314 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
315 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
316 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
318 let Inst{15-7} = 0b010001101;
319 let Inst{2-0} = 0b111;
324 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
325 // a two-value operand where a dag node expects two operands. :(
326 let isBranch = 1, isTerminator = 1 in
327 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
329 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
330 T1Encoding<{1,1,0,1,?,?}>;
332 // Compare and branch on zero / non-zero
333 let isBranch = 1, isTerminator = 1 in {
334 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
335 "cbz\t$cmp, $target", []>,
336 T1Misc<{0,0,?,1,?,?,?}>;
338 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
339 "cbnz\t$cmp, $target", []>,
340 T1Misc<{1,0,?,1,?,?,?}>;
343 //===----------------------------------------------------------------------===//
344 // Load Store Instructions.
347 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
348 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
349 "ldr", "\t$dst, $addr",
350 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
352 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
353 "ldr", "\t$dst, $addr",
357 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
358 "ldrb", "\t$dst, $addr",
359 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
361 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
362 "ldrb", "\t$dst, $addr",
366 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
367 "ldrh", "\t$dst, $addr",
368 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
370 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
371 "ldrh", "\t$dst, $addr",
375 let AddedComplexity = 10 in
376 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
377 "ldrsb", "\t$dst, $addr",
378 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
381 let AddedComplexity = 10 in
382 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
383 "ldrsh", "\t$dst, $addr",
384 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
387 let canFoldAsLoad = 1 in
388 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
389 "ldr", "\t$dst, $addr",
390 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
393 // Special instruction for restore. It cannot clobber condition register
394 // when it's expanded by eliminateCallFramePseudoInstr().
395 let canFoldAsLoad = 1, mayLoad = 1 in
396 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
397 "ldr", "\t$dst, $addr", []>,
401 // FIXME: Use ldr.n to work around a Darwin assembler bug.
402 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
403 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
404 "ldr", ".n\t$dst, $addr",
405 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
406 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
408 // Special LDR for loads from non-pc-relative constpools.
409 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
410 mayHaveSideEffects = 1 in
411 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
412 "ldr", "\t$dst, $addr", []>,
415 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
416 "str", "\t$src, $addr",
417 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
419 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
420 "str", "\t$src, $addr",
424 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
425 "strb", "\t$src, $addr",
426 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
428 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
429 "strb", "\t$src, $addr",
433 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
434 "strh", "\t$src, $addr",
435 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
437 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
438 "strh", "\t$src, $addr",
442 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
443 "str", "\t$src, $addr",
444 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
447 let mayStore = 1 in {
448 // Special instruction for spill. It cannot clobber condition register
449 // when it's expanded by eliminateCallFramePseudoInstr().
450 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
451 "str", "\t$src, $addr", []>,
455 //===----------------------------------------------------------------------===//
456 // Load / store multiple Instructions.
459 // These requires base address to be written back or one of the loaded regs.
460 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
461 def tLDM : T1I<(outs),
462 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
464 "ldm${addr:submode}${p}\t$addr, $wb", []>,
465 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
467 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
468 def tSTM : T1I<(outs),
469 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
471 "stm${addr:submode}${p}\t$addr, $wb", []>,
472 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
474 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
475 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
477 T1Misc<{1,1,0,?,?,?,?}>;
479 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
480 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
481 "push${p}\t$wb", []>,
482 T1Misc<{0,1,0,?,?,?,?}>;
484 //===----------------------------------------------------------------------===//
485 // Arithmetic Instructions.
488 // Add with carry register
489 let isCommutable = 1, Uses = [CPSR] in
490 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
491 "adc", "\t$dst, $rhs",
492 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
493 T1DataProcessing<0b0101>;
496 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
497 "add", "\t$dst, $lhs, $rhs",
498 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
501 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
502 "add", "\t$dst, $rhs",
503 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
504 T1General<{1,1,0,?,?}>;
507 let isCommutable = 1 in
508 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
509 "add", "\t$dst, $lhs, $rhs",
510 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
513 let neverHasSideEffects = 1 in
514 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
515 "add", "\t$dst, $rhs", []>,
516 T1Special<{0,0,?,?}>;
519 let isCommutable = 1 in
520 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
521 "and", "\t$dst, $rhs",
522 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
523 T1DataProcessing<0b0000>;
526 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
527 "asr", "\t$dst, $lhs, $rhs",
528 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
529 T1General<{0,1,0,?,?}>;
532 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
533 "asr", "\t$dst, $rhs",
534 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
535 T1DataProcessing<0b0100>;
538 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
539 "bic", "\t$dst, $rhs",
540 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
541 T1DataProcessing<0b1110>;
544 let Defs = [CPSR] in {
545 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
546 // Compare-to-zero still works out, just not the relationals
547 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
548 // "cmn", "\t$lhs, $rhs",
549 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
550 // T1DataProcessing<0b1011>;
551 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
552 "cmn", "\t$lhs, $rhs",
553 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
554 T1DataProcessing<0b1011>;
558 let Defs = [CPSR] in {
559 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
560 "cmp", "\t$lhs, $rhs",
561 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
562 T1General<{1,0,1,?,?}>;
563 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
564 "cmp", "\t$lhs, $rhs",
565 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
566 T1General<{1,0,1,?,?}>;
570 let Defs = [CPSR] in {
571 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
572 "cmp", "\t$lhs, $rhs",
573 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
574 T1DataProcessing<0b1010>;
575 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
576 "cmp", "\t$lhs, $rhs",
577 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
578 T1DataProcessing<0b1010>;
580 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
581 "cmp", "\t$lhs, $rhs", []>,
582 T1Special<{0,1,?,?}>;
583 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
584 "cmp", "\t$lhs, $rhs", []>,
585 T1Special<{0,1,?,?}>;
590 let isCommutable = 1 in
591 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
592 "eor", "\t$dst, $rhs",
593 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
594 T1DataProcessing<0b0001>;
597 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
598 "lsl", "\t$dst, $lhs, $rhs",
599 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
600 T1General<{0,0,0,?,?}>;
603 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
604 "lsl", "\t$dst, $rhs",
605 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
606 T1DataProcessing<0b0010>;
609 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
610 "lsr", "\t$dst, $lhs, $rhs",
611 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
612 T1General<{0,0,1,?,?}>;
615 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
616 "lsr", "\t$dst, $rhs",
617 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
618 T1DataProcessing<0b0011>;
621 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
622 "mov", "\t$dst, $src",
623 [(set tGPR:$dst, imm0_255:$src)]>,
624 T1General<{1,0,0,?,?}>;
626 // TODO: A7-73: MOV(2) - mov setting flag.
629 let neverHasSideEffects = 1 in {
630 // FIXME: Make this predicable.
631 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
632 "mov\t$dst, $src", []>,
635 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
636 "movs\t$dst, $src", []>, Encoding16 {
637 let Inst{15-6} = 0b0000000000;
640 // FIXME: Make these predicable.
641 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
642 "mov\t$dst, $src", []>,
643 T1Special<{1,0,0,?}>;
644 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
645 "mov\t$dst, $src", []>,
646 T1Special<{1,0,?,0}>;
647 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
648 "mov\t$dst, $src", []>,
649 T1Special<{1,0,?,?}>;
650 } // neverHasSideEffects
653 let isCommutable = 1 in
654 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
655 "mul", "\t$dst, $rhs",
656 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
657 T1DataProcessing<0b1101>;
659 // move inverse register
660 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
661 "mvn", "\t$dst, $src",
662 [(set tGPR:$dst, (not tGPR:$src))]>,
663 T1DataProcessing<0b1111>;
665 // bitwise or register
666 let isCommutable = 1 in
667 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
668 "orr", "\t$dst, $rhs",
669 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
670 T1DataProcessing<0b1100>;
673 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
674 "rev", "\t$dst, $src",
675 [(set tGPR:$dst, (bswap tGPR:$src))]>,
676 Requires<[IsThumb1Only, HasV6]>,
677 T1Misc<{1,0,1,0,0,0,?}>;
679 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
680 "rev16", "\t$dst, $src",
682 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
683 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
684 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
685 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
686 Requires<[IsThumb1Only, HasV6]>,
687 T1Misc<{1,0,1,0,0,1,?}>;
689 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
690 "revsh", "\t$dst, $src",
693 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
694 (shl tGPR:$src, (i32 8))), i16))]>,
695 Requires<[IsThumb1Only, HasV6]>,
696 T1Misc<{1,0,1,0,1,1,?}>;
698 // rotate right register
699 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
700 "ror", "\t$dst, $rhs",
701 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
702 T1DataProcessing<0b0111>;
705 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
706 "rsb", "\t$dst, $src, #0",
707 [(set tGPR:$dst, (ineg tGPR:$src))]>,
708 T1DataProcessing<0b1001>;
710 // Subtract with carry register
712 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
713 "sbc", "\t$dst, $rhs",
714 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
715 T1DataProcessing<0b0110>;
717 // Subtract immediate
718 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
719 "sub", "\t$dst, $lhs, $rhs",
720 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
723 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
724 "sub", "\t$dst, $rhs",
725 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
726 T1General<{1,1,1,?,?}>;
729 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
730 "sub", "\t$dst, $lhs, $rhs",
731 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
734 // TODO: A7-96: STMIA - store multiple.
737 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
738 "sxtb", "\t$dst, $src",
739 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
740 Requires<[IsThumb1Only, HasV6]>,
741 T1Misc<{0,0,1,0,0,1,?}>;
744 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
745 "sxth", "\t$dst, $src",
746 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
747 Requires<[IsThumb1Only, HasV6]>,
748 T1Misc<{0,0,1,0,0,0,?}>;
751 let isCommutable = 1, Defs = [CPSR] in
752 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
753 "tst", "\t$lhs, $rhs",
754 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
755 T1DataProcessing<0b1000>;
758 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
759 "uxtb", "\t$dst, $src",
760 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
761 Requires<[IsThumb1Only, HasV6]>,
762 T1Misc<{0,0,1,0,1,1,?}>;
765 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
766 "uxth", "\t$dst, $src",
767 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
768 Requires<[IsThumb1Only, HasV6]>,
769 T1Misc<{0,0,1,0,1,0,?}>;
772 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
773 // Expanded after instruction selection into a branch sequence.
774 let usesCustomInserter = 1 in // Expanded after instruction selection.
776 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
777 NoItinerary, "@ tMOVCCr $cc",
778 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
781 // 16-bit movcc in IT blocks for Thumb2.
782 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
783 "mov", "\t$dst, $rhs", []>,
784 T1Special<{1,0,?,?}>;
786 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
787 "mov", "\t$dst, $rhs", []>,
788 T1General<{1,0,0,?,?}>;
790 // tLEApcrel - Load a pc-relative address into a register without offending the
792 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
793 "adr$p\t$dst, #$label", []>,
794 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
796 def tLEApcrelJT : T1I<(outs tGPR:$dst),
797 (ins i32imm:$label, nohash_imm:$id, pred:$p),
798 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
799 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
801 //===----------------------------------------------------------------------===//
805 // __aeabi_read_tp preserves the registers r1-r3.
808 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
809 "bl\t__aeabi_read_tp",
810 [(set R0, ARMthread_pointer)]>;
813 // SJLJ Exception handling intrinsics
814 // eh_sjlj_setjmp() is an instruction sequence to store the return
815 // address and save #0 in R0 for the non-longjmp case.
816 // Since by its nature we may be coming from some other function to get
817 // here, and we're using the stack frame for the containing function to
818 // save/restore registers, we can't keep anything live in regs across
819 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
820 // when we get here from a longjmp(). We force everthing out of registers
821 // except for our own input by listing the relevant registers in Defs. By
822 // doing so, we also cause the prologue/epilogue code to actively preserve
823 // all of the callee-saved resgisters, which is exactly what we want.
824 // The current SP is passed in $val, and we reuse the reg as a scratch.
826 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
827 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
828 AddrModeNone, SizeSpecial, NoItinerary,
829 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
832 "\tstr\t$val, [$src, #4]\n"
835 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
837 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
839 //===----------------------------------------------------------------------===//
840 // Non-Instruction Patterns
844 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
845 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
846 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
847 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
848 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
849 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
851 // Subtract with carry
852 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
853 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
854 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
855 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
856 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
857 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
859 // ConstantPool, GlobalAddress
860 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
861 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
864 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
865 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
868 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
869 Requires<[IsThumb, IsNotDarwin]>;
870 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
871 Requires<[IsThumb, IsDarwin]>;
873 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
874 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
875 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
876 Requires<[IsThumb, HasV5T, IsDarwin]>;
878 // Indirect calls to ARM routines
879 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
880 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
881 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
882 Requires<[IsThumb, HasV5T, IsDarwin]>;
884 // zextload i1 -> zextload i8
885 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
886 (tLDRB t_addrmode_s1:$addr)>;
888 // extload -> zextload
889 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
890 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
891 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
893 // If it's impossible to use [r,r] address mode for sextload, select to
894 // ldr{b|h} + sxt{b|h} instead.
895 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
896 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
897 Requires<[IsThumb1Only, HasV6]>;
898 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
899 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
900 Requires<[IsThumb1Only, HasV6]>;
902 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
903 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
904 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
905 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
907 // Large immediate handling.
910 def : T1Pat<(i32 thumb_immshifted:$src),
911 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
912 (thumb_immshifted_shamt imm:$src))>;
914 def : T1Pat<(i32 imm0_255_comp:$src),
915 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
917 // Pseudo instruction that combines ldr from constpool and add pc. This should
918 // be expanded into two instructions late to allow if-conversion and
920 let isReMaterializable = 1 in
921 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
922 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
923 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
925 Requires<[IsThumb1Only]>;