1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Scaled 4 immediate.
70 def t_imm_s4 : Operand<i32> {
71 let PrintMethod = "printThumbS4ImmOperand";
74 // Define Thumb specific addressing modes.
76 // t_addrmode_rr := reg + reg
78 def t_addrmode_rr : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
80 let PrintMethod = "printThumbAddrModeRROperand";
81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
84 // t_addrmode_s4 := reg + reg
87 def t_addrmode_s4 : Operand<i32>,
88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
89 let PrintMethod = "printThumbAddrModeS4Operand";
90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
93 // t_addrmode_s2 := reg + reg
96 def t_addrmode_s2 : Operand<i32>,
97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
98 let PrintMethod = "printThumbAddrModeS2Operand";
99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
102 // t_addrmode_s1 := reg + reg
105 def t_addrmode_s1 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
107 let PrintMethod = "printThumbAddrModeS1Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
111 // t_addrmode_sp := sp + imm8 * 4
113 def t_addrmode_sp : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
115 let PrintMethod = "printThumbAddrModeSPOperand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions.
123 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
124 // from removing one half of the matched pairs. That breaks PEI, which assumes
125 // these will always be in pairs, and asserts if it finds otherwise. Better way?
126 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
127 def tADJCALLSTACKUP :
128 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
129 "@ tADJCALLSTACKUP $amt1",
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
132 def tADJCALLSTACKDOWN :
133 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
134 "@ tADJCALLSTACKDOWN $amt",
135 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
138 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
139 [/* For disassembly only; pattern left blank */]>,
140 T1Encoding<0b101111> {
141 let Inst{9-8} = 0b11;
142 let Inst{7-0} = 0b00000000;
145 // The i32imm operand $val can be used by a debugger to store more information
146 // about the breakpoint.
147 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
148 [/* For disassembly only; pattern left blank */]>,
149 T1Encoding<0b101111> {
150 let Inst{9-8} = 0b10;
153 // For both thumb1 and thumb2.
154 let isNotDuplicable = 1 in
155 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
156 "\n$cp:\n\tadd\t$dst, pc",
157 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
158 T1Special<{0,0,?,?}> {
159 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
163 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
164 "add\t$dst, pc, $rhs", []>,
165 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
168 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
169 "add\t$dst, $sp, $rhs", []>,
170 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
173 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
174 "add\t$dst, $rhs", []>,
175 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
178 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
179 "sub\t$dst, $rhs", []>,
180 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
183 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
184 "add\t$dst, $rhs", []>,
185 T1Special<{0,0,?,?}> {
186 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
190 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
191 "add\t$dst, $rhs", []>,
192 T1Special<{0,0,?,?}> {
193 // A8.6.9 Encoding T2
195 let Inst{2-0} = 0b101;
198 // Pseudo instruction that will expand into a tSUBspi + a copy.
199 let usesCustomInserter = 1 in { // Expanded after instruction selection.
200 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
201 NoItinerary, "@ sub\t$dst, $rhs", []>;
203 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
204 NoItinerary, "@ add\t$dst, $rhs", []>;
207 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
208 NoItinerary, "@ and\t$dst, $rhs", []>;
209 } // usesCustomInserter
211 //===----------------------------------------------------------------------===//
212 // Control Flow Instructions.
215 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
216 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
217 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
218 let Inst{6-3} = 0b1110; // Rm = lr
220 // Alternative return instruction used by vararg functions.
221 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
222 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
226 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
227 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
229 T1Special<{1,0,1,?}> {
230 // <Rd> = Inst{7:2-0} = pc
231 let Inst{2-0} = 0b111;
235 // FIXME: remove when we have a way to marking a MI with these properties.
236 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
237 hasExtraDefRegAllocReq = 1 in
238 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
240 T1Misc<{1,1,0,?,?,?,?}>;
243 Defs = [R0, R1, R2, R3, R12, LR,
244 D0, D1, D2, D3, D4, D5, D6, D7,
245 D16, D17, D18, D19, D20, D21, D22, D23,
246 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
247 // Also used for Thumb2
248 def tBL : TIx2<0b11110, 0b11, 1,
249 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
251 [(ARMtcall tglobaladdr:$func)]>,
252 Requires<[IsThumb, IsNotDarwin]>;
254 // ARMv5T and above, also used for Thumb2
255 def tBLXi : TIx2<0b11110, 0b11, 0,
256 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
258 [(ARMcall tglobaladdr:$func)]>,
259 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
261 // Also used for Thumb2
262 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
264 [(ARMtcall GPR:$func)]>,
265 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
266 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
269 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
270 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
271 "mov\tlr, pc\n\tbx\t$func",
272 [(ARMcall_nolink tGPR:$func)]>,
273 Requires<[IsThumb1Only, IsNotDarwin]>;
276 // On Darwin R9 is call-clobbered.
278 Defs = [R0, R1, R2, R3, R9, R12, LR,
279 D0, D1, D2, D3, D4, D5, D6, D7,
280 D16, D17, D18, D19, D20, D21, D22, D23,
281 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
282 // Also used for Thumb2
283 def tBLr9 : TIx2<0b11110, 0b11, 1,
284 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
286 [(ARMtcall tglobaladdr:$func)]>,
287 Requires<[IsThumb, IsDarwin]>;
289 // ARMv5T and above, also used for Thumb2
290 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
291 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
293 [(ARMcall tglobaladdr:$func)]>,
294 Requires<[IsThumb, HasV5T, IsDarwin]>;
296 // Also used for Thumb2
297 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
299 [(ARMtcall GPR:$func)]>,
300 Requires<[IsThumb, HasV5T, IsDarwin]>,
301 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
304 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
305 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
306 "mov\tlr, pc\n\tbx\t$func",
307 [(ARMcall_nolink tGPR:$func)]>,
308 Requires<[IsThumb1Only, IsDarwin]>;
311 let isBranch = 1, isTerminator = 1 in {
312 let isBarrier = 1 in {
313 let isPredicable = 1 in
314 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
315 "b\t$target", [(br bb:$target)]>,
316 T1Encoding<{1,1,1,0,0,?}>;
320 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
321 "bl\t$target\t@ far jump",[]>;
323 def tBR_JTr : T1JTI<(outs),
324 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
325 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
326 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
328 let Inst{15-7} = 0b010001101;
329 let Inst{2-0} = 0b111;
334 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
335 // a two-value operand where a dag node expects two operands. :(
336 let isBranch = 1, isTerminator = 1 in
337 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
339 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
340 T1Encoding<{1,1,0,1,?,?}>;
342 // Compare and branch on zero / non-zero
343 let isBranch = 1, isTerminator = 1 in {
344 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
345 "cbz\t$cmp, $target", []>,
346 T1Misc<{0,0,?,1,?,?,?}>;
348 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
349 "cbnz\t$cmp, $target", []>,
350 T1Misc<{1,0,?,1,?,?,?}>;
353 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
354 // A8.6.16 B: Encoding T1
355 // If Inst{11-8} == 0b1111 then SEE SVC
357 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
359 let Inst{15-12} = 0b1101;
360 let Inst{11-8} = 0b1111;
364 // A8.6.16 B: Encoding T1 -- for disassembly only
365 // If Inst{11-8} == 0b1110 then UNDEFINED
366 def tTRAP : T1I<(outs), (ins), IIC_Br, "trap", []>, Encoding16 {
367 let Inst{15-12} = 0b1101;
368 let Inst{11-8} = 0b1110;
371 //===----------------------------------------------------------------------===//
372 // Load Store Instructions.
375 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
376 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
377 "ldr", "\t$dst, $addr",
378 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
380 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
381 "ldr", "\t$dst, $addr",
385 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
386 "ldrb", "\t$dst, $addr",
387 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
389 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
390 "ldrb", "\t$dst, $addr",
394 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
395 "ldrh", "\t$dst, $addr",
396 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
398 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
399 "ldrh", "\t$dst, $addr",
403 let AddedComplexity = 10 in
404 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
405 "ldrsb", "\t$dst, $addr",
406 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
409 let AddedComplexity = 10 in
410 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
411 "ldrsh", "\t$dst, $addr",
412 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
415 let canFoldAsLoad = 1 in
416 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
417 "ldr", "\t$dst, $addr",
418 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
421 // Special instruction for restore. It cannot clobber condition register
422 // when it's expanded by eliminateCallFramePseudoInstr().
423 let canFoldAsLoad = 1, mayLoad = 1 in
424 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
425 "ldr", "\t$dst, $addr", []>,
429 // FIXME: Use ldr.n to work around a Darwin assembler bug.
430 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
431 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
432 "ldr", ".n\t$dst, $addr",
433 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
434 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
436 // Special LDR for loads from non-pc-relative constpools.
437 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
438 mayHaveSideEffects = 1 in
439 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
440 "ldr", "\t$dst, $addr", []>,
443 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
444 "str", "\t$src, $addr",
445 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
447 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
448 "str", "\t$src, $addr",
452 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
453 "strb", "\t$src, $addr",
454 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
456 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
457 "strb", "\t$src, $addr",
461 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
462 "strh", "\t$src, $addr",
463 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
465 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
466 "strh", "\t$src, $addr",
470 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
471 "str", "\t$src, $addr",
472 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
475 let mayStore = 1 in {
476 // Special instruction for spill. It cannot clobber condition register
477 // when it's expanded by eliminateCallFramePseudoInstr().
478 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
479 "str", "\t$src, $addr", []>,
483 //===----------------------------------------------------------------------===//
484 // Load / store multiple Instructions.
487 // These requires base address to be written back or one of the loaded regs.
488 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
489 def tLDM : T1I<(outs),
490 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
492 "ldm${addr:submode}${p}\t$addr, $wb", []>,
493 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
495 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
496 def tSTM : T1I<(outs),
497 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
499 "stm${addr:submode}${p}\t$addr, $wb", []>,
500 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
502 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
503 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
505 T1Misc<{1,1,0,?,?,?,?}>;
507 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
508 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
509 "push${p}\t$wb", []>,
510 T1Misc<{0,1,0,?,?,?,?}>;
512 //===----------------------------------------------------------------------===//
513 // Arithmetic Instructions.
516 // Add with carry register
517 let isCommutable = 1, Uses = [CPSR] in
518 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
519 "adc", "\t$dst, $rhs",
520 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
521 T1DataProcessing<0b0101>;
524 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
525 "add", "\t$dst, $lhs, $rhs",
526 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
529 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
530 "add", "\t$dst, $rhs",
531 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
532 T1General<{1,1,0,?,?}>;
535 let isCommutable = 1 in
536 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
537 "add", "\t$dst, $lhs, $rhs",
538 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
541 let neverHasSideEffects = 1 in
542 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
543 "add", "\t$dst, $rhs", []>,
544 T1Special<{0,0,?,?}>;
547 let isCommutable = 1 in
548 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
549 "and", "\t$dst, $rhs",
550 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
551 T1DataProcessing<0b0000>;
554 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
555 "asr", "\t$dst, $lhs, $rhs",
556 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
557 T1General<{0,1,0,?,?}>;
560 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
561 "asr", "\t$dst, $rhs",
562 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
563 T1DataProcessing<0b0100>;
566 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
567 "bic", "\t$dst, $rhs",
568 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
569 T1DataProcessing<0b1110>;
572 let Defs = [CPSR] in {
573 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
574 // Compare-to-zero still works out, just not the relationals
575 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
576 // "cmn", "\t$lhs, $rhs",
577 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
578 // T1DataProcessing<0b1011>;
579 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
580 "cmn", "\t$lhs, $rhs",
581 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
582 T1DataProcessing<0b1011>;
586 let Defs = [CPSR] in {
587 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
588 "cmp", "\t$lhs, $rhs",
589 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
590 T1General<{1,0,1,?,?}>;
591 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
592 "cmp", "\t$lhs, $rhs",
593 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
594 T1General<{1,0,1,?,?}>;
598 let Defs = [CPSR] in {
599 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
600 "cmp", "\t$lhs, $rhs",
601 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
602 T1DataProcessing<0b1010>;
603 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
604 "cmp", "\t$lhs, $rhs",
605 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
606 T1DataProcessing<0b1010>;
608 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
609 "cmp", "\t$lhs, $rhs", []>,
610 T1Special<{0,1,?,?}>;
611 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
612 "cmp", "\t$lhs, $rhs", []>,
613 T1Special<{0,1,?,?}>;
618 let isCommutable = 1 in
619 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
620 "eor", "\t$dst, $rhs",
621 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
622 T1DataProcessing<0b0001>;
625 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
626 "lsl", "\t$dst, $lhs, $rhs",
627 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
628 T1General<{0,0,0,?,?}>;
631 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
632 "lsl", "\t$dst, $rhs",
633 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
634 T1DataProcessing<0b0010>;
637 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
638 "lsr", "\t$dst, $lhs, $rhs",
639 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
640 T1General<{0,0,1,?,?}>;
643 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
644 "lsr", "\t$dst, $rhs",
645 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
646 T1DataProcessing<0b0011>;
649 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
650 "mov", "\t$dst, $src",
651 [(set tGPR:$dst, imm0_255:$src)]>,
652 T1General<{1,0,0,?,?}>;
654 // TODO: A7-73: MOV(2) - mov setting flag.
657 let neverHasSideEffects = 1 in {
658 // FIXME: Make this predicable.
659 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
660 "mov\t$dst, $src", []>,
663 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
664 "movs\t$dst, $src", []>, Encoding16 {
665 let Inst{15-6} = 0b0000000000;
668 // FIXME: Make these predicable.
669 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
670 "mov\t$dst, $src", []>,
671 T1Special<{1,0,0,?}>;
672 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
673 "mov\t$dst, $src", []>,
674 T1Special<{1,0,?,0}>;
675 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
676 "mov\t$dst, $src", []>,
677 T1Special<{1,0,?,?}>;
678 } // neverHasSideEffects
681 let isCommutable = 1 in
682 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
683 "mul", "\t$dst, $rhs",
684 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
685 T1DataProcessing<0b1101>;
687 // move inverse register
688 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
689 "mvn", "\t$dst, $src",
690 [(set tGPR:$dst, (not tGPR:$src))]>,
691 T1DataProcessing<0b1111>;
693 // bitwise or register
694 let isCommutable = 1 in
695 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
696 "orr", "\t$dst, $rhs",
697 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
698 T1DataProcessing<0b1100>;
701 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
702 "rev", "\t$dst, $src",
703 [(set tGPR:$dst, (bswap tGPR:$src))]>,
704 Requires<[IsThumb1Only, HasV6]>,
705 T1Misc<{1,0,1,0,0,0,?}>;
707 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
708 "rev16", "\t$dst, $src",
710 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
711 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
712 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
713 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
714 Requires<[IsThumb1Only, HasV6]>,
715 T1Misc<{1,0,1,0,0,1,?}>;
717 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
718 "revsh", "\t$dst, $src",
721 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
722 (shl tGPR:$src, (i32 8))), i16))]>,
723 Requires<[IsThumb1Only, HasV6]>,
724 T1Misc<{1,0,1,0,1,1,?}>;
726 // rotate right register
727 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
728 "ror", "\t$dst, $rhs",
729 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
730 T1DataProcessing<0b0111>;
733 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
734 "rsb", "\t$dst, $src, #0",
735 [(set tGPR:$dst, (ineg tGPR:$src))]>,
736 T1DataProcessing<0b1001>;
738 // Subtract with carry register
740 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
741 "sbc", "\t$dst, $rhs",
742 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
743 T1DataProcessing<0b0110>;
745 // Subtract immediate
746 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
747 "sub", "\t$dst, $lhs, $rhs",
748 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
751 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
752 "sub", "\t$dst, $rhs",
753 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
754 T1General<{1,1,1,?,?}>;
757 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
758 "sub", "\t$dst, $lhs, $rhs",
759 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
762 // TODO: A7-96: STMIA - store multiple.
765 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
766 "sxtb", "\t$dst, $src",
767 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
768 Requires<[IsThumb1Only, HasV6]>,
769 T1Misc<{0,0,1,0,0,1,?}>;
772 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
773 "sxth", "\t$dst, $src",
774 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
775 Requires<[IsThumb1Only, HasV6]>,
776 T1Misc<{0,0,1,0,0,0,?}>;
779 let isCommutable = 1, Defs = [CPSR] in
780 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
781 "tst", "\t$lhs, $rhs",
782 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
783 T1DataProcessing<0b1000>;
786 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
787 "uxtb", "\t$dst, $src",
788 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
789 Requires<[IsThumb1Only, HasV6]>,
790 T1Misc<{0,0,1,0,1,1,?}>;
793 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
794 "uxth", "\t$dst, $src",
795 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
796 Requires<[IsThumb1Only, HasV6]>,
797 T1Misc<{0,0,1,0,1,0,?}>;
800 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
801 // Expanded after instruction selection into a branch sequence.
802 let usesCustomInserter = 1 in // Expanded after instruction selection.
804 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
805 NoItinerary, "@ tMOVCCr $cc",
806 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
809 // 16-bit movcc in IT blocks for Thumb2.
810 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
811 "mov", "\t$dst, $rhs", []>,
812 T1Special<{1,0,?,?}>;
814 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
815 "mov", "\t$dst, $rhs", []>,
816 T1General<{1,0,0,?,?}>;
818 // tLEApcrel - Load a pc-relative address into a register without offending the
820 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
821 "adr$p\t$dst, #$label", []>,
822 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
824 def tLEApcrelJT : T1I<(outs tGPR:$dst),
825 (ins i32imm:$label, nohash_imm:$id, pred:$p),
826 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
827 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
829 //===----------------------------------------------------------------------===//
833 // __aeabi_read_tp preserves the registers r1-r3.
836 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
837 "bl\t__aeabi_read_tp",
838 [(set R0, ARMthread_pointer)]>;
841 // SJLJ Exception handling intrinsics
842 // eh_sjlj_setjmp() is an instruction sequence to store the return
843 // address and save #0 in R0 for the non-longjmp case.
844 // Since by its nature we may be coming from some other function to get
845 // here, and we're using the stack frame for the containing function to
846 // save/restore registers, we can't keep anything live in regs across
847 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
848 // when we get here from a longjmp(). We force everthing out of registers
849 // except for our own input by listing the relevant registers in Defs. By
850 // doing so, we also cause the prologue/epilogue code to actively preserve
851 // all of the callee-saved resgisters, which is exactly what we want.
852 // The current SP is passed in $val, and we reuse the reg as a scratch.
854 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
855 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
856 AddrModeNone, SizeSpecial, NoItinerary,
857 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
860 "\tstr\t$val, [$src, #4]\n"
863 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
865 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
867 //===----------------------------------------------------------------------===//
868 // Non-Instruction Patterns
872 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
873 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
874 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
875 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
876 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
877 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
879 // Subtract with carry
880 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
881 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
882 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
883 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
884 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
885 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
887 // ConstantPool, GlobalAddress
888 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
889 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
892 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
893 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
896 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
897 Requires<[IsThumb, IsNotDarwin]>;
898 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
899 Requires<[IsThumb, IsDarwin]>;
901 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
902 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
903 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
904 Requires<[IsThumb, HasV5T, IsDarwin]>;
906 // Indirect calls to ARM routines
907 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
908 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
909 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
910 Requires<[IsThumb, HasV5T, IsDarwin]>;
912 // zextload i1 -> zextload i8
913 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
914 (tLDRB t_addrmode_s1:$addr)>;
916 // extload -> zextload
917 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
918 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
919 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
921 // If it's impossible to use [r,r] address mode for sextload, select to
922 // ldr{b|h} + sxt{b|h} instead.
923 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
924 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
925 Requires<[IsThumb1Only, HasV6]>;
926 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
927 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
928 Requires<[IsThumb1Only, HasV6]>;
930 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
931 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
932 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
933 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
935 // Large immediate handling.
938 def : T1Pat<(i32 thumb_immshifted:$src),
939 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
940 (thumb_immshifted_shamt imm:$src))>;
942 def : T1Pat<(i32 imm0_255_comp:$src),
943 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
945 // Pseudo instruction that combines ldr from constpool and add pc. This should
946 // be expanded into two instructions late to allow if-conversion and
948 let isReMaterializable = 1 in
949 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
950 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
951 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
953 Requires<[IsThumb1Only]>;