1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Scaled 4 immediate.
70 def t_imm_s4 : Operand<i32> {
71 let PrintMethod = "printThumbS4ImmOperand";
74 // Define Thumb specific addressing modes.
76 // t_addrmode_rr := reg + reg
78 def t_addrmode_rr : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
80 let PrintMethod = "printThumbAddrModeRROperand";
81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
84 // t_addrmode_s4 := reg + reg
87 def t_addrmode_s4 : Operand<i32>,
88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
89 let PrintMethod = "printThumbAddrModeS4Operand";
90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
93 // t_addrmode_s2 := reg + reg
96 def t_addrmode_s2 : Operand<i32>,
97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
98 let PrintMethod = "printThumbAddrModeS2Operand";
99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
102 // t_addrmode_s1 := reg + reg
105 def t_addrmode_s1 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
107 let PrintMethod = "printThumbAddrModeS1Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
111 // t_addrmode_sp := sp + imm8 * 4
113 def t_addrmode_sp : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
115 let PrintMethod = "printThumbAddrModeSPOperand";
116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions.
123 let Defs = [SP], Uses = [SP] in {
124 def tADJCALLSTACKUP :
125 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
126 "@ tADJCALLSTACKUP $amt1",
127 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
129 def tADJCALLSTACKDOWN :
130 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
131 "@ tADJCALLSTACKDOWN $amt",
132 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
135 // For both thumb1 and thumb2.
136 let isNotDuplicable = 1 in
137 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
138 "\n$cp:\n\tadd\t$dst, pc",
139 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
140 T1Special<{0,0,?,?}> {
141 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
145 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
146 "add\t$dst, pc, $rhs", []>,
147 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
150 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
151 "add\t$dst, $sp, $rhs", []>,
152 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
155 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
156 "add\t$dst, $rhs", []>,
157 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
160 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
161 "sub\t$dst, $rhs", []>,
162 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
165 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
166 "add\t$dst, $rhs", []>,
167 T1Special<{0,0,?,?}> {
168 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
172 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
173 "add\t$dst, $rhs", []>,
174 T1Special<{0,0,?,?}> {
175 // A8.6.9 Encoding T2
177 let Inst{2-0} = 0b101;
180 // Pseudo instruction that will expand into a tSUBspi + a copy.
181 let usesCustomInserter = 1 in { // Expanded after instruction selection.
182 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
183 NoItinerary, "@ sub\t$dst, $rhs", []>;
185 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
186 NoItinerary, "@ add\t$dst, $rhs", []>;
189 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
190 NoItinerary, "@ and\t$dst, $rhs", []>;
191 } // usesCustomInserter
193 //===----------------------------------------------------------------------===//
194 // Control Flow Instructions.
197 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
198 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
199 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
200 let Inst{6-3} = 0b1110; // Rm = lr
202 // Alternative return instruction used by vararg functions.
203 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>,
204 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
208 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
209 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
211 T1Special<{1,0,?,?}> {
214 let Inst{2-0} = 0b111;
218 // FIXME: remove when we have a way to marking a MI with these properties.
219 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
220 hasExtraDefRegAllocReq = 1 in
221 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
223 T1Misc<{1,1,0,?,?,?,?}>;
226 Defs = [R0, R1, R2, R3, R12, LR,
227 D0, D1, D2, D3, D4, D5, D6, D7,
228 D16, D17, D18, D19, D20, D21, D22, D23,
229 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
230 // Also used for Thumb2
231 def tBL : TIx2<0b11110, 0b11, 1,
232 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
234 [(ARMtcall tglobaladdr:$func)]>,
235 Requires<[IsThumb, IsNotDarwin]>;
237 // ARMv5T and above, also used for Thumb2
238 def tBLXi : TIx2<0b11110, 0b11, 0,
239 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
241 [(ARMcall tglobaladdr:$func)]>,
242 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
244 // Also used for Thumb2
245 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
247 [(ARMtcall GPR:$func)]>,
248 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
249 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
252 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
253 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
254 "mov\tlr, pc\n\tbx\t$func",
255 [(ARMcall_nolink tGPR:$func)]>,
256 Requires<[IsThumb1Only, IsNotDarwin]>;
259 // On Darwin R9 is call-clobbered.
261 Defs = [R0, R1, R2, R3, R9, R12, LR,
262 D0, D1, D2, D3, D4, D5, D6, D7,
263 D16, D17, D18, D19, D20, D21, D22, D23,
264 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
265 // Also used for Thumb2
266 def tBLr9 : TIx2<0b11110, 0b11, 1,
267 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
269 [(ARMtcall tglobaladdr:$func)]>,
270 Requires<[IsThumb, IsDarwin]>;
272 // ARMv5T and above, also used for Thumb2
273 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
274 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
276 [(ARMcall tglobaladdr:$func)]>,
277 Requires<[IsThumb, HasV5T, IsDarwin]>;
279 // Also used for Thumb2
280 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
282 [(ARMtcall GPR:$func)]>,
283 Requires<[IsThumb, HasV5T, IsDarwin]>,
284 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
287 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
288 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
289 "mov\tlr, pc\n\tbx\t$func",
290 [(ARMcall_nolink tGPR:$func)]>,
291 Requires<[IsThumb1Only, IsDarwin]>;
294 let isBranch = 1, isTerminator = 1 in {
295 let isBarrier = 1 in {
296 let isPredicable = 1 in
297 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
298 "b\t$target", [(br bb:$target)]>,
299 T1Encoding<{1,1,1,0,0,?}>;
303 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
304 "bl\t$target\t@ far jump",[]>;
306 def tBR_JTr : T1JTI<(outs),
307 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
308 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
309 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
311 let Inst{15-7} = 0b010001101;
312 let Inst{2-0} = 0b111;
317 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
318 // a two-value operand where a dag node expects two operands. :(
319 let isBranch = 1, isTerminator = 1 in
320 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
322 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
323 T1Encoding<{1,1,0,1,?,?}>;
325 // Compare and branch on zero / non-zero
326 let isBranch = 1, isTerminator = 1 in {
327 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
328 "cbz\t$cmp, $target", []>,
329 T1Misc<{0,0,?,1,?,?,?}>;
331 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
332 "cbnz\t$cmp, $target", []>,
333 T1Misc<{1,0,?,1,?,?,?}>;
336 //===----------------------------------------------------------------------===//
337 // Load Store Instructions.
340 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
341 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
342 "ldr", "\t$dst, $addr",
343 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
346 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
347 "ldrb", "\t$dst, $addr",
348 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
351 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
352 "ldrh", "\t$dst, $addr",
353 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
356 let AddedComplexity = 10 in
357 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
358 "ldrsb", "\t$dst, $addr",
359 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
362 let AddedComplexity = 10 in
363 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
364 "ldrsh", "\t$dst, $addr",
365 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
368 let canFoldAsLoad = 1 in
369 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
370 "ldr", "\t$dst, $addr",
371 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
374 // Special instruction for restore. It cannot clobber condition register
375 // when it's expanded by eliminateCallFramePseudoInstr().
376 let canFoldAsLoad = 1, mayLoad = 1 in
377 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
378 "ldr", "\t$dst, $addr", []>,
382 // FIXME: Use ldr.n to work around a Darwin assembler bug.
383 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
384 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
385 "ldr", ".n\t$dst, $addr",
386 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
387 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
389 // Special LDR for loads from non-pc-relative constpools.
390 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
391 mayHaveSideEffects = 1 in
392 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
393 "ldr", "\t$dst, $addr", []>,
396 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
397 "str", "\t$src, $addr",
398 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
401 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
402 "strb", "\t$src, $addr",
403 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
406 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
407 "strh", "\t$src, $addr",
408 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
411 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
412 "str", "\t$src, $addr",
413 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
416 let mayStore = 1 in {
417 // Special instruction for spill. It cannot clobber condition register
418 // when it's expanded by eliminateCallFramePseudoInstr().
419 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
420 "str", "\t$src, $addr", []>,
424 //===----------------------------------------------------------------------===//
425 // Load / store multiple Instructions.
428 // These requires base address to be written back or one of the loaded regs.
429 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
430 def tLDM : T1I<(outs),
431 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
433 "ldm${addr:submode}${p}\t$addr, $wb", []>,
434 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
436 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
437 def tSTM : T1I<(outs),
438 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
440 "stm${addr:submode}${p}\t$addr, $wb", []>,
441 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
443 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
444 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
446 T1Misc<{1,1,0,?,?,?,?}>;
448 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
449 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
450 "push${p}\t$wb", []>,
451 T1Misc<{0,1,0,?,?,?,?}>;
453 //===----------------------------------------------------------------------===//
454 // Arithmetic Instructions.
457 // Add with carry register
458 let isCommutable = 1, Uses = [CPSR] in
459 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
460 "adc", "\t$dst, $rhs",
461 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
462 T1DataProcessing<0b0101>;
465 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
466 "add", "\t$dst, $lhs, $rhs",
467 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
470 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
471 "add", "\t$dst, $rhs",
472 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
473 T1General<{1,1,0,?,?}>;
476 let isCommutable = 1 in
477 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
478 "add", "\t$dst, $lhs, $rhs",
479 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
482 let neverHasSideEffects = 1 in
483 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
484 "add", "\t$dst, $rhs", []>,
485 T1Special<{0,0,?,?}>;
488 let isCommutable = 1 in
489 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
490 "and", "\t$dst, $rhs",
491 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
492 T1DataProcessing<0b0000>;
495 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
496 "asr", "\t$dst, $lhs, $rhs",
497 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
498 T1General<{0,1,0,?,?}>;
501 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
502 "asr", "\t$dst, $rhs",
503 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
504 T1DataProcessing<0b0100>;
507 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
508 "bic", "\t$dst, $rhs",
509 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
510 T1DataProcessing<0b1110>;
513 let Defs = [CPSR] in {
514 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
515 "cmn", "\t$lhs, $rhs",
516 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
517 T1DataProcessing<0b1011>;
518 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
519 "cmn", "\t$lhs, $rhs",
520 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
521 T1DataProcessing<0b1011>;
525 let Defs = [CPSR] in {
526 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
527 "cmp", "\t$lhs, $rhs",
528 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
529 T1General<{1,0,1,?,?}>;
530 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
531 "cmp", "\t$lhs, $rhs",
532 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
533 T1General<{1,0,1,?,?}>;
537 let Defs = [CPSR] in {
538 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
539 "cmp", "\t$lhs, $rhs",
540 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
541 T1DataProcessing<0b1010>;
542 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
543 "cmp", "\t$lhs, $rhs",
544 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
545 T1DataProcessing<0b1010>;
547 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
548 "cmp", "\t$lhs, $rhs", []>,
549 T1Special<{0,1,?,?}>;
550 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
551 "cmp", "\t$lhs, $rhs", []>,
552 T1Special<{0,1,?,?}>;
557 let isCommutable = 1 in
558 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
559 "eor", "\t$dst, $rhs",
560 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
561 T1DataProcessing<0b0001>;
564 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
565 "lsl", "\t$dst, $lhs, $rhs",
566 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
567 T1General<{0,0,0,?,?}>;
570 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
571 "lsl", "\t$dst, $rhs",
572 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
573 T1DataProcessing<0b0010>;
576 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
577 "lsr", "\t$dst, $lhs, $rhs",
578 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
579 T1General<{0,0,1,?,?}>;
582 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
583 "lsr", "\t$dst, $rhs",
584 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
585 T1DataProcessing<0b0011>;
588 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
589 "mov", "\t$dst, $src",
590 [(set tGPR:$dst, imm0_255:$src)]>,
591 T1General<{1,0,0,?,?}>;
593 // TODO: A7-73: MOV(2) - mov setting flag.
596 let neverHasSideEffects = 1 in {
597 // FIXME: Make this predicable.
598 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
599 "mov\t$dst, $src", []>,
602 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
603 "movs\t$dst, $src", []>, Encoding16 {
604 let Inst{15-6} = 0b0000000000;
607 // FIXME: Make these predicable.
608 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
609 "mov\t$dst, $src", []>,
610 T1Special<{1,0,0,1}>;
611 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
612 "mov\t$dst, $src", []>,
613 T1Special<{1,0,1,0}>;
614 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
615 "mov\t$dst, $src", []>,
616 T1Special<{1,0,1,1}>;
617 } // neverHasSideEffects
620 let isCommutable = 1 in
621 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
622 "mul", "\t$dst, $rhs",
623 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
624 T1DataProcessing<0b1101>;
626 // move inverse register
627 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
628 "mvn", "\t$dst, $src",
629 [(set tGPR:$dst, (not tGPR:$src))]>,
630 T1DataProcessing<0b1111>;
632 // bitwise or register
633 let isCommutable = 1 in
634 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
635 "orr", "\t$dst, $rhs",
636 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
637 T1DataProcessing<0b1100>;
640 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
641 "rev", "\t$dst, $src",
642 [(set tGPR:$dst, (bswap tGPR:$src))]>,
643 Requires<[IsThumb1Only, HasV6]>,
644 T1Misc<{1,0,1,0,0,0,?}>;
646 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
647 "rev16", "\t$dst, $src",
649 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
650 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
651 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
652 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
653 Requires<[IsThumb1Only, HasV6]>,
654 T1Misc<{1,0,1,0,0,1,?}>;
656 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
657 "revsh", "\t$dst, $src",
660 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
661 (shl tGPR:$src, (i32 8))), i16))]>,
662 Requires<[IsThumb1Only, HasV6]>,
663 T1Misc<{1,0,1,0,1,1,?}>;
665 // rotate right register
666 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
667 "ror", "\t$dst, $rhs",
668 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
669 T1DataProcessing<0b0111>;
672 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
673 "rsb", "\t$dst, $src, #0",
674 [(set tGPR:$dst, (ineg tGPR:$src))]>,
675 T1DataProcessing<0b1001>;
677 // Subtract with carry register
679 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
680 "sbc", "\t$dst, $rhs",
681 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
682 T1DataProcessing<0b0110>;
684 // Subtract immediate
685 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
686 "sub", "\t$dst, $lhs, $rhs",
687 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
690 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
691 "sub", "\t$dst, $rhs",
692 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
693 T1General<{1,1,1,?,?}>;
696 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
697 "sub", "\t$dst, $lhs, $rhs",
698 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
701 // TODO: A7-96: STMIA - store multiple.
704 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
705 "sxtb", "\t$dst, $src",
706 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
707 Requires<[IsThumb1Only, HasV6]>,
708 T1Misc<{0,0,1,0,0,1,?}>;
711 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
712 "sxth", "\t$dst, $src",
713 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
714 Requires<[IsThumb1Only, HasV6]>,
715 T1Misc<{0,0,1,0,0,0,?}>;
718 let isCommutable = 1, Defs = [CPSR] in
719 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
720 "tst", "\t$lhs, $rhs",
721 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
722 T1DataProcessing<0b1000>;
725 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
726 "uxtb", "\t$dst, $src",
727 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
728 Requires<[IsThumb1Only, HasV6]>,
729 T1Misc<{0,0,1,0,1,1,?}>;
732 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
733 "uxth", "\t$dst, $src",
734 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
735 Requires<[IsThumb1Only, HasV6]>,
736 T1Misc<{0,0,1,0,1,0,?}>;
739 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
740 // Expanded after instruction selection into a branch sequence.
741 let usesCustomInserter = 1 in // Expanded after instruction selection.
743 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
744 NoItinerary, "@ tMOVCCr $cc",
745 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
748 // 16-bit movcc in IT blocks for Thumb2.
749 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
750 "mov", "\t$dst, $rhs", []>,
751 T1Special<{1,0,?,?}>;
753 def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
754 "mov", "\t$dst, $rhs", []>,
755 T1General<{1,0,0,?,?}>;
757 // tLEApcrel - Load a pc-relative address into a register without offending the
759 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
760 "adr$p\t$dst, #$label", []>,
761 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
763 def tLEApcrelJT : T1I<(outs tGPR:$dst),
764 (ins i32imm:$label, nohash_imm:$id, pred:$p),
765 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
766 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
768 //===----------------------------------------------------------------------===//
772 // __aeabi_read_tp preserves the registers r1-r3.
775 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
776 "bl\t__aeabi_read_tp",
777 [(set R0, ARMthread_pointer)]>;
780 // SJLJ Exception handling intrinsics
781 // eh_sjlj_setjmp() is an instruction sequence to store the return
782 // address and save #0 in R0 for the non-longjmp case.
783 // Since by its nature we may be coming from some other function to get
784 // here, and we're using the stack frame for the containing function to
785 // save/restore registers, we can't keep anything live in regs across
786 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
787 // when we get here from a longjmp(). We force everthing out of registers
788 // except for our own input by listing the relevant registers in Defs. By
789 // doing so, we also cause the prologue/epilogue code to actively preserve
790 // all of the callee-saved resgisters, which is exactly what we want.
792 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
793 def tInt_eh_sjlj_setjmp : ThumbXI<(outs), (ins GPR:$src),
794 AddrModeNone, SizeSpecial, NoItinerary,
795 "mov\tr12, r1\t@ begin eh.setjmp\n"
797 "\tstr\tr1, [$src, #8]\n"
800 "\tstr\tr1, [$src, #4]\n"
805 "0:\tmovs\tr0, #1\t@ end eh.setjmp\n"
807 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
809 //===----------------------------------------------------------------------===//
810 // Non-Instruction Patterns
814 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
815 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
816 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
817 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
818 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
819 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
821 // Subtract with carry
822 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
823 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
824 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
825 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
826 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
827 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
829 // ConstantPool, GlobalAddress
830 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
831 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
834 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
835 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
838 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
839 Requires<[IsThumb, IsNotDarwin]>;
840 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
841 Requires<[IsThumb, IsDarwin]>;
843 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
844 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
845 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
846 Requires<[IsThumb, HasV5T, IsDarwin]>;
848 // Indirect calls to ARM routines
849 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
850 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
851 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
852 Requires<[IsThumb, HasV5T, IsDarwin]>;
854 // zextload i1 -> zextload i8
855 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
856 (tLDRB t_addrmode_s1:$addr)>;
858 // extload -> zextload
859 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
860 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
861 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
863 // If it's impossible to use [r,r] address mode for sextload, select to
864 // ldr{b|h} + sxt{b|h} instead.
865 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
866 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
867 Requires<[IsThumb1Only, HasV6]>;
868 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
869 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
870 Requires<[IsThumb1Only, HasV6]>;
872 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
873 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
874 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
875 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
877 // Large immediate handling.
880 def : T1Pat<(i32 thumb_immshifted:$src),
881 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
882 (thumb_immshifted_shamt imm:$src))>;
884 def : T1Pat<(i32 imm0_255_comp:$src),
885 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
887 // Pseudo instruction that combines ldr from constpool and add pc. This should
888 // be expanded into two instructions late to allow if-conversion and
890 let isReMaterializable = 1 in
891 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
892 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
893 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
895 Requires<[IsThumb1Only]>;