1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
43 def nImmSplatI64 : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmSplatI64AsmOperand;
48 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
49 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
50 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
51 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
52 return ((uint64_t)Imm) < 8;
54 let ParserMatchClass = VectorIndex8Operand;
55 let PrintMethod = "printVectorIndex";
56 let MIOperandInfo = (ops i32imm);
58 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
59 return ((uint64_t)Imm) < 4;
61 let ParserMatchClass = VectorIndex16Operand;
62 let PrintMethod = "printVectorIndex";
63 let MIOperandInfo = (ops i32imm);
65 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
66 return ((uint64_t)Imm) < 2;
68 let ParserMatchClass = VectorIndex32Operand;
69 let PrintMethod = "printVectorIndex";
70 let MIOperandInfo = (ops i32imm);
73 def VecListOneDAsmOperand : AsmOperandClass {
74 let Name = "VecListOneD";
75 let ParserMethod = "parseVectorList";
77 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
78 let ParserMatchClass = VecListOneDAsmOperand;
81 //===----------------------------------------------------------------------===//
82 // NEON-specific DAG Nodes.
83 //===----------------------------------------------------------------------===//
85 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
86 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
88 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
89 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
90 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
91 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
92 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
93 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
94 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
95 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
96 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
97 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
98 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
100 // Types for vector shift by immediates. The "SHX" version is for long and
101 // narrow operations where the source and destination vectors have different
102 // types. The "SHINS" version is for shift and insert operations.
103 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
105 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
107 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
108 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
110 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
111 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
112 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
113 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
114 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
115 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
116 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
118 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
119 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
120 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
122 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
123 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
124 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
125 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
126 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
127 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
129 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
130 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
131 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
133 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
134 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
136 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
138 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
139 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
141 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
142 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
143 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
145 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
147 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
148 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
150 def NEONvbsl : SDNode<"ARMISD::VBSL",
151 SDTypeProfile<1, 3, [SDTCisVec<0>,
154 SDTCisSameAs<0, 3>]>>;
156 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
158 // VDUPLANE can produce a quad-register result from a double-register source,
159 // so the result is not constrained to match the source.
160 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
161 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
164 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
165 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
166 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
168 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
169 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
170 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
171 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
173 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
175 SDTCisSameAs<0, 3>]>;
176 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
177 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
178 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
180 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
181 SDTCisSameAs<1, 2>]>;
182 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
183 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
185 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
186 SDTCisSameAs<0, 2>]>;
187 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
188 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
190 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
191 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
192 unsigned EltBits = 0;
193 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
194 return (EltBits == 32 && EltVal == 0);
197 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
198 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
199 unsigned EltBits = 0;
200 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
201 return (EltBits == 8 && EltVal == 0xff);
204 //===----------------------------------------------------------------------===//
205 // NEON load / store instructions
206 //===----------------------------------------------------------------------===//
208 // Use VLDM to load a Q register as a D register pair.
209 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
211 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
213 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
215 // Use VSTM to store a Q register as a D register pair.
216 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
218 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
220 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
222 // Classes for VLD* pseudo-instructions with multi-register operands.
223 // These are expanded to real instructions after register allocation.
224 class VLDQPseudo<InstrItinClass itin>
225 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
226 class VLDQWBPseudo<InstrItinClass itin>
227 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
228 (ins addrmode6:$addr, am6offset:$offset), itin,
230 class VLDQQPseudo<InstrItinClass itin>
231 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
232 class VLDQQWBPseudo<InstrItinClass itin>
233 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
234 (ins addrmode6:$addr, am6offset:$offset), itin,
236 class VLDQQQQPseudo<InstrItinClass itin>
237 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
239 class VLDQQQQWBPseudo<InstrItinClass itin>
240 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
241 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
242 "$addr.addr = $wb, $src = $dst">;
244 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
246 // VLD1 : Vector Load (multiple single elements)
247 class VLD1D<bits<4> op7_4, string Dt>
248 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
249 (ins addrmode6:$Rn), IIC_VLD1,
250 "vld1", Dt, "$Vd, $Rn", "", []> {
253 let DecoderMethod = "DecodeVLDInstruction";
255 class VLD1Q<bits<4> op7_4, string Dt>
256 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
257 (ins addrmode6:$Rn), IIC_VLD1x2,
258 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
260 let Inst{5-4} = Rn{5-4};
261 let DecoderMethod = "DecodeVLDInstruction";
264 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
265 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
266 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
267 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
269 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
270 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
271 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
272 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
274 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
275 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
276 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
277 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
279 // ...with address register writeback:
280 class VLD1DWB<bits<4> op7_4, string Dt>
281 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
282 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
283 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
284 "$Rn.addr = $wb", []> {
286 let DecoderMethod = "DecodeVLDInstruction";
288 class VLD1QWB<bits<4> op7_4, string Dt>
289 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
290 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
291 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
292 "$Rn.addr = $wb", []> {
293 let Inst{5-4} = Rn{5-4};
294 let DecoderMethod = "DecodeVLDInstruction";
297 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
298 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
299 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
300 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
302 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
303 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
304 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
305 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
307 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
308 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
309 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
310 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
312 // ...with 3 registers
313 class VLD1D3<bits<4> op7_4, string Dt>
314 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
315 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
316 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
319 let DecoderMethod = "DecodeVLDInstruction";
321 class VLD1D3WB<bits<4> op7_4, string Dt>
322 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
323 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
324 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
326 let DecoderMethod = "DecodeVLDInstruction";
329 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
330 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
331 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
332 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
334 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
335 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
336 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
337 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
339 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
340 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
342 // ...with 4 registers
343 class VLD1D4<bits<4> op7_4, string Dt>
344 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
345 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
346 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
348 let Inst{5-4} = Rn{5-4};
349 let DecoderMethod = "DecodeVLDInstruction";
351 class VLD1D4WB<bits<4> op7_4, string Dt>
352 : NLdSt<0,0b10,0b0010,op7_4,
353 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
354 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
355 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
357 let Inst{5-4} = Rn{5-4};
358 let DecoderMethod = "DecodeVLDInstruction";
361 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
362 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
363 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
364 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
366 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
367 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
368 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
369 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
371 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
372 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
374 // VLD2 : Vector Load (multiple 2-element structures)
375 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
376 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
377 (ins addrmode6:$Rn), IIC_VLD2,
378 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
380 let Inst{5-4} = Rn{5-4};
381 let DecoderMethod = "DecodeVLDInstruction";
383 class VLD2Q<bits<4> op7_4, string Dt>
384 : NLdSt<0, 0b10, 0b0011, op7_4,
385 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
386 (ins addrmode6:$Rn), IIC_VLD2x2,
387 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
389 let Inst{5-4} = Rn{5-4};
390 let DecoderMethod = "DecodeVLDInstruction";
393 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
394 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
395 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
397 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
398 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
399 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
401 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
402 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
403 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
405 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
406 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
407 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
409 // ...with address register writeback:
410 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
411 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
412 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
413 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
414 "$Rn.addr = $wb", []> {
415 let Inst{5-4} = Rn{5-4};
416 let DecoderMethod = "DecodeVLDInstruction";
418 class VLD2QWB<bits<4> op7_4, string Dt>
419 : NLdSt<0, 0b10, 0b0011, op7_4,
420 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
421 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
422 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
423 "$Rn.addr = $wb", []> {
424 let Inst{5-4} = Rn{5-4};
425 let DecoderMethod = "DecodeVLDInstruction";
428 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
429 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
430 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
432 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
433 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
434 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
436 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
437 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
438 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
440 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
441 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
442 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
444 // ...with double-spaced registers
445 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
446 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
447 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
448 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
449 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
450 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
452 // VLD3 : Vector Load (multiple 3-element structures)
453 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
454 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
455 (ins addrmode6:$Rn), IIC_VLD3,
456 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
459 let DecoderMethod = "DecodeVLDInstruction";
462 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
463 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
464 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
466 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
467 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
468 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
470 // ...with address register writeback:
471 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
472 : NLdSt<0, 0b10, op11_8, op7_4,
473 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
474 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
475 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
476 "$Rn.addr = $wb", []> {
478 let DecoderMethod = "DecodeVLDInstruction";
481 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
482 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
483 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
485 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
486 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
487 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
489 // ...with double-spaced registers:
490 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
491 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
492 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
493 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
494 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
495 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
497 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
498 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
499 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
501 // ...alternate versions to be allocated odd register numbers:
502 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
503 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
504 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
506 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
507 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
508 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
510 // VLD4 : Vector Load (multiple 4-element structures)
511 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
512 : NLdSt<0, 0b10, op11_8, op7_4,
513 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
514 (ins addrmode6:$Rn), IIC_VLD4,
515 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
517 let Inst{5-4} = Rn{5-4};
518 let DecoderMethod = "DecodeVLDInstruction";
521 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
522 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
523 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
525 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
526 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
527 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
529 // ...with address register writeback:
530 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
531 : NLdSt<0, 0b10, op11_8, op7_4,
532 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
533 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
534 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
535 "$Rn.addr = $wb", []> {
536 let Inst{5-4} = Rn{5-4};
537 let DecoderMethod = "DecodeVLDInstruction";
540 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
541 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
542 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
544 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
545 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
546 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
548 // ...with double-spaced registers:
549 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
550 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
551 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
552 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
553 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
554 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
556 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
557 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
558 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
560 // ...alternate versions to be allocated odd register numbers:
561 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
562 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
563 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
565 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
566 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
567 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
569 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
571 // Classes for VLD*LN pseudo-instructions with multi-register operands.
572 // These are expanded to real instructions after register allocation.
573 class VLDQLNPseudo<InstrItinClass itin>
574 : PseudoNLdSt<(outs QPR:$dst),
575 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
576 itin, "$src = $dst">;
577 class VLDQLNWBPseudo<InstrItinClass itin>
578 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
579 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
580 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
581 class VLDQQLNPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QQPR:$dst),
583 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
584 itin, "$src = $dst">;
585 class VLDQQLNWBPseudo<InstrItinClass itin>
586 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
587 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
588 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
589 class VLDQQQQLNPseudo<InstrItinClass itin>
590 : PseudoNLdSt<(outs QQQQPR:$dst),
591 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
592 itin, "$src = $dst">;
593 class VLDQQQQLNWBPseudo<InstrItinClass itin>
594 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
595 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
596 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
598 // VLD1LN : Vector Load (single element to one lane)
599 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
601 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
602 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
603 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
605 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
606 (i32 (LoadOp addrmode6:$Rn)),
609 let DecoderMethod = "DecodeVLD1LN";
611 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
613 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
614 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
615 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
617 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
618 (i32 (LoadOp addrmode6oneL32:$Rn)),
621 let DecoderMethod = "DecodeVLD1LN";
623 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
624 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
625 (i32 (LoadOp addrmode6:$addr)),
629 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
630 let Inst{7-5} = lane{2-0};
632 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
633 let Inst{7-6} = lane{1-0};
636 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
637 let Inst{7} = lane{0};
642 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
643 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
644 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
646 def : Pat<(vector_insert (v2f32 DPR:$src),
647 (f32 (load addrmode6:$addr)), imm:$lane),
648 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
649 def : Pat<(vector_insert (v4f32 QPR:$src),
650 (f32 (load addrmode6:$addr)), imm:$lane),
651 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
653 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
655 // ...with address register writeback:
656 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
657 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
658 (ins addrmode6:$Rn, am6offset:$Rm,
659 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
660 "\\{$Vd[$lane]\\}, $Rn$Rm",
661 "$src = $Vd, $Rn.addr = $wb", []> {
662 let DecoderMethod = "DecodeVLD1LN";
665 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
666 let Inst{7-5} = lane{2-0};
668 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
669 let Inst{7-6} = lane{1-0};
672 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
673 let Inst{7} = lane{0};
678 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
679 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
680 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
682 // VLD2LN : Vector Load (single 2-element structure to one lane)
683 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
684 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
685 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
686 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
687 "$src1 = $Vd, $src2 = $dst2", []> {
690 let DecoderMethod = "DecodeVLD2LN";
693 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
694 let Inst{7-5} = lane{2-0};
696 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
697 let Inst{7-6} = lane{1-0};
699 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
700 let Inst{7} = lane{0};
703 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
704 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
705 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
707 // ...with double-spaced registers:
708 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
709 let Inst{7-6} = lane{1-0};
711 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
712 let Inst{7} = lane{0};
715 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
716 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
718 // ...with address register writeback:
719 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
720 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
721 (ins addrmode6:$Rn, am6offset:$Rm,
722 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
723 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
724 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
726 let DecoderMethod = "DecodeVLD2LN";
729 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
730 let Inst{7-5} = lane{2-0};
732 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
733 let Inst{7-6} = lane{1-0};
735 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
736 let Inst{7} = lane{0};
739 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
740 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
741 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
743 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
744 let Inst{7-6} = lane{1-0};
746 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
747 let Inst{7} = lane{0};
750 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
751 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
753 // VLD3LN : Vector Load (single 3-element structure to one lane)
754 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
755 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
756 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
757 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
758 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
759 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
761 let DecoderMethod = "DecodeVLD3LN";
764 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
765 let Inst{7-5} = lane{2-0};
767 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
768 let Inst{7-6} = lane{1-0};
770 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
771 let Inst{7} = lane{0};
774 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
775 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
776 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
778 // ...with double-spaced registers:
779 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
780 let Inst{7-6} = lane{1-0};
782 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
783 let Inst{7} = lane{0};
786 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
787 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
789 // ...with address register writeback:
790 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
791 : NLdStLn<1, 0b10, op11_8, op7_4,
792 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
793 (ins addrmode6:$Rn, am6offset:$Rm,
794 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
795 IIC_VLD3lnu, "vld3", Dt,
796 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
797 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
799 let DecoderMethod = "DecodeVLD3LN";
802 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
803 let Inst{7-5} = lane{2-0};
805 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
806 let Inst{7-6} = lane{1-0};
808 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
809 let Inst{7} = lane{0};
812 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
813 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
814 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
816 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
817 let Inst{7-6} = lane{1-0};
819 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
820 let Inst{7} = lane{0};
823 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
824 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
826 // VLD4LN : Vector Load (single 4-element structure to one lane)
827 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
828 : NLdStLn<1, 0b10, op11_8, op7_4,
829 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
830 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
831 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
832 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
833 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
836 let DecoderMethod = "DecodeVLD4LN";
839 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
840 let Inst{7-5} = lane{2-0};
842 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
843 let Inst{7-6} = lane{1-0};
845 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
846 let Inst{7} = lane{0};
850 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
851 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
852 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
854 // ...with double-spaced registers:
855 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
856 let Inst{7-6} = lane{1-0};
858 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
859 let Inst{7} = lane{0};
863 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
864 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
866 // ...with address register writeback:
867 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
868 : NLdStLn<1, 0b10, op11_8, op7_4,
869 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
870 (ins addrmode6:$Rn, am6offset:$Rm,
871 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
872 IIC_VLD4lnu, "vld4", Dt,
873 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
874 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
877 let DecoderMethod = "DecodeVLD4LN" ;
880 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
881 let Inst{7-5} = lane{2-0};
883 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
884 let Inst{7-6} = lane{1-0};
886 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
887 let Inst{7} = lane{0};
891 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
892 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
893 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
895 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
896 let Inst{7-6} = lane{1-0};
898 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
899 let Inst{7} = lane{0};
903 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
904 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
906 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
908 // VLD1DUP : Vector Load (single element to all lanes)
909 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
910 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
911 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
912 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
915 let DecoderMethod = "DecodeVLD1DupInstruction";
917 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
918 let Pattern = [(set QPR:$dst,
919 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
922 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
923 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
924 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
926 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
927 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
928 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
930 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
931 (VLD1DUPd32 addrmode6:$addr)>;
932 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
933 (VLD1DUPq32Pseudo addrmode6:$addr)>;
935 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
937 class VLD1QDUP<bits<4> op7_4, string Dt>
938 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
939 (ins addrmode6dup:$Rn), IIC_VLD1dup,
940 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
943 let DecoderMethod = "DecodeVLD1DupInstruction";
946 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
947 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
948 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
950 // ...with address register writeback:
951 class VLD1DUPWB<bits<4> op7_4, string Dt>
952 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
953 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
954 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
956 let DecoderMethod = "DecodeVLD1DupInstruction";
958 class VLD1QDUPWB<bits<4> op7_4, string Dt>
959 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
960 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
961 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
963 let DecoderMethod = "DecodeVLD1DupInstruction";
966 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
967 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
968 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
970 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
971 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
972 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
974 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
975 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
976 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
978 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
979 class VLD2DUP<bits<4> op7_4, string Dt>
980 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
981 (ins addrmode6dup:$Rn), IIC_VLD2dup,
982 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
985 let DecoderMethod = "DecodeVLD2DupInstruction";
988 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
989 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
990 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
992 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
993 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
994 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
996 // ...with double-spaced registers (not used for codegen):
997 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
998 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
999 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1001 // ...with address register writeback:
1002 class VLD2DUPWB<bits<4> op7_4, string Dt>
1003 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1004 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1005 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1006 let Inst{4} = Rn{4};
1007 let DecoderMethod = "DecodeVLD2DupInstruction";
1010 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1011 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1012 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1014 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1015 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1016 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1018 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1019 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1020 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1022 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1023 class VLD3DUP<bits<4> op7_4, string Dt>
1024 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1025 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1026 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1029 let DecoderMethod = "DecodeVLD3DupInstruction";
1032 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1033 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1034 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1036 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1037 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1038 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1040 // ...with double-spaced registers (not used for codegen):
1041 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1042 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1043 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1045 // ...with address register writeback:
1046 class VLD3DUPWB<bits<4> op7_4, string Dt>
1047 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1048 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1049 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1050 "$Rn.addr = $wb", []> {
1052 let DecoderMethod = "DecodeVLD3DupInstruction";
1055 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1056 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1057 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1059 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1060 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1061 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1063 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1064 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1065 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1067 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1068 class VLD4DUP<bits<4> op7_4, string Dt>
1069 : NLdSt<1, 0b10, 0b1111, op7_4,
1070 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1071 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1072 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1074 let Inst{4} = Rn{4};
1075 let DecoderMethod = "DecodeVLD4DupInstruction";
1078 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1079 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1080 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1082 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1083 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1084 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1086 // ...with double-spaced registers (not used for codegen):
1087 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1088 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1089 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1091 // ...with address register writeback:
1092 class VLD4DUPWB<bits<4> op7_4, string Dt>
1093 : NLdSt<1, 0b10, 0b1111, op7_4,
1094 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1095 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1096 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1097 "$Rn.addr = $wb", []> {
1098 let Inst{4} = Rn{4};
1099 let DecoderMethod = "DecodeVLD4DupInstruction";
1102 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1103 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1104 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1106 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1107 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1108 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1110 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1111 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1112 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1114 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1116 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1118 // Classes for VST* pseudo-instructions with multi-register operands.
1119 // These are expanded to real instructions after register allocation.
1120 class VSTQPseudo<InstrItinClass itin>
1121 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1122 class VSTQWBPseudo<InstrItinClass itin>
1123 : PseudoNLdSt<(outs GPR:$wb),
1124 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1125 "$addr.addr = $wb">;
1126 class VSTQQPseudo<InstrItinClass itin>
1127 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1128 class VSTQQWBPseudo<InstrItinClass itin>
1129 : PseudoNLdSt<(outs GPR:$wb),
1130 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1131 "$addr.addr = $wb">;
1132 class VSTQQQQPseudo<InstrItinClass itin>
1133 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1134 class VSTQQQQWBPseudo<InstrItinClass itin>
1135 : PseudoNLdSt<(outs GPR:$wb),
1136 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1137 "$addr.addr = $wb">;
1139 // VST1 : Vector Store (multiple single elements)
1140 class VST1D<bits<4> op7_4, string Dt>
1141 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1142 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1144 let Inst{4} = Rn{4};
1145 let DecoderMethod = "DecodeVSTInstruction";
1147 class VST1Q<bits<4> op7_4, string Dt>
1148 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1149 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1150 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1152 let Inst{5-4} = Rn{5-4};
1153 let DecoderMethod = "DecodeVSTInstruction";
1156 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1157 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1158 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1159 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1161 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1162 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1163 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1164 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1166 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1167 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1168 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1169 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1171 // ...with address register writeback:
1172 class VST1DWB<bits<4> op7_4, string Dt>
1173 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1174 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1175 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1176 let Inst{4} = Rn{4};
1177 let DecoderMethod = "DecodeVSTInstruction";
1179 class VST1QWB<bits<4> op7_4, string Dt>
1180 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1181 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1182 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1183 "$Rn.addr = $wb", []> {
1184 let Inst{5-4} = Rn{5-4};
1185 let DecoderMethod = "DecodeVSTInstruction";
1188 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1189 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1190 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1191 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1193 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1194 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1195 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1196 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1198 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1199 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1200 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1201 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1203 // ...with 3 registers
1204 class VST1D3<bits<4> op7_4, string Dt>
1205 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1206 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1207 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1209 let Inst{4} = Rn{4};
1210 let DecoderMethod = "DecodeVSTInstruction";
1212 class VST1D3WB<bits<4> op7_4, string Dt>
1213 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1214 (ins addrmode6:$Rn, am6offset:$Rm,
1215 DPR:$Vd, DPR:$src2, DPR:$src3),
1216 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1217 "$Rn.addr = $wb", []> {
1218 let Inst{4} = Rn{4};
1219 let DecoderMethod = "DecodeVSTInstruction";
1222 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1223 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1224 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1225 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1227 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1228 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1229 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1230 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1232 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1233 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1235 // ...with 4 registers
1236 class VST1D4<bits<4> op7_4, string Dt>
1237 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1238 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1239 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1242 let Inst{5-4} = Rn{5-4};
1243 let DecoderMethod = "DecodeVSTInstruction";
1245 class VST1D4WB<bits<4> op7_4, string Dt>
1246 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1247 (ins addrmode6:$Rn, am6offset:$Rm,
1248 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1249 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1250 "$Rn.addr = $wb", []> {
1251 let Inst{5-4} = Rn{5-4};
1252 let DecoderMethod = "DecodeVSTInstruction";
1255 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1256 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1257 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1258 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1260 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1261 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1262 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1263 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1265 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1266 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1268 // VST2 : Vector Store (multiple 2-element structures)
1269 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1270 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1271 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1272 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1274 let Inst{5-4} = Rn{5-4};
1275 let DecoderMethod = "DecodeVSTInstruction";
1277 class VST2Q<bits<4> op7_4, string Dt>
1278 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1279 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1280 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1283 let Inst{5-4} = Rn{5-4};
1284 let DecoderMethod = "DecodeVSTInstruction";
1287 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1288 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1289 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1291 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1292 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1293 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1295 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1296 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1297 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1299 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1300 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1301 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1303 // ...with address register writeback:
1304 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1305 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1306 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1307 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1308 "$Rn.addr = $wb", []> {
1309 let Inst{5-4} = Rn{5-4};
1310 let DecoderMethod = "DecodeVSTInstruction";
1312 class VST2QWB<bits<4> op7_4, string Dt>
1313 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1314 (ins addrmode6:$Rn, am6offset:$Rm,
1315 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1316 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1317 "$Rn.addr = $wb", []> {
1318 let Inst{5-4} = Rn{5-4};
1319 let DecoderMethod = "DecodeVSTInstruction";
1322 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1323 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1324 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1326 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1327 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1328 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1330 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1331 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1332 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1334 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1335 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1336 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1338 // ...with double-spaced registers
1339 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1340 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1341 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1342 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1343 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1344 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1346 // VST3 : Vector Store (multiple 3-element structures)
1347 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1348 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1349 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1350 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1352 let Inst{4} = Rn{4};
1353 let DecoderMethod = "DecodeVSTInstruction";
1356 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1357 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1358 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1360 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1361 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1362 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1364 // ...with address register writeback:
1365 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1366 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1367 (ins addrmode6:$Rn, am6offset:$Rm,
1368 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1369 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1370 "$Rn.addr = $wb", []> {
1371 let Inst{4} = Rn{4};
1372 let DecoderMethod = "DecodeVSTInstruction";
1375 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1376 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1377 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1379 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1380 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1381 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1383 // ...with double-spaced registers:
1384 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1385 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1386 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1387 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1388 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1389 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1391 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1392 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1393 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1395 // ...alternate versions to be allocated odd register numbers:
1396 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1397 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1398 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1400 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1401 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1402 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1404 // VST4 : Vector Store (multiple 4-element structures)
1405 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1406 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1407 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1408 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1411 let Inst{5-4} = Rn{5-4};
1412 let DecoderMethod = "DecodeVSTInstruction";
1415 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1416 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1417 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1419 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1420 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1421 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1423 // ...with address register writeback:
1424 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1425 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1426 (ins addrmode6:$Rn, am6offset:$Rm,
1427 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1428 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1429 "$Rn.addr = $wb", []> {
1430 let Inst{5-4} = Rn{5-4};
1431 let DecoderMethod = "DecodeVSTInstruction";
1434 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1435 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1436 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1438 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1439 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1440 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1442 // ...with double-spaced registers:
1443 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1444 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1445 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1446 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1447 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1448 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1450 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1451 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1452 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1454 // ...alternate versions to be allocated odd register numbers:
1455 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1456 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1457 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1459 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1460 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1461 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1463 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1465 // Classes for VST*LN pseudo-instructions with multi-register operands.
1466 // These are expanded to real instructions after register allocation.
1467 class VSTQLNPseudo<InstrItinClass itin>
1468 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1470 class VSTQLNWBPseudo<InstrItinClass itin>
1471 : PseudoNLdSt<(outs GPR:$wb),
1472 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1473 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1474 class VSTQQLNPseudo<InstrItinClass itin>
1475 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1477 class VSTQQLNWBPseudo<InstrItinClass itin>
1478 : PseudoNLdSt<(outs GPR:$wb),
1479 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1480 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1481 class VSTQQQQLNPseudo<InstrItinClass itin>
1482 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1484 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1485 : PseudoNLdSt<(outs GPR:$wb),
1486 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1487 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1489 // VST1LN : Vector Store (single element from one lane)
1490 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1491 PatFrag StoreOp, SDNode ExtractOp>
1492 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1493 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1494 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1495 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1497 let DecoderMethod = "DecodeVST1LN";
1499 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1500 PatFrag StoreOp, SDNode ExtractOp>
1501 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1502 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1503 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1504 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1506 let DecoderMethod = "DecodeVST1LN";
1508 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1509 : VSTQLNPseudo<IIC_VST1ln> {
1510 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1514 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1516 let Inst{7-5} = lane{2-0};
1518 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1520 let Inst{7-6} = lane{1-0};
1521 let Inst{4} = Rn{5};
1524 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1525 let Inst{7} = lane{0};
1526 let Inst{5-4} = Rn{5-4};
1529 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1530 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1531 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1533 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1534 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1535 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1536 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1538 // ...with address register writeback:
1539 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1540 PatFrag StoreOp, SDNode ExtractOp>
1541 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1542 (ins addrmode6:$Rn, am6offset:$Rm,
1543 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1544 "\\{$Vd[$lane]\\}, $Rn$Rm",
1546 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1547 addrmode6:$Rn, am6offset:$Rm))]> {
1548 let DecoderMethod = "DecodeVST1LN";
1550 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1551 : VSTQLNWBPseudo<IIC_VST1lnu> {
1552 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1553 addrmode6:$addr, am6offset:$offset))];
1556 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1558 let Inst{7-5} = lane{2-0};
1560 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1562 let Inst{7-6} = lane{1-0};
1563 let Inst{4} = Rn{5};
1565 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1567 let Inst{7} = lane{0};
1568 let Inst{5-4} = Rn{5-4};
1571 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1572 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1573 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1575 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1577 // VST2LN : Vector Store (single 2-element structure from one lane)
1578 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1579 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1580 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1581 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1584 let Inst{4} = Rn{4};
1585 let DecoderMethod = "DecodeVST2LN";
1588 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1589 let Inst{7-5} = lane{2-0};
1591 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1592 let Inst{7-6} = lane{1-0};
1594 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1595 let Inst{7} = lane{0};
1598 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1599 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1600 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1602 // ...with double-spaced registers:
1603 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1604 let Inst{7-6} = lane{1-0};
1605 let Inst{4} = Rn{4};
1607 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1608 let Inst{7} = lane{0};
1609 let Inst{4} = Rn{4};
1612 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1613 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1615 // ...with address register writeback:
1616 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1617 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1618 (ins addrmode6:$addr, am6offset:$offset,
1619 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1620 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1621 "$addr.addr = $wb", []> {
1622 let Inst{4} = Rn{4};
1623 let DecoderMethod = "DecodeVST2LN";
1626 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1627 let Inst{7-5} = lane{2-0};
1629 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1630 let Inst{7-6} = lane{1-0};
1632 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1633 let Inst{7} = lane{0};
1636 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1637 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1638 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1640 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1641 let Inst{7-6} = lane{1-0};
1643 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1644 let Inst{7} = lane{0};
1647 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1648 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1650 // VST3LN : Vector Store (single 3-element structure from one lane)
1651 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1652 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1653 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1654 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1655 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1657 let DecoderMethod = "DecodeVST3LN";
1660 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1661 let Inst{7-5} = lane{2-0};
1663 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1664 let Inst{7-6} = lane{1-0};
1666 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1667 let Inst{7} = lane{0};
1670 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1671 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1672 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1674 // ...with double-spaced registers:
1675 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1676 let Inst{7-6} = lane{1-0};
1678 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1679 let Inst{7} = lane{0};
1682 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1683 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1685 // ...with address register writeback:
1686 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1687 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1688 (ins addrmode6:$Rn, am6offset:$Rm,
1689 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1690 IIC_VST3lnu, "vst3", Dt,
1691 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1692 "$Rn.addr = $wb", []> {
1693 let DecoderMethod = "DecodeVST3LN";
1696 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1697 let Inst{7-5} = lane{2-0};
1699 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1700 let Inst{7-6} = lane{1-0};
1702 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1703 let Inst{7} = lane{0};
1706 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1707 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1708 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1710 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1711 let Inst{7-6} = lane{1-0};
1713 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1714 let Inst{7} = lane{0};
1717 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1718 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1720 // VST4LN : Vector Store (single 4-element structure from one lane)
1721 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1722 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1723 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1724 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1725 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1728 let Inst{4} = Rn{4};
1729 let DecoderMethod = "DecodeVST4LN";
1732 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1733 let Inst{7-5} = lane{2-0};
1735 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1736 let Inst{7-6} = lane{1-0};
1738 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1739 let Inst{7} = lane{0};
1740 let Inst{5} = Rn{5};
1743 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1744 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1745 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1747 // ...with double-spaced registers:
1748 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1749 let Inst{7-6} = lane{1-0};
1751 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1752 let Inst{7} = lane{0};
1753 let Inst{5} = Rn{5};
1756 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1757 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1759 // ...with address register writeback:
1760 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1761 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1762 (ins addrmode6:$Rn, am6offset:$Rm,
1763 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1764 IIC_VST4lnu, "vst4", Dt,
1765 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1766 "$Rn.addr = $wb", []> {
1767 let Inst{4} = Rn{4};
1768 let DecoderMethod = "DecodeVST4LN";
1771 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1772 let Inst{7-5} = lane{2-0};
1774 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1775 let Inst{7-6} = lane{1-0};
1777 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1778 let Inst{7} = lane{0};
1779 let Inst{5} = Rn{5};
1782 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1783 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1784 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1786 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1787 let Inst{7-6} = lane{1-0};
1789 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1790 let Inst{7} = lane{0};
1791 let Inst{5} = Rn{5};
1794 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1795 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1797 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1800 //===----------------------------------------------------------------------===//
1801 // NEON pattern fragments
1802 //===----------------------------------------------------------------------===//
1804 // Extract D sub-registers of Q registers.
1805 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1806 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1807 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1809 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1810 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1811 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1813 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1814 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1815 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1817 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1818 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1819 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1822 // Extract S sub-registers of Q/D registers.
1823 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1824 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1825 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1828 // Translate lane numbers from Q registers to D subregs.
1829 def SubReg_i8_lane : SDNodeXForm<imm, [{
1830 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1832 def SubReg_i16_lane : SDNodeXForm<imm, [{
1833 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1835 def SubReg_i32_lane : SDNodeXForm<imm, [{
1836 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1839 //===----------------------------------------------------------------------===//
1840 // Instruction Classes
1841 //===----------------------------------------------------------------------===//
1843 // Basic 2-register operations: double- and quad-register.
1844 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1845 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1846 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1847 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1848 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1849 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1850 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1851 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1852 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1853 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1854 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1855 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1857 // Basic 2-register intrinsics, both double- and quad-register.
1858 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1859 bits<2> op17_16, bits<5> op11_7, bit op4,
1860 InstrItinClass itin, string OpcodeStr, string Dt,
1861 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1862 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1863 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1864 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1865 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1866 bits<2> op17_16, bits<5> op11_7, bit op4,
1867 InstrItinClass itin, string OpcodeStr, string Dt,
1868 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1869 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1870 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1871 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1873 // Narrow 2-register operations.
1874 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1875 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1876 InstrItinClass itin, string OpcodeStr, string Dt,
1877 ValueType TyD, ValueType TyQ, SDNode OpNode>
1878 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1879 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1880 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1882 // Narrow 2-register intrinsics.
1883 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1884 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1885 InstrItinClass itin, string OpcodeStr, string Dt,
1886 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1887 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1888 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1889 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1891 // Long 2-register operations (currently only used for VMOVL).
1892 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1893 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1894 InstrItinClass itin, string OpcodeStr, string Dt,
1895 ValueType TyQ, ValueType TyD, SDNode OpNode>
1896 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1897 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1898 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1900 // Long 2-register intrinsics.
1901 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1902 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1903 InstrItinClass itin, string OpcodeStr, string Dt,
1904 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1905 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1906 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1907 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1909 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1910 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1911 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1912 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1913 OpcodeStr, Dt, "$Vd, $Vm",
1914 "$src1 = $Vd, $src2 = $Vm", []>;
1915 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1916 InstrItinClass itin, string OpcodeStr, string Dt>
1917 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1918 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1919 "$src1 = $Vd, $src2 = $Vm", []>;
1921 // Basic 3-register operations: double- and quad-register.
1922 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1923 InstrItinClass itin, string OpcodeStr, string Dt,
1924 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1925 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1926 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1927 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1928 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1929 let isCommutable = Commutable;
1931 // Same as N3VD but no data type.
1932 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1933 InstrItinClass itin, string OpcodeStr,
1934 ValueType ResTy, ValueType OpTy,
1935 SDNode OpNode, bit Commutable>
1936 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1937 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1938 OpcodeStr, "$Vd, $Vn, $Vm", "",
1939 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1940 let isCommutable = Commutable;
1943 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1944 InstrItinClass itin, string OpcodeStr, string Dt,
1945 ValueType Ty, SDNode ShOp>
1946 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1947 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
1948 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
1950 (Ty (ShOp (Ty DPR:$Vn),
1951 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1952 let isCommutable = 0;
1954 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1955 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1956 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1957 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
1958 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
1960 (Ty (ShOp (Ty DPR:$Vn),
1961 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1962 let isCommutable = 0;
1965 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1966 InstrItinClass itin, string OpcodeStr, string Dt,
1967 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1968 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1969 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1970 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1971 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1972 let isCommutable = Commutable;
1974 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1975 InstrItinClass itin, string OpcodeStr,
1976 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1977 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1978 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1979 OpcodeStr, "$Vd, $Vn, $Vm", "",
1980 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1981 let isCommutable = Commutable;
1983 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1984 InstrItinClass itin, string OpcodeStr, string Dt,
1985 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1986 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
1987 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
1988 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
1989 [(set (ResTy QPR:$Vd),
1990 (ResTy (ShOp (ResTy QPR:$Vn),
1991 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1993 let isCommutable = 0;
1995 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1996 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1997 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
1998 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
1999 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2000 [(set (ResTy QPR:$Vd),
2001 (ResTy (ShOp (ResTy QPR:$Vn),
2002 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2004 let isCommutable = 0;
2007 // Basic 3-register intrinsics, both double- and quad-register.
2008 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2009 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2010 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2011 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2012 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2013 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2014 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2015 let isCommutable = Commutable;
2017 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2018 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2019 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2020 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2021 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2023 (Ty (IntOp (Ty DPR:$Vn),
2024 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2026 let isCommutable = 0;
2028 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2029 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2030 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2031 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2032 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2034 (Ty (IntOp (Ty DPR:$Vn),
2035 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2036 let isCommutable = 0;
2038 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2039 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2040 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2041 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2042 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2043 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2044 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2045 let isCommutable = 0;
2048 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2049 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2050 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2051 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2052 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2053 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2054 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2055 let isCommutable = Commutable;
2057 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2058 string OpcodeStr, string Dt,
2059 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2060 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2061 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2062 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2063 [(set (ResTy QPR:$Vd),
2064 (ResTy (IntOp (ResTy QPR:$Vn),
2065 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2067 let isCommutable = 0;
2069 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2070 string OpcodeStr, string Dt,
2071 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2072 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2073 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2074 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2075 [(set (ResTy QPR:$Vd),
2076 (ResTy (IntOp (ResTy QPR:$Vn),
2077 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2079 let isCommutable = 0;
2081 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2082 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2083 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2084 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2085 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2086 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2087 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2088 let isCommutable = 0;
2091 // Multiply-Add/Sub operations: double- and quad-register.
2092 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2093 InstrItinClass itin, string OpcodeStr, string Dt,
2094 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2095 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2096 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2097 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2098 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2099 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2101 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2102 string OpcodeStr, string Dt,
2103 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2104 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2106 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2108 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2110 (Ty (ShOp (Ty DPR:$src1),
2112 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2114 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2115 string OpcodeStr, string Dt,
2116 ValueType Ty, SDNode MulOp, SDNode ShOp>
2117 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2119 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2121 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2123 (Ty (ShOp (Ty DPR:$src1),
2125 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2128 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2129 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2130 SDPatternOperator MulOp, SDPatternOperator OpNode>
2131 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2132 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2133 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2134 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2135 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2136 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2137 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2138 SDPatternOperator MulOp, SDPatternOperator ShOp>
2139 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2141 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2143 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2144 [(set (ResTy QPR:$Vd),
2145 (ResTy (ShOp (ResTy QPR:$src1),
2146 (ResTy (MulOp QPR:$Vn,
2147 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2149 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2150 string OpcodeStr, string Dt,
2151 ValueType ResTy, ValueType OpTy,
2152 SDNode MulOp, SDNode ShOp>
2153 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2155 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2157 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2158 [(set (ResTy QPR:$Vd),
2159 (ResTy (ShOp (ResTy QPR:$src1),
2160 (ResTy (MulOp QPR:$Vn,
2161 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2164 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2165 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2166 InstrItinClass itin, string OpcodeStr, string Dt,
2167 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2168 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2169 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2170 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2171 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2172 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2173 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2174 InstrItinClass itin, string OpcodeStr, string Dt,
2175 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2176 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2177 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2178 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2179 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2180 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2182 // Neon 3-argument intrinsics, both double- and quad-register.
2183 // The destination register is also used as the first source operand register.
2184 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2185 InstrItinClass itin, string OpcodeStr, string Dt,
2186 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2187 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2188 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2189 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2190 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2191 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2192 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2193 InstrItinClass itin, string OpcodeStr, string Dt,
2194 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2195 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2196 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2197 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2198 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2199 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2201 // Long Multiply-Add/Sub operations.
2202 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2203 InstrItinClass itin, string OpcodeStr, string Dt,
2204 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2205 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2206 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2207 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2208 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2209 (TyQ (MulOp (TyD DPR:$Vn),
2210 (TyD DPR:$Vm)))))]>;
2211 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2212 InstrItinClass itin, string OpcodeStr, string Dt,
2213 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2214 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2215 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2217 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2219 (OpNode (TyQ QPR:$src1),
2220 (TyQ (MulOp (TyD DPR:$Vn),
2221 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2223 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2224 InstrItinClass itin, string OpcodeStr, string Dt,
2225 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2226 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2227 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2229 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2231 (OpNode (TyQ QPR:$src1),
2232 (TyQ (MulOp (TyD DPR:$Vn),
2233 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2236 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2237 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2238 InstrItinClass itin, string OpcodeStr, string Dt,
2239 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2241 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2242 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2243 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2244 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2245 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2246 (TyD DPR:$Vm)))))))]>;
2248 // Neon Long 3-argument intrinsic. The destination register is
2249 // a quad-register and is also used as the first source operand register.
2250 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2251 InstrItinClass itin, string OpcodeStr, string Dt,
2252 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2253 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2254 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2255 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2257 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2258 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2259 string OpcodeStr, string Dt,
2260 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2261 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2263 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2265 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2266 [(set (ResTy QPR:$Vd),
2267 (ResTy (IntOp (ResTy QPR:$src1),
2269 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2271 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2272 InstrItinClass itin, string OpcodeStr, string Dt,
2273 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2274 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2276 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2278 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2279 [(set (ResTy QPR:$Vd),
2280 (ResTy (IntOp (ResTy QPR:$src1),
2282 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2285 // Narrowing 3-register intrinsics.
2286 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2287 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2288 Intrinsic IntOp, bit Commutable>
2289 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2290 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2291 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2292 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2293 let isCommutable = Commutable;
2296 // Long 3-register operations.
2297 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2298 InstrItinClass itin, string OpcodeStr, string Dt,
2299 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2300 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2301 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2302 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2303 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2304 let isCommutable = Commutable;
2306 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2307 InstrItinClass itin, string OpcodeStr, string Dt,
2308 ValueType TyQ, ValueType TyD, SDNode OpNode>
2309 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2310 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2311 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2313 (TyQ (OpNode (TyD DPR:$Vn),
2314 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2315 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2316 InstrItinClass itin, string OpcodeStr, string Dt,
2317 ValueType TyQ, ValueType TyD, SDNode OpNode>
2318 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2319 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2320 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2322 (TyQ (OpNode (TyD DPR:$Vn),
2323 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2325 // Long 3-register operations with explicitly extended operands.
2326 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2327 InstrItinClass itin, string OpcodeStr, string Dt,
2328 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2330 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2331 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2332 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2333 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2334 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2335 let isCommutable = Commutable;
2338 // Long 3-register intrinsics with explicit extend (VABDL).
2339 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2340 InstrItinClass itin, string OpcodeStr, string Dt,
2341 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2343 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2344 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2345 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2346 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2347 (TyD DPR:$Vm))))))]> {
2348 let isCommutable = Commutable;
2351 // Long 3-register intrinsics.
2352 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2353 InstrItinClass itin, string OpcodeStr, string Dt,
2354 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2355 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2356 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2357 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2358 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2359 let isCommutable = Commutable;
2361 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2362 string OpcodeStr, string Dt,
2363 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2364 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2365 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2366 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2367 [(set (ResTy QPR:$Vd),
2368 (ResTy (IntOp (OpTy DPR:$Vn),
2369 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2371 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2372 InstrItinClass itin, string OpcodeStr, string Dt,
2373 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2374 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2375 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2376 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2377 [(set (ResTy QPR:$Vd),
2378 (ResTy (IntOp (OpTy DPR:$Vn),
2379 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2382 // Wide 3-register operations.
2383 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2384 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2385 SDNode OpNode, SDNode ExtOp, bit Commutable>
2386 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2387 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2388 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2389 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2390 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2391 let isCommutable = Commutable;
2394 // Pairwise long 2-register intrinsics, both double- and quad-register.
2395 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2396 bits<2> op17_16, bits<5> op11_7, bit op4,
2397 string OpcodeStr, string Dt,
2398 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2399 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2400 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2401 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2402 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2403 bits<2> op17_16, bits<5> op11_7, bit op4,
2404 string OpcodeStr, string Dt,
2405 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2406 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2407 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2408 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2410 // Pairwise long 2-register accumulate intrinsics,
2411 // both double- and quad-register.
2412 // The destination register is also used as the first source operand register.
2413 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2414 bits<2> op17_16, bits<5> op11_7, bit op4,
2415 string OpcodeStr, string Dt,
2416 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2417 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2418 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2419 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2420 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2421 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2422 bits<2> op17_16, bits<5> op11_7, bit op4,
2423 string OpcodeStr, string Dt,
2424 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2425 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2426 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2427 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2428 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2430 // Shift by immediate,
2431 // both double- and quad-register.
2432 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2433 Format f, InstrItinClass itin, Operand ImmTy,
2434 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2435 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2436 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2437 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2438 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2439 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2440 Format f, InstrItinClass itin, Operand ImmTy,
2441 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2442 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2443 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2444 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2445 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2447 // Long shift by immediate.
2448 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2449 string OpcodeStr, string Dt,
2450 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2451 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2452 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2453 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2454 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2455 (i32 imm:$SIMM))))]>;
2457 // Narrow shift by immediate.
2458 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2459 InstrItinClass itin, string OpcodeStr, string Dt,
2460 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2461 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2462 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2463 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2464 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2465 (i32 imm:$SIMM))))]>;
2467 // Shift right by immediate and accumulate,
2468 // both double- and quad-register.
2469 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2470 Operand ImmTy, string OpcodeStr, string Dt,
2471 ValueType Ty, SDNode ShOp>
2472 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2473 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2474 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2475 [(set DPR:$Vd, (Ty (add DPR:$src1,
2476 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2477 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2478 Operand ImmTy, string OpcodeStr, string Dt,
2479 ValueType Ty, SDNode ShOp>
2480 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2481 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2482 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2483 [(set QPR:$Vd, (Ty (add QPR:$src1,
2484 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2486 // Shift by immediate and insert,
2487 // both double- and quad-register.
2488 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2489 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2490 ValueType Ty,SDNode ShOp>
2491 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2492 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2493 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2494 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2495 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2496 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2497 ValueType Ty,SDNode ShOp>
2498 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2499 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2500 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2501 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2503 // Convert, with fractional bits immediate,
2504 // both double- and quad-register.
2505 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2506 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2508 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2509 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2510 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2511 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2512 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2513 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2515 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2516 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2517 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2518 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2520 //===----------------------------------------------------------------------===//
2522 //===----------------------------------------------------------------------===//
2524 // Abbreviations used in multiclass suffixes:
2525 // Q = quarter int (8 bit) elements
2526 // H = half int (16 bit) elements
2527 // S = single int (32 bit) elements
2528 // D = double int (64 bit) elements
2530 // Neon 2-register vector operations and intrinsics.
2532 // Neon 2-register comparisons.
2533 // source operand element sizes of 8, 16 and 32 bits:
2534 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2535 bits<5> op11_7, bit op4, string opc, string Dt,
2536 string asm, SDNode OpNode> {
2537 // 64-bit vector types.
2538 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2539 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2540 opc, !strconcat(Dt, "8"), asm, "",
2541 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2542 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2543 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2544 opc, !strconcat(Dt, "16"), asm, "",
2545 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2546 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2547 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2548 opc, !strconcat(Dt, "32"), asm, "",
2549 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2550 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2551 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2552 opc, "f32", asm, "",
2553 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2554 let Inst{10} = 1; // overwrite F = 1
2557 // 128-bit vector types.
2558 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2559 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2560 opc, !strconcat(Dt, "8"), asm, "",
2561 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2562 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2563 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2564 opc, !strconcat(Dt, "16"), asm, "",
2565 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2566 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2567 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2568 opc, !strconcat(Dt, "32"), asm, "",
2569 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2570 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2571 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2572 opc, "f32", asm, "",
2573 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2574 let Inst{10} = 1; // overwrite F = 1
2579 // Neon 2-register vector intrinsics,
2580 // element sizes of 8, 16 and 32 bits:
2581 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2582 bits<5> op11_7, bit op4,
2583 InstrItinClass itinD, InstrItinClass itinQ,
2584 string OpcodeStr, string Dt, Intrinsic IntOp> {
2585 // 64-bit vector types.
2586 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2587 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2588 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2589 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2590 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2591 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2593 // 128-bit vector types.
2594 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2595 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2596 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2597 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2598 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2599 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2603 // Neon Narrowing 2-register vector operations,
2604 // source operand element sizes of 16, 32 and 64 bits:
2605 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2606 bits<5> op11_7, bit op6, bit op4,
2607 InstrItinClass itin, string OpcodeStr, string Dt,
2609 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2610 itin, OpcodeStr, !strconcat(Dt, "16"),
2611 v8i8, v8i16, OpNode>;
2612 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2613 itin, OpcodeStr, !strconcat(Dt, "32"),
2614 v4i16, v4i32, OpNode>;
2615 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2616 itin, OpcodeStr, !strconcat(Dt, "64"),
2617 v2i32, v2i64, OpNode>;
2620 // Neon Narrowing 2-register vector intrinsics,
2621 // source operand element sizes of 16, 32 and 64 bits:
2622 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2623 bits<5> op11_7, bit op6, bit op4,
2624 InstrItinClass itin, string OpcodeStr, string Dt,
2626 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2627 itin, OpcodeStr, !strconcat(Dt, "16"),
2628 v8i8, v8i16, IntOp>;
2629 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2630 itin, OpcodeStr, !strconcat(Dt, "32"),
2631 v4i16, v4i32, IntOp>;
2632 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2633 itin, OpcodeStr, !strconcat(Dt, "64"),
2634 v2i32, v2i64, IntOp>;
2638 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2639 // source operand element sizes of 16, 32 and 64 bits:
2640 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2641 string OpcodeStr, string Dt, SDNode OpNode> {
2642 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2643 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2644 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2645 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2646 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2647 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2651 // Neon 3-register vector operations.
2653 // First with only element sizes of 8, 16 and 32 bits:
2654 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2655 InstrItinClass itinD16, InstrItinClass itinD32,
2656 InstrItinClass itinQ16, InstrItinClass itinQ32,
2657 string OpcodeStr, string Dt,
2658 SDNode OpNode, bit Commutable = 0> {
2659 // 64-bit vector types.
2660 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2661 OpcodeStr, !strconcat(Dt, "8"),
2662 v8i8, v8i8, OpNode, Commutable>;
2663 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2664 OpcodeStr, !strconcat(Dt, "16"),
2665 v4i16, v4i16, OpNode, Commutable>;
2666 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2667 OpcodeStr, !strconcat(Dt, "32"),
2668 v2i32, v2i32, OpNode, Commutable>;
2670 // 128-bit vector types.
2671 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2672 OpcodeStr, !strconcat(Dt, "8"),
2673 v16i8, v16i8, OpNode, Commutable>;
2674 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2675 OpcodeStr, !strconcat(Dt, "16"),
2676 v8i16, v8i16, OpNode, Commutable>;
2677 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2678 OpcodeStr, !strconcat(Dt, "32"),
2679 v4i32, v4i32, OpNode, Commutable>;
2682 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2683 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2685 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2687 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2688 v8i16, v4i16, ShOp>;
2689 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2690 v4i32, v2i32, ShOp>;
2693 // ....then also with element size 64 bits:
2694 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2695 InstrItinClass itinD, InstrItinClass itinQ,
2696 string OpcodeStr, string Dt,
2697 SDNode OpNode, bit Commutable = 0>
2698 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2699 OpcodeStr, Dt, OpNode, Commutable> {
2700 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2701 OpcodeStr, !strconcat(Dt, "64"),
2702 v1i64, v1i64, OpNode, Commutable>;
2703 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2704 OpcodeStr, !strconcat(Dt, "64"),
2705 v2i64, v2i64, OpNode, Commutable>;
2709 // Neon 3-register vector intrinsics.
2711 // First with only element sizes of 16 and 32 bits:
2712 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2713 InstrItinClass itinD16, InstrItinClass itinD32,
2714 InstrItinClass itinQ16, InstrItinClass itinQ32,
2715 string OpcodeStr, string Dt,
2716 Intrinsic IntOp, bit Commutable = 0> {
2717 // 64-bit vector types.
2718 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2719 OpcodeStr, !strconcat(Dt, "16"),
2720 v4i16, v4i16, IntOp, Commutable>;
2721 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2722 OpcodeStr, !strconcat(Dt, "32"),
2723 v2i32, v2i32, IntOp, Commutable>;
2725 // 128-bit vector types.
2726 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2727 OpcodeStr, !strconcat(Dt, "16"),
2728 v8i16, v8i16, IntOp, Commutable>;
2729 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2730 OpcodeStr, !strconcat(Dt, "32"),
2731 v4i32, v4i32, IntOp, Commutable>;
2733 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2734 InstrItinClass itinD16, InstrItinClass itinD32,
2735 InstrItinClass itinQ16, InstrItinClass itinQ32,
2736 string OpcodeStr, string Dt,
2738 // 64-bit vector types.
2739 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2740 OpcodeStr, !strconcat(Dt, "16"),
2741 v4i16, v4i16, IntOp>;
2742 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2743 OpcodeStr, !strconcat(Dt, "32"),
2744 v2i32, v2i32, IntOp>;
2746 // 128-bit vector types.
2747 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2748 OpcodeStr, !strconcat(Dt, "16"),
2749 v8i16, v8i16, IntOp>;
2750 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2751 OpcodeStr, !strconcat(Dt, "32"),
2752 v4i32, v4i32, IntOp>;
2755 multiclass N3VIntSL_HS<bits<4> op11_8,
2756 InstrItinClass itinD16, InstrItinClass itinD32,
2757 InstrItinClass itinQ16, InstrItinClass itinQ32,
2758 string OpcodeStr, string Dt, Intrinsic IntOp> {
2759 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2760 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2761 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2762 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2763 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2764 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2765 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2766 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2769 // ....then also with element size of 8 bits:
2770 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2771 InstrItinClass itinD16, InstrItinClass itinD32,
2772 InstrItinClass itinQ16, InstrItinClass itinQ32,
2773 string OpcodeStr, string Dt,
2774 Intrinsic IntOp, bit Commutable = 0>
2775 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2776 OpcodeStr, Dt, IntOp, Commutable> {
2777 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2778 OpcodeStr, !strconcat(Dt, "8"),
2779 v8i8, v8i8, IntOp, Commutable>;
2780 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2781 OpcodeStr, !strconcat(Dt, "8"),
2782 v16i8, v16i8, IntOp, Commutable>;
2784 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2785 InstrItinClass itinD16, InstrItinClass itinD32,
2786 InstrItinClass itinQ16, InstrItinClass itinQ32,
2787 string OpcodeStr, string Dt,
2789 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2790 OpcodeStr, Dt, IntOp> {
2791 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2792 OpcodeStr, !strconcat(Dt, "8"),
2794 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2795 OpcodeStr, !strconcat(Dt, "8"),
2796 v16i8, v16i8, IntOp>;
2800 // ....then also with element size of 64 bits:
2801 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2802 InstrItinClass itinD16, InstrItinClass itinD32,
2803 InstrItinClass itinQ16, InstrItinClass itinQ32,
2804 string OpcodeStr, string Dt,
2805 Intrinsic IntOp, bit Commutable = 0>
2806 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2807 OpcodeStr, Dt, IntOp, Commutable> {
2808 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2809 OpcodeStr, !strconcat(Dt, "64"),
2810 v1i64, v1i64, IntOp, Commutable>;
2811 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2812 OpcodeStr, !strconcat(Dt, "64"),
2813 v2i64, v2i64, IntOp, Commutable>;
2815 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2816 InstrItinClass itinD16, InstrItinClass itinD32,
2817 InstrItinClass itinQ16, InstrItinClass itinQ32,
2818 string OpcodeStr, string Dt,
2820 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2821 OpcodeStr, Dt, IntOp> {
2822 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2823 OpcodeStr, !strconcat(Dt, "64"),
2824 v1i64, v1i64, IntOp>;
2825 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2826 OpcodeStr, !strconcat(Dt, "64"),
2827 v2i64, v2i64, IntOp>;
2830 // Neon Narrowing 3-register vector intrinsics,
2831 // source operand element sizes of 16, 32 and 64 bits:
2832 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2833 string OpcodeStr, string Dt,
2834 Intrinsic IntOp, bit Commutable = 0> {
2835 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2836 OpcodeStr, !strconcat(Dt, "16"),
2837 v8i8, v8i16, IntOp, Commutable>;
2838 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2839 OpcodeStr, !strconcat(Dt, "32"),
2840 v4i16, v4i32, IntOp, Commutable>;
2841 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2842 OpcodeStr, !strconcat(Dt, "64"),
2843 v2i32, v2i64, IntOp, Commutable>;
2847 // Neon Long 3-register vector operations.
2849 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2850 InstrItinClass itin16, InstrItinClass itin32,
2851 string OpcodeStr, string Dt,
2852 SDNode OpNode, bit Commutable = 0> {
2853 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2854 OpcodeStr, !strconcat(Dt, "8"),
2855 v8i16, v8i8, OpNode, Commutable>;
2856 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2857 OpcodeStr, !strconcat(Dt, "16"),
2858 v4i32, v4i16, OpNode, Commutable>;
2859 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2860 OpcodeStr, !strconcat(Dt, "32"),
2861 v2i64, v2i32, OpNode, Commutable>;
2864 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2865 InstrItinClass itin, string OpcodeStr, string Dt,
2867 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2868 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2869 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2870 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2873 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2874 InstrItinClass itin16, InstrItinClass itin32,
2875 string OpcodeStr, string Dt,
2876 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2877 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2878 OpcodeStr, !strconcat(Dt, "8"),
2879 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2880 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2881 OpcodeStr, !strconcat(Dt, "16"),
2882 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2883 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2884 OpcodeStr, !strconcat(Dt, "32"),
2885 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2888 // Neon Long 3-register vector intrinsics.
2890 // First with only element sizes of 16 and 32 bits:
2891 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2892 InstrItinClass itin16, InstrItinClass itin32,
2893 string OpcodeStr, string Dt,
2894 Intrinsic IntOp, bit Commutable = 0> {
2895 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2896 OpcodeStr, !strconcat(Dt, "16"),
2897 v4i32, v4i16, IntOp, Commutable>;
2898 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2899 OpcodeStr, !strconcat(Dt, "32"),
2900 v2i64, v2i32, IntOp, Commutable>;
2903 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2904 InstrItinClass itin, string OpcodeStr, string Dt,
2906 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2907 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2908 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2909 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2912 // ....then also with element size of 8 bits:
2913 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2914 InstrItinClass itin16, InstrItinClass itin32,
2915 string OpcodeStr, string Dt,
2916 Intrinsic IntOp, bit Commutable = 0>
2917 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2918 IntOp, Commutable> {
2919 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2920 OpcodeStr, !strconcat(Dt, "8"),
2921 v8i16, v8i8, IntOp, Commutable>;
2924 // ....with explicit extend (VABDL).
2925 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2926 InstrItinClass itin, string OpcodeStr, string Dt,
2927 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2928 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2929 OpcodeStr, !strconcat(Dt, "8"),
2930 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2931 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2932 OpcodeStr, !strconcat(Dt, "16"),
2933 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2934 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2935 OpcodeStr, !strconcat(Dt, "32"),
2936 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2940 // Neon Wide 3-register vector intrinsics,
2941 // source operand element sizes of 8, 16 and 32 bits:
2942 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2943 string OpcodeStr, string Dt,
2944 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2945 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2946 OpcodeStr, !strconcat(Dt, "8"),
2947 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2948 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2949 OpcodeStr, !strconcat(Dt, "16"),
2950 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2951 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2952 OpcodeStr, !strconcat(Dt, "32"),
2953 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2957 // Neon Multiply-Op vector operations,
2958 // element sizes of 8, 16 and 32 bits:
2959 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2960 InstrItinClass itinD16, InstrItinClass itinD32,
2961 InstrItinClass itinQ16, InstrItinClass itinQ32,
2962 string OpcodeStr, string Dt, SDNode OpNode> {
2963 // 64-bit vector types.
2964 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2965 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2966 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2967 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2968 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2969 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2971 // 128-bit vector types.
2972 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2973 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2974 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2975 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2976 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2977 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2980 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2981 InstrItinClass itinD16, InstrItinClass itinD32,
2982 InstrItinClass itinQ16, InstrItinClass itinQ32,
2983 string OpcodeStr, string Dt, SDNode ShOp> {
2984 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2985 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2986 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2987 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2988 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2989 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2991 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2992 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2996 // Neon Intrinsic-Op vector operations,
2997 // element sizes of 8, 16 and 32 bits:
2998 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2999 InstrItinClass itinD, InstrItinClass itinQ,
3000 string OpcodeStr, string Dt, Intrinsic IntOp,
3002 // 64-bit vector types.
3003 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3004 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3005 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3006 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3007 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3008 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3010 // 128-bit vector types.
3011 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3012 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3013 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3014 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3015 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3016 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3019 // Neon 3-argument intrinsics,
3020 // element sizes of 8, 16 and 32 bits:
3021 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3022 InstrItinClass itinD, InstrItinClass itinQ,
3023 string OpcodeStr, string Dt, Intrinsic IntOp> {
3024 // 64-bit vector types.
3025 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3026 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3027 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3028 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3029 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3030 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3032 // 128-bit vector types.
3033 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3034 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3035 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3036 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3037 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3038 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3042 // Neon Long Multiply-Op vector operations,
3043 // element sizes of 8, 16 and 32 bits:
3044 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3045 InstrItinClass itin16, InstrItinClass itin32,
3046 string OpcodeStr, string Dt, SDNode MulOp,
3048 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3049 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3050 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3051 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3052 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3053 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3056 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3057 string Dt, SDNode MulOp, SDNode OpNode> {
3058 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3059 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3060 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3061 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3065 // Neon Long 3-argument intrinsics.
3067 // First with only element sizes of 16 and 32 bits:
3068 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3069 InstrItinClass itin16, InstrItinClass itin32,
3070 string OpcodeStr, string Dt, Intrinsic IntOp> {
3071 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3072 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3073 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3074 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3077 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3078 string OpcodeStr, string Dt, Intrinsic IntOp> {
3079 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3080 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3081 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3082 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3085 // ....then also with element size of 8 bits:
3086 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3087 InstrItinClass itin16, InstrItinClass itin32,
3088 string OpcodeStr, string Dt, Intrinsic IntOp>
3089 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3090 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3091 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3094 // ....with explicit extend (VABAL).
3095 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3096 InstrItinClass itin, string OpcodeStr, string Dt,
3097 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3098 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3099 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3100 IntOp, ExtOp, OpNode>;
3101 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3102 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3103 IntOp, ExtOp, OpNode>;
3104 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3105 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3106 IntOp, ExtOp, OpNode>;
3110 // Neon Pairwise long 2-register intrinsics,
3111 // element sizes of 8, 16 and 32 bits:
3112 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3113 bits<5> op11_7, bit op4,
3114 string OpcodeStr, string Dt, Intrinsic IntOp> {
3115 // 64-bit vector types.
3116 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3117 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3118 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3119 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3120 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3121 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3123 // 128-bit vector types.
3124 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3125 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3126 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3127 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3128 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3129 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3133 // Neon Pairwise long 2-register accumulate intrinsics,
3134 // element sizes of 8, 16 and 32 bits:
3135 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3136 bits<5> op11_7, bit op4,
3137 string OpcodeStr, string Dt, Intrinsic IntOp> {
3138 // 64-bit vector types.
3139 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3140 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3141 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3142 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3143 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3144 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3146 // 128-bit vector types.
3147 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3148 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3149 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3150 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3151 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3152 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3156 // Neon 2-register vector shift by immediate,
3157 // with f of either N2RegVShLFrm or N2RegVShRFrm
3158 // element sizes of 8, 16, 32 and 64 bits:
3159 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3160 InstrItinClass itin, string OpcodeStr, string Dt,
3162 // 64-bit vector types.
3163 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3164 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3165 let Inst{21-19} = 0b001; // imm6 = 001xxx
3167 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3168 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3169 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3171 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3172 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3173 let Inst{21} = 0b1; // imm6 = 1xxxxx
3175 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3176 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3179 // 128-bit vector types.
3180 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3181 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3182 let Inst{21-19} = 0b001; // imm6 = 001xxx
3184 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3185 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3186 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3188 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3189 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3190 let Inst{21} = 0b1; // imm6 = 1xxxxx
3192 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3193 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3196 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3197 InstrItinClass itin, string OpcodeStr, string Dt,
3199 // 64-bit vector types.
3200 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3201 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3202 let Inst{21-19} = 0b001; // imm6 = 001xxx
3204 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3205 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3206 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3208 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3209 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3210 let Inst{21} = 0b1; // imm6 = 1xxxxx
3212 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3213 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3216 // 128-bit vector types.
3217 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3218 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3219 let Inst{21-19} = 0b001; // imm6 = 001xxx
3221 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3222 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3223 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3225 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3226 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3227 let Inst{21} = 0b1; // imm6 = 1xxxxx
3229 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3230 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3234 // Neon Shift-Accumulate vector operations,
3235 // element sizes of 8, 16, 32 and 64 bits:
3236 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3237 string OpcodeStr, string Dt, SDNode ShOp> {
3238 // 64-bit vector types.
3239 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3240 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3241 let Inst{21-19} = 0b001; // imm6 = 001xxx
3243 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3244 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3245 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3247 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3248 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3249 let Inst{21} = 0b1; // imm6 = 1xxxxx
3251 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3252 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3255 // 128-bit vector types.
3256 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3257 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3258 let Inst{21-19} = 0b001; // imm6 = 001xxx
3260 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3261 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3262 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3264 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3265 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3266 let Inst{21} = 0b1; // imm6 = 1xxxxx
3268 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3269 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3273 // Neon Shift-Insert vector operations,
3274 // with f of either N2RegVShLFrm or N2RegVShRFrm
3275 // element sizes of 8, 16, 32 and 64 bits:
3276 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3278 // 64-bit vector types.
3279 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3280 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3281 let Inst{21-19} = 0b001; // imm6 = 001xxx
3283 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3284 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3285 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3287 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3288 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3289 let Inst{21} = 0b1; // imm6 = 1xxxxx
3291 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3292 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3295 // 128-bit vector types.
3296 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3297 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3298 let Inst{21-19} = 0b001; // imm6 = 001xxx
3300 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3301 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3302 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3304 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3305 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3306 let Inst{21} = 0b1; // imm6 = 1xxxxx
3308 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3309 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3312 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3314 // 64-bit vector types.
3315 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3316 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3317 let Inst{21-19} = 0b001; // imm6 = 001xxx
3319 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3320 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3321 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3323 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3324 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3325 let Inst{21} = 0b1; // imm6 = 1xxxxx
3327 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3328 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3331 // 128-bit vector types.
3332 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3333 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3334 let Inst{21-19} = 0b001; // imm6 = 001xxx
3336 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3337 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3338 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3340 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3341 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3342 let Inst{21} = 0b1; // imm6 = 1xxxxx
3344 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3345 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3349 // Neon Shift Long operations,
3350 // element sizes of 8, 16, 32 bits:
3351 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3352 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3353 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3354 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3355 let Inst{21-19} = 0b001; // imm6 = 001xxx
3357 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3358 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3359 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3361 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3362 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3363 let Inst{21} = 0b1; // imm6 = 1xxxxx
3367 // Neon Shift Narrow operations,
3368 // element sizes of 16, 32, 64 bits:
3369 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3370 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3372 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3373 OpcodeStr, !strconcat(Dt, "16"),
3374 v8i8, v8i16, shr_imm8, OpNode> {
3375 let Inst{21-19} = 0b001; // imm6 = 001xxx
3377 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3378 OpcodeStr, !strconcat(Dt, "32"),
3379 v4i16, v4i32, shr_imm16, OpNode> {
3380 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3382 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3383 OpcodeStr, !strconcat(Dt, "64"),
3384 v2i32, v2i64, shr_imm32, OpNode> {
3385 let Inst{21} = 0b1; // imm6 = 1xxxxx
3389 //===----------------------------------------------------------------------===//
3390 // Instruction Definitions.
3391 //===----------------------------------------------------------------------===//
3393 // Vector Add Operations.
3395 // VADD : Vector Add (integer and floating-point)
3396 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3398 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3399 v2f32, v2f32, fadd, 1>;
3400 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3401 v4f32, v4f32, fadd, 1>;
3402 // VADDL : Vector Add Long (Q = D + D)
3403 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3404 "vaddl", "s", add, sext, 1>;
3405 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3406 "vaddl", "u", add, zext, 1>;
3407 // VADDW : Vector Add Wide (Q = Q + D)
3408 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3409 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3410 // VHADD : Vector Halving Add
3411 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3412 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3413 "vhadd", "s", int_arm_neon_vhadds, 1>;
3414 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3415 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3416 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3417 // VRHADD : Vector Rounding Halving Add
3418 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3419 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3420 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3421 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3422 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3423 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3424 // VQADD : Vector Saturating Add
3425 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3426 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3427 "vqadd", "s", int_arm_neon_vqadds, 1>;
3428 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3429 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3430 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3431 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3432 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3433 int_arm_neon_vaddhn, 1>;
3434 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3435 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3436 int_arm_neon_vraddhn, 1>;
3438 // Vector Multiply Operations.
3440 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3441 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3442 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3443 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3444 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3445 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3446 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3447 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3448 v2f32, v2f32, fmul, 1>;
3449 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3450 v4f32, v4f32, fmul, 1>;
3451 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3452 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3453 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3456 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3457 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3458 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3459 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3460 (DSubReg_i16_reg imm:$lane))),
3461 (SubReg_i16_lane imm:$lane)))>;
3462 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3463 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3464 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3465 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3466 (DSubReg_i32_reg imm:$lane))),
3467 (SubReg_i32_lane imm:$lane)))>;
3468 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3469 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3470 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3471 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3472 (DSubReg_i32_reg imm:$lane))),
3473 (SubReg_i32_lane imm:$lane)))>;
3475 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3476 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3477 IIC_VMULi16Q, IIC_VMULi32Q,
3478 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3479 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3480 IIC_VMULi16Q, IIC_VMULi32Q,
3481 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3482 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3483 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3485 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3486 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3487 (DSubReg_i16_reg imm:$lane))),
3488 (SubReg_i16_lane imm:$lane)))>;
3489 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3490 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3492 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3493 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3494 (DSubReg_i32_reg imm:$lane))),
3495 (SubReg_i32_lane imm:$lane)))>;
3497 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3498 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3499 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3500 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3501 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3502 IIC_VMULi16Q, IIC_VMULi32Q,
3503 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3504 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3505 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3507 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3508 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3509 (DSubReg_i16_reg imm:$lane))),
3510 (SubReg_i16_lane imm:$lane)))>;
3511 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3512 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3514 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3515 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3516 (DSubReg_i32_reg imm:$lane))),
3517 (SubReg_i32_lane imm:$lane)))>;
3519 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3520 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3521 "vmull", "s", NEONvmulls, 1>;
3522 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3523 "vmull", "u", NEONvmullu, 1>;
3524 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3525 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3526 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3527 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3529 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3530 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3531 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3532 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3533 "vqdmull", "s", int_arm_neon_vqdmull>;
3535 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3537 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3538 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3539 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3540 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3541 v2f32, fmul_su, fadd_mlx>,
3542 Requires<[HasNEON, UseFPVMLx]>;
3543 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3544 v4f32, fmul_su, fadd_mlx>,
3545 Requires<[HasNEON, UseFPVMLx]>;
3546 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3547 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3548 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3549 v2f32, fmul_su, fadd_mlx>,
3550 Requires<[HasNEON, UseFPVMLx]>;
3551 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3552 v4f32, v2f32, fmul_su, fadd_mlx>,
3553 Requires<[HasNEON, UseFPVMLx]>;
3555 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3556 (mul (v8i16 QPR:$src2),
3557 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3558 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3559 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3560 (DSubReg_i16_reg imm:$lane))),
3561 (SubReg_i16_lane imm:$lane)))>;
3563 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3564 (mul (v4i32 QPR:$src2),
3565 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3566 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3567 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3568 (DSubReg_i32_reg imm:$lane))),
3569 (SubReg_i32_lane imm:$lane)))>;
3571 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3572 (fmul_su (v4f32 QPR:$src2),
3573 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3574 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3576 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3577 (DSubReg_i32_reg imm:$lane))),
3578 (SubReg_i32_lane imm:$lane)))>,
3579 Requires<[HasNEON, UseFPVMLx]>;
3581 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3582 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3583 "vmlal", "s", NEONvmulls, add>;
3584 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3585 "vmlal", "u", NEONvmullu, add>;
3587 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3588 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3590 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3591 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3592 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3593 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3595 // VMLS : Vector Multiply Subtract (integer and floating-point)
3596 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3597 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3598 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3599 v2f32, fmul_su, fsub_mlx>,
3600 Requires<[HasNEON, UseFPVMLx]>;
3601 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3602 v4f32, fmul_su, fsub_mlx>,
3603 Requires<[HasNEON, UseFPVMLx]>;
3604 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3605 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3606 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3607 v2f32, fmul_su, fsub_mlx>,
3608 Requires<[HasNEON, UseFPVMLx]>;
3609 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3610 v4f32, v2f32, fmul_su, fsub_mlx>,
3611 Requires<[HasNEON, UseFPVMLx]>;
3613 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3614 (mul (v8i16 QPR:$src2),
3615 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3616 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3617 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3618 (DSubReg_i16_reg imm:$lane))),
3619 (SubReg_i16_lane imm:$lane)))>;
3621 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3622 (mul (v4i32 QPR:$src2),
3623 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3624 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3625 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3626 (DSubReg_i32_reg imm:$lane))),
3627 (SubReg_i32_lane imm:$lane)))>;
3629 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3630 (fmul_su (v4f32 QPR:$src2),
3631 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3632 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3633 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3634 (DSubReg_i32_reg imm:$lane))),
3635 (SubReg_i32_lane imm:$lane)))>,
3636 Requires<[HasNEON, UseFPVMLx]>;
3638 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3639 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3640 "vmlsl", "s", NEONvmulls, sub>;
3641 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3642 "vmlsl", "u", NEONvmullu, sub>;
3644 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3645 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3647 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3648 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3649 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3650 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3652 // Vector Subtract Operations.
3654 // VSUB : Vector Subtract (integer and floating-point)
3655 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3656 "vsub", "i", sub, 0>;
3657 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3658 v2f32, v2f32, fsub, 0>;
3659 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3660 v4f32, v4f32, fsub, 0>;
3661 // VSUBL : Vector Subtract Long (Q = D - D)
3662 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3663 "vsubl", "s", sub, sext, 0>;
3664 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3665 "vsubl", "u", sub, zext, 0>;
3666 // VSUBW : Vector Subtract Wide (Q = Q - D)
3667 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3668 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3669 // VHSUB : Vector Halving Subtract
3670 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3671 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3672 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3673 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3674 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3675 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3676 // VQSUB : Vector Saturing Subtract
3677 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3678 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3679 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3680 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3681 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3682 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3683 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3684 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3685 int_arm_neon_vsubhn, 0>;
3686 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3687 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3688 int_arm_neon_vrsubhn, 0>;
3690 // Vector Comparisons.
3692 // VCEQ : Vector Compare Equal
3693 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3694 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3695 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3697 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3700 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3701 "$Vd, $Vm, #0", NEONvceqz>;
3703 // VCGE : Vector Compare Greater Than or Equal
3704 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3705 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3706 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3707 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3708 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3710 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3713 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3714 "$Vd, $Vm, #0", NEONvcgez>;
3715 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3716 "$Vd, $Vm, #0", NEONvclez>;
3718 // VCGT : Vector Compare Greater Than
3719 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3720 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3721 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3722 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3723 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3725 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3728 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3729 "$Vd, $Vm, #0", NEONvcgtz>;
3730 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3731 "$Vd, $Vm, #0", NEONvcltz>;
3733 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3734 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3735 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3736 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3737 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3738 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3739 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3740 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3741 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3742 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3743 // VTST : Vector Test Bits
3744 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3745 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3747 // Vector Bitwise Operations.
3749 def vnotd : PatFrag<(ops node:$in),
3750 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3751 def vnotq : PatFrag<(ops node:$in),
3752 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3755 // VAND : Vector Bitwise AND
3756 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3757 v2i32, v2i32, and, 1>;
3758 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3759 v4i32, v4i32, and, 1>;
3761 // VEOR : Vector Bitwise Exclusive OR
3762 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3763 v2i32, v2i32, xor, 1>;
3764 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3765 v4i32, v4i32, xor, 1>;
3767 // VORR : Vector Bitwise OR
3768 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3769 v2i32, v2i32, or, 1>;
3770 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3771 v4i32, v4i32, or, 1>;
3773 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3774 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3776 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3778 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3779 let Inst{9} = SIMM{9};
3782 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3783 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3785 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3787 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3788 let Inst{10-9} = SIMM{10-9};
3791 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3792 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3794 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3796 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3797 let Inst{9} = SIMM{9};
3800 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3801 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3803 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3805 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3806 let Inst{10-9} = SIMM{10-9};
3810 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3811 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3812 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3813 "vbic", "$Vd, $Vn, $Vm", "",
3814 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3815 (vnotd DPR:$Vm))))]>;
3816 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3817 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3818 "vbic", "$Vd, $Vn, $Vm", "",
3819 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3820 (vnotq QPR:$Vm))))]>;
3822 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3823 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3825 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3827 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3828 let Inst{9} = SIMM{9};
3831 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3832 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3834 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3836 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3837 let Inst{10-9} = SIMM{10-9};
3840 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3841 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3843 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3845 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3846 let Inst{9} = SIMM{9};
3849 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3850 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3852 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3854 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3855 let Inst{10-9} = SIMM{10-9};
3858 // VORN : Vector Bitwise OR NOT
3859 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3860 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3861 "vorn", "$Vd, $Vn, $Vm", "",
3862 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3863 (vnotd DPR:$Vm))))]>;
3864 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3865 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3866 "vorn", "$Vd, $Vn, $Vm", "",
3867 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3868 (vnotq QPR:$Vm))))]>;
3870 // VMVN : Vector Bitwise NOT (Immediate)
3872 let isReMaterializable = 1 in {
3874 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3875 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3876 "vmvn", "i16", "$Vd, $SIMM", "",
3877 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3878 let Inst{9} = SIMM{9};
3881 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3882 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3883 "vmvn", "i16", "$Vd, $SIMM", "",
3884 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3885 let Inst{9} = SIMM{9};
3888 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3889 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3890 "vmvn", "i32", "$Vd, $SIMM", "",
3891 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3892 let Inst{11-8} = SIMM{11-8};
3895 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3896 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3897 "vmvn", "i32", "$Vd, $SIMM", "",
3898 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3899 let Inst{11-8} = SIMM{11-8};
3903 // VMVN : Vector Bitwise NOT
3904 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3905 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3906 "vmvn", "$Vd, $Vm", "",
3907 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3908 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3909 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3910 "vmvn", "$Vd, $Vm", "",
3911 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3912 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3913 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3915 // VBSL : Vector Bitwise Select
3916 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3917 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3918 N3RegFrm, IIC_VCNTiD,
3919 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3921 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3923 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3924 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3925 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3927 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3928 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3929 N3RegFrm, IIC_VCNTiQ,
3930 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3932 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3934 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3935 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3936 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3938 // VBIF : Vector Bitwise Insert if False
3939 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3940 // FIXME: This instruction's encoding MAY NOT BE correct.
3941 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3942 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3943 N3RegFrm, IIC_VBINiD,
3944 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3946 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3947 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3948 N3RegFrm, IIC_VBINiQ,
3949 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3952 // VBIT : Vector Bitwise Insert if True
3953 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3954 // FIXME: This instruction's encoding MAY NOT BE correct.
3955 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3956 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3957 N3RegFrm, IIC_VBINiD,
3958 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3960 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3961 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3962 N3RegFrm, IIC_VBINiQ,
3963 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3966 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3967 // for equivalent operations with different register constraints; it just
3970 // Vector Absolute Differences.
3972 // VABD : Vector Absolute Difference
3973 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3974 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3975 "vabd", "s", int_arm_neon_vabds, 1>;
3976 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3977 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3978 "vabd", "u", int_arm_neon_vabdu, 1>;
3979 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3980 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3981 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3982 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3984 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3985 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3986 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3987 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3988 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3990 // VABA : Vector Absolute Difference and Accumulate
3991 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3992 "vaba", "s", int_arm_neon_vabds, add>;
3993 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3994 "vaba", "u", int_arm_neon_vabdu, add>;
3996 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3997 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3998 "vabal", "s", int_arm_neon_vabds, zext, add>;
3999 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4000 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4002 // Vector Maximum and Minimum.
4004 // VMAX : Vector Maximum
4005 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4006 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4007 "vmax", "s", int_arm_neon_vmaxs, 1>;
4008 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4009 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4010 "vmax", "u", int_arm_neon_vmaxu, 1>;
4011 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4013 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4014 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4016 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4018 // VMIN : Vector Minimum
4019 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4020 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4021 "vmin", "s", int_arm_neon_vmins, 1>;
4022 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4023 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4024 "vmin", "u", int_arm_neon_vminu, 1>;
4025 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4027 v2f32, v2f32, int_arm_neon_vmins, 1>;
4028 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4030 v4f32, v4f32, int_arm_neon_vmins, 1>;
4032 // Vector Pairwise Operations.
4034 // VPADD : Vector Pairwise Add
4035 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4037 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4038 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4040 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4041 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4043 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4044 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4045 IIC_VPBIND, "vpadd", "f32",
4046 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4048 // VPADDL : Vector Pairwise Add Long
4049 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4050 int_arm_neon_vpaddls>;
4051 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4052 int_arm_neon_vpaddlu>;
4054 // VPADAL : Vector Pairwise Add and Accumulate Long
4055 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4056 int_arm_neon_vpadals>;
4057 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4058 int_arm_neon_vpadalu>;
4060 // VPMAX : Vector Pairwise Maximum
4061 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4062 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4063 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4064 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4065 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4066 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4067 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4068 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4069 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4070 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4071 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4072 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4073 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4074 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4076 // VPMIN : Vector Pairwise Minimum
4077 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4078 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4079 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4080 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4081 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4082 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4083 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4084 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4085 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4086 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4087 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4088 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4089 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4090 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4092 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4094 // VRECPE : Vector Reciprocal Estimate
4095 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4096 IIC_VUNAD, "vrecpe", "u32",
4097 v2i32, v2i32, int_arm_neon_vrecpe>;
4098 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4099 IIC_VUNAQ, "vrecpe", "u32",
4100 v4i32, v4i32, int_arm_neon_vrecpe>;
4101 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4102 IIC_VUNAD, "vrecpe", "f32",
4103 v2f32, v2f32, int_arm_neon_vrecpe>;
4104 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4105 IIC_VUNAQ, "vrecpe", "f32",
4106 v4f32, v4f32, int_arm_neon_vrecpe>;
4108 // VRECPS : Vector Reciprocal Step
4109 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4110 IIC_VRECSD, "vrecps", "f32",
4111 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4112 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4113 IIC_VRECSQ, "vrecps", "f32",
4114 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4116 // VRSQRTE : Vector Reciprocal Square Root Estimate
4117 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4118 IIC_VUNAD, "vrsqrte", "u32",
4119 v2i32, v2i32, int_arm_neon_vrsqrte>;
4120 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4121 IIC_VUNAQ, "vrsqrte", "u32",
4122 v4i32, v4i32, int_arm_neon_vrsqrte>;
4123 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4124 IIC_VUNAD, "vrsqrte", "f32",
4125 v2f32, v2f32, int_arm_neon_vrsqrte>;
4126 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4127 IIC_VUNAQ, "vrsqrte", "f32",
4128 v4f32, v4f32, int_arm_neon_vrsqrte>;
4130 // VRSQRTS : Vector Reciprocal Square Root Step
4131 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4132 IIC_VRECSD, "vrsqrts", "f32",
4133 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4134 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4135 IIC_VRECSQ, "vrsqrts", "f32",
4136 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4140 // VSHL : Vector Shift
4141 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4142 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4143 "vshl", "s", int_arm_neon_vshifts>;
4144 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4145 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4146 "vshl", "u", int_arm_neon_vshiftu>;
4148 // VSHL : Vector Shift Left (Immediate)
4149 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4151 // VSHR : Vector Shift Right (Immediate)
4152 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4153 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4155 // VSHLL : Vector Shift Left Long
4156 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4157 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4159 // VSHLL : Vector Shift Left Long (with maximum shift count)
4160 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4161 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4162 ValueType OpTy, SDNode OpNode>
4163 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4164 ResTy, OpTy, OpNode> {
4165 let Inst{21-16} = op21_16;
4166 let DecoderMethod = "DecodeVSHLMaxInstruction";
4168 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4169 v8i16, v8i8, NEONvshlli>;
4170 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4171 v4i32, v4i16, NEONvshlli>;
4172 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4173 v2i64, v2i32, NEONvshlli>;
4175 // VSHRN : Vector Shift Right and Narrow
4176 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4179 // VRSHL : Vector Rounding Shift
4180 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4181 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4182 "vrshl", "s", int_arm_neon_vrshifts>;
4183 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4184 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4185 "vrshl", "u", int_arm_neon_vrshiftu>;
4186 // VRSHR : Vector Rounding Shift Right
4187 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4188 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4190 // VRSHRN : Vector Rounding Shift Right and Narrow
4191 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4194 // VQSHL : Vector Saturating Shift
4195 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4196 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4197 "vqshl", "s", int_arm_neon_vqshifts>;
4198 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4199 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4200 "vqshl", "u", int_arm_neon_vqshiftu>;
4201 // VQSHL : Vector Saturating Shift Left (Immediate)
4202 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4203 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4205 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4206 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4208 // VQSHRN : Vector Saturating Shift Right and Narrow
4209 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4211 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4214 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4215 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4218 // VQRSHL : Vector Saturating Rounding Shift
4219 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4220 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4221 "vqrshl", "s", int_arm_neon_vqrshifts>;
4222 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4223 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4224 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4226 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4227 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4229 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4232 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4233 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4236 // VSRA : Vector Shift Right and Accumulate
4237 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4238 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4239 // VRSRA : Vector Rounding Shift Right and Accumulate
4240 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4241 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4243 // VSLI : Vector Shift Left and Insert
4244 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4246 // VSRI : Vector Shift Right and Insert
4247 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4249 // Vector Absolute and Saturating Absolute.
4251 // VABS : Vector Absolute Value
4252 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4253 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4255 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4256 IIC_VUNAD, "vabs", "f32",
4257 v2f32, v2f32, int_arm_neon_vabs>;
4258 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4259 IIC_VUNAQ, "vabs", "f32",
4260 v4f32, v4f32, int_arm_neon_vabs>;
4262 // VQABS : Vector Saturating Absolute Value
4263 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4264 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4265 int_arm_neon_vqabs>;
4269 def vnegd : PatFrag<(ops node:$in),
4270 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4271 def vnegq : PatFrag<(ops node:$in),
4272 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4274 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4275 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4276 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4277 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4278 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4279 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4280 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4281 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4283 // VNEG : Vector Negate (integer)
4284 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4285 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4286 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4287 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4288 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4289 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4291 // VNEG : Vector Negate (floating-point)
4292 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4293 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4294 "vneg", "f32", "$Vd, $Vm", "",
4295 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4296 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4297 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4298 "vneg", "f32", "$Vd, $Vm", "",
4299 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4301 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4302 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4303 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4304 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4305 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4306 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4308 // VQNEG : Vector Saturating Negate
4309 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4310 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4311 int_arm_neon_vqneg>;
4313 // Vector Bit Counting Operations.
4315 // VCLS : Vector Count Leading Sign Bits
4316 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4317 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4319 // VCLZ : Vector Count Leading Zeros
4320 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4321 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4323 // VCNT : Vector Count One Bits
4324 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4325 IIC_VCNTiD, "vcnt", "8",
4326 v8i8, v8i8, int_arm_neon_vcnt>;
4327 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4328 IIC_VCNTiQ, "vcnt", "8",
4329 v16i8, v16i8, int_arm_neon_vcnt>;
4332 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4333 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4334 "vswp", "$Vd, $Vm", "", []>;
4335 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4336 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4337 "vswp", "$Vd, $Vm", "", []>;
4339 // Vector Move Operations.
4341 // VMOV : Vector Move (Register)
4342 def : InstAlias<"vmov${p} $Vd, $Vm",
4343 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4344 def : InstAlias<"vmov${p} $Vd, $Vm",
4345 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4347 // VMOV : Vector Move (Immediate)
4349 let isReMaterializable = 1 in {
4350 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4351 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4352 "vmov", "i8", "$Vd, $SIMM", "",
4353 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4354 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4355 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4356 "vmov", "i8", "$Vd, $SIMM", "",
4357 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4359 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4360 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4361 "vmov", "i16", "$Vd, $SIMM", "",
4362 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4363 let Inst{9} = SIMM{9};
4366 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4367 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4368 "vmov", "i16", "$Vd, $SIMM", "",
4369 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4370 let Inst{9} = SIMM{9};
4373 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4374 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4375 "vmov", "i32", "$Vd, $SIMM", "",
4376 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4377 let Inst{11-8} = SIMM{11-8};
4380 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4381 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4382 "vmov", "i32", "$Vd, $SIMM", "",
4383 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4384 let Inst{11-8} = SIMM{11-8};
4387 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4388 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4389 "vmov", "i64", "$Vd, $SIMM", "",
4390 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4391 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4392 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4393 "vmov", "i64", "$Vd, $SIMM", "",
4394 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4395 } // isReMaterializable
4397 // VMOV : Vector Get Lane (move scalar to ARM core register)
4399 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4400 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4401 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4402 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4404 let Inst{21} = lane{2};
4405 let Inst{6-5} = lane{1-0};
4407 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4408 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4409 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4410 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4412 let Inst{21} = lane{1};
4413 let Inst{6} = lane{0};
4415 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4416 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4417 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4418 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4420 let Inst{21} = lane{2};
4421 let Inst{6-5} = lane{1-0};
4423 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4424 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4425 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4426 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4428 let Inst{21} = lane{1};
4429 let Inst{6} = lane{0};
4431 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4432 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4433 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4434 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4436 let Inst{21} = lane{0};
4438 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4439 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4440 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4441 (DSubReg_i8_reg imm:$lane))),
4442 (SubReg_i8_lane imm:$lane))>;
4443 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4444 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4445 (DSubReg_i16_reg imm:$lane))),
4446 (SubReg_i16_lane imm:$lane))>;
4447 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4448 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4449 (DSubReg_i8_reg imm:$lane))),
4450 (SubReg_i8_lane imm:$lane))>;
4451 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4452 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4453 (DSubReg_i16_reg imm:$lane))),
4454 (SubReg_i16_lane imm:$lane))>;
4455 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4456 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4457 (DSubReg_i32_reg imm:$lane))),
4458 (SubReg_i32_lane imm:$lane))>;
4459 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4460 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4461 (SSubReg_f32_reg imm:$src2))>;
4462 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4463 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4464 (SSubReg_f32_reg imm:$src2))>;
4465 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4466 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4467 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4468 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4471 // VMOV : Vector Set Lane (move ARM core register to scalar)
4473 let Constraints = "$src1 = $V" in {
4474 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4475 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4476 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4477 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4478 GPR:$R, imm:$lane))]> {
4479 let Inst{21} = lane{2};
4480 let Inst{6-5} = lane{1-0};
4482 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4483 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4484 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4485 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4486 GPR:$R, imm:$lane))]> {
4487 let Inst{21} = lane{1};
4488 let Inst{6} = lane{0};
4490 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4491 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4492 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4493 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4494 GPR:$R, imm:$lane))]> {
4495 let Inst{21} = lane{0};
4498 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4499 (v16i8 (INSERT_SUBREG QPR:$src1,
4500 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4501 (DSubReg_i8_reg imm:$lane))),
4502 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4503 (DSubReg_i8_reg imm:$lane)))>;
4504 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4505 (v8i16 (INSERT_SUBREG QPR:$src1,
4506 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4507 (DSubReg_i16_reg imm:$lane))),
4508 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4509 (DSubReg_i16_reg imm:$lane)))>;
4510 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4511 (v4i32 (INSERT_SUBREG QPR:$src1,
4512 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4513 (DSubReg_i32_reg imm:$lane))),
4514 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4515 (DSubReg_i32_reg imm:$lane)))>;
4517 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4518 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4519 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4520 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4521 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4522 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4524 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4525 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4526 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4527 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4529 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4530 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4531 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4532 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4533 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4534 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4536 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4537 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4538 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4539 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4540 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4541 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4543 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4544 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4545 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4547 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4548 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4549 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4551 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4552 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4553 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4556 // VDUP : Vector Duplicate (from ARM core register to all elements)
4558 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4559 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4560 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4561 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4562 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4563 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4564 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4565 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4567 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4568 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4569 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4570 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4571 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4572 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4574 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4575 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4577 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4579 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4580 ValueType Ty, Operand IdxTy>
4581 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4582 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4583 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4585 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4586 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4587 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4588 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4589 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4590 VectorIndex32:$lane)))]>;
4592 // Inst{19-16} is partially specified depending on the element size.
4594 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4596 let Inst{19-17} = lane{2-0};
4598 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4600 let Inst{19-18} = lane{1-0};
4602 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4604 let Inst{19} = lane{0};
4606 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4608 let Inst{19-17} = lane{2-0};
4610 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4612 let Inst{19-18} = lane{1-0};
4614 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4616 let Inst{19} = lane{0};
4619 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4620 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4622 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4623 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4625 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4626 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4627 (DSubReg_i8_reg imm:$lane))),
4628 (SubReg_i8_lane imm:$lane)))>;
4629 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4630 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4631 (DSubReg_i16_reg imm:$lane))),
4632 (SubReg_i16_lane imm:$lane)))>;
4633 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4634 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4635 (DSubReg_i32_reg imm:$lane))),
4636 (SubReg_i32_lane imm:$lane)))>;
4637 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4638 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4639 (DSubReg_i32_reg imm:$lane))),
4640 (SubReg_i32_lane imm:$lane)))>;
4642 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4643 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4644 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4645 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4647 // VMOVN : Vector Narrowing Move
4648 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4649 "vmovn", "i", trunc>;
4650 // VQMOVN : Vector Saturating Narrowing Move
4651 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4652 "vqmovn", "s", int_arm_neon_vqmovns>;
4653 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4654 "vqmovn", "u", int_arm_neon_vqmovnu>;
4655 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4656 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4657 // VMOVL : Vector Lengthening Move
4658 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4659 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4661 // Vector Conversions.
4663 // VCVT : Vector Convert Between Floating-Point and Integers
4664 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4665 v2i32, v2f32, fp_to_sint>;
4666 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4667 v2i32, v2f32, fp_to_uint>;
4668 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4669 v2f32, v2i32, sint_to_fp>;
4670 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4671 v2f32, v2i32, uint_to_fp>;
4673 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4674 v4i32, v4f32, fp_to_sint>;
4675 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4676 v4i32, v4f32, fp_to_uint>;
4677 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4678 v4f32, v4i32, sint_to_fp>;
4679 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4680 v4f32, v4i32, uint_to_fp>;
4682 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4683 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4684 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4685 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4686 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4687 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4688 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4689 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4690 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4692 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4693 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4694 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4695 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4696 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4697 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4698 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4699 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4701 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4702 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4703 IIC_VUNAQ, "vcvt", "f16.f32",
4704 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4705 Requires<[HasNEON, HasFP16]>;
4706 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4707 IIC_VUNAQ, "vcvt", "f32.f16",
4708 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4709 Requires<[HasNEON, HasFP16]>;
4713 // VREV64 : Vector Reverse elements within 64-bit doublewords
4715 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4716 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4717 (ins DPR:$Vm), IIC_VMOVD,
4718 OpcodeStr, Dt, "$Vd, $Vm", "",
4719 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4720 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4721 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4722 (ins QPR:$Vm), IIC_VMOVQ,
4723 OpcodeStr, Dt, "$Vd, $Vm", "",
4724 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4726 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4727 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4728 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4729 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4731 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4732 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4733 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4734 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4736 // VREV32 : Vector Reverse elements within 32-bit words
4738 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4739 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4740 (ins DPR:$Vm), IIC_VMOVD,
4741 OpcodeStr, Dt, "$Vd, $Vm", "",
4742 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4743 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4744 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4745 (ins QPR:$Vm), IIC_VMOVQ,
4746 OpcodeStr, Dt, "$Vd, $Vm", "",
4747 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4749 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4750 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4752 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4753 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4755 // VREV16 : Vector Reverse elements within 16-bit halfwords
4757 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4758 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4759 (ins DPR:$Vm), IIC_VMOVD,
4760 OpcodeStr, Dt, "$Vd, $Vm", "",
4761 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4762 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4763 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4764 (ins QPR:$Vm), IIC_VMOVQ,
4765 OpcodeStr, Dt, "$Vd, $Vm", "",
4766 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4768 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4769 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4771 // Other Vector Shuffles.
4773 // Aligned extractions: really just dropping registers
4775 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4776 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4777 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4779 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4781 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4783 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4785 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4787 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4790 // VEXT : Vector Extract
4792 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4793 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4794 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4795 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4796 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4797 (Ty DPR:$Vm), imm:$index)))]> {
4799 let Inst{11-8} = index{3-0};
4802 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4803 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4804 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4805 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4806 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4807 (Ty QPR:$Vm), imm:$index)))]> {
4809 let Inst{11-8} = index{3-0};
4812 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4813 let Inst{11-8} = index{3-0};
4815 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4816 let Inst{11-9} = index{2-0};
4819 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4820 let Inst{11-10} = index{1-0};
4821 let Inst{9-8} = 0b00;
4823 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4826 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4828 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4829 let Inst{11-8} = index{3-0};
4831 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4832 let Inst{11-9} = index{2-0};
4835 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4836 let Inst{11-10} = index{1-0};
4837 let Inst{9-8} = 0b00;
4839 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4842 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4844 // VTRN : Vector Transpose
4846 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4847 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4848 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4850 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4851 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4852 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4854 // VUZP : Vector Unzip (Deinterleave)
4856 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4857 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4858 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4860 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4861 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4862 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4864 // VZIP : Vector Zip (Interleave)
4866 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4867 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4868 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4870 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4871 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4872 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4874 // Vector Table Lookup and Table Extension.
4876 // VTBL : Vector Table Lookup
4877 let DecoderMethod = "DecodeTBLInstruction" in {
4879 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4880 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4881 "vtbl", "8", "$Vd, $Vn, $Vm", "",
4882 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
4883 let hasExtraSrcRegAllocReq = 1 in {
4885 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4886 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4887 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4889 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4890 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4891 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4893 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4894 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4896 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4897 } // hasExtraSrcRegAllocReq = 1
4900 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4902 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4904 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4906 // VTBX : Vector Table Extension
4908 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4909 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4910 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
4911 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4912 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
4913 let hasExtraSrcRegAllocReq = 1 in {
4915 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4916 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4917 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4919 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4920 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4921 NVTBLFrm, IIC_VTBX3,
4922 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4925 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4926 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4927 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4929 } // hasExtraSrcRegAllocReq = 1
4932 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4933 IIC_VTBX2, "$orig = $dst", []>;
4935 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4936 IIC_VTBX3, "$orig = $dst", []>;
4938 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4939 IIC_VTBX4, "$orig = $dst", []>;
4940 } // DecoderMethod = "DecodeTBLInstruction"
4942 //===----------------------------------------------------------------------===//
4943 // NEON instructions for single-precision FP math
4944 //===----------------------------------------------------------------------===//
4946 class N2VSPat<SDNode OpNode, NeonI Inst>
4947 : NEONFPPat<(f32 (OpNode SPR:$a)),
4949 (v2f32 (COPY_TO_REGCLASS (Inst
4951 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4952 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4954 class N3VSPat<SDNode OpNode, NeonI Inst>
4955 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4957 (v2f32 (COPY_TO_REGCLASS (Inst
4959 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4962 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4963 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4965 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4966 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4968 (v2f32 (COPY_TO_REGCLASS (Inst
4970 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4973 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4976 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4977 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4979 def : N3VSPat<fadd, VADDfd>;
4980 def : N3VSPat<fsub, VSUBfd>;
4981 def : N3VSPat<fmul, VMULfd>;
4982 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4983 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4984 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4985 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4986 def : N2VSPat<fabs, VABSfd>;
4987 def : N2VSPat<fneg, VNEGfd>;
4988 def : N3VSPat<NEONfmax, VMAXfd>;
4989 def : N3VSPat<NEONfmin, VMINfd>;
4990 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4991 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4992 def : N2VSPat<arm_sitof, VCVTs2fd>;
4993 def : N2VSPat<arm_uitof, VCVTu2fd>;
4995 //===----------------------------------------------------------------------===//
4996 // Non-Instruction Patterns
4997 //===----------------------------------------------------------------------===//
5000 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5001 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5002 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5003 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5004 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5005 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5006 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5007 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5008 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5009 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5010 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5011 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5012 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5013 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5014 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5015 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5016 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5017 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5018 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5019 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5020 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5021 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5022 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5023 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5024 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5025 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5026 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5027 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5028 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5029 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5031 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5032 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5033 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5034 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5035 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5036 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5037 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5038 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5039 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5040 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5041 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5042 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5043 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5044 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5045 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5046 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5047 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5048 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5049 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5050 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5051 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5052 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5053 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5054 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5055 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5056 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5057 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5058 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5059 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5060 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;