1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 //===----------------------------------------------------------------------===//
99 // NEON operand definitions
100 //===----------------------------------------------------------------------===//
102 // addrmode_neonldstm := reg
104 /* TODO: Take advantage of vldm.
105 def addrmode_neonldstm : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
107 let PrintMethod = "printAddrNeonLdStMOperand";
108 let MIOperandInfo = (ops GPR, i32imm);
112 //===----------------------------------------------------------------------===//
113 // NEON load / store instructions
114 //===----------------------------------------------------------------------===//
116 /* TODO: Take advantage of vldm.
118 def VLDMD : NI<(outs),
119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
121 "vldm${addr:submode} ${addr:base}, $dst1",
123 let Inst{27-25} = 0b110;
125 let Inst{11-9} = 0b101;
128 def VLDMS : NI<(outs),
129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
131 "vldm${addr:submode} ${addr:base}, $dst1",
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
140 // Use vldmia to load a Q register as a D register pair.
141 def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
143 "vldmia $addr, ${dst:dregpair}",
144 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
145 let Inst{27-25} = 0b110;
146 let Inst{24} = 0; // P bit
147 let Inst{23} = 1; // U bit
149 let Inst{11-9} = 0b101;
152 // Use vstmia to store a Q register as a D register pair.
153 def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
155 "vstmia $addr, ${src:dregpair}",
156 [(store (v2f64 QPR:$src), GPR:$addr)]> {
157 let Inst{27-25} = 0b110;
158 let Inst{24} = 0; // P bit
159 let Inst{23} = 1; // U bit
161 let Inst{11-9} = 0b101;
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
167 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
169 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
170 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
171 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
172 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
174 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
175 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
177 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
178 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
179 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
180 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
181 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
183 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
184 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
185 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
186 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
187 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
189 // VLD2 : Vector Load (multiple 2-element structures)
190 class VLD2D<string OpcodeStr>
191 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
193 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
195 def VLD2d8 : VLD2D<"vld2.8">;
196 def VLD2d16 : VLD2D<"vld2.16">;
197 def VLD2d32 : VLD2D<"vld2.32">;
199 // VLD3 : Vector Load (multiple 3-element structures)
200 class VLD3D<string OpcodeStr>
201 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
203 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
205 def VLD3d8 : VLD3D<"vld3.8">;
206 def VLD3d16 : VLD3D<"vld3.16">;
207 def VLD3d32 : VLD3D<"vld3.32">;
209 // VLD4 : Vector Load (multiple 4-element structures)
210 class VLD4D<string OpcodeStr>
211 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
212 (ins addrmode6:$addr),
214 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
216 def VLD4d8 : VLD4D<"vld4.8">;
217 def VLD4d16 : VLD4D<"vld4.16">;
218 def VLD4d32 : VLD4D<"vld4.32">;
220 // VST1 : Vector Store (multiple single elements)
221 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
222 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
224 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
225 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
226 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
227 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
229 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
230 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
232 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
233 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
234 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
235 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
236 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
238 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
239 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
240 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
241 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
242 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
244 // VST2 : Vector Store (multiple 2-element structures)
245 class VST2D<string OpcodeStr>
246 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
247 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
249 def VST2d8 : VST2D<"vst2.8">;
250 def VST2d16 : VST2D<"vst2.16">;
251 def VST2d32 : VST2D<"vst2.32">;
253 // VST3 : Vector Store (multiple 3-element structures)
254 class VST3D<string OpcodeStr>
255 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
257 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
259 def VST3d8 : VST3D<"vst3.8">;
260 def VST3d16 : VST3D<"vst3.16">;
261 def VST3d32 : VST3D<"vst3.32">;
263 // VST4 : Vector Store (multiple 4-element structures)
264 class VST4D<string OpcodeStr>
265 : NLdSt<(outs), (ins addrmode6:$addr,
266 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
267 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
269 def VST4d8 : VST4D<"vst4.8">;
270 def VST4d16 : VST4D<"vst4.16">;
271 def VST4d32 : VST4D<"vst4.32">;
274 //===----------------------------------------------------------------------===//
275 // NEON pattern fragments
276 //===----------------------------------------------------------------------===//
278 // Extract D sub-registers of Q registers.
279 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
280 def SubReg_i8_reg : SDNodeXForm<imm, [{
281 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
283 def SubReg_i16_reg : SDNodeXForm<imm, [{
284 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
286 def SubReg_i32_reg : SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
289 def SubReg_f64_reg : SDNodeXForm<imm, [{
290 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
293 // Translate lane numbers from Q registers to D subregs.
294 def SubReg_i8_lane : SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
297 def SubReg_i16_lane : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
300 def SubReg_i32_lane : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
304 //===----------------------------------------------------------------------===//
305 // Instruction Classes
306 //===----------------------------------------------------------------------===//
308 // Basic 2-register operations, both double- and quad-register.
309 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
310 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
311 ValueType ResTy, ValueType OpTy, SDNode OpNode>
312 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
313 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
314 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
315 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
316 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
317 ValueType ResTy, ValueType OpTy, SDNode OpNode>
318 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
319 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
320 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
322 // Basic 2-register intrinsics, both double- and quad-register.
323 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
324 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
325 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
326 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
327 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
328 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
329 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
330 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
331 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
332 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
333 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
334 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
336 // Basic 2-register operations, scalar single-precision
337 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
338 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
339 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
340 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
341 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
342 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
344 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
345 : NEONFPPat<(f32 (OpNode SPR:$a)),
347 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
350 // Narrow 2-register intrinsics.
351 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
352 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
353 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
354 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
355 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
356 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
358 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
359 // derived from N2VImm instead of N2V because of the way the size is encoded.)
360 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
361 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
363 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
364 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
365 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
367 // Basic 3-register operations, both double- and quad-register.
368 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
369 string OpcodeStr, ValueType ResTy, ValueType OpTy,
370 SDNode OpNode, bit Commutable>
371 : N3V<op24, op23, op21_20, op11_8, 0, op4,
372 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
373 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
374 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
375 let isCommutable = Commutable;
377 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
378 string OpcodeStr, ValueType ResTy, ValueType OpTy,
379 SDNode OpNode, bit Commutable>
380 : N3V<op24, op23, op21_20, op11_8, 1, op4,
381 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
382 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
383 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
384 let isCommutable = Commutable;
387 // Basic 3-register operations, scalar single-precision
388 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
389 string OpcodeStr, ValueType ResTy, ValueType OpTy,
390 SDNode OpNode, bit Commutable>
391 : N3V<op24, op23, op21_20, op11_8, 0, op4,
392 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
393 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
394 let isCommutable = Commutable;
396 class N3VDsPat<SDNode OpNode, NeonI Inst>
397 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
399 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
400 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
403 // Basic 3-register intrinsics, both double- and quad-register.
404 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
405 string OpcodeStr, ValueType ResTy, ValueType OpTy,
406 Intrinsic IntOp, bit Commutable>
407 : N3V<op24, op23, op21_20, op11_8, 0, op4,
408 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
409 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
410 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
411 let isCommutable = Commutable;
413 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
414 string OpcodeStr, ValueType ResTy, ValueType OpTy,
415 Intrinsic IntOp, bit Commutable>
416 : N3V<op24, op23, op21_20, op11_8, 1, op4,
417 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
418 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
419 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
420 let isCommutable = Commutable;
423 // Multiply-Add/Sub operations, both double- and quad-register.
424 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
425 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
426 : N3V<op24, op23, op21_20, op11_8, 0, op4,
427 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
428 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
429 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
430 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
431 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
432 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
433 : N3V<op24, op23, op21_20, op11_8, 1, op4,
434 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
435 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
436 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
437 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
439 // Multiply-Add/Sub operations, scalar single-precision
440 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
441 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
442 : N3V<op24, op23, op21_20, op11_8, 0, op4,
443 (outs DPR_VFP2:$dst),
444 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
445 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
447 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
448 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
450 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
451 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
452 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
455 // Neon 3-argument intrinsics, both double- and quad-register.
456 // The destination register is also used as the first source operand register.
457 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
458 string OpcodeStr, ValueType ResTy, ValueType OpTy,
460 : N3V<op24, op23, op21_20, op11_8, 0, op4,
461 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
462 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
463 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
464 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
465 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
466 string OpcodeStr, ValueType ResTy, ValueType OpTy,
468 : N3V<op24, op23, op21_20, op11_8, 1, op4,
469 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
470 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
471 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
472 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
474 // Neon Long 3-argument intrinsic. The destination register is
475 // a quad-register and is also used as the first source operand register.
476 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
477 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
478 : N3V<op24, op23, op21_20, op11_8, 0, op4,
479 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
480 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
482 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
484 // Narrowing 3-register intrinsics.
485 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
486 string OpcodeStr, ValueType TyD, ValueType TyQ,
487 Intrinsic IntOp, bit Commutable>
488 : N3V<op24, op23, op21_20, op11_8, 0, op4,
489 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
490 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
491 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
492 let isCommutable = Commutable;
495 // Long 3-register intrinsics.
496 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
497 string OpcodeStr, ValueType TyQ, ValueType TyD,
498 Intrinsic IntOp, bit Commutable>
499 : N3V<op24, op23, op21_20, op11_8, 0, op4,
500 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
501 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
502 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
503 let isCommutable = Commutable;
506 // Wide 3-register intrinsics.
507 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
508 string OpcodeStr, ValueType TyQ, ValueType TyD,
509 Intrinsic IntOp, bit Commutable>
510 : N3V<op24, op23, op21_20, op11_8, 0, op4,
511 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
512 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
513 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
514 let isCommutable = Commutable;
517 // Pairwise long 2-register intrinsics, both double- and quad-register.
518 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
519 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
520 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
521 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
522 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
523 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
524 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
525 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
526 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
527 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
528 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
529 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
531 // Pairwise long 2-register accumulate intrinsics,
532 // both double- and quad-register.
533 // The destination register is also used as the first source operand register.
534 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
535 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
536 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
537 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
538 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
539 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
540 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
541 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
542 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
543 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
544 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
545 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
546 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
547 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
549 // Shift by immediate,
550 // both double- and quad-register.
551 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
552 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
553 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
554 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
555 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
556 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
557 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
558 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
559 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
560 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
561 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
562 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
564 // Long shift by immediate.
565 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
566 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
567 ValueType OpTy, SDNode OpNode>
568 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
569 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
570 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
571 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
572 (i32 imm:$SIMM))))]>;
574 // Narrow shift by immediate.
575 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
576 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
577 ValueType OpTy, SDNode OpNode>
578 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
579 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
580 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
581 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
582 (i32 imm:$SIMM))))]>;
584 // Shift right by immediate and accumulate,
585 // both double- and quad-register.
586 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
587 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
588 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
589 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
591 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
592 [(set DPR:$dst, (Ty (add DPR:$src1,
593 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
594 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
595 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
596 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
597 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
599 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
600 [(set QPR:$dst, (Ty (add QPR:$src1,
601 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
603 // Shift by immediate and insert,
604 // both double- and quad-register.
605 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
606 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
607 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
608 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
610 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
611 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
612 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
613 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
614 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
615 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
617 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
618 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
620 // Convert, with fractional bits immediate,
621 // both double- and quad-register.
622 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
623 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
625 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
626 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
627 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
628 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
629 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
630 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
632 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
633 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
634 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
635 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
637 //===----------------------------------------------------------------------===//
639 //===----------------------------------------------------------------------===//
641 // Neon 3-register vector operations.
643 // First with only element sizes of 8, 16 and 32 bits:
644 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
645 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
646 // 64-bit vector types.
647 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
648 v8i8, v8i8, OpNode, Commutable>;
649 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
650 v4i16, v4i16, OpNode, Commutable>;
651 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
652 v2i32, v2i32, OpNode, Commutable>;
654 // 128-bit vector types.
655 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
656 v16i8, v16i8, OpNode, Commutable>;
657 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
658 v8i16, v8i16, OpNode, Commutable>;
659 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
660 v4i32, v4i32, OpNode, Commutable>;
663 // ....then also with element size 64 bits:
664 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
665 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
666 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
667 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
668 v1i64, v1i64, OpNode, Commutable>;
669 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
670 v2i64, v2i64, OpNode, Commutable>;
674 // Neon Narrowing 2-register vector intrinsics,
675 // source operand element sizes of 16, 32 and 64 bits:
676 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
677 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
679 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
680 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
681 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
682 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
683 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
684 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
688 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
689 // source operand element sizes of 16, 32 and 64 bits:
690 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
691 bit op4, string OpcodeStr, Intrinsic IntOp> {
692 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
693 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
694 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
695 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
696 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
697 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
701 // Neon 3-register vector intrinsics.
703 // First with only element sizes of 16 and 32 bits:
704 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
705 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
706 // 64-bit vector types.
707 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
708 v4i16, v4i16, IntOp, Commutable>;
709 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
710 v2i32, v2i32, IntOp, Commutable>;
712 // 128-bit vector types.
713 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
714 v8i16, v8i16, IntOp, Commutable>;
715 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
716 v4i32, v4i32, IntOp, Commutable>;
719 // ....then also with element size of 8 bits:
720 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
721 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
722 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
723 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
724 v8i8, v8i8, IntOp, Commutable>;
725 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
726 v16i8, v16i8, IntOp, Commutable>;
729 // ....then also with element size of 64 bits:
730 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
731 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
732 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
733 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
734 v1i64, v1i64, IntOp, Commutable>;
735 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
736 v2i64, v2i64, IntOp, Commutable>;
740 // Neon Narrowing 3-register vector intrinsics,
741 // source operand element sizes of 16, 32 and 64 bits:
742 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
743 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
744 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
745 v8i8, v8i16, IntOp, Commutable>;
746 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
747 v4i16, v4i32, IntOp, Commutable>;
748 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
749 v2i32, v2i64, IntOp, Commutable>;
753 // Neon Long 3-register vector intrinsics.
755 // First with only element sizes of 16 and 32 bits:
756 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
757 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
758 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
759 v4i32, v4i16, IntOp, Commutable>;
760 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
761 v2i64, v2i32, IntOp, Commutable>;
764 // ....then also with element size of 8 bits:
765 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
766 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
767 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
768 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
769 v8i16, v8i8, IntOp, Commutable>;
773 // Neon Wide 3-register vector intrinsics,
774 // source operand element sizes of 8, 16 and 32 bits:
775 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
776 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
777 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
778 v8i16, v8i8, IntOp, Commutable>;
779 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
780 v4i32, v4i16, IntOp, Commutable>;
781 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
782 v2i64, v2i32, IntOp, Commutable>;
786 // Neon Multiply-Op vector operations,
787 // element sizes of 8, 16 and 32 bits:
788 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
789 string OpcodeStr, SDNode OpNode> {
790 // 64-bit vector types.
791 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
792 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
793 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
794 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
795 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
796 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
798 // 128-bit vector types.
799 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
800 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
801 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
802 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
803 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
804 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
808 // Neon 3-argument intrinsics,
809 // element sizes of 8, 16 and 32 bits:
810 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
811 string OpcodeStr, Intrinsic IntOp> {
812 // 64-bit vector types.
813 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
814 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
815 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
816 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
817 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
818 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
820 // 128-bit vector types.
821 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
822 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
823 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
824 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
825 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
826 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
830 // Neon Long 3-argument intrinsics.
832 // First with only element sizes of 16 and 32 bits:
833 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
834 string OpcodeStr, Intrinsic IntOp> {
835 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
836 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
837 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
838 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
841 // ....then also with element size of 8 bits:
842 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
843 string OpcodeStr, Intrinsic IntOp>
844 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
845 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
846 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
850 // Neon 2-register vector intrinsics,
851 // element sizes of 8, 16 and 32 bits:
852 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
853 bits<5> op11_7, bit op4, string OpcodeStr,
855 // 64-bit vector types.
856 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
857 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
858 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
859 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
860 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
861 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
863 // 128-bit vector types.
864 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
865 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
866 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
867 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
868 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
869 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
873 // Neon Pairwise long 2-register intrinsics,
874 // element sizes of 8, 16 and 32 bits:
875 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
876 bits<5> op11_7, bit op4,
877 string OpcodeStr, Intrinsic IntOp> {
878 // 64-bit vector types.
879 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
880 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
881 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
882 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
883 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
884 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
886 // 128-bit vector types.
887 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
888 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
889 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
890 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
891 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
892 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
896 // Neon Pairwise long 2-register accumulate intrinsics,
897 // element sizes of 8, 16 and 32 bits:
898 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
899 bits<5> op11_7, bit op4,
900 string OpcodeStr, Intrinsic IntOp> {
901 // 64-bit vector types.
902 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
903 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
904 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
905 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
906 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
907 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
909 // 128-bit vector types.
910 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
911 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
912 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
913 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
914 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
915 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
919 // Neon 2-register vector shift by immediate,
920 // element sizes of 8, 16, 32 and 64 bits:
921 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
922 string OpcodeStr, SDNode OpNode> {
923 // 64-bit vector types.
924 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
925 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
926 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
927 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
928 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
929 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
930 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
931 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
933 // 128-bit vector types.
934 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
935 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
936 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
937 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
938 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
939 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
940 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
941 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
945 // Neon Shift-Accumulate vector operations,
946 // element sizes of 8, 16, 32 and 64 bits:
947 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
948 string OpcodeStr, SDNode ShOp> {
949 // 64-bit vector types.
950 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
951 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
952 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
953 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
954 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
955 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
956 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
957 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
959 // 128-bit vector types.
960 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
961 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
962 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
963 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
964 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
965 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
966 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
967 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
971 // Neon Shift-Insert vector operations,
972 // element sizes of 8, 16, 32 and 64 bits:
973 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
974 string OpcodeStr, SDNode ShOp> {
975 // 64-bit vector types.
976 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
977 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
978 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
979 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
980 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
981 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
982 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
983 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
985 // 128-bit vector types.
986 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
987 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
988 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
989 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
990 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
991 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
992 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
993 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
996 //===----------------------------------------------------------------------===//
997 // Instruction Definitions.
998 //===----------------------------------------------------------------------===//
1000 // Vector Add Operations.
1002 // VADD : Vector Add (integer and floating-point)
1003 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1004 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1005 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1006 // VADDL : Vector Add Long (Q = D + D)
1007 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1008 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1009 // VADDW : Vector Add Wide (Q = Q + D)
1010 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1011 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1012 // VHADD : Vector Halving Add
1013 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1014 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1015 // VRHADD : Vector Rounding Halving Add
1016 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1017 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1018 // VQADD : Vector Saturating Add
1019 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1020 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1021 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1022 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1023 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1024 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1026 // Vector Multiply Operations.
1028 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1029 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1030 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1031 int_arm_neon_vmulp, 1>;
1032 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1033 int_arm_neon_vmulp, 1>;
1034 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1035 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1036 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1037 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1038 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1039 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1040 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1041 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1042 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1043 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1044 int_arm_neon_vmullp, 1>;
1045 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1046 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1048 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1050 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1051 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1052 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1053 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1054 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1055 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1056 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1057 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1058 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1059 // VMLS : Vector Multiply Subtract (integer and floating-point)
1060 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1061 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1062 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1063 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1064 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1065 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1066 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1067 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1069 // Vector Subtract Operations.
1071 // VSUB : Vector Subtract (integer and floating-point)
1072 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1073 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1074 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1075 // VSUBL : Vector Subtract Long (Q = D - D)
1076 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1077 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1078 // VSUBW : Vector Subtract Wide (Q = Q - D)
1079 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1080 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1081 // VHSUB : Vector Halving Subtract
1082 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1083 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1084 // VQSUB : Vector Saturing Subtract
1085 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1086 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1087 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1088 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1089 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1090 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1092 // Vector Comparisons.
1094 // VCEQ : Vector Compare Equal
1095 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1096 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1097 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1098 // VCGE : Vector Compare Greater Than or Equal
1099 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1100 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1101 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1102 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1103 // VCGT : Vector Compare Greater Than
1104 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1105 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1106 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1107 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1108 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1109 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1110 int_arm_neon_vacged, 0>;
1111 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1112 int_arm_neon_vacgeq, 0>;
1113 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1114 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1115 int_arm_neon_vacgtd, 0>;
1116 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1117 int_arm_neon_vacgtq, 0>;
1118 // VTST : Vector Test Bits
1119 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1121 // Vector Bitwise Operations.
1123 // VAND : Vector Bitwise AND
1124 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1125 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1127 // VEOR : Vector Bitwise Exclusive OR
1128 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1129 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1131 // VORR : Vector Bitwise OR
1132 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1133 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1135 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1136 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1137 (ins DPR:$src1, DPR:$src2), NoItinerary,
1138 "vbic\t$dst, $src1, $src2", "",
1139 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1140 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1141 (ins QPR:$src1, QPR:$src2), NoItinerary,
1142 "vbic\t$dst, $src1, $src2", "",
1143 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1145 // VORN : Vector Bitwise OR NOT
1146 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1147 (ins DPR:$src1, DPR:$src2), NoItinerary,
1148 "vorn\t$dst, $src1, $src2", "",
1149 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1150 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1151 (ins QPR:$src1, QPR:$src2), NoItinerary,
1152 "vorn\t$dst, $src1, $src2", "",
1153 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1155 // VMVN : Vector Bitwise NOT
1156 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1157 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1158 "vmvn\t$dst, $src", "",
1159 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1160 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1161 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1162 "vmvn\t$dst, $src", "",
1163 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1164 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1165 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1167 // VBSL : Vector Bitwise Select
1168 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1169 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1170 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1172 (v2i32 (or (and DPR:$src2, DPR:$src1),
1173 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1174 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1175 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1176 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1178 (v4i32 (or (and QPR:$src2, QPR:$src1),
1179 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1181 // VBIF : Vector Bitwise Insert if False
1182 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1183 // VBIT : Vector Bitwise Insert if True
1184 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1185 // These are not yet implemented. The TwoAddress pass will not go looking
1186 // for equivalent operations with different register constraints; it just
1189 // Vector Absolute Differences.
1191 // VABD : Vector Absolute Difference
1192 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1193 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1194 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1195 int_arm_neon_vabdf, 0>;
1196 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1197 int_arm_neon_vabdf, 0>;
1199 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1200 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1201 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1203 // VABA : Vector Absolute Difference and Accumulate
1204 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1205 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1207 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1208 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1209 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1211 // Vector Maximum and Minimum.
1213 // VMAX : Vector Maximum
1214 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1215 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1216 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1217 int_arm_neon_vmaxf, 1>;
1218 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1219 int_arm_neon_vmaxf, 1>;
1221 // VMIN : Vector Minimum
1222 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1223 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1224 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1225 int_arm_neon_vminf, 1>;
1226 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1227 int_arm_neon_vminf, 1>;
1229 // Vector Pairwise Operations.
1231 // VPADD : Vector Pairwise Add
1232 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1233 int_arm_neon_vpaddi, 0>;
1234 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1235 int_arm_neon_vpaddi, 0>;
1236 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1237 int_arm_neon_vpaddi, 0>;
1238 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1239 int_arm_neon_vpaddf, 0>;
1241 // VPADDL : Vector Pairwise Add Long
1242 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1243 int_arm_neon_vpaddls>;
1244 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1245 int_arm_neon_vpaddlu>;
1247 // VPADAL : Vector Pairwise Add and Accumulate Long
1248 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1249 int_arm_neon_vpadals>;
1250 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1251 int_arm_neon_vpadalu>;
1253 // VPMAX : Vector Pairwise Maximum
1254 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1255 int_arm_neon_vpmaxs, 0>;
1256 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1257 int_arm_neon_vpmaxs, 0>;
1258 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1259 int_arm_neon_vpmaxs, 0>;
1260 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1261 int_arm_neon_vpmaxu, 0>;
1262 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1263 int_arm_neon_vpmaxu, 0>;
1264 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1265 int_arm_neon_vpmaxu, 0>;
1266 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1267 int_arm_neon_vpmaxf, 0>;
1269 // VPMIN : Vector Pairwise Minimum
1270 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1271 int_arm_neon_vpmins, 0>;
1272 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1273 int_arm_neon_vpmins, 0>;
1274 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1275 int_arm_neon_vpmins, 0>;
1276 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1277 int_arm_neon_vpminu, 0>;
1278 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1279 int_arm_neon_vpminu, 0>;
1280 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1281 int_arm_neon_vpminu, 0>;
1282 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1283 int_arm_neon_vpminf, 0>;
1285 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1287 // VRECPE : Vector Reciprocal Estimate
1288 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1289 v2i32, v2i32, int_arm_neon_vrecpe>;
1290 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1291 v4i32, v4i32, int_arm_neon_vrecpe>;
1292 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1293 v2f32, v2f32, int_arm_neon_vrecpef>;
1294 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1295 v4f32, v4f32, int_arm_neon_vrecpef>;
1297 // VRECPS : Vector Reciprocal Step
1298 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1299 int_arm_neon_vrecps, 1>;
1300 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1301 int_arm_neon_vrecps, 1>;
1303 // VRSQRTE : Vector Reciprocal Square Root Estimate
1304 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1305 v2i32, v2i32, int_arm_neon_vrsqrte>;
1306 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1307 v4i32, v4i32, int_arm_neon_vrsqrte>;
1308 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1309 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1310 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1311 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1313 // VRSQRTS : Vector Reciprocal Square Root Step
1314 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1315 int_arm_neon_vrsqrts, 1>;
1316 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1317 int_arm_neon_vrsqrts, 1>;
1321 // VSHL : Vector Shift
1322 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1323 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1324 // VSHL : Vector Shift Left (Immediate)
1325 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1326 // VSHR : Vector Shift Right (Immediate)
1327 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1328 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1330 // VSHLL : Vector Shift Left Long
1331 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1332 v8i16, v8i8, NEONvshlls>;
1333 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1334 v4i32, v4i16, NEONvshlls>;
1335 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1336 v2i64, v2i32, NEONvshlls>;
1337 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1338 v8i16, v8i8, NEONvshllu>;
1339 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1340 v4i32, v4i16, NEONvshllu>;
1341 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1342 v2i64, v2i32, NEONvshllu>;
1344 // VSHLL : Vector Shift Left Long (with maximum shift count)
1345 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1346 v8i16, v8i8, NEONvshlli>;
1347 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1348 v4i32, v4i16, NEONvshlli>;
1349 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1350 v2i64, v2i32, NEONvshlli>;
1352 // VSHRN : Vector Shift Right and Narrow
1353 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1354 v8i8, v8i16, NEONvshrn>;
1355 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1356 v4i16, v4i32, NEONvshrn>;
1357 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1358 v2i32, v2i64, NEONvshrn>;
1360 // VRSHL : Vector Rounding Shift
1361 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1362 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1363 // VRSHR : Vector Rounding Shift Right
1364 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1365 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1367 // VRSHRN : Vector Rounding Shift Right and Narrow
1368 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1369 v8i8, v8i16, NEONvrshrn>;
1370 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1371 v4i16, v4i32, NEONvrshrn>;
1372 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1373 v2i32, v2i64, NEONvrshrn>;
1375 // VQSHL : Vector Saturating Shift
1376 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1377 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1378 // VQSHL : Vector Saturating Shift Left (Immediate)
1379 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1380 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1381 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1382 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1384 // VQSHRN : Vector Saturating Shift Right and Narrow
1385 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1386 v8i8, v8i16, NEONvqshrns>;
1387 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1388 v4i16, v4i32, NEONvqshrns>;
1389 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1390 v2i32, v2i64, NEONvqshrns>;
1391 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1392 v8i8, v8i16, NEONvqshrnu>;
1393 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1394 v4i16, v4i32, NEONvqshrnu>;
1395 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1396 v2i32, v2i64, NEONvqshrnu>;
1398 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1399 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1400 v8i8, v8i16, NEONvqshrnsu>;
1401 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1402 v4i16, v4i32, NEONvqshrnsu>;
1403 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1404 v2i32, v2i64, NEONvqshrnsu>;
1406 // VQRSHL : Vector Saturating Rounding Shift
1407 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1408 int_arm_neon_vqrshifts, 0>;
1409 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1410 int_arm_neon_vqrshiftu, 0>;
1412 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1413 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1414 v8i8, v8i16, NEONvqrshrns>;
1415 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1416 v4i16, v4i32, NEONvqrshrns>;
1417 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1418 v2i32, v2i64, NEONvqrshrns>;
1419 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1420 v8i8, v8i16, NEONvqrshrnu>;
1421 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1422 v4i16, v4i32, NEONvqrshrnu>;
1423 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1424 v2i32, v2i64, NEONvqrshrnu>;
1426 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1427 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1428 v8i8, v8i16, NEONvqrshrnsu>;
1429 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1430 v4i16, v4i32, NEONvqrshrnsu>;
1431 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1432 v2i32, v2i64, NEONvqrshrnsu>;
1434 // VSRA : Vector Shift Right and Accumulate
1435 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1436 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1437 // VRSRA : Vector Rounding Shift Right and Accumulate
1438 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1439 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1441 // VSLI : Vector Shift Left and Insert
1442 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1443 // VSRI : Vector Shift Right and Insert
1444 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1446 // Vector Absolute and Saturating Absolute.
1448 // VABS : Vector Absolute Value
1449 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1451 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1452 v2f32, v2f32, int_arm_neon_vabsf>;
1453 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1454 v4f32, v4f32, int_arm_neon_vabsf>;
1456 // VQABS : Vector Saturating Absolute Value
1457 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1458 int_arm_neon_vqabs>;
1462 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1463 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1465 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1466 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1468 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1469 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1470 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1471 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1473 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1474 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1476 // VNEG : Vector Negate
1477 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1478 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1479 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1480 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1481 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1482 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1484 // VNEG : Vector Negate (floating-point)
1485 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1486 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1487 "vneg.f32\t$dst, $src", "",
1488 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1489 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1490 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1491 "vneg.f32\t$dst, $src", "",
1492 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1494 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1495 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1496 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1497 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1498 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1499 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1501 // VQNEG : Vector Saturating Negate
1502 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1503 int_arm_neon_vqneg>;
1505 // Vector Bit Counting Operations.
1507 // VCLS : Vector Count Leading Sign Bits
1508 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1510 // VCLZ : Vector Count Leading Zeros
1511 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1513 // VCNT : Vector Count One Bits
1514 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1515 v8i8, v8i8, int_arm_neon_vcnt>;
1516 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1517 v16i8, v16i8, int_arm_neon_vcnt>;
1519 // Vector Move Operations.
1521 // VMOV : Vector Move (Register)
1523 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1524 NoItinerary, "vmov\t$dst, $src", "", []>;
1525 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1526 NoItinerary, "vmov\t$dst, $src", "", []>;
1528 // VMOV : Vector Move (Immediate)
1530 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1531 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1532 return ARM::getVMOVImm(N, 1, *CurDAG);
1534 def vmovImm8 : PatLeaf<(build_vector), [{
1535 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1538 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1539 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1540 return ARM::getVMOVImm(N, 2, *CurDAG);
1542 def vmovImm16 : PatLeaf<(build_vector), [{
1543 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1544 }], VMOV_get_imm16>;
1546 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1547 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1548 return ARM::getVMOVImm(N, 4, *CurDAG);
1550 def vmovImm32 : PatLeaf<(build_vector), [{
1551 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1552 }], VMOV_get_imm32>;
1554 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1555 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1556 return ARM::getVMOVImm(N, 8, *CurDAG);
1558 def vmovImm64 : PatLeaf<(build_vector), [{
1559 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1560 }], VMOV_get_imm64>;
1562 // Note: Some of the cmode bits in the following VMOV instructions need to
1563 // be encoded based on the immed values.
1565 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1566 (ins i8imm:$SIMM), NoItinerary,
1567 "vmov.i8\t$dst, $SIMM", "",
1568 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1569 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1570 (ins i8imm:$SIMM), NoItinerary,
1571 "vmov.i8\t$dst, $SIMM", "",
1572 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1574 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1575 (ins i16imm:$SIMM), NoItinerary,
1576 "vmov.i16\t$dst, $SIMM", "",
1577 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1578 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1579 (ins i16imm:$SIMM), NoItinerary,
1580 "vmov.i16\t$dst, $SIMM", "",
1581 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1583 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1584 (ins i32imm:$SIMM), NoItinerary,
1585 "vmov.i32\t$dst, $SIMM", "",
1586 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1587 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1588 (ins i32imm:$SIMM), NoItinerary,
1589 "vmov.i32\t$dst, $SIMM", "",
1590 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1592 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1593 (ins i64imm:$SIMM), NoItinerary,
1594 "vmov.i64\t$dst, $SIMM", "",
1595 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1596 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1597 (ins i64imm:$SIMM), NoItinerary,
1598 "vmov.i64\t$dst, $SIMM", "",
1599 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1601 // VMOV : Vector Get Lane (move scalar to ARM core register)
1603 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1604 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1605 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1606 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1608 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1609 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1610 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1611 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1613 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1614 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1615 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1616 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1618 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1619 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1620 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1621 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1623 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1624 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1625 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1626 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1628 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1629 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1630 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1631 (SubReg_i8_reg imm:$lane))),
1632 (SubReg_i8_lane imm:$lane))>;
1633 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1634 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1635 (SubReg_i16_reg imm:$lane))),
1636 (SubReg_i16_lane imm:$lane))>;
1637 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1638 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1639 (SubReg_i8_reg imm:$lane))),
1640 (SubReg_i8_lane imm:$lane))>;
1641 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1642 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1643 (SubReg_i16_reg imm:$lane))),
1644 (SubReg_i16_lane imm:$lane))>;
1645 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1646 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1647 (SubReg_i32_reg imm:$lane))),
1648 (SubReg_i32_lane imm:$lane))>;
1649 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1650 // (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1651 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1652 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1655 // VMOV : Vector Set Lane (move ARM core register to scalar)
1657 let Constraints = "$src1 = $dst" in {
1658 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1659 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1660 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1661 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1662 GPR:$src2, imm:$lane))]>;
1663 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1664 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1665 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1666 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1667 GPR:$src2, imm:$lane))]>;
1668 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1669 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1670 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1671 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1672 GPR:$src2, imm:$lane))]>;
1674 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1675 (v16i8 (INSERT_SUBREG QPR:$src1,
1676 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1677 (SubReg_i8_reg imm:$lane))),
1678 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1679 (SubReg_i8_reg imm:$lane)))>;
1680 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1681 (v8i16 (INSERT_SUBREG QPR:$src1,
1682 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1683 (SubReg_i16_reg imm:$lane))),
1684 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1685 (SubReg_i16_reg imm:$lane)))>;
1686 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1687 (v4i32 (INSERT_SUBREG QPR:$src1,
1688 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1689 (SubReg_i32_reg imm:$lane))),
1690 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1691 (SubReg_i32_reg imm:$lane)))>;
1693 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1694 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1695 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1696 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1698 // VDUP : Vector Duplicate (from ARM core register to all elements)
1700 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1701 (vector_shuffle node:$lhs, node:$rhs), [{
1702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1703 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1706 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1707 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1708 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1709 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1710 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1711 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1712 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1713 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1715 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1716 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1717 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1718 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1719 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1720 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1722 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1723 NoItinerary, "vdup", ".32\t$dst, $src",
1724 [(set DPR:$dst, (v2f32 (splat_lo
1726 (f32 (bitconvert GPR:$src))),
1728 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1729 NoItinerary, "vdup", ".32\t$dst, $src",
1730 [(set QPR:$dst, (v4f32 (splat_lo
1732 (f32 (bitconvert GPR:$src))),
1735 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1737 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1739 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1742 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1743 (vector_shuffle node:$lhs, node:$rhs), [{
1744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1745 return SVOp->isSplat();
1746 }], SHUFFLE_get_splat_lane>;
1748 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1749 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1750 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1751 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1752 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1754 // vector_shuffle requires that the source and destination types match, so
1755 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1756 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1757 ValueType ResTy, ValueType OpTy>
1758 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1759 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1760 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1761 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1763 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1764 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1765 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1766 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1767 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1768 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1769 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1770 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1772 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1773 (outs DPR:$dst), (ins SPR:$src),
1774 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1775 [(set DPR:$dst, (v2f32 (splat_lo
1776 (scalar_to_vector SPR:$src),
1779 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1780 (outs QPR:$dst), (ins SPR:$src),
1781 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1782 [(set QPR:$dst, (v4f32 (splat_lo
1783 (scalar_to_vector SPR:$src),
1786 // VMOVN : Vector Narrowing Move
1787 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1788 int_arm_neon_vmovn>;
1789 // VQMOVN : Vector Saturating Narrowing Move
1790 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1791 int_arm_neon_vqmovns>;
1792 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1793 int_arm_neon_vqmovnu>;
1794 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1795 int_arm_neon_vqmovnsu>;
1796 // VMOVL : Vector Lengthening Move
1797 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1798 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1800 // Vector Conversions.
1802 // VCVT : Vector Convert Between Floating-Point and Integers
1803 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1804 v2i32, v2f32, fp_to_sint>;
1805 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1806 v2i32, v2f32, fp_to_uint>;
1807 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1808 v2f32, v2i32, sint_to_fp>;
1809 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1810 v2f32, v2i32, uint_to_fp>;
1812 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1813 v4i32, v4f32, fp_to_sint>;
1814 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1815 v4i32, v4f32, fp_to_uint>;
1816 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1817 v4f32, v4i32, sint_to_fp>;
1818 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1819 v4f32, v4i32, uint_to_fp>;
1821 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1822 // Note: Some of the opcode bits in the following VCVT instructions need to
1823 // be encoded based on the immed values.
1824 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1825 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1826 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1827 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1828 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1829 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1830 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1831 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1833 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1834 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1835 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1836 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1837 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1838 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1839 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1840 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1842 // VREV : Vector Reverse
1844 def vrev64_shuffle : PatFrag<(ops node:$in),
1845 (vector_shuffle node:$in, undef), [{
1846 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1847 return ARM::isVREVMask(SVOp, 64);
1850 def vrev32_shuffle : PatFrag<(ops node:$in),
1851 (vector_shuffle node:$in, undef), [{
1852 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1853 return ARM::isVREVMask(SVOp, 32);
1856 def vrev16_shuffle : PatFrag<(ops node:$in),
1857 (vector_shuffle node:$in, undef), [{
1858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1859 return ARM::isVREVMask(SVOp, 16);
1862 // VREV64 : Vector Reverse elements within 64-bit doublewords
1864 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1865 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1866 (ins DPR:$src), NoItinerary,
1867 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1868 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1869 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1870 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1871 (ins QPR:$src), NoItinerary,
1872 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1873 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1875 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1876 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1877 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1878 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1880 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1881 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1882 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1883 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1885 // VREV32 : Vector Reverse elements within 32-bit words
1887 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1888 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1889 (ins DPR:$src), NoItinerary,
1890 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1891 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1892 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1893 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1894 (ins QPR:$src), NoItinerary,
1895 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1896 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1898 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1899 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1901 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1902 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1904 // VREV16 : Vector Reverse elements within 16-bit halfwords
1906 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1907 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1908 (ins DPR:$src), NoItinerary,
1909 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1910 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1911 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1912 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1913 (ins QPR:$src), NoItinerary,
1914 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1915 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1917 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1918 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1920 //===----------------------------------------------------------------------===//
1921 // NEON instructions for single-precision FP math
1922 //===----------------------------------------------------------------------===//
1924 // These need separate instructions because they must use DPR_VFP2 register
1925 // class which have SPR sub-registers.
1927 // Vector Add Operations used for single-precision FP
1928 let neverHasSideEffects = 1 in
1929 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
1930 def : N3VDsPat<fadd, VADDfd_sfp>;
1932 // Vector Multiply Operations used for single-precision FP
1933 let neverHasSideEffects = 1 in
1934 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
1935 def : N3VDsPat<fmul, VMULfd_sfp>;
1937 // Vector Multiply-Accumulate/Subtract used for single-precision FP
1938 let neverHasSideEffects = 1 in
1939 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
1940 def : N3VDMulOpsPat<fmul, fadd, VMLAfd>;
1942 let neverHasSideEffects = 1 in
1943 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
1944 def : N3VDMulOpsPat<fmul, fsub, VMLSfd>;
1946 // Vector Sub Operations used for single-precision FP
1947 let neverHasSideEffects = 1 in
1948 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
1949 def : N3VDsPat<fsub, VSUBfd_sfp>;
1951 // Vector Absolute for single-precision FP
1952 let neverHasSideEffects = 1 in
1953 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1954 v2f32, v2f32, int_arm_neon_vabsf>;
1955 def : N2VDIntsPat<fabs, VABSfd_sfp>;
1957 // Vector Negate for single-precision FP
1959 let neverHasSideEffects = 1 in
1960 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1961 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
1962 "vneg.f32\t$dst, $src", "", []>;
1963 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
1965 //===----------------------------------------------------------------------===//
1966 // Non-Instruction Patterns
1967 //===----------------------------------------------------------------------===//
1970 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1971 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1972 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1973 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1974 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1975 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1976 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1977 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1978 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1979 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1980 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1981 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1982 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1983 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1984 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1985 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1986 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1987 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1988 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1989 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1990 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1991 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1992 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1993 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1994 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1995 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1996 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1997 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1998 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1999 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2001 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2002 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2003 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2004 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2005 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2006 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2007 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2008 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2009 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2010 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2011 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2012 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2013 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2014 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2015 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2016 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2017 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2018 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2019 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2020 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2021 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2022 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2023 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2024 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2025 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2026 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2027 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2028 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2029 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2030 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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