1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
43 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
44 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
45 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
46 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
47 return ((uint64_t)Imm) < 8;
49 let ParserMatchClass = VectorIndex8Operand;
50 let PrintMethod = "printVectorIndex";
51 let MIOperandInfo = (ops i32imm);
53 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
54 return ((uint64_t)Imm) < 4;
56 let ParserMatchClass = VectorIndex16Operand;
57 let PrintMethod = "printVectorIndex";
58 let MIOperandInfo = (ops i32imm);
60 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 2;
63 let ParserMatchClass = VectorIndex32Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
68 //===----------------------------------------------------------------------===//
69 // NEON-specific DAG Nodes.
70 //===----------------------------------------------------------------------===//
72 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
73 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
75 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
76 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
77 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
78 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
79 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
80 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
81 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
82 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
83 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
84 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
85 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
87 // Types for vector shift by immediates. The "SHX" version is for long and
88 // narrow operations where the source and destination vectors have different
89 // types. The "SHINS" version is for shift and insert operations.
90 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
92 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
94 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
95 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
97 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
98 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
99 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
100 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
101 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
102 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
103 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
105 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
106 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
107 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
109 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
110 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
111 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
112 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
113 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
114 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
116 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
117 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
118 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
120 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
121 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
123 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
125 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
126 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
128 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
129 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
130 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
132 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
134 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
135 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
137 def NEONvbsl : SDNode<"ARMISD::VBSL",
138 SDTypeProfile<1, 3, [SDTCisVec<0>,
141 SDTCisSameAs<0, 3>]>>;
143 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
145 // VDUPLANE can produce a quad-register result from a double-register source,
146 // so the result is not constrained to match the source.
147 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
148 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
151 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
152 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
153 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
155 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
156 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
157 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
158 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
160 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
162 SDTCisSameAs<0, 3>]>;
163 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
164 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
165 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
167 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
168 SDTCisSameAs<1, 2>]>;
169 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
170 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
172 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
173 SDTCisSameAs<0, 2>]>;
174 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
175 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
177 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
178 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
179 unsigned EltBits = 0;
180 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
181 return (EltBits == 32 && EltVal == 0);
184 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
185 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
186 unsigned EltBits = 0;
187 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
188 return (EltBits == 8 && EltVal == 0xff);
191 //===----------------------------------------------------------------------===//
192 // NEON load / store instructions
193 //===----------------------------------------------------------------------===//
195 // Use VLDM to load a Q register as a D register pair.
196 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
198 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
200 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
202 // Use VSTM to store a Q register as a D register pair.
203 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
205 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
207 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
209 // Classes for VLD* pseudo-instructions with multi-register operands.
210 // These are expanded to real instructions after register allocation.
211 class VLDQPseudo<InstrItinClass itin>
212 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
213 class VLDQWBPseudo<InstrItinClass itin>
214 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
215 (ins addrmode6:$addr, am6offset:$offset), itin,
217 class VLDQQPseudo<InstrItinClass itin>
218 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
219 class VLDQQWBPseudo<InstrItinClass itin>
220 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
221 (ins addrmode6:$addr, am6offset:$offset), itin,
223 class VLDQQQQPseudo<InstrItinClass itin>
224 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
226 class VLDQQQQWBPseudo<InstrItinClass itin>
227 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
228 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
229 "$addr.addr = $wb, $src = $dst">;
231 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
233 // VLD1 : Vector Load (multiple single elements)
234 class VLD1D<bits<4> op7_4, string Dt>
235 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
236 (ins addrmode6:$Rn), IIC_VLD1,
237 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
240 let DecoderMethod = "DecodeVLDInstruction";
242 class VLD1Q<bits<4> op7_4, string Dt>
243 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
244 (ins addrmode6:$Rn), IIC_VLD1x2,
245 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
247 let Inst{5-4} = Rn{5-4};
248 let DecoderMethod = "DecodeVLDInstruction";
251 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
252 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
253 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
254 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
256 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
257 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
258 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
259 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
261 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
262 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
263 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
264 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
266 // ...with address register writeback:
267 class VLD1DWB<bits<4> op7_4, string Dt>
268 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
269 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
270 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
271 "$Rn.addr = $wb", []> {
273 let DecoderMethod = "DecodeVLDInstruction";
275 class VLD1QWB<bits<4> op7_4, string Dt>
276 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
277 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
278 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
279 "$Rn.addr = $wb", []> {
280 let Inst{5-4} = Rn{5-4};
281 let DecoderMethod = "DecodeVLDInstruction";
284 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
285 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
286 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
287 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
289 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
290 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
291 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
292 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
294 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
295 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
296 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
297 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
299 // ...with 3 registers (some of these are only for the disassembler):
300 class VLD1D3<bits<4> op7_4, string Dt>
301 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
302 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
303 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
306 let DecoderMethod = "DecodeVLDInstruction";
308 class VLD1D3WB<bits<4> op7_4, string Dt>
309 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
310 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
311 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
313 let DecoderMethod = "DecodeVLDInstruction";
316 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
317 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
318 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
319 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
321 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
322 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
323 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
324 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
326 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
327 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
329 // ...with 4 registers (some of these are only for the disassembler):
330 class VLD1D4<bits<4> op7_4, string Dt>
331 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
332 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
333 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
335 let Inst{5-4} = Rn{5-4};
336 let DecoderMethod = "DecodeVLDInstruction";
338 class VLD1D4WB<bits<4> op7_4, string Dt>
339 : NLdSt<0,0b10,0b0010,op7_4,
340 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
341 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
342 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
344 let Inst{5-4} = Rn{5-4};
345 let DecoderMethod = "DecodeVLDInstruction";
348 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
349 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
350 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
351 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
353 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
354 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
355 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
356 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
358 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
359 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
361 // VLD2 : Vector Load (multiple 2-element structures)
362 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
363 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
364 (ins addrmode6:$Rn), IIC_VLD2,
365 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
367 let Inst{5-4} = Rn{5-4};
368 let DecoderMethod = "DecodeVLDInstruction";
370 class VLD2Q<bits<4> op7_4, string Dt>
371 : NLdSt<0, 0b10, 0b0011, op7_4,
372 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
373 (ins addrmode6:$Rn), IIC_VLD2x2,
374 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
376 let Inst{5-4} = Rn{5-4};
377 let DecoderMethod = "DecodeVLDInstruction";
380 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
381 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
382 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
384 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
385 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
386 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
388 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
389 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
390 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
392 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
393 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
394 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
396 // ...with address register writeback:
397 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
398 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
399 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
400 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
401 "$Rn.addr = $wb", []> {
402 let Inst{5-4} = Rn{5-4};
403 let DecoderMethod = "DecodeVLDInstruction";
405 class VLD2QWB<bits<4> op7_4, string Dt>
406 : NLdSt<0, 0b10, 0b0011, op7_4,
407 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
408 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
409 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
410 "$Rn.addr = $wb", []> {
411 let Inst{5-4} = Rn{5-4};
412 let DecoderMethod = "DecodeVLDInstruction";
415 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
416 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
417 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
419 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
420 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
421 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
423 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
424 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
425 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
427 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
428 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
429 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
431 // ...with double-spaced registers (for disassembly only):
432 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
433 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
434 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
435 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
436 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
437 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
439 // VLD3 : Vector Load (multiple 3-element structures)
440 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
441 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
442 (ins addrmode6:$Rn), IIC_VLD3,
443 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
446 let DecoderMethod = "DecodeVLDInstruction";
449 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
450 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
451 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
453 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
454 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
455 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
457 // ...with address register writeback:
458 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
459 : NLdSt<0, 0b10, op11_8, op7_4,
460 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
461 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
462 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
463 "$Rn.addr = $wb", []> {
465 let DecoderMethod = "DecodeVLDInstruction";
468 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
469 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
470 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
472 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
473 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
474 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
476 // ...with double-spaced registers:
477 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
478 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
479 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
480 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
481 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
482 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
484 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
485 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
486 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
488 // ...alternate versions to be allocated odd register numbers:
489 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
490 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
491 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
493 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
494 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
495 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
497 // VLD4 : Vector Load (multiple 4-element structures)
498 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
499 : NLdSt<0, 0b10, op11_8, op7_4,
500 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
501 (ins addrmode6:$Rn), IIC_VLD4,
502 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
504 let Inst{5-4} = Rn{5-4};
505 let DecoderMethod = "DecodeVLDInstruction";
508 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
509 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
510 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
512 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
513 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
514 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
516 // ...with address register writeback:
517 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
518 : NLdSt<0, 0b10, op11_8, op7_4,
519 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
520 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
521 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
522 "$Rn.addr = $wb", []> {
523 let Inst{5-4} = Rn{5-4};
524 let DecoderMethod = "DecodeVLDInstruction";
527 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
528 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
529 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
531 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
532 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
533 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
535 // ...with double-spaced registers:
536 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
537 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
538 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
539 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
540 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
541 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
543 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
544 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
545 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
547 // ...alternate versions to be allocated odd register numbers:
548 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
549 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
550 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
552 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
553 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
554 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
556 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
558 // Classes for VLD*LN pseudo-instructions with multi-register operands.
559 // These are expanded to real instructions after register allocation.
560 class VLDQLNPseudo<InstrItinClass itin>
561 : PseudoNLdSt<(outs QPR:$dst),
562 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
563 itin, "$src = $dst">;
564 class VLDQLNWBPseudo<InstrItinClass itin>
565 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
566 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
567 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
568 class VLDQQLNPseudo<InstrItinClass itin>
569 : PseudoNLdSt<(outs QQPR:$dst),
570 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
571 itin, "$src = $dst">;
572 class VLDQQLNWBPseudo<InstrItinClass itin>
573 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
574 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
575 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
576 class VLDQQQQLNPseudo<InstrItinClass itin>
577 : PseudoNLdSt<(outs QQQQPR:$dst),
578 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
579 itin, "$src = $dst">;
580 class VLDQQQQLNWBPseudo<InstrItinClass itin>
581 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
583 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
585 // VLD1LN : Vector Load (single element to one lane)
586 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
588 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
589 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
590 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
592 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
593 (i32 (LoadOp addrmode6:$Rn)),
596 let DecoderMethod = "DecodeVLD1LN";
598 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
600 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
601 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
602 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
604 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
605 (i32 (LoadOp addrmode6oneL32:$Rn)),
608 let DecoderMethod = "DecodeVLD1LN";
610 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
611 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
612 (i32 (LoadOp addrmode6:$addr)),
616 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
617 let Inst{7-5} = lane{2-0};
619 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
620 let Inst{7-6} = lane{1-0};
623 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
624 let Inst{7} = lane{0};
629 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
630 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
631 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
633 def : Pat<(vector_insert (v2f32 DPR:$src),
634 (f32 (load addrmode6:$addr)), imm:$lane),
635 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
636 def : Pat<(vector_insert (v4f32 QPR:$src),
637 (f32 (load addrmode6:$addr)), imm:$lane),
638 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
640 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
642 // ...with address register writeback:
643 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
644 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
645 (ins addrmode6:$Rn, am6offset:$Rm,
646 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
647 "\\{$Vd[$lane]\\}, $Rn$Rm",
648 "$src = $Vd, $Rn.addr = $wb", []> {
649 let DecoderMethod = "DecodeVLD1LN";
652 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
653 let Inst{7-5} = lane{2-0};
655 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
656 let Inst{7-6} = lane{1-0};
659 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
660 let Inst{7} = lane{0};
665 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
666 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
667 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
669 // VLD2LN : Vector Load (single 2-element structure to one lane)
670 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
671 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
672 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
673 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
674 "$src1 = $Vd, $src2 = $dst2", []> {
677 let DecoderMethod = "DecodeVLD2LN";
680 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
681 let Inst{7-5} = lane{2-0};
683 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
684 let Inst{7-6} = lane{1-0};
686 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
687 let Inst{7} = lane{0};
690 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
691 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
692 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
694 // ...with double-spaced registers:
695 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
696 let Inst{7-6} = lane{1-0};
698 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
699 let Inst{7} = lane{0};
702 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
703 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
705 // ...with address register writeback:
706 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
707 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
708 (ins addrmode6:$Rn, am6offset:$Rm,
709 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
710 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
711 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
713 let DecoderMethod = "DecodeVLD2LN";
716 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
717 let Inst{7-5} = lane{2-0};
719 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
720 let Inst{7-6} = lane{1-0};
722 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
723 let Inst{7} = lane{0};
726 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
727 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
728 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
730 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
731 let Inst{7-6} = lane{1-0};
733 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
734 let Inst{7} = lane{0};
737 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
738 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
740 // VLD3LN : Vector Load (single 3-element structure to one lane)
741 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
742 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
743 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
744 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
745 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
746 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
748 let DecoderMethod = "DecodeVLD3LN";
751 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
752 let Inst{7-5} = lane{2-0};
754 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
755 let Inst{7-6} = lane{1-0};
757 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
758 let Inst{7} = lane{0};
761 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
762 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
763 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
765 // ...with double-spaced registers:
766 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
767 let Inst{7-6} = lane{1-0};
769 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
770 let Inst{7} = lane{0};
773 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
774 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
776 // ...with address register writeback:
777 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
778 : NLdStLn<1, 0b10, op11_8, op7_4,
779 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
780 (ins addrmode6:$Rn, am6offset:$Rm,
781 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
782 IIC_VLD3lnu, "vld3", Dt,
783 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
784 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
786 let DecoderMethod = "DecodeVLD3LN";
789 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
790 let Inst{7-5} = lane{2-0};
792 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
793 let Inst{7-6} = lane{1-0};
795 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
796 let Inst{7} = lane{0};
799 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
800 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
801 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
803 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
804 let Inst{7-6} = lane{1-0};
806 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
807 let Inst{7} = lane{0};
810 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
811 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
813 // VLD4LN : Vector Load (single 4-element structure to one lane)
814 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
815 : NLdStLn<1, 0b10, op11_8, op7_4,
816 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
817 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
818 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
819 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
820 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
823 let DecoderMethod = "DecodeVLD4LN";
826 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
827 let Inst{7-5} = lane{2-0};
829 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
830 let Inst{7-6} = lane{1-0};
832 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
833 let Inst{7} = lane{0};
837 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
838 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
839 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
841 // ...with double-spaced registers:
842 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
843 let Inst{7-6} = lane{1-0};
845 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
846 let Inst{7} = lane{0};
850 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
851 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
853 // ...with address register writeback:
854 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
855 : NLdStLn<1, 0b10, op11_8, op7_4,
856 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
857 (ins addrmode6:$Rn, am6offset:$Rm,
858 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
859 IIC_VLD4lnu, "vld4", Dt,
860 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
861 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
864 let DecoderMethod = "DecodeVLD4LN" ;
867 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
868 let Inst{7-5} = lane{2-0};
870 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
871 let Inst{7-6} = lane{1-0};
873 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
874 let Inst{7} = lane{0};
878 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
879 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
880 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
882 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
883 let Inst{7-6} = lane{1-0};
885 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
886 let Inst{7} = lane{0};
890 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
891 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
893 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
895 // VLD1DUP : Vector Load (single element to all lanes)
896 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
897 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
898 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
899 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
902 let DecoderMethod = "DecodeVLD1DupInstruction";
904 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
905 let Pattern = [(set QPR:$dst,
906 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
909 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
910 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
911 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
913 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
914 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
915 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
917 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
918 (VLD1DUPd32 addrmode6:$addr)>;
919 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
920 (VLD1DUPq32Pseudo addrmode6:$addr)>;
922 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
924 class VLD1QDUP<bits<4> op7_4, string Dt>
925 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
926 (ins addrmode6dup:$Rn), IIC_VLD1dup,
927 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
930 let DecoderMethod = "DecodeVLD1DupInstruction";
933 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
934 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
935 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
937 // ...with address register writeback:
938 class VLD1DUPWB<bits<4> op7_4, string Dt>
939 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
940 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
941 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
943 let DecoderMethod = "DecodeVLD1DupInstruction";
945 class VLD1QDUPWB<bits<4> op7_4, string Dt>
946 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
947 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
948 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
950 let DecoderMethod = "DecodeVLD1DupInstruction";
953 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
954 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
955 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
957 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
958 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
959 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
961 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
962 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
963 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
965 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
966 class VLD2DUP<bits<4> op7_4, string Dt>
967 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
968 (ins addrmode6dup:$Rn), IIC_VLD2dup,
969 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
972 let DecoderMethod = "DecodeVLD2DupInstruction";
975 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
976 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
977 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
979 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
980 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
981 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
983 // ...with double-spaced registers (not used for codegen):
984 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
985 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
986 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
988 // ...with address register writeback:
989 class VLD2DUPWB<bits<4> op7_4, string Dt>
990 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
991 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
992 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
994 let DecoderMethod = "DecodeVLD2DupInstruction";
997 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
998 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
999 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1001 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1002 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1003 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1005 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1006 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1007 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1009 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1010 class VLD3DUP<bits<4> op7_4, string Dt>
1011 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1012 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1013 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1016 let DecoderMethod = "DecodeVLD3DupInstruction";
1019 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1020 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1021 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1023 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1024 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1025 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1027 // ...with double-spaced registers (not used for codegen):
1028 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1029 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1030 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1032 // ...with address register writeback:
1033 class VLD3DUPWB<bits<4> op7_4, string Dt>
1034 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1035 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1036 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1037 "$Rn.addr = $wb", []> {
1039 let DecoderMethod = "DecodeVLD3DupInstruction";
1042 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1043 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1044 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1046 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1047 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1048 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1050 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1051 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1052 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1054 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1055 class VLD4DUP<bits<4> op7_4, string Dt>
1056 : NLdSt<1, 0b10, 0b1111, op7_4,
1057 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1058 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1059 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1061 let Inst{4} = Rn{4};
1062 let DecoderMethod = "DecodeVLD4DupInstruction";
1065 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1066 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1067 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1069 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1070 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1071 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1073 // ...with double-spaced registers (not used for codegen):
1074 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1075 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1076 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1078 // ...with address register writeback:
1079 class VLD4DUPWB<bits<4> op7_4, string Dt>
1080 : NLdSt<1, 0b10, 0b1111, op7_4,
1081 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1082 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1083 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1084 "$Rn.addr = $wb", []> {
1085 let Inst{4} = Rn{4};
1086 let DecoderMethod = "DecodeVLD4DupInstruction";
1089 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1090 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1091 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1093 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1094 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1095 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1097 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1098 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1099 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1101 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1103 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1105 // Classes for VST* pseudo-instructions with multi-register operands.
1106 // These are expanded to real instructions after register allocation.
1107 class VSTQPseudo<InstrItinClass itin>
1108 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1109 class VSTQWBPseudo<InstrItinClass itin>
1110 : PseudoNLdSt<(outs GPR:$wb),
1111 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1112 "$addr.addr = $wb">;
1113 class VSTQQPseudo<InstrItinClass itin>
1114 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1115 class VSTQQWBPseudo<InstrItinClass itin>
1116 : PseudoNLdSt<(outs GPR:$wb),
1117 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1118 "$addr.addr = $wb">;
1119 class VSTQQQQPseudo<InstrItinClass itin>
1120 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1121 class VSTQQQQWBPseudo<InstrItinClass itin>
1122 : PseudoNLdSt<(outs GPR:$wb),
1123 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1124 "$addr.addr = $wb">;
1126 // VST1 : Vector Store (multiple single elements)
1127 class VST1D<bits<4> op7_4, string Dt>
1128 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1129 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1131 let Inst{4} = Rn{4};
1132 let DecoderMethod = "DecodeVSTInstruction";
1134 class VST1Q<bits<4> op7_4, string Dt>
1135 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1136 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1137 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1139 let Inst{5-4} = Rn{5-4};
1140 let DecoderMethod = "DecodeVSTInstruction";
1143 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1144 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1145 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1146 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1148 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1149 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1150 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1151 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1153 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1154 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1155 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1156 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1158 // ...with address register writeback:
1159 class VST1DWB<bits<4> op7_4, string Dt>
1160 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1161 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1162 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1163 let Inst{4} = Rn{4};
1164 let DecoderMethod = "DecodeVSTInstruction";
1166 class VST1QWB<bits<4> op7_4, string Dt>
1167 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1168 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1169 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1170 "$Rn.addr = $wb", []> {
1171 let Inst{5-4} = Rn{5-4};
1172 let DecoderMethod = "DecodeVSTInstruction";
1175 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1176 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1177 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1178 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1180 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1181 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1182 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1183 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1185 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1186 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1187 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1188 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1190 // ...with 3 registers (some of these are only for the disassembler):
1191 class VST1D3<bits<4> op7_4, string Dt>
1192 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1193 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1194 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1196 let Inst{4} = Rn{4};
1197 let DecoderMethod = "DecodeVSTInstruction";
1199 class VST1D3WB<bits<4> op7_4, string Dt>
1200 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1201 (ins addrmode6:$Rn, am6offset:$Rm,
1202 DPR:$Vd, DPR:$src2, DPR:$src3),
1203 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1204 "$Rn.addr = $wb", []> {
1205 let Inst{4} = Rn{4};
1206 let DecoderMethod = "DecodeVSTInstruction";
1209 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1210 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1211 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1212 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1214 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1215 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1216 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1217 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1219 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1220 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1222 // ...with 4 registers (some of these are only for the disassembler):
1223 class VST1D4<bits<4> op7_4, string Dt>
1224 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1225 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1226 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1229 let Inst{5-4} = Rn{5-4};
1230 let DecoderMethod = "DecodeVSTInstruction";
1232 class VST1D4WB<bits<4> op7_4, string Dt>
1233 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1234 (ins addrmode6:$Rn, am6offset:$Rm,
1235 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1236 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1237 "$Rn.addr = $wb", []> {
1238 let Inst{5-4} = Rn{5-4};
1239 let DecoderMethod = "DecodeVSTInstruction";
1242 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1243 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1244 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1245 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1247 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1248 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1249 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1250 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1252 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1253 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1255 // VST2 : Vector Store (multiple 2-element structures)
1256 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1257 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1258 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1259 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1261 let Inst{5-4} = Rn{5-4};
1262 let DecoderMethod = "DecodeVSTInstruction";
1264 class VST2Q<bits<4> op7_4, string Dt>
1265 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1266 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1267 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1270 let Inst{5-4} = Rn{5-4};
1271 let DecoderMethod = "DecodeVSTInstruction";
1274 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1275 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1276 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1278 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1279 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1280 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1282 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1283 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1284 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1286 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1287 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1288 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1290 // ...with address register writeback:
1291 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1292 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1293 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1294 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1295 "$Rn.addr = $wb", []> {
1296 let Inst{5-4} = Rn{5-4};
1297 let DecoderMethod = "DecodeVSTInstruction";
1299 class VST2QWB<bits<4> op7_4, string Dt>
1300 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1301 (ins addrmode6:$Rn, am6offset:$Rm,
1302 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1303 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1304 "$Rn.addr = $wb", []> {
1305 let Inst{5-4} = Rn{5-4};
1306 let DecoderMethod = "DecodeVSTInstruction";
1309 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1310 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1311 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1313 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1314 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1315 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1317 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1318 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1319 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1321 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1322 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1323 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1325 // ...with double-spaced registers (for disassembly only):
1326 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1327 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1328 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1329 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1330 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1331 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1333 // VST3 : Vector Store (multiple 3-element structures)
1334 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1335 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1336 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1337 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1339 let Inst{4} = Rn{4};
1340 let DecoderMethod = "DecodeVSTInstruction";
1343 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1344 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1345 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1347 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1348 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1349 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1351 // ...with address register writeback:
1352 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1353 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1354 (ins addrmode6:$Rn, am6offset:$Rm,
1355 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1356 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1357 "$Rn.addr = $wb", []> {
1358 let Inst{4} = Rn{4};
1359 let DecoderMethod = "DecodeVSTInstruction";
1362 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1363 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1364 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1366 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1367 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1368 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1370 // ...with double-spaced registers:
1371 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1372 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1373 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1374 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1375 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1376 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1378 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1379 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1380 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1382 // ...alternate versions to be allocated odd register numbers:
1383 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1384 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1385 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1387 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1388 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1389 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1391 // VST4 : Vector Store (multiple 4-element structures)
1392 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1393 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1394 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1395 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1398 let Inst{5-4} = Rn{5-4};
1399 let DecoderMethod = "DecodeVSTInstruction";
1402 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1403 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1404 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1406 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1407 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1408 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1410 // ...with address register writeback:
1411 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1412 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1413 (ins addrmode6:$Rn, am6offset:$Rm,
1414 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1415 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1416 "$Rn.addr = $wb", []> {
1417 let Inst{5-4} = Rn{5-4};
1418 let DecoderMethod = "DecodeVSTInstruction";
1421 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1422 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1423 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1425 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1426 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1427 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1429 // ...with double-spaced registers:
1430 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1431 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1432 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1433 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1434 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1435 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1437 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1438 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1439 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1441 // ...alternate versions to be allocated odd register numbers:
1442 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1443 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1444 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1446 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1447 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1448 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1450 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1452 // Classes for VST*LN pseudo-instructions with multi-register operands.
1453 // These are expanded to real instructions after register allocation.
1454 class VSTQLNPseudo<InstrItinClass itin>
1455 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1457 class VSTQLNWBPseudo<InstrItinClass itin>
1458 : PseudoNLdSt<(outs GPR:$wb),
1459 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1460 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1461 class VSTQQLNPseudo<InstrItinClass itin>
1462 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1464 class VSTQQLNWBPseudo<InstrItinClass itin>
1465 : PseudoNLdSt<(outs GPR:$wb),
1466 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1467 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1468 class VSTQQQQLNPseudo<InstrItinClass itin>
1469 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1471 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1472 : PseudoNLdSt<(outs GPR:$wb),
1473 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1474 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1476 // VST1LN : Vector Store (single element from one lane)
1477 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1478 PatFrag StoreOp, SDNode ExtractOp>
1479 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1480 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1481 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1482 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1484 let DecoderMethod = "DecodeVST1LN";
1486 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1487 PatFrag StoreOp, SDNode ExtractOp>
1488 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1489 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1490 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1491 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1493 let DecoderMethod = "DecodeVST1LN";
1495 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1496 : VSTQLNPseudo<IIC_VST1ln> {
1497 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1501 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1503 let Inst{7-5} = lane{2-0};
1505 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1507 let Inst{7-6} = lane{1-0};
1508 let Inst{4} = Rn{5};
1511 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1512 let Inst{7} = lane{0};
1513 let Inst{5-4} = Rn{5-4};
1516 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1517 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1518 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1520 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1521 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1522 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1523 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1525 // ...with address register writeback:
1526 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1527 PatFrag StoreOp, SDNode ExtractOp>
1528 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1529 (ins addrmode6:$Rn, am6offset:$Rm,
1530 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1531 "\\{$Vd[$lane]\\}, $Rn$Rm",
1533 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1534 addrmode6:$Rn, am6offset:$Rm))]> {
1535 let DecoderMethod = "DecodeVST1LN";
1537 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1538 : VSTQLNWBPseudo<IIC_VST1lnu> {
1539 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1540 addrmode6:$addr, am6offset:$offset))];
1543 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1545 let Inst{7-5} = lane{2-0};
1547 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1549 let Inst{7-6} = lane{1-0};
1550 let Inst{4} = Rn{5};
1552 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1554 let Inst{7} = lane{0};
1555 let Inst{5-4} = Rn{5-4};
1558 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1559 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1560 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1562 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1564 // VST2LN : Vector Store (single 2-element structure from one lane)
1565 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1566 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1567 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1568 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1571 let Inst{4} = Rn{4};
1572 let DecoderMethod = "DecodeVST2LN";
1575 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1576 let Inst{7-5} = lane{2-0};
1578 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1579 let Inst{7-6} = lane{1-0};
1581 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1582 let Inst{7} = lane{0};
1585 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1586 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1587 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1589 // ...with double-spaced registers:
1590 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1591 let Inst{7-6} = lane{1-0};
1592 let Inst{4} = Rn{4};
1594 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1595 let Inst{7} = lane{0};
1596 let Inst{4} = Rn{4};
1599 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1600 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1602 // ...with address register writeback:
1603 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1604 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1605 (ins addrmode6:$addr, am6offset:$offset,
1606 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1607 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1608 "$addr.addr = $wb", []> {
1609 let Inst{4} = Rn{4};
1610 let DecoderMethod = "DecodeVST2LN";
1613 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1614 let Inst{7-5} = lane{2-0};
1616 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1617 let Inst{7-6} = lane{1-0};
1619 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1620 let Inst{7} = lane{0};
1623 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1624 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1625 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1627 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1628 let Inst{7-6} = lane{1-0};
1630 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1631 let Inst{7} = lane{0};
1634 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1635 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1637 // VST3LN : Vector Store (single 3-element structure from one lane)
1638 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1639 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1640 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1641 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1642 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1644 let DecoderMethod = "DecodeVST3LN";
1647 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1648 let Inst{7-5} = lane{2-0};
1650 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1651 let Inst{7-6} = lane{1-0};
1653 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1654 let Inst{7} = lane{0};
1657 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1658 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1659 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1661 // ...with double-spaced registers:
1662 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1663 let Inst{7-6} = lane{1-0};
1665 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1666 let Inst{7} = lane{0};
1669 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1670 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1672 // ...with address register writeback:
1673 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1674 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1675 (ins addrmode6:$Rn, am6offset:$Rm,
1676 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1677 IIC_VST3lnu, "vst3", Dt,
1678 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1679 "$Rn.addr = $wb", []> {
1680 let DecoderMethod = "DecodeVST3LN";
1683 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1684 let Inst{7-5} = lane{2-0};
1686 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1687 let Inst{7-6} = lane{1-0};
1689 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1690 let Inst{7} = lane{0};
1693 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1694 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1695 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1697 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1698 let Inst{7-6} = lane{1-0};
1700 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1701 let Inst{7} = lane{0};
1704 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1705 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1707 // VST4LN : Vector Store (single 4-element structure from one lane)
1708 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1709 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1710 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1711 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1712 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1715 let Inst{4} = Rn{4};
1716 let DecoderMethod = "DecodeVST4LN";
1719 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1720 let Inst{7-5} = lane{2-0};
1722 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1723 let Inst{7-6} = lane{1-0};
1725 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1726 let Inst{7} = lane{0};
1727 let Inst{5} = Rn{5};
1730 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1731 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1732 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1734 // ...with double-spaced registers:
1735 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1736 let Inst{7-6} = lane{1-0};
1738 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1739 let Inst{7} = lane{0};
1740 let Inst{5} = Rn{5};
1743 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1744 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1746 // ...with address register writeback:
1747 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1748 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1749 (ins addrmode6:$Rn, am6offset:$Rm,
1750 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1751 IIC_VST4lnu, "vst4", Dt,
1752 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1753 "$Rn.addr = $wb", []> {
1754 let Inst{4} = Rn{4};
1755 let DecoderMethod = "DecodeVST4LN";
1758 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1759 let Inst{7-5} = lane{2-0};
1761 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1762 let Inst{7-6} = lane{1-0};
1764 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1765 let Inst{7} = lane{0};
1766 let Inst{5} = Rn{5};
1769 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1770 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1771 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1773 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1774 let Inst{7-6} = lane{1-0};
1776 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1777 let Inst{7} = lane{0};
1778 let Inst{5} = Rn{5};
1781 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1782 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1784 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1787 //===----------------------------------------------------------------------===//
1788 // NEON pattern fragments
1789 //===----------------------------------------------------------------------===//
1791 // Extract D sub-registers of Q registers.
1792 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1793 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1794 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1796 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1797 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1798 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1800 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1801 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1802 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1804 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1805 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1806 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1809 // Extract S sub-registers of Q/D registers.
1810 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1811 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1812 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1815 // Translate lane numbers from Q registers to D subregs.
1816 def SubReg_i8_lane : SDNodeXForm<imm, [{
1817 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1819 def SubReg_i16_lane : SDNodeXForm<imm, [{
1820 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1822 def SubReg_i32_lane : SDNodeXForm<imm, [{
1823 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1826 //===----------------------------------------------------------------------===//
1827 // Instruction Classes
1828 //===----------------------------------------------------------------------===//
1830 // Basic 2-register operations: double- and quad-register.
1831 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1832 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1833 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1834 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1835 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1836 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1837 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1838 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1839 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1840 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1841 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1842 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1844 // Basic 2-register intrinsics, both double- and quad-register.
1845 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1846 bits<2> op17_16, bits<5> op11_7, bit op4,
1847 InstrItinClass itin, string OpcodeStr, string Dt,
1848 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1849 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1850 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1851 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1852 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1853 bits<2> op17_16, bits<5> op11_7, bit op4,
1854 InstrItinClass itin, string OpcodeStr, string Dt,
1855 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1856 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1857 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1858 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1860 // Narrow 2-register operations.
1861 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1862 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1863 InstrItinClass itin, string OpcodeStr, string Dt,
1864 ValueType TyD, ValueType TyQ, SDNode OpNode>
1865 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1866 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1867 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1869 // Narrow 2-register intrinsics.
1870 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1871 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1872 InstrItinClass itin, string OpcodeStr, string Dt,
1873 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1874 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1875 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1876 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1878 // Long 2-register operations (currently only used for VMOVL).
1879 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1880 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1881 InstrItinClass itin, string OpcodeStr, string Dt,
1882 ValueType TyQ, ValueType TyD, SDNode OpNode>
1883 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1884 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1885 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1887 // Long 2-register intrinsics.
1888 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1889 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1890 InstrItinClass itin, string OpcodeStr, string Dt,
1891 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1892 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1893 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1894 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1896 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1897 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1898 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1899 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1900 OpcodeStr, Dt, "$Vd, $Vm",
1901 "$src1 = $Vd, $src2 = $Vm", []>;
1902 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1903 InstrItinClass itin, string OpcodeStr, string Dt>
1904 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1905 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1906 "$src1 = $Vd, $src2 = $Vm", []>;
1908 // Basic 3-register operations: double- and quad-register.
1909 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1910 InstrItinClass itin, string OpcodeStr, string Dt,
1911 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1912 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1913 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1914 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1915 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1916 let isCommutable = Commutable;
1918 // Same as N3VD but no data type.
1919 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1920 InstrItinClass itin, string OpcodeStr,
1921 ValueType ResTy, ValueType OpTy,
1922 SDNode OpNode, bit Commutable>
1923 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1924 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1925 OpcodeStr, "$Vd, $Vn, $Vm", "",
1926 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1927 let isCommutable = Commutable;
1930 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1931 InstrItinClass itin, string OpcodeStr, string Dt,
1932 ValueType Ty, SDNode ShOp>
1933 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1934 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1935 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1937 (Ty (ShOp (Ty DPR:$Vn),
1938 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1939 let isCommutable = 0;
1941 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1942 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1943 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1944 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1945 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1947 (Ty (ShOp (Ty DPR:$Vn),
1948 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1949 let isCommutable = 0;
1952 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1953 InstrItinClass itin, string OpcodeStr, string Dt,
1954 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1955 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1956 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1957 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1958 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1959 let isCommutable = Commutable;
1961 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1962 InstrItinClass itin, string OpcodeStr,
1963 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1964 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1965 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1966 OpcodeStr, "$Vd, $Vn, $Vm", "",
1967 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1968 let isCommutable = Commutable;
1970 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1971 InstrItinClass itin, string OpcodeStr, string Dt,
1972 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1973 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
1974 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1975 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1976 [(set (ResTy QPR:$Vd),
1977 (ResTy (ShOp (ResTy QPR:$Vn),
1978 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1980 let isCommutable = 0;
1982 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1983 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1984 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
1985 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1986 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1987 [(set (ResTy QPR:$Vd),
1988 (ResTy (ShOp (ResTy QPR:$Vn),
1989 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1991 let isCommutable = 0;
1994 // Basic 3-register intrinsics, both double- and quad-register.
1995 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1996 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1997 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1998 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1999 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2000 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2001 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2002 let isCommutable = Commutable;
2004 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2005 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2006 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2007 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2008 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2010 (Ty (IntOp (Ty DPR:$Vn),
2011 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2013 let isCommutable = 0;
2015 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2016 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2017 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2018 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2019 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2021 (Ty (IntOp (Ty DPR:$Vn),
2022 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2023 let isCommutable = 0;
2025 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2026 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2027 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2028 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2029 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2030 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2031 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2032 let isCommutable = 0;
2035 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2036 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2037 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2038 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2039 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2040 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2041 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2042 let isCommutable = Commutable;
2044 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2045 string OpcodeStr, string Dt,
2046 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2047 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2048 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2049 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2050 [(set (ResTy QPR:$Vd),
2051 (ResTy (IntOp (ResTy QPR:$Vn),
2052 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2054 let isCommutable = 0;
2056 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2057 string OpcodeStr, string Dt,
2058 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2059 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2060 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2061 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2062 [(set (ResTy QPR:$Vd),
2063 (ResTy (IntOp (ResTy QPR:$Vn),
2064 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2066 let isCommutable = 0;
2068 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2069 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2070 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2071 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2072 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2073 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2074 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2075 let isCommutable = 0;
2078 // Multiply-Add/Sub operations: double- and quad-register.
2079 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2080 InstrItinClass itin, string OpcodeStr, string Dt,
2081 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2082 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2083 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2084 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2085 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2086 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2088 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2089 string OpcodeStr, string Dt,
2090 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2091 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2093 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2095 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2097 (Ty (ShOp (Ty DPR:$src1),
2099 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2101 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2102 string OpcodeStr, string Dt,
2103 ValueType Ty, SDNode MulOp, SDNode ShOp>
2104 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2106 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2108 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2110 (Ty (ShOp (Ty DPR:$src1),
2112 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2115 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2116 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2117 SDPatternOperator MulOp, SDPatternOperator OpNode>
2118 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2119 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2120 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2121 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2122 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2123 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2124 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2125 SDPatternOperator MulOp, SDPatternOperator ShOp>
2126 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2128 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2130 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2131 [(set (ResTy QPR:$Vd),
2132 (ResTy (ShOp (ResTy QPR:$src1),
2133 (ResTy (MulOp QPR:$Vn,
2134 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2136 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2137 string OpcodeStr, string Dt,
2138 ValueType ResTy, ValueType OpTy,
2139 SDNode MulOp, SDNode ShOp>
2140 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2142 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2144 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2145 [(set (ResTy QPR:$Vd),
2146 (ResTy (ShOp (ResTy QPR:$src1),
2147 (ResTy (MulOp QPR:$Vn,
2148 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2151 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2152 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2153 InstrItinClass itin, string OpcodeStr, string Dt,
2154 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2155 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2156 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2157 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2158 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2159 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2160 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2161 InstrItinClass itin, string OpcodeStr, string Dt,
2162 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2163 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2164 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2165 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2166 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2167 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2169 // Neon 3-argument intrinsics, both double- and quad-register.
2170 // The destination register is also used as the first source operand register.
2171 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2172 InstrItinClass itin, string OpcodeStr, string Dt,
2173 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2174 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2175 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2176 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2177 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2178 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2179 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2180 InstrItinClass itin, string OpcodeStr, string Dt,
2181 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2182 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2183 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2184 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2185 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2186 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2188 // Long Multiply-Add/Sub operations.
2189 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2190 InstrItinClass itin, string OpcodeStr, string Dt,
2191 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2192 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2193 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2194 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2195 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2196 (TyQ (MulOp (TyD DPR:$Vn),
2197 (TyD DPR:$Vm)))))]>;
2198 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2199 InstrItinClass itin, string OpcodeStr, string Dt,
2200 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2201 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2202 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2204 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2206 (OpNode (TyQ QPR:$src1),
2207 (TyQ (MulOp (TyD DPR:$Vn),
2208 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2210 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2211 InstrItinClass itin, string OpcodeStr, string Dt,
2212 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2213 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2214 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2216 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2218 (OpNode (TyQ QPR:$src1),
2219 (TyQ (MulOp (TyD DPR:$Vn),
2220 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2223 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2224 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2225 InstrItinClass itin, string OpcodeStr, string Dt,
2226 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2228 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2229 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2230 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2231 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2232 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2233 (TyD DPR:$Vm)))))))]>;
2235 // Neon Long 3-argument intrinsic. The destination register is
2236 // a quad-register and is also used as the first source operand register.
2237 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2238 InstrItinClass itin, string OpcodeStr, string Dt,
2239 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2240 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2241 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2242 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2244 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2245 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2246 string OpcodeStr, string Dt,
2247 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2248 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2250 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2252 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2253 [(set (ResTy QPR:$Vd),
2254 (ResTy (IntOp (ResTy QPR:$src1),
2256 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2258 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2259 InstrItinClass itin, string OpcodeStr, string Dt,
2260 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2261 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2263 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2265 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2266 [(set (ResTy QPR:$Vd),
2267 (ResTy (IntOp (ResTy QPR:$src1),
2269 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2272 // Narrowing 3-register intrinsics.
2273 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2274 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2275 Intrinsic IntOp, bit Commutable>
2276 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2277 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2278 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2279 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2280 let isCommutable = Commutable;
2283 // Long 3-register operations.
2284 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2285 InstrItinClass itin, string OpcodeStr, string Dt,
2286 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2287 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2288 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2289 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2290 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2291 let isCommutable = Commutable;
2293 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2294 InstrItinClass itin, string OpcodeStr, string Dt,
2295 ValueType TyQ, ValueType TyD, SDNode OpNode>
2296 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2297 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2298 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2300 (TyQ (OpNode (TyD DPR:$Vn),
2301 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2302 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2303 InstrItinClass itin, string OpcodeStr, string Dt,
2304 ValueType TyQ, ValueType TyD, SDNode OpNode>
2305 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2306 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2307 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2309 (TyQ (OpNode (TyD DPR:$Vn),
2310 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2312 // Long 3-register operations with explicitly extended operands.
2313 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2314 InstrItinClass itin, string OpcodeStr, string Dt,
2315 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2317 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2318 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2319 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2320 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2321 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2322 let isCommutable = Commutable;
2325 // Long 3-register intrinsics with explicit extend (VABDL).
2326 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2327 InstrItinClass itin, string OpcodeStr, string Dt,
2328 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2330 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2331 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2332 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2333 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2334 (TyD DPR:$Vm))))))]> {
2335 let isCommutable = Commutable;
2338 // Long 3-register intrinsics.
2339 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2340 InstrItinClass itin, string OpcodeStr, string Dt,
2341 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2342 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2343 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2344 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2345 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2346 let isCommutable = Commutable;
2348 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2349 string OpcodeStr, string Dt,
2350 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2351 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2352 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2353 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2354 [(set (ResTy QPR:$Vd),
2355 (ResTy (IntOp (OpTy DPR:$Vn),
2356 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2358 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2359 InstrItinClass itin, string OpcodeStr, string Dt,
2360 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2361 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2362 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2363 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2364 [(set (ResTy QPR:$Vd),
2365 (ResTy (IntOp (OpTy DPR:$Vn),
2366 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2369 // Wide 3-register operations.
2370 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2371 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2372 SDNode OpNode, SDNode ExtOp, bit Commutable>
2373 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2374 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2375 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2376 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2377 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2378 let isCommutable = Commutable;
2381 // Pairwise long 2-register intrinsics, both double- and quad-register.
2382 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2383 bits<2> op17_16, bits<5> op11_7, bit op4,
2384 string OpcodeStr, string Dt,
2385 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2386 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2387 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2388 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2389 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2390 bits<2> op17_16, bits<5> op11_7, bit op4,
2391 string OpcodeStr, string Dt,
2392 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2394 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2395 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2397 // Pairwise long 2-register accumulate intrinsics,
2398 // both double- and quad-register.
2399 // The destination register is also used as the first source operand register.
2400 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2401 bits<2> op17_16, bits<5> op11_7, bit op4,
2402 string OpcodeStr, string Dt,
2403 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2404 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2405 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2406 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2407 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2408 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2409 bits<2> op17_16, bits<5> op11_7, bit op4,
2410 string OpcodeStr, string Dt,
2411 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2412 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2413 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2414 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2415 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2417 // Shift by immediate,
2418 // both double- and quad-register.
2419 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2420 Format f, InstrItinClass itin, Operand ImmTy,
2421 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2422 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2423 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2424 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2425 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2426 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2427 Format f, InstrItinClass itin, Operand ImmTy,
2428 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2429 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2430 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2431 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2432 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2434 // Long shift by immediate.
2435 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2436 string OpcodeStr, string Dt,
2437 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2438 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2439 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2440 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2441 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2442 (i32 imm:$SIMM))))]>;
2444 // Narrow shift by immediate.
2445 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2446 InstrItinClass itin, string OpcodeStr, string Dt,
2447 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2448 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2449 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2450 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2451 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2452 (i32 imm:$SIMM))))]>;
2454 // Shift right by immediate and accumulate,
2455 // both double- and quad-register.
2456 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2457 Operand ImmTy, string OpcodeStr, string Dt,
2458 ValueType Ty, SDNode ShOp>
2459 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2460 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2461 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2462 [(set DPR:$Vd, (Ty (add DPR:$src1,
2463 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2464 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2465 Operand ImmTy, string OpcodeStr, string Dt,
2466 ValueType Ty, SDNode ShOp>
2467 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2468 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2469 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2470 [(set QPR:$Vd, (Ty (add QPR:$src1,
2471 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2473 // Shift by immediate and insert,
2474 // both double- and quad-register.
2475 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2476 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2477 ValueType Ty,SDNode ShOp>
2478 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2479 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2480 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2481 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2482 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2483 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2484 ValueType Ty,SDNode ShOp>
2485 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2486 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2487 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2488 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2490 // Convert, with fractional bits immediate,
2491 // both double- and quad-register.
2492 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2493 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2495 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2496 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2497 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2498 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2499 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2500 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2502 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2503 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2504 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2505 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2507 //===----------------------------------------------------------------------===//
2509 //===----------------------------------------------------------------------===//
2511 // Abbreviations used in multiclass suffixes:
2512 // Q = quarter int (8 bit) elements
2513 // H = half int (16 bit) elements
2514 // S = single int (32 bit) elements
2515 // D = double int (64 bit) elements
2517 // Neon 2-register vector operations and intrinsics.
2519 // Neon 2-register comparisons.
2520 // source operand element sizes of 8, 16 and 32 bits:
2521 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2522 bits<5> op11_7, bit op4, string opc, string Dt,
2523 string asm, SDNode OpNode> {
2524 // 64-bit vector types.
2525 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2526 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2527 opc, !strconcat(Dt, "8"), asm, "",
2528 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2529 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2530 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2531 opc, !strconcat(Dt, "16"), asm, "",
2532 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2533 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2534 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2535 opc, !strconcat(Dt, "32"), asm, "",
2536 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2537 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2538 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2539 opc, "f32", asm, "",
2540 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2541 let Inst{10} = 1; // overwrite F = 1
2544 // 128-bit vector types.
2545 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2546 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2547 opc, !strconcat(Dt, "8"), asm, "",
2548 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2549 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2550 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2551 opc, !strconcat(Dt, "16"), asm, "",
2552 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2553 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2554 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2555 opc, !strconcat(Dt, "32"), asm, "",
2556 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2557 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2558 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2559 opc, "f32", asm, "",
2560 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2561 let Inst{10} = 1; // overwrite F = 1
2566 // Neon 2-register vector intrinsics,
2567 // element sizes of 8, 16 and 32 bits:
2568 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2569 bits<5> op11_7, bit op4,
2570 InstrItinClass itinD, InstrItinClass itinQ,
2571 string OpcodeStr, string Dt, Intrinsic IntOp> {
2572 // 64-bit vector types.
2573 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2574 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2575 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2576 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2577 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2578 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2580 // 128-bit vector types.
2581 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2582 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2583 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2584 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2585 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2586 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2590 // Neon Narrowing 2-register vector operations,
2591 // source operand element sizes of 16, 32 and 64 bits:
2592 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2593 bits<5> op11_7, bit op6, bit op4,
2594 InstrItinClass itin, string OpcodeStr, string Dt,
2596 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2597 itin, OpcodeStr, !strconcat(Dt, "16"),
2598 v8i8, v8i16, OpNode>;
2599 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2600 itin, OpcodeStr, !strconcat(Dt, "32"),
2601 v4i16, v4i32, OpNode>;
2602 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2603 itin, OpcodeStr, !strconcat(Dt, "64"),
2604 v2i32, v2i64, OpNode>;
2607 // Neon Narrowing 2-register vector intrinsics,
2608 // source operand element sizes of 16, 32 and 64 bits:
2609 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2610 bits<5> op11_7, bit op6, bit op4,
2611 InstrItinClass itin, string OpcodeStr, string Dt,
2613 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2614 itin, OpcodeStr, !strconcat(Dt, "16"),
2615 v8i8, v8i16, IntOp>;
2616 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2617 itin, OpcodeStr, !strconcat(Dt, "32"),
2618 v4i16, v4i32, IntOp>;
2619 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2620 itin, OpcodeStr, !strconcat(Dt, "64"),
2621 v2i32, v2i64, IntOp>;
2625 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2626 // source operand element sizes of 16, 32 and 64 bits:
2627 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2628 string OpcodeStr, string Dt, SDNode OpNode> {
2629 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2630 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2631 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2632 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2633 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2634 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2638 // Neon 3-register vector operations.
2640 // First with only element sizes of 8, 16 and 32 bits:
2641 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2642 InstrItinClass itinD16, InstrItinClass itinD32,
2643 InstrItinClass itinQ16, InstrItinClass itinQ32,
2644 string OpcodeStr, string Dt,
2645 SDNode OpNode, bit Commutable = 0> {
2646 // 64-bit vector types.
2647 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2648 OpcodeStr, !strconcat(Dt, "8"),
2649 v8i8, v8i8, OpNode, Commutable>;
2650 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2651 OpcodeStr, !strconcat(Dt, "16"),
2652 v4i16, v4i16, OpNode, Commutable>;
2653 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2654 OpcodeStr, !strconcat(Dt, "32"),
2655 v2i32, v2i32, OpNode, Commutable>;
2657 // 128-bit vector types.
2658 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2659 OpcodeStr, !strconcat(Dt, "8"),
2660 v16i8, v16i8, OpNode, Commutable>;
2661 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2662 OpcodeStr, !strconcat(Dt, "16"),
2663 v8i16, v8i16, OpNode, Commutable>;
2664 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2665 OpcodeStr, !strconcat(Dt, "32"),
2666 v4i32, v4i32, OpNode, Commutable>;
2669 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2670 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2672 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2674 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2675 v8i16, v4i16, ShOp>;
2676 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2677 v4i32, v2i32, ShOp>;
2680 // ....then also with element size 64 bits:
2681 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2682 InstrItinClass itinD, InstrItinClass itinQ,
2683 string OpcodeStr, string Dt,
2684 SDNode OpNode, bit Commutable = 0>
2685 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2686 OpcodeStr, Dt, OpNode, Commutable> {
2687 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2688 OpcodeStr, !strconcat(Dt, "64"),
2689 v1i64, v1i64, OpNode, Commutable>;
2690 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2691 OpcodeStr, !strconcat(Dt, "64"),
2692 v2i64, v2i64, OpNode, Commutable>;
2696 // Neon 3-register vector intrinsics.
2698 // First with only element sizes of 16 and 32 bits:
2699 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2700 InstrItinClass itinD16, InstrItinClass itinD32,
2701 InstrItinClass itinQ16, InstrItinClass itinQ32,
2702 string OpcodeStr, string Dt,
2703 Intrinsic IntOp, bit Commutable = 0> {
2704 // 64-bit vector types.
2705 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2706 OpcodeStr, !strconcat(Dt, "16"),
2707 v4i16, v4i16, IntOp, Commutable>;
2708 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2709 OpcodeStr, !strconcat(Dt, "32"),
2710 v2i32, v2i32, IntOp, Commutable>;
2712 // 128-bit vector types.
2713 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2714 OpcodeStr, !strconcat(Dt, "16"),
2715 v8i16, v8i16, IntOp, Commutable>;
2716 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2717 OpcodeStr, !strconcat(Dt, "32"),
2718 v4i32, v4i32, IntOp, Commutable>;
2720 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2721 InstrItinClass itinD16, InstrItinClass itinD32,
2722 InstrItinClass itinQ16, InstrItinClass itinQ32,
2723 string OpcodeStr, string Dt,
2725 // 64-bit vector types.
2726 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2727 OpcodeStr, !strconcat(Dt, "16"),
2728 v4i16, v4i16, IntOp>;
2729 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2730 OpcodeStr, !strconcat(Dt, "32"),
2731 v2i32, v2i32, IntOp>;
2733 // 128-bit vector types.
2734 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2735 OpcodeStr, !strconcat(Dt, "16"),
2736 v8i16, v8i16, IntOp>;
2737 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2738 OpcodeStr, !strconcat(Dt, "32"),
2739 v4i32, v4i32, IntOp>;
2742 multiclass N3VIntSL_HS<bits<4> op11_8,
2743 InstrItinClass itinD16, InstrItinClass itinD32,
2744 InstrItinClass itinQ16, InstrItinClass itinQ32,
2745 string OpcodeStr, string Dt, Intrinsic IntOp> {
2746 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2747 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2748 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2749 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2750 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2751 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2752 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2753 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2756 // ....then also with element size of 8 bits:
2757 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2758 InstrItinClass itinD16, InstrItinClass itinD32,
2759 InstrItinClass itinQ16, InstrItinClass itinQ32,
2760 string OpcodeStr, string Dt,
2761 Intrinsic IntOp, bit Commutable = 0>
2762 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2763 OpcodeStr, Dt, IntOp, Commutable> {
2764 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2765 OpcodeStr, !strconcat(Dt, "8"),
2766 v8i8, v8i8, IntOp, Commutable>;
2767 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2768 OpcodeStr, !strconcat(Dt, "8"),
2769 v16i8, v16i8, IntOp, Commutable>;
2771 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2772 InstrItinClass itinD16, InstrItinClass itinD32,
2773 InstrItinClass itinQ16, InstrItinClass itinQ32,
2774 string OpcodeStr, string Dt,
2776 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2777 OpcodeStr, Dt, IntOp> {
2778 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2779 OpcodeStr, !strconcat(Dt, "8"),
2781 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2782 OpcodeStr, !strconcat(Dt, "8"),
2783 v16i8, v16i8, IntOp>;
2787 // ....then also with element size of 64 bits:
2788 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2789 InstrItinClass itinD16, InstrItinClass itinD32,
2790 InstrItinClass itinQ16, InstrItinClass itinQ32,
2791 string OpcodeStr, string Dt,
2792 Intrinsic IntOp, bit Commutable = 0>
2793 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2794 OpcodeStr, Dt, IntOp, Commutable> {
2795 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2796 OpcodeStr, !strconcat(Dt, "64"),
2797 v1i64, v1i64, IntOp, Commutable>;
2798 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2799 OpcodeStr, !strconcat(Dt, "64"),
2800 v2i64, v2i64, IntOp, Commutable>;
2802 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2803 InstrItinClass itinD16, InstrItinClass itinD32,
2804 InstrItinClass itinQ16, InstrItinClass itinQ32,
2805 string OpcodeStr, string Dt,
2807 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2808 OpcodeStr, Dt, IntOp> {
2809 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2810 OpcodeStr, !strconcat(Dt, "64"),
2811 v1i64, v1i64, IntOp>;
2812 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2813 OpcodeStr, !strconcat(Dt, "64"),
2814 v2i64, v2i64, IntOp>;
2817 // Neon Narrowing 3-register vector intrinsics,
2818 // source operand element sizes of 16, 32 and 64 bits:
2819 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2820 string OpcodeStr, string Dt,
2821 Intrinsic IntOp, bit Commutable = 0> {
2822 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2823 OpcodeStr, !strconcat(Dt, "16"),
2824 v8i8, v8i16, IntOp, Commutable>;
2825 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2826 OpcodeStr, !strconcat(Dt, "32"),
2827 v4i16, v4i32, IntOp, Commutable>;
2828 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2829 OpcodeStr, !strconcat(Dt, "64"),
2830 v2i32, v2i64, IntOp, Commutable>;
2834 // Neon Long 3-register vector operations.
2836 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2837 InstrItinClass itin16, InstrItinClass itin32,
2838 string OpcodeStr, string Dt,
2839 SDNode OpNode, bit Commutable = 0> {
2840 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2841 OpcodeStr, !strconcat(Dt, "8"),
2842 v8i16, v8i8, OpNode, Commutable>;
2843 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2844 OpcodeStr, !strconcat(Dt, "16"),
2845 v4i32, v4i16, OpNode, Commutable>;
2846 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2847 OpcodeStr, !strconcat(Dt, "32"),
2848 v2i64, v2i32, OpNode, Commutable>;
2851 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2852 InstrItinClass itin, string OpcodeStr, string Dt,
2854 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2855 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2856 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2857 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2860 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2861 InstrItinClass itin16, InstrItinClass itin32,
2862 string OpcodeStr, string Dt,
2863 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2864 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2865 OpcodeStr, !strconcat(Dt, "8"),
2866 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2867 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2868 OpcodeStr, !strconcat(Dt, "16"),
2869 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2870 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2871 OpcodeStr, !strconcat(Dt, "32"),
2872 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2875 // Neon Long 3-register vector intrinsics.
2877 // First with only element sizes of 16 and 32 bits:
2878 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2879 InstrItinClass itin16, InstrItinClass itin32,
2880 string OpcodeStr, string Dt,
2881 Intrinsic IntOp, bit Commutable = 0> {
2882 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2883 OpcodeStr, !strconcat(Dt, "16"),
2884 v4i32, v4i16, IntOp, Commutable>;
2885 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2886 OpcodeStr, !strconcat(Dt, "32"),
2887 v2i64, v2i32, IntOp, Commutable>;
2890 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2891 InstrItinClass itin, string OpcodeStr, string Dt,
2893 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2894 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2895 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2896 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2899 // ....then also with element size of 8 bits:
2900 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2901 InstrItinClass itin16, InstrItinClass itin32,
2902 string OpcodeStr, string Dt,
2903 Intrinsic IntOp, bit Commutable = 0>
2904 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2905 IntOp, Commutable> {
2906 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2907 OpcodeStr, !strconcat(Dt, "8"),
2908 v8i16, v8i8, IntOp, Commutable>;
2911 // ....with explicit extend (VABDL).
2912 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2913 InstrItinClass itin, string OpcodeStr, string Dt,
2914 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2915 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2916 OpcodeStr, !strconcat(Dt, "8"),
2917 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2918 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2919 OpcodeStr, !strconcat(Dt, "16"),
2920 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2921 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2922 OpcodeStr, !strconcat(Dt, "32"),
2923 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2927 // Neon Wide 3-register vector intrinsics,
2928 // source operand element sizes of 8, 16 and 32 bits:
2929 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2930 string OpcodeStr, string Dt,
2931 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2932 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2933 OpcodeStr, !strconcat(Dt, "8"),
2934 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2935 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2936 OpcodeStr, !strconcat(Dt, "16"),
2937 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2938 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2939 OpcodeStr, !strconcat(Dt, "32"),
2940 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2944 // Neon Multiply-Op vector operations,
2945 // element sizes of 8, 16 and 32 bits:
2946 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2947 InstrItinClass itinD16, InstrItinClass itinD32,
2948 InstrItinClass itinQ16, InstrItinClass itinQ32,
2949 string OpcodeStr, string Dt, SDNode OpNode> {
2950 // 64-bit vector types.
2951 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2952 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2953 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2954 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2955 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2956 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2958 // 128-bit vector types.
2959 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2960 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2961 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2962 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2963 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2964 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2967 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2968 InstrItinClass itinD16, InstrItinClass itinD32,
2969 InstrItinClass itinQ16, InstrItinClass itinQ32,
2970 string OpcodeStr, string Dt, SDNode ShOp> {
2971 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2972 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2973 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2974 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2975 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2976 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2978 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2979 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2983 // Neon Intrinsic-Op vector operations,
2984 // element sizes of 8, 16 and 32 bits:
2985 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2986 InstrItinClass itinD, InstrItinClass itinQ,
2987 string OpcodeStr, string Dt, Intrinsic IntOp,
2989 // 64-bit vector types.
2990 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2991 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2992 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2993 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2994 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2995 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2997 // 128-bit vector types.
2998 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2999 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3000 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3001 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3002 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3003 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3006 // Neon 3-argument intrinsics,
3007 // element sizes of 8, 16 and 32 bits:
3008 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3009 InstrItinClass itinD, InstrItinClass itinQ,
3010 string OpcodeStr, string Dt, Intrinsic IntOp> {
3011 // 64-bit vector types.
3012 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3013 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3014 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3015 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3016 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3017 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3019 // 128-bit vector types.
3020 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3021 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3022 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3023 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3024 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3025 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3029 // Neon Long Multiply-Op vector operations,
3030 // element sizes of 8, 16 and 32 bits:
3031 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3032 InstrItinClass itin16, InstrItinClass itin32,
3033 string OpcodeStr, string Dt, SDNode MulOp,
3035 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3036 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3037 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3038 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3039 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3040 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3043 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3044 string Dt, SDNode MulOp, SDNode OpNode> {
3045 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3046 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3047 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3048 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3052 // Neon Long 3-argument intrinsics.
3054 // First with only element sizes of 16 and 32 bits:
3055 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3056 InstrItinClass itin16, InstrItinClass itin32,
3057 string OpcodeStr, string Dt, Intrinsic IntOp> {
3058 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3059 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3060 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3061 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3064 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3065 string OpcodeStr, string Dt, Intrinsic IntOp> {
3066 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3067 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3068 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3069 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3072 // ....then also with element size of 8 bits:
3073 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3074 InstrItinClass itin16, InstrItinClass itin32,
3075 string OpcodeStr, string Dt, Intrinsic IntOp>
3076 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3077 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3078 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3081 // ....with explicit extend (VABAL).
3082 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3083 InstrItinClass itin, string OpcodeStr, string Dt,
3084 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3085 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3086 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3087 IntOp, ExtOp, OpNode>;
3088 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3089 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3090 IntOp, ExtOp, OpNode>;
3091 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3092 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3093 IntOp, ExtOp, OpNode>;
3097 // Neon Pairwise long 2-register intrinsics,
3098 // element sizes of 8, 16 and 32 bits:
3099 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3100 bits<5> op11_7, bit op4,
3101 string OpcodeStr, string Dt, Intrinsic IntOp> {
3102 // 64-bit vector types.
3103 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3104 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3105 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3106 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3107 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3108 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3110 // 128-bit vector types.
3111 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3112 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3113 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3114 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3115 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3116 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3120 // Neon Pairwise long 2-register accumulate intrinsics,
3121 // element sizes of 8, 16 and 32 bits:
3122 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3123 bits<5> op11_7, bit op4,
3124 string OpcodeStr, string Dt, Intrinsic IntOp> {
3125 // 64-bit vector types.
3126 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3127 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3128 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3129 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3130 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3131 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3133 // 128-bit vector types.
3134 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3135 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3136 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3137 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3138 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3139 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3143 // Neon 2-register vector shift by immediate,
3144 // with f of either N2RegVShLFrm or N2RegVShRFrm
3145 // element sizes of 8, 16, 32 and 64 bits:
3146 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3147 InstrItinClass itin, string OpcodeStr, string Dt,
3149 // 64-bit vector types.
3150 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3151 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3152 let Inst{21-19} = 0b001; // imm6 = 001xxx
3154 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3155 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3156 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3158 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3159 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3160 let Inst{21} = 0b1; // imm6 = 1xxxxx
3162 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3163 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3166 // 128-bit vector types.
3167 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3168 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3169 let Inst{21-19} = 0b001; // imm6 = 001xxx
3171 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3172 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3173 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3175 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3176 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3177 let Inst{21} = 0b1; // imm6 = 1xxxxx
3179 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3180 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3183 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3184 InstrItinClass itin, string OpcodeStr, string Dt,
3186 // 64-bit vector types.
3187 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3188 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3189 let Inst{21-19} = 0b001; // imm6 = 001xxx
3191 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3192 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3193 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3195 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3196 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3197 let Inst{21} = 0b1; // imm6 = 1xxxxx
3199 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3200 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3203 // 128-bit vector types.
3204 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3205 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3206 let Inst{21-19} = 0b001; // imm6 = 001xxx
3208 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3209 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3210 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3212 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3213 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3214 let Inst{21} = 0b1; // imm6 = 1xxxxx
3216 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3217 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3221 // Neon Shift-Accumulate vector operations,
3222 // element sizes of 8, 16, 32 and 64 bits:
3223 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3224 string OpcodeStr, string Dt, SDNode ShOp> {
3225 // 64-bit vector types.
3226 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3227 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3228 let Inst{21-19} = 0b001; // imm6 = 001xxx
3230 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3231 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3232 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3234 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3235 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3236 let Inst{21} = 0b1; // imm6 = 1xxxxx
3238 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3239 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3242 // 128-bit vector types.
3243 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3244 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3245 let Inst{21-19} = 0b001; // imm6 = 001xxx
3247 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3248 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3249 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3251 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3252 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3253 let Inst{21} = 0b1; // imm6 = 1xxxxx
3255 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3256 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3260 // Neon Shift-Insert vector operations,
3261 // with f of either N2RegVShLFrm or N2RegVShRFrm
3262 // element sizes of 8, 16, 32 and 64 bits:
3263 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3265 // 64-bit vector types.
3266 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3267 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3268 let Inst{21-19} = 0b001; // imm6 = 001xxx
3270 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3271 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3272 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3274 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3275 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3276 let Inst{21} = 0b1; // imm6 = 1xxxxx
3278 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3279 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3282 // 128-bit vector types.
3283 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3284 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3285 let Inst{21-19} = 0b001; // imm6 = 001xxx
3287 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3288 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3289 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3291 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3292 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3293 let Inst{21} = 0b1; // imm6 = 1xxxxx
3295 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3296 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3299 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3301 // 64-bit vector types.
3302 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3303 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3304 let Inst{21-19} = 0b001; // imm6 = 001xxx
3306 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3307 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3308 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3310 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3311 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3312 let Inst{21} = 0b1; // imm6 = 1xxxxx
3314 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3315 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3318 // 128-bit vector types.
3319 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3320 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3321 let Inst{21-19} = 0b001; // imm6 = 001xxx
3323 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3324 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3325 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3327 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3328 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3329 let Inst{21} = 0b1; // imm6 = 1xxxxx
3331 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3332 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3336 // Neon Shift Long operations,
3337 // element sizes of 8, 16, 32 bits:
3338 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3339 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3340 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3341 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3342 let Inst{21-19} = 0b001; // imm6 = 001xxx
3344 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3345 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3346 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3348 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3349 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3350 let Inst{21} = 0b1; // imm6 = 1xxxxx
3354 // Neon Shift Narrow operations,
3355 // element sizes of 16, 32, 64 bits:
3356 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3357 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3359 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3360 OpcodeStr, !strconcat(Dt, "16"),
3361 v8i8, v8i16, shr_imm8, OpNode> {
3362 let Inst{21-19} = 0b001; // imm6 = 001xxx
3364 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3365 OpcodeStr, !strconcat(Dt, "32"),
3366 v4i16, v4i32, shr_imm16, OpNode> {
3367 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3369 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3370 OpcodeStr, !strconcat(Dt, "64"),
3371 v2i32, v2i64, shr_imm32, OpNode> {
3372 let Inst{21} = 0b1; // imm6 = 1xxxxx
3376 //===----------------------------------------------------------------------===//
3377 // Instruction Definitions.
3378 //===----------------------------------------------------------------------===//
3380 // Vector Add Operations.
3382 // VADD : Vector Add (integer and floating-point)
3383 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3385 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3386 v2f32, v2f32, fadd, 1>;
3387 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3388 v4f32, v4f32, fadd, 1>;
3389 // VADDL : Vector Add Long (Q = D + D)
3390 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3391 "vaddl", "s", add, sext, 1>;
3392 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3393 "vaddl", "u", add, zext, 1>;
3394 // VADDW : Vector Add Wide (Q = Q + D)
3395 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3396 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3397 // VHADD : Vector Halving Add
3398 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3399 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3400 "vhadd", "s", int_arm_neon_vhadds, 1>;
3401 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3402 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3403 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3404 // VRHADD : Vector Rounding Halving Add
3405 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3406 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3407 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3408 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3409 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3410 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3411 // VQADD : Vector Saturating Add
3412 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3413 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3414 "vqadd", "s", int_arm_neon_vqadds, 1>;
3415 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3416 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3417 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3418 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3419 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3420 int_arm_neon_vaddhn, 1>;
3421 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3422 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3423 int_arm_neon_vraddhn, 1>;
3425 // Vector Multiply Operations.
3427 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3428 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3429 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3430 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3431 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3432 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3433 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3434 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3435 v2f32, v2f32, fmul, 1>;
3436 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3437 v4f32, v4f32, fmul, 1>;
3438 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3439 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3440 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3443 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3444 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3445 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3446 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3447 (DSubReg_i16_reg imm:$lane))),
3448 (SubReg_i16_lane imm:$lane)))>;
3449 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3450 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3451 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3452 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3453 (DSubReg_i32_reg imm:$lane))),
3454 (SubReg_i32_lane imm:$lane)))>;
3455 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3456 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3457 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3458 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3459 (DSubReg_i32_reg imm:$lane))),
3460 (SubReg_i32_lane imm:$lane)))>;
3462 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3463 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3464 IIC_VMULi16Q, IIC_VMULi32Q,
3465 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3466 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3467 IIC_VMULi16Q, IIC_VMULi32Q,
3468 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3469 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3470 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3472 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3473 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3474 (DSubReg_i16_reg imm:$lane))),
3475 (SubReg_i16_lane imm:$lane)))>;
3476 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3477 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3479 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3480 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3481 (DSubReg_i32_reg imm:$lane))),
3482 (SubReg_i32_lane imm:$lane)))>;
3484 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3485 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3486 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3487 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3488 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3489 IIC_VMULi16Q, IIC_VMULi32Q,
3490 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3491 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3492 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3494 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3495 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3496 (DSubReg_i16_reg imm:$lane))),
3497 (SubReg_i16_lane imm:$lane)))>;
3498 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3499 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3501 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3502 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3503 (DSubReg_i32_reg imm:$lane))),
3504 (SubReg_i32_lane imm:$lane)))>;
3506 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3507 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3508 "vmull", "s", NEONvmulls, 1>;
3509 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3510 "vmull", "u", NEONvmullu, 1>;
3511 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3512 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3513 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3514 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3516 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3517 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3518 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3519 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3520 "vqdmull", "s", int_arm_neon_vqdmull>;
3522 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3524 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3525 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3526 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3527 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3528 v2f32, fmul_su, fadd_mlx>,
3529 Requires<[HasNEON, UseFPVMLx]>;
3530 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3531 v4f32, fmul_su, fadd_mlx>,
3532 Requires<[HasNEON, UseFPVMLx]>;
3533 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3534 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3535 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3536 v2f32, fmul_su, fadd_mlx>,
3537 Requires<[HasNEON, UseFPVMLx]>;
3538 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3539 v4f32, v2f32, fmul_su, fadd_mlx>,
3540 Requires<[HasNEON, UseFPVMLx]>;
3542 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3543 (mul (v8i16 QPR:$src2),
3544 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3545 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3546 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3547 (DSubReg_i16_reg imm:$lane))),
3548 (SubReg_i16_lane imm:$lane)))>;
3550 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3551 (mul (v4i32 QPR:$src2),
3552 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3553 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3554 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3555 (DSubReg_i32_reg imm:$lane))),
3556 (SubReg_i32_lane imm:$lane)))>;
3558 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3559 (fmul_su (v4f32 QPR:$src2),
3560 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3561 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3563 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3564 (DSubReg_i32_reg imm:$lane))),
3565 (SubReg_i32_lane imm:$lane)))>,
3566 Requires<[HasNEON, UseFPVMLx]>;
3568 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3569 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3570 "vmlal", "s", NEONvmulls, add>;
3571 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3572 "vmlal", "u", NEONvmullu, add>;
3574 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3575 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3577 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3578 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3579 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3580 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3582 // VMLS : Vector Multiply Subtract (integer and floating-point)
3583 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3584 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3585 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3586 v2f32, fmul_su, fsub_mlx>,
3587 Requires<[HasNEON, UseFPVMLx]>;
3588 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3589 v4f32, fmul_su, fsub_mlx>,
3590 Requires<[HasNEON, UseFPVMLx]>;
3591 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3592 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3593 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3594 v2f32, fmul_su, fsub_mlx>,
3595 Requires<[HasNEON, UseFPVMLx]>;
3596 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3597 v4f32, v2f32, fmul_su, fsub_mlx>,
3598 Requires<[HasNEON, UseFPVMLx]>;
3600 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3601 (mul (v8i16 QPR:$src2),
3602 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3603 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3604 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3605 (DSubReg_i16_reg imm:$lane))),
3606 (SubReg_i16_lane imm:$lane)))>;
3608 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3609 (mul (v4i32 QPR:$src2),
3610 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3611 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3612 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3613 (DSubReg_i32_reg imm:$lane))),
3614 (SubReg_i32_lane imm:$lane)))>;
3616 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3617 (fmul_su (v4f32 QPR:$src2),
3618 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3619 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3620 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3621 (DSubReg_i32_reg imm:$lane))),
3622 (SubReg_i32_lane imm:$lane)))>,
3623 Requires<[HasNEON, UseFPVMLx]>;
3625 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3626 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3627 "vmlsl", "s", NEONvmulls, sub>;
3628 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3629 "vmlsl", "u", NEONvmullu, sub>;
3631 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3632 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3634 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3635 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3636 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3637 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3639 // Vector Subtract Operations.
3641 // VSUB : Vector Subtract (integer and floating-point)
3642 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3643 "vsub", "i", sub, 0>;
3644 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3645 v2f32, v2f32, fsub, 0>;
3646 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3647 v4f32, v4f32, fsub, 0>;
3648 // VSUBL : Vector Subtract Long (Q = D - D)
3649 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3650 "vsubl", "s", sub, sext, 0>;
3651 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3652 "vsubl", "u", sub, zext, 0>;
3653 // VSUBW : Vector Subtract Wide (Q = Q - D)
3654 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3655 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3656 // VHSUB : Vector Halving Subtract
3657 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3658 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3659 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3660 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3661 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3662 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3663 // VQSUB : Vector Saturing Subtract
3664 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3665 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3666 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3667 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3668 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3669 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3670 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3671 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3672 int_arm_neon_vsubhn, 0>;
3673 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3674 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3675 int_arm_neon_vrsubhn, 0>;
3677 // Vector Comparisons.
3679 // VCEQ : Vector Compare Equal
3680 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3681 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3682 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3684 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3687 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3688 "$Vd, $Vm, #0", NEONvceqz>;
3690 // VCGE : Vector Compare Greater Than or Equal
3691 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3692 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3693 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3694 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3695 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3697 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3700 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3701 "$Vd, $Vm, #0", NEONvcgez>;
3702 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3703 "$Vd, $Vm, #0", NEONvclez>;
3705 // VCGT : Vector Compare Greater Than
3706 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3707 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3708 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3709 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3710 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3712 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3715 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3716 "$Vd, $Vm, #0", NEONvcgtz>;
3717 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3718 "$Vd, $Vm, #0", NEONvcltz>;
3720 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3721 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3722 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3723 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3724 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3725 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3726 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3727 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3728 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3729 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3730 // VTST : Vector Test Bits
3731 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3732 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3734 // Vector Bitwise Operations.
3736 def vnotd : PatFrag<(ops node:$in),
3737 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3738 def vnotq : PatFrag<(ops node:$in),
3739 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3742 // VAND : Vector Bitwise AND
3743 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3744 v2i32, v2i32, and, 1>;
3745 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3746 v4i32, v4i32, and, 1>;
3748 // VEOR : Vector Bitwise Exclusive OR
3749 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3750 v2i32, v2i32, xor, 1>;
3751 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3752 v4i32, v4i32, xor, 1>;
3754 // VORR : Vector Bitwise OR
3755 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3756 v2i32, v2i32, or, 1>;
3757 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3758 v4i32, v4i32, or, 1>;
3760 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3761 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3763 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3765 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3766 let Inst{9} = SIMM{9};
3769 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3770 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3772 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3774 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3775 let Inst{10-9} = SIMM{10-9};
3778 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3779 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3781 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3783 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3784 let Inst{9} = SIMM{9};
3787 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3788 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3790 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3792 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3793 let Inst{10-9} = SIMM{10-9};
3797 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3798 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3799 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3800 "vbic", "$Vd, $Vn, $Vm", "",
3801 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3802 (vnotd DPR:$Vm))))]>;
3803 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3804 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3805 "vbic", "$Vd, $Vn, $Vm", "",
3806 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3807 (vnotq QPR:$Vm))))]>;
3809 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3810 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3812 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3814 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3815 let Inst{9} = SIMM{9};
3818 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3819 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3821 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3823 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3824 let Inst{10-9} = SIMM{10-9};
3827 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3828 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3830 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3832 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3833 let Inst{9} = SIMM{9};
3836 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3837 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3839 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3841 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3842 let Inst{10-9} = SIMM{10-9};
3845 // VORN : Vector Bitwise OR NOT
3846 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3847 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3848 "vorn", "$Vd, $Vn, $Vm", "",
3849 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3850 (vnotd DPR:$Vm))))]>;
3851 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3852 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3853 "vorn", "$Vd, $Vn, $Vm", "",
3854 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3855 (vnotq QPR:$Vm))))]>;
3857 // VMVN : Vector Bitwise NOT (Immediate)
3859 let isReMaterializable = 1 in {
3861 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3862 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3863 "vmvn", "i16", "$Vd, $SIMM", "",
3864 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3865 let Inst{9} = SIMM{9};
3868 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3869 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3870 "vmvn", "i16", "$Vd, $SIMM", "",
3871 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3872 let Inst{9} = SIMM{9};
3875 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3876 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3877 "vmvn", "i32", "$Vd, $SIMM", "",
3878 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3879 let Inst{11-8} = SIMM{11-8};
3882 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3883 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3884 "vmvn", "i32", "$Vd, $SIMM", "",
3885 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3886 let Inst{11-8} = SIMM{11-8};
3890 // VMVN : Vector Bitwise NOT
3891 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3892 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3893 "vmvn", "$Vd, $Vm", "",
3894 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3895 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3896 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3897 "vmvn", "$Vd, $Vm", "",
3898 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3899 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3900 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3902 // VBSL : Vector Bitwise Select
3903 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3904 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3905 N3RegFrm, IIC_VCNTiD,
3906 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3908 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3910 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3911 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3912 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3914 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3915 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3916 N3RegFrm, IIC_VCNTiQ,
3917 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3919 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3921 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3922 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3923 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3925 // VBIF : Vector Bitwise Insert if False
3926 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3927 // FIXME: This instruction's encoding MAY NOT BE correct.
3928 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3929 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3930 N3RegFrm, IIC_VBINiD,
3931 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3932 [/* For disassembly only; pattern left blank */]>;
3933 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3934 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3935 N3RegFrm, IIC_VBINiQ,
3936 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3937 [/* For disassembly only; pattern left blank */]>;
3939 // VBIT : Vector Bitwise Insert if True
3940 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3941 // FIXME: This instruction's encoding MAY NOT BE correct.
3942 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3943 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3944 N3RegFrm, IIC_VBINiD,
3945 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3946 [/* For disassembly only; pattern left blank */]>;
3947 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3948 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3949 N3RegFrm, IIC_VBINiQ,
3950 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3951 [/* For disassembly only; pattern left blank */]>;
3953 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3954 // for equivalent operations with different register constraints; it just
3957 // Vector Absolute Differences.
3959 // VABD : Vector Absolute Difference
3960 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3961 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3962 "vabd", "s", int_arm_neon_vabds, 1>;
3963 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3964 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3965 "vabd", "u", int_arm_neon_vabdu, 1>;
3966 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3967 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3968 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3969 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3971 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3972 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3973 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3974 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3975 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3977 // VABA : Vector Absolute Difference and Accumulate
3978 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3979 "vaba", "s", int_arm_neon_vabds, add>;
3980 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3981 "vaba", "u", int_arm_neon_vabdu, add>;
3983 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3984 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3985 "vabal", "s", int_arm_neon_vabds, zext, add>;
3986 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3987 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3989 // Vector Maximum and Minimum.
3991 // VMAX : Vector Maximum
3992 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3993 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3994 "vmax", "s", int_arm_neon_vmaxs, 1>;
3995 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3996 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3997 "vmax", "u", int_arm_neon_vmaxu, 1>;
3998 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4000 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4001 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4003 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4005 // VMIN : Vector Minimum
4006 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4007 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4008 "vmin", "s", int_arm_neon_vmins, 1>;
4009 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4010 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4011 "vmin", "u", int_arm_neon_vminu, 1>;
4012 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4014 v2f32, v2f32, int_arm_neon_vmins, 1>;
4015 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4017 v4f32, v4f32, int_arm_neon_vmins, 1>;
4019 // Vector Pairwise Operations.
4021 // VPADD : Vector Pairwise Add
4022 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4024 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4025 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4027 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4028 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4030 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4031 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4032 IIC_VPBIND, "vpadd", "f32",
4033 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4035 // VPADDL : Vector Pairwise Add Long
4036 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4037 int_arm_neon_vpaddls>;
4038 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4039 int_arm_neon_vpaddlu>;
4041 // VPADAL : Vector Pairwise Add and Accumulate Long
4042 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4043 int_arm_neon_vpadals>;
4044 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4045 int_arm_neon_vpadalu>;
4047 // VPMAX : Vector Pairwise Maximum
4048 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4049 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4050 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4051 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4052 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4053 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4054 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4055 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4056 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4057 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4058 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4059 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4060 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4061 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4063 // VPMIN : Vector Pairwise Minimum
4064 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4065 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4066 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4067 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4068 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4069 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4070 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4071 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4072 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4073 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4074 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4075 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4076 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4077 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4079 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4081 // VRECPE : Vector Reciprocal Estimate
4082 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4083 IIC_VUNAD, "vrecpe", "u32",
4084 v2i32, v2i32, int_arm_neon_vrecpe>;
4085 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4086 IIC_VUNAQ, "vrecpe", "u32",
4087 v4i32, v4i32, int_arm_neon_vrecpe>;
4088 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4089 IIC_VUNAD, "vrecpe", "f32",
4090 v2f32, v2f32, int_arm_neon_vrecpe>;
4091 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4092 IIC_VUNAQ, "vrecpe", "f32",
4093 v4f32, v4f32, int_arm_neon_vrecpe>;
4095 // VRECPS : Vector Reciprocal Step
4096 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4097 IIC_VRECSD, "vrecps", "f32",
4098 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4099 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4100 IIC_VRECSQ, "vrecps", "f32",
4101 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4103 // VRSQRTE : Vector Reciprocal Square Root Estimate
4104 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4105 IIC_VUNAD, "vrsqrte", "u32",
4106 v2i32, v2i32, int_arm_neon_vrsqrte>;
4107 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4108 IIC_VUNAQ, "vrsqrte", "u32",
4109 v4i32, v4i32, int_arm_neon_vrsqrte>;
4110 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4111 IIC_VUNAD, "vrsqrte", "f32",
4112 v2f32, v2f32, int_arm_neon_vrsqrte>;
4113 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4114 IIC_VUNAQ, "vrsqrte", "f32",
4115 v4f32, v4f32, int_arm_neon_vrsqrte>;
4117 // VRSQRTS : Vector Reciprocal Square Root Step
4118 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4119 IIC_VRECSD, "vrsqrts", "f32",
4120 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4121 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4122 IIC_VRECSQ, "vrsqrts", "f32",
4123 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4127 // VSHL : Vector Shift
4128 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4129 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4130 "vshl", "s", int_arm_neon_vshifts>;
4131 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4132 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4133 "vshl", "u", int_arm_neon_vshiftu>;
4135 // VSHL : Vector Shift Left (Immediate)
4136 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4138 // VSHR : Vector Shift Right (Immediate)
4139 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4140 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4142 // VSHLL : Vector Shift Left Long
4143 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4144 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4146 // VSHLL : Vector Shift Left Long (with maximum shift count)
4147 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4148 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4149 ValueType OpTy, SDNode OpNode>
4150 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4151 ResTy, OpTy, OpNode> {
4152 let Inst{21-16} = op21_16;
4153 let DecoderMethod = "DecodeVSHLMaxInstruction";
4155 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4156 v8i16, v8i8, NEONvshlli>;
4157 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4158 v4i32, v4i16, NEONvshlli>;
4159 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4160 v2i64, v2i32, NEONvshlli>;
4162 // VSHRN : Vector Shift Right and Narrow
4163 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4166 // VRSHL : Vector Rounding Shift
4167 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4168 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4169 "vrshl", "s", int_arm_neon_vrshifts>;
4170 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4171 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4172 "vrshl", "u", int_arm_neon_vrshiftu>;
4173 // VRSHR : Vector Rounding Shift Right
4174 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4175 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4177 // VRSHRN : Vector Rounding Shift Right and Narrow
4178 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4181 // VQSHL : Vector Saturating Shift
4182 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4183 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4184 "vqshl", "s", int_arm_neon_vqshifts>;
4185 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4186 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4187 "vqshl", "u", int_arm_neon_vqshiftu>;
4188 // VQSHL : Vector Saturating Shift Left (Immediate)
4189 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4190 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4192 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4193 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4195 // VQSHRN : Vector Saturating Shift Right and Narrow
4196 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4198 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4201 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4202 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4205 // VQRSHL : Vector Saturating Rounding Shift
4206 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4207 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4208 "vqrshl", "s", int_arm_neon_vqrshifts>;
4209 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4210 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4211 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4213 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4214 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4216 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4219 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4220 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4223 // VSRA : Vector Shift Right and Accumulate
4224 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4225 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4226 // VRSRA : Vector Rounding Shift Right and Accumulate
4227 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4228 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4230 // VSLI : Vector Shift Left and Insert
4231 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4233 // VSRI : Vector Shift Right and Insert
4234 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4236 // Vector Absolute and Saturating Absolute.
4238 // VABS : Vector Absolute Value
4239 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4240 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4242 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4243 IIC_VUNAD, "vabs", "f32",
4244 v2f32, v2f32, int_arm_neon_vabs>;
4245 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4246 IIC_VUNAQ, "vabs", "f32",
4247 v4f32, v4f32, int_arm_neon_vabs>;
4249 // VQABS : Vector Saturating Absolute Value
4250 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4251 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4252 int_arm_neon_vqabs>;
4256 def vnegd : PatFrag<(ops node:$in),
4257 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4258 def vnegq : PatFrag<(ops node:$in),
4259 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4261 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4262 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4263 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4264 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4265 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4266 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4267 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4268 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4270 // VNEG : Vector Negate (integer)
4271 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4272 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4273 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4274 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4275 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4276 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4278 // VNEG : Vector Negate (floating-point)
4279 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4280 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4281 "vneg", "f32", "$Vd, $Vm", "",
4282 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4283 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4284 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4285 "vneg", "f32", "$Vd, $Vm", "",
4286 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4288 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4289 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4290 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4291 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4292 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4293 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4295 // VQNEG : Vector Saturating Negate
4296 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4297 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4298 int_arm_neon_vqneg>;
4300 // Vector Bit Counting Operations.
4302 // VCLS : Vector Count Leading Sign Bits
4303 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4304 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4306 // VCLZ : Vector Count Leading Zeros
4307 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4308 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4310 // VCNT : Vector Count One Bits
4311 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4312 IIC_VCNTiD, "vcnt", "8",
4313 v8i8, v8i8, int_arm_neon_vcnt>;
4314 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4315 IIC_VCNTiQ, "vcnt", "8",
4316 v16i8, v16i8, int_arm_neon_vcnt>;
4318 // Vector Swap -- for disassembly only.
4319 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4320 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4321 "vswp", "$Vd, $Vm", "", []>;
4322 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4323 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4324 "vswp", "$Vd, $Vm", "", []>;
4326 // Vector Move Operations.
4328 // VMOV : Vector Move (Register)
4329 def : InstAlias<"vmov${p} $Vd, $Vm",
4330 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4331 def : InstAlias<"vmov${p} $Vd, $Vm",
4332 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4334 // VMOV : Vector Move (Immediate)
4336 let isReMaterializable = 1 in {
4337 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4338 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4339 "vmov", "i8", "$Vd, $SIMM", "",
4340 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4341 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4342 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4343 "vmov", "i8", "$Vd, $SIMM", "",
4344 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4346 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4347 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4348 "vmov", "i16", "$Vd, $SIMM", "",
4349 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4350 let Inst{9} = SIMM{9};
4353 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4354 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4355 "vmov", "i16", "$Vd, $SIMM", "",
4356 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4357 let Inst{9} = SIMM{9};
4360 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4361 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4362 "vmov", "i32", "$Vd, $SIMM", "",
4363 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4364 let Inst{11-8} = SIMM{11-8};
4367 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4368 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4369 "vmov", "i32", "$Vd, $SIMM", "",
4370 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4371 let Inst{11-8} = SIMM{11-8};
4374 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4375 (ins nModImm:$SIMM), IIC_VMOVImm,
4376 "vmov", "i64", "$Vd, $SIMM", "",
4377 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4378 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4379 (ins nModImm:$SIMM), IIC_VMOVImm,
4380 "vmov", "i64", "$Vd, $SIMM", "",
4381 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4382 } // isReMaterializable
4384 // VMOV : Vector Get Lane (move scalar to ARM core register)
4386 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4387 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4388 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4389 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4391 let Inst{21} = lane{2};
4392 let Inst{6-5} = lane{1-0};
4394 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4395 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4396 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4397 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4399 let Inst{21} = lane{1};
4400 let Inst{6} = lane{0};
4402 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4403 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4404 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4405 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4407 let Inst{21} = lane{2};
4408 let Inst{6-5} = lane{1-0};
4410 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4411 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4412 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4413 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4415 let Inst{21} = lane{1};
4416 let Inst{6} = lane{0};
4418 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4419 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4420 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4421 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4423 let Inst{21} = lane{0};
4425 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4426 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4427 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4428 (DSubReg_i8_reg imm:$lane))),
4429 (SubReg_i8_lane imm:$lane))>;
4430 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4431 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4432 (DSubReg_i16_reg imm:$lane))),
4433 (SubReg_i16_lane imm:$lane))>;
4434 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4435 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4436 (DSubReg_i8_reg imm:$lane))),
4437 (SubReg_i8_lane imm:$lane))>;
4438 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4439 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4440 (DSubReg_i16_reg imm:$lane))),
4441 (SubReg_i16_lane imm:$lane))>;
4442 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4443 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4444 (DSubReg_i32_reg imm:$lane))),
4445 (SubReg_i32_lane imm:$lane))>;
4446 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4447 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4448 (SSubReg_f32_reg imm:$src2))>;
4449 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4450 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4451 (SSubReg_f32_reg imm:$src2))>;
4452 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4453 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4454 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4455 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4458 // VMOV : Vector Set Lane (move ARM core register to scalar)
4460 let Constraints = "$src1 = $V" in {
4461 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4462 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4463 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4464 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4465 GPR:$R, imm:$lane))]> {
4466 let Inst{21} = lane{2};
4467 let Inst{6-5} = lane{1-0};
4469 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4470 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4471 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4472 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4473 GPR:$R, imm:$lane))]> {
4474 let Inst{21} = lane{1};
4475 let Inst{6} = lane{0};
4477 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4478 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4479 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4480 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4481 GPR:$R, imm:$lane))]> {
4482 let Inst{21} = lane{0};
4485 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4486 (v16i8 (INSERT_SUBREG QPR:$src1,
4487 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4488 (DSubReg_i8_reg imm:$lane))),
4489 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4490 (DSubReg_i8_reg imm:$lane)))>;
4491 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4492 (v8i16 (INSERT_SUBREG QPR:$src1,
4493 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4494 (DSubReg_i16_reg imm:$lane))),
4495 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4496 (DSubReg_i16_reg imm:$lane)))>;
4497 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4498 (v4i32 (INSERT_SUBREG QPR:$src1,
4499 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4500 (DSubReg_i32_reg imm:$lane))),
4501 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4502 (DSubReg_i32_reg imm:$lane)))>;
4504 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4505 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4506 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4507 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4508 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4509 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4511 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4512 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4513 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4514 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4516 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4517 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4518 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4519 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4520 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4521 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4523 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4524 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4525 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4526 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4527 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4528 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4530 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4531 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4532 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4534 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4535 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4536 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4538 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4539 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4540 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4543 // VDUP : Vector Duplicate (from ARM core register to all elements)
4545 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4546 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4547 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4548 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4549 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4550 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4551 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4552 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4554 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4555 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4556 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4557 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4558 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4559 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4561 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4562 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4564 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4566 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4567 ValueType Ty, Operand IdxTy>
4568 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4569 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4570 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4572 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4573 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4574 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4575 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4576 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4577 VectorIndex32:$lane)))]>;
4579 // Inst{19-16} is partially specified depending on the element size.
4581 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4583 let Inst{19-17} = lane{2-0};
4585 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4587 let Inst{19-18} = lane{1-0};
4589 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4591 let Inst{19} = lane{0};
4593 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4595 let Inst{19-17} = lane{2-0};
4597 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4599 let Inst{19-18} = lane{1-0};
4601 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4603 let Inst{19} = lane{0};
4606 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4607 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4609 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4610 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4612 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4613 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4614 (DSubReg_i8_reg imm:$lane))),
4615 (SubReg_i8_lane imm:$lane)))>;
4616 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4617 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4618 (DSubReg_i16_reg imm:$lane))),
4619 (SubReg_i16_lane imm:$lane)))>;
4620 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4621 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4622 (DSubReg_i32_reg imm:$lane))),
4623 (SubReg_i32_lane imm:$lane)))>;
4624 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4625 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4626 (DSubReg_i32_reg imm:$lane))),
4627 (SubReg_i32_lane imm:$lane)))>;
4629 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4630 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4631 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4632 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4634 // VMOVN : Vector Narrowing Move
4635 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4636 "vmovn", "i", trunc>;
4637 // VQMOVN : Vector Saturating Narrowing Move
4638 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4639 "vqmovn", "s", int_arm_neon_vqmovns>;
4640 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4641 "vqmovn", "u", int_arm_neon_vqmovnu>;
4642 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4643 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4644 // VMOVL : Vector Lengthening Move
4645 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4646 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4648 // Vector Conversions.
4650 // VCVT : Vector Convert Between Floating-Point and Integers
4651 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4652 v2i32, v2f32, fp_to_sint>;
4653 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4654 v2i32, v2f32, fp_to_uint>;
4655 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4656 v2f32, v2i32, sint_to_fp>;
4657 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4658 v2f32, v2i32, uint_to_fp>;
4660 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4661 v4i32, v4f32, fp_to_sint>;
4662 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4663 v4i32, v4f32, fp_to_uint>;
4664 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4665 v4f32, v4i32, sint_to_fp>;
4666 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4667 v4f32, v4i32, uint_to_fp>;
4669 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4670 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4671 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4672 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4673 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4674 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4675 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4676 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4677 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4679 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4680 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4681 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4682 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4683 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4684 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4685 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4686 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4688 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4689 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4690 IIC_VUNAQ, "vcvt", "f16.f32",
4691 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4692 Requires<[HasNEON, HasFP16]>;
4693 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4694 IIC_VUNAQ, "vcvt", "f32.f16",
4695 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4696 Requires<[HasNEON, HasFP16]>;
4700 // VREV64 : Vector Reverse elements within 64-bit doublewords
4702 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4703 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4704 (ins DPR:$Vm), IIC_VMOVD,
4705 OpcodeStr, Dt, "$Vd, $Vm", "",
4706 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4707 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4708 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4709 (ins QPR:$Vm), IIC_VMOVQ,
4710 OpcodeStr, Dt, "$Vd, $Vm", "",
4711 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4713 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4714 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4715 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4716 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4718 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4719 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4720 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4721 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4723 // VREV32 : Vector Reverse elements within 32-bit words
4725 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4726 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4727 (ins DPR:$Vm), IIC_VMOVD,
4728 OpcodeStr, Dt, "$Vd, $Vm", "",
4729 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4730 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4731 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4732 (ins QPR:$Vm), IIC_VMOVQ,
4733 OpcodeStr, Dt, "$Vd, $Vm", "",
4734 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4736 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4737 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4739 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4740 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4742 // VREV16 : Vector Reverse elements within 16-bit halfwords
4744 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4745 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4746 (ins DPR:$Vm), IIC_VMOVD,
4747 OpcodeStr, Dt, "$Vd, $Vm", "",
4748 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4749 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4750 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4751 (ins QPR:$Vm), IIC_VMOVQ,
4752 OpcodeStr, Dt, "$Vd, $Vm", "",
4753 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4755 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4756 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4758 // Other Vector Shuffles.
4760 // Aligned extractions: really just dropping registers
4762 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4763 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4764 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4766 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4768 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4770 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4772 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4774 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4777 // VEXT : Vector Extract
4779 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4780 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4781 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4782 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4783 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4784 (Ty DPR:$Vm), imm:$index)))]> {
4786 let Inst{11-8} = index{3-0};
4789 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4790 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4791 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4792 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4793 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4794 (Ty QPR:$Vm), imm:$index)))]> {
4796 let Inst{11-8} = index{3-0};
4799 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4800 let Inst{11-8} = index{3-0};
4802 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4803 let Inst{11-9} = index{2-0};
4806 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4807 let Inst{11-10} = index{1-0};
4808 let Inst{9-8} = 0b00;
4810 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4813 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4815 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4816 let Inst{11-8} = index{3-0};
4818 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4819 let Inst{11-9} = index{2-0};
4822 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4823 let Inst{11-10} = index{1-0};
4824 let Inst{9-8} = 0b00;
4826 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4829 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4831 // VTRN : Vector Transpose
4833 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4834 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4835 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4837 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4838 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4839 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4841 // VUZP : Vector Unzip (Deinterleave)
4843 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4844 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4845 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4847 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4848 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4849 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4851 // VZIP : Vector Zip (Interleave)
4853 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4854 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4855 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4857 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4858 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4859 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4861 // Vector Table Lookup and Table Extension.
4863 // VTBL : Vector Table Lookup
4864 let DecoderMethod = "DecodeTBLInstruction" in {
4866 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4867 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4868 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4869 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4870 let hasExtraSrcRegAllocReq = 1 in {
4872 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4873 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4874 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4876 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4877 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4878 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4880 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4881 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4883 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4884 } // hasExtraSrcRegAllocReq = 1
4887 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4889 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4891 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4893 // VTBX : Vector Table Extension
4895 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4896 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4897 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4898 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4899 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4900 let hasExtraSrcRegAllocReq = 1 in {
4902 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4903 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4904 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4906 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4907 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4908 NVTBLFrm, IIC_VTBX3,
4909 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4912 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4913 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4914 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4916 } // hasExtraSrcRegAllocReq = 1
4919 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4920 IIC_VTBX2, "$orig = $dst", []>;
4922 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4923 IIC_VTBX3, "$orig = $dst", []>;
4925 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4926 IIC_VTBX4, "$orig = $dst", []>;
4927 } // DecoderMethod = "DecodeTBLInstruction"
4929 //===----------------------------------------------------------------------===//
4930 // NEON instructions for single-precision FP math
4931 //===----------------------------------------------------------------------===//
4933 class N2VSPat<SDNode OpNode, NeonI Inst>
4934 : NEONFPPat<(f32 (OpNode SPR:$a)),
4936 (v2f32 (COPY_TO_REGCLASS (Inst
4938 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4939 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4941 class N3VSPat<SDNode OpNode, NeonI Inst>
4942 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4944 (v2f32 (COPY_TO_REGCLASS (Inst
4946 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4949 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4950 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4952 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4953 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4955 (v2f32 (COPY_TO_REGCLASS (Inst
4957 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4960 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4963 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4964 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4966 def : N3VSPat<fadd, VADDfd>;
4967 def : N3VSPat<fsub, VSUBfd>;
4968 def : N3VSPat<fmul, VMULfd>;
4969 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4970 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4971 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4972 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4973 def : N2VSPat<fabs, VABSfd>;
4974 def : N2VSPat<fneg, VNEGfd>;
4975 def : N3VSPat<NEONfmax, VMAXfd>;
4976 def : N3VSPat<NEONfmin, VMINfd>;
4977 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4978 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4979 def : N2VSPat<arm_sitof, VCVTs2fd>;
4980 def : N2VSPat<arm_uitof, VCVTu2fd>;
4982 //===----------------------------------------------------------------------===//
4983 // Non-Instruction Patterns
4984 //===----------------------------------------------------------------------===//
4987 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4988 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4989 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4990 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4991 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4992 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4993 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4994 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4995 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4996 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4997 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4998 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4999 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5000 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5001 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5002 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5003 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5004 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5005 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5006 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5007 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5008 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5009 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5010 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5011 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5012 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5013 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5014 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5015 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5016 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5018 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5019 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5020 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5021 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5022 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5023 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5024 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5025 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5026 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5027 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5028 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5029 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5030 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5031 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5032 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5033 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5034 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5035 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5036 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5037 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5038 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5039 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5040 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5041 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5042 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5043 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5044 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5045 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5046 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5047 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;