1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
43 def nImmSplatI64 : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmSplatI64AsmOperand;
48 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
49 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
50 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
51 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
52 return ((uint64_t)Imm) < 8;
54 let ParserMatchClass = VectorIndex8Operand;
55 let PrintMethod = "printVectorIndex";
56 let MIOperandInfo = (ops i32imm);
58 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
59 return ((uint64_t)Imm) < 4;
61 let ParserMatchClass = VectorIndex16Operand;
62 let PrintMethod = "printVectorIndex";
63 let MIOperandInfo = (ops i32imm);
65 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
66 return ((uint64_t)Imm) < 2;
68 let ParserMatchClass = VectorIndex32Operand;
69 let PrintMethod = "printVectorIndex";
70 let MIOperandInfo = (ops i32imm);
73 def VecListOneDAsmOperand : AsmOperandClass {
74 let Name = "VecListOneD";
75 let ParserMethod = "parseVectorList";
77 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
78 let ParserMatchClass = VecListOneDAsmOperand;
80 // Register list of two sequential D registers.
81 def VecListTwoDAsmOperand : AsmOperandClass {
82 let Name = "VecListTwoD";
83 let ParserMethod = "parseVectorList";
85 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
86 let ParserMatchClass = VecListTwoDAsmOperand;
88 // Register list of three sequential D registers.
89 def VecListThreeDAsmOperand : AsmOperandClass {
90 let Name = "VecListThreeD";
91 let ParserMethod = "parseVectorList";
93 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
94 let ParserMatchClass = VecListThreeDAsmOperand;
96 // Register list of four sequential D registers.
97 def VecListFourDAsmOperand : AsmOperandClass {
98 let Name = "VecListFourD";
99 let ParserMethod = "parseVectorList";
101 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
102 let ParserMatchClass = VecListFourDAsmOperand;
104 // Register list of two D registers spaced by 2 (two sequential Q registers).
105 def VecListTwoQAsmOperand : AsmOperandClass {
106 let Name = "VecListTwoQ";
107 let ParserMethod = "parseVectorList";
109 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
110 let ParserMatchClass = VecListTwoQAsmOperand;
113 //===----------------------------------------------------------------------===//
114 // NEON-specific DAG Nodes.
115 //===----------------------------------------------------------------------===//
117 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
118 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
120 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
121 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
122 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
123 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
124 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
125 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
126 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
127 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
128 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
129 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
130 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
132 // Types for vector shift by immediates. The "SHX" version is for long and
133 // narrow operations where the source and destination vectors have different
134 // types. The "SHINS" version is for shift and insert operations.
135 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
137 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
139 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
140 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
142 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
143 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
144 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
145 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
146 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
147 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
148 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
150 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
151 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
152 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
154 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
155 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
156 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
157 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
158 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
159 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
161 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
162 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
163 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
165 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
166 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
168 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
170 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
171 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
173 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
174 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
175 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
177 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
179 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
180 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
182 def NEONvbsl : SDNode<"ARMISD::VBSL",
183 SDTypeProfile<1, 3, [SDTCisVec<0>,
186 SDTCisSameAs<0, 3>]>>;
188 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
190 // VDUPLANE can produce a quad-register result from a double-register source,
191 // so the result is not constrained to match the source.
192 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
193 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
196 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
197 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
198 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
200 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
201 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
202 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
203 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
205 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
207 SDTCisSameAs<0, 3>]>;
208 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
209 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
210 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
212 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
213 SDTCisSameAs<1, 2>]>;
214 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
215 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
217 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
218 SDTCisSameAs<0, 2>]>;
219 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
220 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
222 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
223 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
224 unsigned EltBits = 0;
225 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
226 return (EltBits == 32 && EltVal == 0);
229 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
230 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
231 unsigned EltBits = 0;
232 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
233 return (EltBits == 8 && EltVal == 0xff);
236 //===----------------------------------------------------------------------===//
237 // NEON load / store instructions
238 //===----------------------------------------------------------------------===//
240 // Use VLDM to load a Q register as a D register pair.
241 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
243 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
245 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
247 // Use VSTM to store a Q register as a D register pair.
248 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
250 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
252 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
254 // Classes for VLD* pseudo-instructions with multi-register operands.
255 // These are expanded to real instructions after register allocation.
256 class VLDQPseudo<InstrItinClass itin>
257 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
258 class VLDQWBPseudo<InstrItinClass itin>
259 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
260 (ins addrmode6:$addr, am6offset:$offset), itin,
262 class VLDQWBfixedPseudo<InstrItinClass itin>
263 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
264 (ins addrmode6:$addr), itin,
266 class VLDQWBregisterPseudo<InstrItinClass itin>
267 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
268 (ins addrmode6:$addr, rGPR:$offset), itin,
270 class VLDQQPseudo<InstrItinClass itin>
271 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
272 class VLDQQWBPseudo<InstrItinClass itin>
273 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
274 (ins addrmode6:$addr, am6offset:$offset), itin,
276 class VLDQQQQPseudo<InstrItinClass itin>
277 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
279 class VLDQQQQWBPseudo<InstrItinClass itin>
280 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
281 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
282 "$addr.addr = $wb, $src = $dst">;
284 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
286 // VLD1 : Vector Load (multiple single elements)
287 class VLD1D<bits<4> op7_4, string Dt>
288 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
289 (ins addrmode6:$Rn), IIC_VLD1,
290 "vld1", Dt, "$Vd, $Rn", "", []> {
293 let DecoderMethod = "DecodeVLDInstruction";
295 class VLD1Q<bits<4> op7_4, string Dt>
296 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
297 (ins addrmode6:$Rn), IIC_VLD1x2,
298 "vld1", Dt, "$Vd, $Rn", "", []> {
300 let Inst{5-4} = Rn{5-4};
301 let DecoderMethod = "DecodeVLDInstruction";
304 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
305 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
306 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
307 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
309 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
310 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
311 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
312 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
314 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
315 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
316 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
317 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
319 // ...with address register writeback:
320 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
321 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
322 (ins addrmode6:$Rn), IIC_VLD1u,
323 "vld1", Dt, "$Vd, $Rn!",
324 "$Rn.addr = $wb", []> {
325 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
327 let DecoderMethod = "DecodeVLDInstruction";
328 let AsmMatchConverter = "cvtVLDwbFixed";
330 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
331 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
332 "vld1", Dt, "$Vd, $Rn, $Rm",
333 "$Rn.addr = $wb", []> {
335 let DecoderMethod = "DecodeVLDInstruction";
336 let AsmMatchConverter = "cvtVLDwbRegister";
339 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
340 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
341 (ins addrmode6:$Rn), IIC_VLD1x2u,
342 "vld1", Dt, "$Vd, $Rn!",
343 "$Rn.addr = $wb", []> {
344 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
345 let Inst{5-4} = Rn{5-4};
346 let DecoderMethod = "DecodeVLDInstruction";
347 let AsmMatchConverter = "cvtVLDwbFixed";
349 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
350 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
351 "vld1", Dt, "$Vd, $Rn, $Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
354 let DecoderMethod = "DecodeVLDInstruction";
355 let AsmMatchConverter = "cvtVLDwbRegister";
359 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
360 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
361 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
362 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
363 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
364 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
365 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
366 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
368 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
369 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
370 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
371 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
372 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
373 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
374 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
375 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
377 // ...with 3 registers
378 class VLD1D3<bits<4> op7_4, string Dt>
379 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
380 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
381 "$Vd, $Rn", "", []> {
384 let DecoderMethod = "DecodeVLDInstruction";
386 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
387 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
388 (ins addrmode6:$Rn), IIC_VLD1x2u,
389 "vld1", Dt, "$Vd, $Rn!",
390 "$Rn.addr = $wb", []> {
391 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
393 let DecoderMethod = "DecodeVLDInstruction";
394 let AsmMatchConverter = "cvtVLDwbFixed";
396 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
397 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
398 "vld1", Dt, "$Vd, $Rn, $Rm",
399 "$Rn.addr = $wb", []> {
401 let DecoderMethod = "DecodeVLDInstruction";
402 let AsmMatchConverter = "cvtVLDwbRegister";
406 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
407 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
408 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
409 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
411 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
412 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
413 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
414 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
416 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
418 // ...with 4 registers
419 class VLD1D4<bits<4> op7_4, string Dt>
420 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
421 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
422 "$Vd, $Rn", "", []> {
424 let Inst{5-4} = Rn{5-4};
425 let DecoderMethod = "DecodeVLDInstruction";
427 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
428 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
429 (ins addrmode6:$Rn), IIC_VLD1x2u,
430 "vld1", Dt, "$Vd, $Rn!",
431 "$Rn.addr = $wb", []> {
432 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
433 let Inst{5-4} = Rn{5-4};
434 let DecoderMethod = "DecodeVLDInstruction";
435 let AsmMatchConverter = "cvtVLDwbFixed";
437 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
438 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
439 "vld1", Dt, "$Vd, $Rn, $Rm",
440 "$Rn.addr = $wb", []> {
441 let Inst{5-4} = Rn{5-4};
442 let DecoderMethod = "DecodeVLDInstruction";
443 let AsmMatchConverter = "cvtVLDwbRegister";
447 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
448 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
449 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
450 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
452 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
453 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
454 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
455 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
457 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
459 // VLD2 : Vector Load (multiple 2-element structures)
460 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
461 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
462 (ins addrmode6:$Rn), IIC_VLD2,
463 "vld2", Dt, "$Vd, $Rn", "", []> {
465 let Inst{5-4} = Rn{5-4};
466 let DecoderMethod = "DecodeVLDInstruction";
468 class VLD2Q<bits<4> op7_4, string Dt, RegisterOperand VdTy>
469 : NLdSt<0, 0b10, 0b0011, op7_4,
471 (ins addrmode6:$Rn), IIC_VLD2x2,
472 "vld2", Dt, "$Vd, $Rn", "", []> {
474 let Inst{5-4} = Rn{5-4};
475 let DecoderMethod = "DecodeVLDInstruction";
478 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
479 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
480 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
482 def VLD2q8 : VLD2Q<{0,0,?,?}, "8", VecListFourD>;
483 def VLD2q16 : VLD2Q<{0,1,?,?}, "16", VecListFourD>;
484 def VLD2q32 : VLD2Q<{1,0,?,?}, "32", VecListFourD>;
486 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
487 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
488 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
490 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
491 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
492 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
494 // ...with address register writeback:
495 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
496 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
497 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
498 "vld2", Dt, "$Vd, $Rn$Rm",
499 "$Rn.addr = $wb", []> {
500 let Inst{5-4} = Rn{5-4};
501 let DecoderMethod = "DecodeVLDInstruction";
503 class VLD2QWB<bits<4> op7_4, string Dt, RegisterOperand VdTy>
504 : NLdSt<0, 0b10, 0b0011, op7_4,
505 (outs VdTy:$Vd, GPR:$wb),
506 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
507 "vld2", Dt, "$Vd, $Rn$Rm",
508 "$Rn.addr = $wb", []> {
509 let Inst{5-4} = Rn{5-4};
510 let DecoderMethod = "DecodeVLDInstruction";
513 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
514 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
515 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
517 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8", VecListFourD>;
518 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16", VecListFourD>;
519 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32", VecListFourD>;
521 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
522 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
523 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
525 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
526 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
527 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
529 // ...with double-spaced registers
530 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
531 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
532 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
533 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
534 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
535 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
537 // VLD3 : Vector Load (multiple 3-element structures)
538 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
539 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
540 (ins addrmode6:$Rn), IIC_VLD3,
541 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
544 let DecoderMethod = "DecodeVLDInstruction";
547 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
548 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
549 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
551 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
552 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
553 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
555 // ...with address register writeback:
556 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b10, op11_8, op7_4,
558 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
559 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
560 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
561 "$Rn.addr = $wb", []> {
563 let DecoderMethod = "DecodeVLDInstruction";
566 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
567 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
568 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
570 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
571 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
572 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
574 // ...with double-spaced registers:
575 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
576 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
577 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
578 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
579 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
580 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
582 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
583 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
584 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
586 // ...alternate versions to be allocated odd register numbers:
587 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
588 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
589 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
591 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
592 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
593 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
595 // VLD4 : Vector Load (multiple 4-element structures)
596 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
597 : NLdSt<0, 0b10, op11_8, op7_4,
598 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
599 (ins addrmode6:$Rn), IIC_VLD4,
600 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
602 let Inst{5-4} = Rn{5-4};
603 let DecoderMethod = "DecodeVLDInstruction";
606 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
607 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
608 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
610 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
611 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
612 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
614 // ...with address register writeback:
615 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
616 : NLdSt<0, 0b10, op11_8, op7_4,
617 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
618 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
619 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
620 "$Rn.addr = $wb", []> {
621 let Inst{5-4} = Rn{5-4};
622 let DecoderMethod = "DecodeVLDInstruction";
625 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
626 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
627 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
629 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
630 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
631 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
633 // ...with double-spaced registers:
634 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
635 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
636 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
637 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
638 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
639 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
641 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
642 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
643 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
645 // ...alternate versions to be allocated odd register numbers:
646 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
647 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
648 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
650 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
651 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
652 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
654 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
656 // Classes for VLD*LN pseudo-instructions with multi-register operands.
657 // These are expanded to real instructions after register allocation.
658 class VLDQLNPseudo<InstrItinClass itin>
659 : PseudoNLdSt<(outs QPR:$dst),
660 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
661 itin, "$src = $dst">;
662 class VLDQLNWBPseudo<InstrItinClass itin>
663 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
664 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
665 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
666 class VLDQQLNPseudo<InstrItinClass itin>
667 : PseudoNLdSt<(outs QQPR:$dst),
668 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
669 itin, "$src = $dst">;
670 class VLDQQLNWBPseudo<InstrItinClass itin>
671 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
672 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
673 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
674 class VLDQQQQLNPseudo<InstrItinClass itin>
675 : PseudoNLdSt<(outs QQQQPR:$dst),
676 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
677 itin, "$src = $dst">;
678 class VLDQQQQLNWBPseudo<InstrItinClass itin>
679 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
681 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
683 // VLD1LN : Vector Load (single element to one lane)
684 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
686 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
687 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
688 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
690 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
691 (i32 (LoadOp addrmode6:$Rn)),
694 let DecoderMethod = "DecodeVLD1LN";
696 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
698 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
699 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
700 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
702 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
703 (i32 (LoadOp addrmode6oneL32:$Rn)),
706 let DecoderMethod = "DecodeVLD1LN";
708 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
709 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
710 (i32 (LoadOp addrmode6:$addr)),
714 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
715 let Inst{7-5} = lane{2-0};
717 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
718 let Inst{7-6} = lane{1-0};
721 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
722 let Inst{7} = lane{0};
727 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
728 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
729 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
731 def : Pat<(vector_insert (v2f32 DPR:$src),
732 (f32 (load addrmode6:$addr)), imm:$lane),
733 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
734 def : Pat<(vector_insert (v4f32 QPR:$src),
735 (f32 (load addrmode6:$addr)), imm:$lane),
736 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
738 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
740 // ...with address register writeback:
741 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
742 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
743 (ins addrmode6:$Rn, am6offset:$Rm,
744 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
745 "\\{$Vd[$lane]\\}, $Rn$Rm",
746 "$src = $Vd, $Rn.addr = $wb", []> {
747 let DecoderMethod = "DecodeVLD1LN";
750 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
751 let Inst{7-5} = lane{2-0};
753 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
754 let Inst{7-6} = lane{1-0};
757 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
758 let Inst{7} = lane{0};
763 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
764 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
765 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
767 // VLD2LN : Vector Load (single 2-element structure to one lane)
768 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
769 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
770 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
771 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
772 "$src1 = $Vd, $src2 = $dst2", []> {
775 let DecoderMethod = "DecodeVLD2LN";
778 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
779 let Inst{7-5} = lane{2-0};
781 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
782 let Inst{7-6} = lane{1-0};
784 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
785 let Inst{7} = lane{0};
788 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
789 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
790 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
792 // ...with double-spaced registers:
793 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
794 let Inst{7-6} = lane{1-0};
796 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
797 let Inst{7} = lane{0};
800 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
801 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
803 // ...with address register writeback:
804 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
805 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
806 (ins addrmode6:$Rn, am6offset:$Rm,
807 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
808 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
809 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
811 let DecoderMethod = "DecodeVLD2LN";
814 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
815 let Inst{7-5} = lane{2-0};
817 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
818 let Inst{7-6} = lane{1-0};
820 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
821 let Inst{7} = lane{0};
824 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
825 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
826 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
828 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
829 let Inst{7-6} = lane{1-0};
831 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
832 let Inst{7} = lane{0};
835 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
836 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
838 // VLD3LN : Vector Load (single 3-element structure to one lane)
839 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
840 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
841 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
842 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
843 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
844 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
846 let DecoderMethod = "DecodeVLD3LN";
849 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
850 let Inst{7-5} = lane{2-0};
852 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
853 let Inst{7-6} = lane{1-0};
855 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
856 let Inst{7} = lane{0};
859 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
860 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
861 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
863 // ...with double-spaced registers:
864 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
865 let Inst{7-6} = lane{1-0};
867 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
868 let Inst{7} = lane{0};
871 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
872 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
874 // ...with address register writeback:
875 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
876 : NLdStLn<1, 0b10, op11_8, op7_4,
877 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
878 (ins addrmode6:$Rn, am6offset:$Rm,
879 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
880 IIC_VLD3lnu, "vld3", Dt,
881 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
882 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
884 let DecoderMethod = "DecodeVLD3LN";
887 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
888 let Inst{7-5} = lane{2-0};
890 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
891 let Inst{7-6} = lane{1-0};
893 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
894 let Inst{7} = lane{0};
897 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
898 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
899 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
901 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
902 let Inst{7-6} = lane{1-0};
904 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
905 let Inst{7} = lane{0};
908 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
909 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
911 // VLD4LN : Vector Load (single 4-element structure to one lane)
912 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
913 : NLdStLn<1, 0b10, op11_8, op7_4,
914 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
915 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
916 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
917 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
918 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
921 let DecoderMethod = "DecodeVLD4LN";
924 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
925 let Inst{7-5} = lane{2-0};
927 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
928 let Inst{7-6} = lane{1-0};
930 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
931 let Inst{7} = lane{0};
935 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
936 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
937 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
939 // ...with double-spaced registers:
940 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
941 let Inst{7-6} = lane{1-0};
943 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
944 let Inst{7} = lane{0};
948 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
949 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
951 // ...with address register writeback:
952 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
953 : NLdStLn<1, 0b10, op11_8, op7_4,
954 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
955 (ins addrmode6:$Rn, am6offset:$Rm,
956 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
957 IIC_VLD4lnu, "vld4", Dt,
958 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
959 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
962 let DecoderMethod = "DecodeVLD4LN" ;
965 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
966 let Inst{7-5} = lane{2-0};
968 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
969 let Inst{7-6} = lane{1-0};
971 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
972 let Inst{7} = lane{0};
976 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
977 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
978 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
980 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
981 let Inst{7-6} = lane{1-0};
983 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
984 let Inst{7} = lane{0};
988 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
989 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
991 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
993 // VLD1DUP : Vector Load (single element to all lanes)
994 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
995 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
996 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
997 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1000 let DecoderMethod = "DecodeVLD1DupInstruction";
1002 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1003 let Pattern = [(set QPR:$dst,
1004 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1007 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1008 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1009 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1011 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1012 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1013 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1015 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1016 (VLD1DUPd32 addrmode6:$addr)>;
1017 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1018 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1020 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1022 class VLD1QDUP<bits<4> op7_4, string Dt>
1023 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
1024 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1025 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1027 let Inst{4} = Rn{4};
1028 let DecoderMethod = "DecodeVLD1DupInstruction";
1031 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1032 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1033 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1035 // ...with address register writeback:
1036 class VLD1DUPWB<bits<4> op7_4, string Dt>
1037 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
1038 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1039 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1040 let Inst{4} = Rn{4};
1041 let DecoderMethod = "DecodeVLD1DupInstruction";
1043 class VLD1QDUPWB<bits<4> op7_4, string Dt>
1044 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1045 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1046 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1047 let Inst{4} = Rn{4};
1048 let DecoderMethod = "DecodeVLD1DupInstruction";
1051 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
1052 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
1053 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
1055 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
1056 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
1057 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
1059 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1060 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1061 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1063 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1064 class VLD2DUP<bits<4> op7_4, string Dt>
1065 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
1066 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1067 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1069 let Inst{4} = Rn{4};
1070 let DecoderMethod = "DecodeVLD2DupInstruction";
1073 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
1074 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
1075 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
1077 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1078 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1079 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1081 // ...with double-spaced registers (not used for codegen):
1082 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
1083 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
1084 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1086 // ...with address register writeback:
1087 class VLD2DUPWB<bits<4> op7_4, string Dt>
1088 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1089 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1090 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1091 let Inst{4} = Rn{4};
1092 let DecoderMethod = "DecodeVLD2DupInstruction";
1095 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1096 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1097 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1099 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1100 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1101 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1103 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1104 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1105 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1107 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1108 class VLD3DUP<bits<4> op7_4, string Dt>
1109 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1110 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1111 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1114 let DecoderMethod = "DecodeVLD3DupInstruction";
1117 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1118 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1119 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1121 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1122 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1123 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1125 // ...with double-spaced registers (not used for codegen):
1126 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1127 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1128 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1130 // ...with address register writeback:
1131 class VLD3DUPWB<bits<4> op7_4, string Dt>
1132 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1133 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1134 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1135 "$Rn.addr = $wb", []> {
1137 let DecoderMethod = "DecodeVLD3DupInstruction";
1140 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1141 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1142 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1144 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1145 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1146 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1148 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1149 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1150 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1152 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1153 class VLD4DUP<bits<4> op7_4, string Dt>
1154 : NLdSt<1, 0b10, 0b1111, op7_4,
1155 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1156 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1157 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1159 let Inst{4} = Rn{4};
1160 let DecoderMethod = "DecodeVLD4DupInstruction";
1163 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1164 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1165 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1167 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1168 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1169 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1171 // ...with double-spaced registers (not used for codegen):
1172 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1173 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1174 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1176 // ...with address register writeback:
1177 class VLD4DUPWB<bits<4> op7_4, string Dt>
1178 : NLdSt<1, 0b10, 0b1111, op7_4,
1179 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1180 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1181 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1182 "$Rn.addr = $wb", []> {
1183 let Inst{4} = Rn{4};
1184 let DecoderMethod = "DecodeVLD4DupInstruction";
1187 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1188 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1189 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1191 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1192 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1193 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1195 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1196 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1197 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1199 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1201 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1203 // Classes for VST* pseudo-instructions with multi-register operands.
1204 // These are expanded to real instructions after register allocation.
1205 class VSTQPseudo<InstrItinClass itin>
1206 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1207 class VSTQWBPseudo<InstrItinClass itin>
1208 : PseudoNLdSt<(outs GPR:$wb),
1209 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1210 "$addr.addr = $wb">;
1211 class VSTQWBfixedPseudo<InstrItinClass itin>
1212 : PseudoNLdSt<(outs GPR:$wb),
1213 (ins addrmode6:$addr, QPR:$src), itin,
1214 "$addr.addr = $wb">;
1215 class VSTQWBregisterPseudo<InstrItinClass itin>
1216 : PseudoNLdSt<(outs GPR:$wb),
1217 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1218 "$addr.addr = $wb">;
1219 class VSTQQPseudo<InstrItinClass itin>
1220 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1221 class VSTQQWBPseudo<InstrItinClass itin>
1222 : PseudoNLdSt<(outs GPR:$wb),
1223 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1224 "$addr.addr = $wb">;
1225 class VSTQQQQPseudo<InstrItinClass itin>
1226 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1227 class VSTQQQQWBPseudo<InstrItinClass itin>
1228 : PseudoNLdSt<(outs GPR:$wb),
1229 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1230 "$addr.addr = $wb">;
1232 // VST1 : Vector Store (multiple single elements)
1233 class VST1D<bits<4> op7_4, string Dt>
1234 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1235 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1237 let Inst{4} = Rn{4};
1238 let DecoderMethod = "DecodeVSTInstruction";
1240 class VST1Q<bits<4> op7_4, string Dt>
1241 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1242 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1243 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1245 let Inst{5-4} = Rn{5-4};
1246 let DecoderMethod = "DecodeVSTInstruction";
1249 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1250 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1251 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1252 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1254 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1255 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1256 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1257 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1259 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1260 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1261 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1262 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1264 // ...with address register writeback:
1265 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1266 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1267 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1268 "vst1", Dt, "$Vd, $Rn!",
1269 "$Rn.addr = $wb", []> {
1270 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1271 let Inst{4} = Rn{4};
1272 let DecoderMethod = "DecodeVSTInstruction";
1273 let AsmMatchConverter = "cvtVSTwbFixed";
1275 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1276 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1278 "vst1", Dt, "$Vd, $Rn, $Rm",
1279 "$Rn.addr = $wb", []> {
1280 let Inst{4} = Rn{4};
1281 let DecoderMethod = "DecodeVSTInstruction";
1282 let AsmMatchConverter = "cvtVSTwbRegister";
1285 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1286 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1287 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1288 "vst1", Dt, "$Vd, $Rn!",
1289 "$Rn.addr = $wb", []> {
1290 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1291 let Inst{5-4} = Rn{5-4};
1292 let DecoderMethod = "DecodeVSTInstruction";
1293 let AsmMatchConverter = "cvtVSTwbFixed";
1295 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1296 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1298 "vst1", Dt, "$Vd, $Rn, $Rm",
1299 "$Rn.addr = $wb", []> {
1300 let Inst{5-4} = Rn{5-4};
1301 let DecoderMethod = "DecodeVSTInstruction";
1302 let AsmMatchConverter = "cvtVSTwbRegister";
1306 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1307 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1308 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1309 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1311 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1312 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1313 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1314 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1316 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1317 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1318 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1319 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1320 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1321 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1322 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1323 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1325 // ...with 3 registers
1326 class VST1D3<bits<4> op7_4, string Dt>
1327 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1328 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1329 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1331 let Inst{4} = Rn{4};
1332 let DecoderMethod = "DecodeVSTInstruction";
1334 class VST1D3WB<bits<4> op7_4, string Dt>
1335 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1336 (ins addrmode6:$Rn, am6offset:$Rm,
1337 DPR:$Vd, DPR:$src2, DPR:$src3),
1338 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1339 "$Rn.addr = $wb", []> {
1340 let Inst{4} = Rn{4};
1341 let DecoderMethod = "DecodeVSTInstruction";
1344 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1345 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1346 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1347 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1349 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1350 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1351 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1352 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1354 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1355 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1357 // ...with 4 registers
1358 class VST1D4<bits<4> op7_4, string Dt>
1359 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1360 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1361 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1364 let Inst{5-4} = Rn{5-4};
1365 let DecoderMethod = "DecodeVSTInstruction";
1367 class VST1D4WB<bits<4> op7_4, string Dt>
1368 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1369 (ins addrmode6:$Rn, am6offset:$Rm,
1370 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1371 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1372 "$Rn.addr = $wb", []> {
1373 let Inst{5-4} = Rn{5-4};
1374 let DecoderMethod = "DecodeVSTInstruction";
1377 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1378 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1379 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1380 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1382 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1383 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1384 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1385 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1387 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1388 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1390 // VST2 : Vector Store (multiple 2-element structures)
1391 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1392 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1393 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1394 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1396 let Inst{5-4} = Rn{5-4};
1397 let DecoderMethod = "DecodeVSTInstruction";
1399 class VST2Q<bits<4> op7_4, string Dt>
1400 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1401 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1402 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1405 let Inst{5-4} = Rn{5-4};
1406 let DecoderMethod = "DecodeVSTInstruction";
1409 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1410 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1411 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1413 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1414 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1415 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1417 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1418 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1419 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1421 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1422 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1423 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1425 // ...with address register writeback:
1426 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1427 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1428 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1429 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1430 "$Rn.addr = $wb", []> {
1431 let Inst{5-4} = Rn{5-4};
1432 let DecoderMethod = "DecodeVSTInstruction";
1434 class VST2QWB<bits<4> op7_4, string Dt>
1435 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1436 (ins addrmode6:$Rn, am6offset:$Rm,
1437 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1438 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1439 "$Rn.addr = $wb", []> {
1440 let Inst{5-4} = Rn{5-4};
1441 let DecoderMethod = "DecodeVSTInstruction";
1444 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1445 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1446 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1448 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1449 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1450 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1452 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1453 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1454 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1456 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1457 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1458 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1460 // ...with double-spaced registers
1461 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1462 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1463 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1464 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1465 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1466 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1468 // VST3 : Vector Store (multiple 3-element structures)
1469 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1470 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1471 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1472 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1474 let Inst{4} = Rn{4};
1475 let DecoderMethod = "DecodeVSTInstruction";
1478 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1479 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1480 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1482 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1483 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1484 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1486 // ...with address register writeback:
1487 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1488 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1489 (ins addrmode6:$Rn, am6offset:$Rm,
1490 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1491 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1492 "$Rn.addr = $wb", []> {
1493 let Inst{4} = Rn{4};
1494 let DecoderMethod = "DecodeVSTInstruction";
1497 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1498 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1499 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1501 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1502 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1503 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1505 // ...with double-spaced registers:
1506 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1507 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1508 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1509 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1510 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1511 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1513 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1514 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1515 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1517 // ...alternate versions to be allocated odd register numbers:
1518 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1519 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1520 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1522 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1523 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1524 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1526 // VST4 : Vector Store (multiple 4-element structures)
1527 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1528 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1529 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1530 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1533 let Inst{5-4} = Rn{5-4};
1534 let DecoderMethod = "DecodeVSTInstruction";
1537 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1538 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1539 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1541 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1542 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1543 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1545 // ...with address register writeback:
1546 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1547 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1548 (ins addrmode6:$Rn, am6offset:$Rm,
1549 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1550 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1551 "$Rn.addr = $wb", []> {
1552 let Inst{5-4} = Rn{5-4};
1553 let DecoderMethod = "DecodeVSTInstruction";
1556 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1557 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1558 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1560 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1561 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1562 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1564 // ...with double-spaced registers:
1565 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1566 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1567 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1568 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1569 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1570 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1572 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1573 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1574 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1576 // ...alternate versions to be allocated odd register numbers:
1577 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1578 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1579 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1581 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1582 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1583 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1585 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1587 // Classes for VST*LN pseudo-instructions with multi-register operands.
1588 // These are expanded to real instructions after register allocation.
1589 class VSTQLNPseudo<InstrItinClass itin>
1590 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1592 class VSTQLNWBPseudo<InstrItinClass itin>
1593 : PseudoNLdSt<(outs GPR:$wb),
1594 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1595 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1596 class VSTQQLNPseudo<InstrItinClass itin>
1597 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1599 class VSTQQLNWBPseudo<InstrItinClass itin>
1600 : PseudoNLdSt<(outs GPR:$wb),
1601 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1602 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1603 class VSTQQQQLNPseudo<InstrItinClass itin>
1604 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1606 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1607 : PseudoNLdSt<(outs GPR:$wb),
1608 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1609 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1611 // VST1LN : Vector Store (single element from one lane)
1612 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1613 PatFrag StoreOp, SDNode ExtractOp>
1614 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1615 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1616 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1617 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1619 let DecoderMethod = "DecodeVST1LN";
1621 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1622 PatFrag StoreOp, SDNode ExtractOp>
1623 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1624 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1625 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1626 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1628 let DecoderMethod = "DecodeVST1LN";
1630 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1631 : VSTQLNPseudo<IIC_VST1ln> {
1632 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1636 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1638 let Inst{7-5} = lane{2-0};
1640 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1642 let Inst{7-6} = lane{1-0};
1643 let Inst{4} = Rn{5};
1646 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1647 let Inst{7} = lane{0};
1648 let Inst{5-4} = Rn{5-4};
1651 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1652 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1653 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1655 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1656 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1657 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1658 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1660 // ...with address register writeback:
1661 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1662 PatFrag StoreOp, SDNode ExtractOp>
1663 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1664 (ins addrmode6:$Rn, am6offset:$Rm,
1665 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1666 "\\{$Vd[$lane]\\}, $Rn$Rm",
1668 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1669 addrmode6:$Rn, am6offset:$Rm))]> {
1670 let DecoderMethod = "DecodeVST1LN";
1672 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1673 : VSTQLNWBPseudo<IIC_VST1lnu> {
1674 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1675 addrmode6:$addr, am6offset:$offset))];
1678 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1680 let Inst{7-5} = lane{2-0};
1682 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1684 let Inst{7-6} = lane{1-0};
1685 let Inst{4} = Rn{5};
1687 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1689 let Inst{7} = lane{0};
1690 let Inst{5-4} = Rn{5-4};
1693 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1694 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1695 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1697 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1699 // VST2LN : Vector Store (single 2-element structure from one lane)
1700 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1701 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1702 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1703 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1706 let Inst{4} = Rn{4};
1707 let DecoderMethod = "DecodeVST2LN";
1710 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1711 let Inst{7-5} = lane{2-0};
1713 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1714 let Inst{7-6} = lane{1-0};
1716 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1717 let Inst{7} = lane{0};
1720 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1721 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1722 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1724 // ...with double-spaced registers:
1725 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1726 let Inst{7-6} = lane{1-0};
1727 let Inst{4} = Rn{4};
1729 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1730 let Inst{7} = lane{0};
1731 let Inst{4} = Rn{4};
1734 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1735 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1737 // ...with address register writeback:
1738 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1739 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1740 (ins addrmode6:$addr, am6offset:$offset,
1741 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1742 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1743 "$addr.addr = $wb", []> {
1744 let Inst{4} = Rn{4};
1745 let DecoderMethod = "DecodeVST2LN";
1748 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1749 let Inst{7-5} = lane{2-0};
1751 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1752 let Inst{7-6} = lane{1-0};
1754 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1755 let Inst{7} = lane{0};
1758 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1759 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1760 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1762 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1763 let Inst{7-6} = lane{1-0};
1765 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1766 let Inst{7} = lane{0};
1769 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1770 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1772 // VST3LN : Vector Store (single 3-element structure from one lane)
1773 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1774 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1775 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1776 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1777 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1779 let DecoderMethod = "DecodeVST3LN";
1782 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1783 let Inst{7-5} = lane{2-0};
1785 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1786 let Inst{7-6} = lane{1-0};
1788 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1789 let Inst{7} = lane{0};
1792 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1793 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1794 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1796 // ...with double-spaced registers:
1797 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1798 let Inst{7-6} = lane{1-0};
1800 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1801 let Inst{7} = lane{0};
1804 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1805 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1807 // ...with address register writeback:
1808 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1809 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1810 (ins addrmode6:$Rn, am6offset:$Rm,
1811 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1812 IIC_VST3lnu, "vst3", Dt,
1813 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1814 "$Rn.addr = $wb", []> {
1815 let DecoderMethod = "DecodeVST3LN";
1818 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1819 let Inst{7-5} = lane{2-0};
1821 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1822 let Inst{7-6} = lane{1-0};
1824 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1825 let Inst{7} = lane{0};
1828 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1829 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1830 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1832 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1833 let Inst{7-6} = lane{1-0};
1835 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1836 let Inst{7} = lane{0};
1839 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1840 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1842 // VST4LN : Vector Store (single 4-element structure from one lane)
1843 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1844 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1845 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1846 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1847 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1850 let Inst{4} = Rn{4};
1851 let DecoderMethod = "DecodeVST4LN";
1854 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1855 let Inst{7-5} = lane{2-0};
1857 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1858 let Inst{7-6} = lane{1-0};
1860 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1861 let Inst{7} = lane{0};
1862 let Inst{5} = Rn{5};
1865 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1866 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1867 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1869 // ...with double-spaced registers:
1870 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1871 let Inst{7-6} = lane{1-0};
1873 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1874 let Inst{7} = lane{0};
1875 let Inst{5} = Rn{5};
1878 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1879 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1881 // ...with address register writeback:
1882 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1883 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1884 (ins addrmode6:$Rn, am6offset:$Rm,
1885 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1886 IIC_VST4lnu, "vst4", Dt,
1887 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1888 "$Rn.addr = $wb", []> {
1889 let Inst{4} = Rn{4};
1890 let DecoderMethod = "DecodeVST4LN";
1893 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1894 let Inst{7-5} = lane{2-0};
1896 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1897 let Inst{7-6} = lane{1-0};
1899 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1900 let Inst{7} = lane{0};
1901 let Inst{5} = Rn{5};
1904 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1905 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1906 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1908 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1909 let Inst{7-6} = lane{1-0};
1911 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1912 let Inst{7} = lane{0};
1913 let Inst{5} = Rn{5};
1916 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1917 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1919 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1922 //===----------------------------------------------------------------------===//
1923 // NEON pattern fragments
1924 //===----------------------------------------------------------------------===//
1926 // Extract D sub-registers of Q registers.
1927 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1928 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1929 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1931 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1932 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1933 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1935 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1936 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1937 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1939 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1940 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1941 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1944 // Extract S sub-registers of Q/D registers.
1945 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1946 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1947 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1950 // Translate lane numbers from Q registers to D subregs.
1951 def SubReg_i8_lane : SDNodeXForm<imm, [{
1952 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1954 def SubReg_i16_lane : SDNodeXForm<imm, [{
1955 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1957 def SubReg_i32_lane : SDNodeXForm<imm, [{
1958 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1961 //===----------------------------------------------------------------------===//
1962 // Instruction Classes
1963 //===----------------------------------------------------------------------===//
1965 // Basic 2-register operations: double- and quad-register.
1966 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1967 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1968 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1969 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1970 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1971 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1972 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1973 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1974 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1975 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1976 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1977 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1979 // Basic 2-register intrinsics, both double- and quad-register.
1980 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1981 bits<2> op17_16, bits<5> op11_7, bit op4,
1982 InstrItinClass itin, string OpcodeStr, string Dt,
1983 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1984 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1985 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1986 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1987 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1988 bits<2> op17_16, bits<5> op11_7, bit op4,
1989 InstrItinClass itin, string OpcodeStr, string Dt,
1990 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1991 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1992 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1993 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1995 // Narrow 2-register operations.
1996 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1997 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1998 InstrItinClass itin, string OpcodeStr, string Dt,
1999 ValueType TyD, ValueType TyQ, SDNode OpNode>
2000 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2001 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2002 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2004 // Narrow 2-register intrinsics.
2005 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2006 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2007 InstrItinClass itin, string OpcodeStr, string Dt,
2008 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2009 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2010 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2011 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2013 // Long 2-register operations (currently only used for VMOVL).
2014 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2015 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2016 InstrItinClass itin, string OpcodeStr, string Dt,
2017 ValueType TyQ, ValueType TyD, SDNode OpNode>
2018 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2019 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2020 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2022 // Long 2-register intrinsics.
2023 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2024 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2025 InstrItinClass itin, string OpcodeStr, string Dt,
2026 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2027 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2028 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2029 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2031 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2032 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2033 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2034 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2035 OpcodeStr, Dt, "$Vd, $Vm",
2036 "$src1 = $Vd, $src2 = $Vm", []>;
2037 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2038 InstrItinClass itin, string OpcodeStr, string Dt>
2039 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2040 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2041 "$src1 = $Vd, $src2 = $Vm", []>;
2043 // Basic 3-register operations: double- and quad-register.
2044 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2045 InstrItinClass itin, string OpcodeStr, string Dt,
2046 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2047 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2048 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2049 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2050 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2051 let isCommutable = Commutable;
2053 // Same as N3VD but no data type.
2054 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2055 InstrItinClass itin, string OpcodeStr,
2056 ValueType ResTy, ValueType OpTy,
2057 SDNode OpNode, bit Commutable>
2058 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2059 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2060 OpcodeStr, "$Vd, $Vn, $Vm", "",
2061 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2062 let isCommutable = Commutable;
2065 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2066 InstrItinClass itin, string OpcodeStr, string Dt,
2067 ValueType Ty, SDNode ShOp>
2068 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2069 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2070 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2072 (Ty (ShOp (Ty DPR:$Vn),
2073 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2074 let isCommutable = 0;
2076 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2077 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2078 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2079 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2080 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2082 (Ty (ShOp (Ty DPR:$Vn),
2083 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2084 let isCommutable = 0;
2087 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2088 InstrItinClass itin, string OpcodeStr, string Dt,
2089 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2090 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2091 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2092 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2093 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2094 let isCommutable = Commutable;
2096 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2097 InstrItinClass itin, string OpcodeStr,
2098 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2099 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2100 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2101 OpcodeStr, "$Vd, $Vn, $Vm", "",
2102 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2103 let isCommutable = Commutable;
2105 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2106 InstrItinClass itin, string OpcodeStr, string Dt,
2107 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2108 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2109 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2110 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2111 [(set (ResTy QPR:$Vd),
2112 (ResTy (ShOp (ResTy QPR:$Vn),
2113 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2115 let isCommutable = 0;
2117 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2118 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2119 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2120 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2121 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2122 [(set (ResTy QPR:$Vd),
2123 (ResTy (ShOp (ResTy QPR:$Vn),
2124 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2126 let isCommutable = 0;
2129 // Basic 3-register intrinsics, both double- and quad-register.
2130 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2131 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2132 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2133 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2134 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2135 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2136 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2137 let isCommutable = Commutable;
2139 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2140 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2141 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2142 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2143 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2145 (Ty (IntOp (Ty DPR:$Vn),
2146 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2148 let isCommutable = 0;
2150 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2151 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2152 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2153 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2154 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2156 (Ty (IntOp (Ty DPR:$Vn),
2157 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2158 let isCommutable = 0;
2160 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2161 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2162 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2163 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2164 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2165 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2166 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2167 let isCommutable = 0;
2170 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2171 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2172 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2173 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2174 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2175 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2176 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2177 let isCommutable = Commutable;
2179 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2180 string OpcodeStr, string Dt,
2181 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2182 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2183 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2184 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2185 [(set (ResTy QPR:$Vd),
2186 (ResTy (IntOp (ResTy QPR:$Vn),
2187 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2189 let isCommutable = 0;
2191 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2192 string OpcodeStr, string Dt,
2193 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2194 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2195 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2196 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2197 [(set (ResTy QPR:$Vd),
2198 (ResTy (IntOp (ResTy QPR:$Vn),
2199 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2201 let isCommutable = 0;
2203 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2204 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2205 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2206 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2207 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2208 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2209 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2210 let isCommutable = 0;
2213 // Multiply-Add/Sub operations: double- and quad-register.
2214 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2215 InstrItinClass itin, string OpcodeStr, string Dt,
2216 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2217 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2218 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2219 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2220 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2221 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2223 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2224 string OpcodeStr, string Dt,
2225 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2226 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2228 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2230 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2232 (Ty (ShOp (Ty DPR:$src1),
2234 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2236 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2237 string OpcodeStr, string Dt,
2238 ValueType Ty, SDNode MulOp, SDNode ShOp>
2239 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2241 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2243 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2245 (Ty (ShOp (Ty DPR:$src1),
2247 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2250 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2251 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2252 SDPatternOperator MulOp, SDPatternOperator OpNode>
2253 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2254 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2255 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2256 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2257 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2258 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2259 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2260 SDPatternOperator MulOp, SDPatternOperator ShOp>
2261 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2263 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2265 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2266 [(set (ResTy QPR:$Vd),
2267 (ResTy (ShOp (ResTy QPR:$src1),
2268 (ResTy (MulOp QPR:$Vn,
2269 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2271 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2272 string OpcodeStr, string Dt,
2273 ValueType ResTy, ValueType OpTy,
2274 SDNode MulOp, SDNode ShOp>
2275 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2277 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2279 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2280 [(set (ResTy QPR:$Vd),
2281 (ResTy (ShOp (ResTy QPR:$src1),
2282 (ResTy (MulOp QPR:$Vn,
2283 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2286 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2287 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2288 InstrItinClass itin, string OpcodeStr, string Dt,
2289 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2290 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2291 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2292 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2293 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2294 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2295 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2296 InstrItinClass itin, string OpcodeStr, string Dt,
2297 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2298 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2299 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2300 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2301 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2302 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2304 // Neon 3-argument intrinsics, both double- and quad-register.
2305 // The destination register is also used as the first source operand register.
2306 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2307 InstrItinClass itin, string OpcodeStr, string Dt,
2308 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2309 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2310 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2311 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2312 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2313 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2314 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2315 InstrItinClass itin, string OpcodeStr, string Dt,
2316 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2317 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2318 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2319 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2320 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2321 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2323 // Long Multiply-Add/Sub operations.
2324 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2325 InstrItinClass itin, string OpcodeStr, string Dt,
2326 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2327 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2328 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2329 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2330 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2331 (TyQ (MulOp (TyD DPR:$Vn),
2332 (TyD DPR:$Vm)))))]>;
2333 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2334 InstrItinClass itin, string OpcodeStr, string Dt,
2335 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2336 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2337 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2339 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2341 (OpNode (TyQ QPR:$src1),
2342 (TyQ (MulOp (TyD DPR:$Vn),
2343 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2345 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2346 InstrItinClass itin, string OpcodeStr, string Dt,
2347 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2348 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2349 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2351 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2353 (OpNode (TyQ QPR:$src1),
2354 (TyQ (MulOp (TyD DPR:$Vn),
2355 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2358 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2359 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2360 InstrItinClass itin, string OpcodeStr, string Dt,
2361 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2363 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2364 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2365 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2366 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2367 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2368 (TyD DPR:$Vm)))))))]>;
2370 // Neon Long 3-argument intrinsic. The destination register is
2371 // a quad-register and is also used as the first source operand register.
2372 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2373 InstrItinClass itin, string OpcodeStr, string Dt,
2374 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2375 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2376 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2377 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2379 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2380 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2381 string OpcodeStr, string Dt,
2382 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2383 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2385 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2387 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2388 [(set (ResTy QPR:$Vd),
2389 (ResTy (IntOp (ResTy QPR:$src1),
2391 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2393 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2394 InstrItinClass itin, string OpcodeStr, string Dt,
2395 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2396 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2398 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2400 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2401 [(set (ResTy QPR:$Vd),
2402 (ResTy (IntOp (ResTy QPR:$src1),
2404 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2407 // Narrowing 3-register intrinsics.
2408 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2409 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2410 Intrinsic IntOp, bit Commutable>
2411 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2412 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2413 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2414 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2415 let isCommutable = Commutable;
2418 // Long 3-register operations.
2419 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2420 InstrItinClass itin, string OpcodeStr, string Dt,
2421 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2422 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2423 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2424 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2425 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2426 let isCommutable = Commutable;
2428 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2429 InstrItinClass itin, string OpcodeStr, string Dt,
2430 ValueType TyQ, ValueType TyD, SDNode OpNode>
2431 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2432 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2433 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2435 (TyQ (OpNode (TyD DPR:$Vn),
2436 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2437 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2438 InstrItinClass itin, string OpcodeStr, string Dt,
2439 ValueType TyQ, ValueType TyD, SDNode OpNode>
2440 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2441 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2442 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2444 (TyQ (OpNode (TyD DPR:$Vn),
2445 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2447 // Long 3-register operations with explicitly extended operands.
2448 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2449 InstrItinClass itin, string OpcodeStr, string Dt,
2450 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2452 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2453 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2454 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2455 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2456 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2457 let isCommutable = Commutable;
2460 // Long 3-register intrinsics with explicit extend (VABDL).
2461 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2462 InstrItinClass itin, string OpcodeStr, string Dt,
2463 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2465 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2466 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2467 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2468 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2469 (TyD DPR:$Vm))))))]> {
2470 let isCommutable = Commutable;
2473 // Long 3-register intrinsics.
2474 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2475 InstrItinClass itin, string OpcodeStr, string Dt,
2476 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2477 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2478 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2479 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2480 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2481 let isCommutable = Commutable;
2483 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2484 string OpcodeStr, string Dt,
2485 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2486 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2487 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2488 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2489 [(set (ResTy QPR:$Vd),
2490 (ResTy (IntOp (OpTy DPR:$Vn),
2491 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2493 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2494 InstrItinClass itin, string OpcodeStr, string Dt,
2495 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2496 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2497 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2498 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2499 [(set (ResTy QPR:$Vd),
2500 (ResTy (IntOp (OpTy DPR:$Vn),
2501 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2504 // Wide 3-register operations.
2505 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2506 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2507 SDNode OpNode, SDNode ExtOp, bit Commutable>
2508 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2509 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2510 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2511 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2512 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2513 let isCommutable = Commutable;
2516 // Pairwise long 2-register intrinsics, both double- and quad-register.
2517 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2518 bits<2> op17_16, bits<5> op11_7, bit op4,
2519 string OpcodeStr, string Dt,
2520 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2521 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2522 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2523 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2524 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2525 bits<2> op17_16, bits<5> op11_7, bit op4,
2526 string OpcodeStr, string Dt,
2527 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2528 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2529 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2530 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2532 // Pairwise long 2-register accumulate intrinsics,
2533 // both double- and quad-register.
2534 // The destination register is also used as the first source operand register.
2535 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2536 bits<2> op17_16, bits<5> op11_7, bit op4,
2537 string OpcodeStr, string Dt,
2538 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2539 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2540 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2541 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2542 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2543 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2544 bits<2> op17_16, bits<5> op11_7, bit op4,
2545 string OpcodeStr, string Dt,
2546 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2547 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2548 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2549 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2550 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2552 // Shift by immediate,
2553 // both double- and quad-register.
2554 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2555 Format f, InstrItinClass itin, Operand ImmTy,
2556 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2557 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2558 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2559 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2560 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2561 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2562 Format f, InstrItinClass itin, Operand ImmTy,
2563 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2564 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2565 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2566 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2567 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2569 // Long shift by immediate.
2570 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2571 string OpcodeStr, string Dt,
2572 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2573 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2574 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2575 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2576 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2577 (i32 imm:$SIMM))))]>;
2579 // Narrow shift by immediate.
2580 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2581 InstrItinClass itin, string OpcodeStr, string Dt,
2582 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2583 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2584 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2585 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2586 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2587 (i32 imm:$SIMM))))]>;
2589 // Shift right by immediate and accumulate,
2590 // both double- and quad-register.
2591 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2592 Operand ImmTy, string OpcodeStr, string Dt,
2593 ValueType Ty, SDNode ShOp>
2594 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2595 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2596 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2597 [(set DPR:$Vd, (Ty (add DPR:$src1,
2598 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2599 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2600 Operand ImmTy, string OpcodeStr, string Dt,
2601 ValueType Ty, SDNode ShOp>
2602 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2603 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2604 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2605 [(set QPR:$Vd, (Ty (add QPR:$src1,
2606 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2608 // Shift by immediate and insert,
2609 // both double- and quad-register.
2610 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2611 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2612 ValueType Ty,SDNode ShOp>
2613 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2614 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2615 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2616 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2617 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2618 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2619 ValueType Ty,SDNode ShOp>
2620 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2621 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2622 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2623 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2625 // Convert, with fractional bits immediate,
2626 // both double- and quad-register.
2627 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2628 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2630 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2631 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2632 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2633 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2634 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2635 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2637 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2638 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2639 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2640 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2642 //===----------------------------------------------------------------------===//
2644 //===----------------------------------------------------------------------===//
2646 // Abbreviations used in multiclass suffixes:
2647 // Q = quarter int (8 bit) elements
2648 // H = half int (16 bit) elements
2649 // S = single int (32 bit) elements
2650 // D = double int (64 bit) elements
2652 // Neon 2-register vector operations and intrinsics.
2654 // Neon 2-register comparisons.
2655 // source operand element sizes of 8, 16 and 32 bits:
2656 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2657 bits<5> op11_7, bit op4, string opc, string Dt,
2658 string asm, SDNode OpNode> {
2659 // 64-bit vector types.
2660 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2661 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2662 opc, !strconcat(Dt, "8"), asm, "",
2663 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2664 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2665 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2666 opc, !strconcat(Dt, "16"), asm, "",
2667 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2668 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2669 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2670 opc, !strconcat(Dt, "32"), asm, "",
2671 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2672 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2673 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2674 opc, "f32", asm, "",
2675 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2676 let Inst{10} = 1; // overwrite F = 1
2679 // 128-bit vector types.
2680 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2681 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2682 opc, !strconcat(Dt, "8"), asm, "",
2683 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2684 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2685 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2686 opc, !strconcat(Dt, "16"), asm, "",
2687 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2688 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2689 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2690 opc, !strconcat(Dt, "32"), asm, "",
2691 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2692 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2693 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2694 opc, "f32", asm, "",
2695 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2696 let Inst{10} = 1; // overwrite F = 1
2701 // Neon 2-register vector intrinsics,
2702 // element sizes of 8, 16 and 32 bits:
2703 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2704 bits<5> op11_7, bit op4,
2705 InstrItinClass itinD, InstrItinClass itinQ,
2706 string OpcodeStr, string Dt, Intrinsic IntOp> {
2707 // 64-bit vector types.
2708 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2709 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2710 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2711 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2712 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2713 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2715 // 128-bit vector types.
2716 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2717 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2718 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2719 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2720 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2721 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2725 // Neon Narrowing 2-register vector operations,
2726 // source operand element sizes of 16, 32 and 64 bits:
2727 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2728 bits<5> op11_7, bit op6, bit op4,
2729 InstrItinClass itin, string OpcodeStr, string Dt,
2731 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2732 itin, OpcodeStr, !strconcat(Dt, "16"),
2733 v8i8, v8i16, OpNode>;
2734 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2735 itin, OpcodeStr, !strconcat(Dt, "32"),
2736 v4i16, v4i32, OpNode>;
2737 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2738 itin, OpcodeStr, !strconcat(Dt, "64"),
2739 v2i32, v2i64, OpNode>;
2742 // Neon Narrowing 2-register vector intrinsics,
2743 // source operand element sizes of 16, 32 and 64 bits:
2744 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2745 bits<5> op11_7, bit op6, bit op4,
2746 InstrItinClass itin, string OpcodeStr, string Dt,
2748 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2749 itin, OpcodeStr, !strconcat(Dt, "16"),
2750 v8i8, v8i16, IntOp>;
2751 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2752 itin, OpcodeStr, !strconcat(Dt, "32"),
2753 v4i16, v4i32, IntOp>;
2754 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2755 itin, OpcodeStr, !strconcat(Dt, "64"),
2756 v2i32, v2i64, IntOp>;
2760 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2761 // source operand element sizes of 16, 32 and 64 bits:
2762 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2763 string OpcodeStr, string Dt, SDNode OpNode> {
2764 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2765 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2766 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2767 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2768 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2769 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2773 // Neon 3-register vector operations.
2775 // First with only element sizes of 8, 16 and 32 bits:
2776 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2777 InstrItinClass itinD16, InstrItinClass itinD32,
2778 InstrItinClass itinQ16, InstrItinClass itinQ32,
2779 string OpcodeStr, string Dt,
2780 SDNode OpNode, bit Commutable = 0> {
2781 // 64-bit vector types.
2782 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2783 OpcodeStr, !strconcat(Dt, "8"),
2784 v8i8, v8i8, OpNode, Commutable>;
2785 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2786 OpcodeStr, !strconcat(Dt, "16"),
2787 v4i16, v4i16, OpNode, Commutable>;
2788 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2789 OpcodeStr, !strconcat(Dt, "32"),
2790 v2i32, v2i32, OpNode, Commutable>;
2792 // 128-bit vector types.
2793 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2794 OpcodeStr, !strconcat(Dt, "8"),
2795 v16i8, v16i8, OpNode, Commutable>;
2796 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2797 OpcodeStr, !strconcat(Dt, "16"),
2798 v8i16, v8i16, OpNode, Commutable>;
2799 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2800 OpcodeStr, !strconcat(Dt, "32"),
2801 v4i32, v4i32, OpNode, Commutable>;
2804 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2805 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2807 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2809 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2810 v8i16, v4i16, ShOp>;
2811 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2812 v4i32, v2i32, ShOp>;
2815 // ....then also with element size 64 bits:
2816 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2817 InstrItinClass itinD, InstrItinClass itinQ,
2818 string OpcodeStr, string Dt,
2819 SDNode OpNode, bit Commutable = 0>
2820 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2821 OpcodeStr, Dt, OpNode, Commutable> {
2822 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2823 OpcodeStr, !strconcat(Dt, "64"),
2824 v1i64, v1i64, OpNode, Commutable>;
2825 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2826 OpcodeStr, !strconcat(Dt, "64"),
2827 v2i64, v2i64, OpNode, Commutable>;
2831 // Neon 3-register vector intrinsics.
2833 // First with only element sizes of 16 and 32 bits:
2834 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2835 InstrItinClass itinD16, InstrItinClass itinD32,
2836 InstrItinClass itinQ16, InstrItinClass itinQ32,
2837 string OpcodeStr, string Dt,
2838 Intrinsic IntOp, bit Commutable = 0> {
2839 // 64-bit vector types.
2840 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2841 OpcodeStr, !strconcat(Dt, "16"),
2842 v4i16, v4i16, IntOp, Commutable>;
2843 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2844 OpcodeStr, !strconcat(Dt, "32"),
2845 v2i32, v2i32, IntOp, Commutable>;
2847 // 128-bit vector types.
2848 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2849 OpcodeStr, !strconcat(Dt, "16"),
2850 v8i16, v8i16, IntOp, Commutable>;
2851 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2852 OpcodeStr, !strconcat(Dt, "32"),
2853 v4i32, v4i32, IntOp, Commutable>;
2855 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2856 InstrItinClass itinD16, InstrItinClass itinD32,
2857 InstrItinClass itinQ16, InstrItinClass itinQ32,
2858 string OpcodeStr, string Dt,
2860 // 64-bit vector types.
2861 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2862 OpcodeStr, !strconcat(Dt, "16"),
2863 v4i16, v4i16, IntOp>;
2864 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2865 OpcodeStr, !strconcat(Dt, "32"),
2866 v2i32, v2i32, IntOp>;
2868 // 128-bit vector types.
2869 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2870 OpcodeStr, !strconcat(Dt, "16"),
2871 v8i16, v8i16, IntOp>;
2872 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2873 OpcodeStr, !strconcat(Dt, "32"),
2874 v4i32, v4i32, IntOp>;
2877 multiclass N3VIntSL_HS<bits<4> op11_8,
2878 InstrItinClass itinD16, InstrItinClass itinD32,
2879 InstrItinClass itinQ16, InstrItinClass itinQ32,
2880 string OpcodeStr, string Dt, Intrinsic IntOp> {
2881 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2882 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2883 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2884 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2885 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2886 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2887 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2888 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2891 // ....then also with element size of 8 bits:
2892 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2893 InstrItinClass itinD16, InstrItinClass itinD32,
2894 InstrItinClass itinQ16, InstrItinClass itinQ32,
2895 string OpcodeStr, string Dt,
2896 Intrinsic IntOp, bit Commutable = 0>
2897 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2898 OpcodeStr, Dt, IntOp, Commutable> {
2899 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2900 OpcodeStr, !strconcat(Dt, "8"),
2901 v8i8, v8i8, IntOp, Commutable>;
2902 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2903 OpcodeStr, !strconcat(Dt, "8"),
2904 v16i8, v16i8, IntOp, Commutable>;
2906 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2907 InstrItinClass itinD16, InstrItinClass itinD32,
2908 InstrItinClass itinQ16, InstrItinClass itinQ32,
2909 string OpcodeStr, string Dt,
2911 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2912 OpcodeStr, Dt, IntOp> {
2913 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2914 OpcodeStr, !strconcat(Dt, "8"),
2916 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2917 OpcodeStr, !strconcat(Dt, "8"),
2918 v16i8, v16i8, IntOp>;
2922 // ....then also with element size of 64 bits:
2923 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2924 InstrItinClass itinD16, InstrItinClass itinD32,
2925 InstrItinClass itinQ16, InstrItinClass itinQ32,
2926 string OpcodeStr, string Dt,
2927 Intrinsic IntOp, bit Commutable = 0>
2928 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2929 OpcodeStr, Dt, IntOp, Commutable> {
2930 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2931 OpcodeStr, !strconcat(Dt, "64"),
2932 v1i64, v1i64, IntOp, Commutable>;
2933 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2934 OpcodeStr, !strconcat(Dt, "64"),
2935 v2i64, v2i64, IntOp, Commutable>;
2937 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2938 InstrItinClass itinD16, InstrItinClass itinD32,
2939 InstrItinClass itinQ16, InstrItinClass itinQ32,
2940 string OpcodeStr, string Dt,
2942 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2943 OpcodeStr, Dt, IntOp> {
2944 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2945 OpcodeStr, !strconcat(Dt, "64"),
2946 v1i64, v1i64, IntOp>;
2947 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2948 OpcodeStr, !strconcat(Dt, "64"),
2949 v2i64, v2i64, IntOp>;
2952 // Neon Narrowing 3-register vector intrinsics,
2953 // source operand element sizes of 16, 32 and 64 bits:
2954 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2955 string OpcodeStr, string Dt,
2956 Intrinsic IntOp, bit Commutable = 0> {
2957 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2958 OpcodeStr, !strconcat(Dt, "16"),
2959 v8i8, v8i16, IntOp, Commutable>;
2960 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2961 OpcodeStr, !strconcat(Dt, "32"),
2962 v4i16, v4i32, IntOp, Commutable>;
2963 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2964 OpcodeStr, !strconcat(Dt, "64"),
2965 v2i32, v2i64, IntOp, Commutable>;
2969 // Neon Long 3-register vector operations.
2971 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2972 InstrItinClass itin16, InstrItinClass itin32,
2973 string OpcodeStr, string Dt,
2974 SDNode OpNode, bit Commutable = 0> {
2975 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2976 OpcodeStr, !strconcat(Dt, "8"),
2977 v8i16, v8i8, OpNode, Commutable>;
2978 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2979 OpcodeStr, !strconcat(Dt, "16"),
2980 v4i32, v4i16, OpNode, Commutable>;
2981 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2982 OpcodeStr, !strconcat(Dt, "32"),
2983 v2i64, v2i32, OpNode, Commutable>;
2986 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2987 InstrItinClass itin, string OpcodeStr, string Dt,
2989 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2990 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2991 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2992 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2995 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2996 InstrItinClass itin16, InstrItinClass itin32,
2997 string OpcodeStr, string Dt,
2998 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2999 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3000 OpcodeStr, !strconcat(Dt, "8"),
3001 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3002 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3003 OpcodeStr, !strconcat(Dt, "16"),
3004 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3005 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3006 OpcodeStr, !strconcat(Dt, "32"),
3007 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3010 // Neon Long 3-register vector intrinsics.
3012 // First with only element sizes of 16 and 32 bits:
3013 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3014 InstrItinClass itin16, InstrItinClass itin32,
3015 string OpcodeStr, string Dt,
3016 Intrinsic IntOp, bit Commutable = 0> {
3017 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3018 OpcodeStr, !strconcat(Dt, "16"),
3019 v4i32, v4i16, IntOp, Commutable>;
3020 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3021 OpcodeStr, !strconcat(Dt, "32"),
3022 v2i64, v2i32, IntOp, Commutable>;
3025 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3026 InstrItinClass itin, string OpcodeStr, string Dt,
3028 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3029 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3030 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3031 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3034 // ....then also with element size of 8 bits:
3035 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3036 InstrItinClass itin16, InstrItinClass itin32,
3037 string OpcodeStr, string Dt,
3038 Intrinsic IntOp, bit Commutable = 0>
3039 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3040 IntOp, Commutable> {
3041 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3042 OpcodeStr, !strconcat(Dt, "8"),
3043 v8i16, v8i8, IntOp, Commutable>;
3046 // ....with explicit extend (VABDL).
3047 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3048 InstrItinClass itin, string OpcodeStr, string Dt,
3049 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3050 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3051 OpcodeStr, !strconcat(Dt, "8"),
3052 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3053 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3054 OpcodeStr, !strconcat(Dt, "16"),
3055 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3056 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3057 OpcodeStr, !strconcat(Dt, "32"),
3058 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3062 // Neon Wide 3-register vector intrinsics,
3063 // source operand element sizes of 8, 16 and 32 bits:
3064 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3065 string OpcodeStr, string Dt,
3066 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3067 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3068 OpcodeStr, !strconcat(Dt, "8"),
3069 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3070 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3071 OpcodeStr, !strconcat(Dt, "16"),
3072 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3073 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3074 OpcodeStr, !strconcat(Dt, "32"),
3075 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3079 // Neon Multiply-Op vector operations,
3080 // element sizes of 8, 16 and 32 bits:
3081 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3082 InstrItinClass itinD16, InstrItinClass itinD32,
3083 InstrItinClass itinQ16, InstrItinClass itinQ32,
3084 string OpcodeStr, string Dt, SDNode OpNode> {
3085 // 64-bit vector types.
3086 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3087 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3088 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3089 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3090 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3091 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3093 // 128-bit vector types.
3094 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3095 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3096 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3097 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3098 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3099 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3102 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3103 InstrItinClass itinD16, InstrItinClass itinD32,
3104 InstrItinClass itinQ16, InstrItinClass itinQ32,
3105 string OpcodeStr, string Dt, SDNode ShOp> {
3106 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3107 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3108 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3109 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3110 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3111 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3113 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3114 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3118 // Neon Intrinsic-Op vector operations,
3119 // element sizes of 8, 16 and 32 bits:
3120 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3121 InstrItinClass itinD, InstrItinClass itinQ,
3122 string OpcodeStr, string Dt, Intrinsic IntOp,
3124 // 64-bit vector types.
3125 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3126 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3127 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3128 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3129 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3130 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3132 // 128-bit vector types.
3133 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3134 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3135 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3136 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3137 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3138 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3141 // Neon 3-argument intrinsics,
3142 // element sizes of 8, 16 and 32 bits:
3143 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3144 InstrItinClass itinD, InstrItinClass itinQ,
3145 string OpcodeStr, string Dt, Intrinsic IntOp> {
3146 // 64-bit vector types.
3147 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3148 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3149 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3150 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3151 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3152 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3154 // 128-bit vector types.
3155 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3156 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3157 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3158 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3159 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3160 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3164 // Neon Long Multiply-Op vector operations,
3165 // element sizes of 8, 16 and 32 bits:
3166 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3167 InstrItinClass itin16, InstrItinClass itin32,
3168 string OpcodeStr, string Dt, SDNode MulOp,
3170 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3171 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3172 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3173 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3174 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3175 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3178 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3179 string Dt, SDNode MulOp, SDNode OpNode> {
3180 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3181 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3182 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3183 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3187 // Neon Long 3-argument intrinsics.
3189 // First with only element sizes of 16 and 32 bits:
3190 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3191 InstrItinClass itin16, InstrItinClass itin32,
3192 string OpcodeStr, string Dt, Intrinsic IntOp> {
3193 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3194 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3195 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3196 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3199 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3200 string OpcodeStr, string Dt, Intrinsic IntOp> {
3201 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3202 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3203 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3204 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3207 // ....then also with element size of 8 bits:
3208 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3209 InstrItinClass itin16, InstrItinClass itin32,
3210 string OpcodeStr, string Dt, Intrinsic IntOp>
3211 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3212 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3213 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3216 // ....with explicit extend (VABAL).
3217 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3218 InstrItinClass itin, string OpcodeStr, string Dt,
3219 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3220 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3221 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3222 IntOp, ExtOp, OpNode>;
3223 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3224 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3225 IntOp, ExtOp, OpNode>;
3226 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3227 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3228 IntOp, ExtOp, OpNode>;
3232 // Neon Pairwise long 2-register intrinsics,
3233 // element sizes of 8, 16 and 32 bits:
3234 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3235 bits<5> op11_7, bit op4,
3236 string OpcodeStr, string Dt, Intrinsic IntOp> {
3237 // 64-bit vector types.
3238 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3239 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3240 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3241 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3242 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3243 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3245 // 128-bit vector types.
3246 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3247 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3248 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3249 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3250 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3251 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3255 // Neon Pairwise long 2-register accumulate intrinsics,
3256 // element sizes of 8, 16 and 32 bits:
3257 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3258 bits<5> op11_7, bit op4,
3259 string OpcodeStr, string Dt, Intrinsic IntOp> {
3260 // 64-bit vector types.
3261 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3262 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3263 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3264 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3265 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3266 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3268 // 128-bit vector types.
3269 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3270 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3271 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3272 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3273 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3274 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3278 // Neon 2-register vector shift by immediate,
3279 // with f of either N2RegVShLFrm or N2RegVShRFrm
3280 // element sizes of 8, 16, 32 and 64 bits:
3281 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3282 InstrItinClass itin, string OpcodeStr, string Dt,
3284 // 64-bit vector types.
3285 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3286 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3287 let Inst{21-19} = 0b001; // imm6 = 001xxx
3289 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3290 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3291 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3293 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3294 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3295 let Inst{21} = 0b1; // imm6 = 1xxxxx
3297 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3298 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3301 // 128-bit vector types.
3302 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3303 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3304 let Inst{21-19} = 0b001; // imm6 = 001xxx
3306 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3307 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3308 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3310 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3311 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3312 let Inst{21} = 0b1; // imm6 = 1xxxxx
3314 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3315 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3318 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3319 InstrItinClass itin, string OpcodeStr, string Dt,
3321 // 64-bit vector types.
3322 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3323 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3324 let Inst{21-19} = 0b001; // imm6 = 001xxx
3326 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3327 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3328 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3330 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3331 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3332 let Inst{21} = 0b1; // imm6 = 1xxxxx
3334 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3335 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3338 // 128-bit vector types.
3339 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3340 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3341 let Inst{21-19} = 0b001; // imm6 = 001xxx
3343 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3344 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3345 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3347 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3348 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3349 let Inst{21} = 0b1; // imm6 = 1xxxxx
3351 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3352 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3356 // Neon Shift-Accumulate vector operations,
3357 // element sizes of 8, 16, 32 and 64 bits:
3358 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3359 string OpcodeStr, string Dt, SDNode ShOp> {
3360 // 64-bit vector types.
3361 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3362 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3363 let Inst{21-19} = 0b001; // imm6 = 001xxx
3365 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3366 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3367 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3369 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3370 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3371 let Inst{21} = 0b1; // imm6 = 1xxxxx
3373 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3374 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3377 // 128-bit vector types.
3378 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3379 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3380 let Inst{21-19} = 0b001; // imm6 = 001xxx
3382 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3383 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3384 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3386 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3387 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3388 let Inst{21} = 0b1; // imm6 = 1xxxxx
3390 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3391 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3395 // Neon Shift-Insert vector operations,
3396 // with f of either N2RegVShLFrm or N2RegVShRFrm
3397 // element sizes of 8, 16, 32 and 64 bits:
3398 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3400 // 64-bit vector types.
3401 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3402 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3403 let Inst{21-19} = 0b001; // imm6 = 001xxx
3405 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3406 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3407 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3409 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3410 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3411 let Inst{21} = 0b1; // imm6 = 1xxxxx
3413 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3414 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3417 // 128-bit vector types.
3418 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3419 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3420 let Inst{21-19} = 0b001; // imm6 = 001xxx
3422 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3423 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3424 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3426 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3427 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3428 let Inst{21} = 0b1; // imm6 = 1xxxxx
3430 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3431 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3434 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3436 // 64-bit vector types.
3437 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3438 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3439 let Inst{21-19} = 0b001; // imm6 = 001xxx
3441 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3442 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3443 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3445 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3446 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3447 let Inst{21} = 0b1; // imm6 = 1xxxxx
3449 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3450 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3453 // 128-bit vector types.
3454 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3455 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3456 let Inst{21-19} = 0b001; // imm6 = 001xxx
3458 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3459 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3460 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3462 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3463 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3464 let Inst{21} = 0b1; // imm6 = 1xxxxx
3466 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3467 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3471 // Neon Shift Long operations,
3472 // element sizes of 8, 16, 32 bits:
3473 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3474 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3475 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3476 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3477 let Inst{21-19} = 0b001; // imm6 = 001xxx
3479 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3480 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3481 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3483 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3484 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3485 let Inst{21} = 0b1; // imm6 = 1xxxxx
3489 // Neon Shift Narrow operations,
3490 // element sizes of 16, 32, 64 bits:
3491 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3492 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3494 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3495 OpcodeStr, !strconcat(Dt, "16"),
3496 v8i8, v8i16, shr_imm8, OpNode> {
3497 let Inst{21-19} = 0b001; // imm6 = 001xxx
3499 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3500 OpcodeStr, !strconcat(Dt, "32"),
3501 v4i16, v4i32, shr_imm16, OpNode> {
3502 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3504 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3505 OpcodeStr, !strconcat(Dt, "64"),
3506 v2i32, v2i64, shr_imm32, OpNode> {
3507 let Inst{21} = 0b1; // imm6 = 1xxxxx
3511 //===----------------------------------------------------------------------===//
3512 // Instruction Definitions.
3513 //===----------------------------------------------------------------------===//
3515 // Vector Add Operations.
3517 // VADD : Vector Add (integer and floating-point)
3518 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3520 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3521 v2f32, v2f32, fadd, 1>;
3522 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3523 v4f32, v4f32, fadd, 1>;
3524 // VADDL : Vector Add Long (Q = D + D)
3525 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3526 "vaddl", "s", add, sext, 1>;
3527 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3528 "vaddl", "u", add, zext, 1>;
3529 // VADDW : Vector Add Wide (Q = Q + D)
3530 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3531 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3532 // VHADD : Vector Halving Add
3533 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3534 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3535 "vhadd", "s", int_arm_neon_vhadds, 1>;
3536 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3537 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3538 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3539 // VRHADD : Vector Rounding Halving Add
3540 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3541 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3542 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3543 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3544 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3545 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3546 // VQADD : Vector Saturating Add
3547 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3548 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3549 "vqadd", "s", int_arm_neon_vqadds, 1>;
3550 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3551 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3552 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3553 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3554 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3555 int_arm_neon_vaddhn, 1>;
3556 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3557 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3558 int_arm_neon_vraddhn, 1>;
3560 // Vector Multiply Operations.
3562 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3563 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3564 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3565 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3566 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3567 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3568 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3569 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3570 v2f32, v2f32, fmul, 1>;
3571 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3572 v4f32, v4f32, fmul, 1>;
3573 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3574 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3575 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3578 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3579 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3580 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3581 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3582 (DSubReg_i16_reg imm:$lane))),
3583 (SubReg_i16_lane imm:$lane)))>;
3584 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3585 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3586 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3587 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3588 (DSubReg_i32_reg imm:$lane))),
3589 (SubReg_i32_lane imm:$lane)))>;
3590 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3591 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3592 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3593 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3594 (DSubReg_i32_reg imm:$lane))),
3595 (SubReg_i32_lane imm:$lane)))>;
3597 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3598 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3599 IIC_VMULi16Q, IIC_VMULi32Q,
3600 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3601 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3602 IIC_VMULi16Q, IIC_VMULi32Q,
3603 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3604 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3605 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3607 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3608 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3609 (DSubReg_i16_reg imm:$lane))),
3610 (SubReg_i16_lane imm:$lane)))>;
3611 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3612 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3614 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3615 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3616 (DSubReg_i32_reg imm:$lane))),
3617 (SubReg_i32_lane imm:$lane)))>;
3619 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3620 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3621 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3622 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3623 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3624 IIC_VMULi16Q, IIC_VMULi32Q,
3625 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3626 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3627 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3629 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3630 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3631 (DSubReg_i16_reg imm:$lane))),
3632 (SubReg_i16_lane imm:$lane)))>;
3633 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3634 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3636 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3637 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3638 (DSubReg_i32_reg imm:$lane))),
3639 (SubReg_i32_lane imm:$lane)))>;
3641 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3642 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3643 "vmull", "s", NEONvmulls, 1>;
3644 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3645 "vmull", "u", NEONvmullu, 1>;
3646 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3647 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3648 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3649 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3651 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3652 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3653 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3654 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3655 "vqdmull", "s", int_arm_neon_vqdmull>;
3657 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3659 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3660 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3661 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3662 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3663 v2f32, fmul_su, fadd_mlx>,
3664 Requires<[HasNEON, UseFPVMLx]>;
3665 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3666 v4f32, fmul_su, fadd_mlx>,
3667 Requires<[HasNEON, UseFPVMLx]>;
3668 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3669 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3670 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3671 v2f32, fmul_su, fadd_mlx>,
3672 Requires<[HasNEON, UseFPVMLx]>;
3673 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3674 v4f32, v2f32, fmul_su, fadd_mlx>,
3675 Requires<[HasNEON, UseFPVMLx]>;
3677 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3678 (mul (v8i16 QPR:$src2),
3679 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3680 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3681 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3682 (DSubReg_i16_reg imm:$lane))),
3683 (SubReg_i16_lane imm:$lane)))>;
3685 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3686 (mul (v4i32 QPR:$src2),
3687 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3688 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3689 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3690 (DSubReg_i32_reg imm:$lane))),
3691 (SubReg_i32_lane imm:$lane)))>;
3693 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3694 (fmul_su (v4f32 QPR:$src2),
3695 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3696 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3698 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3699 (DSubReg_i32_reg imm:$lane))),
3700 (SubReg_i32_lane imm:$lane)))>,
3701 Requires<[HasNEON, UseFPVMLx]>;
3703 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3704 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3705 "vmlal", "s", NEONvmulls, add>;
3706 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3707 "vmlal", "u", NEONvmullu, add>;
3709 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3710 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3712 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3713 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3714 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3715 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3717 // VMLS : Vector Multiply Subtract (integer and floating-point)
3718 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3719 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3720 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3721 v2f32, fmul_su, fsub_mlx>,
3722 Requires<[HasNEON, UseFPVMLx]>;
3723 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3724 v4f32, fmul_su, fsub_mlx>,
3725 Requires<[HasNEON, UseFPVMLx]>;
3726 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3727 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3728 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3729 v2f32, fmul_su, fsub_mlx>,
3730 Requires<[HasNEON, UseFPVMLx]>;
3731 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3732 v4f32, v2f32, fmul_su, fsub_mlx>,
3733 Requires<[HasNEON, UseFPVMLx]>;
3735 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3736 (mul (v8i16 QPR:$src2),
3737 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3738 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3739 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3740 (DSubReg_i16_reg imm:$lane))),
3741 (SubReg_i16_lane imm:$lane)))>;
3743 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3744 (mul (v4i32 QPR:$src2),
3745 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3746 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3747 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3748 (DSubReg_i32_reg imm:$lane))),
3749 (SubReg_i32_lane imm:$lane)))>;
3751 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3752 (fmul_su (v4f32 QPR:$src2),
3753 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3754 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3755 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3756 (DSubReg_i32_reg imm:$lane))),
3757 (SubReg_i32_lane imm:$lane)))>,
3758 Requires<[HasNEON, UseFPVMLx]>;
3760 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3761 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3762 "vmlsl", "s", NEONvmulls, sub>;
3763 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3764 "vmlsl", "u", NEONvmullu, sub>;
3766 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3767 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3769 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3770 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3771 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3772 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3774 // Vector Subtract Operations.
3776 // VSUB : Vector Subtract (integer and floating-point)
3777 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3778 "vsub", "i", sub, 0>;
3779 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3780 v2f32, v2f32, fsub, 0>;
3781 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3782 v4f32, v4f32, fsub, 0>;
3783 // VSUBL : Vector Subtract Long (Q = D - D)
3784 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3785 "vsubl", "s", sub, sext, 0>;
3786 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3787 "vsubl", "u", sub, zext, 0>;
3788 // VSUBW : Vector Subtract Wide (Q = Q - D)
3789 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3790 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3791 // VHSUB : Vector Halving Subtract
3792 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3793 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3794 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3795 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3796 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3797 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3798 // VQSUB : Vector Saturing Subtract
3799 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3800 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3801 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3802 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3803 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3804 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3805 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3806 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3807 int_arm_neon_vsubhn, 0>;
3808 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3809 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3810 int_arm_neon_vrsubhn, 0>;
3812 // Vector Comparisons.
3814 // VCEQ : Vector Compare Equal
3815 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3816 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3817 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3819 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3822 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3823 "$Vd, $Vm, #0", NEONvceqz>;
3825 // VCGE : Vector Compare Greater Than or Equal
3826 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3827 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3828 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3829 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3830 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3832 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3835 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3836 "$Vd, $Vm, #0", NEONvcgez>;
3837 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3838 "$Vd, $Vm, #0", NEONvclez>;
3840 // VCGT : Vector Compare Greater Than
3841 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3842 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3843 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3844 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3845 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3847 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3850 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3851 "$Vd, $Vm, #0", NEONvcgtz>;
3852 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3853 "$Vd, $Vm, #0", NEONvcltz>;
3855 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3856 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3857 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3858 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3859 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3860 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3861 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3862 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3863 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3864 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3865 // VTST : Vector Test Bits
3866 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3867 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3869 // Vector Bitwise Operations.
3871 def vnotd : PatFrag<(ops node:$in),
3872 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3873 def vnotq : PatFrag<(ops node:$in),
3874 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3877 // VAND : Vector Bitwise AND
3878 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3879 v2i32, v2i32, and, 1>;
3880 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3881 v4i32, v4i32, and, 1>;
3883 // VEOR : Vector Bitwise Exclusive OR
3884 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3885 v2i32, v2i32, xor, 1>;
3886 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3887 v4i32, v4i32, xor, 1>;
3889 // VORR : Vector Bitwise OR
3890 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3891 v2i32, v2i32, or, 1>;
3892 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3893 v4i32, v4i32, or, 1>;
3895 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3896 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3898 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3900 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3901 let Inst{9} = SIMM{9};
3904 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3905 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3907 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3909 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3910 let Inst{10-9} = SIMM{10-9};
3913 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3914 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3916 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3918 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3919 let Inst{9} = SIMM{9};
3922 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3923 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3925 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3927 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3928 let Inst{10-9} = SIMM{10-9};
3932 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3933 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3934 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3935 "vbic", "$Vd, $Vn, $Vm", "",
3936 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3937 (vnotd DPR:$Vm))))]>;
3938 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3939 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3940 "vbic", "$Vd, $Vn, $Vm", "",
3941 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3942 (vnotq QPR:$Vm))))]>;
3944 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3945 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3947 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3949 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3950 let Inst{9} = SIMM{9};
3953 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3954 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3956 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3958 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3959 let Inst{10-9} = SIMM{10-9};
3962 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3963 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3965 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3967 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3968 let Inst{9} = SIMM{9};
3971 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3972 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3974 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3976 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3977 let Inst{10-9} = SIMM{10-9};
3980 // VORN : Vector Bitwise OR NOT
3981 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3982 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3983 "vorn", "$Vd, $Vn, $Vm", "",
3984 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3985 (vnotd DPR:$Vm))))]>;
3986 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3987 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3988 "vorn", "$Vd, $Vn, $Vm", "",
3989 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3990 (vnotq QPR:$Vm))))]>;
3992 // VMVN : Vector Bitwise NOT (Immediate)
3994 let isReMaterializable = 1 in {
3996 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3997 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3998 "vmvn", "i16", "$Vd, $SIMM", "",
3999 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4000 let Inst{9} = SIMM{9};
4003 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4004 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4005 "vmvn", "i16", "$Vd, $SIMM", "",
4006 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4007 let Inst{9} = SIMM{9};
4010 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4011 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4012 "vmvn", "i32", "$Vd, $SIMM", "",
4013 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4014 let Inst{11-8} = SIMM{11-8};
4017 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4018 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4019 "vmvn", "i32", "$Vd, $SIMM", "",
4020 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4021 let Inst{11-8} = SIMM{11-8};
4025 // VMVN : Vector Bitwise NOT
4026 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4027 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4028 "vmvn", "$Vd, $Vm", "",
4029 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4030 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4031 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4032 "vmvn", "$Vd, $Vm", "",
4033 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4034 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4035 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4037 // VBSL : Vector Bitwise Select
4038 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4039 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4040 N3RegFrm, IIC_VCNTiD,
4041 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4043 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4045 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4046 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4047 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4049 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4050 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4051 N3RegFrm, IIC_VCNTiQ,
4052 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4054 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4056 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4057 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4058 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4060 // VBIF : Vector Bitwise Insert if False
4061 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4062 // FIXME: This instruction's encoding MAY NOT BE correct.
4063 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4064 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4065 N3RegFrm, IIC_VBINiD,
4066 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4068 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4069 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4070 N3RegFrm, IIC_VBINiQ,
4071 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4074 // VBIT : Vector Bitwise Insert if True
4075 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4076 // FIXME: This instruction's encoding MAY NOT BE correct.
4077 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4078 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4079 N3RegFrm, IIC_VBINiD,
4080 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4082 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4083 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4084 N3RegFrm, IIC_VBINiQ,
4085 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4088 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4089 // for equivalent operations with different register constraints; it just
4092 // Vector Absolute Differences.
4094 // VABD : Vector Absolute Difference
4095 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4096 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4097 "vabd", "s", int_arm_neon_vabds, 1>;
4098 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4099 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4100 "vabd", "u", int_arm_neon_vabdu, 1>;
4101 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4102 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4103 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4104 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4106 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4107 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4108 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4109 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4110 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4112 // VABA : Vector Absolute Difference and Accumulate
4113 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4114 "vaba", "s", int_arm_neon_vabds, add>;
4115 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4116 "vaba", "u", int_arm_neon_vabdu, add>;
4118 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4119 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4120 "vabal", "s", int_arm_neon_vabds, zext, add>;
4121 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4122 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4124 // Vector Maximum and Minimum.
4126 // VMAX : Vector Maximum
4127 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4128 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4129 "vmax", "s", int_arm_neon_vmaxs, 1>;
4130 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4131 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4132 "vmax", "u", int_arm_neon_vmaxu, 1>;
4133 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4135 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4136 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4138 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4140 // VMIN : Vector Minimum
4141 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4142 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4143 "vmin", "s", int_arm_neon_vmins, 1>;
4144 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4145 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4146 "vmin", "u", int_arm_neon_vminu, 1>;
4147 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4149 v2f32, v2f32, int_arm_neon_vmins, 1>;
4150 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4152 v4f32, v4f32, int_arm_neon_vmins, 1>;
4154 // Vector Pairwise Operations.
4156 // VPADD : Vector Pairwise Add
4157 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4159 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4160 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4162 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4163 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4165 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4166 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4167 IIC_VPBIND, "vpadd", "f32",
4168 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4170 // VPADDL : Vector Pairwise Add Long
4171 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4172 int_arm_neon_vpaddls>;
4173 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4174 int_arm_neon_vpaddlu>;
4176 // VPADAL : Vector Pairwise Add and Accumulate Long
4177 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4178 int_arm_neon_vpadals>;
4179 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4180 int_arm_neon_vpadalu>;
4182 // VPMAX : Vector Pairwise Maximum
4183 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4184 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4185 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4186 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4187 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4188 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4189 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4190 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4191 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4192 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4193 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4194 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4195 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4196 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4198 // VPMIN : Vector Pairwise Minimum
4199 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4200 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4201 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4202 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4203 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4204 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4205 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4206 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4207 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4208 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4209 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4210 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4211 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4212 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4214 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4216 // VRECPE : Vector Reciprocal Estimate
4217 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4218 IIC_VUNAD, "vrecpe", "u32",
4219 v2i32, v2i32, int_arm_neon_vrecpe>;
4220 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4221 IIC_VUNAQ, "vrecpe", "u32",
4222 v4i32, v4i32, int_arm_neon_vrecpe>;
4223 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4224 IIC_VUNAD, "vrecpe", "f32",
4225 v2f32, v2f32, int_arm_neon_vrecpe>;
4226 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4227 IIC_VUNAQ, "vrecpe", "f32",
4228 v4f32, v4f32, int_arm_neon_vrecpe>;
4230 // VRECPS : Vector Reciprocal Step
4231 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4232 IIC_VRECSD, "vrecps", "f32",
4233 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4234 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4235 IIC_VRECSQ, "vrecps", "f32",
4236 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4238 // VRSQRTE : Vector Reciprocal Square Root Estimate
4239 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4240 IIC_VUNAD, "vrsqrte", "u32",
4241 v2i32, v2i32, int_arm_neon_vrsqrte>;
4242 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4243 IIC_VUNAQ, "vrsqrte", "u32",
4244 v4i32, v4i32, int_arm_neon_vrsqrte>;
4245 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4246 IIC_VUNAD, "vrsqrte", "f32",
4247 v2f32, v2f32, int_arm_neon_vrsqrte>;
4248 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4249 IIC_VUNAQ, "vrsqrte", "f32",
4250 v4f32, v4f32, int_arm_neon_vrsqrte>;
4252 // VRSQRTS : Vector Reciprocal Square Root Step
4253 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4254 IIC_VRECSD, "vrsqrts", "f32",
4255 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4256 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4257 IIC_VRECSQ, "vrsqrts", "f32",
4258 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4262 // VSHL : Vector Shift
4263 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4264 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4265 "vshl", "s", int_arm_neon_vshifts>;
4266 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4267 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4268 "vshl", "u", int_arm_neon_vshiftu>;
4270 // VSHL : Vector Shift Left (Immediate)
4271 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4273 // VSHR : Vector Shift Right (Immediate)
4274 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4275 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4277 // VSHLL : Vector Shift Left Long
4278 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4279 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4281 // VSHLL : Vector Shift Left Long (with maximum shift count)
4282 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4283 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4284 ValueType OpTy, SDNode OpNode>
4285 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4286 ResTy, OpTy, OpNode> {
4287 let Inst{21-16} = op21_16;
4288 let DecoderMethod = "DecodeVSHLMaxInstruction";
4290 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4291 v8i16, v8i8, NEONvshlli>;
4292 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4293 v4i32, v4i16, NEONvshlli>;
4294 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4295 v2i64, v2i32, NEONvshlli>;
4297 // VSHRN : Vector Shift Right and Narrow
4298 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4301 // VRSHL : Vector Rounding Shift
4302 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4303 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4304 "vrshl", "s", int_arm_neon_vrshifts>;
4305 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4306 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4307 "vrshl", "u", int_arm_neon_vrshiftu>;
4308 // VRSHR : Vector Rounding Shift Right
4309 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4310 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4312 // VRSHRN : Vector Rounding Shift Right and Narrow
4313 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4316 // VQSHL : Vector Saturating Shift
4317 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4318 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4319 "vqshl", "s", int_arm_neon_vqshifts>;
4320 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4321 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4322 "vqshl", "u", int_arm_neon_vqshiftu>;
4323 // VQSHL : Vector Saturating Shift Left (Immediate)
4324 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4325 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4327 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4328 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4330 // VQSHRN : Vector Saturating Shift Right and Narrow
4331 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4333 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4336 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4337 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4340 // VQRSHL : Vector Saturating Rounding Shift
4341 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4342 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4343 "vqrshl", "s", int_arm_neon_vqrshifts>;
4344 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4345 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4346 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4348 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4349 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4351 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4354 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4355 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4358 // VSRA : Vector Shift Right and Accumulate
4359 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4360 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4361 // VRSRA : Vector Rounding Shift Right and Accumulate
4362 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4363 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4365 // VSLI : Vector Shift Left and Insert
4366 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4368 // VSRI : Vector Shift Right and Insert
4369 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4371 // Vector Absolute and Saturating Absolute.
4373 // VABS : Vector Absolute Value
4374 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4375 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4377 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4378 IIC_VUNAD, "vabs", "f32",
4379 v2f32, v2f32, int_arm_neon_vabs>;
4380 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4381 IIC_VUNAQ, "vabs", "f32",
4382 v4f32, v4f32, int_arm_neon_vabs>;
4384 // VQABS : Vector Saturating Absolute Value
4385 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4386 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4387 int_arm_neon_vqabs>;
4391 def vnegd : PatFrag<(ops node:$in),
4392 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4393 def vnegq : PatFrag<(ops node:$in),
4394 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4396 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4397 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4398 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4399 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4400 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4401 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4402 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4403 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4405 // VNEG : Vector Negate (integer)
4406 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4407 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4408 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4409 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4410 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4411 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4413 // VNEG : Vector Negate (floating-point)
4414 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4415 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4416 "vneg", "f32", "$Vd, $Vm", "",
4417 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4418 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4419 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4420 "vneg", "f32", "$Vd, $Vm", "",
4421 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4423 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4424 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4425 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4426 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4427 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4428 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4430 // VQNEG : Vector Saturating Negate
4431 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4432 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4433 int_arm_neon_vqneg>;
4435 // Vector Bit Counting Operations.
4437 // VCLS : Vector Count Leading Sign Bits
4438 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4439 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4441 // VCLZ : Vector Count Leading Zeros
4442 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4443 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4445 // VCNT : Vector Count One Bits
4446 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4447 IIC_VCNTiD, "vcnt", "8",
4448 v8i8, v8i8, int_arm_neon_vcnt>;
4449 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4450 IIC_VCNTiQ, "vcnt", "8",
4451 v16i8, v16i8, int_arm_neon_vcnt>;
4454 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4455 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4456 "vswp", "$Vd, $Vm", "", []>;
4457 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4458 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4459 "vswp", "$Vd, $Vm", "", []>;
4461 // Vector Move Operations.
4463 // VMOV : Vector Move (Register)
4464 def : InstAlias<"vmov${p} $Vd, $Vm",
4465 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4466 def : InstAlias<"vmov${p} $Vd, $Vm",
4467 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4469 // VMOV : Vector Move (Immediate)
4471 let isReMaterializable = 1 in {
4472 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4473 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4474 "vmov", "i8", "$Vd, $SIMM", "",
4475 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4476 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4477 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4478 "vmov", "i8", "$Vd, $SIMM", "",
4479 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4481 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4482 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4483 "vmov", "i16", "$Vd, $SIMM", "",
4484 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4485 let Inst{9} = SIMM{9};
4488 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4489 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4490 "vmov", "i16", "$Vd, $SIMM", "",
4491 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4492 let Inst{9} = SIMM{9};
4495 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4496 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4497 "vmov", "i32", "$Vd, $SIMM", "",
4498 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4499 let Inst{11-8} = SIMM{11-8};
4502 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4503 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4504 "vmov", "i32", "$Vd, $SIMM", "",
4505 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4506 let Inst{11-8} = SIMM{11-8};
4509 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4510 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4511 "vmov", "i64", "$Vd, $SIMM", "",
4512 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4513 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4514 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4515 "vmov", "i64", "$Vd, $SIMM", "",
4516 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4517 } // isReMaterializable
4519 // VMOV : Vector Get Lane (move scalar to ARM core register)
4521 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4522 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4523 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4524 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4526 let Inst{21} = lane{2};
4527 let Inst{6-5} = lane{1-0};
4529 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4530 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4531 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4532 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4534 let Inst{21} = lane{1};
4535 let Inst{6} = lane{0};
4537 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4538 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4539 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4540 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4542 let Inst{21} = lane{2};
4543 let Inst{6-5} = lane{1-0};
4545 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4546 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4547 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4548 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4550 let Inst{21} = lane{1};
4551 let Inst{6} = lane{0};
4553 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4554 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4555 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4556 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4558 let Inst{21} = lane{0};
4560 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4561 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4562 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4563 (DSubReg_i8_reg imm:$lane))),
4564 (SubReg_i8_lane imm:$lane))>;
4565 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4566 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4567 (DSubReg_i16_reg imm:$lane))),
4568 (SubReg_i16_lane imm:$lane))>;
4569 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4570 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4571 (DSubReg_i8_reg imm:$lane))),
4572 (SubReg_i8_lane imm:$lane))>;
4573 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4574 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4575 (DSubReg_i16_reg imm:$lane))),
4576 (SubReg_i16_lane imm:$lane))>;
4577 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4578 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4579 (DSubReg_i32_reg imm:$lane))),
4580 (SubReg_i32_lane imm:$lane))>;
4581 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4582 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4583 (SSubReg_f32_reg imm:$src2))>;
4584 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4585 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4586 (SSubReg_f32_reg imm:$src2))>;
4587 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4588 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4589 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4590 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4593 // VMOV : Vector Set Lane (move ARM core register to scalar)
4595 let Constraints = "$src1 = $V" in {
4596 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4597 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4598 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4599 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4600 GPR:$R, imm:$lane))]> {
4601 let Inst{21} = lane{2};
4602 let Inst{6-5} = lane{1-0};
4604 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4605 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4606 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4607 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4608 GPR:$R, imm:$lane))]> {
4609 let Inst{21} = lane{1};
4610 let Inst{6} = lane{0};
4612 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4613 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4614 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4615 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4616 GPR:$R, imm:$lane))]> {
4617 let Inst{21} = lane{0};
4620 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4621 (v16i8 (INSERT_SUBREG QPR:$src1,
4622 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4623 (DSubReg_i8_reg imm:$lane))),
4624 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4625 (DSubReg_i8_reg imm:$lane)))>;
4626 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4627 (v8i16 (INSERT_SUBREG QPR:$src1,
4628 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4629 (DSubReg_i16_reg imm:$lane))),
4630 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4631 (DSubReg_i16_reg imm:$lane)))>;
4632 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4633 (v4i32 (INSERT_SUBREG QPR:$src1,
4634 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4635 (DSubReg_i32_reg imm:$lane))),
4636 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4637 (DSubReg_i32_reg imm:$lane)))>;
4639 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4640 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4641 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4642 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4643 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4644 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4646 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4647 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4648 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4649 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4651 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4652 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4653 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4654 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4655 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4656 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4658 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4659 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4660 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4661 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4662 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4663 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4665 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4666 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4667 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4669 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4670 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4671 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4673 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4674 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4675 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4678 // VDUP : Vector Duplicate (from ARM core register to all elements)
4680 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4681 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4682 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4683 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4684 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4685 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4686 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4687 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4689 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4690 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4691 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4692 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4693 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4694 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4696 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4697 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4699 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4701 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4702 ValueType Ty, Operand IdxTy>
4703 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4704 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4705 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4707 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4708 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4709 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4710 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4711 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4712 VectorIndex32:$lane)))]>;
4714 // Inst{19-16} is partially specified depending on the element size.
4716 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4718 let Inst{19-17} = lane{2-0};
4720 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4722 let Inst{19-18} = lane{1-0};
4724 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4726 let Inst{19} = lane{0};
4728 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4730 let Inst{19-17} = lane{2-0};
4732 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4734 let Inst{19-18} = lane{1-0};
4736 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4738 let Inst{19} = lane{0};
4741 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4742 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4744 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4745 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4747 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4748 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4749 (DSubReg_i8_reg imm:$lane))),
4750 (SubReg_i8_lane imm:$lane)))>;
4751 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4752 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4753 (DSubReg_i16_reg imm:$lane))),
4754 (SubReg_i16_lane imm:$lane)))>;
4755 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4756 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4757 (DSubReg_i32_reg imm:$lane))),
4758 (SubReg_i32_lane imm:$lane)))>;
4759 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4760 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4761 (DSubReg_i32_reg imm:$lane))),
4762 (SubReg_i32_lane imm:$lane)))>;
4764 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4765 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4766 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4767 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4769 // VMOVN : Vector Narrowing Move
4770 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4771 "vmovn", "i", trunc>;
4772 // VQMOVN : Vector Saturating Narrowing Move
4773 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4774 "vqmovn", "s", int_arm_neon_vqmovns>;
4775 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4776 "vqmovn", "u", int_arm_neon_vqmovnu>;
4777 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4778 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4779 // VMOVL : Vector Lengthening Move
4780 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4781 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4783 // Vector Conversions.
4785 // VCVT : Vector Convert Between Floating-Point and Integers
4786 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4787 v2i32, v2f32, fp_to_sint>;
4788 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4789 v2i32, v2f32, fp_to_uint>;
4790 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4791 v2f32, v2i32, sint_to_fp>;
4792 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4793 v2f32, v2i32, uint_to_fp>;
4795 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4796 v4i32, v4f32, fp_to_sint>;
4797 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4798 v4i32, v4f32, fp_to_uint>;
4799 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4800 v4f32, v4i32, sint_to_fp>;
4801 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4802 v4f32, v4i32, uint_to_fp>;
4804 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4805 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4806 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4807 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4808 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4809 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4810 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4811 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4812 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4814 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4815 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4816 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4817 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4818 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4819 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4820 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4821 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4823 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4824 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4825 IIC_VUNAQ, "vcvt", "f16.f32",
4826 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4827 Requires<[HasNEON, HasFP16]>;
4828 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4829 IIC_VUNAQ, "vcvt", "f32.f16",
4830 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4831 Requires<[HasNEON, HasFP16]>;
4835 // VREV64 : Vector Reverse elements within 64-bit doublewords
4837 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4838 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4839 (ins DPR:$Vm), IIC_VMOVD,
4840 OpcodeStr, Dt, "$Vd, $Vm", "",
4841 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4842 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4843 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4844 (ins QPR:$Vm), IIC_VMOVQ,
4845 OpcodeStr, Dt, "$Vd, $Vm", "",
4846 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4848 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4849 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4850 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4851 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4853 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4854 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4855 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4856 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4858 // VREV32 : Vector Reverse elements within 32-bit words
4860 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4861 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4862 (ins DPR:$Vm), IIC_VMOVD,
4863 OpcodeStr, Dt, "$Vd, $Vm", "",
4864 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4865 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4866 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4867 (ins QPR:$Vm), IIC_VMOVQ,
4868 OpcodeStr, Dt, "$Vd, $Vm", "",
4869 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4871 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4872 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4874 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4875 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4877 // VREV16 : Vector Reverse elements within 16-bit halfwords
4879 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4880 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4881 (ins DPR:$Vm), IIC_VMOVD,
4882 OpcodeStr, Dt, "$Vd, $Vm", "",
4883 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4884 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4885 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4886 (ins QPR:$Vm), IIC_VMOVQ,
4887 OpcodeStr, Dt, "$Vd, $Vm", "",
4888 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4890 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4891 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4893 // Other Vector Shuffles.
4895 // Aligned extractions: really just dropping registers
4897 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4898 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4899 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4901 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4903 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4905 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4907 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4909 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4912 // VEXT : Vector Extract
4914 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4915 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4916 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4917 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4918 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4919 (Ty DPR:$Vm), imm:$index)))]> {
4921 let Inst{11-8} = index{3-0};
4924 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4925 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4926 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4927 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4928 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4929 (Ty QPR:$Vm), imm:$index)))]> {
4931 let Inst{11-8} = index{3-0};
4934 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4935 let Inst{11-8} = index{3-0};
4937 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4938 let Inst{11-9} = index{2-0};
4941 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4942 let Inst{11-10} = index{1-0};
4943 let Inst{9-8} = 0b00;
4945 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4948 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4950 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4951 let Inst{11-8} = index{3-0};
4953 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4954 let Inst{11-9} = index{2-0};
4957 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4958 let Inst{11-10} = index{1-0};
4959 let Inst{9-8} = 0b00;
4961 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4964 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4966 // VTRN : Vector Transpose
4968 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4969 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4970 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4972 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4973 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4974 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4976 // VUZP : Vector Unzip (Deinterleave)
4978 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4979 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4980 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4982 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4983 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4984 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4986 // VZIP : Vector Zip (Interleave)
4988 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4989 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4990 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4992 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4993 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4994 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4996 // Vector Table Lookup and Table Extension.
4998 // VTBL : Vector Table Lookup
4999 let DecoderMethod = "DecodeTBLInstruction" in {
5001 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5002 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5003 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5004 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5005 let hasExtraSrcRegAllocReq = 1 in {
5007 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5008 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5009 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
5011 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5012 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5013 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
5015 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5016 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
5018 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
5019 } // hasExtraSrcRegAllocReq = 1
5022 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5024 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5026 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5028 // VTBX : Vector Table Extension
5030 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5031 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5032 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5033 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5034 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5035 let hasExtraSrcRegAllocReq = 1 in {
5037 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5038 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5039 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
5041 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5042 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
5043 NVTBLFrm, IIC_VTBX3,
5044 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
5047 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
5048 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5049 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
5051 } // hasExtraSrcRegAllocReq = 1
5054 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5055 IIC_VTBX2, "$orig = $dst", []>;
5057 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5058 IIC_VTBX3, "$orig = $dst", []>;
5060 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5061 IIC_VTBX4, "$orig = $dst", []>;
5062 } // DecoderMethod = "DecodeTBLInstruction"
5064 //===----------------------------------------------------------------------===//
5065 // NEON instructions for single-precision FP math
5066 //===----------------------------------------------------------------------===//
5068 class N2VSPat<SDNode OpNode, NeonI Inst>
5069 : NEONFPPat<(f32 (OpNode SPR:$a)),
5071 (v2f32 (COPY_TO_REGCLASS (Inst
5073 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5074 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5076 class N3VSPat<SDNode OpNode, NeonI Inst>
5077 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5079 (v2f32 (COPY_TO_REGCLASS (Inst
5081 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5084 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5085 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5087 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5088 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5090 (v2f32 (COPY_TO_REGCLASS (Inst
5092 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5095 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5098 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5099 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5101 def : N3VSPat<fadd, VADDfd>;
5102 def : N3VSPat<fsub, VSUBfd>;
5103 def : N3VSPat<fmul, VMULfd>;
5104 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5105 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5106 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5107 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5108 def : N2VSPat<fabs, VABSfd>;
5109 def : N2VSPat<fneg, VNEGfd>;
5110 def : N3VSPat<NEONfmax, VMAXfd>;
5111 def : N3VSPat<NEONfmin, VMINfd>;
5112 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5113 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5114 def : N2VSPat<arm_sitof, VCVTs2fd>;
5115 def : N2VSPat<arm_uitof, VCVTu2fd>;
5117 //===----------------------------------------------------------------------===//
5118 // Non-Instruction Patterns
5119 //===----------------------------------------------------------------------===//
5122 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5123 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5124 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5125 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5126 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5127 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5128 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5129 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5130 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5131 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5132 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5133 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5134 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5135 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5136 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5137 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5138 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5139 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5140 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5141 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5142 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5143 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5144 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5145 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5146 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5147 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5148 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5149 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5150 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5151 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5153 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5154 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5155 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5156 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5157 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5158 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5159 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5160 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5161 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5162 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5163 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5164 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5165 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5166 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5167 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5168 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5169 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5170 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5171 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5172 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5173 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5174 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5175 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5176 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5177 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5178 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5179 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5180 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5181 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5182 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;