1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
77 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
78 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
79 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
82 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
83 [SDNPHasChain, SDNPMayLoad]>;
84 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
85 [SDNPHasChain, SDNPMayLoad]>;
86 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
87 [SDNPHasChain, SDNPMayLoad]>;
89 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
90 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
92 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
96 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
97 [SDNPHasChain, SDNPMayStore]>;
98 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
99 [SDNPHasChain, SDNPMayStore]>;
100 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
101 [SDNPHasChain, SDNPMayStore]>;
103 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
104 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
105 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
107 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
108 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
109 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
110 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
112 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
114 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
115 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
116 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
118 //===----------------------------------------------------------------------===//
119 // NEON operand definitions
120 //===----------------------------------------------------------------------===//
122 // addrmode_neonldstm := reg
124 /* TODO: Take advantage of vldm.
125 def addrmode_neonldstm : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
127 let PrintMethod = "printAddrNeonLdStMOperand";
128 let MIOperandInfo = (ops GPR, i32imm);
132 //===----------------------------------------------------------------------===//
133 // NEON load / store instructions
134 //===----------------------------------------------------------------------===//
136 /* TODO: Take advantage of vldm.
138 def VLDMD : NI<(outs),
139 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
141 "vldm${addr:submode} ${addr:base}, $dst1",
143 let Inst{27-25} = 0b110;
145 let Inst{11-9} = 0b101;
148 def VLDMS : NI<(outs),
149 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
151 "vldm${addr:submode} ${addr:base}, $dst1",
153 let Inst{27-25} = 0b110;
155 let Inst{11-9} = 0b101;
160 // Use vldmia to load a Q register as a D register pair.
161 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
163 "vldmia $addr, ${dst:dregpair}",
164 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
165 let Inst{27-25} = 0b110;
166 let Inst{24} = 0; // P bit
167 let Inst{23} = 1; // U bit
169 let Inst{11-9} = 0b101;
172 // Use vstmia to store a Q register as a D register pair.
173 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
175 "vstmia $addr, ${src:dregpair}",
176 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
177 let Inst{27-25} = 0b110;
178 let Inst{24} = 0; // P bit
179 let Inst{23} = 1; // U bit
181 let Inst{11-9} = 0b101;
184 // VLD1 : Vector Load (multiple single elements)
185 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
186 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
188 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
189 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
190 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
191 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
193 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
194 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
196 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
197 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
198 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
199 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
200 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
202 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
203 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
204 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
205 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
206 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
210 // VLD2 : Vector Load (multiple 2-element structures)
211 class VLD2D<string OpcodeStr>
212 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
214 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
216 def VLD2d8 : VLD2D<"vld2.8">;
217 def VLD2d16 : VLD2D<"vld2.16">;
218 def VLD2d32 : VLD2D<"vld2.32">;
220 // VLD3 : Vector Load (multiple 3-element structures)
221 class VLD3D<string OpcodeStr>
222 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
224 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
226 def VLD3d8 : VLD3D<"vld3.8">;
227 def VLD3d16 : VLD3D<"vld3.16">;
228 def VLD3d32 : VLD3D<"vld3.32">;
230 // VLD4 : Vector Load (multiple 4-element structures)
231 class VLD4D<string OpcodeStr>
232 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
233 (ins addrmode6:$addr),
235 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
237 def VLD4d8 : VLD4D<"vld4.8">;
238 def VLD4d16 : VLD4D<"vld4.16">;
239 def VLD4d32 : VLD4D<"vld4.32">;
242 // VST1 : Vector Store (multiple single elements)
243 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
244 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
246 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
247 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
248 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
249 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
251 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
252 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
254 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
255 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
256 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
257 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
258 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
260 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
261 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
262 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
263 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
264 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
266 let mayStore = 1 in {
268 // VST2 : Vector Store (multiple 2-element structures)
269 class VST2D<string OpcodeStr>
270 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
271 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
273 def VST2d8 : VST2D<"vst2.8">;
274 def VST2d16 : VST2D<"vst2.16">;
275 def VST2d32 : VST2D<"vst2.32">;
277 // VST3 : Vector Store (multiple 3-element structures)
278 class VST3D<string OpcodeStr>
279 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
281 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
283 def VST3d8 : VST3D<"vst3.8">;
284 def VST3d16 : VST3D<"vst3.16">;
285 def VST3d32 : VST3D<"vst3.32">;
287 // VST4 : Vector Store (multiple 4-element structures)
288 class VST4D<string OpcodeStr>
289 : NLdSt<(outs), (ins addrmode6:$addr,
290 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
291 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
293 def VST4d8 : VST4D<"vst4.8">;
294 def VST4d16 : VST4D<"vst4.16">;
295 def VST4d32 : VST4D<"vst4.32">;
299 //===----------------------------------------------------------------------===//
300 // NEON pattern fragments
301 //===----------------------------------------------------------------------===//
303 // Extract D sub-registers of Q registers.
304 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
305 def DSubReg_i8_reg : SDNodeXForm<imm, [{
306 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
308 def DSubReg_i16_reg : SDNodeXForm<imm, [{
309 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
311 def DSubReg_i32_reg : SDNodeXForm<imm, [{
312 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
314 def DSubReg_f64_reg : SDNodeXForm<imm, [{
315 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
318 // Extract S sub-registers of Q registers.
319 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
320 def SSubReg_f32_reg : SDNodeXForm<imm, [{
321 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
324 // Translate lane numbers from Q registers to D subregs.
325 def SubReg_i8_lane : SDNodeXForm<imm, [{
326 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
328 def SubReg_i16_lane : SDNodeXForm<imm, [{
329 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
331 def SubReg_i32_lane : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
335 //===----------------------------------------------------------------------===//
336 // Instruction Classes
337 //===----------------------------------------------------------------------===//
339 // Basic 2-register operations, both double- and quad-register.
340 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
341 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
342 ValueType ResTy, ValueType OpTy, SDNode OpNode>
343 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
344 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
345 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
346 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
347 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
348 ValueType ResTy, ValueType OpTy, SDNode OpNode>
349 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
350 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
351 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
353 // Basic 2-register operations, scalar single-precision.
354 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
355 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
356 ValueType ResTy, ValueType OpTy, SDNode OpNode>
357 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
358 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
359 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
361 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
362 : NEONFPPat<(ResTy (OpNode SPR:$a)),
364 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
367 // Basic 2-register intrinsics, both double- and quad-register.
368 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
369 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
370 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
371 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
372 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
373 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
374 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
375 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
376 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
377 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
378 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
379 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
381 // Basic 2-register intrinsics, scalar single-precision
382 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
383 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
384 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
385 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
386 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
387 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
389 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
390 : NEONFPPat<(f32 (OpNode SPR:$a)),
392 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
395 // Narrow 2-register intrinsics.
396 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
397 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
398 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
399 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
400 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
401 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
403 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
404 // derived from N2VImm instead of N2V because of the way the size is encoded.)
405 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
406 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
408 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
409 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
410 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
412 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
413 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
414 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
415 (ins DPR:$src1, DPR:$src2), NoItinerary,
416 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
417 "$src1 = $dst1, $src2 = $dst2", []>;
418 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
419 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
420 (ins QPR:$src1, QPR:$src2), NoItinerary,
421 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
422 "$src1 = $dst1, $src2 = $dst2", []>;
424 // Basic 3-register operations, both double- and quad-register.
425 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
426 string OpcodeStr, ValueType ResTy, ValueType OpTy,
427 SDNode OpNode, bit Commutable>
428 : N3V<op24, op23, op21_20, op11_8, 0, op4,
429 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
430 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
431 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
432 let isCommutable = Commutable;
434 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
435 string OpcodeStr, ValueType ResTy, ValueType OpTy,
436 SDNode OpNode, bit Commutable>
437 : N3V<op24, op23, op21_20, op11_8, 1, op4,
438 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
439 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
440 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
441 let isCommutable = Commutable;
444 // Basic 3-register operations, scalar single-precision
445 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
446 string OpcodeStr, ValueType ResTy, ValueType OpTy,
447 SDNode OpNode, bit Commutable>
448 : N3V<op24, op23, op21_20, op11_8, 0, op4,
449 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
450 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
451 let isCommutable = Commutable;
453 class N3VDsPat<SDNode OpNode, NeonI Inst>
454 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
456 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
457 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
460 // Basic 3-register intrinsics, both double- and quad-register.
461 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
462 string OpcodeStr, ValueType ResTy, ValueType OpTy,
463 Intrinsic IntOp, bit Commutable>
464 : N3V<op24, op23, op21_20, op11_8, 0, op4,
465 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
466 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
467 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
468 let isCommutable = Commutable;
470 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
471 string OpcodeStr, ValueType ResTy, ValueType OpTy,
472 Intrinsic IntOp, bit Commutable>
473 : N3V<op24, op23, op21_20, op11_8, 1, op4,
474 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
475 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
476 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
477 let isCommutable = Commutable;
480 // Multiply-Add/Sub operations, both double- and quad-register.
481 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
482 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
483 : N3V<op24, op23, op21_20, op11_8, 0, op4,
484 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
485 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
486 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
487 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
488 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
489 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
490 : N3V<op24, op23, op21_20, op11_8, 1, op4,
491 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
492 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
493 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
494 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
496 // Multiply-Add/Sub operations, scalar single-precision
497 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
498 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
499 : N3V<op24, op23, op21_20, op11_8, 0, op4,
500 (outs DPR_VFP2:$dst),
501 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
502 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
504 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
505 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
507 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
508 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
509 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
512 // Neon 3-argument intrinsics, both double- and quad-register.
513 // The destination register is also used as the first source operand register.
514 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
515 string OpcodeStr, ValueType ResTy, ValueType OpTy,
517 : N3V<op24, op23, op21_20, op11_8, 0, op4,
518 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
519 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
520 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
521 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
522 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
523 string OpcodeStr, ValueType ResTy, ValueType OpTy,
525 : N3V<op24, op23, op21_20, op11_8, 1, op4,
526 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
527 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
528 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
529 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
531 // Neon Long 3-argument intrinsic. The destination register is
532 // a quad-register and is also used as the first source operand register.
533 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
534 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
535 : N3V<op24, op23, op21_20, op11_8, 0, op4,
536 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
537 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
539 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
541 // Narrowing 3-register intrinsics.
542 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
543 string OpcodeStr, ValueType TyD, ValueType TyQ,
544 Intrinsic IntOp, bit Commutable>
545 : N3V<op24, op23, op21_20, op11_8, 0, op4,
546 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
547 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
548 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
549 let isCommutable = Commutable;
552 // Long 3-register intrinsics.
553 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
554 string OpcodeStr, ValueType TyQ, ValueType TyD,
555 Intrinsic IntOp, bit Commutable>
556 : N3V<op24, op23, op21_20, op11_8, 0, op4,
557 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
558 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
559 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
560 let isCommutable = Commutable;
563 // Wide 3-register intrinsics.
564 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
565 string OpcodeStr, ValueType TyQ, ValueType TyD,
566 Intrinsic IntOp, bit Commutable>
567 : N3V<op24, op23, op21_20, op11_8, 0, op4,
568 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
569 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
570 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
571 let isCommutable = Commutable;
574 // Pairwise long 2-register intrinsics, both double- and quad-register.
575 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
576 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
577 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
578 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
579 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
580 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
581 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
582 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
583 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
584 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
585 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
586 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
588 // Pairwise long 2-register accumulate intrinsics,
589 // both double- and quad-register.
590 // The destination register is also used as the first source operand register.
591 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
592 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
593 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
594 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
595 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
596 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
597 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
598 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
599 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
600 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
601 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
602 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
603 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
604 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
606 // Shift by immediate,
607 // both double- and quad-register.
608 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
609 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
610 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
611 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
612 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
613 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
614 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
615 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
616 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
617 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
618 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
619 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
621 // Long shift by immediate.
622 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
623 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
624 ValueType OpTy, SDNode OpNode>
625 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
626 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
627 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
628 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
629 (i32 imm:$SIMM))))]>;
631 // Narrow shift by immediate.
632 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
633 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
634 ValueType OpTy, SDNode OpNode>
635 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
636 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
637 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
638 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
639 (i32 imm:$SIMM))))]>;
641 // Shift right by immediate and accumulate,
642 // both double- and quad-register.
643 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
644 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
645 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
646 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
648 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
649 [(set DPR:$dst, (Ty (add DPR:$src1,
650 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
651 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
652 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
653 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
654 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
656 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
657 [(set QPR:$dst, (Ty (add QPR:$src1,
658 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
660 // Shift by immediate and insert,
661 // both double- and quad-register.
662 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
663 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
664 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
665 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
667 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
668 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
669 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
670 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
671 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
672 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
674 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
675 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
677 // Convert, with fractional bits immediate,
678 // both double- and quad-register.
679 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
680 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
682 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
683 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
684 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
685 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
686 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
687 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
689 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
690 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
691 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
692 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
694 //===----------------------------------------------------------------------===//
696 //===----------------------------------------------------------------------===//
698 // Neon 3-register vector operations.
700 // First with only element sizes of 8, 16 and 32 bits:
701 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
702 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
703 // 64-bit vector types.
704 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
705 v8i8, v8i8, OpNode, Commutable>;
706 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
707 v4i16, v4i16, OpNode, Commutable>;
708 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
709 v2i32, v2i32, OpNode, Commutable>;
711 // 128-bit vector types.
712 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
713 v16i8, v16i8, OpNode, Commutable>;
714 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
715 v8i16, v8i16, OpNode, Commutable>;
716 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
717 v4i32, v4i32, OpNode, Commutable>;
720 // ....then also with element size 64 bits:
721 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
722 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
723 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
724 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
725 v1i64, v1i64, OpNode, Commutable>;
726 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
727 v2i64, v2i64, OpNode, Commutable>;
731 // Neon Narrowing 2-register vector intrinsics,
732 // source operand element sizes of 16, 32 and 64 bits:
733 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
734 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
736 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
737 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
738 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
739 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
740 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
741 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
745 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
746 // source operand element sizes of 16, 32 and 64 bits:
747 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
748 bit op4, string OpcodeStr, Intrinsic IntOp> {
749 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
750 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
751 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
752 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
753 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
754 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
758 // Neon 3-register vector intrinsics.
760 // First with only element sizes of 16 and 32 bits:
761 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
762 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
763 // 64-bit vector types.
764 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
765 v4i16, v4i16, IntOp, Commutable>;
766 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
767 v2i32, v2i32, IntOp, Commutable>;
769 // 128-bit vector types.
770 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
771 v8i16, v8i16, IntOp, Commutable>;
772 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
773 v4i32, v4i32, IntOp, Commutable>;
776 // ....then also with element size of 8 bits:
777 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
778 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
779 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
780 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
781 v8i8, v8i8, IntOp, Commutable>;
782 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
783 v16i8, v16i8, IntOp, Commutable>;
786 // ....then also with element size of 64 bits:
787 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
788 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
789 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
790 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
791 v1i64, v1i64, IntOp, Commutable>;
792 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
793 v2i64, v2i64, IntOp, Commutable>;
797 // Neon Narrowing 3-register vector intrinsics,
798 // source operand element sizes of 16, 32 and 64 bits:
799 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
800 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
801 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
802 v8i8, v8i16, IntOp, Commutable>;
803 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
804 v4i16, v4i32, IntOp, Commutable>;
805 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
806 v2i32, v2i64, IntOp, Commutable>;
810 // Neon Long 3-register vector intrinsics.
812 // First with only element sizes of 16 and 32 bits:
813 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
814 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
815 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
816 v4i32, v4i16, IntOp, Commutable>;
817 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
818 v2i64, v2i32, IntOp, Commutable>;
821 // ....then also with element size of 8 bits:
822 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
823 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
824 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
825 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
826 v8i16, v8i8, IntOp, Commutable>;
830 // Neon Wide 3-register vector intrinsics,
831 // source operand element sizes of 8, 16 and 32 bits:
832 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
833 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
834 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
835 v8i16, v8i8, IntOp, Commutable>;
836 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
837 v4i32, v4i16, IntOp, Commutable>;
838 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
839 v2i64, v2i32, IntOp, Commutable>;
843 // Neon Multiply-Op vector operations,
844 // element sizes of 8, 16 and 32 bits:
845 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
846 string OpcodeStr, SDNode OpNode> {
847 // 64-bit vector types.
848 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
849 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
850 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
851 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
852 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
853 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
855 // 128-bit vector types.
856 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
857 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
858 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
859 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
860 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
861 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
865 // Neon 3-argument intrinsics,
866 // element sizes of 8, 16 and 32 bits:
867 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
868 string OpcodeStr, Intrinsic IntOp> {
869 // 64-bit vector types.
870 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
871 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
872 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
873 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
874 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
875 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
877 // 128-bit vector types.
878 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
879 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
880 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
881 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
882 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
883 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
887 // Neon Long 3-argument intrinsics.
889 // First with only element sizes of 16 and 32 bits:
890 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
891 string OpcodeStr, Intrinsic IntOp> {
892 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
893 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
894 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
895 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
898 // ....then also with element size of 8 bits:
899 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
900 string OpcodeStr, Intrinsic IntOp>
901 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
902 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
903 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
907 // Neon 2-register vector intrinsics,
908 // element sizes of 8, 16 and 32 bits:
909 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
910 bits<5> op11_7, bit op4, string OpcodeStr,
912 // 64-bit vector types.
913 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
914 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
915 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
916 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
917 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
918 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
920 // 128-bit vector types.
921 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
922 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
923 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
924 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
925 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
926 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
930 // Neon Pairwise long 2-register intrinsics,
931 // element sizes of 8, 16 and 32 bits:
932 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
933 bits<5> op11_7, bit op4,
934 string OpcodeStr, Intrinsic IntOp> {
935 // 64-bit vector types.
936 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
937 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
938 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
939 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
940 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
941 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
943 // 128-bit vector types.
944 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
945 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
946 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
947 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
948 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
949 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
953 // Neon Pairwise long 2-register accumulate intrinsics,
954 // element sizes of 8, 16 and 32 bits:
955 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
956 bits<5> op11_7, bit op4,
957 string OpcodeStr, Intrinsic IntOp> {
958 // 64-bit vector types.
959 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
960 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
961 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
962 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
963 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
964 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
966 // 128-bit vector types.
967 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
968 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
969 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
970 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
971 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
972 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
976 // Neon 2-register vector shift by immediate,
977 // element sizes of 8, 16, 32 and 64 bits:
978 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
979 string OpcodeStr, SDNode OpNode> {
980 // 64-bit vector types.
981 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
982 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
983 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
984 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
985 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
986 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
987 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
988 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
990 // 128-bit vector types.
991 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
992 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
993 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
994 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
995 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
996 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
997 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
998 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1002 // Neon Shift-Accumulate vector operations,
1003 // element sizes of 8, 16, 32 and 64 bits:
1004 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1005 string OpcodeStr, SDNode ShOp> {
1006 // 64-bit vector types.
1007 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1008 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1009 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1010 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1011 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1012 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1013 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1014 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1016 // 128-bit vector types.
1017 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1018 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1019 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1020 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1021 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1022 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1023 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1024 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1028 // Neon Shift-Insert vector operations,
1029 // element sizes of 8, 16, 32 and 64 bits:
1030 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1031 string OpcodeStr, SDNode ShOp> {
1032 // 64-bit vector types.
1033 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1034 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1035 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1036 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1037 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1038 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1039 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1040 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1042 // 128-bit vector types.
1043 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1044 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1045 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1046 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1047 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1048 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1049 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1050 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1053 //===----------------------------------------------------------------------===//
1054 // Instruction Definitions.
1055 //===----------------------------------------------------------------------===//
1057 // Vector Add Operations.
1059 // VADD : Vector Add (integer and floating-point)
1060 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1061 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1062 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1063 // VADDL : Vector Add Long (Q = D + D)
1064 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1065 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1066 // VADDW : Vector Add Wide (Q = Q + D)
1067 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1068 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1069 // VHADD : Vector Halving Add
1070 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1071 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1072 // VRHADD : Vector Rounding Halving Add
1073 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1074 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1075 // VQADD : Vector Saturating Add
1076 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1077 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1078 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1079 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1080 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1081 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1083 // Vector Multiply Operations.
1085 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1086 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1087 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1088 int_arm_neon_vmulp, 1>;
1089 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1090 int_arm_neon_vmulp, 1>;
1091 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1092 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1093 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1094 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1095 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1096 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1097 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1098 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1099 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1100 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1101 int_arm_neon_vmullp, 1>;
1102 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1103 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1105 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1107 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1108 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1109 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1110 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1111 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1112 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1113 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1114 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1115 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1116 // VMLS : Vector Multiply Subtract (integer and floating-point)
1117 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1118 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1119 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1120 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1121 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1122 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1123 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1124 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1126 // Vector Subtract Operations.
1128 // VSUB : Vector Subtract (integer and floating-point)
1129 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1130 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1131 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1132 // VSUBL : Vector Subtract Long (Q = D - D)
1133 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1134 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1135 // VSUBW : Vector Subtract Wide (Q = Q - D)
1136 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1137 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1138 // VHSUB : Vector Halving Subtract
1139 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1140 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1141 // VQSUB : Vector Saturing Subtract
1142 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1143 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1144 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1145 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1146 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1147 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1149 // Vector Comparisons.
1151 // VCEQ : Vector Compare Equal
1152 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1153 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1154 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1155 // VCGE : Vector Compare Greater Than or Equal
1156 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1157 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1158 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1159 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1160 // VCGT : Vector Compare Greater Than
1161 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1162 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1163 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1164 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1165 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1166 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1167 int_arm_neon_vacged, 0>;
1168 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1169 int_arm_neon_vacgeq, 0>;
1170 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1171 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1172 int_arm_neon_vacgtd, 0>;
1173 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1174 int_arm_neon_vacgtq, 0>;
1175 // VTST : Vector Test Bits
1176 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1178 // Vector Bitwise Operations.
1180 // VAND : Vector Bitwise AND
1181 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1182 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1184 // VEOR : Vector Bitwise Exclusive OR
1185 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1186 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1188 // VORR : Vector Bitwise OR
1189 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1190 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1192 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1193 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1194 (ins DPR:$src1, DPR:$src2), NoItinerary,
1195 "vbic\t$dst, $src1, $src2", "",
1196 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1197 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1198 (ins QPR:$src1, QPR:$src2), NoItinerary,
1199 "vbic\t$dst, $src1, $src2", "",
1200 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1202 // VORN : Vector Bitwise OR NOT
1203 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1204 (ins DPR:$src1, DPR:$src2), NoItinerary,
1205 "vorn\t$dst, $src1, $src2", "",
1206 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1207 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1208 (ins QPR:$src1, QPR:$src2), NoItinerary,
1209 "vorn\t$dst, $src1, $src2", "",
1210 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1212 // VMVN : Vector Bitwise NOT
1213 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1214 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1215 "vmvn\t$dst, $src", "",
1216 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1217 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1218 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1219 "vmvn\t$dst, $src", "",
1220 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1221 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1222 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1224 // VBSL : Vector Bitwise Select
1225 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1226 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1227 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1229 (v2i32 (or (and DPR:$src2, DPR:$src1),
1230 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1231 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1232 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1233 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1235 (v4i32 (or (and QPR:$src2, QPR:$src1),
1236 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1238 // VBIF : Vector Bitwise Insert if False
1239 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1240 // VBIT : Vector Bitwise Insert if True
1241 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1242 // These are not yet implemented. The TwoAddress pass will not go looking
1243 // for equivalent operations with different register constraints; it just
1246 // Vector Absolute Differences.
1248 // VABD : Vector Absolute Difference
1249 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1250 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1251 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1252 int_arm_neon_vabds, 0>;
1253 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1254 int_arm_neon_vabds, 0>;
1256 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1257 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1258 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1260 // VABA : Vector Absolute Difference and Accumulate
1261 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1262 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1264 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1265 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1266 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1268 // Vector Maximum and Minimum.
1270 // VMAX : Vector Maximum
1271 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1272 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1273 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1274 int_arm_neon_vmaxs, 1>;
1275 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1276 int_arm_neon_vmaxs, 1>;
1278 // VMIN : Vector Minimum
1279 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1280 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1281 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1282 int_arm_neon_vmins, 1>;
1283 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1284 int_arm_neon_vmins, 1>;
1286 // Vector Pairwise Operations.
1288 // VPADD : Vector Pairwise Add
1289 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1290 int_arm_neon_vpadd, 0>;
1291 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1292 int_arm_neon_vpadd, 0>;
1293 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1294 int_arm_neon_vpadd, 0>;
1295 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1296 int_arm_neon_vpadd, 0>;
1298 // VPADDL : Vector Pairwise Add Long
1299 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1300 int_arm_neon_vpaddls>;
1301 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1302 int_arm_neon_vpaddlu>;
1304 // VPADAL : Vector Pairwise Add and Accumulate Long
1305 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1306 int_arm_neon_vpadals>;
1307 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1308 int_arm_neon_vpadalu>;
1310 // VPMAX : Vector Pairwise Maximum
1311 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1312 int_arm_neon_vpmaxs, 0>;
1313 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1314 int_arm_neon_vpmaxs, 0>;
1315 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1316 int_arm_neon_vpmaxs, 0>;
1317 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1318 int_arm_neon_vpmaxu, 0>;
1319 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1320 int_arm_neon_vpmaxu, 0>;
1321 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1322 int_arm_neon_vpmaxu, 0>;
1323 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1324 int_arm_neon_vpmaxs, 0>;
1326 // VPMIN : Vector Pairwise Minimum
1327 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1328 int_arm_neon_vpmins, 0>;
1329 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1330 int_arm_neon_vpmins, 0>;
1331 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1332 int_arm_neon_vpmins, 0>;
1333 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1334 int_arm_neon_vpminu, 0>;
1335 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1336 int_arm_neon_vpminu, 0>;
1337 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1338 int_arm_neon_vpminu, 0>;
1339 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1340 int_arm_neon_vpmins, 0>;
1342 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1344 // VRECPE : Vector Reciprocal Estimate
1345 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1346 v2i32, v2i32, int_arm_neon_vrecpe>;
1347 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1348 v4i32, v4i32, int_arm_neon_vrecpe>;
1349 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1350 v2f32, v2f32, int_arm_neon_vrecpe>;
1351 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1352 v4f32, v4f32, int_arm_neon_vrecpe>;
1354 // VRECPS : Vector Reciprocal Step
1355 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1356 int_arm_neon_vrecps, 1>;
1357 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1358 int_arm_neon_vrecps, 1>;
1360 // VRSQRTE : Vector Reciprocal Square Root Estimate
1361 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1362 v2i32, v2i32, int_arm_neon_vrsqrte>;
1363 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1364 v4i32, v4i32, int_arm_neon_vrsqrte>;
1365 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1366 v2f32, v2f32, int_arm_neon_vrsqrte>;
1367 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1368 v4f32, v4f32, int_arm_neon_vrsqrte>;
1370 // VRSQRTS : Vector Reciprocal Square Root Step
1371 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1372 int_arm_neon_vrsqrts, 1>;
1373 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1374 int_arm_neon_vrsqrts, 1>;
1378 // VSHL : Vector Shift
1379 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1380 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1381 // VSHL : Vector Shift Left (Immediate)
1382 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1383 // VSHR : Vector Shift Right (Immediate)
1384 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1385 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1387 // VSHLL : Vector Shift Left Long
1388 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1389 v8i16, v8i8, NEONvshlls>;
1390 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1391 v4i32, v4i16, NEONvshlls>;
1392 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1393 v2i64, v2i32, NEONvshlls>;
1394 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1395 v8i16, v8i8, NEONvshllu>;
1396 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1397 v4i32, v4i16, NEONvshllu>;
1398 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1399 v2i64, v2i32, NEONvshllu>;
1401 // VSHLL : Vector Shift Left Long (with maximum shift count)
1402 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1403 v8i16, v8i8, NEONvshlli>;
1404 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1405 v4i32, v4i16, NEONvshlli>;
1406 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1407 v2i64, v2i32, NEONvshlli>;
1409 // VSHRN : Vector Shift Right and Narrow
1410 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1411 v8i8, v8i16, NEONvshrn>;
1412 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1413 v4i16, v4i32, NEONvshrn>;
1414 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1415 v2i32, v2i64, NEONvshrn>;
1417 // VRSHL : Vector Rounding Shift
1418 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1419 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1420 // VRSHR : Vector Rounding Shift Right
1421 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1422 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1424 // VRSHRN : Vector Rounding Shift Right and Narrow
1425 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1426 v8i8, v8i16, NEONvrshrn>;
1427 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1428 v4i16, v4i32, NEONvrshrn>;
1429 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1430 v2i32, v2i64, NEONvrshrn>;
1432 // VQSHL : Vector Saturating Shift
1433 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1434 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1435 // VQSHL : Vector Saturating Shift Left (Immediate)
1436 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1437 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1438 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1439 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1441 // VQSHRN : Vector Saturating Shift Right and Narrow
1442 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1443 v8i8, v8i16, NEONvqshrns>;
1444 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1445 v4i16, v4i32, NEONvqshrns>;
1446 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1447 v2i32, v2i64, NEONvqshrns>;
1448 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1449 v8i8, v8i16, NEONvqshrnu>;
1450 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1451 v4i16, v4i32, NEONvqshrnu>;
1452 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1453 v2i32, v2i64, NEONvqshrnu>;
1455 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1456 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1457 v8i8, v8i16, NEONvqshrnsu>;
1458 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1459 v4i16, v4i32, NEONvqshrnsu>;
1460 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1461 v2i32, v2i64, NEONvqshrnsu>;
1463 // VQRSHL : Vector Saturating Rounding Shift
1464 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1465 int_arm_neon_vqrshifts, 0>;
1466 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1467 int_arm_neon_vqrshiftu, 0>;
1469 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1470 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1471 v8i8, v8i16, NEONvqrshrns>;
1472 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1473 v4i16, v4i32, NEONvqrshrns>;
1474 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1475 v2i32, v2i64, NEONvqrshrns>;
1476 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1477 v8i8, v8i16, NEONvqrshrnu>;
1478 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1479 v4i16, v4i32, NEONvqrshrnu>;
1480 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1481 v2i32, v2i64, NEONvqrshrnu>;
1483 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1484 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1485 v8i8, v8i16, NEONvqrshrnsu>;
1486 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1487 v4i16, v4i32, NEONvqrshrnsu>;
1488 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1489 v2i32, v2i64, NEONvqrshrnsu>;
1491 // VSRA : Vector Shift Right and Accumulate
1492 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1493 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1494 // VRSRA : Vector Rounding Shift Right and Accumulate
1495 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1496 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1498 // VSLI : Vector Shift Left and Insert
1499 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1500 // VSRI : Vector Shift Right and Insert
1501 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1503 // Vector Absolute and Saturating Absolute.
1505 // VABS : Vector Absolute Value
1506 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1508 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1509 v2f32, v2f32, int_arm_neon_vabs>;
1510 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1511 v4f32, v4f32, int_arm_neon_vabs>;
1513 // VQABS : Vector Saturating Absolute Value
1514 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1515 int_arm_neon_vqabs>;
1519 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1520 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1522 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1523 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1525 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1526 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1527 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1528 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1530 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1531 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1533 // VNEG : Vector Negate
1534 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1535 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1536 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1537 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1538 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1539 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1541 // VNEG : Vector Negate (floating-point)
1542 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1543 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1544 "vneg.f32\t$dst, $src", "",
1545 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1546 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1547 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1548 "vneg.f32\t$dst, $src", "",
1549 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1551 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1552 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1553 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1554 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1555 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1556 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1558 // VQNEG : Vector Saturating Negate
1559 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1560 int_arm_neon_vqneg>;
1562 // Vector Bit Counting Operations.
1564 // VCLS : Vector Count Leading Sign Bits
1565 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1567 // VCLZ : Vector Count Leading Zeros
1568 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1570 // VCNT : Vector Count One Bits
1571 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1572 v8i8, v8i8, int_arm_neon_vcnt>;
1573 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1574 v16i8, v16i8, int_arm_neon_vcnt>;
1576 // Vector Move Operations.
1578 // VMOV : Vector Move (Register)
1580 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1581 NoItinerary, "vmov\t$dst, $src", "", []>;
1582 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1583 NoItinerary, "vmov\t$dst, $src", "", []>;
1585 // VMOV : Vector Move (Immediate)
1587 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1588 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1589 return ARM::getVMOVImm(N, 1, *CurDAG);
1591 def vmovImm8 : PatLeaf<(build_vector), [{
1592 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1595 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1596 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1597 return ARM::getVMOVImm(N, 2, *CurDAG);
1599 def vmovImm16 : PatLeaf<(build_vector), [{
1600 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1601 }], VMOV_get_imm16>;
1603 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1604 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1605 return ARM::getVMOVImm(N, 4, *CurDAG);
1607 def vmovImm32 : PatLeaf<(build_vector), [{
1608 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1609 }], VMOV_get_imm32>;
1611 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1612 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1613 return ARM::getVMOVImm(N, 8, *CurDAG);
1615 def vmovImm64 : PatLeaf<(build_vector), [{
1616 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1617 }], VMOV_get_imm64>;
1619 // Note: Some of the cmode bits in the following VMOV instructions need to
1620 // be encoded based on the immed values.
1622 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1623 (ins i8imm:$SIMM), NoItinerary,
1624 "vmov.i8\t$dst, $SIMM", "",
1625 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1626 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1627 (ins i8imm:$SIMM), NoItinerary,
1628 "vmov.i8\t$dst, $SIMM", "",
1629 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1631 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1632 (ins i16imm:$SIMM), NoItinerary,
1633 "vmov.i16\t$dst, $SIMM", "",
1634 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1635 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1636 (ins i16imm:$SIMM), NoItinerary,
1637 "vmov.i16\t$dst, $SIMM", "",
1638 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1640 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1641 (ins i32imm:$SIMM), NoItinerary,
1642 "vmov.i32\t$dst, $SIMM", "",
1643 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1644 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1645 (ins i32imm:$SIMM), NoItinerary,
1646 "vmov.i32\t$dst, $SIMM", "",
1647 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1649 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1650 (ins i64imm:$SIMM), NoItinerary,
1651 "vmov.i64\t$dst, $SIMM", "",
1652 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1653 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1654 (ins i64imm:$SIMM), NoItinerary,
1655 "vmov.i64\t$dst, $SIMM", "",
1656 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1658 // VMOV : Vector Get Lane (move scalar to ARM core register)
1660 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1661 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1662 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1663 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1665 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1666 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1667 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1668 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1670 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1671 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1672 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1673 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1675 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1676 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1677 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1678 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1680 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1681 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1682 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1683 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1685 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1686 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1687 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1688 (DSubReg_i8_reg imm:$lane))),
1689 (SubReg_i8_lane imm:$lane))>;
1690 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1691 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1692 (DSubReg_i16_reg imm:$lane))),
1693 (SubReg_i16_lane imm:$lane))>;
1694 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1695 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1696 (DSubReg_i8_reg imm:$lane))),
1697 (SubReg_i8_lane imm:$lane))>;
1698 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1699 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1700 (DSubReg_i16_reg imm:$lane))),
1701 (SubReg_i16_lane imm:$lane))>;
1702 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1703 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1704 (DSubReg_i32_reg imm:$lane))),
1705 (SubReg_i32_lane imm:$lane))>;
1706 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1707 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1708 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1709 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1710 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1711 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1714 // VMOV : Vector Set Lane (move ARM core register to scalar)
1716 let Constraints = "$src1 = $dst" in {
1717 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1718 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1719 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1720 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1721 GPR:$src2, imm:$lane))]>;
1722 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1723 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1724 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1725 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1726 GPR:$src2, imm:$lane))]>;
1727 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1728 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1729 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1730 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1731 GPR:$src2, imm:$lane))]>;
1733 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1734 (v16i8 (INSERT_SUBREG QPR:$src1,
1735 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1736 (DSubReg_i8_reg imm:$lane))),
1737 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1738 (DSubReg_i8_reg imm:$lane)))>;
1739 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1740 (v8i16 (INSERT_SUBREG QPR:$src1,
1741 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1742 (DSubReg_i16_reg imm:$lane))),
1743 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1744 (DSubReg_i16_reg imm:$lane)))>;
1745 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1746 (v4i32 (INSERT_SUBREG QPR:$src1,
1747 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1748 (DSubReg_i32_reg imm:$lane))),
1749 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1750 (DSubReg_i32_reg imm:$lane)))>;
1752 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1753 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1755 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1756 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1757 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1758 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1760 // VDUP : Vector Duplicate (from ARM core register to all elements)
1762 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1763 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1764 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1765 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1766 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1767 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1768 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1769 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1771 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1772 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1773 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1774 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1775 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1776 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1778 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1779 NoItinerary, "vdup", ".32\t$dst, $src",
1780 [(set DPR:$dst, (v2f32 (NEONvdup
1781 (f32 (bitconvert GPR:$src)))))]>;
1782 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1783 NoItinerary, "vdup", ".32\t$dst, $src",
1784 [(set QPR:$dst, (v4f32 (NEONvdup
1785 (f32 (bitconvert GPR:$src)))))]>;
1787 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1789 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1790 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1791 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1792 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1793 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
1795 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1796 ValueType ResTy, ValueType OpTy>
1797 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1798 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1799 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1800 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
1802 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1803 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1804 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1805 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1806 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1807 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1808 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1809 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1811 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
1812 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
1813 (DSubReg_i8_reg imm:$lane))),
1814 (SubReg_i8_lane imm:$lane)))>;
1815 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
1816 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
1817 (DSubReg_i16_reg imm:$lane))),
1818 (SubReg_i16_lane imm:$lane)))>;
1819 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
1820 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
1821 (DSubReg_i32_reg imm:$lane))),
1822 (SubReg_i32_lane imm:$lane)))>;
1823 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
1824 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
1825 (DSubReg_i32_reg imm:$lane))),
1826 (SubReg_i32_lane imm:$lane)))>;
1828 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1829 (outs DPR:$dst), (ins SPR:$src),
1830 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1831 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
1833 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1834 (outs QPR:$dst), (ins SPR:$src),
1835 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1836 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
1838 // VMOVN : Vector Narrowing Move
1839 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1840 int_arm_neon_vmovn>;
1841 // VQMOVN : Vector Saturating Narrowing Move
1842 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1843 int_arm_neon_vqmovns>;
1844 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1845 int_arm_neon_vqmovnu>;
1846 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1847 int_arm_neon_vqmovnsu>;
1848 // VMOVL : Vector Lengthening Move
1849 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1850 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1852 // Vector Conversions.
1854 // VCVT : Vector Convert Between Floating-Point and Integers
1855 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1856 v2i32, v2f32, fp_to_sint>;
1857 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1858 v2i32, v2f32, fp_to_uint>;
1859 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1860 v2f32, v2i32, sint_to_fp>;
1861 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1862 v2f32, v2i32, uint_to_fp>;
1864 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1865 v4i32, v4f32, fp_to_sint>;
1866 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1867 v4i32, v4f32, fp_to_uint>;
1868 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1869 v4f32, v4i32, sint_to_fp>;
1870 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1871 v4f32, v4i32, uint_to_fp>;
1873 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1874 // Note: Some of the opcode bits in the following VCVT instructions need to
1875 // be encoded based on the immed values.
1876 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1877 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1878 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1879 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1880 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1881 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1882 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1883 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1885 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1886 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1887 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1888 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1889 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1890 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1891 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1892 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1896 // VREV64 : Vector Reverse elements within 64-bit doublewords
1898 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1899 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1900 (ins DPR:$src), NoItinerary,
1901 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1902 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1903 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1904 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1905 (ins QPR:$src), NoItinerary,
1906 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1907 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1909 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1910 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1911 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1912 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1914 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1915 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1916 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1917 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1919 // VREV32 : Vector Reverse elements within 32-bit words
1921 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1922 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1923 (ins DPR:$src), NoItinerary,
1924 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1925 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
1926 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1927 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1928 (ins QPR:$src), NoItinerary,
1929 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1930 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
1932 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1933 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1935 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1936 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1938 // VREV16 : Vector Reverse elements within 16-bit halfwords
1940 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1941 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1942 (ins DPR:$src), NoItinerary,
1943 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1944 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
1945 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1946 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1947 (ins QPR:$src), NoItinerary,
1948 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1949 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
1951 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1952 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1954 // Other Vector Shuffles.
1956 // VEXT : Vector Extract
1958 class VEXTd<string OpcodeStr, ValueType Ty>
1959 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
1960 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
1961 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
1962 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
1963 (Ty DPR:$rhs), imm:$index)))]>;
1965 class VEXTq<string OpcodeStr, ValueType Ty>
1966 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
1967 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
1968 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
1969 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
1970 (Ty QPR:$rhs), imm:$index)))]>;
1972 def VEXTd8 : VEXTd<"vext.8", v8i8>;
1973 def VEXTd16 : VEXTd<"vext.16", v4i16>;
1974 def VEXTd32 : VEXTd<"vext.32", v2i32>;
1975 def VEXTdf : VEXTd<"vext.32", v2f32>;
1977 def VEXTq8 : VEXTq<"vext.8", v16i8>;
1978 def VEXTq16 : VEXTq<"vext.16", v8i16>;
1979 def VEXTq32 : VEXTq<"vext.32", v4i32>;
1980 def VEXTqf : VEXTq<"vext.32", v4f32>;
1982 // VTRN : Vector Transpose
1984 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1985 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1986 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1988 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1989 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1990 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1992 // VUZP : Vector Unzip (Deinterleave)
1994 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1995 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1996 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1998 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1999 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
2000 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
2002 // VZIP : Vector Zip (Interleave)
2004 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2005 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2006 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2008 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
2009 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
2010 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
2012 // Vector Table Lookup and Table Extension.
2014 // VTBL : Vector Table Lookup
2016 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2017 (ins DPR:$tbl1, DPR:$src), NoItinerary,
2018 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2019 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2021 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2022 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2023 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2024 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2025 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2027 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2028 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2029 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2030 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2031 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2033 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2034 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2035 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2036 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2037 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2039 // VTBX : Vector Table Extension
2041 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2042 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2043 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2044 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2045 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2047 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2048 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2049 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2050 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2051 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2053 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2054 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2055 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2056 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2057 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2059 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2060 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2061 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2062 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2063 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2065 //===----------------------------------------------------------------------===//
2066 // NEON instructions for single-precision FP math
2067 //===----------------------------------------------------------------------===//
2069 // These need separate instructions because they must use DPR_VFP2 register
2070 // class which have SPR sub-registers.
2072 // Vector Add Operations used for single-precision FP
2073 let neverHasSideEffects = 1 in
2074 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2075 def : N3VDsPat<fadd, VADDfd_sfp>;
2077 // Vector Sub Operations used for single-precision FP
2078 let neverHasSideEffects = 1 in
2079 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2080 def : N3VDsPat<fsub, VSUBfd_sfp>;
2082 // Vector Multiply Operations used for single-precision FP
2083 let neverHasSideEffects = 1 in
2084 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2085 def : N3VDsPat<fmul, VMULfd_sfp>;
2087 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2088 let neverHasSideEffects = 1 in
2089 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2090 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2092 let neverHasSideEffects = 1 in
2093 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2094 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2096 // Vector Absolute used for single-precision FP
2097 let neverHasSideEffects = 1 in
2098 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2099 v2f32, v2f32, int_arm_neon_vabs>;
2100 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2102 // Vector Negate used for single-precision FP
2103 let neverHasSideEffects = 1 in
2104 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2105 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2106 "vneg.f32\t$dst, $src", "", []>;
2107 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2109 // Vector Convert between single-precision FP and integer
2110 let neverHasSideEffects = 1 in
2111 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2112 v2i32, v2f32, fp_to_sint>;
2113 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2115 let neverHasSideEffects = 1 in
2116 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2117 v2i32, v2f32, fp_to_uint>;
2118 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2120 let neverHasSideEffects = 1 in
2121 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2122 v2f32, v2i32, sint_to_fp>;
2123 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2125 let neverHasSideEffects = 1 in
2126 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2127 v2f32, v2i32, uint_to_fp>;
2128 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2130 //===----------------------------------------------------------------------===//
2131 // Non-Instruction Patterns
2132 //===----------------------------------------------------------------------===//
2135 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2136 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2137 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2138 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2139 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2140 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2141 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2142 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2143 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2144 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2145 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2146 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2147 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2148 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2149 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2150 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2151 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2152 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2153 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2154 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2155 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2156 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2157 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2158 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2159 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2160 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2161 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2162 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2163 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2164 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2166 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2167 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2168 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2169 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2170 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2171 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2172 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2173 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2174 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2175 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2176 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2177 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2178 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2179 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2180 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2181 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2182 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2183 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2184 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2185 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2186 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2187 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2188 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2189 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2190 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2191 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2192 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2193 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2194 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2195 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;