1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
402 //===----------------------------------------------------------------------===//
403 // NEON-specific DAG Nodes.
404 //===----------------------------------------------------------------------===//
406 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
407 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
409 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
410 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
411 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
412 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
413 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
414 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
415 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
416 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
417 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
418 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
419 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
421 // Types for vector shift by immediates. The "SHX" version is for long and
422 // narrow operations where the source and destination vectors have different
423 // types. The "SHINS" version is for shift and insert operations.
424 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
426 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
428 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
429 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
431 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
432 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
433 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
434 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
435 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
436 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
437 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
439 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
440 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
441 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
443 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
444 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
445 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
446 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
447 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
448 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
450 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
451 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
452 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
454 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
455 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
457 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
459 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
460 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
462 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
463 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
464 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
465 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
467 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
469 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
470 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
472 def NEONvbsl : SDNode<"ARMISD::VBSL",
473 SDTypeProfile<1, 3, [SDTCisVec<0>,
476 SDTCisSameAs<0, 3>]>>;
478 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
480 // VDUPLANE can produce a quad-register result from a double-register source,
481 // so the result is not constrained to match the source.
482 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
483 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
486 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
487 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
488 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
490 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
491 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
492 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
493 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
495 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
497 SDTCisSameAs<0, 3>]>;
498 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
499 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
500 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
502 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
503 SDTCisSameAs<1, 2>]>;
504 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
505 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
507 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
508 SDTCisSameAs<0, 2>]>;
509 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
510 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
512 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
513 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
514 unsigned EltBits = 0;
515 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
516 return (EltBits == 32 && EltVal == 0);
519 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
520 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
521 unsigned EltBits = 0;
522 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
523 return (EltBits == 8 && EltVal == 0xff);
526 //===----------------------------------------------------------------------===//
527 // NEON load / store instructions
528 //===----------------------------------------------------------------------===//
530 // Use VLDM to load a Q register as a D register pair.
531 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
533 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
535 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
537 // Use VSTM to store a Q register as a D register pair.
538 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
540 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
542 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
544 // Classes for VLD* pseudo-instructions with multi-register operands.
545 // These are expanded to real instructions after register allocation.
546 class VLDQPseudo<InstrItinClass itin>
547 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
548 class VLDQWBPseudo<InstrItinClass itin>
549 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
550 (ins addrmode6:$addr, am6offset:$offset), itin,
552 class VLDQWBfixedPseudo<InstrItinClass itin>
553 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
554 (ins addrmode6:$addr), itin,
556 class VLDQWBregisterPseudo<InstrItinClass itin>
557 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
558 (ins addrmode6:$addr, rGPR:$offset), itin,
561 class VLDQQPseudo<InstrItinClass itin>
562 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
563 class VLDQQWBPseudo<InstrItinClass itin>
564 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
565 (ins addrmode6:$addr, am6offset:$offset), itin,
567 class VLDQQWBfixedPseudo<InstrItinClass itin>
568 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
569 (ins addrmode6:$addr), itin,
571 class VLDQQWBregisterPseudo<InstrItinClass itin>
572 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
573 (ins addrmode6:$addr, rGPR:$offset), itin,
577 class VLDQQQQPseudo<InstrItinClass itin>
578 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
580 class VLDQQQQWBPseudo<InstrItinClass itin>
581 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
583 "$addr.addr = $wb, $src = $dst">;
585 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
587 // VLD1 : Vector Load (multiple single elements)
588 class VLD1D<bits<4> op7_4, string Dt>
589 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
590 (ins addrmode6:$Rn), IIC_VLD1,
591 "vld1", Dt, "$Vd, $Rn", "", []> {
594 let DecoderMethod = "DecodeVLDInstruction";
596 class VLD1Q<bits<4> op7_4, string Dt>
597 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
598 (ins addrmode6:$Rn), IIC_VLD1x2,
599 "vld1", Dt, "$Vd, $Rn", "", []> {
601 let Inst{5-4} = Rn{5-4};
602 let DecoderMethod = "DecodeVLDInstruction";
605 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
606 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
607 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
608 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
610 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
611 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
612 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
613 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
615 // ...with address register writeback:
616 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
617 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
618 (ins addrmode6:$Rn), IIC_VLD1u,
619 "vld1", Dt, "$Vd, $Rn!",
620 "$Rn.addr = $wb", []> {
621 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
623 let DecoderMethod = "DecodeVLDInstruction";
624 let AsmMatchConverter = "cvtVLDwbFixed";
626 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
627 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
628 "vld1", Dt, "$Vd, $Rn, $Rm",
629 "$Rn.addr = $wb", []> {
631 let DecoderMethod = "DecodeVLDInstruction";
632 let AsmMatchConverter = "cvtVLDwbRegister";
635 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
636 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
637 (ins addrmode6:$Rn), IIC_VLD1x2u,
638 "vld1", Dt, "$Vd, $Rn!",
639 "$Rn.addr = $wb", []> {
640 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
641 let Inst{5-4} = Rn{5-4};
642 let DecoderMethod = "DecodeVLDInstruction";
643 let AsmMatchConverter = "cvtVLDwbFixed";
645 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
646 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
647 "vld1", Dt, "$Vd, $Rn, $Rm",
648 "$Rn.addr = $wb", []> {
649 let Inst{5-4} = Rn{5-4};
650 let DecoderMethod = "DecodeVLDInstruction";
651 let AsmMatchConverter = "cvtVLDwbRegister";
655 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
656 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
657 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
658 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
659 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
660 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
661 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
662 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
664 // ...with 3 registers
665 class VLD1D3<bits<4> op7_4, string Dt>
666 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
667 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
668 "$Vd, $Rn", "", []> {
671 let DecoderMethod = "DecodeVLDInstruction";
673 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
674 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
675 (ins addrmode6:$Rn), IIC_VLD1x2u,
676 "vld1", Dt, "$Vd, $Rn!",
677 "$Rn.addr = $wb", []> {
678 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
680 let DecoderMethod = "DecodeVLDInstruction";
681 let AsmMatchConverter = "cvtVLDwbFixed";
683 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
684 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
685 "vld1", Dt, "$Vd, $Rn, $Rm",
686 "$Rn.addr = $wb", []> {
688 let DecoderMethod = "DecodeVLDInstruction";
689 let AsmMatchConverter = "cvtVLDwbRegister";
693 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
694 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
695 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
696 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
698 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
699 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
700 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
701 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
703 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
705 // ...with 4 registers
706 class VLD1D4<bits<4> op7_4, string Dt>
707 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
708 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
709 "$Vd, $Rn", "", []> {
711 let Inst{5-4} = Rn{5-4};
712 let DecoderMethod = "DecodeVLDInstruction";
714 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
715 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
716 (ins addrmode6:$Rn), IIC_VLD1x2u,
717 "vld1", Dt, "$Vd, $Rn!",
718 "$Rn.addr = $wb", []> {
719 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
720 let Inst{5-4} = Rn{5-4};
721 let DecoderMethod = "DecodeVLDInstruction";
722 let AsmMatchConverter = "cvtVLDwbFixed";
724 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
725 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
726 "vld1", Dt, "$Vd, $Rn, $Rm",
727 "$Rn.addr = $wb", []> {
728 let Inst{5-4} = Rn{5-4};
729 let DecoderMethod = "DecodeVLDInstruction";
730 let AsmMatchConverter = "cvtVLDwbRegister";
734 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
735 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
736 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
737 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
739 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
740 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
741 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
742 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
744 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
746 // VLD2 : Vector Load (multiple 2-element structures)
747 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
749 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
750 (ins addrmode6:$Rn), itin,
751 "vld2", Dt, "$Vd, $Rn", "", []> {
753 let Inst{5-4} = Rn{5-4};
754 let DecoderMethod = "DecodeVLDInstruction";
757 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
758 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
759 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
761 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
762 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
763 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
765 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
766 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
767 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
769 // ...with address register writeback:
770 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
771 RegisterOperand VdTy, InstrItinClass itin> {
772 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
773 (ins addrmode6:$Rn), itin,
774 "vld2", Dt, "$Vd, $Rn!",
775 "$Rn.addr = $wb", []> {
776 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
777 let Inst{5-4} = Rn{5-4};
778 let DecoderMethod = "DecodeVLDInstruction";
779 let AsmMatchConverter = "cvtVLDwbFixed";
781 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
782 (ins addrmode6:$Rn, rGPR:$Rm), itin,
783 "vld2", Dt, "$Vd, $Rn, $Rm",
784 "$Rn.addr = $wb", []> {
785 let Inst{5-4} = Rn{5-4};
786 let DecoderMethod = "DecodeVLDInstruction";
787 let AsmMatchConverter = "cvtVLDwbRegister";
791 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
792 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
793 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
795 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
796 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
797 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
799 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
800 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
801 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
802 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
803 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
804 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
806 // ...with double-spaced registers
807 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
808 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
809 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
810 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
811 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
812 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
814 // VLD3 : Vector Load (multiple 3-element structures)
815 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
816 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
817 (ins addrmode6:$Rn), IIC_VLD3,
818 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
821 let DecoderMethod = "DecodeVLDInstruction";
824 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
825 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
826 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
828 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
829 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
830 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
832 // ...with address register writeback:
833 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
834 : NLdSt<0, 0b10, op11_8, op7_4,
835 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
836 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
837 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
838 "$Rn.addr = $wb", []> {
840 let DecoderMethod = "DecodeVLDInstruction";
843 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
844 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
845 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
847 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
848 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
849 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
851 // ...with double-spaced registers:
852 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
853 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
854 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
855 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
856 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
857 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
859 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
860 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
861 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
863 // ...alternate versions to be allocated odd register numbers:
864 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
865 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
866 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
868 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
869 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
870 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
872 // VLD4 : Vector Load (multiple 4-element structures)
873 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
874 : NLdSt<0, 0b10, op11_8, op7_4,
875 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
876 (ins addrmode6:$Rn), IIC_VLD4,
877 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
879 let Inst{5-4} = Rn{5-4};
880 let DecoderMethod = "DecodeVLDInstruction";
883 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
884 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
885 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
887 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
888 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
889 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
891 // ...with address register writeback:
892 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
893 : NLdSt<0, 0b10, op11_8, op7_4,
894 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
895 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
896 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
897 "$Rn.addr = $wb", []> {
898 let Inst{5-4} = Rn{5-4};
899 let DecoderMethod = "DecodeVLDInstruction";
902 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
903 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
904 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
906 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
907 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
908 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
910 // ...with double-spaced registers:
911 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
912 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
913 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
914 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
915 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
916 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
918 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
919 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
920 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
922 // ...alternate versions to be allocated odd register numbers:
923 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
924 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
925 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
927 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
928 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
929 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
931 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
933 // Classes for VLD*LN pseudo-instructions with multi-register operands.
934 // These are expanded to real instructions after register allocation.
935 class VLDQLNPseudo<InstrItinClass itin>
936 : PseudoNLdSt<(outs QPR:$dst),
937 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
938 itin, "$src = $dst">;
939 class VLDQLNWBPseudo<InstrItinClass itin>
940 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
941 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
942 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
943 class VLDQQLNPseudo<InstrItinClass itin>
944 : PseudoNLdSt<(outs QQPR:$dst),
945 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
946 itin, "$src = $dst">;
947 class VLDQQLNWBPseudo<InstrItinClass itin>
948 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
949 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
950 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
951 class VLDQQQQLNPseudo<InstrItinClass itin>
952 : PseudoNLdSt<(outs QQQQPR:$dst),
953 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
954 itin, "$src = $dst">;
955 class VLDQQQQLNWBPseudo<InstrItinClass itin>
956 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
957 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
958 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
960 // VLD1LN : Vector Load (single element to one lane)
961 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
963 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
964 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
965 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
967 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
968 (i32 (LoadOp addrmode6:$Rn)),
971 let DecoderMethod = "DecodeVLD1LN";
973 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
975 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
976 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
977 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
979 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
980 (i32 (LoadOp addrmode6oneL32:$Rn)),
983 let DecoderMethod = "DecodeVLD1LN";
985 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
986 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
987 (i32 (LoadOp addrmode6:$addr)),
991 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
992 let Inst{7-5} = lane{2-0};
994 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
995 let Inst{7-6} = lane{1-0};
996 let Inst{5-4} = Rn{5-4};
998 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
999 let Inst{7} = lane{0};
1000 let Inst{5-4} = Rn{5-4};
1003 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1004 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1005 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1007 def : Pat<(vector_insert (v2f32 DPR:$src),
1008 (f32 (load addrmode6:$addr)), imm:$lane),
1009 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1010 def : Pat<(vector_insert (v4f32 QPR:$src),
1011 (f32 (load addrmode6:$addr)), imm:$lane),
1012 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1014 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1016 // ...with address register writeback:
1017 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1018 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1019 (ins addrmode6:$Rn, am6offset:$Rm,
1020 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1021 "\\{$Vd[$lane]\\}, $Rn$Rm",
1022 "$src = $Vd, $Rn.addr = $wb", []> {
1023 let DecoderMethod = "DecodeVLD1LN";
1026 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1027 let Inst{7-5} = lane{2-0};
1029 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1030 let Inst{7-6} = lane{1-0};
1031 let Inst{4} = Rn{4};
1033 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1034 let Inst{7} = lane{0};
1035 let Inst{5} = Rn{4};
1036 let Inst{4} = Rn{4};
1039 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1040 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1041 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1043 // VLD2LN : Vector Load (single 2-element structure to one lane)
1044 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1045 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1046 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1047 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1048 "$src1 = $Vd, $src2 = $dst2", []> {
1050 let Inst{4} = Rn{4};
1051 let DecoderMethod = "DecodeVLD2LN";
1054 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1055 let Inst{7-5} = lane{2-0};
1057 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1058 let Inst{7-6} = lane{1-0};
1060 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1061 let Inst{7} = lane{0};
1064 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1065 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1066 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1068 // ...with double-spaced registers:
1069 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1070 let Inst{7-6} = lane{1-0};
1072 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1073 let Inst{7} = lane{0};
1076 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1077 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1079 // ...with address register writeback:
1080 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1081 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1082 (ins addrmode6:$Rn, am6offset:$Rm,
1083 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1084 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1085 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1086 let Inst{4} = Rn{4};
1087 let DecoderMethod = "DecodeVLD2LN";
1090 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1091 let Inst{7-5} = lane{2-0};
1093 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1094 let Inst{7-6} = lane{1-0};
1096 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1097 let Inst{7} = lane{0};
1100 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1101 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1102 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1104 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1105 let Inst{7-6} = lane{1-0};
1107 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1108 let Inst{7} = lane{0};
1111 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1112 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1114 // VLD3LN : Vector Load (single 3-element structure to one lane)
1115 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1116 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1117 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1118 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1119 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1120 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1122 let DecoderMethod = "DecodeVLD3LN";
1125 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1126 let Inst{7-5} = lane{2-0};
1128 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1129 let Inst{7-6} = lane{1-0};
1131 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1132 let Inst{7} = lane{0};
1135 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1136 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1137 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1139 // ...with double-spaced registers:
1140 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1141 let Inst{7-6} = lane{1-0};
1143 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1144 let Inst{7} = lane{0};
1147 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1148 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1150 // ...with address register writeback:
1151 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1152 : NLdStLn<1, 0b10, op11_8, op7_4,
1153 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1154 (ins addrmode6:$Rn, am6offset:$Rm,
1155 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1156 IIC_VLD3lnu, "vld3", Dt,
1157 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1158 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1160 let DecoderMethod = "DecodeVLD3LN";
1163 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1164 let Inst{7-5} = lane{2-0};
1166 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1167 let Inst{7-6} = lane{1-0};
1169 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1170 let Inst{7} = lane{0};
1173 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1174 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1175 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1177 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1178 let Inst{7-6} = lane{1-0};
1180 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1181 let Inst{7} = lane{0};
1184 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1185 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1187 // VLD4LN : Vector Load (single 4-element structure to one lane)
1188 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1189 : NLdStLn<1, 0b10, op11_8, op7_4,
1190 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1191 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1192 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1193 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1194 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1196 let Inst{4} = Rn{4};
1197 let DecoderMethod = "DecodeVLD4LN";
1200 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1201 let Inst{7-5} = lane{2-0};
1203 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1204 let Inst{7-6} = lane{1-0};
1206 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1207 let Inst{7} = lane{0};
1208 let Inst{5} = Rn{5};
1211 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1212 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1213 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1215 // ...with double-spaced registers:
1216 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1217 let Inst{7-6} = lane{1-0};
1219 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1220 let Inst{7} = lane{0};
1221 let Inst{5} = Rn{5};
1224 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1225 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1227 // ...with address register writeback:
1228 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1229 : NLdStLn<1, 0b10, op11_8, op7_4,
1230 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1231 (ins addrmode6:$Rn, am6offset:$Rm,
1232 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1233 IIC_VLD4lnu, "vld4", Dt,
1234 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1235 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1237 let Inst{4} = Rn{4};
1238 let DecoderMethod = "DecodeVLD4LN" ;
1241 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1242 let Inst{7-5} = lane{2-0};
1244 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1245 let Inst{7-6} = lane{1-0};
1247 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1248 let Inst{7} = lane{0};
1249 let Inst{5} = Rn{5};
1252 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1253 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1254 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1256 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1257 let Inst{7-6} = lane{1-0};
1259 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1260 let Inst{7} = lane{0};
1261 let Inst{5} = Rn{5};
1264 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1265 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1267 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1269 // VLD1DUP : Vector Load (single element to all lanes)
1270 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1271 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1272 (ins addrmode6dup:$Rn),
1273 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1274 [(set VecListOneDAllLanes:$Vd,
1275 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1277 let Inst{4} = Rn{4};
1278 let DecoderMethod = "DecodeVLD1DupInstruction";
1280 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1281 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1282 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1284 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1285 (VLD1DUPd32 addrmode6:$addr)>;
1287 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1288 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1289 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1290 "vld1", Dt, "$Vd, $Rn", "",
1291 [(set VecListDPairAllLanes:$Vd,
1292 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1294 let Inst{4} = Rn{4};
1295 let DecoderMethod = "DecodeVLD1DupInstruction";
1298 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1299 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1300 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1302 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1303 (VLD1DUPq32 addrmode6:$addr)>;
1305 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1306 // ...with address register writeback:
1307 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1308 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1309 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1310 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1311 "vld1", Dt, "$Vd, $Rn!",
1312 "$Rn.addr = $wb", []> {
1313 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1314 let Inst{4} = Rn{4};
1315 let DecoderMethod = "DecodeVLD1DupInstruction";
1316 let AsmMatchConverter = "cvtVLDwbFixed";
1318 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1319 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1320 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1321 "vld1", Dt, "$Vd, $Rn, $Rm",
1322 "$Rn.addr = $wb", []> {
1323 let Inst{4} = Rn{4};
1324 let DecoderMethod = "DecodeVLD1DupInstruction";
1325 let AsmMatchConverter = "cvtVLDwbRegister";
1328 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1329 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1330 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1331 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1332 "vld1", Dt, "$Vd, $Rn!",
1333 "$Rn.addr = $wb", []> {
1334 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1335 let Inst{4} = Rn{4};
1336 let DecoderMethod = "DecodeVLD1DupInstruction";
1337 let AsmMatchConverter = "cvtVLDwbFixed";
1339 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1340 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1341 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1342 "vld1", Dt, "$Vd, $Rn, $Rm",
1343 "$Rn.addr = $wb", []> {
1344 let Inst{4} = Rn{4};
1345 let DecoderMethod = "DecodeVLD1DupInstruction";
1346 let AsmMatchConverter = "cvtVLDwbRegister";
1350 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1351 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1352 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1354 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1355 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1356 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1358 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1359 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1360 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1361 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1362 "vld2", Dt, "$Vd, $Rn", "", []> {
1364 let Inst{4} = Rn{4};
1365 let DecoderMethod = "DecodeVLD2DupInstruction";
1368 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1369 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1370 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1372 // ...with double-spaced registers
1373 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1374 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1375 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1377 // ...with address register writeback:
1378 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1379 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1380 (outs VdTy:$Vd, GPR:$wb),
1381 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1382 "vld2", Dt, "$Vd, $Rn!",
1383 "$Rn.addr = $wb", []> {
1384 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1385 let Inst{4} = Rn{4};
1386 let DecoderMethod = "DecodeVLD2DupInstruction";
1387 let AsmMatchConverter = "cvtVLDwbFixed";
1389 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1390 (outs VdTy:$Vd, GPR:$wb),
1391 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1392 "vld2", Dt, "$Vd, $Rn, $Rm",
1393 "$Rn.addr = $wb", []> {
1394 let Inst{4} = Rn{4};
1395 let DecoderMethod = "DecodeVLD2DupInstruction";
1396 let AsmMatchConverter = "cvtVLDwbRegister";
1400 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1401 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1402 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1404 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1405 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1406 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1408 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1409 class VLD3DUP<bits<4> op7_4, string Dt>
1410 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1411 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1412 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1415 let DecoderMethod = "DecodeVLD3DupInstruction";
1418 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1419 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1420 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1422 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1423 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1424 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1426 // ...with double-spaced registers (not used for codegen):
1427 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1428 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1429 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1431 // ...with address register writeback:
1432 class VLD3DUPWB<bits<4> op7_4, string Dt>
1433 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1434 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1435 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1436 "$Rn.addr = $wb", []> {
1438 let DecoderMethod = "DecodeVLD3DupInstruction";
1441 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1442 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1443 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1445 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1446 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1447 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1449 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1450 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1451 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1453 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1454 class VLD4DUP<bits<4> op7_4, string Dt>
1455 : NLdSt<1, 0b10, 0b1111, op7_4,
1456 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1457 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1458 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1460 let Inst{4} = Rn{4};
1461 let DecoderMethod = "DecodeVLD4DupInstruction";
1464 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1465 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1466 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1468 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1469 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1470 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1472 // ...with double-spaced registers (not used for codegen):
1473 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1474 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1475 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1477 // ...with address register writeback:
1478 class VLD4DUPWB<bits<4> op7_4, string Dt>
1479 : NLdSt<1, 0b10, 0b1111, op7_4,
1480 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1481 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1482 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1483 "$Rn.addr = $wb", []> {
1484 let Inst{4} = Rn{4};
1485 let DecoderMethod = "DecodeVLD4DupInstruction";
1488 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1489 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1490 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1492 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1493 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1494 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1496 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1497 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1498 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1500 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1502 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1504 // Classes for VST* pseudo-instructions with multi-register operands.
1505 // These are expanded to real instructions after register allocation.
1506 class VSTQPseudo<InstrItinClass itin>
1507 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1508 class VSTQWBPseudo<InstrItinClass itin>
1509 : PseudoNLdSt<(outs GPR:$wb),
1510 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1511 "$addr.addr = $wb">;
1512 class VSTQWBfixedPseudo<InstrItinClass itin>
1513 : PseudoNLdSt<(outs GPR:$wb),
1514 (ins addrmode6:$addr, QPR:$src), itin,
1515 "$addr.addr = $wb">;
1516 class VSTQWBregisterPseudo<InstrItinClass itin>
1517 : PseudoNLdSt<(outs GPR:$wb),
1518 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1519 "$addr.addr = $wb">;
1520 class VSTQQPseudo<InstrItinClass itin>
1521 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1522 class VSTQQWBPseudo<InstrItinClass itin>
1523 : PseudoNLdSt<(outs GPR:$wb),
1524 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1525 "$addr.addr = $wb">;
1526 class VSTQQWBfixedPseudo<InstrItinClass itin>
1527 : PseudoNLdSt<(outs GPR:$wb),
1528 (ins addrmode6:$addr, QQPR:$src), itin,
1529 "$addr.addr = $wb">;
1530 class VSTQQWBregisterPseudo<InstrItinClass itin>
1531 : PseudoNLdSt<(outs GPR:$wb),
1532 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1533 "$addr.addr = $wb">;
1535 class VSTQQQQPseudo<InstrItinClass itin>
1536 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1537 class VSTQQQQWBPseudo<InstrItinClass itin>
1538 : PseudoNLdSt<(outs GPR:$wb),
1539 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1540 "$addr.addr = $wb">;
1542 // VST1 : Vector Store (multiple single elements)
1543 class VST1D<bits<4> op7_4, string Dt>
1544 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1545 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1547 let Inst{4} = Rn{4};
1548 let DecoderMethod = "DecodeVSTInstruction";
1550 class VST1Q<bits<4> op7_4, string Dt>
1551 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1552 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1554 let Inst{5-4} = Rn{5-4};
1555 let DecoderMethod = "DecodeVSTInstruction";
1558 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1559 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1560 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1561 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1563 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1564 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1565 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1566 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1568 // ...with address register writeback:
1569 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1570 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1571 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1572 "vst1", Dt, "$Vd, $Rn!",
1573 "$Rn.addr = $wb", []> {
1574 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1575 let Inst{4} = Rn{4};
1576 let DecoderMethod = "DecodeVSTInstruction";
1577 let AsmMatchConverter = "cvtVSTwbFixed";
1579 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1580 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1582 "vst1", Dt, "$Vd, $Rn, $Rm",
1583 "$Rn.addr = $wb", []> {
1584 let Inst{4} = Rn{4};
1585 let DecoderMethod = "DecodeVSTInstruction";
1586 let AsmMatchConverter = "cvtVSTwbRegister";
1589 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1590 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1591 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1592 "vst1", Dt, "$Vd, $Rn!",
1593 "$Rn.addr = $wb", []> {
1594 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1595 let Inst{5-4} = Rn{5-4};
1596 let DecoderMethod = "DecodeVSTInstruction";
1597 let AsmMatchConverter = "cvtVSTwbFixed";
1599 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1600 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1602 "vst1", Dt, "$Vd, $Rn, $Rm",
1603 "$Rn.addr = $wb", []> {
1604 let Inst{5-4} = Rn{5-4};
1605 let DecoderMethod = "DecodeVSTInstruction";
1606 let AsmMatchConverter = "cvtVSTwbRegister";
1610 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1611 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1612 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1613 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1615 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1616 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1617 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1618 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1620 // ...with 3 registers
1621 class VST1D3<bits<4> op7_4, string Dt>
1622 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1623 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1624 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1626 let Inst{4} = Rn{4};
1627 let DecoderMethod = "DecodeVSTInstruction";
1629 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1630 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1631 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1632 "vst1", Dt, "$Vd, $Rn!",
1633 "$Rn.addr = $wb", []> {
1634 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1635 let Inst{5-4} = Rn{5-4};
1636 let DecoderMethod = "DecodeVSTInstruction";
1637 let AsmMatchConverter = "cvtVSTwbFixed";
1639 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1640 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1642 "vst1", Dt, "$Vd, $Rn, $Rm",
1643 "$Rn.addr = $wb", []> {
1644 let Inst{5-4} = Rn{5-4};
1645 let DecoderMethod = "DecodeVSTInstruction";
1646 let AsmMatchConverter = "cvtVSTwbRegister";
1650 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1651 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1652 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1653 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1655 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1656 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1657 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1658 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1660 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1661 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1662 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1664 // ...with 4 registers
1665 class VST1D4<bits<4> op7_4, string Dt>
1666 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1667 (ins addrmode6:$Rn, VecListFourD:$Vd),
1668 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1671 let Inst{5-4} = Rn{5-4};
1672 let DecoderMethod = "DecodeVSTInstruction";
1674 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1675 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1676 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1677 "vst1", Dt, "$Vd, $Rn!",
1678 "$Rn.addr = $wb", []> {
1679 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1680 let Inst{5-4} = Rn{5-4};
1681 let DecoderMethod = "DecodeVSTInstruction";
1682 let AsmMatchConverter = "cvtVSTwbFixed";
1684 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1685 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1687 "vst1", Dt, "$Vd, $Rn, $Rm",
1688 "$Rn.addr = $wb", []> {
1689 let Inst{5-4} = Rn{5-4};
1690 let DecoderMethod = "DecodeVSTInstruction";
1691 let AsmMatchConverter = "cvtVSTwbRegister";
1695 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1696 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1697 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1698 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1700 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1701 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1702 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1703 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1705 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1706 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1707 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1709 // VST2 : Vector Store (multiple 2-element structures)
1710 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1711 InstrItinClass itin>
1712 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1713 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1715 let Inst{5-4} = Rn{5-4};
1716 let DecoderMethod = "DecodeVSTInstruction";
1719 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1720 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1721 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1723 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1724 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1725 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1727 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1728 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1729 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1731 // ...with address register writeback:
1732 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1733 RegisterOperand VdTy> {
1734 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1735 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1736 "vst2", Dt, "$Vd, $Rn!",
1737 "$Rn.addr = $wb", []> {
1738 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1739 let Inst{5-4} = Rn{5-4};
1740 let DecoderMethod = "DecodeVSTInstruction";
1741 let AsmMatchConverter = "cvtVSTwbFixed";
1743 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1744 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1745 "vst2", Dt, "$Vd, $Rn, $Rm",
1746 "$Rn.addr = $wb", []> {
1747 let Inst{5-4} = Rn{5-4};
1748 let DecoderMethod = "DecodeVSTInstruction";
1749 let AsmMatchConverter = "cvtVSTwbRegister";
1752 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1753 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1755 "vst2", Dt, "$Vd, $Rn!",
1756 "$Rn.addr = $wb", []> {
1757 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1758 let Inst{5-4} = Rn{5-4};
1759 let DecoderMethod = "DecodeVSTInstruction";
1760 let AsmMatchConverter = "cvtVSTwbFixed";
1762 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1763 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1765 "vst2", Dt, "$Vd, $Rn, $Rm",
1766 "$Rn.addr = $wb", []> {
1767 let Inst{5-4} = Rn{5-4};
1768 let DecoderMethod = "DecodeVSTInstruction";
1769 let AsmMatchConverter = "cvtVSTwbRegister";
1773 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1774 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1775 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1777 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1778 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1779 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1781 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1782 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1783 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1784 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1785 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1786 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1788 // ...with double-spaced registers
1789 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1790 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1791 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1792 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1793 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1794 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1796 // VST3 : Vector Store (multiple 3-element structures)
1797 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1798 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1799 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1800 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1802 let Inst{4} = Rn{4};
1803 let DecoderMethod = "DecodeVSTInstruction";
1806 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1807 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1808 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1810 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1811 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1812 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1814 // ...with address register writeback:
1815 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1816 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1817 (ins addrmode6:$Rn, am6offset:$Rm,
1818 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1819 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1820 "$Rn.addr = $wb", []> {
1821 let Inst{4} = Rn{4};
1822 let DecoderMethod = "DecodeVSTInstruction";
1825 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1826 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1827 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1829 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1830 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1831 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1833 // ...with double-spaced registers:
1834 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1835 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1836 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1837 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1838 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1839 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1841 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1842 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1843 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1845 // ...alternate versions to be allocated odd register numbers:
1846 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1847 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1848 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1850 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1851 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1852 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1854 // VST4 : Vector Store (multiple 4-element structures)
1855 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1856 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1857 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1858 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1861 let Inst{5-4} = Rn{5-4};
1862 let DecoderMethod = "DecodeVSTInstruction";
1865 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1866 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1867 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1869 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1870 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1871 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1873 // ...with address register writeback:
1874 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1875 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1876 (ins addrmode6:$Rn, am6offset:$Rm,
1877 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1878 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1879 "$Rn.addr = $wb", []> {
1880 let Inst{5-4} = Rn{5-4};
1881 let DecoderMethod = "DecodeVSTInstruction";
1884 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1885 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1886 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1888 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1889 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1890 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1892 // ...with double-spaced registers:
1893 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1894 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1895 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1896 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1897 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1898 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1900 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1901 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1902 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1904 // ...alternate versions to be allocated odd register numbers:
1905 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1906 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1907 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1909 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1910 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1911 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1913 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1915 // Classes for VST*LN pseudo-instructions with multi-register operands.
1916 // These are expanded to real instructions after register allocation.
1917 class VSTQLNPseudo<InstrItinClass itin>
1918 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1920 class VSTQLNWBPseudo<InstrItinClass itin>
1921 : PseudoNLdSt<(outs GPR:$wb),
1922 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1923 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1924 class VSTQQLNPseudo<InstrItinClass itin>
1925 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1927 class VSTQQLNWBPseudo<InstrItinClass itin>
1928 : PseudoNLdSt<(outs GPR:$wb),
1929 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1930 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1931 class VSTQQQQLNPseudo<InstrItinClass itin>
1932 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1934 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1935 : PseudoNLdSt<(outs GPR:$wb),
1936 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1937 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1939 // VST1LN : Vector Store (single element from one lane)
1940 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1941 PatFrag StoreOp, SDNode ExtractOp>
1942 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1943 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1944 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1945 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1947 let DecoderMethod = "DecodeVST1LN";
1949 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1950 PatFrag StoreOp, SDNode ExtractOp>
1951 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1952 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1953 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1954 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1956 let DecoderMethod = "DecodeVST1LN";
1958 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1959 : VSTQLNPseudo<IIC_VST1ln> {
1960 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1964 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1966 let Inst{7-5} = lane{2-0};
1968 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1970 let Inst{7-6} = lane{1-0};
1971 let Inst{4} = Rn{5};
1974 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1975 let Inst{7} = lane{0};
1976 let Inst{5-4} = Rn{5-4};
1979 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1980 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1981 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1983 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1984 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1985 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1986 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1988 // ...with address register writeback:
1989 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1990 PatFrag StoreOp, SDNode ExtractOp>
1991 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1992 (ins addrmode6:$Rn, am6offset:$Rm,
1993 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1994 "\\{$Vd[$lane]\\}, $Rn$Rm",
1996 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1997 addrmode6:$Rn, am6offset:$Rm))]> {
1998 let DecoderMethod = "DecodeVST1LN";
2000 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2001 : VSTQLNWBPseudo<IIC_VST1lnu> {
2002 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2003 addrmode6:$addr, am6offset:$offset))];
2006 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2008 let Inst{7-5} = lane{2-0};
2010 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2012 let Inst{7-6} = lane{1-0};
2013 let Inst{4} = Rn{5};
2015 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2017 let Inst{7} = lane{0};
2018 let Inst{5-4} = Rn{5-4};
2021 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2022 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2023 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2025 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2027 // VST2LN : Vector Store (single 2-element structure from one lane)
2028 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2029 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2030 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2031 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2034 let Inst{4} = Rn{4};
2035 let DecoderMethod = "DecodeVST2LN";
2038 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2039 let Inst{7-5} = lane{2-0};
2041 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2042 let Inst{7-6} = lane{1-0};
2044 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2045 let Inst{7} = lane{0};
2048 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2049 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2050 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2052 // ...with double-spaced registers:
2053 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2054 let Inst{7-6} = lane{1-0};
2055 let Inst{4} = Rn{4};
2057 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2058 let Inst{7} = lane{0};
2059 let Inst{4} = Rn{4};
2062 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2063 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2065 // ...with address register writeback:
2066 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2067 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2068 (ins addrmode6:$Rn, am6offset:$Rm,
2069 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2070 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2071 "$Rn.addr = $wb", []> {
2072 let Inst{4} = Rn{4};
2073 let DecoderMethod = "DecodeVST2LN";
2076 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2077 let Inst{7-5} = lane{2-0};
2079 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2080 let Inst{7-6} = lane{1-0};
2082 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2083 let Inst{7} = lane{0};
2086 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2087 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2088 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2090 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2091 let Inst{7-6} = lane{1-0};
2093 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2094 let Inst{7} = lane{0};
2097 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2098 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2100 // VST3LN : Vector Store (single 3-element structure from one lane)
2101 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2102 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2103 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2104 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2105 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2107 let DecoderMethod = "DecodeVST3LN";
2110 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2111 let Inst{7-5} = lane{2-0};
2113 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2114 let Inst{7-6} = lane{1-0};
2116 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2117 let Inst{7} = lane{0};
2120 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2121 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2122 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2124 // ...with double-spaced registers:
2125 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2126 let Inst{7-6} = lane{1-0};
2128 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2129 let Inst{7} = lane{0};
2132 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2133 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2135 // ...with address register writeback:
2136 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2137 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2138 (ins addrmode6:$Rn, am6offset:$Rm,
2139 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2140 IIC_VST3lnu, "vst3", Dt,
2141 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2142 "$Rn.addr = $wb", []> {
2143 let DecoderMethod = "DecodeVST3LN";
2146 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2147 let Inst{7-5} = lane{2-0};
2149 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2150 let Inst{7-6} = lane{1-0};
2152 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2153 let Inst{7} = lane{0};
2156 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2157 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2158 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2160 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2161 let Inst{7-6} = lane{1-0};
2163 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2164 let Inst{7} = lane{0};
2167 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2168 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2170 // VST4LN : Vector Store (single 4-element structure from one lane)
2171 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2172 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2173 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2174 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2175 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2178 let Inst{4} = Rn{4};
2179 let DecoderMethod = "DecodeVST4LN";
2182 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2183 let Inst{7-5} = lane{2-0};
2185 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2186 let Inst{7-6} = lane{1-0};
2188 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2189 let Inst{7} = lane{0};
2190 let Inst{5} = Rn{5};
2193 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2194 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2195 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2197 // ...with double-spaced registers:
2198 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2199 let Inst{7-6} = lane{1-0};
2201 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2202 let Inst{7} = lane{0};
2203 let Inst{5} = Rn{5};
2206 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2207 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2209 // ...with address register writeback:
2210 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2211 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2212 (ins addrmode6:$Rn, am6offset:$Rm,
2213 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2214 IIC_VST4lnu, "vst4", Dt,
2215 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2216 "$Rn.addr = $wb", []> {
2217 let Inst{4} = Rn{4};
2218 let DecoderMethod = "DecodeVST4LN";
2221 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2222 let Inst{7-5} = lane{2-0};
2224 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2225 let Inst{7-6} = lane{1-0};
2227 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2228 let Inst{7} = lane{0};
2229 let Inst{5} = Rn{5};
2232 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2233 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2234 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2236 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2237 let Inst{7-6} = lane{1-0};
2239 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2240 let Inst{7} = lane{0};
2241 let Inst{5} = Rn{5};
2244 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2245 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2247 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2250 //===----------------------------------------------------------------------===//
2251 // NEON pattern fragments
2252 //===----------------------------------------------------------------------===//
2254 // Extract D sub-registers of Q registers.
2255 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2256 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2257 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2259 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2260 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2261 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2263 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2264 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2265 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2267 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2268 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2269 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2272 // Extract S sub-registers of Q/D registers.
2273 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2274 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2275 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2278 // Translate lane numbers from Q registers to D subregs.
2279 def SubReg_i8_lane : SDNodeXForm<imm, [{
2280 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2282 def SubReg_i16_lane : SDNodeXForm<imm, [{
2283 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2285 def SubReg_i32_lane : SDNodeXForm<imm, [{
2286 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2289 //===----------------------------------------------------------------------===//
2290 // Instruction Classes
2291 //===----------------------------------------------------------------------===//
2293 // Basic 2-register operations: double- and quad-register.
2294 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2295 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2296 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2297 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2298 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2299 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2300 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2301 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2302 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2303 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2304 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2305 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2307 // Basic 2-register intrinsics, both double- and quad-register.
2308 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2309 bits<2> op17_16, bits<5> op11_7, bit op4,
2310 InstrItinClass itin, string OpcodeStr, string Dt,
2311 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2312 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2313 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2314 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2315 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2316 bits<2> op17_16, bits<5> op11_7, bit op4,
2317 InstrItinClass itin, string OpcodeStr, string Dt,
2318 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2319 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2320 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2321 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2323 // Narrow 2-register operations.
2324 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2325 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2326 InstrItinClass itin, string OpcodeStr, string Dt,
2327 ValueType TyD, ValueType TyQ, SDNode OpNode>
2328 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2329 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2330 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2332 // Narrow 2-register intrinsics.
2333 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2334 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2335 InstrItinClass itin, string OpcodeStr, string Dt,
2336 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2337 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2338 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2339 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2341 // Long 2-register operations (currently only used for VMOVL).
2342 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2343 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2344 InstrItinClass itin, string OpcodeStr, string Dt,
2345 ValueType TyQ, ValueType TyD, SDNode OpNode>
2346 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2347 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2348 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2350 // Long 2-register intrinsics.
2351 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2352 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2353 InstrItinClass itin, string OpcodeStr, string Dt,
2354 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2355 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2356 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2357 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2359 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2360 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2361 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2362 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2363 OpcodeStr, Dt, "$Vd, $Vm",
2364 "$src1 = $Vd, $src2 = $Vm", []>;
2365 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2366 InstrItinClass itin, string OpcodeStr, string Dt>
2367 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2368 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2369 "$src1 = $Vd, $src2 = $Vm", []>;
2371 // Basic 3-register operations: double- and quad-register.
2372 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2373 InstrItinClass itin, string OpcodeStr, string Dt,
2374 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2375 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2376 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2377 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2378 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2379 let isCommutable = Commutable;
2381 // Same as N3VD but no data type.
2382 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2383 InstrItinClass itin, string OpcodeStr,
2384 ValueType ResTy, ValueType OpTy,
2385 SDNode OpNode, bit Commutable>
2386 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2387 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2388 OpcodeStr, "$Vd, $Vn, $Vm", "",
2389 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2390 let isCommutable = Commutable;
2393 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2394 InstrItinClass itin, string OpcodeStr, string Dt,
2395 ValueType Ty, SDNode ShOp>
2396 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2397 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2398 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2400 (Ty (ShOp (Ty DPR:$Vn),
2401 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2402 let isCommutable = 0;
2404 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2405 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2406 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2407 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2408 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2410 (Ty (ShOp (Ty DPR:$Vn),
2411 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2412 let isCommutable = 0;
2415 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2416 InstrItinClass itin, string OpcodeStr, string Dt,
2417 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2418 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2419 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2420 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2421 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2422 let isCommutable = Commutable;
2424 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2425 InstrItinClass itin, string OpcodeStr,
2426 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2427 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2428 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2429 OpcodeStr, "$Vd, $Vn, $Vm", "",
2430 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2431 let isCommutable = Commutable;
2433 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2434 InstrItinClass itin, string OpcodeStr, string Dt,
2435 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2436 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2437 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2438 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2439 [(set (ResTy QPR:$Vd),
2440 (ResTy (ShOp (ResTy QPR:$Vn),
2441 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2443 let isCommutable = 0;
2445 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2446 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2447 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2448 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2449 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2450 [(set (ResTy QPR:$Vd),
2451 (ResTy (ShOp (ResTy QPR:$Vn),
2452 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2454 let isCommutable = 0;
2457 // Basic 3-register intrinsics, both double- and quad-register.
2458 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2459 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2460 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2461 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2462 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2463 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2464 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2465 let isCommutable = Commutable;
2467 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2468 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2469 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2470 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2471 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2473 (Ty (IntOp (Ty DPR:$Vn),
2474 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2476 let isCommutable = 0;
2478 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2479 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2480 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2481 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2482 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2484 (Ty (IntOp (Ty DPR:$Vn),
2485 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2486 let isCommutable = 0;
2488 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2489 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2490 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2491 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2492 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2493 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2494 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2495 let isCommutable = 0;
2498 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2499 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2500 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2501 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2502 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2503 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2504 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2505 let isCommutable = Commutable;
2507 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2508 string OpcodeStr, string Dt,
2509 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2510 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2511 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2512 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2513 [(set (ResTy QPR:$Vd),
2514 (ResTy (IntOp (ResTy QPR:$Vn),
2515 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2517 let isCommutable = 0;
2519 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2520 string OpcodeStr, string Dt,
2521 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2522 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2523 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2524 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2525 [(set (ResTy QPR:$Vd),
2526 (ResTy (IntOp (ResTy QPR:$Vn),
2527 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2529 let isCommutable = 0;
2531 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2532 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2533 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2534 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2535 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2536 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2537 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2538 let isCommutable = 0;
2541 // Multiply-Add/Sub operations: double- and quad-register.
2542 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2543 InstrItinClass itin, string OpcodeStr, string Dt,
2544 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2545 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2546 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2547 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2548 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2549 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2551 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2552 string OpcodeStr, string Dt,
2553 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2554 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2556 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2558 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2560 (Ty (ShOp (Ty DPR:$src1),
2562 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2564 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2565 string OpcodeStr, string Dt,
2566 ValueType Ty, SDNode MulOp, SDNode ShOp>
2567 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2569 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2571 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2573 (Ty (ShOp (Ty DPR:$src1),
2575 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2578 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2579 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2580 SDPatternOperator MulOp, SDPatternOperator OpNode>
2581 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2582 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2583 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2584 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2585 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2586 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2587 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2588 SDPatternOperator MulOp, SDPatternOperator ShOp>
2589 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2591 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2593 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2594 [(set (ResTy QPR:$Vd),
2595 (ResTy (ShOp (ResTy QPR:$src1),
2596 (ResTy (MulOp QPR:$Vn,
2597 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2599 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2600 string OpcodeStr, string Dt,
2601 ValueType ResTy, ValueType OpTy,
2602 SDNode MulOp, SDNode ShOp>
2603 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2605 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2607 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2608 [(set (ResTy QPR:$Vd),
2609 (ResTy (ShOp (ResTy QPR:$src1),
2610 (ResTy (MulOp QPR:$Vn,
2611 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2614 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2615 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2616 InstrItinClass itin, string OpcodeStr, string Dt,
2617 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2618 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2619 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2620 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2621 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2622 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2623 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2624 InstrItinClass itin, string OpcodeStr, string Dt,
2625 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2626 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2627 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2628 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2629 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2630 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2632 // Neon 3-argument intrinsics, both double- and quad-register.
2633 // The destination register is also used as the first source operand register.
2634 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2635 InstrItinClass itin, string OpcodeStr, string Dt,
2636 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2637 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2638 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2639 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2640 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2641 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2642 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2643 InstrItinClass itin, string OpcodeStr, string Dt,
2644 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2645 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2646 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2647 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2648 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2649 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2651 // Long Multiply-Add/Sub operations.
2652 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2653 InstrItinClass itin, string OpcodeStr, string Dt,
2654 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2655 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2656 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2657 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2658 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2659 (TyQ (MulOp (TyD DPR:$Vn),
2660 (TyD DPR:$Vm)))))]>;
2661 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2662 InstrItinClass itin, string OpcodeStr, string Dt,
2663 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2664 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2665 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2667 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2669 (OpNode (TyQ QPR:$src1),
2670 (TyQ (MulOp (TyD DPR:$Vn),
2671 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2673 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2674 InstrItinClass itin, string OpcodeStr, string Dt,
2675 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2676 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2677 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2679 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2681 (OpNode (TyQ QPR:$src1),
2682 (TyQ (MulOp (TyD DPR:$Vn),
2683 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2686 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2687 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2688 InstrItinClass itin, string OpcodeStr, string Dt,
2689 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2691 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2692 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2693 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2694 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2695 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2696 (TyD DPR:$Vm)))))))]>;
2698 // Neon Long 3-argument intrinsic. The destination register is
2699 // a quad-register and is also used as the first source operand register.
2700 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2701 InstrItinClass itin, string OpcodeStr, string Dt,
2702 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2703 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2704 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2705 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2707 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2708 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2709 string OpcodeStr, string Dt,
2710 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2711 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2713 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2715 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2716 [(set (ResTy QPR:$Vd),
2717 (ResTy (IntOp (ResTy QPR:$src1),
2719 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2721 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2722 InstrItinClass itin, string OpcodeStr, string Dt,
2723 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2724 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2726 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2728 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2729 [(set (ResTy QPR:$Vd),
2730 (ResTy (IntOp (ResTy QPR:$src1),
2732 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2735 // Narrowing 3-register intrinsics.
2736 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2737 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2738 Intrinsic IntOp, bit Commutable>
2739 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2740 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2741 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2742 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2743 let isCommutable = Commutable;
2746 // Long 3-register operations.
2747 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2748 InstrItinClass itin, string OpcodeStr, string Dt,
2749 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2750 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2751 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2752 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2753 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2754 let isCommutable = Commutable;
2756 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2757 InstrItinClass itin, string OpcodeStr, string Dt,
2758 ValueType TyQ, ValueType TyD, SDNode OpNode>
2759 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2760 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2761 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2763 (TyQ (OpNode (TyD DPR:$Vn),
2764 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2765 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2766 InstrItinClass itin, string OpcodeStr, string Dt,
2767 ValueType TyQ, ValueType TyD, SDNode OpNode>
2768 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2769 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2770 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2772 (TyQ (OpNode (TyD DPR:$Vn),
2773 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2775 // Long 3-register operations with explicitly extended operands.
2776 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2777 InstrItinClass itin, string OpcodeStr, string Dt,
2778 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2780 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2781 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2782 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2783 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2784 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2785 let isCommutable = Commutable;
2788 // Long 3-register intrinsics with explicit extend (VABDL).
2789 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2790 InstrItinClass itin, string OpcodeStr, string Dt,
2791 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2793 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2794 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2795 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2796 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2797 (TyD DPR:$Vm))))))]> {
2798 let isCommutable = Commutable;
2801 // Long 3-register intrinsics.
2802 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2803 InstrItinClass itin, string OpcodeStr, string Dt,
2804 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2805 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2806 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2807 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2808 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2809 let isCommutable = Commutable;
2811 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2812 string OpcodeStr, string Dt,
2813 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2814 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2815 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2816 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2817 [(set (ResTy QPR:$Vd),
2818 (ResTy (IntOp (OpTy DPR:$Vn),
2819 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2821 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2822 InstrItinClass itin, string OpcodeStr, string Dt,
2823 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2824 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2825 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2826 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2827 [(set (ResTy QPR:$Vd),
2828 (ResTy (IntOp (OpTy DPR:$Vn),
2829 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2832 // Wide 3-register operations.
2833 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2834 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2835 SDNode OpNode, SDNode ExtOp, bit Commutable>
2836 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2837 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2838 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2839 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2840 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2841 let isCommutable = Commutable;
2844 // Pairwise long 2-register intrinsics, both double- and quad-register.
2845 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2846 bits<2> op17_16, bits<5> op11_7, bit op4,
2847 string OpcodeStr, string Dt,
2848 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2849 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2850 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2851 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2852 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2853 bits<2> op17_16, bits<5> op11_7, bit op4,
2854 string OpcodeStr, string Dt,
2855 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2856 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2857 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2858 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2860 // Pairwise long 2-register accumulate intrinsics,
2861 // both double- and quad-register.
2862 // The destination register is also used as the first source operand register.
2863 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2864 bits<2> op17_16, bits<5> op11_7, bit op4,
2865 string OpcodeStr, string Dt,
2866 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2867 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2868 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2869 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2870 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2871 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2872 bits<2> op17_16, bits<5> op11_7, bit op4,
2873 string OpcodeStr, string Dt,
2874 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2875 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2876 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2877 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2878 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2880 // Shift by immediate,
2881 // both double- and quad-register.
2882 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2883 Format f, InstrItinClass itin, Operand ImmTy,
2884 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2885 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2886 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2887 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2888 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2889 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2890 Format f, InstrItinClass itin, Operand ImmTy,
2891 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2892 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2893 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2894 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2895 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2897 // Long shift by immediate.
2898 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2899 string OpcodeStr, string Dt,
2900 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2901 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2902 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2903 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2904 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2905 (i32 imm:$SIMM))))]>;
2907 // Narrow shift by immediate.
2908 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2909 InstrItinClass itin, string OpcodeStr, string Dt,
2910 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2911 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2912 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2913 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2914 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2915 (i32 imm:$SIMM))))]>;
2917 // Shift right by immediate and accumulate,
2918 // both double- and quad-register.
2919 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2920 Operand ImmTy, string OpcodeStr, string Dt,
2921 ValueType Ty, SDNode ShOp>
2922 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2923 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2924 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2925 [(set DPR:$Vd, (Ty (add DPR:$src1,
2926 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2927 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2928 Operand ImmTy, string OpcodeStr, string Dt,
2929 ValueType Ty, SDNode ShOp>
2930 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2931 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2932 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2933 [(set QPR:$Vd, (Ty (add QPR:$src1,
2934 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2936 // Shift by immediate and insert,
2937 // both double- and quad-register.
2938 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2939 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2940 ValueType Ty,SDNode ShOp>
2941 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2942 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2943 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2944 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2945 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2946 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2947 ValueType Ty,SDNode ShOp>
2948 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2949 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2950 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2951 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2953 // Convert, with fractional bits immediate,
2954 // both double- and quad-register.
2955 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2956 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2958 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2959 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2960 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2961 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2962 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2963 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2965 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2966 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2967 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2968 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2970 //===----------------------------------------------------------------------===//
2972 //===----------------------------------------------------------------------===//
2974 // Abbreviations used in multiclass suffixes:
2975 // Q = quarter int (8 bit) elements
2976 // H = half int (16 bit) elements
2977 // S = single int (32 bit) elements
2978 // D = double int (64 bit) elements
2980 // Neon 2-register vector operations and intrinsics.
2982 // Neon 2-register comparisons.
2983 // source operand element sizes of 8, 16 and 32 bits:
2984 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2985 bits<5> op11_7, bit op4, string opc, string Dt,
2986 string asm, SDNode OpNode> {
2987 // 64-bit vector types.
2988 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2989 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2990 opc, !strconcat(Dt, "8"), asm, "",
2991 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2992 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2993 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2994 opc, !strconcat(Dt, "16"), asm, "",
2995 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2996 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2997 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2998 opc, !strconcat(Dt, "32"), asm, "",
2999 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3000 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3001 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3002 opc, "f32", asm, "",
3003 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3004 let Inst{10} = 1; // overwrite F = 1
3007 // 128-bit vector types.
3008 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3009 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3010 opc, !strconcat(Dt, "8"), asm, "",
3011 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3012 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3013 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3014 opc, !strconcat(Dt, "16"), asm, "",
3015 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3016 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3017 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3018 opc, !strconcat(Dt, "32"), asm, "",
3019 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3020 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3021 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3022 opc, "f32", asm, "",
3023 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3024 let Inst{10} = 1; // overwrite F = 1
3029 // Neon 2-register vector intrinsics,
3030 // element sizes of 8, 16 and 32 bits:
3031 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3032 bits<5> op11_7, bit op4,
3033 InstrItinClass itinD, InstrItinClass itinQ,
3034 string OpcodeStr, string Dt, Intrinsic IntOp> {
3035 // 64-bit vector types.
3036 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3037 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3038 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3039 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3040 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3041 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3043 // 128-bit vector types.
3044 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3045 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3046 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3047 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3048 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3049 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3053 // Neon Narrowing 2-register vector operations,
3054 // source operand element sizes of 16, 32 and 64 bits:
3055 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3056 bits<5> op11_7, bit op6, bit op4,
3057 InstrItinClass itin, string OpcodeStr, string Dt,
3059 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3060 itin, OpcodeStr, !strconcat(Dt, "16"),
3061 v8i8, v8i16, OpNode>;
3062 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3063 itin, OpcodeStr, !strconcat(Dt, "32"),
3064 v4i16, v4i32, OpNode>;
3065 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3066 itin, OpcodeStr, !strconcat(Dt, "64"),
3067 v2i32, v2i64, OpNode>;
3070 // Neon Narrowing 2-register vector intrinsics,
3071 // source operand element sizes of 16, 32 and 64 bits:
3072 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3073 bits<5> op11_7, bit op6, bit op4,
3074 InstrItinClass itin, string OpcodeStr, string Dt,
3076 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3077 itin, OpcodeStr, !strconcat(Dt, "16"),
3078 v8i8, v8i16, IntOp>;
3079 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3080 itin, OpcodeStr, !strconcat(Dt, "32"),
3081 v4i16, v4i32, IntOp>;
3082 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3083 itin, OpcodeStr, !strconcat(Dt, "64"),
3084 v2i32, v2i64, IntOp>;
3088 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3089 // source operand element sizes of 16, 32 and 64 bits:
3090 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3091 string OpcodeStr, string Dt, SDNode OpNode> {
3092 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3093 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3094 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3095 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3096 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3097 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3101 // Neon 3-register vector operations.
3103 // First with only element sizes of 8, 16 and 32 bits:
3104 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3105 InstrItinClass itinD16, InstrItinClass itinD32,
3106 InstrItinClass itinQ16, InstrItinClass itinQ32,
3107 string OpcodeStr, string Dt,
3108 SDNode OpNode, bit Commutable = 0> {
3109 // 64-bit vector types.
3110 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3111 OpcodeStr, !strconcat(Dt, "8"),
3112 v8i8, v8i8, OpNode, Commutable>;
3113 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3114 OpcodeStr, !strconcat(Dt, "16"),
3115 v4i16, v4i16, OpNode, Commutable>;
3116 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3117 OpcodeStr, !strconcat(Dt, "32"),
3118 v2i32, v2i32, OpNode, Commutable>;
3120 // 128-bit vector types.
3121 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3122 OpcodeStr, !strconcat(Dt, "8"),
3123 v16i8, v16i8, OpNode, Commutable>;
3124 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3125 OpcodeStr, !strconcat(Dt, "16"),
3126 v8i16, v8i16, OpNode, Commutable>;
3127 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3128 OpcodeStr, !strconcat(Dt, "32"),
3129 v4i32, v4i32, OpNode, Commutable>;
3132 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3133 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3134 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3135 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3136 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3137 v4i32, v2i32, ShOp>;
3140 // ....then also with element size 64 bits:
3141 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3142 InstrItinClass itinD, InstrItinClass itinQ,
3143 string OpcodeStr, string Dt,
3144 SDNode OpNode, bit Commutable = 0>
3145 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3146 OpcodeStr, Dt, OpNode, Commutable> {
3147 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3148 OpcodeStr, !strconcat(Dt, "64"),
3149 v1i64, v1i64, OpNode, Commutable>;
3150 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3151 OpcodeStr, !strconcat(Dt, "64"),
3152 v2i64, v2i64, OpNode, Commutable>;
3156 // Neon 3-register vector intrinsics.
3158 // First with only element sizes of 16 and 32 bits:
3159 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3160 InstrItinClass itinD16, InstrItinClass itinD32,
3161 InstrItinClass itinQ16, InstrItinClass itinQ32,
3162 string OpcodeStr, string Dt,
3163 Intrinsic IntOp, bit Commutable = 0> {
3164 // 64-bit vector types.
3165 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3166 OpcodeStr, !strconcat(Dt, "16"),
3167 v4i16, v4i16, IntOp, Commutable>;
3168 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3169 OpcodeStr, !strconcat(Dt, "32"),
3170 v2i32, v2i32, IntOp, Commutable>;
3172 // 128-bit vector types.
3173 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3174 OpcodeStr, !strconcat(Dt, "16"),
3175 v8i16, v8i16, IntOp, Commutable>;
3176 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3177 OpcodeStr, !strconcat(Dt, "32"),
3178 v4i32, v4i32, IntOp, Commutable>;
3180 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3181 InstrItinClass itinD16, InstrItinClass itinD32,
3182 InstrItinClass itinQ16, InstrItinClass itinQ32,
3183 string OpcodeStr, string Dt,
3185 // 64-bit vector types.
3186 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3187 OpcodeStr, !strconcat(Dt, "16"),
3188 v4i16, v4i16, IntOp>;
3189 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3190 OpcodeStr, !strconcat(Dt, "32"),
3191 v2i32, v2i32, IntOp>;
3193 // 128-bit vector types.
3194 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3195 OpcodeStr, !strconcat(Dt, "16"),
3196 v8i16, v8i16, IntOp>;
3197 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3198 OpcodeStr, !strconcat(Dt, "32"),
3199 v4i32, v4i32, IntOp>;
3202 multiclass N3VIntSL_HS<bits<4> op11_8,
3203 InstrItinClass itinD16, InstrItinClass itinD32,
3204 InstrItinClass itinQ16, InstrItinClass itinQ32,
3205 string OpcodeStr, string Dt, Intrinsic IntOp> {
3206 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3207 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3208 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3209 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3210 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3211 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3212 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3213 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3216 // ....then also with element size of 8 bits:
3217 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3218 InstrItinClass itinD16, InstrItinClass itinD32,
3219 InstrItinClass itinQ16, InstrItinClass itinQ32,
3220 string OpcodeStr, string Dt,
3221 Intrinsic IntOp, bit Commutable = 0>
3222 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3223 OpcodeStr, Dt, IntOp, Commutable> {
3224 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3225 OpcodeStr, !strconcat(Dt, "8"),
3226 v8i8, v8i8, IntOp, Commutable>;
3227 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3228 OpcodeStr, !strconcat(Dt, "8"),
3229 v16i8, v16i8, IntOp, Commutable>;
3231 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3232 InstrItinClass itinD16, InstrItinClass itinD32,
3233 InstrItinClass itinQ16, InstrItinClass itinQ32,
3234 string OpcodeStr, string Dt,
3236 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3237 OpcodeStr, Dt, IntOp> {
3238 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3239 OpcodeStr, !strconcat(Dt, "8"),
3241 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3242 OpcodeStr, !strconcat(Dt, "8"),
3243 v16i8, v16i8, IntOp>;
3247 // ....then also with element size of 64 bits:
3248 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3249 InstrItinClass itinD16, InstrItinClass itinD32,
3250 InstrItinClass itinQ16, InstrItinClass itinQ32,
3251 string OpcodeStr, string Dt,
3252 Intrinsic IntOp, bit Commutable = 0>
3253 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3254 OpcodeStr, Dt, IntOp, Commutable> {
3255 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3256 OpcodeStr, !strconcat(Dt, "64"),
3257 v1i64, v1i64, IntOp, Commutable>;
3258 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3259 OpcodeStr, !strconcat(Dt, "64"),
3260 v2i64, v2i64, IntOp, Commutable>;
3262 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3263 InstrItinClass itinD16, InstrItinClass itinD32,
3264 InstrItinClass itinQ16, InstrItinClass itinQ32,
3265 string OpcodeStr, string Dt,
3267 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3268 OpcodeStr, Dt, IntOp> {
3269 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3270 OpcodeStr, !strconcat(Dt, "64"),
3271 v1i64, v1i64, IntOp>;
3272 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3273 OpcodeStr, !strconcat(Dt, "64"),
3274 v2i64, v2i64, IntOp>;
3277 // Neon Narrowing 3-register vector intrinsics,
3278 // source operand element sizes of 16, 32 and 64 bits:
3279 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3280 string OpcodeStr, string Dt,
3281 Intrinsic IntOp, bit Commutable = 0> {
3282 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3283 OpcodeStr, !strconcat(Dt, "16"),
3284 v8i8, v8i16, IntOp, Commutable>;
3285 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3286 OpcodeStr, !strconcat(Dt, "32"),
3287 v4i16, v4i32, IntOp, Commutable>;
3288 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3289 OpcodeStr, !strconcat(Dt, "64"),
3290 v2i32, v2i64, IntOp, Commutable>;
3294 // Neon Long 3-register vector operations.
3296 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3297 InstrItinClass itin16, InstrItinClass itin32,
3298 string OpcodeStr, string Dt,
3299 SDNode OpNode, bit Commutable = 0> {
3300 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3301 OpcodeStr, !strconcat(Dt, "8"),
3302 v8i16, v8i8, OpNode, Commutable>;
3303 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3304 OpcodeStr, !strconcat(Dt, "16"),
3305 v4i32, v4i16, OpNode, Commutable>;
3306 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3307 OpcodeStr, !strconcat(Dt, "32"),
3308 v2i64, v2i32, OpNode, Commutable>;
3311 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3312 InstrItinClass itin, string OpcodeStr, string Dt,
3314 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3315 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3316 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3317 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3320 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3321 InstrItinClass itin16, InstrItinClass itin32,
3322 string OpcodeStr, string Dt,
3323 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3324 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3325 OpcodeStr, !strconcat(Dt, "8"),
3326 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3327 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3328 OpcodeStr, !strconcat(Dt, "16"),
3329 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3330 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3331 OpcodeStr, !strconcat(Dt, "32"),
3332 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3335 // Neon Long 3-register vector intrinsics.
3337 // First with only element sizes of 16 and 32 bits:
3338 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3339 InstrItinClass itin16, InstrItinClass itin32,
3340 string OpcodeStr, string Dt,
3341 Intrinsic IntOp, bit Commutable = 0> {
3342 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3343 OpcodeStr, !strconcat(Dt, "16"),
3344 v4i32, v4i16, IntOp, Commutable>;
3345 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3346 OpcodeStr, !strconcat(Dt, "32"),
3347 v2i64, v2i32, IntOp, Commutable>;
3350 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3351 InstrItinClass itin, string OpcodeStr, string Dt,
3353 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3354 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3355 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3356 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3359 // ....then also with element size of 8 bits:
3360 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3361 InstrItinClass itin16, InstrItinClass itin32,
3362 string OpcodeStr, string Dt,
3363 Intrinsic IntOp, bit Commutable = 0>
3364 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3365 IntOp, Commutable> {
3366 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3367 OpcodeStr, !strconcat(Dt, "8"),
3368 v8i16, v8i8, IntOp, Commutable>;
3371 // ....with explicit extend (VABDL).
3372 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3373 InstrItinClass itin, string OpcodeStr, string Dt,
3374 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3375 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3376 OpcodeStr, !strconcat(Dt, "8"),
3377 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3378 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3379 OpcodeStr, !strconcat(Dt, "16"),
3380 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3381 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3382 OpcodeStr, !strconcat(Dt, "32"),
3383 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3387 // Neon Wide 3-register vector intrinsics,
3388 // source operand element sizes of 8, 16 and 32 bits:
3389 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3390 string OpcodeStr, string Dt,
3391 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3392 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3393 OpcodeStr, !strconcat(Dt, "8"),
3394 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3395 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3396 OpcodeStr, !strconcat(Dt, "16"),
3397 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3398 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3399 OpcodeStr, !strconcat(Dt, "32"),
3400 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3404 // Neon Multiply-Op vector operations,
3405 // element sizes of 8, 16 and 32 bits:
3406 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3407 InstrItinClass itinD16, InstrItinClass itinD32,
3408 InstrItinClass itinQ16, InstrItinClass itinQ32,
3409 string OpcodeStr, string Dt, SDNode OpNode> {
3410 // 64-bit vector types.
3411 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3412 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3413 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3414 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3415 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3416 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3418 // 128-bit vector types.
3419 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3420 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3421 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3422 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3423 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3424 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3427 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3428 InstrItinClass itinD16, InstrItinClass itinD32,
3429 InstrItinClass itinQ16, InstrItinClass itinQ32,
3430 string OpcodeStr, string Dt, SDNode ShOp> {
3431 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3432 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3433 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3434 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3435 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3436 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3438 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3439 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3443 // Neon Intrinsic-Op vector operations,
3444 // element sizes of 8, 16 and 32 bits:
3445 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3446 InstrItinClass itinD, InstrItinClass itinQ,
3447 string OpcodeStr, string Dt, Intrinsic IntOp,
3449 // 64-bit vector types.
3450 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3451 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3452 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3453 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3454 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3455 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3457 // 128-bit vector types.
3458 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3459 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3460 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3461 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3462 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3463 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3466 // Neon 3-argument intrinsics,
3467 // element sizes of 8, 16 and 32 bits:
3468 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3469 InstrItinClass itinD, InstrItinClass itinQ,
3470 string OpcodeStr, string Dt, Intrinsic IntOp> {
3471 // 64-bit vector types.
3472 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3473 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3474 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3475 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3476 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3477 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3479 // 128-bit vector types.
3480 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3481 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3482 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3483 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3484 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3485 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3489 // Neon Long Multiply-Op vector operations,
3490 // element sizes of 8, 16 and 32 bits:
3491 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3492 InstrItinClass itin16, InstrItinClass itin32,
3493 string OpcodeStr, string Dt, SDNode MulOp,
3495 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3496 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3497 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3498 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3499 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3500 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3503 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3504 string Dt, SDNode MulOp, SDNode OpNode> {
3505 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3506 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3507 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3508 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3512 // Neon Long 3-argument intrinsics.
3514 // First with only element sizes of 16 and 32 bits:
3515 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3516 InstrItinClass itin16, InstrItinClass itin32,
3517 string OpcodeStr, string Dt, Intrinsic IntOp> {
3518 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3519 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3520 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3521 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3524 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3525 string OpcodeStr, string Dt, Intrinsic IntOp> {
3526 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3527 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3528 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3529 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3532 // ....then also with element size of 8 bits:
3533 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3534 InstrItinClass itin16, InstrItinClass itin32,
3535 string OpcodeStr, string Dt, Intrinsic IntOp>
3536 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3537 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3538 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3541 // ....with explicit extend (VABAL).
3542 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3543 InstrItinClass itin, string OpcodeStr, string Dt,
3544 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3545 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3546 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3547 IntOp, ExtOp, OpNode>;
3548 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3549 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3550 IntOp, ExtOp, OpNode>;
3551 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3552 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3553 IntOp, ExtOp, OpNode>;
3557 // Neon Pairwise long 2-register intrinsics,
3558 // element sizes of 8, 16 and 32 bits:
3559 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3560 bits<5> op11_7, bit op4,
3561 string OpcodeStr, string Dt, Intrinsic IntOp> {
3562 // 64-bit vector types.
3563 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3564 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3565 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3566 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3567 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3568 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3570 // 128-bit vector types.
3571 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3572 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3573 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3574 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3575 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3576 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3580 // Neon Pairwise long 2-register accumulate intrinsics,
3581 // element sizes of 8, 16 and 32 bits:
3582 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3583 bits<5> op11_7, bit op4,
3584 string OpcodeStr, string Dt, Intrinsic IntOp> {
3585 // 64-bit vector types.
3586 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3587 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3588 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3589 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3590 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3591 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3593 // 128-bit vector types.
3594 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3595 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3596 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3597 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3598 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3599 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3603 // Neon 2-register vector shift by immediate,
3604 // with f of either N2RegVShLFrm or N2RegVShRFrm
3605 // element sizes of 8, 16, 32 and 64 bits:
3606 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3607 InstrItinClass itin, string OpcodeStr, string Dt,
3609 // 64-bit vector types.
3610 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3611 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3612 let Inst{21-19} = 0b001; // imm6 = 001xxx
3614 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3615 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3616 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3618 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3619 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3620 let Inst{21} = 0b1; // imm6 = 1xxxxx
3622 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3623 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3626 // 128-bit vector types.
3627 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3628 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3629 let Inst{21-19} = 0b001; // imm6 = 001xxx
3631 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3632 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3633 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3635 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3636 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3637 let Inst{21} = 0b1; // imm6 = 1xxxxx
3639 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3640 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3643 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3644 InstrItinClass itin, string OpcodeStr, string Dt,
3646 // 64-bit vector types.
3647 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3648 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3649 let Inst{21-19} = 0b001; // imm6 = 001xxx
3651 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3652 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3653 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3655 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3656 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3657 let Inst{21} = 0b1; // imm6 = 1xxxxx
3659 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3660 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3663 // 128-bit vector types.
3664 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3665 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3666 let Inst{21-19} = 0b001; // imm6 = 001xxx
3668 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3669 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3670 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3672 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3673 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3674 let Inst{21} = 0b1; // imm6 = 1xxxxx
3676 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3677 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3681 // Neon Shift-Accumulate vector operations,
3682 // element sizes of 8, 16, 32 and 64 bits:
3683 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3684 string OpcodeStr, string Dt, SDNode ShOp> {
3685 // 64-bit vector types.
3686 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3687 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3688 let Inst{21-19} = 0b001; // imm6 = 001xxx
3690 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3691 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3692 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3694 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3695 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3696 let Inst{21} = 0b1; // imm6 = 1xxxxx
3698 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3699 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3702 // 128-bit vector types.
3703 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3704 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3705 let Inst{21-19} = 0b001; // imm6 = 001xxx
3707 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3708 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3709 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3711 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3712 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3713 let Inst{21} = 0b1; // imm6 = 1xxxxx
3715 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3716 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3720 // Neon Shift-Insert vector operations,
3721 // with f of either N2RegVShLFrm or N2RegVShRFrm
3722 // element sizes of 8, 16, 32 and 64 bits:
3723 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3725 // 64-bit vector types.
3726 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3727 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3728 let Inst{21-19} = 0b001; // imm6 = 001xxx
3730 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3731 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3732 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3734 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3735 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3736 let Inst{21} = 0b1; // imm6 = 1xxxxx
3738 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3739 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3742 // 128-bit vector types.
3743 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3744 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3745 let Inst{21-19} = 0b001; // imm6 = 001xxx
3747 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3748 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3749 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3751 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3752 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3753 let Inst{21} = 0b1; // imm6 = 1xxxxx
3755 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3756 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3759 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3761 // 64-bit vector types.
3762 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3763 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3764 let Inst{21-19} = 0b001; // imm6 = 001xxx
3766 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3767 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3768 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3770 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3771 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3772 let Inst{21} = 0b1; // imm6 = 1xxxxx
3774 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3775 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3778 // 128-bit vector types.
3779 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3780 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3781 let Inst{21-19} = 0b001; // imm6 = 001xxx
3783 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3784 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3785 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3787 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3788 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3789 let Inst{21} = 0b1; // imm6 = 1xxxxx
3791 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3792 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3796 // Neon Shift Long operations,
3797 // element sizes of 8, 16, 32 bits:
3798 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3799 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3800 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3801 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3802 let Inst{21-19} = 0b001; // imm6 = 001xxx
3804 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3805 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3806 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3808 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3809 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3810 let Inst{21} = 0b1; // imm6 = 1xxxxx
3814 // Neon Shift Narrow operations,
3815 // element sizes of 16, 32, 64 bits:
3816 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3817 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3819 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3820 OpcodeStr, !strconcat(Dt, "16"),
3821 v8i8, v8i16, shr_imm8, OpNode> {
3822 let Inst{21-19} = 0b001; // imm6 = 001xxx
3824 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3825 OpcodeStr, !strconcat(Dt, "32"),
3826 v4i16, v4i32, shr_imm16, OpNode> {
3827 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3829 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3830 OpcodeStr, !strconcat(Dt, "64"),
3831 v2i32, v2i64, shr_imm32, OpNode> {
3832 let Inst{21} = 0b1; // imm6 = 1xxxxx
3836 //===----------------------------------------------------------------------===//
3837 // Instruction Definitions.
3838 //===----------------------------------------------------------------------===//
3840 // Vector Add Operations.
3842 // VADD : Vector Add (integer and floating-point)
3843 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3845 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3846 v2f32, v2f32, fadd, 1>;
3847 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3848 v4f32, v4f32, fadd, 1>;
3849 // VADDL : Vector Add Long (Q = D + D)
3850 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3851 "vaddl", "s", add, sext, 1>;
3852 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3853 "vaddl", "u", add, zext, 1>;
3854 // VADDW : Vector Add Wide (Q = Q + D)
3855 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3856 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3857 // VHADD : Vector Halving Add
3858 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3859 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3860 "vhadd", "s", int_arm_neon_vhadds, 1>;
3861 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3862 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3863 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3864 // VRHADD : Vector Rounding Halving Add
3865 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3866 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3867 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3868 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3869 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3870 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3871 // VQADD : Vector Saturating Add
3872 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3873 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3874 "vqadd", "s", int_arm_neon_vqadds, 1>;
3875 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3876 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3877 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3878 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3879 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3880 int_arm_neon_vaddhn, 1>;
3881 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3882 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3883 int_arm_neon_vraddhn, 1>;
3885 // Vector Multiply Operations.
3887 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3888 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3889 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3890 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3891 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3892 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3893 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3894 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3895 v2f32, v2f32, fmul, 1>;
3896 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3897 v4f32, v4f32, fmul, 1>;
3898 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3899 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3900 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3903 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3904 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3905 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3906 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3907 (DSubReg_i16_reg imm:$lane))),
3908 (SubReg_i16_lane imm:$lane)))>;
3909 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3910 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3911 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3912 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3913 (DSubReg_i32_reg imm:$lane))),
3914 (SubReg_i32_lane imm:$lane)))>;
3915 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3916 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3917 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3918 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3919 (DSubReg_i32_reg imm:$lane))),
3920 (SubReg_i32_lane imm:$lane)))>;
3922 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3923 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3924 IIC_VMULi16Q, IIC_VMULi32Q,
3925 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3926 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3927 IIC_VMULi16Q, IIC_VMULi32Q,
3928 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3929 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3930 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3932 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3933 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3934 (DSubReg_i16_reg imm:$lane))),
3935 (SubReg_i16_lane imm:$lane)))>;
3936 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3937 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3939 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3940 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3941 (DSubReg_i32_reg imm:$lane))),
3942 (SubReg_i32_lane imm:$lane)))>;
3944 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3945 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3946 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3947 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3948 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3949 IIC_VMULi16Q, IIC_VMULi32Q,
3950 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3951 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3952 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3954 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3955 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3956 (DSubReg_i16_reg imm:$lane))),
3957 (SubReg_i16_lane imm:$lane)))>;
3958 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3959 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3961 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3962 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3963 (DSubReg_i32_reg imm:$lane))),
3964 (SubReg_i32_lane imm:$lane)))>;
3966 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3967 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3968 "vmull", "s", NEONvmulls, 1>;
3969 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3970 "vmull", "u", NEONvmullu, 1>;
3971 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3972 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3973 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3974 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3976 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3977 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3978 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3979 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3980 "vqdmull", "s", int_arm_neon_vqdmull>;
3982 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3984 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3985 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3986 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3987 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3988 v2f32, fmul_su, fadd_mlx>,
3989 Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
3990 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3991 v4f32, fmul_su, fadd_mlx>,
3992 Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
3993 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3994 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3995 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3996 v2f32, fmul_su, fadd_mlx>,
3997 Requires<[HasNEON, UseFPVMLx]>;
3998 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3999 v4f32, v2f32, fmul_su, fadd_mlx>,
4000 Requires<[HasNEON, UseFPVMLx]>;
4002 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4003 (mul (v8i16 QPR:$src2),
4004 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4005 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4006 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4007 (DSubReg_i16_reg imm:$lane))),
4008 (SubReg_i16_lane imm:$lane)))>;
4010 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4011 (mul (v4i32 QPR:$src2),
4012 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4013 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4014 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4015 (DSubReg_i32_reg imm:$lane))),
4016 (SubReg_i32_lane imm:$lane)))>;
4018 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4019 (fmul_su (v4f32 QPR:$src2),
4020 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4021 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4023 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4024 (DSubReg_i32_reg imm:$lane))),
4025 (SubReg_i32_lane imm:$lane)))>,
4026 Requires<[HasNEON, UseFPVMLx]>;
4028 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4029 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4030 "vmlal", "s", NEONvmulls, add>;
4031 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4032 "vmlal", "u", NEONvmullu, add>;
4034 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4035 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4037 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4038 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4039 "vqdmlal", "s", int_arm_neon_vqdmlal>;
4040 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
4042 // VMLS : Vector Multiply Subtract (integer and floating-point)
4043 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4044 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4045 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4046 v2f32, fmul_su, fsub_mlx>,
4047 Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
4048 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4049 v4f32, fmul_su, fsub_mlx>,
4050 Requires<[HasNEON, UseFPVMLx, NoNEON2]>;
4051 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4052 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4053 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4054 v2f32, fmul_su, fsub_mlx>,
4055 Requires<[HasNEON, UseFPVMLx]>;
4056 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4057 v4f32, v2f32, fmul_su, fsub_mlx>,
4058 Requires<[HasNEON, UseFPVMLx]>;
4060 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4061 (mul (v8i16 QPR:$src2),
4062 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4063 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4064 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4065 (DSubReg_i16_reg imm:$lane))),
4066 (SubReg_i16_lane imm:$lane)))>;
4068 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4069 (mul (v4i32 QPR:$src2),
4070 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4071 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4072 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4073 (DSubReg_i32_reg imm:$lane))),
4074 (SubReg_i32_lane imm:$lane)))>;
4076 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4077 (fmul_su (v4f32 QPR:$src2),
4078 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4079 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4080 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4081 (DSubReg_i32_reg imm:$lane))),
4082 (SubReg_i32_lane imm:$lane)))>,
4083 Requires<[HasNEON, UseFPVMLx]>;
4085 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4086 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4087 "vmlsl", "s", NEONvmulls, sub>;
4088 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4089 "vmlsl", "u", NEONvmullu, sub>;
4091 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4092 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4094 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4095 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4096 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4097 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4100 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4101 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4102 v2f32, fmul_su, fadd_mlx>,
4103 Requires<[HasNEON2,FPContractions]>;
4105 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4106 v4f32, fmul_su, fadd_mlx>,
4107 Requires<[HasNEON2,FPContractions]>;
4109 // Fused Vector Multiply Subtract (floating-point)
4110 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4111 v2f32, fmul_su, fsub_mlx>,
4112 Requires<[HasNEON2,FPContractions]>;
4113 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4114 v4f32, fmul_su, fsub_mlx>,
4115 Requires<[HasNEON2,FPContractions]>;
4117 // Vector Subtract Operations.
4119 // VSUB : Vector Subtract (integer and floating-point)
4120 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4121 "vsub", "i", sub, 0>;
4122 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4123 v2f32, v2f32, fsub, 0>;
4124 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4125 v4f32, v4f32, fsub, 0>;
4126 // VSUBL : Vector Subtract Long (Q = D - D)
4127 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4128 "vsubl", "s", sub, sext, 0>;
4129 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4130 "vsubl", "u", sub, zext, 0>;
4131 // VSUBW : Vector Subtract Wide (Q = Q - D)
4132 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4133 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4134 // VHSUB : Vector Halving Subtract
4135 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4136 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4137 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4138 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4139 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4140 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4141 // VQSUB : Vector Saturing Subtract
4142 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4143 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4144 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4145 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4146 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4147 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4148 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4149 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4150 int_arm_neon_vsubhn, 0>;
4151 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4152 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4153 int_arm_neon_vrsubhn, 0>;
4155 // Vector Comparisons.
4157 // VCEQ : Vector Compare Equal
4158 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4159 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4160 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4162 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4165 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4166 "$Vd, $Vm, #0", NEONvceqz>;
4168 // VCGE : Vector Compare Greater Than or Equal
4169 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4170 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4171 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4172 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4173 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4175 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4178 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4179 "$Vd, $Vm, #0", NEONvcgez>;
4180 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4181 "$Vd, $Vm, #0", NEONvclez>;
4183 // VCGT : Vector Compare Greater Than
4184 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4185 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4186 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4187 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4188 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4190 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4193 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4194 "$Vd, $Vm, #0", NEONvcgtz>;
4195 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4196 "$Vd, $Vm, #0", NEONvcltz>;
4198 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4199 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4200 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4201 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4202 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4203 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4204 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4205 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4206 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4207 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4208 // VTST : Vector Test Bits
4209 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4210 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4212 // Vector Bitwise Operations.
4214 def vnotd : PatFrag<(ops node:$in),
4215 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4216 def vnotq : PatFrag<(ops node:$in),
4217 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4220 // VAND : Vector Bitwise AND
4221 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4222 v2i32, v2i32, and, 1>;
4223 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4224 v4i32, v4i32, and, 1>;
4226 // VEOR : Vector Bitwise Exclusive OR
4227 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4228 v2i32, v2i32, xor, 1>;
4229 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4230 v4i32, v4i32, xor, 1>;
4232 // VORR : Vector Bitwise OR
4233 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4234 v2i32, v2i32, or, 1>;
4235 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4236 v4i32, v4i32, or, 1>;
4238 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4239 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4241 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4243 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4244 let Inst{9} = SIMM{9};
4247 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4248 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4250 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4252 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4253 let Inst{10-9} = SIMM{10-9};
4256 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4257 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4259 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4261 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4262 let Inst{9} = SIMM{9};
4265 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4266 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4268 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4270 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4271 let Inst{10-9} = SIMM{10-9};
4275 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4276 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4277 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4278 "vbic", "$Vd, $Vn, $Vm", "",
4279 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4280 (vnotd DPR:$Vm))))]>;
4281 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4282 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4283 "vbic", "$Vd, $Vn, $Vm", "",
4284 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4285 (vnotq QPR:$Vm))))]>;
4287 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4288 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4290 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4292 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4293 let Inst{9} = SIMM{9};
4296 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4297 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4299 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4301 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4302 let Inst{10-9} = SIMM{10-9};
4305 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4306 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4308 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4310 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4311 let Inst{9} = SIMM{9};
4314 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4315 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4317 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4319 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4320 let Inst{10-9} = SIMM{10-9};
4323 // VORN : Vector Bitwise OR NOT
4324 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4325 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4326 "vorn", "$Vd, $Vn, $Vm", "",
4327 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4328 (vnotd DPR:$Vm))))]>;
4329 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4330 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4331 "vorn", "$Vd, $Vn, $Vm", "",
4332 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4333 (vnotq QPR:$Vm))))]>;
4335 // VMVN : Vector Bitwise NOT (Immediate)
4337 let isReMaterializable = 1 in {
4339 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4340 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4341 "vmvn", "i16", "$Vd, $SIMM", "",
4342 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4343 let Inst{9} = SIMM{9};
4346 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4347 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4348 "vmvn", "i16", "$Vd, $SIMM", "",
4349 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4350 let Inst{9} = SIMM{9};
4353 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4354 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4355 "vmvn", "i32", "$Vd, $SIMM", "",
4356 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4357 let Inst{11-8} = SIMM{11-8};
4360 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4361 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4362 "vmvn", "i32", "$Vd, $SIMM", "",
4363 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4364 let Inst{11-8} = SIMM{11-8};
4368 // VMVN : Vector Bitwise NOT
4369 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4370 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4371 "vmvn", "$Vd, $Vm", "",
4372 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4373 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4374 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4375 "vmvn", "$Vd, $Vm", "",
4376 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4377 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4378 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4380 // VBSL : Vector Bitwise Select
4381 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4382 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4383 N3RegFrm, IIC_VCNTiD,
4384 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4386 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4388 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4389 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4390 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4392 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4393 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4394 N3RegFrm, IIC_VCNTiQ,
4395 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4397 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4399 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4400 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4401 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4403 // VBIF : Vector Bitwise Insert if False
4404 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4405 // FIXME: This instruction's encoding MAY NOT BE correct.
4406 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4407 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4408 N3RegFrm, IIC_VBINiD,
4409 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4411 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4412 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4413 N3RegFrm, IIC_VBINiQ,
4414 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4417 // VBIT : Vector Bitwise Insert if True
4418 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4419 // FIXME: This instruction's encoding MAY NOT BE correct.
4420 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4421 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4422 N3RegFrm, IIC_VBINiD,
4423 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4425 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4426 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4427 N3RegFrm, IIC_VBINiQ,
4428 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4431 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4432 // for equivalent operations with different register constraints; it just
4435 // Vector Absolute Differences.
4437 // VABD : Vector Absolute Difference
4438 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4439 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4440 "vabd", "s", int_arm_neon_vabds, 1>;
4441 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4442 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4443 "vabd", "u", int_arm_neon_vabdu, 1>;
4444 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4445 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4446 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4447 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4449 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4450 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4451 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4452 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4453 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4455 // VABA : Vector Absolute Difference and Accumulate
4456 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4457 "vaba", "s", int_arm_neon_vabds, add>;
4458 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4459 "vaba", "u", int_arm_neon_vabdu, add>;
4461 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4462 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4463 "vabal", "s", int_arm_neon_vabds, zext, add>;
4464 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4465 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4467 // Vector Maximum and Minimum.
4469 // VMAX : Vector Maximum
4470 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4471 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4472 "vmax", "s", int_arm_neon_vmaxs, 1>;
4473 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4474 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4475 "vmax", "u", int_arm_neon_vmaxu, 1>;
4476 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4478 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4479 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4481 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4483 // VMIN : Vector Minimum
4484 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4485 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4486 "vmin", "s", int_arm_neon_vmins, 1>;
4487 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4488 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4489 "vmin", "u", int_arm_neon_vminu, 1>;
4490 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4492 v2f32, v2f32, int_arm_neon_vmins, 1>;
4493 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4495 v4f32, v4f32, int_arm_neon_vmins, 1>;
4497 // Vector Pairwise Operations.
4499 // VPADD : Vector Pairwise Add
4500 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4502 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4503 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4505 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4506 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4508 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4509 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4510 IIC_VPBIND, "vpadd", "f32",
4511 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4513 // VPADDL : Vector Pairwise Add Long
4514 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4515 int_arm_neon_vpaddls>;
4516 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4517 int_arm_neon_vpaddlu>;
4519 // VPADAL : Vector Pairwise Add and Accumulate Long
4520 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4521 int_arm_neon_vpadals>;
4522 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4523 int_arm_neon_vpadalu>;
4525 // VPMAX : Vector Pairwise Maximum
4526 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4527 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4528 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4529 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4530 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4531 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4532 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4533 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4534 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4535 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4536 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4537 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4538 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4539 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4541 // VPMIN : Vector Pairwise Minimum
4542 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4543 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4544 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4545 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4546 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4547 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4548 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4549 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4550 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4551 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4552 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4553 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4554 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4555 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4557 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4559 // VRECPE : Vector Reciprocal Estimate
4560 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4561 IIC_VUNAD, "vrecpe", "u32",
4562 v2i32, v2i32, int_arm_neon_vrecpe>;
4563 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4564 IIC_VUNAQ, "vrecpe", "u32",
4565 v4i32, v4i32, int_arm_neon_vrecpe>;
4566 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4567 IIC_VUNAD, "vrecpe", "f32",
4568 v2f32, v2f32, int_arm_neon_vrecpe>;
4569 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4570 IIC_VUNAQ, "vrecpe", "f32",
4571 v4f32, v4f32, int_arm_neon_vrecpe>;
4573 // VRECPS : Vector Reciprocal Step
4574 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4575 IIC_VRECSD, "vrecps", "f32",
4576 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4577 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4578 IIC_VRECSQ, "vrecps", "f32",
4579 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4581 // VRSQRTE : Vector Reciprocal Square Root Estimate
4582 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4583 IIC_VUNAD, "vrsqrte", "u32",
4584 v2i32, v2i32, int_arm_neon_vrsqrte>;
4585 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4586 IIC_VUNAQ, "vrsqrte", "u32",
4587 v4i32, v4i32, int_arm_neon_vrsqrte>;
4588 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4589 IIC_VUNAD, "vrsqrte", "f32",
4590 v2f32, v2f32, int_arm_neon_vrsqrte>;
4591 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4592 IIC_VUNAQ, "vrsqrte", "f32",
4593 v4f32, v4f32, int_arm_neon_vrsqrte>;
4595 // VRSQRTS : Vector Reciprocal Square Root Step
4596 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4597 IIC_VRECSD, "vrsqrts", "f32",
4598 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4599 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4600 IIC_VRECSQ, "vrsqrts", "f32",
4601 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4605 // VSHL : Vector Shift
4606 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4607 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4608 "vshl", "s", int_arm_neon_vshifts>;
4609 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4610 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4611 "vshl", "u", int_arm_neon_vshiftu>;
4613 // VSHL : Vector Shift Left (Immediate)
4614 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4616 // VSHR : Vector Shift Right (Immediate)
4617 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4618 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4620 // VSHLL : Vector Shift Left Long
4621 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4622 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4624 // VSHLL : Vector Shift Left Long (with maximum shift count)
4625 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4626 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4627 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4628 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4629 ResTy, OpTy, ImmTy, OpNode> {
4630 let Inst{21-16} = op21_16;
4631 let DecoderMethod = "DecodeVSHLMaxInstruction";
4633 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4634 v8i16, v8i8, imm8, NEONvshlli>;
4635 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4636 v4i32, v4i16, imm16, NEONvshlli>;
4637 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4638 v2i64, v2i32, imm32, NEONvshlli>;
4640 // VSHRN : Vector Shift Right and Narrow
4641 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4644 // VRSHL : Vector Rounding Shift
4645 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4646 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4647 "vrshl", "s", int_arm_neon_vrshifts>;
4648 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4649 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4650 "vrshl", "u", int_arm_neon_vrshiftu>;
4651 // VRSHR : Vector Rounding Shift Right
4652 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4653 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4655 // VRSHRN : Vector Rounding Shift Right and Narrow
4656 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4659 // VQSHL : Vector Saturating Shift
4660 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4661 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4662 "vqshl", "s", int_arm_neon_vqshifts>;
4663 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4664 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4665 "vqshl", "u", int_arm_neon_vqshiftu>;
4666 // VQSHL : Vector Saturating Shift Left (Immediate)
4667 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4668 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4670 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4671 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4673 // VQSHRN : Vector Saturating Shift Right and Narrow
4674 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4676 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4679 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4680 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4683 // VQRSHL : Vector Saturating Rounding Shift
4684 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4685 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4686 "vqrshl", "s", int_arm_neon_vqrshifts>;
4687 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4688 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4689 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4691 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4692 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4694 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4697 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4698 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4701 // VSRA : Vector Shift Right and Accumulate
4702 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4703 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4704 // VRSRA : Vector Rounding Shift Right and Accumulate
4705 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4706 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4708 // VSLI : Vector Shift Left and Insert
4709 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4711 // VSRI : Vector Shift Right and Insert
4712 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4714 // Vector Absolute and Saturating Absolute.
4716 // VABS : Vector Absolute Value
4717 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4718 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4720 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4721 IIC_VUNAD, "vabs", "f32",
4722 v2f32, v2f32, int_arm_neon_vabs>;
4723 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4724 IIC_VUNAQ, "vabs", "f32",
4725 v4f32, v4f32, int_arm_neon_vabs>;
4727 // VQABS : Vector Saturating Absolute Value
4728 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4729 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4730 int_arm_neon_vqabs>;
4734 def vnegd : PatFrag<(ops node:$in),
4735 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4736 def vnegq : PatFrag<(ops node:$in),
4737 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4739 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4740 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4741 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4742 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4743 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4744 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4745 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4746 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4748 // VNEG : Vector Negate (integer)
4749 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4750 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4751 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4752 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4753 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4754 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4756 // VNEG : Vector Negate (floating-point)
4757 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4758 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4759 "vneg", "f32", "$Vd, $Vm", "",
4760 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4761 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4762 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4763 "vneg", "f32", "$Vd, $Vm", "",
4764 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4766 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4767 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4768 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4769 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4770 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4771 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4773 // VQNEG : Vector Saturating Negate
4774 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4775 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4776 int_arm_neon_vqneg>;
4778 // Vector Bit Counting Operations.
4780 // VCLS : Vector Count Leading Sign Bits
4781 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4782 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4784 // VCLZ : Vector Count Leading Zeros
4785 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4786 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4788 // VCNT : Vector Count One Bits
4789 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4790 IIC_VCNTiD, "vcnt", "8",
4791 v8i8, v8i8, int_arm_neon_vcnt>;
4792 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4793 IIC_VCNTiQ, "vcnt", "8",
4794 v16i8, v16i8, int_arm_neon_vcnt>;
4797 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4798 (outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1),
4799 NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
4801 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4802 (outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1),
4803 NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
4806 // Vector Move Operations.
4808 // VMOV : Vector Move (Register)
4809 def : InstAlias<"vmov${p} $Vd, $Vm",
4810 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4811 def : InstAlias<"vmov${p} $Vd, $Vm",
4812 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4814 // VMOV : Vector Move (Immediate)
4816 let isReMaterializable = 1 in {
4817 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4818 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4819 "vmov", "i8", "$Vd, $SIMM", "",
4820 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4821 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4822 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4823 "vmov", "i8", "$Vd, $SIMM", "",
4824 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4826 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4827 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4828 "vmov", "i16", "$Vd, $SIMM", "",
4829 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4830 let Inst{9} = SIMM{9};
4833 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4834 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4835 "vmov", "i16", "$Vd, $SIMM", "",
4836 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4837 let Inst{9} = SIMM{9};
4840 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4841 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4842 "vmov", "i32", "$Vd, $SIMM", "",
4843 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4844 let Inst{11-8} = SIMM{11-8};
4847 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4848 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4849 "vmov", "i32", "$Vd, $SIMM", "",
4850 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4851 let Inst{11-8} = SIMM{11-8};
4854 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4855 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4856 "vmov", "i64", "$Vd, $SIMM", "",
4857 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4858 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4859 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4860 "vmov", "i64", "$Vd, $SIMM", "",
4861 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4863 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4864 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4865 "vmov", "f32", "$Vd, $SIMM", "",
4866 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4867 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4868 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4869 "vmov", "f32", "$Vd, $SIMM", "",
4870 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4871 } // isReMaterializable
4873 // VMOV : Vector Get Lane (move scalar to ARM core register)
4875 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4876 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4877 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4878 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4880 let Inst{21} = lane{2};
4881 let Inst{6-5} = lane{1-0};
4883 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4884 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4885 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4886 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4888 let Inst{21} = lane{1};
4889 let Inst{6} = lane{0};
4891 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4892 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4893 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4894 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4896 let Inst{21} = lane{2};
4897 let Inst{6-5} = lane{1-0};
4899 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4900 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4901 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4902 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4904 let Inst{21} = lane{1};
4905 let Inst{6} = lane{0};
4907 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4908 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4909 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4910 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4912 let Inst{21} = lane{0};
4914 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4915 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4916 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4917 (DSubReg_i8_reg imm:$lane))),
4918 (SubReg_i8_lane imm:$lane))>;
4919 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4920 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4921 (DSubReg_i16_reg imm:$lane))),
4922 (SubReg_i16_lane imm:$lane))>;
4923 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4924 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4925 (DSubReg_i8_reg imm:$lane))),
4926 (SubReg_i8_lane imm:$lane))>;
4927 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4928 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4929 (DSubReg_i16_reg imm:$lane))),
4930 (SubReg_i16_lane imm:$lane))>;
4931 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4932 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4933 (DSubReg_i32_reg imm:$lane))),
4934 (SubReg_i32_lane imm:$lane))>;
4935 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4936 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4937 (SSubReg_f32_reg imm:$src2))>;
4938 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4939 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4940 (SSubReg_f32_reg imm:$src2))>;
4941 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4942 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4943 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4944 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4947 // VMOV : Vector Set Lane (move ARM core register to scalar)
4949 let Constraints = "$src1 = $V" in {
4950 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4951 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4952 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4953 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4954 GPR:$R, imm:$lane))]> {
4955 let Inst{21} = lane{2};
4956 let Inst{6-5} = lane{1-0};
4958 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4959 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4960 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4961 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4962 GPR:$R, imm:$lane))]> {
4963 let Inst{21} = lane{1};
4964 let Inst{6} = lane{0};
4966 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4967 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4968 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4969 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4970 GPR:$R, imm:$lane))]> {
4971 let Inst{21} = lane{0};
4974 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4975 (v16i8 (INSERT_SUBREG QPR:$src1,
4976 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4977 (DSubReg_i8_reg imm:$lane))),
4978 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4979 (DSubReg_i8_reg imm:$lane)))>;
4980 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4981 (v8i16 (INSERT_SUBREG QPR:$src1,
4982 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4983 (DSubReg_i16_reg imm:$lane))),
4984 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4985 (DSubReg_i16_reg imm:$lane)))>;
4986 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4987 (v4i32 (INSERT_SUBREG QPR:$src1,
4988 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4989 (DSubReg_i32_reg imm:$lane))),
4990 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4991 (DSubReg_i32_reg imm:$lane)))>;
4993 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4994 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4995 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4996 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4997 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4998 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5000 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5001 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5002 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5003 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5005 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5006 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5007 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5008 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5009 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5010 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5012 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5013 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5014 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5015 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5016 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5017 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5019 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5020 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5021 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5023 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5024 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5025 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5027 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5028 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5029 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5032 // VDUP : Vector Duplicate (from ARM core register to all elements)
5034 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5035 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5036 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5037 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5038 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5039 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5040 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5041 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5043 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5044 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5045 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
5046 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5047 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5048 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5050 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
5051 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5053 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5055 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5056 ValueType Ty, Operand IdxTy>
5057 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5058 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5059 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5061 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5062 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5063 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5064 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5065 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5066 VectorIndex32:$lane)))]>;
5068 // Inst{19-16} is partially specified depending on the element size.
5070 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5072 let Inst{19-17} = lane{2-0};
5074 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5076 let Inst{19-18} = lane{1-0};
5078 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5080 let Inst{19} = lane{0};
5082 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5084 let Inst{19-17} = lane{2-0};
5086 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5088 let Inst{19-18} = lane{1-0};
5090 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5092 let Inst{19} = lane{0};
5095 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5096 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5098 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5099 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5101 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5102 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5103 (DSubReg_i8_reg imm:$lane))),
5104 (SubReg_i8_lane imm:$lane)))>;
5105 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5106 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5107 (DSubReg_i16_reg imm:$lane))),
5108 (SubReg_i16_lane imm:$lane)))>;
5109 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5110 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5111 (DSubReg_i32_reg imm:$lane))),
5112 (SubReg_i32_lane imm:$lane)))>;
5113 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5114 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5115 (DSubReg_i32_reg imm:$lane))),
5116 (SubReg_i32_lane imm:$lane)))>;
5118 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5119 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5120 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5121 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5123 // VMOVN : Vector Narrowing Move
5124 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5125 "vmovn", "i", trunc>;
5126 // VQMOVN : Vector Saturating Narrowing Move
5127 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5128 "vqmovn", "s", int_arm_neon_vqmovns>;
5129 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5130 "vqmovn", "u", int_arm_neon_vqmovnu>;
5131 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5132 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5133 // VMOVL : Vector Lengthening Move
5134 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5135 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5136 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5137 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5138 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5140 // Vector Conversions.
5142 // VCVT : Vector Convert Between Floating-Point and Integers
5143 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5144 v2i32, v2f32, fp_to_sint>;
5145 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5146 v2i32, v2f32, fp_to_uint>;
5147 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5148 v2f32, v2i32, sint_to_fp>;
5149 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5150 v2f32, v2i32, uint_to_fp>;
5152 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5153 v4i32, v4f32, fp_to_sint>;
5154 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5155 v4i32, v4f32, fp_to_uint>;
5156 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5157 v4f32, v4i32, sint_to_fp>;
5158 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5159 v4f32, v4i32, uint_to_fp>;
5161 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5162 let DecoderMethod = "DecodeVCVTD" in {
5163 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5164 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5165 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5166 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5167 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5168 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5169 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5170 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5173 let DecoderMethod = "DecodeVCVTQ" in {
5174 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5175 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5176 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5177 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5178 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5179 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5180 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5181 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5184 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5185 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5186 IIC_VUNAQ, "vcvt", "f16.f32",
5187 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5188 Requires<[HasNEON, HasFP16]>;
5189 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5190 IIC_VUNAQ, "vcvt", "f32.f16",
5191 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5192 Requires<[HasNEON, HasFP16]>;
5196 // VREV64 : Vector Reverse elements within 64-bit doublewords
5198 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5199 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5200 (ins DPR:$Vm), IIC_VMOVD,
5201 OpcodeStr, Dt, "$Vd, $Vm", "",
5202 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5203 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5204 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5205 (ins QPR:$Vm), IIC_VMOVQ,
5206 OpcodeStr, Dt, "$Vd, $Vm", "",
5207 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5209 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5210 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5211 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5212 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5214 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5215 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5216 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5217 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5219 // VREV32 : Vector Reverse elements within 32-bit words
5221 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5222 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5223 (ins DPR:$Vm), IIC_VMOVD,
5224 OpcodeStr, Dt, "$Vd, $Vm", "",
5225 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5226 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5227 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5228 (ins QPR:$Vm), IIC_VMOVQ,
5229 OpcodeStr, Dt, "$Vd, $Vm", "",
5230 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5232 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5233 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5235 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5236 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5238 // VREV16 : Vector Reverse elements within 16-bit halfwords
5240 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5241 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5242 (ins DPR:$Vm), IIC_VMOVD,
5243 OpcodeStr, Dt, "$Vd, $Vm", "",
5244 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5245 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5246 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5247 (ins QPR:$Vm), IIC_VMOVQ,
5248 OpcodeStr, Dt, "$Vd, $Vm", "",
5249 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5251 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5252 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5254 // Other Vector Shuffles.
5256 // Aligned extractions: really just dropping registers
5258 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5259 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5260 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5262 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5264 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5266 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5268 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5270 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5273 // VEXT : Vector Extract
5275 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5276 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5277 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5278 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5279 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5280 (Ty DPR:$Vm), imm:$index)))]> {
5282 let Inst{11-8} = index{3-0};
5285 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5286 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5287 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5288 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5289 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5290 (Ty QPR:$Vm), imm:$index)))]> {
5292 let Inst{11-8} = index{3-0};
5295 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5296 let Inst{11-8} = index{3-0};
5298 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5299 let Inst{11-9} = index{2-0};
5302 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5303 let Inst{11-10} = index{1-0};
5304 let Inst{9-8} = 0b00;
5306 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5309 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5311 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5312 let Inst{11-8} = index{3-0};
5314 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5315 let Inst{11-9} = index{2-0};
5318 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5319 let Inst{11-10} = index{1-0};
5320 let Inst{9-8} = 0b00;
5322 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5323 let Inst{11} = index{0};
5324 let Inst{10-8} = 0b000;
5326 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5329 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5331 // VTRN : Vector Transpose
5333 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5334 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5335 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5337 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5338 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5339 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5341 // VUZP : Vector Unzip (Deinterleave)
5343 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5344 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5345 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
5347 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5348 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5349 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5351 // VZIP : Vector Zip (Interleave)
5353 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5354 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5355 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5357 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5358 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5359 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5361 // Vector Table Lookup and Table Extension.
5363 // VTBL : Vector Table Lookup
5364 let DecoderMethod = "DecodeTBLInstruction" in {
5366 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5367 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5368 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5369 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5370 let hasExtraSrcRegAllocReq = 1 in {
5372 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5373 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5374 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5376 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5377 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5378 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5380 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5381 (ins VecListFourD:$Vn, DPR:$Vm),
5383 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5384 } // hasExtraSrcRegAllocReq = 1
5387 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5389 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5391 // VTBX : Vector Table Extension
5393 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5394 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5395 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5396 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5397 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5398 let hasExtraSrcRegAllocReq = 1 in {
5400 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5401 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5402 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5404 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5405 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5406 NVTBLFrm, IIC_VTBX3,
5407 "vtbx", "8", "$Vd, $Vn, $Vm",
5410 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5411 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5412 "vtbx", "8", "$Vd, $Vn, $Vm",
5414 } // hasExtraSrcRegAllocReq = 1
5417 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5418 IIC_VTBX3, "$orig = $dst", []>;
5420 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5421 IIC_VTBX4, "$orig = $dst", []>;
5422 } // DecoderMethod = "DecodeTBLInstruction"
5424 //===----------------------------------------------------------------------===//
5425 // NEON instructions for single-precision FP math
5426 //===----------------------------------------------------------------------===//
5428 class N2VSPat<SDNode OpNode, NeonI Inst>
5429 : NEONFPPat<(f32 (OpNode SPR:$a)),
5431 (v2f32 (COPY_TO_REGCLASS (Inst
5433 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5434 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5436 class N3VSPat<SDNode OpNode, NeonI Inst>
5437 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5439 (v2f32 (COPY_TO_REGCLASS (Inst
5441 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5444 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5445 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5447 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5448 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5450 (v2f32 (COPY_TO_REGCLASS (Inst
5452 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5455 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5458 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5459 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5461 def : N3VSPat<fadd, VADDfd>;
5462 def : N3VSPat<fsub, VSUBfd>;
5463 def : N3VSPat<fmul, VMULfd>;
5464 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5465 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEON2]>;
5466 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5467 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEON2]>;
5468 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
5469 Requires<[HasNEON2, UseNEONForFP,FPContractions]>;
5470 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
5471 Requires<[HasNEON2, UseNEONForFP,FPContractions]>;
5472 def : N2VSPat<fabs, VABSfd>;
5473 def : N2VSPat<fneg, VNEGfd>;
5474 def : N3VSPat<NEONfmax, VMAXfd>;
5475 def : N3VSPat<NEONfmin, VMINfd>;
5476 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5477 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5478 def : N2VSPat<arm_sitof, VCVTs2fd>;
5479 def : N2VSPat<arm_uitof, VCVTu2fd>;
5481 //===----------------------------------------------------------------------===//
5482 // Non-Instruction Patterns
5483 //===----------------------------------------------------------------------===//
5486 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5487 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5488 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5489 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5490 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5491 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5492 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5493 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5494 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5495 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5496 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5497 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5498 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5499 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5500 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5501 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5502 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5503 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5504 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5505 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5506 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5507 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5508 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5509 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5510 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5511 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5512 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5513 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5514 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5515 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5517 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5518 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5519 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5520 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5521 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5522 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5523 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5524 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5525 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5526 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5527 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5528 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5529 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5530 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5531 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5532 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5533 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5534 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5535 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5536 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5537 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5538 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5539 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5540 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5541 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5542 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5543 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5544 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5545 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5546 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5548 // Vector lengthening move with load, matching extending loads.
5550 // extload, zextload and sextload for a standard lengthening load. Example:
5551 // Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr))
5552 // (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
5553 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
5554 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5555 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5556 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5557 (VLDRD addrmode5:$addr))>;
5558 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5559 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5560 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5561 (VLDRD addrmode5:$addr))>;
5562 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5563 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5564 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
5565 (VLDRD addrmode5:$addr))>;
5568 // extload, zextload and sextload for a lengthening load which only uses
5569 // half the lanes available. Example:
5570 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
5571 // Pat<(v4i16 (extloadvi8 addrmode5:$addr))
5572 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5573 // (VLDRS addrmode5:$addr),
5576 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
5577 string InsnLanes, string InsnTy> {
5578 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5579 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5580 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5581 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5583 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5584 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5585 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5586 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5588 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5589 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5590 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
5591 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5595 // extload, zextload and sextload for a lengthening load followed by another
5596 // lengthening load, to quadruple the initial length.
5597 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
5598 // Pat<(v4i32 (extloadvi8 addrmode5:$addr))
5599 // (EXTRACT_SUBREG (VMOVLuv4i32
5600 // (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5601 // (VLDRS addrmode5:$addr),
5605 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
5606 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5607 string Insn2Ty, SubRegIndex RegType> {
5608 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5609 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
5610 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5611 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5612 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5615 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5616 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
5617 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5618 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5619 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5622 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5623 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
5624 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5625 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
5626 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
5631 defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
5632 defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32
5633 defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64
5635 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
5636 defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
5637 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
5639 // Double lengthening - v4i8 -> v4i16 -> v4i32
5640 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0>;
5641 // v2i8 -> v2i16 -> v2i32
5642 defm : Lengthen_Double<"2", "i32", "i8", "8", "i16", "4", "i32", dsub_0>;
5643 // v2i16 -> v2i32 -> v2i64
5644 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64", qsub_0>;
5646 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
5647 def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
5648 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5649 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5650 dsub_0)), dsub_0))>;
5651 def : Pat<(v2i64 (zextloadvi8 addrmode5:$addr)),
5652 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5653 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5654 dsub_0)), dsub_0))>;
5655 def : Pat<(v2i64 (sextloadvi8 addrmode5:$addr)),
5656 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
5657 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)),
5658 dsub_0)), dsub_0))>;
5660 //===----------------------------------------------------------------------===//
5661 // Assembler aliases
5664 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5665 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5666 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5667 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5670 // VADD two-operand aliases.
5671 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5672 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5673 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5674 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5675 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5676 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5677 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5678 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5680 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5681 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5682 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5683 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5684 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5685 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5686 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5687 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5689 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5690 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5691 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5692 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5694 // VSUB two-operand aliases.
5695 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5696 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5697 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5698 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5699 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5700 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5701 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5702 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5704 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5705 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5706 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5707 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5708 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5709 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5710 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5711 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5713 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5714 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5715 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5716 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5718 // VADDW two-operand aliases.
5719 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
5720 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5721 def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
5722 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5723 def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
5724 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5725 def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
5726 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5727 def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
5728 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5729 def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
5730 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5732 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5733 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5734 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5735 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5736 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5737 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5738 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5739 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5740 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5741 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5742 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5743 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5744 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5745 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5746 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5747 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5748 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5749 // ... two-operand aliases
5750 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5751 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5752 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5753 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5754 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5755 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5756 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5757 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5758 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5759 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5760 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5761 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5762 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5763 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5764 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5765 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5767 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5768 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5769 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5770 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5771 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5772 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5773 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5774 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5775 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5776 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5777 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5778 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5780 // VMUL two-operand aliases.
5781 def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
5782 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5783 def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
5784 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5785 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
5786 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5787 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
5788 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5790 def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
5791 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5792 def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
5793 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5794 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
5795 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5796 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
5797 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5799 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
5800 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5801 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
5802 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5804 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5805 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5806 VectorIndex16:$lane, pred:$p)>;
5807 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5808 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5809 VectorIndex16:$lane, pred:$p)>;
5811 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5812 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5813 VectorIndex32:$lane, pred:$p)>;
5814 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5815 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5816 VectorIndex32:$lane, pred:$p)>;
5818 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5819 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5820 VectorIndex32:$lane, pred:$p)>;
5821 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5822 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5823 VectorIndex32:$lane, pred:$p)>;
5825 // VQADD (register) two-operand aliases.
5826 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5827 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5828 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5829 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5830 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5831 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5832 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5833 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5834 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5835 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5836 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5837 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5838 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5839 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5840 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5841 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5843 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5844 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5845 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5846 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5847 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5848 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5849 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5850 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5851 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5852 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5853 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5854 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5855 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5856 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5857 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5858 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5860 // VSHL (immediate) two-operand aliases.
5861 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5862 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
5863 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5864 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
5865 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5866 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
5867 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5868 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
5870 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5871 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
5872 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5873 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
5874 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5875 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
5876 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5877 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
5879 // VSHL (register) two-operand aliases.
5880 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5881 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5882 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5883 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5884 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5885 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5886 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5887 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5888 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5889 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5890 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5891 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5892 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5893 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5894 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5895 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5897 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5898 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5899 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5900 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5901 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5902 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5903 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5904 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5905 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5906 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5907 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5908 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5909 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5910 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5911 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5912 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5914 // VSHL (immediate) two-operand aliases.
5915 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5916 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5917 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5918 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5919 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5920 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5921 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5922 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5924 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5925 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5926 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5927 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5928 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5929 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5930 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5931 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5933 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5934 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5935 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5936 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5937 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5938 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5939 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5940 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5942 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5943 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5944 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5945 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5946 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5947 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5948 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5949 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5951 // VLD1 single-lane pseudo-instructions. These need special handling for
5952 // the lane index that an InstAlias can't handle, so we use these instead.
5953 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
5954 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5955 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
5956 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5957 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
5958 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5960 def VLD1LNdWB_fixed_Asm_8 :
5961 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
5962 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5963 def VLD1LNdWB_fixed_Asm_16 :
5964 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
5965 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5966 def VLD1LNdWB_fixed_Asm_32 :
5967 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
5968 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5969 def VLD1LNdWB_register_Asm_8 :
5970 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
5971 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5972 rGPR:$Rm, pred:$p)>;
5973 def VLD1LNdWB_register_Asm_16 :
5974 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
5975 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5976 rGPR:$Rm, pred:$p)>;
5977 def VLD1LNdWB_register_Asm_32 :
5978 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
5979 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5980 rGPR:$Rm, pred:$p)>;
5983 // VST1 single-lane pseudo-instructions. These need special handling for
5984 // the lane index that an InstAlias can't handle, so we use these instead.
5985 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
5986 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5987 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
5988 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5989 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
5990 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5992 def VST1LNdWB_fixed_Asm_8 :
5993 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
5994 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5995 def VST1LNdWB_fixed_Asm_16 :
5996 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
5997 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5998 def VST1LNdWB_fixed_Asm_32 :
5999 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6000 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6001 def VST1LNdWB_register_Asm_8 :
6002 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6003 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6004 rGPR:$Rm, pred:$p)>;
6005 def VST1LNdWB_register_Asm_16 :
6006 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6007 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6008 rGPR:$Rm, pred:$p)>;
6009 def VST1LNdWB_register_Asm_32 :
6010 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6011 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6012 rGPR:$Rm, pred:$p)>;
6014 // VLD2 single-lane pseudo-instructions. These need special handling for
6015 // the lane index that an InstAlias can't handle, so we use these instead.
6016 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6017 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6018 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6019 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6020 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6021 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6022 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6023 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6024 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6025 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6027 def VLD2LNdWB_fixed_Asm_8 :
6028 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6029 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6030 def VLD2LNdWB_fixed_Asm_16 :
6031 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6032 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6033 def VLD2LNdWB_fixed_Asm_32 :
6034 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6035 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6036 def VLD2LNqWB_fixed_Asm_16 :
6037 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6038 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6039 def VLD2LNqWB_fixed_Asm_32 :
6040 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6041 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6042 def VLD2LNdWB_register_Asm_8 :
6043 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6044 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6045 rGPR:$Rm, pred:$p)>;
6046 def VLD2LNdWB_register_Asm_16 :
6047 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6048 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6049 rGPR:$Rm, pred:$p)>;
6050 def VLD2LNdWB_register_Asm_32 :
6051 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6052 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6053 rGPR:$Rm, pred:$p)>;
6054 def VLD2LNqWB_register_Asm_16 :
6055 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6056 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6057 rGPR:$Rm, pred:$p)>;
6058 def VLD2LNqWB_register_Asm_32 :
6059 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6060 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6061 rGPR:$Rm, pred:$p)>;
6064 // VST2 single-lane pseudo-instructions. These need special handling for
6065 // the lane index that an InstAlias can't handle, so we use these instead.
6066 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6067 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6068 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6069 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6070 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6071 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6072 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6073 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6074 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6075 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6077 def VST2LNdWB_fixed_Asm_8 :
6078 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6079 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6080 def VST2LNdWB_fixed_Asm_16 :
6081 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6082 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6083 def VST2LNdWB_fixed_Asm_32 :
6084 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6085 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6086 def VST2LNqWB_fixed_Asm_16 :
6087 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6088 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6089 def VST2LNqWB_fixed_Asm_32 :
6090 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6091 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6092 def VST2LNdWB_register_Asm_8 :
6093 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6094 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6095 rGPR:$Rm, pred:$p)>;
6096 def VST2LNdWB_register_Asm_16 :
6097 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6098 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6099 rGPR:$Rm, pred:$p)>;
6100 def VST2LNdWB_register_Asm_32 :
6101 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6102 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6103 rGPR:$Rm, pred:$p)>;
6104 def VST2LNqWB_register_Asm_16 :
6105 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6106 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6107 rGPR:$Rm, pred:$p)>;
6108 def VST2LNqWB_register_Asm_32 :
6109 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6110 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6111 rGPR:$Rm, pred:$p)>;
6113 // VLD3 all-lanes pseudo-instructions. These need special handling for
6114 // the lane index that an InstAlias can't handle, so we use these instead.
6115 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6116 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6117 def VLD3DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6118 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6119 def VLD3DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6120 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6121 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6122 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6123 def VLD3DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6124 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6125 def VLD3DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6126 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6128 def VLD3DUPdWB_fixed_Asm_8 :
6129 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6130 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6131 def VLD3DUPdWB_fixed_Asm_16 :
6132 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6133 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6134 def VLD3DUPdWB_fixed_Asm_32 :
6135 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6136 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6137 def VLD3DUPqWB_fixed_Asm_8 :
6138 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6139 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6140 def VLD3DUPqWB_fixed_Asm_16 :
6141 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6142 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6143 def VLD3DUPqWB_fixed_Asm_32 :
6144 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6145 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6146 def VLD3DUPdWB_register_Asm_8 :
6147 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6148 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6149 rGPR:$Rm, pred:$p)>;
6150 def VLD3DUPdWB_register_Asm_16 :
6151 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6152 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6153 rGPR:$Rm, pred:$p)>;
6154 def VLD3DUPdWB_register_Asm_32 :
6155 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6156 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6157 rGPR:$Rm, pred:$p)>;
6158 def VLD3DUPqWB_register_Asm_8 :
6159 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6160 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6161 rGPR:$Rm, pred:$p)>;
6162 def VLD3DUPqWB_register_Asm_16 :
6163 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6164 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6165 rGPR:$Rm, pred:$p)>;
6166 def VLD3DUPqWB_register_Asm_32 :
6167 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6168 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6169 rGPR:$Rm, pred:$p)>;
6172 // VLD3 single-lane pseudo-instructions. These need special handling for
6173 // the lane index that an InstAlias can't handle, so we use these instead.
6174 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6175 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6176 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6177 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6178 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6179 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6180 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6181 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6182 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6183 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6185 def VLD3LNdWB_fixed_Asm_8 :
6186 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6187 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6188 def VLD3LNdWB_fixed_Asm_16 :
6189 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6190 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6191 def VLD3LNdWB_fixed_Asm_32 :
6192 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6193 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6194 def VLD3LNqWB_fixed_Asm_16 :
6195 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6196 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6197 def VLD3LNqWB_fixed_Asm_32 :
6198 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6199 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6200 def VLD3LNdWB_register_Asm_8 :
6201 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6202 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6203 rGPR:$Rm, pred:$p)>;
6204 def VLD3LNdWB_register_Asm_16 :
6205 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6206 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6207 rGPR:$Rm, pred:$p)>;
6208 def VLD3LNdWB_register_Asm_32 :
6209 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6210 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6211 rGPR:$Rm, pred:$p)>;
6212 def VLD3LNqWB_register_Asm_16 :
6213 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6214 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6215 rGPR:$Rm, pred:$p)>;
6216 def VLD3LNqWB_register_Asm_32 :
6217 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6218 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6219 rGPR:$Rm, pred:$p)>;
6221 // VLD3 multiple structure pseudo-instructions. These need special handling for
6222 // the vector operands that the normal instructions don't yet model.
6223 // FIXME: Remove these when the register classes and instructions are updated.
6224 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6225 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6226 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6227 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6228 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6229 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6230 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6231 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6232 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6233 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6234 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6235 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6237 def VLD3dWB_fixed_Asm_8 :
6238 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6239 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6240 def VLD3dWB_fixed_Asm_16 :
6241 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6242 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6243 def VLD3dWB_fixed_Asm_32 :
6244 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6245 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6246 def VLD3qWB_fixed_Asm_8 :
6247 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6248 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6249 def VLD3qWB_fixed_Asm_16 :
6250 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6251 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6252 def VLD3qWB_fixed_Asm_32 :
6253 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6254 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6255 def VLD3dWB_register_Asm_8 :
6256 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6257 (ins VecListThreeD:$list, addrmode6:$addr,
6258 rGPR:$Rm, pred:$p)>;
6259 def VLD3dWB_register_Asm_16 :
6260 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6261 (ins VecListThreeD:$list, addrmode6:$addr,
6262 rGPR:$Rm, pred:$p)>;
6263 def VLD3dWB_register_Asm_32 :
6264 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6265 (ins VecListThreeD:$list, addrmode6:$addr,
6266 rGPR:$Rm, pred:$p)>;
6267 def VLD3qWB_register_Asm_8 :
6268 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6269 (ins VecListThreeQ:$list, addrmode6:$addr,
6270 rGPR:$Rm, pred:$p)>;
6271 def VLD3qWB_register_Asm_16 :
6272 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6273 (ins VecListThreeQ:$list, addrmode6:$addr,
6274 rGPR:$Rm, pred:$p)>;
6275 def VLD3qWB_register_Asm_32 :
6276 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6277 (ins VecListThreeQ:$list, addrmode6:$addr,
6278 rGPR:$Rm, pred:$p)>;
6280 // VST3 single-lane pseudo-instructions. These need special handling for
6281 // the lane index that an InstAlias can't handle, so we use these instead.
6282 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6283 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6284 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6285 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6286 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6287 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6288 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6289 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6290 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6291 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6293 def VST3LNdWB_fixed_Asm_8 :
6294 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6295 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6296 def VST3LNdWB_fixed_Asm_16 :
6297 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6298 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6299 def VST3LNdWB_fixed_Asm_32 :
6300 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6301 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6302 def VST3LNqWB_fixed_Asm_16 :
6303 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6304 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6305 def VST3LNqWB_fixed_Asm_32 :
6306 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6307 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6308 def VST3LNdWB_register_Asm_8 :
6309 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6310 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6311 rGPR:$Rm, pred:$p)>;
6312 def VST3LNdWB_register_Asm_16 :
6313 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6314 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6315 rGPR:$Rm, pred:$p)>;
6316 def VST3LNdWB_register_Asm_32 :
6317 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6318 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6319 rGPR:$Rm, pred:$p)>;
6320 def VST3LNqWB_register_Asm_16 :
6321 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6322 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6323 rGPR:$Rm, pred:$p)>;
6324 def VST3LNqWB_register_Asm_32 :
6325 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6326 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6327 rGPR:$Rm, pred:$p)>;
6330 // VST3 multiple structure pseudo-instructions. These need special handling for
6331 // the vector operands that the normal instructions don't yet model.
6332 // FIXME: Remove these when the register classes and instructions are updated.
6333 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6334 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6335 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6336 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6337 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6338 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6339 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6340 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6341 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6342 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6343 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6344 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6346 def VST3dWB_fixed_Asm_8 :
6347 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6348 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6349 def VST3dWB_fixed_Asm_16 :
6350 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6351 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6352 def VST3dWB_fixed_Asm_32 :
6353 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6354 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6355 def VST3qWB_fixed_Asm_8 :
6356 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6357 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6358 def VST3qWB_fixed_Asm_16 :
6359 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6360 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6361 def VST3qWB_fixed_Asm_32 :
6362 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6363 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6364 def VST3dWB_register_Asm_8 :
6365 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6366 (ins VecListThreeD:$list, addrmode6:$addr,
6367 rGPR:$Rm, pred:$p)>;
6368 def VST3dWB_register_Asm_16 :
6369 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6370 (ins VecListThreeD:$list, addrmode6:$addr,
6371 rGPR:$Rm, pred:$p)>;
6372 def VST3dWB_register_Asm_32 :
6373 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6374 (ins VecListThreeD:$list, addrmode6:$addr,
6375 rGPR:$Rm, pred:$p)>;
6376 def VST3qWB_register_Asm_8 :
6377 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6378 (ins VecListThreeQ:$list, addrmode6:$addr,
6379 rGPR:$Rm, pred:$p)>;
6380 def VST3qWB_register_Asm_16 :
6381 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6382 (ins VecListThreeQ:$list, addrmode6:$addr,
6383 rGPR:$Rm, pred:$p)>;
6384 def VST3qWB_register_Asm_32 :
6385 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6386 (ins VecListThreeQ:$list, addrmode6:$addr,
6387 rGPR:$Rm, pred:$p)>;
6389 // VLD4 all-lanes pseudo-instructions. These need special handling for
6390 // the lane index that an InstAlias can't handle, so we use these instead.
6391 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6392 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6393 def VLD4DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6394 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6395 def VLD4DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6396 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6397 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6398 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6399 def VLD4DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6400 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6401 def VLD4DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6402 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6404 def VLD4DUPdWB_fixed_Asm_8 :
6405 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6406 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6407 def VLD4DUPdWB_fixed_Asm_16 :
6408 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6409 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6410 def VLD4DUPdWB_fixed_Asm_32 :
6411 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6412 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6413 def VLD4DUPqWB_fixed_Asm_8 :
6414 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6415 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6416 def VLD4DUPqWB_fixed_Asm_16 :
6417 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6418 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6419 def VLD4DUPqWB_fixed_Asm_32 :
6420 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6421 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6422 def VLD4DUPdWB_register_Asm_8 :
6423 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6424 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6425 rGPR:$Rm, pred:$p)>;
6426 def VLD4DUPdWB_register_Asm_16 :
6427 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6428 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6429 rGPR:$Rm, pred:$p)>;
6430 def VLD4DUPdWB_register_Asm_32 :
6431 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6432 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6433 rGPR:$Rm, pred:$p)>;
6434 def VLD4DUPqWB_register_Asm_8 :
6435 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6436 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6437 rGPR:$Rm, pred:$p)>;
6438 def VLD4DUPqWB_register_Asm_16 :
6439 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6440 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6441 rGPR:$Rm, pred:$p)>;
6442 def VLD4DUPqWB_register_Asm_32 :
6443 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6444 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6445 rGPR:$Rm, pred:$p)>;
6448 // VLD4 single-lane pseudo-instructions. These need special handling for
6449 // the lane index that an InstAlias can't handle, so we use these instead.
6450 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6451 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6452 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6453 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6454 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6455 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6456 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6457 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6458 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6459 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6461 def VLD4LNdWB_fixed_Asm_8 :
6462 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6463 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6464 def VLD4LNdWB_fixed_Asm_16 :
6465 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6466 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6467 def VLD4LNdWB_fixed_Asm_32 :
6468 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6469 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6470 def VLD4LNqWB_fixed_Asm_16 :
6471 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6472 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6473 def VLD4LNqWB_fixed_Asm_32 :
6474 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6475 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6476 def VLD4LNdWB_register_Asm_8 :
6477 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6478 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6479 rGPR:$Rm, pred:$p)>;
6480 def VLD4LNdWB_register_Asm_16 :
6481 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6482 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6483 rGPR:$Rm, pred:$p)>;
6484 def VLD4LNdWB_register_Asm_32 :
6485 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6486 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6487 rGPR:$Rm, pred:$p)>;
6488 def VLD4LNqWB_register_Asm_16 :
6489 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6490 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6491 rGPR:$Rm, pred:$p)>;
6492 def VLD4LNqWB_register_Asm_32 :
6493 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6494 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6495 rGPR:$Rm, pred:$p)>;
6499 // VLD4 multiple structure pseudo-instructions. These need special handling for
6500 // the vector operands that the normal instructions don't yet model.
6501 // FIXME: Remove these when the register classes and instructions are updated.
6502 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6503 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6504 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6505 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6506 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6507 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6508 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6509 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6510 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6511 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6512 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6513 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6515 def VLD4dWB_fixed_Asm_8 :
6516 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6517 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6518 def VLD4dWB_fixed_Asm_16 :
6519 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6520 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6521 def VLD4dWB_fixed_Asm_32 :
6522 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6523 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6524 def VLD4qWB_fixed_Asm_8 :
6525 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6526 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6527 def VLD4qWB_fixed_Asm_16 :
6528 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6529 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6530 def VLD4qWB_fixed_Asm_32 :
6531 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6532 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6533 def VLD4dWB_register_Asm_8 :
6534 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6535 (ins VecListFourD:$list, addrmode6:$addr,
6536 rGPR:$Rm, pred:$p)>;
6537 def VLD4dWB_register_Asm_16 :
6538 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6539 (ins VecListFourD:$list, addrmode6:$addr,
6540 rGPR:$Rm, pred:$p)>;
6541 def VLD4dWB_register_Asm_32 :
6542 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6543 (ins VecListFourD:$list, addrmode6:$addr,
6544 rGPR:$Rm, pred:$p)>;
6545 def VLD4qWB_register_Asm_8 :
6546 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6547 (ins VecListFourQ:$list, addrmode6:$addr,
6548 rGPR:$Rm, pred:$p)>;
6549 def VLD4qWB_register_Asm_16 :
6550 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6551 (ins VecListFourQ:$list, addrmode6:$addr,
6552 rGPR:$Rm, pred:$p)>;
6553 def VLD4qWB_register_Asm_32 :
6554 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6555 (ins VecListFourQ:$list, addrmode6:$addr,
6556 rGPR:$Rm, pred:$p)>;
6558 // VST4 single-lane pseudo-instructions. These need special handling for
6559 // the lane index that an InstAlias can't handle, so we use these instead.
6560 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6561 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6562 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6563 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6564 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6565 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6566 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6567 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6568 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6569 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6571 def VST4LNdWB_fixed_Asm_8 :
6572 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6573 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6574 def VST4LNdWB_fixed_Asm_16 :
6575 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6576 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6577 def VST4LNdWB_fixed_Asm_32 :
6578 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6579 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6580 def VST4LNqWB_fixed_Asm_16 :
6581 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6582 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6583 def VST4LNqWB_fixed_Asm_32 :
6584 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6585 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6586 def VST4LNdWB_register_Asm_8 :
6587 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6588 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6589 rGPR:$Rm, pred:$p)>;
6590 def VST4LNdWB_register_Asm_16 :
6591 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6592 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6593 rGPR:$Rm, pred:$p)>;
6594 def VST4LNdWB_register_Asm_32 :
6595 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6596 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6597 rGPR:$Rm, pred:$p)>;
6598 def VST4LNqWB_register_Asm_16 :
6599 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6600 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6601 rGPR:$Rm, pred:$p)>;
6602 def VST4LNqWB_register_Asm_32 :
6603 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6604 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6605 rGPR:$Rm, pred:$p)>;
6608 // VST4 multiple structure pseudo-instructions. These need special handling for
6609 // the vector operands that the normal instructions don't yet model.
6610 // FIXME: Remove these when the register classes and instructions are updated.
6611 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6612 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6613 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6614 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6615 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6616 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6617 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6618 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6619 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6620 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6621 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6622 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6624 def VST4dWB_fixed_Asm_8 :
6625 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6626 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6627 def VST4dWB_fixed_Asm_16 :
6628 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6629 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6630 def VST4dWB_fixed_Asm_32 :
6631 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6632 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6633 def VST4qWB_fixed_Asm_8 :
6634 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6635 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6636 def VST4qWB_fixed_Asm_16 :
6637 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6638 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6639 def VST4qWB_fixed_Asm_32 :
6640 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6641 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6642 def VST4dWB_register_Asm_8 :
6643 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6644 (ins VecListFourD:$list, addrmode6:$addr,
6645 rGPR:$Rm, pred:$p)>;
6646 def VST4dWB_register_Asm_16 :
6647 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6648 (ins VecListFourD:$list, addrmode6:$addr,
6649 rGPR:$Rm, pred:$p)>;
6650 def VST4dWB_register_Asm_32 :
6651 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6652 (ins VecListFourD:$list, addrmode6:$addr,
6653 rGPR:$Rm, pred:$p)>;
6654 def VST4qWB_register_Asm_8 :
6655 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6656 (ins VecListFourQ:$list, addrmode6:$addr,
6657 rGPR:$Rm, pred:$p)>;
6658 def VST4qWB_register_Asm_16 :
6659 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6660 (ins VecListFourQ:$list, addrmode6:$addr,
6661 rGPR:$Rm, pred:$p)>;
6662 def VST4qWB_register_Asm_32 :
6663 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6664 (ins VecListFourQ:$list, addrmode6:$addr,
6665 rGPR:$Rm, pred:$p)>;
6667 // VMOV takes an optional datatype suffix
6668 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6669 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6670 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6671 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6673 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6674 // D-register versions.
6675 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6676 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6677 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6678 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6679 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6680 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6681 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6682 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6683 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6684 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6685 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6686 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6687 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6688 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6689 // Q-register versions.
6690 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6691 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6692 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6693 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6694 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6695 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6696 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6697 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6698 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6699 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6700 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6701 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6702 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6703 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6705 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6706 // D-register versions.
6707 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
6708 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6709 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
6710 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6711 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
6712 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6713 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
6714 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6715 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
6716 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6717 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
6718 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6719 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
6720 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6721 // Q-register versions.
6722 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
6723 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6724 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
6725 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6726 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
6727 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6728 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
6729 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6730 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
6731 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6732 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
6733 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6734 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
6735 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6737 // Two-operand variants for VEXT
6738 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
6739 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
6740 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
6741 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
6742 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
6743 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
6745 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
6746 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
6747 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
6748 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
6749 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
6750 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
6751 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
6752 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
6754 // Two-operand variants for VQDMULH
6755 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
6756 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6757 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
6758 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6760 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
6761 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6762 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
6763 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6765 // Two-operand variants for VMAX.
6766 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
6767 (VMAXsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6768 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
6769 (VMAXsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6770 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
6771 (VMAXsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6772 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
6773 (VMAXuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6774 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
6775 (VMAXuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6776 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
6777 (VMAXuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6778 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
6779 (VMAXfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6781 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
6782 (VMAXsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6783 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
6784 (VMAXsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6785 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
6786 (VMAXsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6787 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
6788 (VMAXuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6789 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
6790 (VMAXuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6791 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
6792 (VMAXuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6793 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
6794 (VMAXfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6796 // Two-operand variants for VMIN.
6797 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
6798 (VMINsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6799 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
6800 (VMINsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6801 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6802 (VMINsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6803 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6804 (VMINuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6805 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6806 (VMINuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6807 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6808 (VMINuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6809 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6810 (VMINfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6812 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
6813 (VMINsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6814 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
6815 (VMINsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6816 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6817 (VMINsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6818 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6819 (VMINuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6820 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6821 (VMINuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6822 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6823 (VMINuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6824 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6825 (VMINfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6827 // Two-operand variants for VPADD.
6828 def : NEONInstAlias<"vpadd${p}.i8 $Vdn, $Vm",
6829 (VPADDi8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6830 def : NEONInstAlias<"vpadd${p}.i16 $Vdn, $Vm",
6831 (VPADDi16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6832 def : NEONInstAlias<"vpadd${p}.i32 $Vdn, $Vm",
6833 (VPADDi32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6834 def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm",
6835 (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6837 // Two-operand variants for VSRA.
6839 def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm",
6840 (VSRAsv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6841 def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm",
6842 (VSRAsv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6843 def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm",
6844 (VSRAsv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6845 def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm",
6846 (VSRAsv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6848 def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm",
6849 (VSRAsv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6850 def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm",
6851 (VSRAsv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6852 def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm",
6853 (VSRAsv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6854 def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm",
6855 (VSRAsv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6858 def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm",
6859 (VSRAuv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6860 def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm",
6861 (VSRAuv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6862 def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm",
6863 (VSRAuv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6864 def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm",
6865 (VSRAuv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6867 def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm",
6868 (VSRAuv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6869 def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm",
6870 (VSRAuv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6871 def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm",
6872 (VSRAuv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6873 def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm",
6874 (VSRAuv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6876 // Two-operand variants for VSRI.
6877 def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm",
6878 (VSRIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6879 def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm",
6880 (VSRIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6881 def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm",
6882 (VSRIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6883 def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm",
6884 (VSRIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6886 def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm",
6887 (VSRIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6888 def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm",
6889 (VSRIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6890 def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm",
6891 (VSRIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6892 def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm",
6893 (VSRIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6895 // Two-operand variants for VSLI.
6896 def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm",
6897 (VSLIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6898 def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm",
6899 (VSLIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6900 def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
6901 (VSLIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6902 def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
6903 (VSLIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6905 def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm",
6906 (VSLIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>;
6907 def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm",
6908 (VSLIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>;
6909 def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
6910 (VSLIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>;
6911 def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
6912 (VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
6914 // VSWP allows, but does not require, a type suffix.
6915 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6916 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
6917 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6918 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6920 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
6921 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6922 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6923 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6924 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6925 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6926 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6927 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6928 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6929 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6930 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6931 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6932 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6934 // "vmov Rd, #-imm" can be handled via "vmvn".
6935 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6936 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6937 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6938 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6939 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6940 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6941 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6942 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6944 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6945 // these should restrict to just the Q register variants, but the register
6946 // classes are enough to match correctly regardless, so we keep it simple
6947 // and just use MnemonicAlias.
6948 def : NEONMnemonicAlias<"vbicq", "vbic">;
6949 def : NEONMnemonicAlias<"vandq", "vand">;
6950 def : NEONMnemonicAlias<"veorq", "veor">;
6951 def : NEONMnemonicAlias<"vorrq", "vorr">;
6953 def : NEONMnemonicAlias<"vmovq", "vmov">;
6954 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
6955 // Explicit versions for floating point so that the FPImm variants get
6956 // handled early. The parser gets confused otherwise.
6957 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6958 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
6960 def : NEONMnemonicAlias<"vaddq", "vadd">;
6961 def : NEONMnemonicAlias<"vsubq", "vsub">;
6963 def : NEONMnemonicAlias<"vminq", "vmin">;
6964 def : NEONMnemonicAlias<"vmaxq", "vmax">;
6966 def : NEONMnemonicAlias<"vmulq", "vmul">;
6968 def : NEONMnemonicAlias<"vabsq", "vabs">;
6970 def : NEONMnemonicAlias<"vshlq", "vshl">;
6971 def : NEONMnemonicAlias<"vshrq", "vshr">;
6973 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6975 def : NEONMnemonicAlias<"vcleq", "vcle">;
6976 def : NEONMnemonicAlias<"vceqq", "vceq">;
6978 def : NEONMnemonicAlias<"vzipq", "vzip">;
6979 def : NEONMnemonicAlias<"vswpq", "vswp">;
6981 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6982 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
6985 // Alias for loading floating point immediates that aren't representable
6986 // using the vmov.f32 encoding but the bitpattern is representable using
6987 // the .i32 encoding.
6988 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6989 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
6990 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6991 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;