1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
485 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
486 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
487 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
489 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
491 // Classes for VLD*LN pseudo-instructions with multi-register operands.
492 // These are expanded to real instructions after register allocation.
493 class VLDQLNPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst),
495 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
496 itin, "$src = $dst">;
497 class VLDQLNWBPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
499 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
500 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
501 class VLDQQLNPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst),
503 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
504 itin, "$src = $dst">;
505 class VLDQQLNWBPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
507 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
508 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
509 class VLDQQQQLNPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst),
511 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
512 itin, "$src = $dst">;
513 class VLDQQQQLNWBPseudo<InstrItinClass itin>
514 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
515 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
516 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
518 // VLD1LN : Vector Load (single element to one lane)
519 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
521 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
522 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
523 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
525 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
526 (i32 (LoadOp addrmode6:$Rn)),
530 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
531 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
532 (i32 (LoadOp addrmode6:$addr)),
536 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
537 let Inst{7-5} = lane{2-0};
539 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
540 let Inst{7-6} = lane{1-0};
543 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
544 let Inst{7} = lane{0};
549 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
550 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
551 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
553 def : Pat<(vector_insert (v2f32 DPR:$src),
554 (f32 (load addrmode6:$addr)), imm:$lane),
555 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
556 def : Pat<(vector_insert (v4f32 QPR:$src),
557 (f32 (load addrmode6:$addr)), imm:$lane),
558 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
560 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
562 // ...with address register writeback:
563 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
564 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
565 (ins addrmode6:$Rn, am6offset:$Rm,
566 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
567 "\\{$Vd[$lane]\\}, $Rn$Rm",
568 "$src = $Vd, $Rn.addr = $wb", []>;
570 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
571 let Inst{7-5} = lane{2-0};
573 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
574 let Inst{7-6} = lane{1-0};
577 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
578 let Inst{7} = lane{0};
583 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
584 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
585 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
587 // VLD2LN : Vector Load (single 2-element structure to one lane)
588 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
589 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
590 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
591 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
592 "$src1 = $Vd, $src2 = $dst2", []> {
597 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
598 let Inst{7-5} = lane{2-0};
600 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
601 let Inst{7-6} = lane{1-0};
603 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
604 let Inst{7} = lane{0};
607 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
608 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
609 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
611 // ...with double-spaced registers:
612 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
613 let Inst{7-6} = lane{1-0};
615 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
616 let Inst{7} = lane{0};
619 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
620 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
622 // ...with address register writeback:
623 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
624 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
625 (ins addrmode6:$Rn, am6offset:$Rm,
626 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
627 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
628 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
632 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
633 let Inst{7-5} = lane{2-0};
635 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
636 let Inst{7-6} = lane{1-0};
638 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
639 let Inst{7} = lane{0};
642 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
643 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
644 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
646 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
647 let Inst{7-6} = lane{1-0};
649 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
650 let Inst{7} = lane{0};
653 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
654 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
656 // VLD3LN : Vector Load (single 3-element structure to one lane)
657 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
658 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
659 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
660 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
661 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
662 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
666 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
667 let Inst{7-5} = lane{2-0};
669 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
670 let Inst{7-6} = lane{1-0};
672 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
673 let Inst{7} = lane{0};
676 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
677 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
678 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
680 // ...with double-spaced registers:
681 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
682 let Inst{7-6} = lane{1-0};
684 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
685 let Inst{7} = lane{0};
688 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
689 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
691 // ...with address register writeback:
692 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
693 : NLdStLn<1, 0b10, op11_8, op7_4,
694 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
695 (ins addrmode6:$Rn, am6offset:$Rm,
696 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
697 IIC_VLD3lnu, "vld3", Dt,
698 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
699 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
702 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
703 let Inst{7-5} = lane{2-0};
705 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
706 let Inst{7-6} = lane{1-0};
708 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
709 let Inst{7} = lane{0};
712 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
713 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
714 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
716 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
717 let Inst{7-6} = lane{1-0};
719 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
720 let Inst{7} = lane{0};
723 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
724 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
726 // VLD4LN : Vector Load (single 4-element structure to one lane)
727 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
728 : NLdStLn<1, 0b10, op11_8, op7_4,
729 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
730 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
731 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
732 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
733 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
738 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
739 let Inst{7-5} = lane{2-0};
741 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
742 let Inst{7-6} = lane{1-0};
744 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
745 let Inst{7} = lane{0};
749 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
750 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
751 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
753 // ...with double-spaced registers:
754 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
755 let Inst{7-6} = lane{1-0};
757 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
758 let Inst{7} = lane{0};
762 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
763 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
765 // ...with address register writeback:
766 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
767 : NLdStLn<1, 0b10, op11_8, op7_4,
768 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
769 (ins addrmode6:$Rn, am6offset:$Rm,
770 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
771 IIC_VLD4lnu, "vld4", Dt,
772 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
773 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
778 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
779 let Inst{7-5} = lane{2-0};
781 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
782 let Inst{7-6} = lane{1-0};
784 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
785 let Inst{7} = lane{0};
789 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
790 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
791 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
793 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
794 let Inst{7-6} = lane{1-0};
796 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
797 let Inst{7} = lane{0};
801 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
802 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
804 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
806 // VLD1DUP : Vector Load (single element to all lanes)
807 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
808 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
809 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
810 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
814 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
815 let Pattern = [(set QPR:$dst,
816 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
819 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
820 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
821 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
823 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
824 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
825 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
827 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
828 (VLD1DUPd32 addrmode6:$addr)>;
829 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
830 (VLD1DUPq32Pseudo addrmode6:$addr)>;
832 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
834 class VLD1QDUP<bits<4> op7_4, string Dt>
835 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
836 (ins addrmode6dup:$Rn), IIC_VLD1dup,
837 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
842 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
843 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
844 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
846 // ...with address register writeback:
847 class VLD1DUPWB<bits<4> op7_4, string Dt>
848 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
849 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
850 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
853 class VLD1QDUPWB<bits<4> op7_4, string Dt>
854 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
855 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
856 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
860 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
861 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
862 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
864 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
865 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
866 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
868 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
869 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
870 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
872 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
873 class VLD2DUP<bits<4> op7_4, string Dt>
874 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
875 (ins addrmode6dup:$Rn), IIC_VLD2dup,
876 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
881 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
882 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
883 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
885 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
886 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
887 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
889 // ...with double-spaced registers (not used for codegen):
890 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
891 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
892 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
894 // ...with address register writeback:
895 class VLD2DUPWB<bits<4> op7_4, string Dt>
896 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
897 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
898 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
902 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
903 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
904 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
906 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
907 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
908 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
910 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
911 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
912 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
914 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
915 class VLD3DUP<bits<4> op7_4, string Dt>
916 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
917 (ins addrmode6dup:$Rn), IIC_VLD3dup,
918 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
923 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
924 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
925 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
927 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
928 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
929 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
931 // ...with double-spaced registers (not used for codegen):
932 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
933 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
934 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
936 // ...with address register writeback:
937 class VLD3DUPWB<bits<4> op7_4, string Dt>
938 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
939 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
940 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
941 "$Rn.addr = $wb", []> {
945 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
946 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
947 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
949 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
950 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
951 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
953 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
954 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
955 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
957 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
958 class VLD4DUP<bits<4> op7_4, string Dt>
959 : NLdSt<1, 0b10, 0b1111, op7_4,
960 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
961 (ins addrmode6dup:$Rn), IIC_VLD4dup,
962 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
967 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
968 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
969 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
971 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
972 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
973 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
975 // ...with double-spaced registers (not used for codegen):
976 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
977 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
978 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
980 // ...with address register writeback:
981 class VLD4DUPWB<bits<4> op7_4, string Dt>
982 : NLdSt<1, 0b10, 0b1111, op7_4,
983 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
984 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
985 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
986 "$Rn.addr = $wb", []> {
990 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
991 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
992 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
994 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
995 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
996 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
998 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
999 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1000 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1002 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1004 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1006 // Classes for VST* pseudo-instructions with multi-register operands.
1007 // These are expanded to real instructions after register allocation.
1008 class VSTQPseudo<InstrItinClass itin>
1009 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1010 class VSTQWBPseudo<InstrItinClass itin>
1011 : PseudoNLdSt<(outs GPR:$wb),
1012 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1013 "$addr.addr = $wb">;
1014 class VSTQQPseudo<InstrItinClass itin>
1015 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1016 class VSTQQWBPseudo<InstrItinClass itin>
1017 : PseudoNLdSt<(outs GPR:$wb),
1018 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1019 "$addr.addr = $wb">;
1020 class VSTQQQQWBPseudo<InstrItinClass itin>
1021 : PseudoNLdSt<(outs GPR:$wb),
1022 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1023 "$addr.addr = $wb">;
1025 // VST1 : Vector Store (multiple single elements)
1026 class VST1D<bits<4> op7_4, string Dt>
1027 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1028 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1030 let Inst{4} = Rn{4};
1032 class VST1Q<bits<4> op7_4, string Dt>
1033 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1034 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1035 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1037 let Inst{5-4} = Rn{5-4};
1040 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1041 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1042 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1043 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1045 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1046 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1047 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1048 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1050 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1051 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1052 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1053 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1055 // ...with address register writeback:
1056 class VST1DWB<bits<4> op7_4, string Dt>
1057 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1058 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1059 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1060 let Inst{4} = Rn{4};
1062 class VST1QWB<bits<4> op7_4, string Dt>
1063 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1064 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1065 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1066 "$Rn.addr = $wb", []> {
1067 let Inst{5-4} = Rn{5-4};
1070 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1071 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1072 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1073 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1075 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1076 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1077 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1078 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1080 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1081 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1082 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1083 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1085 // ...with 3 registers (some of these are only for the disassembler):
1086 class VST1D3<bits<4> op7_4, string Dt>
1087 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1088 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1089 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1091 let Inst{4} = Rn{4};
1093 class VST1D3WB<bits<4> op7_4, string Dt>
1094 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1095 (ins addrmode6:$Rn, am6offset:$Rm,
1096 DPR:$Vd, DPR:$src2, DPR:$src3),
1097 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1098 "$Rn.addr = $wb", []> {
1099 let Inst{4} = Rn{4};
1102 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1103 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1104 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1105 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1107 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1108 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1109 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1110 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1112 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1113 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1115 // ...with 4 registers (some of these are only for the disassembler):
1116 class VST1D4<bits<4> op7_4, string Dt>
1117 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1118 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1119 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1122 let Inst{5-4} = Rn{5-4};
1124 class VST1D4WB<bits<4> op7_4, string Dt>
1125 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1126 (ins addrmode6:$Rn, am6offset:$Rm,
1127 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1128 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1129 "$Rn.addr = $wb", []> {
1130 let Inst{5-4} = Rn{5-4};
1133 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1134 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1135 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1136 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1138 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1139 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1140 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1141 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1143 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1144 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1146 // VST2 : Vector Store (multiple 2-element structures)
1147 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1148 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1149 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1150 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1152 let Inst{5-4} = Rn{5-4};
1154 class VST2Q<bits<4> op7_4, string Dt>
1155 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1156 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1157 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1160 let Inst{5-4} = Rn{5-4};
1163 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1164 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1165 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1167 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1168 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1169 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1171 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1172 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1173 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1175 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1176 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1177 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1179 // ...with address register writeback:
1180 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1181 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1182 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1183 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1184 "$Rn.addr = $wb", []> {
1185 let Inst{5-4} = Rn{5-4};
1187 class VST2QWB<bits<4> op7_4, string Dt>
1188 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1189 (ins addrmode6:$Rn, am6offset:$Rm,
1190 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1191 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1192 "$Rn.addr = $wb", []> {
1193 let Inst{5-4} = Rn{5-4};
1196 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1197 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1198 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1200 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1201 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1202 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1204 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1205 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1206 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1208 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1209 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1210 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1212 // ...with double-spaced registers (for disassembly only):
1213 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1214 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1215 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1216 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1217 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1218 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1220 // VST3 : Vector Store (multiple 3-element structures)
1221 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1222 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1223 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1224 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1226 let Inst{4} = Rn{4};
1229 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1230 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1231 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1233 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1234 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1235 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1237 // ...with address register writeback:
1238 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1239 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1240 (ins addrmode6:$Rn, am6offset:$Rm,
1241 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1242 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1243 "$Rn.addr = $wb", []> {
1244 let Inst{4} = Rn{4};
1247 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1248 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1249 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1251 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1252 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1253 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1255 // ...with double-spaced registers (non-updating versions for disassembly only):
1256 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1257 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1258 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1259 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1260 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1261 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1263 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1264 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1265 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1267 // ...alternate versions to be allocated odd register numbers:
1268 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1269 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1270 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1272 // VST4 : Vector Store (multiple 4-element structures)
1273 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1274 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1275 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1276 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1279 let Inst{5-4} = Rn{5-4};
1282 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1283 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1284 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1286 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1287 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1288 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1290 // ...with address register writeback:
1291 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1292 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1293 (ins addrmode6:$Rn, am6offset:$Rm,
1294 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1295 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1296 "$Rn.addr = $wb", []> {
1297 let Inst{5-4} = Rn{5-4};
1300 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1301 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1302 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1304 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1305 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1306 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1308 // ...with double-spaced registers (non-updating versions for disassembly only):
1309 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1310 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1311 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1312 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1313 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1314 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1316 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1317 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1318 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1320 // ...alternate versions to be allocated odd register numbers:
1321 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1322 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1323 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1325 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1327 // Classes for VST*LN pseudo-instructions with multi-register operands.
1328 // These are expanded to real instructions after register allocation.
1329 class VSTQLNPseudo<InstrItinClass itin>
1330 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1332 class VSTQLNWBPseudo<InstrItinClass itin>
1333 : PseudoNLdSt<(outs GPR:$wb),
1334 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1335 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1336 class VSTQQLNPseudo<InstrItinClass itin>
1337 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1339 class VSTQQLNWBPseudo<InstrItinClass itin>
1340 : PseudoNLdSt<(outs GPR:$wb),
1341 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1342 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1343 class VSTQQQQLNPseudo<InstrItinClass itin>
1344 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1346 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1347 : PseudoNLdSt<(outs GPR:$wb),
1348 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1349 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1351 // VST1LN : Vector Store (single element from one lane)
1352 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1353 PatFrag StoreOp, SDNode ExtractOp>
1354 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1355 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1356 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1357 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1360 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1361 : VSTQLNPseudo<IIC_VST1ln> {
1362 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1366 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1368 let Inst{7-5} = lane{2-0};
1370 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1372 let Inst{7-6} = lane{1-0};
1373 let Inst{4} = Rn{5};
1375 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1376 let Inst{7} = lane{0};
1377 let Inst{5-4} = Rn{5-4};
1380 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1381 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1382 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1384 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1385 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1386 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1387 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1389 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1391 // ...with address register writeback:
1392 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1393 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1394 (ins addrmode6:$Rn, am6offset:$Rm,
1395 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1396 "\\{$Vd[$lane]\\}, $Rn$Rm",
1397 "$Rn.addr = $wb", []>;
1399 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1400 let Inst{7-5} = lane{2-0};
1402 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1403 let Inst{7-6} = lane{1-0};
1404 let Inst{4} = Rn{5};
1406 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1407 let Inst{7} = lane{0};
1408 let Inst{5-4} = Rn{5-4};
1411 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1412 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1413 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1415 // VST2LN : Vector Store (single 2-element structure from one lane)
1416 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1417 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1418 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1419 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1422 let Inst{4} = Rn{4};
1425 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1426 let Inst{7-5} = lane{2-0};
1428 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1429 let Inst{7-6} = lane{1-0};
1431 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1432 let Inst{7} = lane{0};
1435 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1436 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1437 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1439 // ...with double-spaced registers:
1440 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1441 let Inst{7-6} = lane{1-0};
1442 let Inst{4} = Rn{4};
1444 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1445 let Inst{7} = lane{0};
1446 let Inst{4} = Rn{4};
1449 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1450 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1452 // ...with address register writeback:
1453 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1454 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1455 (ins addrmode6:$addr, am6offset:$offset,
1456 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1457 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1458 "$addr.addr = $wb", []> {
1459 let Inst{4} = Rn{4};
1462 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1463 let Inst{7-5} = lane{2-0};
1465 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1466 let Inst{7-6} = lane{1-0};
1468 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1469 let Inst{7} = lane{0};
1472 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1473 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1474 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1476 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1477 let Inst{7-6} = lane{1-0};
1479 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1480 let Inst{7} = lane{0};
1483 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1484 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1486 // VST3LN : Vector Store (single 3-element structure from one lane)
1487 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1488 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1489 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1490 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1491 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1495 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1496 let Inst{7-5} = lane{2-0};
1498 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1499 let Inst{7-6} = lane{1-0};
1501 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1502 let Inst{7} = lane{0};
1505 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1506 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1507 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1509 // ...with double-spaced registers:
1510 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1511 let Inst{7-6} = lane{1-0};
1513 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1514 let Inst{7} = lane{0};
1517 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1518 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1520 // ...with address register writeback:
1521 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1522 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1523 (ins addrmode6:$Rn, am6offset:$Rm,
1524 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1525 IIC_VST3lnu, "vst3", Dt,
1526 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1527 "$Rn.addr = $wb", []>;
1529 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1530 let Inst{7-5} = lane{2-0};
1532 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1533 let Inst{7-6} = lane{1-0};
1535 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1536 let Inst{7} = lane{0};
1539 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1540 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1541 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1543 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1544 let Inst{7-6} = lane{1-0};
1546 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1547 let Inst{7} = lane{0};
1550 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1551 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1553 // VST4LN : Vector Store (single 4-element structure from one lane)
1554 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1555 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1556 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1557 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1558 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1561 let Inst{4} = Rn{4};
1564 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1565 let Inst{7-5} = lane{2-0};
1567 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1568 let Inst{7-6} = lane{1-0};
1570 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1571 let Inst{7} = lane{0};
1572 let Inst{5} = Rn{5};
1575 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1576 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1577 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1579 // ...with double-spaced registers:
1580 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1581 let Inst{7-6} = lane{1-0};
1583 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1584 let Inst{7} = lane{0};
1585 let Inst{5} = Rn{5};
1588 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1589 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1591 // ...with address register writeback:
1592 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1593 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1594 (ins addrmode6:$Rn, am6offset:$Rm,
1595 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1596 IIC_VST4lnu, "vst4", Dt,
1597 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1598 "$Rn.addr = $wb", []> {
1599 let Inst{4} = Rn{4};
1602 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1603 let Inst{7-5} = lane{2-0};
1605 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1606 let Inst{7-6} = lane{1-0};
1608 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1609 let Inst{7} = lane{0};
1610 let Inst{5} = Rn{5};
1613 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1614 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1615 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1617 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1618 let Inst{7-6} = lane{1-0};
1620 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1621 let Inst{7} = lane{0};
1622 let Inst{5} = Rn{5};
1625 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1626 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1628 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1631 //===----------------------------------------------------------------------===//
1632 // NEON pattern fragments
1633 //===----------------------------------------------------------------------===//
1635 // Extract D sub-registers of Q registers.
1636 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1637 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1638 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1640 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1641 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1642 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1644 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1645 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1646 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1648 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1649 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1650 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1653 // Extract S sub-registers of Q/D registers.
1654 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1655 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1656 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1659 // Translate lane numbers from Q registers to D subregs.
1660 def SubReg_i8_lane : SDNodeXForm<imm, [{
1661 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1663 def SubReg_i16_lane : SDNodeXForm<imm, [{
1664 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1666 def SubReg_i32_lane : SDNodeXForm<imm, [{
1667 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1670 //===----------------------------------------------------------------------===//
1671 // Instruction Classes
1672 //===----------------------------------------------------------------------===//
1674 // Basic 2-register operations: double- and quad-register.
1675 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1676 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1677 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1678 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1679 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1680 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1681 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1682 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1683 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1684 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1685 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1686 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1688 // Basic 2-register intrinsics, both double- and quad-register.
1689 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1690 bits<2> op17_16, bits<5> op11_7, bit op4,
1691 InstrItinClass itin, string OpcodeStr, string Dt,
1692 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1693 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1694 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1695 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1696 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1697 bits<2> op17_16, bits<5> op11_7, bit op4,
1698 InstrItinClass itin, string OpcodeStr, string Dt,
1699 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1700 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1701 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1702 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1704 // Narrow 2-register operations.
1705 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1706 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1707 InstrItinClass itin, string OpcodeStr, string Dt,
1708 ValueType TyD, ValueType TyQ, SDNode OpNode>
1709 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1710 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1711 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1713 // Narrow 2-register intrinsics.
1714 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1715 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1716 InstrItinClass itin, string OpcodeStr, string Dt,
1717 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1718 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1719 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1720 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1722 // Long 2-register operations (currently only used for VMOVL).
1723 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1724 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1725 InstrItinClass itin, string OpcodeStr, string Dt,
1726 ValueType TyQ, ValueType TyD, SDNode OpNode>
1727 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1728 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1729 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1731 // Long 2-register intrinsics.
1732 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1733 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1734 InstrItinClass itin, string OpcodeStr, string Dt,
1735 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1736 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1737 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1738 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1740 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1741 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1742 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1743 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1744 OpcodeStr, Dt, "$Vd, $Vm",
1745 "$src1 = $Vd, $src2 = $Vm", []>;
1746 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1747 InstrItinClass itin, string OpcodeStr, string Dt>
1748 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1749 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1750 "$src1 = $Vd, $src2 = $Vm", []>;
1752 // Basic 3-register operations: double- and quad-register.
1753 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1754 InstrItinClass itin, string OpcodeStr, string Dt,
1755 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1756 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1757 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1758 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1759 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1760 let isCommutable = Commutable;
1762 // Same as N3VD but no data type.
1763 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1764 InstrItinClass itin, string OpcodeStr,
1765 ValueType ResTy, ValueType OpTy,
1766 SDNode OpNode, bit Commutable>
1767 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1768 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1769 OpcodeStr, "$Vd, $Vn, $Vm", "",
1770 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1771 let isCommutable = Commutable;
1774 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1775 InstrItinClass itin, string OpcodeStr, string Dt,
1776 ValueType Ty, SDNode ShOp>
1777 : N3V<0, 1, op21_20, op11_8, 1, 0,
1778 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1779 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1781 (Ty (ShOp (Ty DPR:$Vn),
1782 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1783 let isCommutable = 0;
1785 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1786 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1787 : N3V<0, 1, op21_20, op11_8, 1, 0,
1788 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1789 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1791 (Ty (ShOp (Ty DPR:$Vn),
1792 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1793 let isCommutable = 0;
1796 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1797 InstrItinClass itin, string OpcodeStr, string Dt,
1798 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1799 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1800 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1801 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1802 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1803 let isCommutable = Commutable;
1805 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1806 InstrItinClass itin, string OpcodeStr,
1807 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1808 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1809 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1810 OpcodeStr, "$Vd, $Vn, $Vm", "",
1811 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1812 let isCommutable = Commutable;
1814 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1815 InstrItinClass itin, string OpcodeStr, string Dt,
1816 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1817 : N3V<1, 1, op21_20, op11_8, 1, 0,
1818 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1819 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1820 [(set (ResTy QPR:$Vd),
1821 (ResTy (ShOp (ResTy QPR:$Vn),
1822 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1824 let isCommutable = 0;
1826 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1827 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1828 : N3V<1, 1, op21_20, op11_8, 1, 0,
1829 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1830 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1831 [(set (ResTy QPR:$Vd),
1832 (ResTy (ShOp (ResTy QPR:$Vn),
1833 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1835 let isCommutable = 0;
1838 // Basic 3-register intrinsics, both double- and quad-register.
1839 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1840 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1841 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1842 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1843 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1844 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1845 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1846 let isCommutable = Commutable;
1848 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1849 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1850 : N3V<0, 1, op21_20, op11_8, 1, 0,
1851 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1852 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1854 (Ty (IntOp (Ty DPR:$Vn),
1855 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1857 let isCommutable = 0;
1859 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1860 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1861 : N3V<0, 1, op21_20, op11_8, 1, 0,
1862 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1863 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1865 (Ty (IntOp (Ty DPR:$Vn),
1866 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1867 let isCommutable = 0;
1869 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1870 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1871 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1872 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1873 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1874 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1875 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1876 let isCommutable = 0;
1879 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1880 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1881 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1882 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1883 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1884 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1885 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1886 let isCommutable = Commutable;
1888 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1889 string OpcodeStr, string Dt,
1890 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1891 : N3V<1, 1, op21_20, op11_8, 1, 0,
1892 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1893 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1894 [(set (ResTy QPR:$Vd),
1895 (ResTy (IntOp (ResTy QPR:$Vn),
1896 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1898 let isCommutable = 0;
1900 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1901 string OpcodeStr, string Dt,
1902 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1903 : N3V<1, 1, op21_20, op11_8, 1, 0,
1904 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1905 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1906 [(set (ResTy QPR:$Vd),
1907 (ResTy (IntOp (ResTy QPR:$Vn),
1908 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1910 let isCommutable = 0;
1912 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1913 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1914 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1915 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1916 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1917 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1918 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1919 let isCommutable = 0;
1922 // Multiply-Add/Sub operations: double- and quad-register.
1923 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1924 InstrItinClass itin, string OpcodeStr, string Dt,
1925 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1926 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1927 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1928 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1929 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1930 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1932 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1933 string OpcodeStr, string Dt,
1934 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1935 : N3V<0, 1, op21_20, op11_8, 1, 0,
1937 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1939 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1941 (Ty (ShOp (Ty DPR:$src1),
1943 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1945 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1946 string OpcodeStr, string Dt,
1947 ValueType Ty, SDNode MulOp, SDNode ShOp>
1948 : N3V<0, 1, op21_20, op11_8, 1, 0,
1950 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1952 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1954 (Ty (ShOp (Ty DPR:$src1),
1956 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1959 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1960 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1961 SDPatternOperator MulOp, SDPatternOperator OpNode>
1962 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1963 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1964 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1965 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1966 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1967 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1968 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1969 SDPatternOperator MulOp, SDPatternOperator ShOp>
1970 : N3V<1, 1, op21_20, op11_8, 1, 0,
1972 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1974 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1975 [(set (ResTy QPR:$Vd),
1976 (ResTy (ShOp (ResTy QPR:$src1),
1977 (ResTy (MulOp QPR:$Vn,
1978 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1980 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1981 string OpcodeStr, string Dt,
1982 ValueType ResTy, ValueType OpTy,
1983 SDNode MulOp, SDNode ShOp>
1984 : N3V<1, 1, op21_20, op11_8, 1, 0,
1986 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1988 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1989 [(set (ResTy QPR:$Vd),
1990 (ResTy (ShOp (ResTy QPR:$src1),
1991 (ResTy (MulOp QPR:$Vn,
1992 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1995 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1996 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1997 InstrItinClass itin, string OpcodeStr, string Dt,
1998 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1999 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2000 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2001 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2002 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2003 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2004 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2005 InstrItinClass itin, string OpcodeStr, string Dt,
2006 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2007 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2008 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2009 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2010 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2011 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2013 // Neon 3-argument intrinsics, both double- and quad-register.
2014 // The destination register is also used as the first source operand register.
2015 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2016 InstrItinClass itin, string OpcodeStr, string Dt,
2017 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2018 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2019 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2020 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2021 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2022 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2023 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2024 InstrItinClass itin, string OpcodeStr, string Dt,
2025 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2026 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2027 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2028 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2029 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2030 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2032 // Long Multiply-Add/Sub operations.
2033 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2034 InstrItinClass itin, string OpcodeStr, string Dt,
2035 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2036 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2037 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2038 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2039 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2040 (TyQ (MulOp (TyD DPR:$Vn),
2041 (TyD DPR:$Vm)))))]>;
2042 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2043 InstrItinClass itin, string OpcodeStr, string Dt,
2044 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2045 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2046 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2048 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2050 (OpNode (TyQ QPR:$src1),
2051 (TyQ (MulOp (TyD DPR:$Vn),
2052 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2054 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2055 InstrItinClass itin, string OpcodeStr, string Dt,
2056 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2057 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2058 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2060 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2062 (OpNode (TyQ QPR:$src1),
2063 (TyQ (MulOp (TyD DPR:$Vn),
2064 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2067 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2068 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2069 InstrItinClass itin, string OpcodeStr, string Dt,
2070 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2072 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2073 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2074 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2075 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2076 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2077 (TyD DPR:$Vm)))))))]>;
2079 // Neon Long 3-argument intrinsic. The destination register is
2080 // a quad-register and is also used as the first source operand register.
2081 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2082 InstrItinClass itin, string OpcodeStr, string Dt,
2083 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2084 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2085 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2086 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2088 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2089 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2090 string OpcodeStr, string Dt,
2091 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2092 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2094 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2096 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2097 [(set (ResTy QPR:$Vd),
2098 (ResTy (IntOp (ResTy QPR:$src1),
2100 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2102 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2103 InstrItinClass itin, string OpcodeStr, string Dt,
2104 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2105 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2107 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2109 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2110 [(set (ResTy QPR:$Vd),
2111 (ResTy (IntOp (ResTy QPR:$src1),
2113 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2116 // Narrowing 3-register intrinsics.
2117 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2118 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2119 Intrinsic IntOp, bit Commutable>
2120 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2121 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2122 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2123 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2124 let isCommutable = Commutable;
2127 // Long 3-register operations.
2128 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2129 InstrItinClass itin, string OpcodeStr, string Dt,
2130 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2131 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2132 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2133 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2134 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2135 let isCommutable = Commutable;
2137 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2138 InstrItinClass itin, string OpcodeStr, string Dt,
2139 ValueType TyQ, ValueType TyD, SDNode OpNode>
2140 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2141 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2142 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2144 (TyQ (OpNode (TyD DPR:$Vn),
2145 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2146 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2147 InstrItinClass itin, string OpcodeStr, string Dt,
2148 ValueType TyQ, ValueType TyD, SDNode OpNode>
2149 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2150 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2151 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2153 (TyQ (OpNode (TyD DPR:$Vn),
2154 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2156 // Long 3-register operations with explicitly extended operands.
2157 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2158 InstrItinClass itin, string OpcodeStr, string Dt,
2159 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2161 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2162 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2163 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2164 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2165 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2166 let isCommutable = Commutable;
2169 // Long 3-register intrinsics with explicit extend (VABDL).
2170 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2171 InstrItinClass itin, string OpcodeStr, string Dt,
2172 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2174 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2175 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2176 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2177 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2178 (TyD DPR:$Vm))))))]> {
2179 let isCommutable = Commutable;
2182 // Long 3-register intrinsics.
2183 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2184 InstrItinClass itin, string OpcodeStr, string Dt,
2185 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2186 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2187 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2188 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2189 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2190 let isCommutable = Commutable;
2192 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2193 string OpcodeStr, string Dt,
2194 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2195 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2196 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2197 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2198 [(set (ResTy QPR:$Vd),
2199 (ResTy (IntOp (OpTy DPR:$Vn),
2200 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2202 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2203 InstrItinClass itin, string OpcodeStr, string Dt,
2204 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2205 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2206 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2207 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2208 [(set (ResTy QPR:$Vd),
2209 (ResTy (IntOp (OpTy DPR:$Vn),
2210 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2213 // Wide 3-register operations.
2214 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2215 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2216 SDNode OpNode, SDNode ExtOp, bit Commutable>
2217 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2218 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2219 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2220 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2221 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2222 let isCommutable = Commutable;
2225 // Pairwise long 2-register intrinsics, both double- and quad-register.
2226 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2227 bits<2> op17_16, bits<5> op11_7, bit op4,
2228 string OpcodeStr, string Dt,
2229 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2230 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2231 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2232 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2233 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2234 bits<2> op17_16, bits<5> op11_7, bit op4,
2235 string OpcodeStr, string Dt,
2236 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2237 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2238 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2239 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2241 // Pairwise long 2-register accumulate intrinsics,
2242 // both double- and quad-register.
2243 // The destination register is also used as the first source operand register.
2244 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2245 bits<2> op17_16, bits<5> op11_7, bit op4,
2246 string OpcodeStr, string Dt,
2247 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2248 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2249 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2250 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2251 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2252 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2253 bits<2> op17_16, bits<5> op11_7, bit op4,
2254 string OpcodeStr, string Dt,
2255 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2256 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2257 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2258 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2259 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2261 // Shift by immediate,
2262 // both double- and quad-register.
2263 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2264 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2265 ValueType Ty, SDNode OpNode>
2266 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2267 (outs DPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), f, itin,
2268 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2269 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2270 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2271 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2272 ValueType Ty, SDNode OpNode>
2273 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2274 (outs QPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), f, itin,
2275 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2276 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2278 // Long shift by immediate.
2279 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2280 string OpcodeStr, string Dt,
2281 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2282 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2283 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2284 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2285 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2286 (i32 imm:$SIMM))))]>;
2288 // Narrow shift by immediate.
2289 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2290 InstrItinClass itin, string OpcodeStr, string Dt,
2291 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2292 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2293 (outs DPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, itin,
2294 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2295 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2296 (i32 imm:$SIMM))))]>;
2298 // Shift right by immediate and accumulate,
2299 // both double- and quad-register.
2300 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2301 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2302 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2303 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2304 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2305 [(set DPR:$Vd, (Ty (add DPR:$src1,
2306 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2307 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2308 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2309 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2310 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2311 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2312 [(set QPR:$Vd, (Ty (add QPR:$src1,
2313 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2315 // Shift by immediate and insert,
2316 // both double- and quad-register.
2317 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2318 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2319 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2320 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2321 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2322 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2323 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2324 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2325 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2326 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2327 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2328 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2330 // Convert, with fractional bits immediate,
2331 // both double- and quad-register.
2332 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2333 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2335 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2336 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2337 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2338 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2339 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2340 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2342 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2343 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2344 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2345 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2347 //===----------------------------------------------------------------------===//
2349 //===----------------------------------------------------------------------===//
2351 // Abbreviations used in multiclass suffixes:
2352 // Q = quarter int (8 bit) elements
2353 // H = half int (16 bit) elements
2354 // S = single int (32 bit) elements
2355 // D = double int (64 bit) elements
2357 // Neon 2-register vector operations and intrinsics.
2359 // Neon 2-register comparisons.
2360 // source operand element sizes of 8, 16 and 32 bits:
2361 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2362 bits<5> op11_7, bit op4, string opc, string Dt,
2363 string asm, SDNode OpNode> {
2364 // 64-bit vector types.
2365 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2366 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2367 opc, !strconcat(Dt, "8"), asm, "",
2368 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2369 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2370 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2371 opc, !strconcat(Dt, "16"), asm, "",
2372 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2373 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2374 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2375 opc, !strconcat(Dt, "32"), asm, "",
2376 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2377 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2378 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2379 opc, "f32", asm, "",
2380 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2381 let Inst{10} = 1; // overwrite F = 1
2384 // 128-bit vector types.
2385 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2386 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2387 opc, !strconcat(Dt, "8"), asm, "",
2388 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2389 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2390 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2391 opc, !strconcat(Dt, "16"), asm, "",
2392 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2393 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2394 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2395 opc, !strconcat(Dt, "32"), asm, "",
2396 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2397 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2398 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2399 opc, "f32", asm, "",
2400 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2401 let Inst{10} = 1; // overwrite F = 1
2406 // Neon 2-register vector intrinsics,
2407 // element sizes of 8, 16 and 32 bits:
2408 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2409 bits<5> op11_7, bit op4,
2410 InstrItinClass itinD, InstrItinClass itinQ,
2411 string OpcodeStr, string Dt, Intrinsic IntOp> {
2412 // 64-bit vector types.
2413 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2414 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2415 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2416 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2417 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2418 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2420 // 128-bit vector types.
2421 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2422 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2423 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2424 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2425 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2426 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2430 // Neon Narrowing 2-register vector operations,
2431 // source operand element sizes of 16, 32 and 64 bits:
2432 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2433 bits<5> op11_7, bit op6, bit op4,
2434 InstrItinClass itin, string OpcodeStr, string Dt,
2436 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2437 itin, OpcodeStr, !strconcat(Dt, "16"),
2438 v8i8, v8i16, OpNode>;
2439 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2440 itin, OpcodeStr, !strconcat(Dt, "32"),
2441 v4i16, v4i32, OpNode>;
2442 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2443 itin, OpcodeStr, !strconcat(Dt, "64"),
2444 v2i32, v2i64, OpNode>;
2447 // Neon Narrowing 2-register vector intrinsics,
2448 // source operand element sizes of 16, 32 and 64 bits:
2449 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2450 bits<5> op11_7, bit op6, bit op4,
2451 InstrItinClass itin, string OpcodeStr, string Dt,
2453 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2454 itin, OpcodeStr, !strconcat(Dt, "16"),
2455 v8i8, v8i16, IntOp>;
2456 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2457 itin, OpcodeStr, !strconcat(Dt, "32"),
2458 v4i16, v4i32, IntOp>;
2459 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2460 itin, OpcodeStr, !strconcat(Dt, "64"),
2461 v2i32, v2i64, IntOp>;
2465 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2466 // source operand element sizes of 16, 32 and 64 bits:
2467 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2468 string OpcodeStr, string Dt, SDNode OpNode> {
2469 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2470 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2471 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2472 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2473 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2474 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2478 // Neon 3-register vector operations.
2480 // First with only element sizes of 8, 16 and 32 bits:
2481 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2482 InstrItinClass itinD16, InstrItinClass itinD32,
2483 InstrItinClass itinQ16, InstrItinClass itinQ32,
2484 string OpcodeStr, string Dt,
2485 SDNode OpNode, bit Commutable = 0> {
2486 // 64-bit vector types.
2487 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2488 OpcodeStr, !strconcat(Dt, "8"),
2489 v8i8, v8i8, OpNode, Commutable>;
2490 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2491 OpcodeStr, !strconcat(Dt, "16"),
2492 v4i16, v4i16, OpNode, Commutable>;
2493 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2494 OpcodeStr, !strconcat(Dt, "32"),
2495 v2i32, v2i32, OpNode, Commutable>;
2497 // 128-bit vector types.
2498 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2499 OpcodeStr, !strconcat(Dt, "8"),
2500 v16i8, v16i8, OpNode, Commutable>;
2501 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2502 OpcodeStr, !strconcat(Dt, "16"),
2503 v8i16, v8i16, OpNode, Commutable>;
2504 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2505 OpcodeStr, !strconcat(Dt, "32"),
2506 v4i32, v4i32, OpNode, Commutable>;
2509 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2510 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2512 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2514 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2515 v8i16, v4i16, ShOp>;
2516 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2517 v4i32, v2i32, ShOp>;
2520 // ....then also with element size 64 bits:
2521 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2522 InstrItinClass itinD, InstrItinClass itinQ,
2523 string OpcodeStr, string Dt,
2524 SDNode OpNode, bit Commutable = 0>
2525 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2526 OpcodeStr, Dt, OpNode, Commutable> {
2527 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2528 OpcodeStr, !strconcat(Dt, "64"),
2529 v1i64, v1i64, OpNode, Commutable>;
2530 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2531 OpcodeStr, !strconcat(Dt, "64"),
2532 v2i64, v2i64, OpNode, Commutable>;
2536 // Neon 3-register vector intrinsics.
2538 // First with only element sizes of 16 and 32 bits:
2539 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2540 InstrItinClass itinD16, InstrItinClass itinD32,
2541 InstrItinClass itinQ16, InstrItinClass itinQ32,
2542 string OpcodeStr, string Dt,
2543 Intrinsic IntOp, bit Commutable = 0> {
2544 // 64-bit vector types.
2545 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2546 OpcodeStr, !strconcat(Dt, "16"),
2547 v4i16, v4i16, IntOp, Commutable>;
2548 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2549 OpcodeStr, !strconcat(Dt, "32"),
2550 v2i32, v2i32, IntOp, Commutable>;
2552 // 128-bit vector types.
2553 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2554 OpcodeStr, !strconcat(Dt, "16"),
2555 v8i16, v8i16, IntOp, Commutable>;
2556 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2557 OpcodeStr, !strconcat(Dt, "32"),
2558 v4i32, v4i32, IntOp, Commutable>;
2560 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2561 InstrItinClass itinD16, InstrItinClass itinD32,
2562 InstrItinClass itinQ16, InstrItinClass itinQ32,
2563 string OpcodeStr, string Dt,
2565 // 64-bit vector types.
2566 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2567 OpcodeStr, !strconcat(Dt, "16"),
2568 v4i16, v4i16, IntOp>;
2569 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2570 OpcodeStr, !strconcat(Dt, "32"),
2571 v2i32, v2i32, IntOp>;
2573 // 128-bit vector types.
2574 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2575 OpcodeStr, !strconcat(Dt, "16"),
2576 v8i16, v8i16, IntOp>;
2577 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2578 OpcodeStr, !strconcat(Dt, "32"),
2579 v4i32, v4i32, IntOp>;
2582 multiclass N3VIntSL_HS<bits<4> op11_8,
2583 InstrItinClass itinD16, InstrItinClass itinD32,
2584 InstrItinClass itinQ16, InstrItinClass itinQ32,
2585 string OpcodeStr, string Dt, Intrinsic IntOp> {
2586 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2587 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2588 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2589 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2590 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2591 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2592 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2593 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2596 // ....then also with element size of 8 bits:
2597 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2598 InstrItinClass itinD16, InstrItinClass itinD32,
2599 InstrItinClass itinQ16, InstrItinClass itinQ32,
2600 string OpcodeStr, string Dt,
2601 Intrinsic IntOp, bit Commutable = 0>
2602 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2603 OpcodeStr, Dt, IntOp, Commutable> {
2604 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2605 OpcodeStr, !strconcat(Dt, "8"),
2606 v8i8, v8i8, IntOp, Commutable>;
2607 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2608 OpcodeStr, !strconcat(Dt, "8"),
2609 v16i8, v16i8, IntOp, Commutable>;
2611 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2612 InstrItinClass itinD16, InstrItinClass itinD32,
2613 InstrItinClass itinQ16, InstrItinClass itinQ32,
2614 string OpcodeStr, string Dt,
2616 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2617 OpcodeStr, Dt, IntOp> {
2618 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2619 OpcodeStr, !strconcat(Dt, "8"),
2621 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2622 OpcodeStr, !strconcat(Dt, "8"),
2623 v16i8, v16i8, IntOp>;
2627 // ....then also with element size of 64 bits:
2628 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2629 InstrItinClass itinD16, InstrItinClass itinD32,
2630 InstrItinClass itinQ16, InstrItinClass itinQ32,
2631 string OpcodeStr, string Dt,
2632 Intrinsic IntOp, bit Commutable = 0>
2633 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2634 OpcodeStr, Dt, IntOp, Commutable> {
2635 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2636 OpcodeStr, !strconcat(Dt, "64"),
2637 v1i64, v1i64, IntOp, Commutable>;
2638 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2639 OpcodeStr, !strconcat(Dt, "64"),
2640 v2i64, v2i64, IntOp, Commutable>;
2642 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2643 InstrItinClass itinD16, InstrItinClass itinD32,
2644 InstrItinClass itinQ16, InstrItinClass itinQ32,
2645 string OpcodeStr, string Dt,
2647 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2648 OpcodeStr, Dt, IntOp> {
2649 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2650 OpcodeStr, !strconcat(Dt, "64"),
2651 v1i64, v1i64, IntOp>;
2652 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2653 OpcodeStr, !strconcat(Dt, "64"),
2654 v2i64, v2i64, IntOp>;
2657 // Neon Narrowing 3-register vector intrinsics,
2658 // source operand element sizes of 16, 32 and 64 bits:
2659 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2660 string OpcodeStr, string Dt,
2661 Intrinsic IntOp, bit Commutable = 0> {
2662 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2663 OpcodeStr, !strconcat(Dt, "16"),
2664 v8i8, v8i16, IntOp, Commutable>;
2665 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2666 OpcodeStr, !strconcat(Dt, "32"),
2667 v4i16, v4i32, IntOp, Commutable>;
2668 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2669 OpcodeStr, !strconcat(Dt, "64"),
2670 v2i32, v2i64, IntOp, Commutable>;
2674 // Neon Long 3-register vector operations.
2676 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2677 InstrItinClass itin16, InstrItinClass itin32,
2678 string OpcodeStr, string Dt,
2679 SDNode OpNode, bit Commutable = 0> {
2680 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2681 OpcodeStr, !strconcat(Dt, "8"),
2682 v8i16, v8i8, OpNode, Commutable>;
2683 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2684 OpcodeStr, !strconcat(Dt, "16"),
2685 v4i32, v4i16, OpNode, Commutable>;
2686 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2687 OpcodeStr, !strconcat(Dt, "32"),
2688 v2i64, v2i32, OpNode, Commutable>;
2691 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2692 InstrItinClass itin, string OpcodeStr, string Dt,
2694 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2695 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2696 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2697 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2700 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2701 InstrItinClass itin16, InstrItinClass itin32,
2702 string OpcodeStr, string Dt,
2703 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2704 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2705 OpcodeStr, !strconcat(Dt, "8"),
2706 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2707 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2708 OpcodeStr, !strconcat(Dt, "16"),
2709 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2710 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2711 OpcodeStr, !strconcat(Dt, "32"),
2712 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2715 // Neon Long 3-register vector intrinsics.
2717 // First with only element sizes of 16 and 32 bits:
2718 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2719 InstrItinClass itin16, InstrItinClass itin32,
2720 string OpcodeStr, string Dt,
2721 Intrinsic IntOp, bit Commutable = 0> {
2722 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2723 OpcodeStr, !strconcat(Dt, "16"),
2724 v4i32, v4i16, IntOp, Commutable>;
2725 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2726 OpcodeStr, !strconcat(Dt, "32"),
2727 v2i64, v2i32, IntOp, Commutable>;
2730 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2731 InstrItinClass itin, string OpcodeStr, string Dt,
2733 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2734 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2735 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2736 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2739 // ....then also with element size of 8 bits:
2740 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2741 InstrItinClass itin16, InstrItinClass itin32,
2742 string OpcodeStr, string Dt,
2743 Intrinsic IntOp, bit Commutable = 0>
2744 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2745 IntOp, Commutable> {
2746 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2747 OpcodeStr, !strconcat(Dt, "8"),
2748 v8i16, v8i8, IntOp, Commutable>;
2751 // ....with explicit extend (VABDL).
2752 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2753 InstrItinClass itin, string OpcodeStr, string Dt,
2754 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2755 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2756 OpcodeStr, !strconcat(Dt, "8"),
2757 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2758 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2759 OpcodeStr, !strconcat(Dt, "16"),
2760 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2761 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2762 OpcodeStr, !strconcat(Dt, "32"),
2763 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2767 // Neon Wide 3-register vector intrinsics,
2768 // source operand element sizes of 8, 16 and 32 bits:
2769 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2770 string OpcodeStr, string Dt,
2771 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2772 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2773 OpcodeStr, !strconcat(Dt, "8"),
2774 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2775 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2776 OpcodeStr, !strconcat(Dt, "16"),
2777 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2778 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2779 OpcodeStr, !strconcat(Dt, "32"),
2780 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2784 // Neon Multiply-Op vector operations,
2785 // element sizes of 8, 16 and 32 bits:
2786 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2787 InstrItinClass itinD16, InstrItinClass itinD32,
2788 InstrItinClass itinQ16, InstrItinClass itinQ32,
2789 string OpcodeStr, string Dt, SDNode OpNode> {
2790 // 64-bit vector types.
2791 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2792 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2793 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2794 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2795 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2796 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2798 // 128-bit vector types.
2799 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2800 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2801 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2802 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2803 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2804 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2807 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2808 InstrItinClass itinD16, InstrItinClass itinD32,
2809 InstrItinClass itinQ16, InstrItinClass itinQ32,
2810 string OpcodeStr, string Dt, SDNode ShOp> {
2811 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2812 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2813 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2814 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2815 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2816 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2818 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2819 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2823 // Neon Intrinsic-Op vector operations,
2824 // element sizes of 8, 16 and 32 bits:
2825 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2826 InstrItinClass itinD, InstrItinClass itinQ,
2827 string OpcodeStr, string Dt, Intrinsic IntOp,
2829 // 64-bit vector types.
2830 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2831 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2832 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2833 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2834 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2835 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2837 // 128-bit vector types.
2838 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2839 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2840 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2841 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2842 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2843 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2846 // Neon 3-argument intrinsics,
2847 // element sizes of 8, 16 and 32 bits:
2848 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2849 InstrItinClass itinD, InstrItinClass itinQ,
2850 string OpcodeStr, string Dt, Intrinsic IntOp> {
2851 // 64-bit vector types.
2852 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2853 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2854 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2855 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2856 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2857 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2859 // 128-bit vector types.
2860 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2861 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2862 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2863 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2864 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2865 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2869 // Neon Long Multiply-Op vector operations,
2870 // element sizes of 8, 16 and 32 bits:
2871 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2872 InstrItinClass itin16, InstrItinClass itin32,
2873 string OpcodeStr, string Dt, SDNode MulOp,
2875 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2876 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2877 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2878 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2879 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2880 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2883 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2884 string Dt, SDNode MulOp, SDNode OpNode> {
2885 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2886 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2887 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2888 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2892 // Neon Long 3-argument intrinsics.
2894 // First with only element sizes of 16 and 32 bits:
2895 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2896 InstrItinClass itin16, InstrItinClass itin32,
2897 string OpcodeStr, string Dt, Intrinsic IntOp> {
2898 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2899 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2900 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2901 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2904 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2905 string OpcodeStr, string Dt, Intrinsic IntOp> {
2906 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2907 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2908 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2909 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2912 // ....then also with element size of 8 bits:
2913 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2914 InstrItinClass itin16, InstrItinClass itin32,
2915 string OpcodeStr, string Dt, Intrinsic IntOp>
2916 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2917 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2918 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2921 // ....with explicit extend (VABAL).
2922 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2923 InstrItinClass itin, string OpcodeStr, string Dt,
2924 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2925 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2926 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2927 IntOp, ExtOp, OpNode>;
2928 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2929 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2930 IntOp, ExtOp, OpNode>;
2931 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2932 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2933 IntOp, ExtOp, OpNode>;
2937 // Neon Pairwise long 2-register intrinsics,
2938 // element sizes of 8, 16 and 32 bits:
2939 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2940 bits<5> op11_7, bit op4,
2941 string OpcodeStr, string Dt, Intrinsic IntOp> {
2942 // 64-bit vector types.
2943 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2944 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2945 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2946 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2947 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2948 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2950 // 128-bit vector types.
2951 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2952 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2953 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2954 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2955 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2956 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2960 // Neon Pairwise long 2-register accumulate intrinsics,
2961 // element sizes of 8, 16 and 32 bits:
2962 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2963 bits<5> op11_7, bit op4,
2964 string OpcodeStr, string Dt, Intrinsic IntOp> {
2965 // 64-bit vector types.
2966 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2967 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2968 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2969 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2970 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2971 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2973 // 128-bit vector types.
2974 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2976 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2977 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2978 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2979 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2983 // Neon 2-register vector shift by immediate,
2984 // with f of either N2RegVShLFrm or N2RegVShRFrm
2985 // element sizes of 8, 16, 32 and 64 bits:
2986 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2987 InstrItinClass itin, string OpcodeStr, string Dt,
2988 SDNode OpNode, Format f> {
2989 // 64-bit vector types.
2990 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2991 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2992 let Inst{21-19} = 0b001; // imm6 = 001xxx
2994 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2995 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2996 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2998 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2999 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3000 let Inst{21} = 0b1; // imm6 = 1xxxxx
3002 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
3003 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3006 // 128-bit vector types.
3007 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3008 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3009 let Inst{21-19} = 0b001; // imm6 = 001xxx
3011 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3012 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3013 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3015 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3016 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3017 let Inst{21} = 0b1; // imm6 = 1xxxxx
3019 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
3020 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3024 // Neon Shift-Accumulate vector operations,
3025 // element sizes of 8, 16, 32 and 64 bits:
3026 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3027 string OpcodeStr, string Dt, SDNode ShOp> {
3028 // 64-bit vector types.
3029 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3030 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3031 let Inst{21-19} = 0b001; // imm6 = 001xxx
3033 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3034 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3035 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3037 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3038 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3039 let Inst{21} = 0b1; // imm6 = 1xxxxx
3041 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
3042 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3045 // 128-bit vector types.
3046 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3047 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3048 let Inst{21-19} = 0b001; // imm6 = 001xxx
3050 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3051 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3052 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3054 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3055 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3056 let Inst{21} = 0b1; // imm6 = 1xxxxx
3058 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
3059 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3064 // Neon Shift-Insert vector operations,
3065 // with f of either N2RegVShLFrm or N2RegVShRFrm
3066 // element sizes of 8, 16, 32 and 64 bits:
3067 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3068 string OpcodeStr, SDNode ShOp,
3070 // 64-bit vector types.
3071 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
3072 f, OpcodeStr, "8", v8i8, ShOp> {
3073 let Inst{21-19} = 0b001; // imm6 = 001xxx
3075 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
3076 f, OpcodeStr, "16", v4i16, ShOp> {
3077 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3079 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
3080 f, OpcodeStr, "32", v2i32, ShOp> {
3081 let Inst{21} = 0b1; // imm6 = 1xxxxx
3083 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
3084 f, OpcodeStr, "64", v1i64, ShOp>;
3087 // 128-bit vector types.
3088 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
3089 f, OpcodeStr, "8", v16i8, ShOp> {
3090 let Inst{21-19} = 0b001; // imm6 = 001xxx
3092 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
3093 f, OpcodeStr, "16", v8i16, ShOp> {
3094 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3096 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
3097 f, OpcodeStr, "32", v4i32, ShOp> {
3098 let Inst{21} = 0b1; // imm6 = 1xxxxx
3100 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
3101 f, OpcodeStr, "64", v2i64, ShOp>;
3105 // Neon Shift Long operations,
3106 // element sizes of 8, 16, 32 bits:
3107 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3108 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3109 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3110 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3111 let Inst{21-19} = 0b001; // imm6 = 001xxx
3113 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3114 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3115 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3117 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3118 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3119 let Inst{21} = 0b1; // imm6 = 1xxxxx
3123 // Neon Shift Narrow operations,
3124 // element sizes of 16, 32, 64 bits:
3125 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3126 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3128 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3129 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
3130 let Inst{21-19} = 0b001; // imm6 = 001xxx
3132 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3133 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
3134 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3136 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3137 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
3138 let Inst{21} = 0b1; // imm6 = 1xxxxx
3142 //===----------------------------------------------------------------------===//
3143 // Instruction Definitions.
3144 //===----------------------------------------------------------------------===//
3146 // Vector Add Operations.
3148 // VADD : Vector Add (integer and floating-point)
3149 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3151 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3152 v2f32, v2f32, fadd, 1>;
3153 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3154 v4f32, v4f32, fadd, 1>;
3155 // VADDL : Vector Add Long (Q = D + D)
3156 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3157 "vaddl", "s", add, sext, 1>;
3158 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3159 "vaddl", "u", add, zext, 1>;
3160 // VADDW : Vector Add Wide (Q = Q + D)
3161 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3162 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3163 // VHADD : Vector Halving Add
3164 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3165 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3166 "vhadd", "s", int_arm_neon_vhadds, 1>;
3167 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3168 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3169 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3170 // VRHADD : Vector Rounding Halving Add
3171 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3172 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3173 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3174 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3175 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3176 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3177 // VQADD : Vector Saturating Add
3178 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3179 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3180 "vqadd", "s", int_arm_neon_vqadds, 1>;
3181 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3182 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3183 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3184 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3185 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3186 int_arm_neon_vaddhn, 1>;
3187 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3188 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3189 int_arm_neon_vraddhn, 1>;
3191 // Vector Multiply Operations.
3193 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3194 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3195 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3196 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3197 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3198 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3199 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3200 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3201 v2f32, v2f32, fmul, 1>;
3202 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3203 v4f32, v4f32, fmul, 1>;
3204 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3205 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3206 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3209 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3210 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3211 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3212 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3213 (DSubReg_i16_reg imm:$lane))),
3214 (SubReg_i16_lane imm:$lane)))>;
3215 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3216 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3217 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3218 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3219 (DSubReg_i32_reg imm:$lane))),
3220 (SubReg_i32_lane imm:$lane)))>;
3221 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3222 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3223 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3224 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3225 (DSubReg_i32_reg imm:$lane))),
3226 (SubReg_i32_lane imm:$lane)))>;
3228 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3229 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3230 IIC_VMULi16Q, IIC_VMULi32Q,
3231 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3232 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3233 IIC_VMULi16Q, IIC_VMULi32Q,
3234 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3235 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3236 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3238 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3239 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3240 (DSubReg_i16_reg imm:$lane))),
3241 (SubReg_i16_lane imm:$lane)))>;
3242 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3243 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3245 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3246 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3247 (DSubReg_i32_reg imm:$lane))),
3248 (SubReg_i32_lane imm:$lane)))>;
3250 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3251 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3252 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3253 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3254 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3255 IIC_VMULi16Q, IIC_VMULi32Q,
3256 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3257 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3258 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3260 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3261 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3262 (DSubReg_i16_reg imm:$lane))),
3263 (SubReg_i16_lane imm:$lane)))>;
3264 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3265 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3267 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3268 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3269 (DSubReg_i32_reg imm:$lane))),
3270 (SubReg_i32_lane imm:$lane)))>;
3272 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3273 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3274 "vmull", "s", NEONvmulls, 1>;
3275 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3276 "vmull", "u", NEONvmullu, 1>;
3277 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3278 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3279 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3280 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3282 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3283 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3284 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3285 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3286 "vqdmull", "s", int_arm_neon_vqdmull>;
3288 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3290 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3291 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3292 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3293 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3294 v2f32, fmul_su, fadd_mlx>,
3295 Requires<[HasNEON, UseFPVMLx]>;
3296 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3297 v4f32, fmul_su, fadd_mlx>,
3298 Requires<[HasNEON, UseFPVMLx]>;
3299 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3300 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3301 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3302 v2f32, fmul_su, fadd_mlx>,
3303 Requires<[HasNEON, UseFPVMLx]>;
3304 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3305 v4f32, v2f32, fmul_su, fadd_mlx>,
3306 Requires<[HasNEON, UseFPVMLx]>;
3308 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3309 (mul (v8i16 QPR:$src2),
3310 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3311 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3312 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3313 (DSubReg_i16_reg imm:$lane))),
3314 (SubReg_i16_lane imm:$lane)))>;
3316 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3317 (mul (v4i32 QPR:$src2),
3318 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3319 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3320 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3321 (DSubReg_i32_reg imm:$lane))),
3322 (SubReg_i32_lane imm:$lane)))>;
3324 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3325 (fmul_su (v4f32 QPR:$src2),
3326 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3327 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3329 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3330 (DSubReg_i32_reg imm:$lane))),
3331 (SubReg_i32_lane imm:$lane)))>,
3332 Requires<[HasNEON, UseFPVMLx]>;
3334 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3335 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3336 "vmlal", "s", NEONvmulls, add>;
3337 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3338 "vmlal", "u", NEONvmullu, add>;
3340 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3341 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3343 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3344 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3345 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3346 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3348 // VMLS : Vector Multiply Subtract (integer and floating-point)
3349 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3350 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3351 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3352 v2f32, fmul_su, fsub_mlx>,
3353 Requires<[HasNEON, UseFPVMLx]>;
3354 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3355 v4f32, fmul_su, fsub_mlx>,
3356 Requires<[HasNEON, UseFPVMLx]>;
3357 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3358 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3359 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3360 v2f32, fmul_su, fsub_mlx>,
3361 Requires<[HasNEON, UseFPVMLx]>;
3362 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3363 v4f32, v2f32, fmul_su, fsub_mlx>,
3364 Requires<[HasNEON, UseFPVMLx]>;
3366 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3367 (mul (v8i16 QPR:$src2),
3368 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3369 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3370 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3371 (DSubReg_i16_reg imm:$lane))),
3372 (SubReg_i16_lane imm:$lane)))>;
3374 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3375 (mul (v4i32 QPR:$src2),
3376 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3377 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3378 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3379 (DSubReg_i32_reg imm:$lane))),
3380 (SubReg_i32_lane imm:$lane)))>;
3382 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3383 (fmul_su (v4f32 QPR:$src2),
3384 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3385 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3386 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3387 (DSubReg_i32_reg imm:$lane))),
3388 (SubReg_i32_lane imm:$lane)))>,
3389 Requires<[HasNEON, UseFPVMLx]>;
3391 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3392 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3393 "vmlsl", "s", NEONvmulls, sub>;
3394 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3395 "vmlsl", "u", NEONvmullu, sub>;
3397 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3398 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3400 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3401 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3402 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3403 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3405 // Vector Subtract Operations.
3407 // VSUB : Vector Subtract (integer and floating-point)
3408 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3409 "vsub", "i", sub, 0>;
3410 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3411 v2f32, v2f32, fsub, 0>;
3412 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3413 v4f32, v4f32, fsub, 0>;
3414 // VSUBL : Vector Subtract Long (Q = D - D)
3415 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3416 "vsubl", "s", sub, sext, 0>;
3417 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3418 "vsubl", "u", sub, zext, 0>;
3419 // VSUBW : Vector Subtract Wide (Q = Q - D)
3420 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3421 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3422 // VHSUB : Vector Halving Subtract
3423 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3424 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3425 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3426 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3427 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3428 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3429 // VQSUB : Vector Saturing Subtract
3430 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3431 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3432 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3433 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3434 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3435 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3436 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3437 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3438 int_arm_neon_vsubhn, 0>;
3439 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3440 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3441 int_arm_neon_vrsubhn, 0>;
3443 // Vector Comparisons.
3445 // VCEQ : Vector Compare Equal
3446 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3447 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3448 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3450 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3453 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3454 "$Vd, $Vm, #0", NEONvceqz>;
3456 // VCGE : Vector Compare Greater Than or Equal
3457 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3458 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3459 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3460 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3461 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3463 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3466 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3467 "$Vd, $Vm, #0", NEONvcgez>;
3468 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3469 "$Vd, $Vm, #0", NEONvclez>;
3471 // VCGT : Vector Compare Greater Than
3472 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3473 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3474 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3475 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3476 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3478 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3481 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3482 "$Vd, $Vm, #0", NEONvcgtz>;
3483 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3484 "$Vd, $Vm, #0", NEONvcltz>;
3486 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3487 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3488 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3489 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3490 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3491 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3492 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3493 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3494 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3495 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3496 // VTST : Vector Test Bits
3497 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3498 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3500 // Vector Bitwise Operations.
3502 def vnotd : PatFrag<(ops node:$in),
3503 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3504 def vnotq : PatFrag<(ops node:$in),
3505 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3508 // VAND : Vector Bitwise AND
3509 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3510 v2i32, v2i32, and, 1>;
3511 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3512 v4i32, v4i32, and, 1>;
3514 // VEOR : Vector Bitwise Exclusive OR
3515 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3516 v2i32, v2i32, xor, 1>;
3517 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3518 v4i32, v4i32, xor, 1>;
3520 // VORR : Vector Bitwise OR
3521 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3522 v2i32, v2i32, or, 1>;
3523 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3524 v4i32, v4i32, or, 1>;
3526 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3527 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3529 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3531 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3532 let Inst{9} = SIMM{9};
3535 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3536 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3538 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3540 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3541 let Inst{10-9} = SIMM{10-9};
3544 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3545 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3547 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3549 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3550 let Inst{9} = SIMM{9};
3553 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3554 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3556 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3558 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3559 let Inst{10-9} = SIMM{10-9};
3563 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3564 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3565 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3566 "vbic", "$Vd, $Vn, $Vm", "",
3567 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3568 (vnotd DPR:$Vm))))]>;
3569 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3570 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3571 "vbic", "$Vd, $Vn, $Vm", "",
3572 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3573 (vnotq QPR:$Vm))))]>;
3575 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3576 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3578 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3580 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3581 let Inst{9} = SIMM{9};
3584 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3585 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3587 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3589 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3590 let Inst{10-9} = SIMM{10-9};
3593 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3594 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3596 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3598 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3599 let Inst{9} = SIMM{9};
3602 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3603 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3605 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3607 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3608 let Inst{10-9} = SIMM{10-9};
3611 // VORN : Vector Bitwise OR NOT
3612 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3613 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3614 "vorn", "$Vd, $Vn, $Vm", "",
3615 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3616 (vnotd DPR:$Vm))))]>;
3617 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3618 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3619 "vorn", "$Vd, $Vn, $Vm", "",
3620 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3621 (vnotq QPR:$Vm))))]>;
3623 // VMVN : Vector Bitwise NOT (Immediate)
3625 let isReMaterializable = 1 in {
3627 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3628 (ins nModImm:$SIMM), IIC_VMOVImm,
3629 "vmvn", "i16", "$Vd, $SIMM", "",
3630 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3631 let Inst{9} = SIMM{9};
3634 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3635 (ins nModImm:$SIMM), IIC_VMOVImm,
3636 "vmvn", "i16", "$Vd, $SIMM", "",
3637 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3638 let Inst{9} = SIMM{9};
3641 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3642 (ins nModImm:$SIMM), IIC_VMOVImm,
3643 "vmvn", "i32", "$Vd, $SIMM", "",
3644 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3645 let Inst{11-8} = SIMM{11-8};
3648 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3649 (ins nModImm:$SIMM), IIC_VMOVImm,
3650 "vmvn", "i32", "$Vd, $SIMM", "",
3651 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3652 let Inst{11-8} = SIMM{11-8};
3656 // VMVN : Vector Bitwise NOT
3657 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3658 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3659 "vmvn", "$Vd, $Vm", "",
3660 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3661 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3662 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3663 "vmvn", "$Vd, $Vm", "",
3664 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3665 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3666 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3668 // VBSL : Vector Bitwise Select
3669 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3670 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3671 N3RegFrm, IIC_VCNTiD,
3672 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3674 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3675 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3676 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3677 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3678 N3RegFrm, IIC_VCNTiQ,
3679 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3681 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3682 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3684 // VBIF : Vector Bitwise Insert if False
3685 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3686 // FIXME: This instruction's encoding MAY NOT BE correct.
3687 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3688 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3689 N3RegFrm, IIC_VBINiD,
3690 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3691 [/* For disassembly only; pattern left blank */]>;
3692 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3693 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3694 N3RegFrm, IIC_VBINiQ,
3695 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3696 [/* For disassembly only; pattern left blank */]>;
3698 // VBIT : Vector Bitwise Insert if True
3699 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3700 // FIXME: This instruction's encoding MAY NOT BE correct.
3701 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3702 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3703 N3RegFrm, IIC_VBINiD,
3704 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3705 [/* For disassembly only; pattern left blank */]>;
3706 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3707 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3708 N3RegFrm, IIC_VBINiQ,
3709 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3710 [/* For disassembly only; pattern left blank */]>;
3712 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3713 // for equivalent operations with different register constraints; it just
3716 // Vector Absolute Differences.
3718 // VABD : Vector Absolute Difference
3719 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3720 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3721 "vabd", "s", int_arm_neon_vabds, 1>;
3722 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3723 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3724 "vabd", "u", int_arm_neon_vabdu, 1>;
3725 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3726 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3727 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3728 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3730 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3731 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3732 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3733 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3734 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3736 // VABA : Vector Absolute Difference and Accumulate
3737 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3738 "vaba", "s", int_arm_neon_vabds, add>;
3739 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3740 "vaba", "u", int_arm_neon_vabdu, add>;
3742 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3743 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3744 "vabal", "s", int_arm_neon_vabds, zext, add>;
3745 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3746 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3748 // Vector Maximum and Minimum.
3750 // VMAX : Vector Maximum
3751 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3752 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3753 "vmax", "s", int_arm_neon_vmaxs, 1>;
3754 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3755 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3756 "vmax", "u", int_arm_neon_vmaxu, 1>;
3757 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3759 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3760 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3762 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3764 // VMIN : Vector Minimum
3765 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3766 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3767 "vmin", "s", int_arm_neon_vmins, 1>;
3768 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3769 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3770 "vmin", "u", int_arm_neon_vminu, 1>;
3771 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3773 v2f32, v2f32, int_arm_neon_vmins, 1>;
3774 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3776 v4f32, v4f32, int_arm_neon_vmins, 1>;
3778 // Vector Pairwise Operations.
3780 // VPADD : Vector Pairwise Add
3781 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3783 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3784 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3786 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3787 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3789 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3790 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3791 IIC_VPBIND, "vpadd", "f32",
3792 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3794 // VPADDL : Vector Pairwise Add Long
3795 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3796 int_arm_neon_vpaddls>;
3797 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3798 int_arm_neon_vpaddlu>;
3800 // VPADAL : Vector Pairwise Add and Accumulate Long
3801 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3802 int_arm_neon_vpadals>;
3803 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3804 int_arm_neon_vpadalu>;
3806 // VPMAX : Vector Pairwise Maximum
3807 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3808 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3809 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3810 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3811 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3812 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3813 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3814 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3815 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3816 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3817 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3818 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3819 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3820 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3822 // VPMIN : Vector Pairwise Minimum
3823 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3824 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3825 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3826 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3827 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3828 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3829 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3830 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3831 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3832 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3833 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3834 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3835 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3836 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3838 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3840 // VRECPE : Vector Reciprocal Estimate
3841 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3842 IIC_VUNAD, "vrecpe", "u32",
3843 v2i32, v2i32, int_arm_neon_vrecpe>;
3844 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3845 IIC_VUNAQ, "vrecpe", "u32",
3846 v4i32, v4i32, int_arm_neon_vrecpe>;
3847 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3848 IIC_VUNAD, "vrecpe", "f32",
3849 v2f32, v2f32, int_arm_neon_vrecpe>;
3850 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3851 IIC_VUNAQ, "vrecpe", "f32",
3852 v4f32, v4f32, int_arm_neon_vrecpe>;
3854 // VRECPS : Vector Reciprocal Step
3855 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3856 IIC_VRECSD, "vrecps", "f32",
3857 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3858 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3859 IIC_VRECSQ, "vrecps", "f32",
3860 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3862 // VRSQRTE : Vector Reciprocal Square Root Estimate
3863 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3864 IIC_VUNAD, "vrsqrte", "u32",
3865 v2i32, v2i32, int_arm_neon_vrsqrte>;
3866 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3867 IIC_VUNAQ, "vrsqrte", "u32",
3868 v4i32, v4i32, int_arm_neon_vrsqrte>;
3869 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3870 IIC_VUNAD, "vrsqrte", "f32",
3871 v2f32, v2f32, int_arm_neon_vrsqrte>;
3872 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3873 IIC_VUNAQ, "vrsqrte", "f32",
3874 v4f32, v4f32, int_arm_neon_vrsqrte>;
3876 // VRSQRTS : Vector Reciprocal Square Root Step
3877 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3878 IIC_VRECSD, "vrsqrts", "f32",
3879 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3880 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3881 IIC_VRECSQ, "vrsqrts", "f32",
3882 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3886 // VSHL : Vector Shift
3887 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3888 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3889 "vshl", "s", int_arm_neon_vshifts>;
3890 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3891 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3892 "vshl", "u", int_arm_neon_vshiftu>;
3893 // VSHL : Vector Shift Left (Immediate)
3894 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3896 // VSHR : Vector Shift Right (Immediate)
3897 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3899 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3902 // VSHLL : Vector Shift Left Long
3903 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3904 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3906 // VSHLL : Vector Shift Left Long (with maximum shift count)
3907 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3908 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3909 ValueType OpTy, SDNode OpNode>
3910 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3911 ResTy, OpTy, OpNode> {
3912 let Inst{21-16} = op21_16;
3914 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3915 v8i16, v8i8, NEONvshlli>;
3916 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3917 v4i32, v4i16, NEONvshlli>;
3918 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3919 v2i64, v2i32, NEONvshlli>;
3921 // VSHRN : Vector Shift Right and Narrow
3922 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3925 // VRSHL : Vector Rounding Shift
3926 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3927 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3928 "vrshl", "s", int_arm_neon_vrshifts>;
3929 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3930 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3931 "vrshl", "u", int_arm_neon_vrshiftu>;
3932 // VRSHR : Vector Rounding Shift Right
3933 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3935 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3938 // VRSHRN : Vector Rounding Shift Right and Narrow
3939 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3942 // VQSHL : Vector Saturating Shift
3943 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3944 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3945 "vqshl", "s", int_arm_neon_vqshifts>;
3946 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3947 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3948 "vqshl", "u", int_arm_neon_vqshiftu>;
3949 // VQSHL : Vector Saturating Shift Left (Immediate)
3950 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3952 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3954 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3955 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3958 // VQSHRN : Vector Saturating Shift Right and Narrow
3959 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3961 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3964 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3965 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3968 // VQRSHL : Vector Saturating Rounding Shift
3969 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3970 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3971 "vqrshl", "s", int_arm_neon_vqrshifts>;
3972 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3973 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3974 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3976 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3977 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3979 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3982 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3983 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3986 // VSRA : Vector Shift Right and Accumulate
3987 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3988 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3989 // VRSRA : Vector Rounding Shift Right and Accumulate
3990 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3991 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3993 // VSLI : Vector Shift Left and Insert
3994 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3995 // VSRI : Vector Shift Right and Insert
3996 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3998 // Vector Absolute and Saturating Absolute.
4000 // VABS : Vector Absolute Value
4001 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4002 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4004 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4005 IIC_VUNAD, "vabs", "f32",
4006 v2f32, v2f32, int_arm_neon_vabs>;
4007 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4008 IIC_VUNAQ, "vabs", "f32",
4009 v4f32, v4f32, int_arm_neon_vabs>;
4011 // VQABS : Vector Saturating Absolute Value
4012 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4013 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4014 int_arm_neon_vqabs>;
4018 def vnegd : PatFrag<(ops node:$in),
4019 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4020 def vnegq : PatFrag<(ops node:$in),
4021 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4023 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4024 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4025 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4026 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4027 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4028 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4029 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4030 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4032 // VNEG : Vector Negate (integer)
4033 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4034 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4035 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4036 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4037 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4038 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4040 // VNEG : Vector Negate (floating-point)
4041 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4042 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4043 "vneg", "f32", "$Vd, $Vm", "",
4044 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4045 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4046 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4047 "vneg", "f32", "$Vd, $Vm", "",
4048 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4050 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4051 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4052 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4053 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4054 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4055 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4057 // VQNEG : Vector Saturating Negate
4058 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4059 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4060 int_arm_neon_vqneg>;
4062 // Vector Bit Counting Operations.
4064 // VCLS : Vector Count Leading Sign Bits
4065 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4066 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4068 // VCLZ : Vector Count Leading Zeros
4069 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4070 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4072 // VCNT : Vector Count One Bits
4073 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4074 IIC_VCNTiD, "vcnt", "8",
4075 v8i8, v8i8, int_arm_neon_vcnt>;
4076 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4077 IIC_VCNTiQ, "vcnt", "8",
4078 v16i8, v16i8, int_arm_neon_vcnt>;
4080 // Vector Swap -- for disassembly only.
4081 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4082 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4083 "vswp", "$Vd, $Vm", "", []>;
4084 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4085 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4086 "vswp", "$Vd, $Vm", "", []>;
4088 // Vector Move Operations.
4090 // VMOV : Vector Move (Register)
4092 let neverHasSideEffects = 1 in {
4093 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4094 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4095 let Vn{4-0} = Vm{4-0};
4097 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4098 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4099 let Vn{4-0} = Vm{4-0};
4102 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4103 // be expanded after register allocation is completed.
4104 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4107 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4109 } // neverHasSideEffects
4111 // VMOV : Vector Move (Immediate)
4113 let isReMaterializable = 1 in {
4114 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4115 (ins nModImm:$SIMM), IIC_VMOVImm,
4116 "vmov", "i8", "$Vd, $SIMM", "",
4117 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4118 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4119 (ins nModImm:$SIMM), IIC_VMOVImm,
4120 "vmov", "i8", "$Vd, $SIMM", "",
4121 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4123 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4124 (ins nModImm:$SIMM), IIC_VMOVImm,
4125 "vmov", "i16", "$Vd, $SIMM", "",
4126 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4127 let Inst{9} = SIMM{9};
4130 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4131 (ins nModImm:$SIMM), IIC_VMOVImm,
4132 "vmov", "i16", "$Vd, $SIMM", "",
4133 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4134 let Inst{9} = SIMM{9};
4137 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4138 (ins nModImm:$SIMM), IIC_VMOVImm,
4139 "vmov", "i32", "$Vd, $SIMM", "",
4140 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4141 let Inst{11-8} = SIMM{11-8};
4144 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4145 (ins nModImm:$SIMM), IIC_VMOVImm,
4146 "vmov", "i32", "$Vd, $SIMM", "",
4147 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4148 let Inst{11-8} = SIMM{11-8};
4151 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4152 (ins nModImm:$SIMM), IIC_VMOVImm,
4153 "vmov", "i64", "$Vd, $SIMM", "",
4154 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4155 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4156 (ins nModImm:$SIMM), IIC_VMOVImm,
4157 "vmov", "i64", "$Vd, $SIMM", "",
4158 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4159 } // isReMaterializable
4161 // VMOV : Vector Get Lane (move scalar to ARM core register)
4163 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4164 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4165 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4166 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4168 let Inst{21} = lane{2};
4169 let Inst{6-5} = lane{1-0};
4171 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4172 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4173 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4174 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4176 let Inst{21} = lane{1};
4177 let Inst{6} = lane{0};
4179 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4180 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4181 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4182 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4184 let Inst{21} = lane{2};
4185 let Inst{6-5} = lane{1-0};
4187 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4188 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4189 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4190 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4192 let Inst{21} = lane{1};
4193 let Inst{6} = lane{0};
4195 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4196 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4197 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4198 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4200 let Inst{21} = lane{0};
4202 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4203 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4204 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4205 (DSubReg_i8_reg imm:$lane))),
4206 (SubReg_i8_lane imm:$lane))>;
4207 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4208 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4209 (DSubReg_i16_reg imm:$lane))),
4210 (SubReg_i16_lane imm:$lane))>;
4211 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4212 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4213 (DSubReg_i8_reg imm:$lane))),
4214 (SubReg_i8_lane imm:$lane))>;
4215 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4216 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4217 (DSubReg_i16_reg imm:$lane))),
4218 (SubReg_i16_lane imm:$lane))>;
4219 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4220 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4221 (DSubReg_i32_reg imm:$lane))),
4222 (SubReg_i32_lane imm:$lane))>;
4223 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4224 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4225 (SSubReg_f32_reg imm:$src2))>;
4226 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4227 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4228 (SSubReg_f32_reg imm:$src2))>;
4229 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4230 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4231 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4232 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4235 // VMOV : Vector Set Lane (move ARM core register to scalar)
4237 let Constraints = "$src1 = $V" in {
4238 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4239 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4240 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4241 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4242 GPR:$R, imm:$lane))]> {
4243 let Inst{21} = lane{2};
4244 let Inst{6-5} = lane{1-0};
4246 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4247 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4248 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4249 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4250 GPR:$R, imm:$lane))]> {
4251 let Inst{21} = lane{1};
4252 let Inst{6} = lane{0};
4254 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4255 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4256 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4257 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4258 GPR:$R, imm:$lane))]> {
4259 let Inst{21} = lane{0};
4262 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4263 (v16i8 (INSERT_SUBREG QPR:$src1,
4264 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4265 (DSubReg_i8_reg imm:$lane))),
4266 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4267 (DSubReg_i8_reg imm:$lane)))>;
4268 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4269 (v8i16 (INSERT_SUBREG QPR:$src1,
4270 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4271 (DSubReg_i16_reg imm:$lane))),
4272 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4273 (DSubReg_i16_reg imm:$lane)))>;
4274 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4275 (v4i32 (INSERT_SUBREG QPR:$src1,
4276 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4277 (DSubReg_i32_reg imm:$lane))),
4278 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4279 (DSubReg_i32_reg imm:$lane)))>;
4281 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4282 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4283 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4284 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4285 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4286 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4288 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4289 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4290 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4291 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4293 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4294 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4295 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4296 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4297 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4298 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4300 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4301 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4302 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4303 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4304 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4305 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4307 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4308 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4309 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4311 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4312 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4313 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4315 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4316 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4317 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4320 // VDUP : Vector Duplicate (from ARM core register to all elements)
4322 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4323 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4324 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4325 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4326 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4327 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4328 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4329 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4331 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4332 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4333 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4334 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4335 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4336 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4338 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$V), (ins GPR:$R),
4339 IIC_VMOVIS, "vdup", "32", "$V, $R",
4340 [(set DPR:$V, (v2f32 (NEONvdup
4341 (f32 (bitconvert GPR:$R)))))]>;
4342 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$V), (ins GPR:$R),
4343 IIC_VMOVIS, "vdup", "32", "$V, $R",
4344 [(set QPR:$V, (v4f32 (NEONvdup
4345 (f32 (bitconvert GPR:$R)))))]>;
4347 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4349 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4351 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4352 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4353 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4355 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4356 ValueType ResTy, ValueType OpTy>
4357 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4358 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4359 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4362 // Inst{19-16} is partially specified depending on the element size.
4364 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4365 let Inst{19-17} = lane{2-0};
4367 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4368 let Inst{19-18} = lane{1-0};
4370 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4371 let Inst{19} = lane{0};
4373 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4374 let Inst{19} = lane{0};
4376 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4377 let Inst{19-17} = lane{2-0};
4379 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4380 let Inst{19-18} = lane{1-0};
4382 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4383 let Inst{19} = lane{0};
4385 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4386 let Inst{19} = lane{0};
4389 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4390 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4391 (DSubReg_i8_reg imm:$lane))),
4392 (SubReg_i8_lane imm:$lane)))>;
4393 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4394 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4395 (DSubReg_i16_reg imm:$lane))),
4396 (SubReg_i16_lane imm:$lane)))>;
4397 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4398 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4399 (DSubReg_i32_reg imm:$lane))),
4400 (SubReg_i32_lane imm:$lane)))>;
4401 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4402 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4403 (DSubReg_i32_reg imm:$lane))),
4404 (SubReg_i32_lane imm:$lane)))>;
4406 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4407 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4408 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4409 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4411 // VMOVN : Vector Narrowing Move
4412 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4413 "vmovn", "i", trunc>;
4414 // VQMOVN : Vector Saturating Narrowing Move
4415 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4416 "vqmovn", "s", int_arm_neon_vqmovns>;
4417 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4418 "vqmovn", "u", int_arm_neon_vqmovnu>;
4419 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4420 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4421 // VMOVL : Vector Lengthening Move
4422 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4423 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4425 // Vector Conversions.
4427 // VCVT : Vector Convert Between Floating-Point and Integers
4428 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4429 v2i32, v2f32, fp_to_sint>;
4430 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4431 v2i32, v2f32, fp_to_uint>;
4432 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4433 v2f32, v2i32, sint_to_fp>;
4434 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4435 v2f32, v2i32, uint_to_fp>;
4437 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4438 v4i32, v4f32, fp_to_sint>;
4439 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4440 v4i32, v4f32, fp_to_uint>;
4441 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4442 v4f32, v4i32, sint_to_fp>;
4443 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4444 v4f32, v4i32, uint_to_fp>;
4446 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4447 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4448 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4449 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4450 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4451 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4452 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4453 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4454 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4456 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4457 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4458 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4459 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4460 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4461 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4462 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4463 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4465 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4466 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4467 IIC_VUNAQ, "vcvt", "f16.f32",
4468 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4469 Requires<[HasNEON, HasFP16]>;
4470 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4471 IIC_VUNAQ, "vcvt", "f32.f16",
4472 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4473 Requires<[HasNEON, HasFP16]>;
4477 // VREV64 : Vector Reverse elements within 64-bit doublewords
4479 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4480 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4481 (ins DPR:$Vm), IIC_VMOVD,
4482 OpcodeStr, Dt, "$Vd, $Vm", "",
4483 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4484 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4485 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4486 (ins QPR:$Vm), IIC_VMOVQ,
4487 OpcodeStr, Dt, "$Vd, $Vm", "",
4488 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4490 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4491 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4492 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4493 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4495 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4496 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4497 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4498 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4500 // VREV32 : Vector Reverse elements within 32-bit words
4502 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4503 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4504 (ins DPR:$Vm), IIC_VMOVD,
4505 OpcodeStr, Dt, "$Vd, $Vm", "",
4506 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4507 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4508 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4509 (ins QPR:$Vm), IIC_VMOVQ,
4510 OpcodeStr, Dt, "$Vd, $Vm", "",
4511 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4513 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4514 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4516 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4517 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4519 // VREV16 : Vector Reverse elements within 16-bit halfwords
4521 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4522 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4523 (ins DPR:$Vm), IIC_VMOVD,
4524 OpcodeStr, Dt, "$Vd, $Vm", "",
4525 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4526 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4527 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4528 (ins QPR:$Vm), IIC_VMOVQ,
4529 OpcodeStr, Dt, "$Vd, $Vm", "",
4530 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4532 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4533 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4535 // Other Vector Shuffles.
4537 // Aligned extractions: really just dropping registers
4539 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4540 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4541 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4543 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4545 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4547 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4549 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4551 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4554 // VEXT : Vector Extract
4556 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4557 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4558 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4559 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4560 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4561 (Ty DPR:$Vm), imm:$index)))]> {
4563 let Inst{11-8} = index{3-0};
4566 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4567 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4568 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4569 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4570 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4571 (Ty QPR:$Vm), imm:$index)))]> {
4573 let Inst{11-8} = index{3-0};
4576 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4577 let Inst{11-8} = index{3-0};
4579 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4580 let Inst{11-9} = index{2-0};
4583 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4584 let Inst{11-10} = index{1-0};
4585 let Inst{9-8} = 0b00;
4587 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4588 let Inst{11} = index{0};
4589 let Inst{10-8} = 0b000;
4592 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4593 let Inst{11-8} = index{3-0};
4595 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4596 let Inst{11-9} = index{2-0};
4599 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4600 let Inst{11-10} = index{1-0};
4601 let Inst{9-8} = 0b00;
4603 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4604 let Inst{11} = index{0};
4605 let Inst{10-8} = 0b000;
4608 // VTRN : Vector Transpose
4610 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4611 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4612 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4614 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4615 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4616 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4618 // VUZP : Vector Unzip (Deinterleave)
4620 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4621 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4622 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4624 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4625 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4626 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4628 // VZIP : Vector Zip (Interleave)
4630 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4631 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4632 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4634 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4635 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4636 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4638 // Vector Table Lookup and Table Extension.
4640 // VTBL : Vector Table Lookup
4642 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4643 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4644 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4645 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4646 let hasExtraSrcRegAllocReq = 1 in {
4648 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4649 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4650 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4652 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4653 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4654 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4656 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4657 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4659 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4660 } // hasExtraSrcRegAllocReq = 1
4663 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4665 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4667 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4669 // VTBX : Vector Table Extension
4671 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4672 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4673 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4674 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4675 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4676 let hasExtraSrcRegAllocReq = 1 in {
4678 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4679 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4680 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4682 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4683 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4684 NVTBLFrm, IIC_VTBX3,
4685 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4688 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4689 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4690 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4692 } // hasExtraSrcRegAllocReq = 1
4695 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4696 IIC_VTBX2, "$orig = $dst", []>;
4698 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4699 IIC_VTBX3, "$orig = $dst", []>;
4701 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4702 IIC_VTBX4, "$orig = $dst", []>;
4704 //===----------------------------------------------------------------------===//
4705 // NEON instructions for single-precision FP math
4706 //===----------------------------------------------------------------------===//
4708 class N2VSPat<SDNode OpNode, NeonI Inst>
4709 : NEONFPPat<(f32 (OpNode SPR:$a)),
4711 (v2f32 (COPY_TO_REGCLASS (Inst
4713 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4714 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4716 class N3VSPat<SDNode OpNode, NeonI Inst>
4717 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4719 (v2f32 (COPY_TO_REGCLASS (Inst
4721 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4724 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4725 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4727 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4728 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4730 (v2f32 (COPY_TO_REGCLASS (Inst
4732 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4735 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4738 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4739 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4741 def : N3VSPat<fadd, VADDfd>;
4742 def : N3VSPat<fsub, VSUBfd>;
4743 def : N3VSPat<fmul, VMULfd>;
4744 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4745 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4746 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4747 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4748 def : N2VSPat<fabs, VABSfd>;
4749 def : N2VSPat<fneg, VNEGfd>;
4750 def : N3VSPat<NEONfmax, VMAXfd>;
4751 def : N3VSPat<NEONfmin, VMINfd>;
4752 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4753 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4754 def : N2VSPat<arm_sitof, VCVTs2fd>;
4755 def : N2VSPat<arm_uitof, VCVTu2fd>;
4757 //===----------------------------------------------------------------------===//
4758 // Non-Instruction Patterns
4759 //===----------------------------------------------------------------------===//
4762 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4763 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4764 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4765 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4766 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4767 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4768 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4769 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4770 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4771 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4772 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4773 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4774 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4775 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4776 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4777 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4778 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4779 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4780 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4781 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4782 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4783 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4784 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4785 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4786 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4787 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4788 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4789 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4790 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4791 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4793 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4794 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4795 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4796 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4797 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4798 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4799 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4800 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4801 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4802 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4803 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4804 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4805 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4806 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4807 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4808 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4809 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4810 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4811 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4812 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4813 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4814 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4815 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4816 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4817 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4818 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4819 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4820 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4821 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4822 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;