1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
98 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
99 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
101 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 2>]>;
103 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
104 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
106 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
107 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
108 unsigned EltBits = 0;
109 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
110 return (EltBits == 32 && EltVal == 0);
113 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
114 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
115 unsigned EltBits = 0;
116 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
117 return (EltBits == 8 && EltVal == 0xff);
120 //===----------------------------------------------------------------------===//
121 // NEON operand definitions
122 //===----------------------------------------------------------------------===//
124 def nModImm : Operand<i32> {
125 let PrintMethod = "printNEONModImmOperand";
128 //===----------------------------------------------------------------------===//
129 // NEON load / store instructions
130 //===----------------------------------------------------------------------===//
132 // Use vldmia to load a Q register as a D register pair.
133 // This is equivalent to VLDMD except that it has a Q register operand
134 // instead of a pair of D registers.
136 : AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
137 IndexModeNone, IIC_fpLoadm,
138 "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
139 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
141 let mayLoad = 1, neverHasSideEffects = 1 in {
142 // Use vld1 to load a Q register as a D register pair.
143 // This alternative to VLDMQ allows an alignment to be specified.
144 // This is equivalent to VLD1q64 except that it has a Q register operand.
146 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
147 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
148 } // mayLoad = 1, neverHasSideEffects = 1
150 // Use vstmia to store a Q register as a D register pair.
151 // This is equivalent to VSTMD except that it has a Q register operand
152 // instead of a pair of D registers.
154 : AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
155 IndexModeNone, IIC_fpStorem,
156 "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
157 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
159 let mayStore = 1, neverHasSideEffects = 1 in {
160 // Use vst1 to store a Q register as a D register pair.
161 // This alternative to VSTMQ allows an alignment to be specified.
162 // This is equivalent to VST1q64 except that it has a Q register operand.
164 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
165 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
166 } // mayStore = 1, neverHasSideEffects = 1
168 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
170 // Classes for VLD* pseudo-instructions with multi-register operands.
171 // These are expanded to real instructions after register allocation.
173 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD2, "">;
175 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
176 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
179 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VLD4, "">;
181 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
182 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
184 class VLDQQQQWBPseudo
185 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
186 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VLD4,
187 "$addr.addr = $wb, $src = $dst">;
189 // VLD1 : Vector Load (multiple single elements)
190 class VLD1D<bits<4> op7_4, string Dt>
191 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
192 (ins addrmode6:$addr), IIC_VLD1,
193 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
196 (ins addrmode6:$addr), IIC_VLD1,
197 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
199 def VLD1d8 : VLD1D<0b0000, "8">;
200 def VLD1d16 : VLD1D<0b0100, "16">;
201 def VLD1d32 : VLD1D<0b1000, "32">;
202 def VLD1d64 : VLD1D<0b1100, "64">;
204 def VLD1q8 : VLD1Q<0b0000, "8">;
205 def VLD1q16 : VLD1Q<0b0100, "16">;
206 def VLD1q32 : VLD1Q<0b1000, "32">;
207 def VLD1q64 : VLD1Q<0b1100, "64">;
209 def VLD1q8Pseudo : VLDQPseudo;
210 def VLD1q16Pseudo : VLDQPseudo;
211 def VLD1q32Pseudo : VLDQPseudo;
212 def VLD1q64Pseudo : VLDQPseudo;
214 // ...with address register writeback:
215 class VLD1DWB<bits<4> op7_4, string Dt>
216 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
217 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
218 "vld1", Dt, "\\{$dst\\}, $addr$offset",
219 "$addr.addr = $wb", []>;
220 class VLD1QWB<bits<4> op7_4, string Dt>
221 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
222 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
223 "vld1", Dt, "${dst:dregpair}, $addr$offset",
224 "$addr.addr = $wb", []>;
226 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
227 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
228 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
229 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
231 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
232 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
233 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
234 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
236 def VLD1q8Pseudo_UPD : VLDQWBPseudo;
237 def VLD1q16Pseudo_UPD : VLDQWBPseudo;
238 def VLD1q32Pseudo_UPD : VLDQWBPseudo;
239 def VLD1q64Pseudo_UPD : VLDQWBPseudo;
241 // ...with 3 registers (some of these are only for the disassembler):
242 class VLD1D3<bits<4> op7_4, string Dt>
243 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
244 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
245 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
246 class VLD1D3WB<bits<4> op7_4, string Dt>
247 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
248 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
249 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
251 def VLD1d8T : VLD1D3<0b0000, "8">;
252 def VLD1d16T : VLD1D3<0b0100, "16">;
253 def VLD1d32T : VLD1D3<0b1000, "32">;
254 def VLD1d64T : VLD1D3<0b1100, "64">;
256 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
257 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
258 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
259 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
261 def VLD1d64TPseudo : VLDQQPseudo;
262 def VLD1d64TPseudo_UPD : VLDQQWBPseudo;
264 // ...with 4 registers (some of these are only for the disassembler):
265 class VLD1D4<bits<4> op7_4, string Dt>
266 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
267 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
268 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
269 class VLD1D4WB<bits<4> op7_4, string Dt>
270 : NLdSt<0,0b10,0b0010,op7_4,
271 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
272 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
273 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
276 def VLD1d8Q : VLD1D4<0b0000, "8">;
277 def VLD1d16Q : VLD1D4<0b0100, "16">;
278 def VLD1d32Q : VLD1D4<0b1000, "32">;
279 def VLD1d64Q : VLD1D4<0b1100, "64">;
281 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
282 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
283 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
284 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
286 def VLD1d64QPseudo : VLDQQPseudo;
287 def VLD1d64QPseudo_UPD : VLDQQWBPseudo;
289 // VLD2 : Vector Load (multiple 2-element structures)
290 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
291 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
292 (ins addrmode6:$addr), IIC_VLD2,
293 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
294 class VLD2Q<bits<4> op7_4, string Dt>
295 : NLdSt<0, 0b10, 0b0011, op7_4,
296 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
297 (ins addrmode6:$addr), IIC_VLD2,
298 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
300 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
301 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
302 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
304 def VLD2q8 : VLD2Q<0b0000, "8">;
305 def VLD2q16 : VLD2Q<0b0100, "16">;
306 def VLD2q32 : VLD2Q<0b1000, "32">;
308 def VLD2d8Pseudo : VLDQPseudo;
309 def VLD2d16Pseudo : VLDQPseudo;
310 def VLD2d32Pseudo : VLDQPseudo;
312 def VLD2q8Pseudo : VLDQQPseudo;
313 def VLD2q16Pseudo : VLDQQPseudo;
314 def VLD2q32Pseudo : VLDQQPseudo;
316 // ...with address register writeback:
317 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
318 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
319 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
320 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
321 "$addr.addr = $wb", []>;
322 class VLD2QWB<bits<4> op7_4, string Dt>
323 : NLdSt<0, 0b10, 0b0011, op7_4,
324 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
325 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
326 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
327 "$addr.addr = $wb", []>;
329 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
330 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
331 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
333 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
334 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
335 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
337 def VLD2d8Pseudo_UPD : VLDQWBPseudo;
338 def VLD2d16Pseudo_UPD : VLDQWBPseudo;
339 def VLD2d32Pseudo_UPD : VLDQWBPseudo;
341 def VLD2q8Pseudo_UPD : VLDQQWBPseudo;
342 def VLD2q16Pseudo_UPD : VLDQQWBPseudo;
343 def VLD2q32Pseudo_UPD : VLDQQWBPseudo;
345 // ...with double-spaced registers (for disassembly only):
346 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
347 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
348 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
349 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
350 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
351 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
353 // VLD3 : Vector Load (multiple 3-element structures)
354 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
355 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
356 (ins addrmode6:$addr), IIC_VLD3,
357 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
359 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
360 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
361 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
363 def VLD3d8Pseudo : VLDQQPseudo;
364 def VLD3d16Pseudo : VLDQQPseudo;
365 def VLD3d32Pseudo : VLDQQPseudo;
367 // ...with address register writeback:
368 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
369 : NLdSt<0, 0b10, op11_8, op7_4,
370 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
371 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
372 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
373 "$addr.addr = $wb", []>;
375 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
376 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
377 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
379 def VLD3d8Pseudo_UPD : VLDQQWBPseudo;
380 def VLD3d16Pseudo_UPD : VLDQQWBPseudo;
381 def VLD3d32Pseudo_UPD : VLDQQWBPseudo;
383 // ...with double-spaced registers (non-updating versions for disassembly only):
384 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
385 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
386 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
387 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
388 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
389 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
391 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo;
392 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo;
393 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo;
395 // ...alternate versions to be allocated odd register numbers:
396 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo;
397 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo;
398 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo;
400 // VLD4 : Vector Load (multiple 4-element structures)
401 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
402 : NLdSt<0, 0b10, op11_8, op7_4,
403 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
404 (ins addrmode6:$addr), IIC_VLD4,
405 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
407 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
408 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
409 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
411 def VLD4d8Pseudo : VLDQQPseudo;
412 def VLD4d16Pseudo : VLDQQPseudo;
413 def VLD4d32Pseudo : VLDQQPseudo;
415 // ...with address register writeback:
416 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
417 : NLdSt<0, 0b10, op11_8, op7_4,
418 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
419 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
420 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
421 "$addr.addr = $wb", []>;
423 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
424 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
425 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
427 def VLD4d8Pseudo_UPD : VLDQQWBPseudo;
428 def VLD4d16Pseudo_UPD : VLDQQWBPseudo;
429 def VLD4d32Pseudo_UPD : VLDQQWBPseudo;
431 // ...with double-spaced registers (non-updating versions for disassembly only):
432 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
433 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
434 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
435 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
436 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
437 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
439 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo;
440 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo;
441 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo;
443 // ...alternate versions to be allocated odd register numbers:
444 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo;
445 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo;
446 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo;
448 // VLD1LN : Vector Load (single element to one lane)
449 // FIXME: Not yet implemented.
451 // VLD2LN : Vector Load (single 2-element structure to one lane)
452 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
453 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
454 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
455 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
456 "$src1 = $dst1, $src2 = $dst2", []>;
458 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
459 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
460 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
462 // ...with double-spaced registers:
463 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
464 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
466 // ...alternate versions to be allocated odd register numbers:
467 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
468 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
470 // ...with address register writeback:
471 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
472 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
473 (ins addrmode6:$addr, am6offset:$offset,
474 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
475 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
476 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
478 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
479 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
480 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
482 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
483 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
485 // VLD3LN : Vector Load (single 3-element structure to one lane)
486 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
487 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
488 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
489 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
490 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
491 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
493 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
494 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
495 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
497 // ...with double-spaced registers:
498 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
499 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
501 // ...alternate versions to be allocated odd register numbers:
502 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
503 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
505 // ...with address register writeback:
506 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
507 : NLdSt<1, 0b10, op11_8, op7_4,
508 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
509 (ins addrmode6:$addr, am6offset:$offset,
510 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
511 IIC_VLD3, "vld3", Dt,
512 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
513 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
516 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
517 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
518 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
520 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
521 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
523 // VLD4LN : Vector Load (single 4-element structure to one lane)
524 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
525 : NLdSt<1, 0b10, op11_8, op7_4,
526 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
527 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
528 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
529 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
530 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
532 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
533 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
534 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
536 // ...with double-spaced registers:
537 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
538 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
540 // ...alternate versions to be allocated odd register numbers:
541 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
542 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
544 // ...with address register writeback:
545 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
546 : NLdSt<1, 0b10, op11_8, op7_4,
547 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
548 (ins addrmode6:$addr, am6offset:$offset,
549 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
550 IIC_VLD4, "vld4", Dt,
551 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
552 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
555 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
556 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
557 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
559 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
560 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
562 // VLD1DUP : Vector Load (single element to all lanes)
563 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
564 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
565 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
566 // FIXME: Not yet implemented.
567 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
569 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
571 // Classes for VST* pseudo-instructions with multi-register operands.
572 // These are expanded to real instructions after register allocation.
574 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, "">;
576 : PseudoNLdSt<(outs GPR:$wb),
577 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
580 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
582 : PseudoNLdSt<(outs GPR:$wb),
583 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST,
585 class VSTQQQQWBPseudo
586 : PseudoNLdSt<(outs GPR:$wb),
587 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
590 // VST1 : Vector Store (multiple single elements)
591 class VST1D<bits<4> op7_4, string Dt>
592 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
593 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
594 class VST1Q<bits<4> op7_4, string Dt>
595 : NLdSt<0,0b00,0b1010,op7_4, (outs),
596 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
597 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
599 def VST1d8 : VST1D<0b0000, "8">;
600 def VST1d16 : VST1D<0b0100, "16">;
601 def VST1d32 : VST1D<0b1000, "32">;
602 def VST1d64 : VST1D<0b1100, "64">;
604 def VST1q8 : VST1Q<0b0000, "8">;
605 def VST1q16 : VST1Q<0b0100, "16">;
606 def VST1q32 : VST1Q<0b1000, "32">;
607 def VST1q64 : VST1Q<0b1100, "64">;
609 def VST1q8Pseudo : VSTQPseudo;
610 def VST1q16Pseudo : VSTQPseudo;
611 def VST1q32Pseudo : VSTQPseudo;
612 def VST1q64Pseudo : VSTQPseudo;
614 // ...with address register writeback:
615 class VST1DWB<bits<4> op7_4, string Dt>
616 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
617 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
618 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
619 class VST1QWB<bits<4> op7_4, string Dt>
620 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
621 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
622 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
624 def VST1d8_UPD : VST1DWB<0b0000, "8">;
625 def VST1d16_UPD : VST1DWB<0b0100, "16">;
626 def VST1d32_UPD : VST1DWB<0b1000, "32">;
627 def VST1d64_UPD : VST1DWB<0b1100, "64">;
629 def VST1q8_UPD : VST1QWB<0b0000, "8">;
630 def VST1q16_UPD : VST1QWB<0b0100, "16">;
631 def VST1q32_UPD : VST1QWB<0b1000, "32">;
632 def VST1q64_UPD : VST1QWB<0b1100, "64">;
634 def VST1q8Pseudo_UPD : VSTQWBPseudo;
635 def VST1q16Pseudo_UPD : VSTQWBPseudo;
636 def VST1q32Pseudo_UPD : VSTQWBPseudo;
637 def VST1q64Pseudo_UPD : VSTQWBPseudo;
639 // ...with 3 registers (some of these are only for the disassembler):
640 class VST1D3<bits<4> op7_4, string Dt>
641 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
642 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
643 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
644 class VST1D3WB<bits<4> op7_4, string Dt>
645 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
646 (ins addrmode6:$addr, am6offset:$offset,
647 DPR:$src1, DPR:$src2, DPR:$src3),
648 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
649 "$addr.addr = $wb", []>;
651 def VST1d8T : VST1D3<0b0000, "8">;
652 def VST1d16T : VST1D3<0b0100, "16">;
653 def VST1d32T : VST1D3<0b1000, "32">;
654 def VST1d64T : VST1D3<0b1100, "64">;
656 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
657 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
658 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
659 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
661 def VST1d64TPseudo : VSTQQPseudo;
662 def VST1d64TPseudo_UPD : VSTQQWBPseudo;
664 // ...with 4 registers (some of these are only for the disassembler):
665 class VST1D4<bits<4> op7_4, string Dt>
666 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
667 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
668 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
670 class VST1D4WB<bits<4> op7_4, string Dt>
671 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
672 (ins addrmode6:$addr, am6offset:$offset,
673 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
674 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
675 "$addr.addr = $wb", []>;
677 def VST1d8Q : VST1D4<0b0000, "8">;
678 def VST1d16Q : VST1D4<0b0100, "16">;
679 def VST1d32Q : VST1D4<0b1000, "32">;
680 def VST1d64Q : VST1D4<0b1100, "64">;
682 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
683 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
684 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
685 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
687 def VST1d64QPseudo : VSTQQPseudo;
688 def VST1d64QPseudo_UPD : VSTQQWBPseudo;
690 // VST2 : Vector Store (multiple 2-element structures)
691 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
692 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
693 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
694 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
695 class VST2Q<bits<4> op7_4, string Dt>
696 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
697 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
698 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
701 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
702 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
703 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
705 def VST2q8 : VST2Q<0b0000, "8">;
706 def VST2q16 : VST2Q<0b0100, "16">;
707 def VST2q32 : VST2Q<0b1000, "32">;
709 def VST2d8Pseudo : VSTQPseudo;
710 def VST2d16Pseudo : VSTQPseudo;
711 def VST2d32Pseudo : VSTQPseudo;
713 def VST2q8Pseudo : VSTQQPseudo;
714 def VST2q16Pseudo : VSTQQPseudo;
715 def VST2q32Pseudo : VSTQQPseudo;
717 // ...with address register writeback:
718 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
719 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
720 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
721 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
722 "$addr.addr = $wb", []>;
723 class VST2QWB<bits<4> op7_4, string Dt>
724 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
725 (ins addrmode6:$addr, am6offset:$offset,
726 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
727 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
728 "$addr.addr = $wb", []>;
730 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
731 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
732 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
734 def VST2q8_UPD : VST2QWB<0b0000, "8">;
735 def VST2q16_UPD : VST2QWB<0b0100, "16">;
736 def VST2q32_UPD : VST2QWB<0b1000, "32">;
738 def VST2d8Pseudo_UPD : VSTQWBPseudo;
739 def VST2d16Pseudo_UPD : VSTQWBPseudo;
740 def VST2d32Pseudo_UPD : VSTQWBPseudo;
742 def VST2q8Pseudo_UPD : VSTQQWBPseudo;
743 def VST2q16Pseudo_UPD : VSTQQWBPseudo;
744 def VST2q32Pseudo_UPD : VSTQQWBPseudo;
746 // ...with double-spaced registers (for disassembly only):
747 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
748 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
749 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
750 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
751 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
752 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
754 // VST3 : Vector Store (multiple 3-element structures)
755 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
756 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
757 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
758 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
760 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
761 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
762 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
764 def VST3d8Pseudo : VSTQQPseudo;
765 def VST3d16Pseudo : VSTQQPseudo;
766 def VST3d32Pseudo : VSTQQPseudo;
768 // ...with address register writeback:
769 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
770 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
771 (ins addrmode6:$addr, am6offset:$offset,
772 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
773 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
774 "$addr.addr = $wb", []>;
776 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
777 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
778 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
780 def VST3d8Pseudo_UPD : VSTQQWBPseudo;
781 def VST3d16Pseudo_UPD : VSTQQWBPseudo;
782 def VST3d32Pseudo_UPD : VSTQQWBPseudo;
784 // ...with double-spaced registers (non-updating versions for disassembly only):
785 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
786 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
787 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
788 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
789 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
790 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
792 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo;
793 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo;
794 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo;
796 // ...alternate versions to be allocated odd register numbers:
797 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo;
798 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo;
799 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo;
801 // VST4 : Vector Store (multiple 4-element structures)
802 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
803 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
804 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
805 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
808 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
809 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
810 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
812 def VST4d8Pseudo : VSTQQPseudo;
813 def VST4d16Pseudo : VSTQQPseudo;
814 def VST4d32Pseudo : VSTQQPseudo;
816 // ...with address register writeback:
817 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
818 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
819 (ins addrmode6:$addr, am6offset:$offset,
820 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
821 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
822 "$addr.addr = $wb", []>;
824 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
825 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
826 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
828 def VST4d8Pseudo_UPD : VSTQQWBPseudo;
829 def VST4d16Pseudo_UPD : VSTQQWBPseudo;
830 def VST4d32Pseudo_UPD : VSTQQWBPseudo;
832 // ...with double-spaced registers (non-updating versions for disassembly only):
833 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
834 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
835 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
836 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
837 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
838 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
840 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo;
841 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo;
842 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo;
844 // ...alternate versions to be allocated odd register numbers:
845 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo;
846 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo;
847 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo;
849 // VST1LN : Vector Store (single element from one lane)
850 // FIXME: Not yet implemented.
852 // VST2LN : Vector Store (single 2-element structure from one lane)
853 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
854 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
855 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
856 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
859 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
860 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
861 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
863 // ...with double-spaced registers:
864 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
865 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
867 // ...alternate versions to be allocated odd register numbers:
868 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
869 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
871 // ...with address register writeback:
872 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
873 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
874 (ins addrmode6:$addr, am6offset:$offset,
875 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
876 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
877 "$addr.addr = $wb", []>;
879 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
880 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
881 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
883 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
884 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
886 // VST3LN : Vector Store (single 3-element structure from one lane)
887 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
888 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
889 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
890 nohash_imm:$lane), IIC_VST, "vst3", Dt,
891 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
893 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
894 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
895 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
897 // ...with double-spaced registers:
898 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
899 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
901 // ...alternate versions to be allocated odd register numbers:
902 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
903 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
905 // ...with address register writeback:
906 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
907 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
908 (ins addrmode6:$addr, am6offset:$offset,
909 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
911 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
912 "$addr.addr = $wb", []>;
914 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
915 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
916 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
918 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
919 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
921 // VST4LN : Vector Store (single 4-element structure from one lane)
922 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
923 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
924 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
925 nohash_imm:$lane), IIC_VST, "vst4", Dt,
926 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
929 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
930 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
931 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
933 // ...with double-spaced registers:
934 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
935 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
937 // ...alternate versions to be allocated odd register numbers:
938 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
939 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
941 // ...with address register writeback:
942 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
943 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
944 (ins addrmode6:$addr, am6offset:$offset,
945 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
947 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
948 "$addr.addr = $wb", []>;
950 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
951 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
952 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
954 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
955 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
957 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
960 //===----------------------------------------------------------------------===//
961 // NEON pattern fragments
962 //===----------------------------------------------------------------------===//
964 // Extract D sub-registers of Q registers.
965 def DSubReg_i8_reg : SDNodeXForm<imm, [{
966 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
967 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
969 def DSubReg_i16_reg : SDNodeXForm<imm, [{
970 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
971 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
973 def DSubReg_i32_reg : SDNodeXForm<imm, [{
974 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
975 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
977 def DSubReg_f64_reg : SDNodeXForm<imm, [{
978 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
979 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
982 // Extract S sub-registers of Q/D registers.
983 def SSubReg_f32_reg : SDNodeXForm<imm, [{
984 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
985 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
988 // Translate lane numbers from Q registers to D subregs.
989 def SubReg_i8_lane : SDNodeXForm<imm, [{
990 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
992 def SubReg_i16_lane : SDNodeXForm<imm, [{
993 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
995 def SubReg_i32_lane : SDNodeXForm<imm, [{
996 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
999 //===----------------------------------------------------------------------===//
1000 // Instruction Classes
1001 //===----------------------------------------------------------------------===//
1003 // Basic 2-register operations: single-, double- and quad-register.
1004 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1005 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1006 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1007 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1008 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1009 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1010 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1011 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1012 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1013 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1014 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1015 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1016 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1017 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1018 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1019 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1020 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1021 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1023 // Basic 2-register intrinsics, both double- and quad-register.
1024 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1025 bits<2> op17_16, bits<5> op11_7, bit op4,
1026 InstrItinClass itin, string OpcodeStr, string Dt,
1027 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1028 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1029 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1030 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1031 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1032 bits<2> op17_16, bits<5> op11_7, bit op4,
1033 InstrItinClass itin, string OpcodeStr, string Dt,
1034 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1035 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1036 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1037 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1039 // Narrow 2-register operations.
1040 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1041 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1042 InstrItinClass itin, string OpcodeStr, string Dt,
1043 ValueType TyD, ValueType TyQ, SDNode OpNode>
1044 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1045 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1046 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1048 // Narrow 2-register intrinsics.
1049 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1050 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1051 InstrItinClass itin, string OpcodeStr, string Dt,
1052 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1053 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1054 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1055 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1057 // Long 2-register operations (currently only used for VMOVL).
1058 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1059 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1060 InstrItinClass itin, string OpcodeStr, string Dt,
1061 ValueType TyQ, ValueType TyD, SDNode OpNode>
1062 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1063 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1064 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1066 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1067 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1068 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1069 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1070 OpcodeStr, Dt, "$dst1, $dst2",
1071 "$src1 = $dst1, $src2 = $dst2", []>;
1072 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1073 InstrItinClass itin, string OpcodeStr, string Dt>
1074 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1075 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1076 "$src1 = $dst1, $src2 = $dst2", []>;
1078 // Basic 3-register operations: single-, double- and quad-register.
1079 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1080 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1081 SDNode OpNode, bit Commutable>
1082 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1083 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1084 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1085 let isCommutable = Commutable;
1088 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1089 InstrItinClass itin, string OpcodeStr, string Dt,
1090 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1091 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1092 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1093 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1094 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1095 let isCommutable = Commutable;
1097 // Same as N3VD but no data type.
1098 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1099 InstrItinClass itin, string OpcodeStr,
1100 ValueType ResTy, ValueType OpTy,
1101 SDNode OpNode, bit Commutable>
1102 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1103 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1104 OpcodeStr, "$dst, $src1, $src2", "",
1105 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1106 let isCommutable = Commutable;
1109 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1110 InstrItinClass itin, string OpcodeStr, string Dt,
1111 ValueType Ty, SDNode ShOp>
1112 : N3V<0, 1, op21_20, op11_8, 1, 0,
1113 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1114 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1115 [(set (Ty DPR:$dst),
1116 (Ty (ShOp (Ty DPR:$src1),
1117 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1118 let isCommutable = 0;
1120 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1121 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1122 : N3V<0, 1, op21_20, op11_8, 1, 0,
1123 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1124 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1125 [(set (Ty DPR:$dst),
1126 (Ty (ShOp (Ty DPR:$src1),
1127 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1128 let isCommutable = 0;
1131 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1132 InstrItinClass itin, string OpcodeStr, string Dt,
1133 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1134 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1135 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1136 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1137 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1138 let isCommutable = Commutable;
1140 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1141 InstrItinClass itin, string OpcodeStr,
1142 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1143 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1144 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1145 OpcodeStr, "$dst, $src1, $src2", "",
1146 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1147 let isCommutable = Commutable;
1149 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1150 InstrItinClass itin, string OpcodeStr, string Dt,
1151 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1152 : N3V<1, 1, op21_20, op11_8, 1, 0,
1153 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1154 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1155 [(set (ResTy QPR:$dst),
1156 (ResTy (ShOp (ResTy QPR:$src1),
1157 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1159 let isCommutable = 0;
1161 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1162 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1163 : N3V<1, 1, op21_20, op11_8, 1, 0,
1164 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1165 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1166 [(set (ResTy QPR:$dst),
1167 (ResTy (ShOp (ResTy QPR:$src1),
1168 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1170 let isCommutable = 0;
1173 // Basic 3-register intrinsics, both double- and quad-register.
1174 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1175 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1176 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1177 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1178 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1179 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1180 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1181 let isCommutable = Commutable;
1183 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1184 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1185 : N3V<0, 1, op21_20, op11_8, 1, 0,
1186 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1187 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1188 [(set (Ty DPR:$dst),
1189 (Ty (IntOp (Ty DPR:$src1),
1190 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1192 let isCommutable = 0;
1194 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1195 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1196 : N3V<0, 1, op21_20, op11_8, 1, 0,
1197 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1198 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1199 [(set (Ty DPR:$dst),
1200 (Ty (IntOp (Ty DPR:$src1),
1201 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1202 let isCommutable = 0;
1205 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1206 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1207 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1208 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1209 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1210 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1211 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1212 let isCommutable = Commutable;
1214 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1215 string OpcodeStr, string Dt,
1216 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1217 : N3V<1, 1, op21_20, op11_8, 1, 0,
1218 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1219 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1220 [(set (ResTy QPR:$dst),
1221 (ResTy (IntOp (ResTy QPR:$src1),
1222 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1224 let isCommutable = 0;
1226 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1227 string OpcodeStr, string Dt,
1228 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1229 : N3V<1, 1, op21_20, op11_8, 1, 0,
1230 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1231 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1232 [(set (ResTy QPR:$dst),
1233 (ResTy (IntOp (ResTy QPR:$src1),
1234 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1236 let isCommutable = 0;
1239 // Multiply-Add/Sub operations: single-, double- and quad-register.
1240 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1241 InstrItinClass itin, string OpcodeStr, string Dt,
1242 ValueType Ty, SDNode MulOp, SDNode OpNode>
1243 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1244 (outs DPR_VFP2:$dst),
1245 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1246 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1248 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1249 InstrItinClass itin, string OpcodeStr, string Dt,
1250 ValueType Ty, SDNode MulOp, SDNode OpNode>
1251 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1252 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1253 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1254 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1255 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1256 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1257 string OpcodeStr, string Dt,
1258 ValueType Ty, SDNode MulOp, SDNode ShOp>
1259 : N3V<0, 1, op21_20, op11_8, 1, 0,
1261 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1263 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1264 [(set (Ty DPR:$dst),
1265 (Ty (ShOp (Ty DPR:$src1),
1266 (Ty (MulOp DPR:$src2,
1267 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1269 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1270 string OpcodeStr, string Dt,
1271 ValueType Ty, SDNode MulOp, SDNode ShOp>
1272 : N3V<0, 1, op21_20, op11_8, 1, 0,
1274 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1276 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1277 [(set (Ty DPR:$dst),
1278 (Ty (ShOp (Ty DPR:$src1),
1279 (Ty (MulOp DPR:$src2,
1280 (Ty (NEONvduplane (Ty DPR_8:$src3),
1283 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1284 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1285 SDNode MulOp, SDNode OpNode>
1286 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1287 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1288 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1289 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1290 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1291 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1292 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1293 SDNode MulOp, SDNode ShOp>
1294 : N3V<1, 1, op21_20, op11_8, 1, 0,
1296 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1298 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1299 [(set (ResTy QPR:$dst),
1300 (ResTy (ShOp (ResTy QPR:$src1),
1301 (ResTy (MulOp QPR:$src2,
1302 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1304 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1305 string OpcodeStr, string Dt,
1306 ValueType ResTy, ValueType OpTy,
1307 SDNode MulOp, SDNode ShOp>
1308 : N3V<1, 1, op21_20, op11_8, 1, 0,
1310 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1312 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1313 [(set (ResTy QPR:$dst),
1314 (ResTy (ShOp (ResTy QPR:$src1),
1315 (ResTy (MulOp QPR:$src2,
1316 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1319 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1320 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1321 InstrItinClass itin, string OpcodeStr, string Dt,
1322 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1323 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1324 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1325 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1326 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1327 (Ty (IntOp (Ty DPR:$src2), (Ty DPR:$src3))))))]>;
1328 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1329 InstrItinClass itin, string OpcodeStr, string Dt,
1330 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1331 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1332 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1333 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1334 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1335 (Ty (IntOp (Ty QPR:$src2), (Ty QPR:$src3))))))]>;
1337 // Neon 3-argument intrinsics, both double- and quad-register.
1338 // The destination register is also used as the first source operand register.
1339 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1340 InstrItinClass itin, string OpcodeStr, string Dt,
1341 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1342 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1343 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1344 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1345 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1346 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1347 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1348 InstrItinClass itin, string OpcodeStr, string Dt,
1349 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1350 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1351 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1352 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1353 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1354 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1356 // Long Multiply-Add/Sub operations.
1357 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1358 InstrItinClass itin, string OpcodeStr, string Dt,
1359 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1360 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1361 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1362 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1363 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1364 (TyQ (MulOp (TyD DPR:$src2),
1365 (TyD DPR:$src3)))))]>;
1366 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1367 InstrItinClass itin, string OpcodeStr, string Dt,
1368 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1369 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1370 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1372 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1374 (OpNode (TyQ QPR:$src1),
1375 (TyQ (MulOp (TyD DPR:$src2),
1376 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
1378 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1379 InstrItinClass itin, string OpcodeStr, string Dt,
1380 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
1381 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
1382 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1384 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1386 (OpNode (TyQ QPR:$src1),
1387 (TyQ (MulOp (TyD DPR:$src2),
1388 (TyD (NEONvduplane (TyD DPR_8:$src3),
1391 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
1392 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1393 InstrItinClass itin, string OpcodeStr, string Dt,
1394 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1396 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1397 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1398 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1399 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1400 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src2),
1401 (TyD DPR:$src3)))))))]>;
1403 // Neon Long 3-argument intrinsic. The destination register is
1404 // a quad-register and is also used as the first source operand register.
1405 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1406 InstrItinClass itin, string OpcodeStr, string Dt,
1407 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1408 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1409 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1410 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1412 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1413 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1414 string OpcodeStr, string Dt,
1415 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1416 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1418 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1420 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1421 [(set (ResTy QPR:$dst),
1422 (ResTy (IntOp (ResTy QPR:$src1),
1424 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1426 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1427 InstrItinClass itin, string OpcodeStr, string Dt,
1428 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1429 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1431 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1433 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1434 [(set (ResTy QPR:$dst),
1435 (ResTy (IntOp (ResTy QPR:$src1),
1437 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1440 // Narrowing 3-register intrinsics.
1441 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1442 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1443 Intrinsic IntOp, bit Commutable>
1444 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1445 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1446 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1447 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1448 let isCommutable = Commutable;
1451 // Long 3-register operations.
1452 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1453 InstrItinClass itin, string OpcodeStr, string Dt,
1454 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
1455 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1456 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1457 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1458 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1459 let isCommutable = Commutable;
1461 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
1462 InstrItinClass itin, string OpcodeStr, string Dt,
1463 ValueType TyQ, ValueType TyD, SDNode OpNode>
1464 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1465 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1466 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1468 (TyQ (OpNode (TyD DPR:$src1),
1469 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
1470 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1471 InstrItinClass itin, string OpcodeStr, string Dt,
1472 ValueType TyQ, ValueType TyD, SDNode OpNode>
1473 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1474 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1475 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1477 (TyQ (OpNode (TyD DPR:$src1),
1478 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
1480 // Long 3-register operations with explicitly extended operands.
1481 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1482 InstrItinClass itin, string OpcodeStr, string Dt,
1483 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1485 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1486 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1487 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1488 [(set QPR:$dst, (OpNode (TyQ (ExtOp (TyD DPR:$src1))),
1489 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1490 let isCommutable = Commutable;
1493 // Long 3-register intrinsics with explicit extend (VABDL).
1494 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1495 InstrItinClass itin, string OpcodeStr, string Dt,
1496 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
1498 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1499 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1500 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1501 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
1502 (TyD DPR:$src2))))))]> {
1503 let isCommutable = Commutable;
1506 // Long 3-register intrinsics.
1507 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1508 InstrItinClass itin, string OpcodeStr, string Dt,
1509 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1510 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1511 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1512 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1513 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1514 let isCommutable = Commutable;
1516 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1517 string OpcodeStr, string Dt,
1518 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1519 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1520 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1521 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1522 [(set (ResTy QPR:$dst),
1523 (ResTy (IntOp (OpTy DPR:$src1),
1524 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1526 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1527 InstrItinClass itin, string OpcodeStr, string Dt,
1528 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1529 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1530 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1531 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1532 [(set (ResTy QPR:$dst),
1533 (ResTy (IntOp (OpTy DPR:$src1),
1534 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1537 // Wide 3-register operations.
1538 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1539 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1540 SDNode OpNode, SDNode ExtOp, bit Commutable>
1541 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1542 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1543 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1544 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1545 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1546 let isCommutable = Commutable;
1549 // Pairwise long 2-register intrinsics, both double- and quad-register.
1550 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1551 bits<2> op17_16, bits<5> op11_7, bit op4,
1552 string OpcodeStr, string Dt,
1553 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1554 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1555 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1556 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1557 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1558 bits<2> op17_16, bits<5> op11_7, bit op4,
1559 string OpcodeStr, string Dt,
1560 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1561 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1562 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1563 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1565 // Pairwise long 2-register accumulate intrinsics,
1566 // both double- and quad-register.
1567 // The destination register is also used as the first source operand register.
1568 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1569 bits<2> op17_16, bits<5> op11_7, bit op4,
1570 string OpcodeStr, string Dt,
1571 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1572 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1573 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1574 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1575 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1576 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1577 bits<2> op17_16, bits<5> op11_7, bit op4,
1578 string OpcodeStr, string Dt,
1579 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1580 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1581 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1582 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1583 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1585 // Shift by immediate,
1586 // both double- and quad-register.
1587 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1588 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1589 ValueType Ty, SDNode OpNode>
1590 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1591 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1592 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1593 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1594 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1595 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1596 ValueType Ty, SDNode OpNode>
1597 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1598 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1599 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1600 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1602 // Long shift by immediate.
1603 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1604 string OpcodeStr, string Dt,
1605 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1606 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1607 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1608 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1609 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1610 (i32 imm:$SIMM))))]>;
1612 // Narrow shift by immediate.
1613 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1614 InstrItinClass itin, string OpcodeStr, string Dt,
1615 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1616 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1617 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1618 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1619 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1620 (i32 imm:$SIMM))))]>;
1622 // Shift right by immediate and accumulate,
1623 // both double- and quad-register.
1624 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1625 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1626 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1627 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1628 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1629 [(set DPR:$dst, (Ty (add DPR:$src1,
1630 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1631 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1632 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1633 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1634 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1635 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1636 [(set QPR:$dst, (Ty (add QPR:$src1,
1637 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1639 // Shift by immediate and insert,
1640 // both double- and quad-register.
1641 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1642 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1643 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1644 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1645 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1646 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1647 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1648 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1649 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1650 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1651 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1652 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1654 // Convert, with fractional bits immediate,
1655 // both double- and quad-register.
1656 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1657 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1659 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1660 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1661 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1662 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1663 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1664 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1666 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1667 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1668 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1669 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1671 //===----------------------------------------------------------------------===//
1673 //===----------------------------------------------------------------------===//
1675 // Abbreviations used in multiclass suffixes:
1676 // Q = quarter int (8 bit) elements
1677 // H = half int (16 bit) elements
1678 // S = single int (32 bit) elements
1679 // D = double int (64 bit) elements
1681 // Neon 2-register vector operations -- for disassembly only.
1683 // First with only element sizes of 8, 16 and 32 bits:
1684 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1685 bits<5> op11_7, bit op4, string opc, string Dt,
1687 // 64-bit vector types.
1688 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1689 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1690 opc, !strconcat(Dt, "8"), asm, "", []>;
1691 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1692 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1693 opc, !strconcat(Dt, "16"), asm, "", []>;
1694 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1695 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1696 opc, !strconcat(Dt, "32"), asm, "", []>;
1697 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1698 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1699 opc, "f32", asm, "", []> {
1700 let Inst{10} = 1; // overwrite F = 1
1703 // 128-bit vector types.
1704 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1705 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1706 opc, !strconcat(Dt, "8"), asm, "", []>;
1707 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1708 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1709 opc, !strconcat(Dt, "16"), asm, "", []>;
1710 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1711 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1712 opc, !strconcat(Dt, "32"), asm, "", []>;
1713 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1714 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1715 opc, "f32", asm, "", []> {
1716 let Inst{10} = 1; // overwrite F = 1
1720 // Neon 3-register vector operations.
1722 // First with only element sizes of 8, 16 and 32 bits:
1723 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1724 InstrItinClass itinD16, InstrItinClass itinD32,
1725 InstrItinClass itinQ16, InstrItinClass itinQ32,
1726 string OpcodeStr, string Dt,
1727 SDNode OpNode, bit Commutable = 0> {
1728 // 64-bit vector types.
1729 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1730 OpcodeStr, !strconcat(Dt, "8"),
1731 v8i8, v8i8, OpNode, Commutable>;
1732 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1733 OpcodeStr, !strconcat(Dt, "16"),
1734 v4i16, v4i16, OpNode, Commutable>;
1735 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1736 OpcodeStr, !strconcat(Dt, "32"),
1737 v2i32, v2i32, OpNode, Commutable>;
1739 // 128-bit vector types.
1740 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1741 OpcodeStr, !strconcat(Dt, "8"),
1742 v16i8, v16i8, OpNode, Commutable>;
1743 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1744 OpcodeStr, !strconcat(Dt, "16"),
1745 v8i16, v8i16, OpNode, Commutable>;
1746 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1747 OpcodeStr, !strconcat(Dt, "32"),
1748 v4i32, v4i32, OpNode, Commutable>;
1751 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1752 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1754 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1756 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1757 v8i16, v4i16, ShOp>;
1758 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1759 v4i32, v2i32, ShOp>;
1762 // ....then also with element size 64 bits:
1763 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1764 InstrItinClass itinD, InstrItinClass itinQ,
1765 string OpcodeStr, string Dt,
1766 SDNode OpNode, bit Commutable = 0>
1767 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1768 OpcodeStr, Dt, OpNode, Commutable> {
1769 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1770 OpcodeStr, !strconcat(Dt, "64"),
1771 v1i64, v1i64, OpNode, Commutable>;
1772 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1773 OpcodeStr, !strconcat(Dt, "64"),
1774 v2i64, v2i64, OpNode, Commutable>;
1778 // Neon Narrowing 2-register vector operations,
1779 // source operand element sizes of 16, 32 and 64 bits:
1780 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1781 bits<5> op11_7, bit op6, bit op4,
1782 InstrItinClass itin, string OpcodeStr, string Dt,
1784 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1785 itin, OpcodeStr, !strconcat(Dt, "16"),
1786 v8i8, v8i16, OpNode>;
1787 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1788 itin, OpcodeStr, !strconcat(Dt, "32"),
1789 v4i16, v4i32, OpNode>;
1790 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1791 itin, OpcodeStr, !strconcat(Dt, "64"),
1792 v2i32, v2i64, OpNode>;
1795 // Neon Narrowing 2-register vector intrinsics,
1796 // source operand element sizes of 16, 32 and 64 bits:
1797 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1798 bits<5> op11_7, bit op6, bit op4,
1799 InstrItinClass itin, string OpcodeStr, string Dt,
1801 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1802 itin, OpcodeStr, !strconcat(Dt, "16"),
1803 v8i8, v8i16, IntOp>;
1804 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1805 itin, OpcodeStr, !strconcat(Dt, "32"),
1806 v4i16, v4i32, IntOp>;
1807 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1808 itin, OpcodeStr, !strconcat(Dt, "64"),
1809 v2i32, v2i64, IntOp>;
1813 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1814 // source operand element sizes of 16, 32 and 64 bits:
1815 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1816 string OpcodeStr, string Dt, SDNode OpNode> {
1817 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1818 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
1819 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1820 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1821 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1822 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1826 // Neon 3-register vector intrinsics.
1828 // First with only element sizes of 16 and 32 bits:
1829 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1830 InstrItinClass itinD16, InstrItinClass itinD32,
1831 InstrItinClass itinQ16, InstrItinClass itinQ32,
1832 string OpcodeStr, string Dt,
1833 Intrinsic IntOp, bit Commutable = 0> {
1834 // 64-bit vector types.
1835 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1836 OpcodeStr, !strconcat(Dt, "16"),
1837 v4i16, v4i16, IntOp, Commutable>;
1838 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1839 OpcodeStr, !strconcat(Dt, "32"),
1840 v2i32, v2i32, IntOp, Commutable>;
1842 // 128-bit vector types.
1843 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1844 OpcodeStr, !strconcat(Dt, "16"),
1845 v8i16, v8i16, IntOp, Commutable>;
1846 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1847 OpcodeStr, !strconcat(Dt, "32"),
1848 v4i32, v4i32, IntOp, Commutable>;
1851 multiclass N3VIntSL_HS<bits<4> op11_8,
1852 InstrItinClass itinD16, InstrItinClass itinD32,
1853 InstrItinClass itinQ16, InstrItinClass itinQ32,
1854 string OpcodeStr, string Dt, Intrinsic IntOp> {
1855 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1856 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1857 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1858 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1859 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1860 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1861 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1862 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1865 // ....then also with element size of 8 bits:
1866 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1867 InstrItinClass itinD16, InstrItinClass itinD32,
1868 InstrItinClass itinQ16, InstrItinClass itinQ32,
1869 string OpcodeStr, string Dt,
1870 Intrinsic IntOp, bit Commutable = 0>
1871 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1872 OpcodeStr, Dt, IntOp, Commutable> {
1873 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1874 OpcodeStr, !strconcat(Dt, "8"),
1875 v8i8, v8i8, IntOp, Commutable>;
1876 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1877 OpcodeStr, !strconcat(Dt, "8"),
1878 v16i8, v16i8, IntOp, Commutable>;
1881 // ....then also with element size of 64 bits:
1882 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1883 InstrItinClass itinD16, InstrItinClass itinD32,
1884 InstrItinClass itinQ16, InstrItinClass itinQ32,
1885 string OpcodeStr, string Dt,
1886 Intrinsic IntOp, bit Commutable = 0>
1887 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1888 OpcodeStr, Dt, IntOp, Commutable> {
1889 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1890 OpcodeStr, !strconcat(Dt, "64"),
1891 v1i64, v1i64, IntOp, Commutable>;
1892 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1893 OpcodeStr, !strconcat(Dt, "64"),
1894 v2i64, v2i64, IntOp, Commutable>;
1897 // Neon Narrowing 3-register vector intrinsics,
1898 // source operand element sizes of 16, 32 and 64 bits:
1899 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1900 string OpcodeStr, string Dt,
1901 Intrinsic IntOp, bit Commutable = 0> {
1902 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1903 OpcodeStr, !strconcat(Dt, "16"),
1904 v8i8, v8i16, IntOp, Commutable>;
1905 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1906 OpcodeStr, !strconcat(Dt, "32"),
1907 v4i16, v4i32, IntOp, Commutable>;
1908 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1909 OpcodeStr, !strconcat(Dt, "64"),
1910 v2i32, v2i64, IntOp, Commutable>;
1914 // Neon Long 3-register vector operations.
1916 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1917 InstrItinClass itin16, InstrItinClass itin32,
1918 string OpcodeStr, string Dt,
1919 SDNode OpNode, bit Commutable = 0> {
1920 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
1921 OpcodeStr, !strconcat(Dt, "8"),
1922 v8i16, v8i8, OpNode, Commutable>;
1923 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
1924 OpcodeStr, !strconcat(Dt, "16"),
1925 v4i32, v4i16, OpNode, Commutable>;
1926 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
1927 OpcodeStr, !strconcat(Dt, "32"),
1928 v2i64, v2i32, OpNode, Commutable>;
1931 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
1932 InstrItinClass itin, string OpcodeStr, string Dt,
1934 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
1935 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1936 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
1937 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1940 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1941 InstrItinClass itin16, InstrItinClass itin32,
1942 string OpcodeStr, string Dt,
1943 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
1944 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
1945 OpcodeStr, !strconcat(Dt, "8"),
1946 v8i16, v8i8, OpNode, ExtOp, Commutable>;
1947 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
1948 OpcodeStr, !strconcat(Dt, "16"),
1949 v4i32, v4i16, OpNode, ExtOp, Commutable>;
1950 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
1951 OpcodeStr, !strconcat(Dt, "32"),
1952 v2i64, v2i32, OpNode, ExtOp, Commutable>;
1955 // Neon Long 3-register vector intrinsics.
1957 // First with only element sizes of 16 and 32 bits:
1958 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1959 InstrItinClass itin16, InstrItinClass itin32,
1960 string OpcodeStr, string Dt,
1961 Intrinsic IntOp, bit Commutable = 0> {
1962 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
1963 OpcodeStr, !strconcat(Dt, "16"),
1964 v4i32, v4i16, IntOp, Commutable>;
1965 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
1966 OpcodeStr, !strconcat(Dt, "32"),
1967 v2i64, v2i32, IntOp, Commutable>;
1970 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1971 InstrItinClass itin, string OpcodeStr, string Dt,
1973 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1974 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1975 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1976 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1979 // ....then also with element size of 8 bits:
1980 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1981 InstrItinClass itin16, InstrItinClass itin32,
1982 string OpcodeStr, string Dt,
1983 Intrinsic IntOp, bit Commutable = 0>
1984 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
1985 IntOp, Commutable> {
1986 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
1987 OpcodeStr, !strconcat(Dt, "8"),
1988 v8i16, v8i8, IntOp, Commutable>;
1991 // ....with explicit extend (VABDL).
1992 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1993 InstrItinClass itin, string OpcodeStr, string Dt,
1994 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
1995 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
1996 OpcodeStr, !strconcat(Dt, "8"),
1997 v8i16, v8i8, IntOp, ExtOp, Commutable>;
1998 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
1999 OpcodeStr, !strconcat(Dt, "16"),
2000 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2001 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2002 OpcodeStr, !strconcat(Dt, "32"),
2003 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2007 // Neon Wide 3-register vector intrinsics,
2008 // source operand element sizes of 8, 16 and 32 bits:
2009 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2010 string OpcodeStr, string Dt,
2011 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2012 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2013 OpcodeStr, !strconcat(Dt, "8"),
2014 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2015 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2016 OpcodeStr, !strconcat(Dt, "16"),
2017 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2018 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2019 OpcodeStr, !strconcat(Dt, "32"),
2020 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2024 // Neon Multiply-Op vector operations,
2025 // element sizes of 8, 16 and 32 bits:
2026 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2027 InstrItinClass itinD16, InstrItinClass itinD32,
2028 InstrItinClass itinQ16, InstrItinClass itinQ32,
2029 string OpcodeStr, string Dt, SDNode OpNode> {
2030 // 64-bit vector types.
2031 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2032 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2033 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2034 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2035 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2036 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2038 // 128-bit vector types.
2039 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2040 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2041 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2042 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2043 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2044 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2047 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2048 InstrItinClass itinD16, InstrItinClass itinD32,
2049 InstrItinClass itinQ16, InstrItinClass itinQ32,
2050 string OpcodeStr, string Dt, SDNode ShOp> {
2051 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2052 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2053 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2054 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2055 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2056 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2058 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2059 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2063 // Neon Intrinsic-Op vector operations,
2064 // element sizes of 8, 16 and 32 bits:
2065 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2066 InstrItinClass itinD, InstrItinClass itinQ,
2067 string OpcodeStr, string Dt, Intrinsic IntOp,
2069 // 64-bit vector types.
2070 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2071 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2072 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2073 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2074 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2075 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2077 // 128-bit vector types.
2078 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2079 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2080 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2081 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2082 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2083 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2086 // Neon 3-argument intrinsics,
2087 // element sizes of 8, 16 and 32 bits:
2088 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2089 InstrItinClass itinD, InstrItinClass itinQ,
2090 string OpcodeStr, string Dt, Intrinsic IntOp> {
2091 // 64-bit vector types.
2092 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2093 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2094 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2095 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2096 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2097 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2099 // 128-bit vector types.
2100 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2101 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2102 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2103 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2104 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2105 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2109 // Neon Long Multiply-Op vector operations,
2110 // element sizes of 8, 16 and 32 bits:
2111 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2112 InstrItinClass itin16, InstrItinClass itin32,
2113 string OpcodeStr, string Dt, SDNode MulOp,
2115 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2116 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2117 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2118 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2119 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2120 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2123 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2124 string Dt, SDNode MulOp, SDNode OpNode> {
2125 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2126 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2127 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2128 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2132 // Neon Long 3-argument intrinsics.
2134 // First with only element sizes of 16 and 32 bits:
2135 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2136 InstrItinClass itin16, InstrItinClass itin32,
2137 string OpcodeStr, string Dt, Intrinsic IntOp> {
2138 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2139 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2140 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2141 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2144 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2145 string OpcodeStr, string Dt, Intrinsic IntOp> {
2146 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2147 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2148 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2149 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2152 // ....then also with element size of 8 bits:
2153 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2154 InstrItinClass itin16, InstrItinClass itin32,
2155 string OpcodeStr, string Dt, Intrinsic IntOp>
2156 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2157 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2158 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2161 // ....with explicit extend (VABAL).
2162 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2163 InstrItinClass itin, string OpcodeStr, string Dt,
2164 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2165 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2166 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2167 IntOp, ExtOp, OpNode>;
2168 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2169 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2170 IntOp, ExtOp, OpNode>;
2171 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2172 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2173 IntOp, ExtOp, OpNode>;
2177 // Neon 2-register vector intrinsics,
2178 // element sizes of 8, 16 and 32 bits:
2179 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2180 bits<5> op11_7, bit op4,
2181 InstrItinClass itinD, InstrItinClass itinQ,
2182 string OpcodeStr, string Dt, Intrinsic IntOp> {
2183 // 64-bit vector types.
2184 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2185 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2186 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2187 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2188 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2189 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2191 // 128-bit vector types.
2192 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2193 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2194 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2195 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2196 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2197 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2201 // Neon Pairwise long 2-register intrinsics,
2202 // element sizes of 8, 16 and 32 bits:
2203 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2204 bits<5> op11_7, bit op4,
2205 string OpcodeStr, string Dt, Intrinsic IntOp> {
2206 // 64-bit vector types.
2207 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2208 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2209 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2210 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2211 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2212 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2214 // 128-bit vector types.
2215 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2216 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2217 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2218 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2219 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2220 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2224 // Neon Pairwise long 2-register accumulate intrinsics,
2225 // element sizes of 8, 16 and 32 bits:
2226 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2227 bits<5> op11_7, bit op4,
2228 string OpcodeStr, string Dt, Intrinsic IntOp> {
2229 // 64-bit vector types.
2230 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2231 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2232 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2233 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2234 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2235 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2237 // 128-bit vector types.
2238 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2239 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2240 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2241 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2242 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2243 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2247 // Neon 2-register vector shift by immediate,
2248 // with f of either N2RegVShLFrm or N2RegVShRFrm
2249 // element sizes of 8, 16, 32 and 64 bits:
2250 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2251 InstrItinClass itin, string OpcodeStr, string Dt,
2252 SDNode OpNode, Format f> {
2253 // 64-bit vector types.
2254 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2255 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2256 let Inst{21-19} = 0b001; // imm6 = 001xxx
2258 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2259 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2260 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2262 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2263 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2264 let Inst{21} = 0b1; // imm6 = 1xxxxx
2266 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2267 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
2270 // 128-bit vector types.
2271 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2272 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
2273 let Inst{21-19} = 0b001; // imm6 = 001xxx
2275 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2276 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
2277 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2279 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
2280 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
2281 let Inst{21} = 0b1; // imm6 = 1xxxxx
2283 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
2284 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2288 // Neon Shift-Accumulate vector operations,
2289 // element sizes of 8, 16, 32 and 64 bits:
2290 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2291 string OpcodeStr, string Dt, SDNode ShOp> {
2292 // 64-bit vector types.
2293 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2294 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2295 let Inst{21-19} = 0b001; // imm6 = 001xxx
2297 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2298 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2299 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2301 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2302 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2303 let Inst{21} = 0b1; // imm6 = 1xxxxx
2305 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2306 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2309 // 128-bit vector types.
2310 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2311 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2312 let Inst{21-19} = 0b001; // imm6 = 001xxx
2314 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2315 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2316 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2318 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2319 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2320 let Inst{21} = 0b1; // imm6 = 1xxxxx
2322 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2323 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2328 // Neon Shift-Insert vector operations,
2329 // with f of either N2RegVShLFrm or N2RegVShRFrm
2330 // element sizes of 8, 16, 32 and 64 bits:
2331 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2332 string OpcodeStr, SDNode ShOp,
2334 // 64-bit vector types.
2335 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2336 f, OpcodeStr, "8", v8i8, ShOp> {
2337 let Inst{21-19} = 0b001; // imm6 = 001xxx
2339 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2340 f, OpcodeStr, "16", v4i16, ShOp> {
2341 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2343 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2344 f, OpcodeStr, "32", v2i32, ShOp> {
2345 let Inst{21} = 0b1; // imm6 = 1xxxxx
2347 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2348 f, OpcodeStr, "64", v1i64, ShOp>;
2351 // 128-bit vector types.
2352 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2353 f, OpcodeStr, "8", v16i8, ShOp> {
2354 let Inst{21-19} = 0b001; // imm6 = 001xxx
2356 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2357 f, OpcodeStr, "16", v8i16, ShOp> {
2358 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2360 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2361 f, OpcodeStr, "32", v4i32, ShOp> {
2362 let Inst{21} = 0b1; // imm6 = 1xxxxx
2364 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2365 f, OpcodeStr, "64", v2i64, ShOp>;
2369 // Neon Shift Long operations,
2370 // element sizes of 8, 16, 32 bits:
2371 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2372 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2373 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2374 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2375 let Inst{21-19} = 0b001; // imm6 = 001xxx
2377 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2378 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2379 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2381 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2382 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2383 let Inst{21} = 0b1; // imm6 = 1xxxxx
2387 // Neon Shift Narrow operations,
2388 // element sizes of 16, 32, 64 bits:
2389 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2390 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2392 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2393 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2394 let Inst{21-19} = 0b001; // imm6 = 001xxx
2396 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2397 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2398 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2400 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2401 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2402 let Inst{21} = 0b1; // imm6 = 1xxxxx
2406 //===----------------------------------------------------------------------===//
2407 // Instruction Definitions.
2408 //===----------------------------------------------------------------------===//
2410 // Vector Add Operations.
2412 // VADD : Vector Add (integer and floating-point)
2413 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2415 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2416 v2f32, v2f32, fadd, 1>;
2417 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2418 v4f32, v4f32, fadd, 1>;
2419 // VADDL : Vector Add Long (Q = D + D)
2420 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2421 "vaddl", "s", add, sext, 1>;
2422 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2423 "vaddl", "u", add, zext, 1>;
2424 // VADDW : Vector Add Wide (Q = Q + D)
2425 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2426 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2427 // VHADD : Vector Halving Add
2428 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2429 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2430 "vhadd", "s", int_arm_neon_vhadds, 1>;
2431 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2432 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2433 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2434 // VRHADD : Vector Rounding Halving Add
2435 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2436 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2437 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2438 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2439 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2440 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2441 // VQADD : Vector Saturating Add
2442 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2443 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2444 "vqadd", "s", int_arm_neon_vqadds, 1>;
2445 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2446 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2447 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2448 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2449 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2450 int_arm_neon_vaddhn, 1>;
2451 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2452 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2453 int_arm_neon_vraddhn, 1>;
2455 // Vector Multiply Operations.
2457 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2458 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2459 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2460 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2461 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2462 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2463 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2464 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2465 v2f32, v2f32, fmul, 1>;
2466 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2467 v4f32, v4f32, fmul, 1>;
2468 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2469 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2470 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2473 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2474 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2475 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2476 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2477 (DSubReg_i16_reg imm:$lane))),
2478 (SubReg_i16_lane imm:$lane)))>;
2479 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2480 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2481 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2482 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2483 (DSubReg_i32_reg imm:$lane))),
2484 (SubReg_i32_lane imm:$lane)))>;
2485 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2486 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2487 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2488 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2489 (DSubReg_i32_reg imm:$lane))),
2490 (SubReg_i32_lane imm:$lane)))>;
2492 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2493 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2494 IIC_VMULi16Q, IIC_VMULi32Q,
2495 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2496 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2497 IIC_VMULi16Q, IIC_VMULi32Q,
2498 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2499 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2500 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2502 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2503 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2504 (DSubReg_i16_reg imm:$lane))),
2505 (SubReg_i16_lane imm:$lane)))>;
2506 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2507 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2509 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2510 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2511 (DSubReg_i32_reg imm:$lane))),
2512 (SubReg_i32_lane imm:$lane)))>;
2514 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2515 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2516 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2517 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2518 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2519 IIC_VMULi16Q, IIC_VMULi32Q,
2520 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2521 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2522 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2524 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2525 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2526 (DSubReg_i16_reg imm:$lane))),
2527 (SubReg_i16_lane imm:$lane)))>;
2528 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2529 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2531 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2532 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2533 (DSubReg_i32_reg imm:$lane))),
2534 (SubReg_i32_lane imm:$lane)))>;
2536 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2537 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2538 "vmull", "s", NEONvmulls, 1>;
2539 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2540 "vmull", "u", NEONvmullu, 1>;
2541 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2542 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2543 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
2544 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
2546 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2547 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2548 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2549 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2550 "vqdmull", "s", int_arm_neon_vqdmull>;
2552 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2554 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2555 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2556 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2557 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2559 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2561 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2562 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2563 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2565 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2566 v4f32, v2f32, fmul, fadd>;
2568 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2569 (mul (v8i16 QPR:$src2),
2570 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2571 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2572 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2573 (DSubReg_i16_reg imm:$lane))),
2574 (SubReg_i16_lane imm:$lane)))>;
2576 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2577 (mul (v4i32 QPR:$src2),
2578 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2579 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2580 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2581 (DSubReg_i32_reg imm:$lane))),
2582 (SubReg_i32_lane imm:$lane)))>;
2584 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2585 (fmul (v4f32 QPR:$src2),
2586 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2587 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2589 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2590 (DSubReg_i32_reg imm:$lane))),
2591 (SubReg_i32_lane imm:$lane)))>;
2593 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2594 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2595 "vmlal", "s", NEONvmulls, add>;
2596 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2597 "vmlal", "u", NEONvmullu, add>;
2599 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
2600 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
2602 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2603 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2604 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2605 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2607 // VMLS : Vector Multiply Subtract (integer and floating-point)
2608 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2609 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2610 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2612 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2614 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2615 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2616 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2618 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2619 v4f32, v2f32, fmul, fsub>;
2621 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2622 (mul (v8i16 QPR:$src2),
2623 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2624 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2625 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2626 (DSubReg_i16_reg imm:$lane))),
2627 (SubReg_i16_lane imm:$lane)))>;
2629 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2630 (mul (v4i32 QPR:$src2),
2631 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2632 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2633 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2634 (DSubReg_i32_reg imm:$lane))),
2635 (SubReg_i32_lane imm:$lane)))>;
2637 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2638 (fmul (v4f32 QPR:$src2),
2639 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2640 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2641 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2642 (DSubReg_i32_reg imm:$lane))),
2643 (SubReg_i32_lane imm:$lane)))>;
2645 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2646 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2647 "vmlsl", "s", NEONvmulls, sub>;
2648 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2649 "vmlsl", "u", NEONvmullu, sub>;
2651 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
2652 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
2654 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2655 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2656 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2657 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2659 // Vector Subtract Operations.
2661 // VSUB : Vector Subtract (integer and floating-point)
2662 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2663 "vsub", "i", sub, 0>;
2664 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2665 v2f32, v2f32, fsub, 0>;
2666 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2667 v4f32, v4f32, fsub, 0>;
2668 // VSUBL : Vector Subtract Long (Q = D - D)
2669 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2670 "vsubl", "s", sub, sext, 0>;
2671 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2672 "vsubl", "u", sub, zext, 0>;
2673 // VSUBW : Vector Subtract Wide (Q = Q - D)
2674 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
2675 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
2676 // VHSUB : Vector Halving Subtract
2677 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2678 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2679 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2680 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2681 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2682 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2683 // VQSUB : Vector Saturing Subtract
2684 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2685 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2686 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2687 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2688 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2689 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2690 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2691 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2692 int_arm_neon_vsubhn, 0>;
2693 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2694 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2695 int_arm_neon_vrsubhn, 0>;
2697 // Vector Comparisons.
2699 // VCEQ : Vector Compare Equal
2700 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2701 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2702 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2704 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2706 // For disassembly only.
2707 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2710 // VCGE : Vector Compare Greater Than or Equal
2711 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2712 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2713 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2714 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2715 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2717 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2719 // For disassembly only.
2720 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2722 // For disassembly only.
2723 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2726 // VCGT : Vector Compare Greater Than
2727 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2728 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2729 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2730 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2731 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2733 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2735 // For disassembly only.
2736 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2738 // For disassembly only.
2739 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2742 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2743 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2744 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2745 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2746 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2747 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2748 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2749 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2750 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2751 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2752 // VTST : Vector Test Bits
2753 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2754 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2756 // Vector Bitwise Operations.
2758 def vnotd : PatFrag<(ops node:$in),
2759 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2760 def vnotq : PatFrag<(ops node:$in),
2761 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2764 // VAND : Vector Bitwise AND
2765 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2766 v2i32, v2i32, and, 1>;
2767 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2768 v4i32, v4i32, and, 1>;
2770 // VEOR : Vector Bitwise Exclusive OR
2771 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2772 v2i32, v2i32, xor, 1>;
2773 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2774 v4i32, v4i32, xor, 1>;
2776 // VORR : Vector Bitwise OR
2777 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2778 v2i32, v2i32, or, 1>;
2779 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2780 v4i32, v4i32, or, 1>;
2782 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2783 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2784 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2785 "vbic", "$dst, $src1, $src2", "",
2786 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2787 (vnotd DPR:$src2))))]>;
2788 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2789 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2790 "vbic", "$dst, $src1, $src2", "",
2791 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2792 (vnotq QPR:$src2))))]>;
2794 // VORN : Vector Bitwise OR NOT
2795 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2796 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2797 "vorn", "$dst, $src1, $src2", "",
2798 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2799 (vnotd DPR:$src2))))]>;
2800 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2801 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2802 "vorn", "$dst, $src1, $src2", "",
2803 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2804 (vnotq QPR:$src2))))]>;
2806 // VMVN : Vector Bitwise NOT (Immediate)
2808 let isReMaterializable = 1 in {
2809 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2810 (ins nModImm:$SIMM), IIC_VMOVImm,
2811 "vmvn", "i16", "$dst, $SIMM", "",
2812 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2813 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2814 (ins nModImm:$SIMM), IIC_VMOVImm,
2815 "vmvn", "i16", "$dst, $SIMM", "",
2816 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2818 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2819 (ins nModImm:$SIMM), IIC_VMOVImm,
2820 "vmvn", "i32", "$dst, $SIMM", "",
2821 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2822 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2823 (ins nModImm:$SIMM), IIC_VMOVImm,
2824 "vmvn", "i32", "$dst, $SIMM", "",
2825 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2828 // VMVN : Vector Bitwise NOT
2829 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2830 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2831 "vmvn", "$dst, $src", "",
2832 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2833 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2834 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2835 "vmvn", "$dst, $src", "",
2836 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2837 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2838 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2840 // VBSL : Vector Bitwise Select
2841 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2842 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2843 N3RegFrm, IIC_VCNTiD,
2844 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2846 (v2i32 (or (and DPR:$src2, DPR:$src1),
2847 (and DPR:$src3, (vnotd DPR:$src1)))))]>;
2848 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2849 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2850 N3RegFrm, IIC_VCNTiQ,
2851 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2853 (v4i32 (or (and QPR:$src2, QPR:$src1),
2854 (and QPR:$src3, (vnotq QPR:$src1)))))]>;
2856 // VBIF : Vector Bitwise Insert if False
2857 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2858 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2859 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2860 N3RegFrm, IIC_VBINiD,
2861 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2862 [/* For disassembly only; pattern left blank */]>;
2863 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2864 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2865 N3RegFrm, IIC_VBINiQ,
2866 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2867 [/* For disassembly only; pattern left blank */]>;
2869 // VBIT : Vector Bitwise Insert if True
2870 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2871 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2872 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2873 N3RegFrm, IIC_VBINiD,
2874 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2875 [/* For disassembly only; pattern left blank */]>;
2876 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2877 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2878 N3RegFrm, IIC_VBINiQ,
2879 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2880 [/* For disassembly only; pattern left blank */]>;
2882 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2883 // for equivalent operations with different register constraints; it just
2886 // Vector Absolute Differences.
2888 // VABD : Vector Absolute Difference
2889 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2890 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2891 "vabd", "s", int_arm_neon_vabds, 1>;
2892 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2893 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2894 "vabd", "u", int_arm_neon_vabdu, 1>;
2895 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2896 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
2897 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2898 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
2900 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2901 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
2902 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
2903 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
2904 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
2906 // VABA : Vector Absolute Difference and Accumulate
2907 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2908 "vaba", "s", int_arm_neon_vabds, add>;
2909 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2910 "vaba", "u", int_arm_neon_vabdu, add>;
2912 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2913 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
2914 "vabal", "s", int_arm_neon_vabds, zext, add>;
2915 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
2916 "vabal", "u", int_arm_neon_vabdu, zext, add>;
2918 // Vector Maximum and Minimum.
2920 // VMAX : Vector Maximum
2921 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2922 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2923 "vmax", "s", int_arm_neon_vmaxs, 1>;
2924 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2925 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2926 "vmax", "u", int_arm_neon_vmaxu, 1>;
2927 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2929 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2930 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2932 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2934 // VMIN : Vector Minimum
2935 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2936 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2937 "vmin", "s", int_arm_neon_vmins, 1>;
2938 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2939 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2940 "vmin", "u", int_arm_neon_vminu, 1>;
2941 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2943 v2f32, v2f32, int_arm_neon_vmins, 1>;
2944 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2946 v4f32, v4f32, int_arm_neon_vmins, 1>;
2948 // Vector Pairwise Operations.
2950 // VPADD : Vector Pairwise Add
2951 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2953 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2954 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2956 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2957 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2959 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2960 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2961 IIC_VBIND, "vpadd", "f32",
2962 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2964 // VPADDL : Vector Pairwise Add Long
2965 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2966 int_arm_neon_vpaddls>;
2967 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2968 int_arm_neon_vpaddlu>;
2970 // VPADAL : Vector Pairwise Add and Accumulate Long
2971 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2972 int_arm_neon_vpadals>;
2973 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2974 int_arm_neon_vpadalu>;
2976 // VPMAX : Vector Pairwise Maximum
2977 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2978 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2979 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2980 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2981 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2982 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2983 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2984 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2985 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2986 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2987 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2988 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2989 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2990 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2992 // VPMIN : Vector Pairwise Minimum
2993 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2994 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2995 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2996 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2997 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2998 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2999 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3000 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3001 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3002 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3003 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3004 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3005 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
3006 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3008 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3010 // VRECPE : Vector Reciprocal Estimate
3011 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3012 IIC_VUNAD, "vrecpe", "u32",
3013 v2i32, v2i32, int_arm_neon_vrecpe>;
3014 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3015 IIC_VUNAQ, "vrecpe", "u32",
3016 v4i32, v4i32, int_arm_neon_vrecpe>;
3017 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3018 IIC_VUNAD, "vrecpe", "f32",
3019 v2f32, v2f32, int_arm_neon_vrecpe>;
3020 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3021 IIC_VUNAQ, "vrecpe", "f32",
3022 v4f32, v4f32, int_arm_neon_vrecpe>;
3024 // VRECPS : Vector Reciprocal Step
3025 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3026 IIC_VRECSD, "vrecps", "f32",
3027 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3028 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3029 IIC_VRECSQ, "vrecps", "f32",
3030 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3032 // VRSQRTE : Vector Reciprocal Square Root Estimate
3033 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3034 IIC_VUNAD, "vrsqrte", "u32",
3035 v2i32, v2i32, int_arm_neon_vrsqrte>;
3036 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3037 IIC_VUNAQ, "vrsqrte", "u32",
3038 v4i32, v4i32, int_arm_neon_vrsqrte>;
3039 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3040 IIC_VUNAD, "vrsqrte", "f32",
3041 v2f32, v2f32, int_arm_neon_vrsqrte>;
3042 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3043 IIC_VUNAQ, "vrsqrte", "f32",
3044 v4f32, v4f32, int_arm_neon_vrsqrte>;
3046 // VRSQRTS : Vector Reciprocal Square Root Step
3047 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3048 IIC_VRECSD, "vrsqrts", "f32",
3049 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3050 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3051 IIC_VRECSQ, "vrsqrts", "f32",
3052 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3056 // VSHL : Vector Shift
3057 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
3058 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3059 "vshl", "s", int_arm_neon_vshifts, 0>;
3060 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
3061 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3062 "vshl", "u", int_arm_neon_vshiftu, 0>;
3063 // VSHL : Vector Shift Left (Immediate)
3064 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3066 // VSHR : Vector Shift Right (Immediate)
3067 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3069 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3072 // VSHLL : Vector Shift Left Long
3073 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3074 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3076 // VSHLL : Vector Shift Left Long (with maximum shift count)
3077 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3078 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3079 ValueType OpTy, SDNode OpNode>
3080 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3081 ResTy, OpTy, OpNode> {
3082 let Inst{21-16} = op21_16;
3084 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3085 v8i16, v8i8, NEONvshlli>;
3086 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3087 v4i32, v4i16, NEONvshlli>;
3088 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3089 v2i64, v2i32, NEONvshlli>;
3091 // VSHRN : Vector Shift Right and Narrow
3092 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3095 // VRSHL : Vector Rounding Shift
3096 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
3097 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3098 "vrshl", "s", int_arm_neon_vrshifts, 0>;
3099 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
3100 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3101 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
3102 // VRSHR : Vector Rounding Shift Right
3103 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3105 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3108 // VRSHRN : Vector Rounding Shift Right and Narrow
3109 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3112 // VQSHL : Vector Saturating Shift
3113 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
3114 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3115 "vqshl", "s", int_arm_neon_vqshifts, 0>;
3116 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
3117 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3118 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
3119 // VQSHL : Vector Saturating Shift Left (Immediate)
3120 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3122 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3124 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3125 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3128 // VQSHRN : Vector Saturating Shift Right and Narrow
3129 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3131 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3134 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3135 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3138 // VQRSHL : Vector Saturating Rounding Shift
3139 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
3140 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3141 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
3142 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
3143 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3144 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
3146 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3147 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3149 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3152 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3153 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3156 // VSRA : Vector Shift Right and Accumulate
3157 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3158 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3159 // VRSRA : Vector Rounding Shift Right and Accumulate
3160 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3161 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3163 // VSLI : Vector Shift Left and Insert
3164 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3165 // VSRI : Vector Shift Right and Insert
3166 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3168 // Vector Absolute and Saturating Absolute.
3170 // VABS : Vector Absolute Value
3171 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3172 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3174 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3175 IIC_VUNAD, "vabs", "f32",
3176 v2f32, v2f32, int_arm_neon_vabs>;
3177 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3178 IIC_VUNAQ, "vabs", "f32",
3179 v4f32, v4f32, int_arm_neon_vabs>;
3181 // VQABS : Vector Saturating Absolute Value
3182 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
3183 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
3184 int_arm_neon_vqabs>;
3188 def vnegd : PatFrag<(ops node:$in),
3189 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
3190 def vnegq : PatFrag<(ops node:$in),
3191 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
3193 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3194 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
3195 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3196 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
3197 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
3198 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
3199 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
3200 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
3202 // VNEG : Vector Negate (integer)
3203 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
3204 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
3205 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
3206 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
3207 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
3208 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
3210 // VNEG : Vector Negate (floating-point)
3211 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3212 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
3213 "vneg", "f32", "$dst, $src", "",
3214 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
3215 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
3216 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
3217 "vneg", "f32", "$dst, $src", "",
3218 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
3220 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
3221 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
3222 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
3223 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
3224 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
3225 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
3227 // VQNEG : Vector Saturating Negate
3228 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
3229 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
3230 int_arm_neon_vqneg>;
3232 // Vector Bit Counting Operations.
3234 // VCLS : Vector Count Leading Sign Bits
3235 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
3236 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
3238 // VCLZ : Vector Count Leading Zeros
3239 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
3240 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
3242 // VCNT : Vector Count One Bits
3243 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3244 IIC_VCNTiD, "vcnt", "8",
3245 v8i8, v8i8, int_arm_neon_vcnt>;
3246 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
3247 IIC_VCNTiQ, "vcnt", "8",
3248 v16i8, v16i8, int_arm_neon_vcnt>;
3250 // Vector Swap -- for disassembly only.
3251 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
3252 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
3253 "vswp", "$dst, $src", "", []>;
3254 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
3255 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
3256 "vswp", "$dst, $src", "", []>;
3258 // Vector Move Operations.
3260 // VMOV : Vector Move (Register)
3262 let neverHasSideEffects = 1 in {
3263 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
3264 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
3265 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
3266 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
3268 // Pseudo vector move instructions for QQ and QQQQ registers. This should
3269 // be expanded after register allocation is completed.
3270 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
3271 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
3273 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
3274 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
3275 } // neverHasSideEffects
3277 // VMOV : Vector Move (Immediate)
3279 let isReMaterializable = 1 in {
3280 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
3281 (ins nModImm:$SIMM), IIC_VMOVImm,
3282 "vmov", "i8", "$dst, $SIMM", "",
3283 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
3284 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3285 (ins nModImm:$SIMM), IIC_VMOVImm,
3286 "vmov", "i8", "$dst, $SIMM", "",
3287 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3289 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3290 (ins nModImm:$SIMM), IIC_VMOVImm,
3291 "vmov", "i16", "$dst, $SIMM", "",
3292 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
3293 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3294 (ins nModImm:$SIMM), IIC_VMOVImm,
3295 "vmov", "i16", "$dst, $SIMM", "",
3296 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
3298 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3299 (ins nModImm:$SIMM), IIC_VMOVImm,
3300 "vmov", "i32", "$dst, $SIMM", "",
3301 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
3302 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3303 (ins nModImm:$SIMM), IIC_VMOVImm,
3304 "vmov", "i32", "$dst, $SIMM", "",
3305 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
3307 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3308 (ins nModImm:$SIMM), IIC_VMOVImm,
3309 "vmov", "i64", "$dst, $SIMM", "",
3310 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3311 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3312 (ins nModImm:$SIMM), IIC_VMOVImm,
3313 "vmov", "i64", "$dst, $SIMM", "",
3314 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3315 } // isReMaterializable
3317 // VMOV : Vector Get Lane (move scalar to ARM core register)
3319 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3320 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3321 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
3322 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
3324 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3325 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3326 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
3327 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
3329 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3330 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3331 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
3332 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
3334 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3335 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3336 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
3337 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
3339 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3340 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3341 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
3342 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
3344 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3345 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3346 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3347 (DSubReg_i8_reg imm:$lane))),
3348 (SubReg_i8_lane imm:$lane))>;
3349 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3350 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3351 (DSubReg_i16_reg imm:$lane))),
3352 (SubReg_i16_lane imm:$lane))>;
3353 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3354 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3355 (DSubReg_i8_reg imm:$lane))),
3356 (SubReg_i8_lane imm:$lane))>;
3357 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3358 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3359 (DSubReg_i16_reg imm:$lane))),
3360 (SubReg_i16_lane imm:$lane))>;
3361 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3362 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3363 (DSubReg_i32_reg imm:$lane))),
3364 (SubReg_i32_lane imm:$lane))>;
3365 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3366 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3367 (SSubReg_f32_reg imm:$src2))>;
3368 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
3369 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
3370 (SSubReg_f32_reg imm:$src2))>;
3371 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
3372 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3373 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
3374 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3377 // VMOV : Vector Set Lane (move ARM core register to scalar)
3379 let Constraints = "$src1 = $dst" in {
3380 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
3381 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3382 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
3383 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
3384 GPR:$src2, imm:$lane))]>;
3385 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
3386 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3387 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
3388 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
3389 GPR:$src2, imm:$lane))]>;
3390 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
3391 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3392 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
3393 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
3394 GPR:$src2, imm:$lane))]>;
3396 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3397 (v16i8 (INSERT_SUBREG QPR:$src1,
3398 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3399 (DSubReg_i8_reg imm:$lane))),
3400 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3401 (DSubReg_i8_reg imm:$lane)))>;
3402 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3403 (v8i16 (INSERT_SUBREG QPR:$src1,
3404 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3405 (DSubReg_i16_reg imm:$lane))),
3406 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3407 (DSubReg_i16_reg imm:$lane)))>;
3408 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3409 (v4i32 (INSERT_SUBREG QPR:$src1,
3410 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3411 (DSubReg_i32_reg imm:$lane))),
3412 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3413 (DSubReg_i32_reg imm:$lane)))>;
3415 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3416 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3417 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3418 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3419 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3420 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3422 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3423 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3424 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3425 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3427 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3428 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3429 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3430 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3431 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3432 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3434 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3435 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3436 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3437 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3438 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3439 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3441 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3442 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3443 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3445 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3446 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3447 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3449 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3450 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3451 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3454 // VDUP : Vector Duplicate (from ARM core register to all elements)
3456 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3457 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3458 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3459 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3460 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3461 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3462 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3463 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3465 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3466 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3467 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3468 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3469 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3470 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3472 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3473 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3474 [(set DPR:$dst, (v2f32 (NEONvdup
3475 (f32 (bitconvert GPR:$src)))))]>;
3476 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3477 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3478 [(set QPR:$dst, (v4f32 (NEONvdup
3479 (f32 (bitconvert GPR:$src)))))]>;
3481 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3483 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3485 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3486 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3487 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3489 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3490 ValueType ResTy, ValueType OpTy>
3491 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3492 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3493 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3496 // Inst{19-16} is partially specified depending on the element size.
3498 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3499 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3500 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3501 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3502 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3503 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3504 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3505 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3507 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3508 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3509 (DSubReg_i8_reg imm:$lane))),
3510 (SubReg_i8_lane imm:$lane)))>;
3511 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3512 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3513 (DSubReg_i16_reg imm:$lane))),
3514 (SubReg_i16_lane imm:$lane)))>;
3515 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3516 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3517 (DSubReg_i32_reg imm:$lane))),
3518 (SubReg_i32_lane imm:$lane)))>;
3519 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3520 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3521 (DSubReg_i32_reg imm:$lane))),
3522 (SubReg_i32_lane imm:$lane)))>;
3524 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3525 (outs DPR:$dst), (ins SPR:$src),
3526 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3527 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3529 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3530 (outs QPR:$dst), (ins SPR:$src),
3531 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3532 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3534 // VMOVN : Vector Narrowing Move
3535 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3536 "vmovn", "i", trunc>;
3537 // VQMOVN : Vector Saturating Narrowing Move
3538 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3539 "vqmovn", "s", int_arm_neon_vqmovns>;
3540 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3541 "vqmovn", "u", int_arm_neon_vqmovnu>;
3542 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3543 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3544 // VMOVL : Vector Lengthening Move
3545 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3546 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3548 // Vector Conversions.
3550 // VCVT : Vector Convert Between Floating-Point and Integers
3551 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3552 v2i32, v2f32, fp_to_sint>;
3553 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3554 v2i32, v2f32, fp_to_uint>;
3555 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3556 v2f32, v2i32, sint_to_fp>;
3557 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3558 v2f32, v2i32, uint_to_fp>;
3560 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3561 v4i32, v4f32, fp_to_sint>;
3562 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3563 v4i32, v4f32, fp_to_uint>;
3564 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3565 v4f32, v4i32, sint_to_fp>;
3566 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3567 v4f32, v4i32, uint_to_fp>;
3569 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3570 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3571 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3572 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3573 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3574 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3575 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3576 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3577 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3579 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3580 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3581 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3582 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3583 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3584 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3585 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3586 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3590 // VREV64 : Vector Reverse elements within 64-bit doublewords
3592 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3593 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3594 (ins DPR:$src), IIC_VMOVD,
3595 OpcodeStr, Dt, "$dst, $src", "",
3596 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3597 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3598 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3599 (ins QPR:$src), IIC_VMOVD,
3600 OpcodeStr, Dt, "$dst, $src", "",
3601 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3603 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3604 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3605 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3606 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3608 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3609 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3610 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3611 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3613 // VREV32 : Vector Reverse elements within 32-bit words
3615 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3616 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3617 (ins DPR:$src), IIC_VMOVD,
3618 OpcodeStr, Dt, "$dst, $src", "",
3619 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3620 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3621 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3622 (ins QPR:$src), IIC_VMOVD,
3623 OpcodeStr, Dt, "$dst, $src", "",
3624 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3626 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3627 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3629 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3630 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3632 // VREV16 : Vector Reverse elements within 16-bit halfwords
3634 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3635 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3636 (ins DPR:$src), IIC_VMOVD,
3637 OpcodeStr, Dt, "$dst, $src", "",
3638 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3639 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3640 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3641 (ins QPR:$src), IIC_VMOVD,
3642 OpcodeStr, Dt, "$dst, $src", "",
3643 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3645 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3646 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3648 // Other Vector Shuffles.
3650 // VEXT : Vector Extract
3652 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3653 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3654 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3655 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3656 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3657 (Ty DPR:$rhs), imm:$index)))]>;
3659 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3660 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3661 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3662 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3663 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3664 (Ty QPR:$rhs), imm:$index)))]>;
3666 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3667 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3668 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3669 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3671 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3672 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3673 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3674 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3676 // VTRN : Vector Transpose
3678 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3679 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3680 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3682 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3683 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3684 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3686 // VUZP : Vector Unzip (Deinterleave)
3688 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3689 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3690 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3692 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3693 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3694 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3696 // VZIP : Vector Zip (Interleave)
3698 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3699 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3700 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3702 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3703 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3704 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3706 // Vector Table Lookup and Table Extension.
3708 // VTBL : Vector Table Lookup
3710 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3711 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3712 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3713 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3714 let hasExtraSrcRegAllocReq = 1 in {
3716 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3717 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3718 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3720 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3721 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3722 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3724 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3725 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3727 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3728 } // hasExtraSrcRegAllocReq = 1
3730 // VTBX : Vector Table Extension
3732 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3733 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3734 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3735 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3736 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3737 let hasExtraSrcRegAllocReq = 1 in {
3739 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3740 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3741 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3743 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3744 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3745 NVTBLFrm, IIC_VTBX3,
3746 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3747 "$orig = $dst", []>;
3749 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3750 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3751 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3752 "$orig = $dst", []>;
3753 } // hasExtraSrcRegAllocReq = 1
3755 //===----------------------------------------------------------------------===//
3756 // NEON instructions for single-precision FP math
3757 //===----------------------------------------------------------------------===//
3759 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3760 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3761 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3765 class N3VSPat<SDNode OpNode, NeonI Inst>
3766 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3767 (EXTRACT_SUBREG (v2f32
3768 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3770 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3774 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3775 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3776 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3778 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3780 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3784 // These need separate instructions because they must use DPR_VFP2 register
3785 // class which have SPR sub-registers.
3787 // Vector Add Operations used for single-precision FP
3788 let neverHasSideEffects = 1 in
3789 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3790 def : N3VSPat<fadd, VADDfd_sfp>;
3792 // Vector Sub Operations used for single-precision FP
3793 let neverHasSideEffects = 1 in
3794 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3795 def : N3VSPat<fsub, VSUBfd_sfp>;
3797 // Vector Multiply Operations used for single-precision FP
3798 let neverHasSideEffects = 1 in
3799 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3800 def : N3VSPat<fmul, VMULfd_sfp>;
3802 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3803 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3804 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3806 //let neverHasSideEffects = 1 in
3807 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3808 // v2f32, fmul, fadd>;
3809 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3811 //let neverHasSideEffects = 1 in
3812 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3813 // v2f32, fmul, fsub>;
3814 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3816 // Vector Absolute used for single-precision FP
3817 let neverHasSideEffects = 1 in
3818 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3819 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3820 "vabs", "f32", "$dst, $src", "", []>;
3821 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3823 // Vector Negate used for single-precision FP
3824 let neverHasSideEffects = 1 in
3825 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3826 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3827 "vneg", "f32", "$dst, $src", "", []>;
3828 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3830 // Vector Maximum used for single-precision FP
3831 let neverHasSideEffects = 1 in
3832 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3833 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3834 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3835 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3837 // Vector Minimum used for single-precision FP
3838 let neverHasSideEffects = 1 in
3839 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3840 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3841 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3842 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3844 // Vector Convert between single-precision FP and integer
3845 let neverHasSideEffects = 1 in
3846 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3847 v2i32, v2f32, fp_to_sint>;
3848 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3850 let neverHasSideEffects = 1 in
3851 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3852 v2i32, v2f32, fp_to_uint>;
3853 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3855 let neverHasSideEffects = 1 in
3856 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3857 v2f32, v2i32, sint_to_fp>;
3858 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3860 let neverHasSideEffects = 1 in
3861 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3862 v2f32, v2i32, uint_to_fp>;
3863 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3865 //===----------------------------------------------------------------------===//
3866 // Non-Instruction Patterns
3867 //===----------------------------------------------------------------------===//
3870 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3871 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3872 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3873 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3874 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3875 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3876 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3877 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3878 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3879 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3880 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3881 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3882 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3883 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3884 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3885 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3886 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3887 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3888 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3889 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3890 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3891 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3892 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3893 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3894 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3895 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3896 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3897 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3898 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3899 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3901 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3902 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3903 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3904 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3905 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3906 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3907 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3908 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3909 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3910 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3911 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3912 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3913 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3914 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3915 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3916 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3917 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3918 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3919 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3920 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3921 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3922 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3923 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3924 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3925 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3926 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3927 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3928 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3929 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3930 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;