1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvbsl : SDNode<"ARMISD::VBSL",
84 SDTypeProfile<1, 3, [SDTCisVec<0>,
87 SDTCisSameAs<0, 3>]>>;
89 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
91 // VDUPLANE can produce a quad-register result from a double-register source,
92 // so the result is not constrained to match the source.
93 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
94 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
97 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
98 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
99 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
101 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
102 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
103 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
104 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
106 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
108 SDTCisSameAs<0, 3>]>;
109 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
110 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
111 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
113 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisSameAs<1, 2>]>;
115 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
116 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
118 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
119 SDTCisSameAs<0, 2>]>;
120 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
121 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
123 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
124 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
125 unsigned EltBits = 0;
126 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
127 return (EltBits == 32 && EltVal == 0);
130 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
131 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
132 unsigned EltBits = 0;
133 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
134 return (EltBits == 8 && EltVal == 0xff);
137 //===----------------------------------------------------------------------===//
138 // NEON operand definitions
139 //===----------------------------------------------------------------------===//
141 def nModImm : Operand<i32> {
142 let PrintMethod = "printNEONModImmOperand";
145 //===----------------------------------------------------------------------===//
146 // NEON load / store instructions
147 //===----------------------------------------------------------------------===//
149 // Use VLDM to load a Q register as a D register pair.
150 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
152 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
154 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
156 // Use VSTM to store a Q register as a D register pair.
157 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
159 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
161 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
163 // Classes for VLD* pseudo-instructions with multi-register operands.
164 // These are expanded to real instructions after register allocation.
165 class VLDQPseudo<InstrItinClass itin>
166 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
167 class VLDQWBPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
169 (ins addrmode6:$addr, am6offset:$offset), itin,
171 class VLDQQPseudo<InstrItinClass itin>
172 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
173 class VLDQQWBPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
175 (ins addrmode6:$addr, am6offset:$offset), itin,
177 class VLDQQQQPseudo<InstrItinClass itin>
178 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src), itin,"">;
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers:
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
429 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
430 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
432 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
433 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
434 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
436 // VLD4 : Vector Load (multiple 4-element structures)
437 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
438 : NLdSt<0, 0b10, op11_8, op7_4,
439 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
440 (ins addrmode6:$Rn), IIC_VLD4,
441 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
443 let Inst{5-4} = Rn{5-4};
446 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
447 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
448 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
450 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
451 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
452 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
454 // ...with address register writeback:
455 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
456 : NLdSt<0, 0b10, op11_8, op7_4,
457 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
458 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
459 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
460 "$Rn.addr = $wb", []> {
461 let Inst{5-4} = Rn{5-4};
464 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
465 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
466 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
468 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
469 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
470 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
472 // ...with double-spaced registers:
473 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
474 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
475 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
477 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
478 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
480 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
481 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
482 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
484 // ...alternate versions to be allocated odd register numbers:
485 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
486 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
487 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
489 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
490 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
491 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
493 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
495 // Classes for VLD*LN pseudo-instructions with multi-register operands.
496 // These are expanded to real instructions after register allocation.
497 class VLDQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QPR:$dst),
499 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQPR:$dst),
507 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
513 class VLDQQQQLNPseudo<InstrItinClass itin>
514 : PseudoNLdSt<(outs QQQQPR:$dst),
515 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
516 itin, "$src = $dst">;
517 class VLDQQQQLNWBPseudo<InstrItinClass itin>
518 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
519 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
520 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
522 // VLD1LN : Vector Load (single element to one lane)
523 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
525 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
526 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
527 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
529 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
530 (i32 (LoadOp addrmode6:$Rn)),
534 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
535 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
536 (i32 (LoadOp addrmode6:$addr)),
540 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
541 let Inst{7-5} = lane{2-0};
543 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
544 let Inst{7-6} = lane{1-0};
547 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
548 let Inst{7} = lane{0};
553 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
554 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
555 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
557 def : Pat<(vector_insert (v2f32 DPR:$src),
558 (f32 (load addrmode6:$addr)), imm:$lane),
559 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
560 def : Pat<(vector_insert (v4f32 QPR:$src),
561 (f32 (load addrmode6:$addr)), imm:$lane),
562 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
564 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
566 // ...with address register writeback:
567 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
568 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
569 (ins addrmode6:$Rn, am6offset:$Rm,
570 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
571 "\\{$Vd[$lane]\\}, $Rn$Rm",
572 "$src = $Vd, $Rn.addr = $wb", []>;
574 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
575 let Inst{7-5} = lane{2-0};
577 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
578 let Inst{7-6} = lane{1-0};
581 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
582 let Inst{7} = lane{0};
587 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
588 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
589 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
591 // VLD2LN : Vector Load (single 2-element structure to one lane)
592 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
593 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
594 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
595 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
596 "$src1 = $Vd, $src2 = $dst2", []> {
601 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
602 let Inst{7-5} = lane{2-0};
604 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
605 let Inst{7-6} = lane{1-0};
607 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
608 let Inst{7} = lane{0};
611 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
612 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
613 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
615 // ...with double-spaced registers:
616 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
617 let Inst{7-6} = lane{1-0};
619 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
620 let Inst{7} = lane{0};
623 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
624 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
626 // ...with address register writeback:
627 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
628 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
629 (ins addrmode6:$Rn, am6offset:$Rm,
630 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
631 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
632 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
636 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
637 let Inst{7-5} = lane{2-0};
639 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
640 let Inst{7-6} = lane{1-0};
642 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
643 let Inst{7} = lane{0};
646 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
647 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
648 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
650 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
651 let Inst{7-6} = lane{1-0};
653 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
654 let Inst{7} = lane{0};
657 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
658 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
660 // VLD3LN : Vector Load (single 3-element structure to one lane)
661 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
662 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
663 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
664 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
665 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
666 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
670 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
671 let Inst{7-5} = lane{2-0};
673 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
674 let Inst{7-6} = lane{1-0};
676 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
677 let Inst{7} = lane{0};
680 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
681 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
682 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
684 // ...with double-spaced registers:
685 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
686 let Inst{7-6} = lane{1-0};
688 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
689 let Inst{7} = lane{0};
692 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
693 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
695 // ...with address register writeback:
696 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
697 : NLdStLn<1, 0b10, op11_8, op7_4,
698 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
699 (ins addrmode6:$Rn, am6offset:$Rm,
700 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
701 IIC_VLD3lnu, "vld3", Dt,
702 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
703 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
706 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
707 let Inst{7-5} = lane{2-0};
709 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
710 let Inst{7-6} = lane{1-0};
712 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
713 let Inst{7} = lane{0};
716 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
717 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
718 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
720 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
721 let Inst{7-6} = lane{1-0};
723 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
724 let Inst{7} = lane{0};
727 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
728 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
730 // VLD4LN : Vector Load (single 4-element structure to one lane)
731 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
732 : NLdStLn<1, 0b10, op11_8, op7_4,
733 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
734 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
735 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
736 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
737 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
742 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
743 let Inst{7-5} = lane{2-0};
745 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
746 let Inst{7-6} = lane{1-0};
748 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
749 let Inst{7} = lane{0};
753 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
754 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
755 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
757 // ...with double-spaced registers:
758 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
759 let Inst{7-6} = lane{1-0};
761 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
762 let Inst{7} = lane{0};
766 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
767 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
769 // ...with address register writeback:
770 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
771 : NLdStLn<1, 0b10, op11_8, op7_4,
772 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
773 (ins addrmode6:$Rn, am6offset:$Rm,
774 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
775 IIC_VLD4lnu, "vld4", Dt,
776 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
777 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
782 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
783 let Inst{7-5} = lane{2-0};
785 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
786 let Inst{7-6} = lane{1-0};
788 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
789 let Inst{7} = lane{0};
793 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
794 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
795 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
797 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
798 let Inst{7-6} = lane{1-0};
800 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
801 let Inst{7} = lane{0};
805 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
806 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
808 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
810 // VLD1DUP : Vector Load (single element to all lanes)
811 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
812 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
813 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
814 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
818 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
819 let Pattern = [(set QPR:$dst,
820 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
823 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
824 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
825 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
827 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
828 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
829 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
831 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
832 (VLD1DUPd32 addrmode6:$addr)>;
833 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
834 (VLD1DUPq32Pseudo addrmode6:$addr)>;
836 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
838 class VLD1QDUP<bits<4> op7_4, string Dt>
839 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
840 (ins addrmode6dup:$Rn), IIC_VLD1dup,
841 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
846 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
847 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
848 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
850 // ...with address register writeback:
851 class VLD1DUPWB<bits<4> op7_4, string Dt>
852 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
853 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
854 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
857 class VLD1QDUPWB<bits<4> op7_4, string Dt>
858 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
859 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
860 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
864 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
865 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
866 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
868 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
869 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
870 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
872 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
873 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
874 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
876 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
877 class VLD2DUP<bits<4> op7_4, string Dt>
878 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
879 (ins addrmode6dup:$Rn), IIC_VLD2dup,
880 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
885 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
886 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
887 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
889 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
890 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
891 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
893 // ...with double-spaced registers (not used for codegen):
894 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
895 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
896 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
898 // ...with address register writeback:
899 class VLD2DUPWB<bits<4> op7_4, string Dt>
900 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
901 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
902 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
906 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
907 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
908 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
910 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
911 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
912 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
914 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
915 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
916 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
918 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
919 class VLD3DUP<bits<4> op7_4, string Dt>
920 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
921 (ins addrmode6dup:$Rn), IIC_VLD3dup,
922 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
927 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
928 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
929 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
931 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
932 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
933 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
935 // ...with double-spaced registers (not used for codegen):
936 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
937 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
938 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
940 // ...with address register writeback:
941 class VLD3DUPWB<bits<4> op7_4, string Dt>
942 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
943 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
944 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
945 "$Rn.addr = $wb", []> {
949 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
950 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
951 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
953 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
954 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
955 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
957 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
958 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
959 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
961 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
962 class VLD4DUP<bits<4> op7_4, string Dt>
963 : NLdSt<1, 0b10, 0b1111, op7_4,
964 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
965 (ins addrmode6dup:$Rn), IIC_VLD4dup,
966 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
971 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
972 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
973 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
975 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
976 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
977 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
979 // ...with double-spaced registers (not used for codegen):
980 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
981 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
982 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
984 // ...with address register writeback:
985 class VLD4DUPWB<bits<4> op7_4, string Dt>
986 : NLdSt<1, 0b10, 0b1111, op7_4,
987 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
988 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
989 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
990 "$Rn.addr = $wb", []> {
994 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
995 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
996 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
998 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
999 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1000 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1002 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1003 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1004 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1006 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1008 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1010 // Classes for VST* pseudo-instructions with multi-register operands.
1011 // These are expanded to real instructions after register allocation.
1012 class VSTQPseudo<InstrItinClass itin>
1013 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1014 class VSTQWBPseudo<InstrItinClass itin>
1015 : PseudoNLdSt<(outs GPR:$wb),
1016 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1017 "$addr.addr = $wb">;
1018 class VSTQQPseudo<InstrItinClass itin>
1019 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1020 class VSTQQWBPseudo<InstrItinClass itin>
1021 : PseudoNLdSt<(outs GPR:$wb),
1022 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1023 "$addr.addr = $wb">;
1024 class VSTQQQQPseudo<InstrItinClass itin>
1025 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1026 class VSTQQQQWBPseudo<InstrItinClass itin>
1027 : PseudoNLdSt<(outs GPR:$wb),
1028 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1029 "$addr.addr = $wb">;
1031 // VST1 : Vector Store (multiple single elements)
1032 class VST1D<bits<4> op7_4, string Dt>
1033 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1034 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1036 let Inst{4} = Rn{4};
1038 class VST1Q<bits<4> op7_4, string Dt>
1039 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1040 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1041 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1043 let Inst{5-4} = Rn{5-4};
1046 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1047 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1048 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1049 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1051 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1052 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1053 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1054 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1056 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1057 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1058 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1059 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1061 // ...with address register writeback:
1062 class VST1DWB<bits<4> op7_4, string Dt>
1063 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1064 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1065 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1066 let Inst{4} = Rn{4};
1068 class VST1QWB<bits<4> op7_4, string Dt>
1069 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1070 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1071 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1072 "$Rn.addr = $wb", []> {
1073 let Inst{5-4} = Rn{5-4};
1076 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1077 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1078 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1079 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1081 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1082 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1083 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1084 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1086 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1087 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1088 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1089 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1091 // ...with 3 registers (some of these are only for the disassembler):
1092 class VST1D3<bits<4> op7_4, string Dt>
1093 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1094 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1095 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1097 let Inst{4} = Rn{4};
1099 class VST1D3WB<bits<4> op7_4, string Dt>
1100 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1101 (ins addrmode6:$Rn, am6offset:$Rm,
1102 DPR:$Vd, DPR:$src2, DPR:$src3),
1103 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1104 "$Rn.addr = $wb", []> {
1105 let Inst{4} = Rn{4};
1108 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1109 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1110 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1111 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1113 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1114 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1115 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1116 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1118 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1119 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1121 // ...with 4 registers (some of these are only for the disassembler):
1122 class VST1D4<bits<4> op7_4, string Dt>
1123 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1124 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1125 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1128 let Inst{5-4} = Rn{5-4};
1130 class VST1D4WB<bits<4> op7_4, string Dt>
1131 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1132 (ins addrmode6:$Rn, am6offset:$Rm,
1133 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1134 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1135 "$Rn.addr = $wb", []> {
1136 let Inst{5-4} = Rn{5-4};
1139 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1140 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1141 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1142 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1144 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1145 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1146 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1147 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1149 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1150 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1152 // VST2 : Vector Store (multiple 2-element structures)
1153 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1154 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1155 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1156 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1158 let Inst{5-4} = Rn{5-4};
1160 class VST2Q<bits<4> op7_4, string Dt>
1161 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1162 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1163 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1166 let Inst{5-4} = Rn{5-4};
1169 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1170 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1171 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1173 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1174 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1175 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1177 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1178 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1179 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1181 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1182 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1183 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1185 // ...with address register writeback:
1186 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1187 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1188 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1189 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1190 "$Rn.addr = $wb", []> {
1191 let Inst{5-4} = Rn{5-4};
1193 class VST2QWB<bits<4> op7_4, string Dt>
1194 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1195 (ins addrmode6:$Rn, am6offset:$Rm,
1196 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1197 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1198 "$Rn.addr = $wb", []> {
1199 let Inst{5-4} = Rn{5-4};
1202 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1203 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1204 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1206 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1207 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1208 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1210 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1211 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1212 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1214 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1215 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1216 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1218 // ...with double-spaced registers (for disassembly only):
1219 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1220 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1221 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1222 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1223 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1224 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1226 // VST3 : Vector Store (multiple 3-element structures)
1227 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1228 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1229 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1230 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1232 let Inst{4} = Rn{4};
1235 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1236 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1237 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1239 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1240 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1241 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1243 // ...with address register writeback:
1244 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1245 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1246 (ins addrmode6:$Rn, am6offset:$Rm,
1247 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1248 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1249 "$Rn.addr = $wb", []> {
1250 let Inst{4} = Rn{4};
1253 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1254 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1255 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1257 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1258 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1259 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1261 // ...with double-spaced registers:
1262 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1263 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1264 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1265 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1266 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1267 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1269 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1270 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1271 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1273 // ...alternate versions to be allocated odd register numbers:
1274 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1275 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1276 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1278 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1279 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1280 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1282 // VST4 : Vector Store (multiple 4-element structures)
1283 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1284 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1285 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1286 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1289 let Inst{5-4} = Rn{5-4};
1292 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1293 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1294 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1296 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1297 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1298 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1300 // ...with address register writeback:
1301 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1302 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1303 (ins addrmode6:$Rn, am6offset:$Rm,
1304 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1305 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1306 "$Rn.addr = $wb", []> {
1307 let Inst{5-4} = Rn{5-4};
1310 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1311 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1312 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1314 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1315 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1316 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1318 // ...with double-spaced registers:
1319 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1320 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1321 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1322 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1323 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1324 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1326 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1327 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1328 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1330 // ...alternate versions to be allocated odd register numbers:
1331 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1332 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1333 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1335 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1336 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1337 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1339 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1341 // Classes for VST*LN pseudo-instructions with multi-register operands.
1342 // These are expanded to real instructions after register allocation.
1343 class VSTQLNPseudo<InstrItinClass itin>
1344 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1346 class VSTQLNWBPseudo<InstrItinClass itin>
1347 : PseudoNLdSt<(outs GPR:$wb),
1348 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1349 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1350 class VSTQQLNPseudo<InstrItinClass itin>
1351 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1353 class VSTQQLNWBPseudo<InstrItinClass itin>
1354 : PseudoNLdSt<(outs GPR:$wb),
1355 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1356 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1357 class VSTQQQQLNPseudo<InstrItinClass itin>
1358 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1360 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1361 : PseudoNLdSt<(outs GPR:$wb),
1362 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1363 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1365 // VST1LN : Vector Store (single element from one lane)
1366 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1367 PatFrag StoreOp, SDNode ExtractOp>
1368 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1369 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1370 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1371 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1374 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1375 : VSTQLNPseudo<IIC_VST1ln> {
1376 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1380 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1382 let Inst{7-5} = lane{2-0};
1384 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1386 let Inst{7-6} = lane{1-0};
1387 let Inst{4} = Rn{5};
1389 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1390 let Inst{7} = lane{0};
1391 let Inst{5-4} = Rn{5-4};
1394 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1395 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1396 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1398 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1399 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1400 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1401 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1403 // ...with address register writeback:
1404 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1405 PatFrag StoreOp, SDNode ExtractOp>
1406 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1407 (ins addrmode6:$Rn, am6offset:$Rm,
1408 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1409 "\\{$Vd[$lane]\\}, $Rn$Rm",
1411 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1412 addrmode6:$Rn, am6offset:$Rm))]>;
1413 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1414 : VSTQLNWBPseudo<IIC_VST1lnu> {
1415 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1416 addrmode6:$addr, am6offset:$offset))];
1419 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1421 let Inst{7-5} = lane{2-0};
1423 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1425 let Inst{7-6} = lane{1-0};
1426 let Inst{4} = Rn{5};
1428 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1430 let Inst{7} = lane{0};
1431 let Inst{5-4} = Rn{5-4};
1434 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1435 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1436 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1438 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1440 // VST2LN : Vector Store (single 2-element structure from one lane)
1441 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1442 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1443 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1444 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1447 let Inst{4} = Rn{4};
1450 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1451 let Inst{7-5} = lane{2-0};
1453 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1454 let Inst{7-6} = lane{1-0};
1456 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1457 let Inst{7} = lane{0};
1460 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1461 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1462 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1464 // ...with double-spaced registers:
1465 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1466 let Inst{7-6} = lane{1-0};
1467 let Inst{4} = Rn{4};
1469 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1470 let Inst{7} = lane{0};
1471 let Inst{4} = Rn{4};
1474 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1475 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1477 // ...with address register writeback:
1478 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1479 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1480 (ins addrmode6:$addr, am6offset:$offset,
1481 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1482 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1483 "$addr.addr = $wb", []> {
1484 let Inst{4} = Rn{4};
1487 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1488 let Inst{7-5} = lane{2-0};
1490 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1491 let Inst{7-6} = lane{1-0};
1493 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1494 let Inst{7} = lane{0};
1497 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1498 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1499 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1501 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1502 let Inst{7-6} = lane{1-0};
1504 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1505 let Inst{7} = lane{0};
1508 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1509 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1511 // VST3LN : Vector Store (single 3-element structure from one lane)
1512 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1513 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1514 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1515 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1516 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1520 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1521 let Inst{7-5} = lane{2-0};
1523 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1524 let Inst{7-6} = lane{1-0};
1526 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1527 let Inst{7} = lane{0};
1530 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1531 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1532 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1534 // ...with double-spaced registers:
1535 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1536 let Inst{7-6} = lane{1-0};
1538 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1539 let Inst{7} = lane{0};
1542 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1543 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1545 // ...with address register writeback:
1546 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1547 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1548 (ins addrmode6:$Rn, am6offset:$Rm,
1549 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1550 IIC_VST3lnu, "vst3", Dt,
1551 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1552 "$Rn.addr = $wb", []>;
1554 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1555 let Inst{7-5} = lane{2-0};
1557 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1558 let Inst{7-6} = lane{1-0};
1560 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1561 let Inst{7} = lane{0};
1564 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1565 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1566 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1568 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1569 let Inst{7-6} = lane{1-0};
1571 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1572 let Inst{7} = lane{0};
1575 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1576 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1578 // VST4LN : Vector Store (single 4-element structure from one lane)
1579 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1580 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1581 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1582 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1583 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1586 let Inst{4} = Rn{4};
1589 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1590 let Inst{7-5} = lane{2-0};
1592 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1593 let Inst{7-6} = lane{1-0};
1595 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1596 let Inst{7} = lane{0};
1597 let Inst{5} = Rn{5};
1600 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1601 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1602 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1604 // ...with double-spaced registers:
1605 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1606 let Inst{7-6} = lane{1-0};
1608 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1609 let Inst{7} = lane{0};
1610 let Inst{5} = Rn{5};
1613 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1614 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1616 // ...with address register writeback:
1617 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1618 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1619 (ins addrmode6:$Rn, am6offset:$Rm,
1620 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1621 IIC_VST4lnu, "vst4", Dt,
1622 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1623 "$Rn.addr = $wb", []> {
1624 let Inst{4} = Rn{4};
1627 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1628 let Inst{7-5} = lane{2-0};
1630 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1631 let Inst{7-6} = lane{1-0};
1633 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1634 let Inst{7} = lane{0};
1635 let Inst{5} = Rn{5};
1638 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1639 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1640 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1642 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1643 let Inst{7-6} = lane{1-0};
1645 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1646 let Inst{7} = lane{0};
1647 let Inst{5} = Rn{5};
1650 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1651 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1653 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1656 //===----------------------------------------------------------------------===//
1657 // NEON pattern fragments
1658 //===----------------------------------------------------------------------===//
1660 // Extract D sub-registers of Q registers.
1661 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1662 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1663 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1665 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1666 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1667 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1669 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1670 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1671 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1673 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1674 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1675 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1678 // Extract S sub-registers of Q/D registers.
1679 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1680 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1681 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1684 // Translate lane numbers from Q registers to D subregs.
1685 def SubReg_i8_lane : SDNodeXForm<imm, [{
1686 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1688 def SubReg_i16_lane : SDNodeXForm<imm, [{
1689 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1691 def SubReg_i32_lane : SDNodeXForm<imm, [{
1692 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1695 //===----------------------------------------------------------------------===//
1696 // Instruction Classes
1697 //===----------------------------------------------------------------------===//
1699 // Basic 2-register operations: double- and quad-register.
1700 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1701 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1702 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1703 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1704 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1705 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1706 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1707 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1708 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1709 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1710 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1711 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1713 // Basic 2-register intrinsics, both double- and quad-register.
1714 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1715 bits<2> op17_16, bits<5> op11_7, bit op4,
1716 InstrItinClass itin, string OpcodeStr, string Dt,
1717 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1718 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1719 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1720 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1721 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1722 bits<2> op17_16, bits<5> op11_7, bit op4,
1723 InstrItinClass itin, string OpcodeStr, string Dt,
1724 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1725 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1726 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1727 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1729 // Narrow 2-register operations.
1730 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1731 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1732 InstrItinClass itin, string OpcodeStr, string Dt,
1733 ValueType TyD, ValueType TyQ, SDNode OpNode>
1734 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1735 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1736 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1738 // Narrow 2-register intrinsics.
1739 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1740 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1741 InstrItinClass itin, string OpcodeStr, string Dt,
1742 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1743 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1744 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1745 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1747 // Long 2-register operations (currently only used for VMOVL).
1748 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1749 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1750 InstrItinClass itin, string OpcodeStr, string Dt,
1751 ValueType TyQ, ValueType TyD, SDNode OpNode>
1752 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1753 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1754 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1756 // Long 2-register intrinsics.
1757 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1758 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1759 InstrItinClass itin, string OpcodeStr, string Dt,
1760 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1761 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1762 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1763 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1765 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1766 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1767 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1768 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1769 OpcodeStr, Dt, "$Vd, $Vm",
1770 "$src1 = $Vd, $src2 = $Vm", []>;
1771 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1772 InstrItinClass itin, string OpcodeStr, string Dt>
1773 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1774 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1775 "$src1 = $Vd, $src2 = $Vm", []>;
1777 // Basic 3-register operations: double- and quad-register.
1778 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1779 InstrItinClass itin, string OpcodeStr, string Dt,
1780 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1781 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1782 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1783 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1784 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1785 let isCommutable = Commutable;
1787 // Same as N3VD but no data type.
1788 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1789 InstrItinClass itin, string OpcodeStr,
1790 ValueType ResTy, ValueType OpTy,
1791 SDNode OpNode, bit Commutable>
1792 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1793 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1794 OpcodeStr, "$Vd, $Vn, $Vm", "",
1795 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1796 let isCommutable = Commutable;
1799 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1800 InstrItinClass itin, string OpcodeStr, string Dt,
1801 ValueType Ty, SDNode ShOp>
1802 : N3V<0, 1, op21_20, op11_8, 1, 0,
1803 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1804 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1806 (Ty (ShOp (Ty DPR:$Vn),
1807 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1808 let isCommutable = 0;
1810 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1811 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1812 : N3V<0, 1, op21_20, op11_8, 1, 0,
1813 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1814 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1816 (Ty (ShOp (Ty DPR:$Vn),
1817 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1818 let isCommutable = 0;
1821 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1822 InstrItinClass itin, string OpcodeStr, string Dt,
1823 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1824 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1825 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1826 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1827 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1828 let isCommutable = Commutable;
1830 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1831 InstrItinClass itin, string OpcodeStr,
1832 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1833 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1834 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1835 OpcodeStr, "$Vd, $Vn, $Vm", "",
1836 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1837 let isCommutable = Commutable;
1839 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1840 InstrItinClass itin, string OpcodeStr, string Dt,
1841 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1842 : N3V<1, 1, op21_20, op11_8, 1, 0,
1843 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1844 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1845 [(set (ResTy QPR:$Vd),
1846 (ResTy (ShOp (ResTy QPR:$Vn),
1847 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1849 let isCommutable = 0;
1851 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1852 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1853 : N3V<1, 1, op21_20, op11_8, 1, 0,
1854 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1855 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1856 [(set (ResTy QPR:$Vd),
1857 (ResTy (ShOp (ResTy QPR:$Vn),
1858 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1860 let isCommutable = 0;
1863 // Basic 3-register intrinsics, both double- and quad-register.
1864 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1865 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1866 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1867 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1868 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1869 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1870 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1871 let isCommutable = Commutable;
1873 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1874 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1875 : N3V<0, 1, op21_20, op11_8, 1, 0,
1876 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1877 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1879 (Ty (IntOp (Ty DPR:$Vn),
1880 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1882 let isCommutable = 0;
1884 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1885 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1886 : N3V<0, 1, op21_20, op11_8, 1, 0,
1887 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1888 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1890 (Ty (IntOp (Ty DPR:$Vn),
1891 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1892 let isCommutable = 0;
1894 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1895 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1896 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1897 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1898 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1899 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1900 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1901 let isCommutable = 0;
1904 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1905 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1906 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1907 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1908 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1909 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1910 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1911 let isCommutable = Commutable;
1913 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1914 string OpcodeStr, string Dt,
1915 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1916 : N3V<1, 1, op21_20, op11_8, 1, 0,
1917 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1918 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1919 [(set (ResTy QPR:$Vd),
1920 (ResTy (IntOp (ResTy QPR:$Vn),
1921 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1923 let isCommutable = 0;
1925 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1926 string OpcodeStr, string Dt,
1927 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1928 : N3V<1, 1, op21_20, op11_8, 1, 0,
1929 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1930 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1931 [(set (ResTy QPR:$Vd),
1932 (ResTy (IntOp (ResTy QPR:$Vn),
1933 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1935 let isCommutable = 0;
1937 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1938 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1939 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1940 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1941 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1942 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1943 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1944 let isCommutable = 0;
1947 // Multiply-Add/Sub operations: double- and quad-register.
1948 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1949 InstrItinClass itin, string OpcodeStr, string Dt,
1950 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1951 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1952 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1953 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1954 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1955 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1957 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1958 string OpcodeStr, string Dt,
1959 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1960 : N3V<0, 1, op21_20, op11_8, 1, 0,
1962 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1964 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1966 (Ty (ShOp (Ty DPR:$src1),
1968 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1970 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1971 string OpcodeStr, string Dt,
1972 ValueType Ty, SDNode MulOp, SDNode ShOp>
1973 : N3V<0, 1, op21_20, op11_8, 1, 0,
1975 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1977 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1979 (Ty (ShOp (Ty DPR:$src1),
1981 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1984 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1985 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1986 SDPatternOperator MulOp, SDPatternOperator OpNode>
1987 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1988 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1989 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1990 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1991 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1992 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1993 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1994 SDPatternOperator MulOp, SDPatternOperator ShOp>
1995 : N3V<1, 1, op21_20, op11_8, 1, 0,
1997 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1999 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2000 [(set (ResTy QPR:$Vd),
2001 (ResTy (ShOp (ResTy QPR:$src1),
2002 (ResTy (MulOp QPR:$Vn,
2003 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2005 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2006 string OpcodeStr, string Dt,
2007 ValueType ResTy, ValueType OpTy,
2008 SDNode MulOp, SDNode ShOp>
2009 : N3V<1, 1, op21_20, op11_8, 1, 0,
2011 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2013 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2014 [(set (ResTy QPR:$Vd),
2015 (ResTy (ShOp (ResTy QPR:$src1),
2016 (ResTy (MulOp QPR:$Vn,
2017 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2020 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2021 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2022 InstrItinClass itin, string OpcodeStr, string Dt,
2023 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2024 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2025 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2026 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2027 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2028 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2029 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2030 InstrItinClass itin, string OpcodeStr, string Dt,
2031 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2032 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2033 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2034 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2035 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2036 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2038 // Neon 3-argument intrinsics, both double- and quad-register.
2039 // The destination register is also used as the first source operand register.
2040 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2041 InstrItinClass itin, string OpcodeStr, string Dt,
2042 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2043 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2044 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2045 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2046 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2047 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2048 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2049 InstrItinClass itin, string OpcodeStr, string Dt,
2050 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2051 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2052 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2053 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2054 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2055 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2057 // Long Multiply-Add/Sub operations.
2058 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2059 InstrItinClass itin, string OpcodeStr, string Dt,
2060 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2061 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2062 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2063 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2064 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2065 (TyQ (MulOp (TyD DPR:$Vn),
2066 (TyD DPR:$Vm)))))]>;
2067 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2068 InstrItinClass itin, string OpcodeStr, string Dt,
2069 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2070 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2071 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2073 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2075 (OpNode (TyQ QPR:$src1),
2076 (TyQ (MulOp (TyD DPR:$Vn),
2077 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2079 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2080 InstrItinClass itin, string OpcodeStr, string Dt,
2081 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2082 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2083 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2085 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2087 (OpNode (TyQ QPR:$src1),
2088 (TyQ (MulOp (TyD DPR:$Vn),
2089 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2092 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2093 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2094 InstrItinClass itin, string OpcodeStr, string Dt,
2095 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2097 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2098 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2099 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2100 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2101 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2102 (TyD DPR:$Vm)))))))]>;
2104 // Neon Long 3-argument intrinsic. The destination register is
2105 // a quad-register and is also used as the first source operand register.
2106 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2107 InstrItinClass itin, string OpcodeStr, string Dt,
2108 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2109 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2110 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2111 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2113 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2114 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2115 string OpcodeStr, string Dt,
2116 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2117 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2119 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2121 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2122 [(set (ResTy QPR:$Vd),
2123 (ResTy (IntOp (ResTy QPR:$src1),
2125 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2127 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2128 InstrItinClass itin, string OpcodeStr, string Dt,
2129 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2130 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2132 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2134 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2135 [(set (ResTy QPR:$Vd),
2136 (ResTy (IntOp (ResTy QPR:$src1),
2138 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2141 // Narrowing 3-register intrinsics.
2142 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2143 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2144 Intrinsic IntOp, bit Commutable>
2145 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2146 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2147 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2148 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2149 let isCommutable = Commutable;
2152 // Long 3-register operations.
2153 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2154 InstrItinClass itin, string OpcodeStr, string Dt,
2155 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2156 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2157 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2158 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2159 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2160 let isCommutable = Commutable;
2162 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2163 InstrItinClass itin, string OpcodeStr, string Dt,
2164 ValueType TyQ, ValueType TyD, SDNode OpNode>
2165 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2166 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2167 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2169 (TyQ (OpNode (TyD DPR:$Vn),
2170 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2171 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2172 InstrItinClass itin, string OpcodeStr, string Dt,
2173 ValueType TyQ, ValueType TyD, SDNode OpNode>
2174 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2175 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2176 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2178 (TyQ (OpNode (TyD DPR:$Vn),
2179 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2181 // Long 3-register operations with explicitly extended operands.
2182 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2183 InstrItinClass itin, string OpcodeStr, string Dt,
2184 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2186 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2187 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2188 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2189 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2190 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2191 let isCommutable = Commutable;
2194 // Long 3-register intrinsics with explicit extend (VABDL).
2195 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2196 InstrItinClass itin, string OpcodeStr, string Dt,
2197 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2199 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2200 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2201 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2202 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2203 (TyD DPR:$Vm))))))]> {
2204 let isCommutable = Commutable;
2207 // Long 3-register intrinsics.
2208 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2209 InstrItinClass itin, string OpcodeStr, string Dt,
2210 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2211 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2212 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2213 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2214 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2215 let isCommutable = Commutable;
2217 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2218 string OpcodeStr, string Dt,
2219 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2220 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2221 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2222 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2223 [(set (ResTy QPR:$Vd),
2224 (ResTy (IntOp (OpTy DPR:$Vn),
2225 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2227 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2228 InstrItinClass itin, string OpcodeStr, string Dt,
2229 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2230 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2231 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2232 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2233 [(set (ResTy QPR:$Vd),
2234 (ResTy (IntOp (OpTy DPR:$Vn),
2235 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2238 // Wide 3-register operations.
2239 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2240 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2241 SDNode OpNode, SDNode ExtOp, bit Commutable>
2242 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2243 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2244 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2245 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2246 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2247 let isCommutable = Commutable;
2250 // Pairwise long 2-register intrinsics, both double- and quad-register.
2251 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2252 bits<2> op17_16, bits<5> op11_7, bit op4,
2253 string OpcodeStr, string Dt,
2254 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2255 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2256 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2257 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2258 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2259 bits<2> op17_16, bits<5> op11_7, bit op4,
2260 string OpcodeStr, string Dt,
2261 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2262 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2263 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2264 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2266 // Pairwise long 2-register accumulate intrinsics,
2267 // both double- and quad-register.
2268 // The destination register is also used as the first source operand register.
2269 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2270 bits<2> op17_16, bits<5> op11_7, bit op4,
2271 string OpcodeStr, string Dt,
2272 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2273 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2274 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2275 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2276 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2277 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2278 bits<2> op17_16, bits<5> op11_7, bit op4,
2279 string OpcodeStr, string Dt,
2280 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2281 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2282 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2283 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2284 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2286 // Shift by immediate,
2287 // both double- and quad-register.
2288 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2289 Format f, InstrItinClass itin, Operand ImmTy,
2290 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2291 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2292 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2293 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2294 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2295 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2296 Format f, InstrItinClass itin, Operand ImmTy,
2297 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2298 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2299 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2300 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2301 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2303 // Long shift by immediate.
2304 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2305 string OpcodeStr, string Dt,
2306 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2307 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2308 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2309 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2310 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2311 (i32 imm:$SIMM))))]>;
2313 // Narrow shift by immediate.
2314 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2315 InstrItinClass itin, string OpcodeStr, string Dt,
2316 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2317 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2318 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2319 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2320 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2321 (i32 imm:$SIMM))))]>;
2323 // Shift right by immediate and accumulate,
2324 // both double- and quad-register.
2325 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2326 Operand ImmTy, string OpcodeStr, string Dt,
2327 ValueType Ty, SDNode ShOp>
2328 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2329 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2330 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2331 [(set DPR:$Vd, (Ty (add DPR:$src1,
2332 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2333 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2334 Operand ImmTy, string OpcodeStr, string Dt,
2335 ValueType Ty, SDNode ShOp>
2336 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2337 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2338 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2339 [(set QPR:$Vd, (Ty (add QPR:$src1,
2340 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2342 // Shift by immediate and insert,
2343 // both double- and quad-register.
2344 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2345 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2346 ValueType Ty,SDNode ShOp>
2347 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2348 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2349 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2350 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2351 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2352 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2353 ValueType Ty,SDNode ShOp>
2354 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2355 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2356 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2357 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2359 // Convert, with fractional bits immediate,
2360 // both double- and quad-register.
2361 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2362 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2364 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2365 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2366 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2367 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2368 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2369 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2371 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2372 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2373 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2374 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2376 //===----------------------------------------------------------------------===//
2378 //===----------------------------------------------------------------------===//
2380 // Abbreviations used in multiclass suffixes:
2381 // Q = quarter int (8 bit) elements
2382 // H = half int (16 bit) elements
2383 // S = single int (32 bit) elements
2384 // D = double int (64 bit) elements
2386 // Neon 2-register vector operations and intrinsics.
2388 // Neon 2-register comparisons.
2389 // source operand element sizes of 8, 16 and 32 bits:
2390 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2391 bits<5> op11_7, bit op4, string opc, string Dt,
2392 string asm, SDNode OpNode> {
2393 // 64-bit vector types.
2394 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2395 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2396 opc, !strconcat(Dt, "8"), asm, "",
2397 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2398 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2399 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2400 opc, !strconcat(Dt, "16"), asm, "",
2401 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2402 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2403 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2404 opc, !strconcat(Dt, "32"), asm, "",
2405 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2406 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2407 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2408 opc, "f32", asm, "",
2409 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2410 let Inst{10} = 1; // overwrite F = 1
2413 // 128-bit vector types.
2414 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2415 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2416 opc, !strconcat(Dt, "8"), asm, "",
2417 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2418 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2419 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2420 opc, !strconcat(Dt, "16"), asm, "",
2421 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2422 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2423 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2424 opc, !strconcat(Dt, "32"), asm, "",
2425 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2426 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2427 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2428 opc, "f32", asm, "",
2429 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2430 let Inst{10} = 1; // overwrite F = 1
2435 // Neon 2-register vector intrinsics,
2436 // element sizes of 8, 16 and 32 bits:
2437 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2438 bits<5> op11_7, bit op4,
2439 InstrItinClass itinD, InstrItinClass itinQ,
2440 string OpcodeStr, string Dt, Intrinsic IntOp> {
2441 // 64-bit vector types.
2442 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2443 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2444 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2445 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2446 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2447 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2449 // 128-bit vector types.
2450 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2451 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2452 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2453 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2454 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2455 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2459 // Neon Narrowing 2-register vector operations,
2460 // source operand element sizes of 16, 32 and 64 bits:
2461 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2462 bits<5> op11_7, bit op6, bit op4,
2463 InstrItinClass itin, string OpcodeStr, string Dt,
2465 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2466 itin, OpcodeStr, !strconcat(Dt, "16"),
2467 v8i8, v8i16, OpNode>;
2468 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2469 itin, OpcodeStr, !strconcat(Dt, "32"),
2470 v4i16, v4i32, OpNode>;
2471 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2472 itin, OpcodeStr, !strconcat(Dt, "64"),
2473 v2i32, v2i64, OpNode>;
2476 // Neon Narrowing 2-register vector intrinsics,
2477 // source operand element sizes of 16, 32 and 64 bits:
2478 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2479 bits<5> op11_7, bit op6, bit op4,
2480 InstrItinClass itin, string OpcodeStr, string Dt,
2482 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2483 itin, OpcodeStr, !strconcat(Dt, "16"),
2484 v8i8, v8i16, IntOp>;
2485 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2486 itin, OpcodeStr, !strconcat(Dt, "32"),
2487 v4i16, v4i32, IntOp>;
2488 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2489 itin, OpcodeStr, !strconcat(Dt, "64"),
2490 v2i32, v2i64, IntOp>;
2494 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2495 // source operand element sizes of 16, 32 and 64 bits:
2496 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2497 string OpcodeStr, string Dt, SDNode OpNode> {
2498 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2499 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2500 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2501 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2502 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2503 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2507 // Neon 3-register vector operations.
2509 // First with only element sizes of 8, 16 and 32 bits:
2510 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2511 InstrItinClass itinD16, InstrItinClass itinD32,
2512 InstrItinClass itinQ16, InstrItinClass itinQ32,
2513 string OpcodeStr, string Dt,
2514 SDNode OpNode, bit Commutable = 0> {
2515 // 64-bit vector types.
2516 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2517 OpcodeStr, !strconcat(Dt, "8"),
2518 v8i8, v8i8, OpNode, Commutable>;
2519 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2520 OpcodeStr, !strconcat(Dt, "16"),
2521 v4i16, v4i16, OpNode, Commutable>;
2522 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2523 OpcodeStr, !strconcat(Dt, "32"),
2524 v2i32, v2i32, OpNode, Commutable>;
2526 // 128-bit vector types.
2527 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2528 OpcodeStr, !strconcat(Dt, "8"),
2529 v16i8, v16i8, OpNode, Commutable>;
2530 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2531 OpcodeStr, !strconcat(Dt, "16"),
2532 v8i16, v8i16, OpNode, Commutable>;
2533 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2534 OpcodeStr, !strconcat(Dt, "32"),
2535 v4i32, v4i32, OpNode, Commutable>;
2538 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2539 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2541 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2543 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2544 v8i16, v4i16, ShOp>;
2545 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2546 v4i32, v2i32, ShOp>;
2549 // ....then also with element size 64 bits:
2550 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2551 InstrItinClass itinD, InstrItinClass itinQ,
2552 string OpcodeStr, string Dt,
2553 SDNode OpNode, bit Commutable = 0>
2554 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2555 OpcodeStr, Dt, OpNode, Commutable> {
2556 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2557 OpcodeStr, !strconcat(Dt, "64"),
2558 v1i64, v1i64, OpNode, Commutable>;
2559 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2560 OpcodeStr, !strconcat(Dt, "64"),
2561 v2i64, v2i64, OpNode, Commutable>;
2565 // Neon 3-register vector intrinsics.
2567 // First with only element sizes of 16 and 32 bits:
2568 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2569 InstrItinClass itinD16, InstrItinClass itinD32,
2570 InstrItinClass itinQ16, InstrItinClass itinQ32,
2571 string OpcodeStr, string Dt,
2572 Intrinsic IntOp, bit Commutable = 0> {
2573 // 64-bit vector types.
2574 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2575 OpcodeStr, !strconcat(Dt, "16"),
2576 v4i16, v4i16, IntOp, Commutable>;
2577 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2578 OpcodeStr, !strconcat(Dt, "32"),
2579 v2i32, v2i32, IntOp, Commutable>;
2581 // 128-bit vector types.
2582 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2583 OpcodeStr, !strconcat(Dt, "16"),
2584 v8i16, v8i16, IntOp, Commutable>;
2585 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2586 OpcodeStr, !strconcat(Dt, "32"),
2587 v4i32, v4i32, IntOp, Commutable>;
2589 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2590 InstrItinClass itinD16, InstrItinClass itinD32,
2591 InstrItinClass itinQ16, InstrItinClass itinQ32,
2592 string OpcodeStr, string Dt,
2594 // 64-bit vector types.
2595 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2596 OpcodeStr, !strconcat(Dt, "16"),
2597 v4i16, v4i16, IntOp>;
2598 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2599 OpcodeStr, !strconcat(Dt, "32"),
2600 v2i32, v2i32, IntOp>;
2602 // 128-bit vector types.
2603 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2604 OpcodeStr, !strconcat(Dt, "16"),
2605 v8i16, v8i16, IntOp>;
2606 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2607 OpcodeStr, !strconcat(Dt, "32"),
2608 v4i32, v4i32, IntOp>;
2611 multiclass N3VIntSL_HS<bits<4> op11_8,
2612 InstrItinClass itinD16, InstrItinClass itinD32,
2613 InstrItinClass itinQ16, InstrItinClass itinQ32,
2614 string OpcodeStr, string Dt, Intrinsic IntOp> {
2615 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2616 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2617 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2618 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2619 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2620 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2621 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2622 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2625 // ....then also with element size of 8 bits:
2626 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2627 InstrItinClass itinD16, InstrItinClass itinD32,
2628 InstrItinClass itinQ16, InstrItinClass itinQ32,
2629 string OpcodeStr, string Dt,
2630 Intrinsic IntOp, bit Commutable = 0>
2631 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2632 OpcodeStr, Dt, IntOp, Commutable> {
2633 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2634 OpcodeStr, !strconcat(Dt, "8"),
2635 v8i8, v8i8, IntOp, Commutable>;
2636 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2637 OpcodeStr, !strconcat(Dt, "8"),
2638 v16i8, v16i8, IntOp, Commutable>;
2640 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2641 InstrItinClass itinD16, InstrItinClass itinD32,
2642 InstrItinClass itinQ16, InstrItinClass itinQ32,
2643 string OpcodeStr, string Dt,
2645 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2646 OpcodeStr, Dt, IntOp> {
2647 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2648 OpcodeStr, !strconcat(Dt, "8"),
2650 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2651 OpcodeStr, !strconcat(Dt, "8"),
2652 v16i8, v16i8, IntOp>;
2656 // ....then also with element size of 64 bits:
2657 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2658 InstrItinClass itinD16, InstrItinClass itinD32,
2659 InstrItinClass itinQ16, InstrItinClass itinQ32,
2660 string OpcodeStr, string Dt,
2661 Intrinsic IntOp, bit Commutable = 0>
2662 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2663 OpcodeStr, Dt, IntOp, Commutable> {
2664 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2665 OpcodeStr, !strconcat(Dt, "64"),
2666 v1i64, v1i64, IntOp, Commutable>;
2667 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2668 OpcodeStr, !strconcat(Dt, "64"),
2669 v2i64, v2i64, IntOp, Commutable>;
2671 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2672 InstrItinClass itinD16, InstrItinClass itinD32,
2673 InstrItinClass itinQ16, InstrItinClass itinQ32,
2674 string OpcodeStr, string Dt,
2676 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2677 OpcodeStr, Dt, IntOp> {
2678 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2679 OpcodeStr, !strconcat(Dt, "64"),
2680 v1i64, v1i64, IntOp>;
2681 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2682 OpcodeStr, !strconcat(Dt, "64"),
2683 v2i64, v2i64, IntOp>;
2686 // Neon Narrowing 3-register vector intrinsics,
2687 // source operand element sizes of 16, 32 and 64 bits:
2688 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2689 string OpcodeStr, string Dt,
2690 Intrinsic IntOp, bit Commutable = 0> {
2691 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2692 OpcodeStr, !strconcat(Dt, "16"),
2693 v8i8, v8i16, IntOp, Commutable>;
2694 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2695 OpcodeStr, !strconcat(Dt, "32"),
2696 v4i16, v4i32, IntOp, Commutable>;
2697 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2698 OpcodeStr, !strconcat(Dt, "64"),
2699 v2i32, v2i64, IntOp, Commutable>;
2703 // Neon Long 3-register vector operations.
2705 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2706 InstrItinClass itin16, InstrItinClass itin32,
2707 string OpcodeStr, string Dt,
2708 SDNode OpNode, bit Commutable = 0> {
2709 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2710 OpcodeStr, !strconcat(Dt, "8"),
2711 v8i16, v8i8, OpNode, Commutable>;
2712 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2713 OpcodeStr, !strconcat(Dt, "16"),
2714 v4i32, v4i16, OpNode, Commutable>;
2715 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2716 OpcodeStr, !strconcat(Dt, "32"),
2717 v2i64, v2i32, OpNode, Commutable>;
2720 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2721 InstrItinClass itin, string OpcodeStr, string Dt,
2723 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2724 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2725 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2726 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2729 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2730 InstrItinClass itin16, InstrItinClass itin32,
2731 string OpcodeStr, string Dt,
2732 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2733 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2734 OpcodeStr, !strconcat(Dt, "8"),
2735 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2736 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2737 OpcodeStr, !strconcat(Dt, "16"),
2738 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2739 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2740 OpcodeStr, !strconcat(Dt, "32"),
2741 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2744 // Neon Long 3-register vector intrinsics.
2746 // First with only element sizes of 16 and 32 bits:
2747 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2748 InstrItinClass itin16, InstrItinClass itin32,
2749 string OpcodeStr, string Dt,
2750 Intrinsic IntOp, bit Commutable = 0> {
2751 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2752 OpcodeStr, !strconcat(Dt, "16"),
2753 v4i32, v4i16, IntOp, Commutable>;
2754 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2755 OpcodeStr, !strconcat(Dt, "32"),
2756 v2i64, v2i32, IntOp, Commutable>;
2759 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2760 InstrItinClass itin, string OpcodeStr, string Dt,
2762 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2763 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2764 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2765 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2768 // ....then also with element size of 8 bits:
2769 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2770 InstrItinClass itin16, InstrItinClass itin32,
2771 string OpcodeStr, string Dt,
2772 Intrinsic IntOp, bit Commutable = 0>
2773 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2774 IntOp, Commutable> {
2775 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2776 OpcodeStr, !strconcat(Dt, "8"),
2777 v8i16, v8i8, IntOp, Commutable>;
2780 // ....with explicit extend (VABDL).
2781 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2782 InstrItinClass itin, string OpcodeStr, string Dt,
2783 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2784 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2785 OpcodeStr, !strconcat(Dt, "8"),
2786 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2787 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2788 OpcodeStr, !strconcat(Dt, "16"),
2789 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2790 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2791 OpcodeStr, !strconcat(Dt, "32"),
2792 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2796 // Neon Wide 3-register vector intrinsics,
2797 // source operand element sizes of 8, 16 and 32 bits:
2798 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2799 string OpcodeStr, string Dt,
2800 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2801 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2802 OpcodeStr, !strconcat(Dt, "8"),
2803 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2804 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2805 OpcodeStr, !strconcat(Dt, "16"),
2806 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2807 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2808 OpcodeStr, !strconcat(Dt, "32"),
2809 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2813 // Neon Multiply-Op vector operations,
2814 // element sizes of 8, 16 and 32 bits:
2815 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2816 InstrItinClass itinD16, InstrItinClass itinD32,
2817 InstrItinClass itinQ16, InstrItinClass itinQ32,
2818 string OpcodeStr, string Dt, SDNode OpNode> {
2819 // 64-bit vector types.
2820 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2821 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2822 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2823 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2824 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2825 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2827 // 128-bit vector types.
2828 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2829 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2830 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2831 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2832 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2833 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2836 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2837 InstrItinClass itinD16, InstrItinClass itinD32,
2838 InstrItinClass itinQ16, InstrItinClass itinQ32,
2839 string OpcodeStr, string Dt, SDNode ShOp> {
2840 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2841 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2842 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2843 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2844 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2845 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2847 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2848 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2852 // Neon Intrinsic-Op vector operations,
2853 // element sizes of 8, 16 and 32 bits:
2854 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2855 InstrItinClass itinD, InstrItinClass itinQ,
2856 string OpcodeStr, string Dt, Intrinsic IntOp,
2858 // 64-bit vector types.
2859 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2860 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2861 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2862 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2863 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2864 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2866 // 128-bit vector types.
2867 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2868 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2869 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2870 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2871 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2872 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2875 // Neon 3-argument intrinsics,
2876 // element sizes of 8, 16 and 32 bits:
2877 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2878 InstrItinClass itinD, InstrItinClass itinQ,
2879 string OpcodeStr, string Dt, Intrinsic IntOp> {
2880 // 64-bit vector types.
2881 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2882 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2883 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2884 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2885 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2886 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2888 // 128-bit vector types.
2889 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2890 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2891 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2892 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2893 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2894 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2898 // Neon Long Multiply-Op vector operations,
2899 // element sizes of 8, 16 and 32 bits:
2900 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2901 InstrItinClass itin16, InstrItinClass itin32,
2902 string OpcodeStr, string Dt, SDNode MulOp,
2904 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2905 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2906 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2907 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2908 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2909 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2912 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2913 string Dt, SDNode MulOp, SDNode OpNode> {
2914 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2915 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2916 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2917 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2921 // Neon Long 3-argument intrinsics.
2923 // First with only element sizes of 16 and 32 bits:
2924 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2925 InstrItinClass itin16, InstrItinClass itin32,
2926 string OpcodeStr, string Dt, Intrinsic IntOp> {
2927 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2928 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2929 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2930 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2933 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2934 string OpcodeStr, string Dt, Intrinsic IntOp> {
2935 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2936 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2937 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2938 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2941 // ....then also with element size of 8 bits:
2942 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2943 InstrItinClass itin16, InstrItinClass itin32,
2944 string OpcodeStr, string Dt, Intrinsic IntOp>
2945 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2946 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2947 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2950 // ....with explicit extend (VABAL).
2951 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2952 InstrItinClass itin, string OpcodeStr, string Dt,
2953 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2954 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2955 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2956 IntOp, ExtOp, OpNode>;
2957 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2958 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2959 IntOp, ExtOp, OpNode>;
2960 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2961 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2962 IntOp, ExtOp, OpNode>;
2966 // Neon Pairwise long 2-register intrinsics,
2967 // element sizes of 8, 16 and 32 bits:
2968 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2969 bits<5> op11_7, bit op4,
2970 string OpcodeStr, string Dt, Intrinsic IntOp> {
2971 // 64-bit vector types.
2972 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2973 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2974 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2976 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2977 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2979 // 128-bit vector types.
2980 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2981 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2982 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2983 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2984 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2985 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2989 // Neon Pairwise long 2-register accumulate intrinsics,
2990 // element sizes of 8, 16 and 32 bits:
2991 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2992 bits<5> op11_7, bit op4,
2993 string OpcodeStr, string Dt, Intrinsic IntOp> {
2994 // 64-bit vector types.
2995 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2996 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2997 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2998 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2999 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3000 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3002 // 128-bit vector types.
3003 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3004 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3005 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3006 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3007 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3008 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3012 // Neon 2-register vector shift by immediate,
3013 // with f of either N2RegVShLFrm or N2RegVShRFrm
3014 // element sizes of 8, 16, 32 and 64 bits:
3015 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3016 InstrItinClass itin, string OpcodeStr, string Dt,
3018 // 64-bit vector types.
3019 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3020 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3021 let Inst{21-19} = 0b001; // imm6 = 001xxx
3023 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3024 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3025 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3027 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3028 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3029 let Inst{21} = 0b1; // imm6 = 1xxxxx
3031 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3032 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3035 // 128-bit vector types.
3036 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3037 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3038 let Inst{21-19} = 0b001; // imm6 = 001xxx
3040 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3041 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3042 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3044 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3045 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3046 let Inst{21} = 0b1; // imm6 = 1xxxxx
3048 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3049 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3052 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3053 InstrItinClass itin, string OpcodeStr, string Dt,
3055 // 64-bit vector types.
3056 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3057 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3058 let Inst{21-19} = 0b001; // imm6 = 001xxx
3060 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3061 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3062 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3064 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3065 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3066 let Inst{21} = 0b1; // imm6 = 1xxxxx
3068 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3069 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3072 // 128-bit vector types.
3073 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3074 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3075 let Inst{21-19} = 0b001; // imm6 = 001xxx
3077 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3078 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3079 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3081 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3082 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3083 let Inst{21} = 0b1; // imm6 = 1xxxxx
3085 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3086 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3090 // Neon Shift-Accumulate vector operations,
3091 // element sizes of 8, 16, 32 and 64 bits:
3092 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3093 string OpcodeStr, string Dt, SDNode ShOp> {
3094 // 64-bit vector types.
3095 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3096 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3097 let Inst{21-19} = 0b001; // imm6 = 001xxx
3099 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3100 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3101 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3103 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3104 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3105 let Inst{21} = 0b1; // imm6 = 1xxxxx
3107 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3108 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3111 // 128-bit vector types.
3112 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3113 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3114 let Inst{21-19} = 0b001; // imm6 = 001xxx
3116 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3117 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3118 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3120 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3121 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3122 let Inst{21} = 0b1; // imm6 = 1xxxxx
3124 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3125 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3129 // Neon Shift-Insert vector operations,
3130 // with f of either N2RegVShLFrm or N2RegVShRFrm
3131 // element sizes of 8, 16, 32 and 64 bits:
3132 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3134 // 64-bit vector types.
3135 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3136 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3137 let Inst{21-19} = 0b001; // imm6 = 001xxx
3139 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3140 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3141 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3143 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3144 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3145 let Inst{21} = 0b1; // imm6 = 1xxxxx
3147 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3148 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3151 // 128-bit vector types.
3152 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3153 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3154 let Inst{21-19} = 0b001; // imm6 = 001xxx
3156 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3157 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3158 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3160 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3161 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3162 let Inst{21} = 0b1; // imm6 = 1xxxxx
3164 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3165 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3168 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3170 // 64-bit vector types.
3171 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3172 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3173 let Inst{21-19} = 0b001; // imm6 = 001xxx
3175 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3176 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3177 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3179 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3180 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3181 let Inst{21} = 0b1; // imm6 = 1xxxxx
3183 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3184 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3187 // 128-bit vector types.
3188 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3189 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3190 let Inst{21-19} = 0b001; // imm6 = 001xxx
3192 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3193 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3194 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3196 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3197 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3198 let Inst{21} = 0b1; // imm6 = 1xxxxx
3200 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3201 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3205 // Neon Shift Long operations,
3206 // element sizes of 8, 16, 32 bits:
3207 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3208 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3209 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3210 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3211 let Inst{21-19} = 0b001; // imm6 = 001xxx
3213 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3214 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3215 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3217 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3218 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3219 let Inst{21} = 0b1; // imm6 = 1xxxxx
3223 // Neon Shift Narrow operations,
3224 // element sizes of 16, 32, 64 bits:
3225 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3226 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3228 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3229 OpcodeStr, !strconcat(Dt, "16"),
3230 v8i8, v8i16, shr_imm8, OpNode> {
3231 let Inst{21-19} = 0b001; // imm6 = 001xxx
3233 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3234 OpcodeStr, !strconcat(Dt, "32"),
3235 v4i16, v4i32, shr_imm16, OpNode> {
3236 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3238 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3239 OpcodeStr, !strconcat(Dt, "64"),
3240 v2i32, v2i64, shr_imm32, OpNode> {
3241 let Inst{21} = 0b1; // imm6 = 1xxxxx
3245 //===----------------------------------------------------------------------===//
3246 // Instruction Definitions.
3247 //===----------------------------------------------------------------------===//
3249 // Vector Add Operations.
3251 // VADD : Vector Add (integer and floating-point)
3252 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3254 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3255 v2f32, v2f32, fadd, 1>;
3256 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3257 v4f32, v4f32, fadd, 1>;
3258 // VADDL : Vector Add Long (Q = D + D)
3259 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3260 "vaddl", "s", add, sext, 1>;
3261 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3262 "vaddl", "u", add, zext, 1>;
3263 // VADDW : Vector Add Wide (Q = Q + D)
3264 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3265 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3266 // VHADD : Vector Halving Add
3267 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3268 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3269 "vhadd", "s", int_arm_neon_vhadds, 1>;
3270 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3271 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3272 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3273 // VRHADD : Vector Rounding Halving Add
3274 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3275 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3276 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3277 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3278 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3279 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3280 // VQADD : Vector Saturating Add
3281 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3282 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3283 "vqadd", "s", int_arm_neon_vqadds, 1>;
3284 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3285 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3286 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3287 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3288 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3289 int_arm_neon_vaddhn, 1>;
3290 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3291 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3292 int_arm_neon_vraddhn, 1>;
3294 // Vector Multiply Operations.
3296 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3297 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3298 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3299 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3300 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3301 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3302 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3303 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3304 v2f32, v2f32, fmul, 1>;
3305 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3306 v4f32, v4f32, fmul, 1>;
3307 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3308 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3309 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3312 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3313 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3314 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3315 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3316 (DSubReg_i16_reg imm:$lane))),
3317 (SubReg_i16_lane imm:$lane)))>;
3318 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3319 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3320 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3321 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3322 (DSubReg_i32_reg imm:$lane))),
3323 (SubReg_i32_lane imm:$lane)))>;
3324 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3325 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3326 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3327 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3328 (DSubReg_i32_reg imm:$lane))),
3329 (SubReg_i32_lane imm:$lane)))>;
3331 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3332 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3333 IIC_VMULi16Q, IIC_VMULi32Q,
3334 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3335 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3336 IIC_VMULi16Q, IIC_VMULi32Q,
3337 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3338 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3339 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3341 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3342 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3343 (DSubReg_i16_reg imm:$lane))),
3344 (SubReg_i16_lane imm:$lane)))>;
3345 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3346 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3348 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3349 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3350 (DSubReg_i32_reg imm:$lane))),
3351 (SubReg_i32_lane imm:$lane)))>;
3353 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3354 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3355 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3356 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3357 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3358 IIC_VMULi16Q, IIC_VMULi32Q,
3359 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3360 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3361 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3363 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3364 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3365 (DSubReg_i16_reg imm:$lane))),
3366 (SubReg_i16_lane imm:$lane)))>;
3367 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3368 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3370 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3371 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3372 (DSubReg_i32_reg imm:$lane))),
3373 (SubReg_i32_lane imm:$lane)))>;
3375 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3376 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3377 "vmull", "s", NEONvmulls, 1>;
3378 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3379 "vmull", "u", NEONvmullu, 1>;
3380 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3381 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3382 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3383 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3385 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3386 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3387 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3388 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3389 "vqdmull", "s", int_arm_neon_vqdmull>;
3391 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3393 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3394 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3395 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3396 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3397 v2f32, fmul_su, fadd_mlx>,
3398 Requires<[HasNEON, UseFPVMLx]>;
3399 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3400 v4f32, fmul_su, fadd_mlx>,
3401 Requires<[HasNEON, UseFPVMLx]>;
3402 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3403 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3404 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3405 v2f32, fmul_su, fadd_mlx>,
3406 Requires<[HasNEON, UseFPVMLx]>;
3407 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3408 v4f32, v2f32, fmul_su, fadd_mlx>,
3409 Requires<[HasNEON, UseFPVMLx]>;
3411 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3412 (mul (v8i16 QPR:$src2),
3413 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3414 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3415 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3416 (DSubReg_i16_reg imm:$lane))),
3417 (SubReg_i16_lane imm:$lane)))>;
3419 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3420 (mul (v4i32 QPR:$src2),
3421 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3422 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3423 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3424 (DSubReg_i32_reg imm:$lane))),
3425 (SubReg_i32_lane imm:$lane)))>;
3427 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3428 (fmul_su (v4f32 QPR:$src2),
3429 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3430 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3432 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3433 (DSubReg_i32_reg imm:$lane))),
3434 (SubReg_i32_lane imm:$lane)))>,
3435 Requires<[HasNEON, UseFPVMLx]>;
3437 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3438 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3439 "vmlal", "s", NEONvmulls, add>;
3440 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3441 "vmlal", "u", NEONvmullu, add>;
3443 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3444 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3446 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3447 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3448 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3449 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3451 // VMLS : Vector Multiply Subtract (integer and floating-point)
3452 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3453 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3454 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3455 v2f32, fmul_su, fsub_mlx>,
3456 Requires<[HasNEON, UseFPVMLx]>;
3457 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3458 v4f32, fmul_su, fsub_mlx>,
3459 Requires<[HasNEON, UseFPVMLx]>;
3460 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3461 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3462 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3463 v2f32, fmul_su, fsub_mlx>,
3464 Requires<[HasNEON, UseFPVMLx]>;
3465 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3466 v4f32, v2f32, fmul_su, fsub_mlx>,
3467 Requires<[HasNEON, UseFPVMLx]>;
3469 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3470 (mul (v8i16 QPR:$src2),
3471 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3472 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3473 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3474 (DSubReg_i16_reg imm:$lane))),
3475 (SubReg_i16_lane imm:$lane)))>;
3477 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3478 (mul (v4i32 QPR:$src2),
3479 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3480 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3481 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3482 (DSubReg_i32_reg imm:$lane))),
3483 (SubReg_i32_lane imm:$lane)))>;
3485 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3486 (fmul_su (v4f32 QPR:$src2),
3487 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3488 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3489 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3490 (DSubReg_i32_reg imm:$lane))),
3491 (SubReg_i32_lane imm:$lane)))>,
3492 Requires<[HasNEON, UseFPVMLx]>;
3494 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3495 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3496 "vmlsl", "s", NEONvmulls, sub>;
3497 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3498 "vmlsl", "u", NEONvmullu, sub>;
3500 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3501 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3503 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3504 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3505 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3506 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3508 // Vector Subtract Operations.
3510 // VSUB : Vector Subtract (integer and floating-point)
3511 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3512 "vsub", "i", sub, 0>;
3513 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3514 v2f32, v2f32, fsub, 0>;
3515 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3516 v4f32, v4f32, fsub, 0>;
3517 // VSUBL : Vector Subtract Long (Q = D - D)
3518 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3519 "vsubl", "s", sub, sext, 0>;
3520 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3521 "vsubl", "u", sub, zext, 0>;
3522 // VSUBW : Vector Subtract Wide (Q = Q - D)
3523 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3524 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3525 // VHSUB : Vector Halving Subtract
3526 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3527 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3528 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3529 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3530 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3531 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3532 // VQSUB : Vector Saturing Subtract
3533 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3534 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3535 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3536 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3537 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3538 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3539 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3540 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3541 int_arm_neon_vsubhn, 0>;
3542 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3543 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3544 int_arm_neon_vrsubhn, 0>;
3546 // Vector Comparisons.
3548 // VCEQ : Vector Compare Equal
3549 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3550 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3551 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3553 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3556 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3557 "$Vd, $Vm, #0", NEONvceqz>;
3559 // VCGE : Vector Compare Greater Than or Equal
3560 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3561 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3562 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3563 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3564 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3566 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3569 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3570 "$Vd, $Vm, #0", NEONvcgez>;
3571 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3572 "$Vd, $Vm, #0", NEONvclez>;
3574 // VCGT : Vector Compare Greater Than
3575 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3576 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3577 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3578 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3579 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3581 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3584 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3585 "$Vd, $Vm, #0", NEONvcgtz>;
3586 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3587 "$Vd, $Vm, #0", NEONvcltz>;
3589 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3590 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3591 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3592 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3593 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3594 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3595 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3596 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3597 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3598 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3599 // VTST : Vector Test Bits
3600 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3601 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3603 // Vector Bitwise Operations.
3605 def vnotd : PatFrag<(ops node:$in),
3606 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3607 def vnotq : PatFrag<(ops node:$in),
3608 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3611 // VAND : Vector Bitwise AND
3612 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3613 v2i32, v2i32, and, 1>;
3614 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3615 v4i32, v4i32, and, 1>;
3617 // VEOR : Vector Bitwise Exclusive OR
3618 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3619 v2i32, v2i32, xor, 1>;
3620 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3621 v4i32, v4i32, xor, 1>;
3623 // VORR : Vector Bitwise OR
3624 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3625 v2i32, v2i32, or, 1>;
3626 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3627 v4i32, v4i32, or, 1>;
3629 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3630 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3632 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3634 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3635 let Inst{9} = SIMM{9};
3638 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3639 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3641 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3643 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3644 let Inst{10-9} = SIMM{10-9};
3647 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3648 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3650 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3652 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3653 let Inst{9} = SIMM{9};
3656 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3657 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3659 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3661 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3662 let Inst{10-9} = SIMM{10-9};
3666 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3667 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3668 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3669 "vbic", "$Vd, $Vn, $Vm", "",
3670 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3671 (vnotd DPR:$Vm))))]>;
3672 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3673 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3674 "vbic", "$Vd, $Vn, $Vm", "",
3675 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3676 (vnotq QPR:$Vm))))]>;
3678 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3679 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3681 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3683 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3684 let Inst{9} = SIMM{9};
3687 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3688 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3690 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3692 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3693 let Inst{10-9} = SIMM{10-9};
3696 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3697 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3699 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3701 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3702 let Inst{9} = SIMM{9};
3705 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3706 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3708 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3710 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3711 let Inst{10-9} = SIMM{10-9};
3714 // VORN : Vector Bitwise OR NOT
3715 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3716 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3717 "vorn", "$Vd, $Vn, $Vm", "",
3718 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3719 (vnotd DPR:$Vm))))]>;
3720 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3721 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3722 "vorn", "$Vd, $Vn, $Vm", "",
3723 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3724 (vnotq QPR:$Vm))))]>;
3726 // VMVN : Vector Bitwise NOT (Immediate)
3728 let isReMaterializable = 1 in {
3730 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3731 (ins nModImm:$SIMM), IIC_VMOVImm,
3732 "vmvn", "i16", "$Vd, $SIMM", "",
3733 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3734 let Inst{9} = SIMM{9};
3737 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3738 (ins nModImm:$SIMM), IIC_VMOVImm,
3739 "vmvn", "i16", "$Vd, $SIMM", "",
3740 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3741 let Inst{9} = SIMM{9};
3744 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3745 (ins nModImm:$SIMM), IIC_VMOVImm,
3746 "vmvn", "i32", "$Vd, $SIMM", "",
3747 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3748 let Inst{11-8} = SIMM{11-8};
3751 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3752 (ins nModImm:$SIMM), IIC_VMOVImm,
3753 "vmvn", "i32", "$Vd, $SIMM", "",
3754 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3755 let Inst{11-8} = SIMM{11-8};
3759 // VMVN : Vector Bitwise NOT
3760 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3761 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3762 "vmvn", "$Vd, $Vm", "",
3763 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3764 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3765 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3766 "vmvn", "$Vd, $Vm", "",
3767 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3768 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3769 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3771 // VBSL : Vector Bitwise Select
3772 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3773 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3774 N3RegFrm, IIC_VCNTiD,
3775 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3776 [(set DPR:$Vd, (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3778 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3779 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3780 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3782 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3783 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3784 N3RegFrm, IIC_VCNTiQ,
3785 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3786 [(set QPR:$Vd, (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3788 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3789 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3790 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3792 // VBIF : Vector Bitwise Insert if False
3793 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3794 // FIXME: This instruction's encoding MAY NOT BE correct.
3795 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3796 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3797 N3RegFrm, IIC_VBINiD,
3798 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3799 [/* For disassembly only; pattern left blank */]>;
3800 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3801 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3802 N3RegFrm, IIC_VBINiQ,
3803 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3804 [/* For disassembly only; pattern left blank */]>;
3806 // VBIT : Vector Bitwise Insert if True
3807 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3808 // FIXME: This instruction's encoding MAY NOT BE correct.
3809 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3810 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3811 N3RegFrm, IIC_VBINiD,
3812 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3813 [/* For disassembly only; pattern left blank */]>;
3814 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3815 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3816 N3RegFrm, IIC_VBINiQ,
3817 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3818 [/* For disassembly only; pattern left blank */]>;
3820 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3821 // for equivalent operations with different register constraints; it just
3824 // Vector Absolute Differences.
3826 // VABD : Vector Absolute Difference
3827 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3828 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3829 "vabd", "s", int_arm_neon_vabds, 1>;
3830 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3831 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3832 "vabd", "u", int_arm_neon_vabdu, 1>;
3833 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3834 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3835 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3836 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3838 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3839 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3840 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3841 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3842 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3844 // VABA : Vector Absolute Difference and Accumulate
3845 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3846 "vaba", "s", int_arm_neon_vabds, add>;
3847 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3848 "vaba", "u", int_arm_neon_vabdu, add>;
3850 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3851 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3852 "vabal", "s", int_arm_neon_vabds, zext, add>;
3853 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3854 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3856 // Vector Maximum and Minimum.
3858 // VMAX : Vector Maximum
3859 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3860 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3861 "vmax", "s", int_arm_neon_vmaxs, 1>;
3862 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3863 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3864 "vmax", "u", int_arm_neon_vmaxu, 1>;
3865 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3867 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3868 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3870 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3872 // VMIN : Vector Minimum
3873 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3874 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3875 "vmin", "s", int_arm_neon_vmins, 1>;
3876 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3877 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3878 "vmin", "u", int_arm_neon_vminu, 1>;
3879 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3881 v2f32, v2f32, int_arm_neon_vmins, 1>;
3882 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3884 v4f32, v4f32, int_arm_neon_vmins, 1>;
3886 // Vector Pairwise Operations.
3888 // VPADD : Vector Pairwise Add
3889 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3891 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3892 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3894 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3895 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3897 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3898 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3899 IIC_VPBIND, "vpadd", "f32",
3900 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3902 // VPADDL : Vector Pairwise Add Long
3903 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3904 int_arm_neon_vpaddls>;
3905 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3906 int_arm_neon_vpaddlu>;
3908 // VPADAL : Vector Pairwise Add and Accumulate Long
3909 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3910 int_arm_neon_vpadals>;
3911 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3912 int_arm_neon_vpadalu>;
3914 // VPMAX : Vector Pairwise Maximum
3915 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3916 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3917 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3918 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3919 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3920 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3921 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3922 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3923 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3924 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3925 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3926 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3927 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3928 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3930 // VPMIN : Vector Pairwise Minimum
3931 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3932 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3933 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3934 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3935 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3936 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3937 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3938 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3939 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3940 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3941 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3942 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3943 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3944 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3946 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3948 // VRECPE : Vector Reciprocal Estimate
3949 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3950 IIC_VUNAD, "vrecpe", "u32",
3951 v2i32, v2i32, int_arm_neon_vrecpe>;
3952 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3953 IIC_VUNAQ, "vrecpe", "u32",
3954 v4i32, v4i32, int_arm_neon_vrecpe>;
3955 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3956 IIC_VUNAD, "vrecpe", "f32",
3957 v2f32, v2f32, int_arm_neon_vrecpe>;
3958 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3959 IIC_VUNAQ, "vrecpe", "f32",
3960 v4f32, v4f32, int_arm_neon_vrecpe>;
3962 // VRECPS : Vector Reciprocal Step
3963 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3964 IIC_VRECSD, "vrecps", "f32",
3965 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3966 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3967 IIC_VRECSQ, "vrecps", "f32",
3968 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3970 // VRSQRTE : Vector Reciprocal Square Root Estimate
3971 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3972 IIC_VUNAD, "vrsqrte", "u32",
3973 v2i32, v2i32, int_arm_neon_vrsqrte>;
3974 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3975 IIC_VUNAQ, "vrsqrte", "u32",
3976 v4i32, v4i32, int_arm_neon_vrsqrte>;
3977 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3978 IIC_VUNAD, "vrsqrte", "f32",
3979 v2f32, v2f32, int_arm_neon_vrsqrte>;
3980 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3981 IIC_VUNAQ, "vrsqrte", "f32",
3982 v4f32, v4f32, int_arm_neon_vrsqrte>;
3984 // VRSQRTS : Vector Reciprocal Square Root Step
3985 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3986 IIC_VRECSD, "vrsqrts", "f32",
3987 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3988 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3989 IIC_VRECSQ, "vrsqrts", "f32",
3990 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3994 // VSHL : Vector Shift
3995 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3996 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3997 "vshl", "s", int_arm_neon_vshifts>;
3998 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3999 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4000 "vshl", "u", int_arm_neon_vshiftu>;
4002 // VSHL : Vector Shift Left (Immediate)
4003 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4005 // VSHR : Vector Shift Right (Immediate)
4006 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4007 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4009 // VSHLL : Vector Shift Left Long
4010 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4011 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4013 // VSHLL : Vector Shift Left Long (with maximum shift count)
4014 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4015 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4016 ValueType OpTy, SDNode OpNode>
4017 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4018 ResTy, OpTy, OpNode> {
4019 let Inst{21-16} = op21_16;
4021 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4022 v8i16, v8i8, NEONvshlli>;
4023 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4024 v4i32, v4i16, NEONvshlli>;
4025 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4026 v2i64, v2i32, NEONvshlli>;
4028 // VSHRN : Vector Shift Right and Narrow
4029 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4032 // VRSHL : Vector Rounding Shift
4033 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4034 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4035 "vrshl", "s", int_arm_neon_vrshifts>;
4036 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4037 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4038 "vrshl", "u", int_arm_neon_vrshiftu>;
4039 // VRSHR : Vector Rounding Shift Right
4040 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4041 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4043 // VRSHRN : Vector Rounding Shift Right and Narrow
4044 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4047 // VQSHL : Vector Saturating Shift
4048 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4049 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4050 "vqshl", "s", int_arm_neon_vqshifts>;
4051 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4052 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4053 "vqshl", "u", int_arm_neon_vqshiftu>;
4054 // VQSHL : Vector Saturating Shift Left (Immediate)
4055 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4056 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4058 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4059 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4061 // VQSHRN : Vector Saturating Shift Right and Narrow
4062 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4064 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4067 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4068 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4071 // VQRSHL : Vector Saturating Rounding Shift
4072 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4073 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4074 "vqrshl", "s", int_arm_neon_vqrshifts>;
4075 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4076 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4077 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4079 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4080 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4082 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4085 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4086 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4089 // VSRA : Vector Shift Right and Accumulate
4090 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4091 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4092 // VRSRA : Vector Rounding Shift Right and Accumulate
4093 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4094 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4096 // VSLI : Vector Shift Left and Insert
4097 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4099 // VSRI : Vector Shift Right and Insert
4100 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4102 // Vector Absolute and Saturating Absolute.
4104 // VABS : Vector Absolute Value
4105 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4106 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4108 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4109 IIC_VUNAD, "vabs", "f32",
4110 v2f32, v2f32, int_arm_neon_vabs>;
4111 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4112 IIC_VUNAQ, "vabs", "f32",
4113 v4f32, v4f32, int_arm_neon_vabs>;
4115 // VQABS : Vector Saturating Absolute Value
4116 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4117 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4118 int_arm_neon_vqabs>;
4122 def vnegd : PatFrag<(ops node:$in),
4123 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4124 def vnegq : PatFrag<(ops node:$in),
4125 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4127 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4128 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4129 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4130 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4131 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4132 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4133 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4134 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4136 // VNEG : Vector Negate (integer)
4137 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4138 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4139 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4140 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4141 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4142 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4144 // VNEG : Vector Negate (floating-point)
4145 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4146 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4147 "vneg", "f32", "$Vd, $Vm", "",
4148 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4149 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4150 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4151 "vneg", "f32", "$Vd, $Vm", "",
4152 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4154 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4155 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4156 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4157 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4158 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4159 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4161 // VQNEG : Vector Saturating Negate
4162 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4163 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4164 int_arm_neon_vqneg>;
4166 // Vector Bit Counting Operations.
4168 // VCLS : Vector Count Leading Sign Bits
4169 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4170 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4172 // VCLZ : Vector Count Leading Zeros
4173 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4174 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4176 // VCNT : Vector Count One Bits
4177 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4178 IIC_VCNTiD, "vcnt", "8",
4179 v8i8, v8i8, int_arm_neon_vcnt>;
4180 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4181 IIC_VCNTiQ, "vcnt", "8",
4182 v16i8, v16i8, int_arm_neon_vcnt>;
4184 // Vector Swap -- for disassembly only.
4185 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4186 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4187 "vswp", "$Vd, $Vm", "", []>;
4188 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4189 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4190 "vswp", "$Vd, $Vm", "", []>;
4192 // Vector Move Operations.
4194 // VMOV : Vector Move (Register)
4196 let neverHasSideEffects = 1 in {
4197 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4198 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4199 let Vn{4-0} = Vm{4-0};
4201 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4202 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4203 let Vn{4-0} = Vm{4-0};
4206 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4207 // be expanded after register allocation is completed.
4208 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4211 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4213 } // neverHasSideEffects
4215 // VMOV : Vector Move (Immediate)
4217 let isReMaterializable = 1 in {
4218 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4219 (ins nModImm:$SIMM), IIC_VMOVImm,
4220 "vmov", "i8", "$Vd, $SIMM", "",
4221 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4222 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4223 (ins nModImm:$SIMM), IIC_VMOVImm,
4224 "vmov", "i8", "$Vd, $SIMM", "",
4225 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4227 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4228 (ins nModImm:$SIMM), IIC_VMOVImm,
4229 "vmov", "i16", "$Vd, $SIMM", "",
4230 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4231 let Inst{9} = SIMM{9};
4234 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4235 (ins nModImm:$SIMM), IIC_VMOVImm,
4236 "vmov", "i16", "$Vd, $SIMM", "",
4237 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4238 let Inst{9} = SIMM{9};
4241 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4242 (ins nModImm:$SIMM), IIC_VMOVImm,
4243 "vmov", "i32", "$Vd, $SIMM", "",
4244 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4245 let Inst{11-8} = SIMM{11-8};
4248 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4249 (ins nModImm:$SIMM), IIC_VMOVImm,
4250 "vmov", "i32", "$Vd, $SIMM", "",
4251 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4252 let Inst{11-8} = SIMM{11-8};
4255 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4256 (ins nModImm:$SIMM), IIC_VMOVImm,
4257 "vmov", "i64", "$Vd, $SIMM", "",
4258 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4259 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4260 (ins nModImm:$SIMM), IIC_VMOVImm,
4261 "vmov", "i64", "$Vd, $SIMM", "",
4262 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4263 } // isReMaterializable
4265 // VMOV : Vector Get Lane (move scalar to ARM core register)
4267 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4268 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4269 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4270 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4272 let Inst{21} = lane{2};
4273 let Inst{6-5} = lane{1-0};
4275 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4276 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4277 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4278 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4280 let Inst{21} = lane{1};
4281 let Inst{6} = lane{0};
4283 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4284 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4285 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4286 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4288 let Inst{21} = lane{2};
4289 let Inst{6-5} = lane{1-0};
4291 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4292 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4293 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4294 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4296 let Inst{21} = lane{1};
4297 let Inst{6} = lane{0};
4299 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4300 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4301 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4302 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4304 let Inst{21} = lane{0};
4306 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4307 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4308 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4309 (DSubReg_i8_reg imm:$lane))),
4310 (SubReg_i8_lane imm:$lane))>;
4311 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4312 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4313 (DSubReg_i16_reg imm:$lane))),
4314 (SubReg_i16_lane imm:$lane))>;
4315 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4316 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4317 (DSubReg_i8_reg imm:$lane))),
4318 (SubReg_i8_lane imm:$lane))>;
4319 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4320 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4321 (DSubReg_i16_reg imm:$lane))),
4322 (SubReg_i16_lane imm:$lane))>;
4323 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4324 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4325 (DSubReg_i32_reg imm:$lane))),
4326 (SubReg_i32_lane imm:$lane))>;
4327 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4328 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4329 (SSubReg_f32_reg imm:$src2))>;
4330 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4331 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4332 (SSubReg_f32_reg imm:$src2))>;
4333 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4334 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4335 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4336 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4339 // VMOV : Vector Set Lane (move ARM core register to scalar)
4341 let Constraints = "$src1 = $V" in {
4342 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4343 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4344 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4345 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4346 GPR:$R, imm:$lane))]> {
4347 let Inst{21} = lane{2};
4348 let Inst{6-5} = lane{1-0};
4350 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4351 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4352 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4353 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4354 GPR:$R, imm:$lane))]> {
4355 let Inst{21} = lane{1};
4356 let Inst{6} = lane{0};
4358 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4359 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4360 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4361 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4362 GPR:$R, imm:$lane))]> {
4363 let Inst{21} = lane{0};
4366 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4367 (v16i8 (INSERT_SUBREG QPR:$src1,
4368 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4369 (DSubReg_i8_reg imm:$lane))),
4370 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4371 (DSubReg_i8_reg imm:$lane)))>;
4372 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4373 (v8i16 (INSERT_SUBREG QPR:$src1,
4374 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4375 (DSubReg_i16_reg imm:$lane))),
4376 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4377 (DSubReg_i16_reg imm:$lane)))>;
4378 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4379 (v4i32 (INSERT_SUBREG QPR:$src1,
4380 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4381 (DSubReg_i32_reg imm:$lane))),
4382 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4383 (DSubReg_i32_reg imm:$lane)))>;
4385 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4386 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4387 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4388 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4389 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4390 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4392 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4393 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4394 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4395 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4397 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4398 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4399 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4400 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4401 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4402 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4404 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4405 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4406 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4407 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4408 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4409 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4411 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4412 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4413 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4415 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4416 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4417 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4419 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4420 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4421 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4424 // VDUP : Vector Duplicate (from ARM core register to all elements)
4426 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4427 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4428 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4429 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4430 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4431 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4432 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4433 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4435 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4436 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4437 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4438 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4439 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4440 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4442 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4443 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4445 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4447 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4449 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4450 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4451 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4453 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4454 ValueType ResTy, ValueType OpTy>
4455 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4456 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4457 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4460 // Inst{19-16} is partially specified depending on the element size.
4462 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4463 let Inst{19-17} = lane{2-0};
4465 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4466 let Inst{19-18} = lane{1-0};
4468 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4469 let Inst{19} = lane{0};
4471 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4472 let Inst{19-17} = lane{2-0};
4474 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4475 let Inst{19-18} = lane{1-0};
4477 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4478 let Inst{19} = lane{0};
4481 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4482 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4484 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4485 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4487 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4488 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4489 (DSubReg_i8_reg imm:$lane))),
4490 (SubReg_i8_lane imm:$lane)))>;
4491 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4492 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4493 (DSubReg_i16_reg imm:$lane))),
4494 (SubReg_i16_lane imm:$lane)))>;
4495 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4496 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4497 (DSubReg_i32_reg imm:$lane))),
4498 (SubReg_i32_lane imm:$lane)))>;
4499 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4500 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4501 (DSubReg_i32_reg imm:$lane))),
4502 (SubReg_i32_lane imm:$lane)))>;
4504 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4505 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4506 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4507 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4509 // VMOVN : Vector Narrowing Move
4510 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4511 "vmovn", "i", trunc>;
4512 // VQMOVN : Vector Saturating Narrowing Move
4513 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4514 "vqmovn", "s", int_arm_neon_vqmovns>;
4515 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4516 "vqmovn", "u", int_arm_neon_vqmovnu>;
4517 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4518 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4519 // VMOVL : Vector Lengthening Move
4520 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4521 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4523 // Vector Conversions.
4525 // VCVT : Vector Convert Between Floating-Point and Integers
4526 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4527 v2i32, v2f32, fp_to_sint>;
4528 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4529 v2i32, v2f32, fp_to_uint>;
4530 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4531 v2f32, v2i32, sint_to_fp>;
4532 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4533 v2f32, v2i32, uint_to_fp>;
4535 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4536 v4i32, v4f32, fp_to_sint>;
4537 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4538 v4i32, v4f32, fp_to_uint>;
4539 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4540 v4f32, v4i32, sint_to_fp>;
4541 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4542 v4f32, v4i32, uint_to_fp>;
4544 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4545 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4546 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4547 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4548 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4549 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4550 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4551 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4552 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4554 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4555 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4556 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4557 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4558 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4559 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4560 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4561 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4563 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4564 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4565 IIC_VUNAQ, "vcvt", "f16.f32",
4566 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4567 Requires<[HasNEON, HasFP16]>;
4568 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4569 IIC_VUNAQ, "vcvt", "f32.f16",
4570 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4571 Requires<[HasNEON, HasFP16]>;
4575 // VREV64 : Vector Reverse elements within 64-bit doublewords
4577 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4578 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4579 (ins DPR:$Vm), IIC_VMOVD,
4580 OpcodeStr, Dt, "$Vd, $Vm", "",
4581 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4582 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4583 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4584 (ins QPR:$Vm), IIC_VMOVQ,
4585 OpcodeStr, Dt, "$Vd, $Vm", "",
4586 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4588 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4589 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4590 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4591 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4593 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4594 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4595 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4596 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4598 // VREV32 : Vector Reverse elements within 32-bit words
4600 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4601 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4602 (ins DPR:$Vm), IIC_VMOVD,
4603 OpcodeStr, Dt, "$Vd, $Vm", "",
4604 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4605 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4606 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4607 (ins QPR:$Vm), IIC_VMOVQ,
4608 OpcodeStr, Dt, "$Vd, $Vm", "",
4609 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4611 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4612 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4614 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4615 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4617 // VREV16 : Vector Reverse elements within 16-bit halfwords
4619 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4620 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4621 (ins DPR:$Vm), IIC_VMOVD,
4622 OpcodeStr, Dt, "$Vd, $Vm", "",
4623 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4624 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4625 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4626 (ins QPR:$Vm), IIC_VMOVQ,
4627 OpcodeStr, Dt, "$Vd, $Vm", "",
4628 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4630 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4631 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4633 // Other Vector Shuffles.
4635 // Aligned extractions: really just dropping registers
4637 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4638 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4639 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4641 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4643 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4645 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4647 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4649 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4652 // VEXT : Vector Extract
4654 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4655 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4656 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4657 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4658 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4659 (Ty DPR:$Vm), imm:$index)))]> {
4661 let Inst{11-8} = index{3-0};
4664 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4665 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4666 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4667 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4668 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4669 (Ty QPR:$Vm), imm:$index)))]> {
4671 let Inst{11-8} = index{3-0};
4674 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4675 let Inst{11-8} = index{3-0};
4677 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4678 let Inst{11-9} = index{2-0};
4681 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4682 let Inst{11-10} = index{1-0};
4683 let Inst{9-8} = 0b00;
4685 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4686 let Inst{11} = index{0};
4687 let Inst{10-8} = 0b000;
4690 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4691 let Inst{11-8} = index{3-0};
4693 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4694 let Inst{11-9} = index{2-0};
4697 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4698 let Inst{11-10} = index{1-0};
4699 let Inst{9-8} = 0b00;
4701 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4702 let Inst{11} = index{0};
4703 let Inst{10-8} = 0b000;
4706 // VTRN : Vector Transpose
4708 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4709 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4710 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4712 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4713 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4714 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4716 // VUZP : Vector Unzip (Deinterleave)
4718 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4719 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4720 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4722 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4723 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4724 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4726 // VZIP : Vector Zip (Interleave)
4728 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4729 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4730 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4732 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4733 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4734 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4736 // Vector Table Lookup and Table Extension.
4738 // VTBL : Vector Table Lookup
4740 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4741 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4742 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4743 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4744 let hasExtraSrcRegAllocReq = 1 in {
4746 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4747 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4748 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4750 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4751 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4752 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4754 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4755 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4757 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4758 } // hasExtraSrcRegAllocReq = 1
4761 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4763 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4765 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4767 // VTBX : Vector Table Extension
4769 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4770 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4771 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4772 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4773 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4774 let hasExtraSrcRegAllocReq = 1 in {
4776 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4777 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4778 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4780 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4781 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4782 NVTBLFrm, IIC_VTBX3,
4783 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4786 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4787 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4788 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4790 } // hasExtraSrcRegAllocReq = 1
4793 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4794 IIC_VTBX2, "$orig = $dst", []>;
4796 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4797 IIC_VTBX3, "$orig = $dst", []>;
4799 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4800 IIC_VTBX4, "$orig = $dst", []>;
4802 //===----------------------------------------------------------------------===//
4803 // NEON instructions for single-precision FP math
4804 //===----------------------------------------------------------------------===//
4806 class N2VSPat<SDNode OpNode, NeonI Inst>
4807 : NEONFPPat<(f32 (OpNode SPR:$a)),
4809 (v2f32 (COPY_TO_REGCLASS (Inst
4811 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4812 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4814 class N3VSPat<SDNode OpNode, NeonI Inst>
4815 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4817 (v2f32 (COPY_TO_REGCLASS (Inst
4819 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4822 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4823 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4825 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4826 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4828 (v2f32 (COPY_TO_REGCLASS (Inst
4830 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4833 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4836 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4837 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4839 def : N3VSPat<fadd, VADDfd>;
4840 def : N3VSPat<fsub, VSUBfd>;
4841 def : N3VSPat<fmul, VMULfd>;
4842 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4843 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4844 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4845 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4846 def : N2VSPat<fabs, VABSfd>;
4847 def : N2VSPat<fneg, VNEGfd>;
4848 def : N3VSPat<NEONfmax, VMAXfd>;
4849 def : N3VSPat<NEONfmin, VMINfd>;
4850 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4851 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4852 def : N2VSPat<arm_sitof, VCVTs2fd>;
4853 def : N2VSPat<arm_uitof, VCVTu2fd>;
4855 //===----------------------------------------------------------------------===//
4856 // Non-Instruction Patterns
4857 //===----------------------------------------------------------------------===//
4860 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4861 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4862 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4863 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4864 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4865 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4866 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4867 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4868 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4869 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4870 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4871 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4872 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4873 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4874 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4875 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4876 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4877 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4878 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4879 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4880 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4881 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4882 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4883 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4884 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4885 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4886 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4887 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4888 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4889 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4891 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4892 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4893 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4894 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4895 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4896 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4897 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4898 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4899 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4900 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4901 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4902 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4903 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4904 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4905 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4906 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4907 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4908 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4909 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4910 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4911 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4912 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4913 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4914 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4915 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4916 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4917 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4918 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4919 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4920 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;