1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 // Classes for VLD*LN pseudo-instructions with multi-register operands.
488 // These are expanded to real instructions after register allocation.
489 class VLDQLNPseudo<InstrItinClass itin>
490 : PseudoNLdSt<(outs QPR:$dst),
491 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
492 itin, "$src = $dst">;
493 class VLDQLNWBPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
496 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
497 class VLDQQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QQPR:$dst),
499 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQQQPR:$dst),
507 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
514 // VLD1LN : Vector Load (single element to one lane)
515 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
517 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
518 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
519 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
521 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
522 (i32 (LoadOp addrmode6:$Rn)),
526 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
527 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
528 (i32 (LoadOp addrmode6:$addr)),
532 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
533 let Inst{7-5} = lane{2-0};
535 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
536 let Inst{7-6} = lane{1-0};
539 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
540 let Inst{7} = lane{0};
545 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
546 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
547 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
549 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
551 // ...with address register writeback:
552 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
553 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
554 (ins addrmode6:$Rn, am6offset:$Rm,
555 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
556 "\\{$Vd[$lane]\\}, $Rn$Rm",
557 "$src = $Vd, $Rn.addr = $wb", []>;
559 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
560 let Inst{7-5} = lane{2-0};
562 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
563 let Inst{7-6} = lane{1-0};
566 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
567 let Inst{7} = lane{0};
572 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
573 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
574 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
576 // VLD2LN : Vector Load (single 2-element structure to one lane)
577 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
578 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
579 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
580 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
581 "$src1 = $Vd, $src2 = $dst2", []> {
586 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
587 let Inst{7-5} = lane{2-0};
589 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
590 let Inst{7-6} = lane{1-0};
592 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
593 let Inst{7} = lane{0};
596 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
597 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
598 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
600 // ...with double-spaced registers:
601 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
602 let Inst{7-6} = lane{1-0};
604 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
605 let Inst{7} = lane{0};
608 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
609 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
611 // ...with address register writeback:
612 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
613 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
614 (ins addrmode6:$Rn, am6offset:$Rm,
615 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
616 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
617 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
621 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
622 let Inst{7-5} = lane{2-0};
624 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
625 let Inst{7-6} = lane{1-0};
627 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
628 let Inst{7} = lane{0};
631 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
632 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
633 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
635 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
636 let Inst{7-6} = lane{1-0};
638 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
639 let Inst{7} = lane{0};
642 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
643 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
645 // VLD3LN : Vector Load (single 3-element structure to one lane)
646 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
647 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
648 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
649 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
650 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
651 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
655 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
656 let Inst{7-5} = lane{2-0};
658 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
659 let Inst{7-6} = lane{1-0};
661 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
662 let Inst{7} = lane{0};
665 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
666 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
667 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
669 // ...with double-spaced registers:
670 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
671 let Inst{7-6} = lane{1-0};
673 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
674 let Inst{7} = lane{0};
677 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
678 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
680 // ...with address register writeback:
681 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
682 : NLdStLn<1, 0b10, op11_8, op7_4,
683 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
684 (ins addrmode6:$Rn, am6offset:$Rm,
685 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
686 IIC_VLD3lnu, "vld3", Dt,
687 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
688 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
691 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
692 let Inst{7-5} = lane{2-0};
694 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
695 let Inst{7-6} = lane{1-0};
697 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
698 let Inst{7} = lane{0};
701 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
702 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
703 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
705 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
706 let Inst{7-6} = lane{1-0};
708 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
709 let Inst{7} = lane{0};
712 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
713 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
715 // VLD4LN : Vector Load (single 4-element structure to one lane)
716 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
717 : NLdStLn<1, 0b10, op11_8, op7_4,
718 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
719 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
720 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
721 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
722 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
727 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
728 let Inst{7-5} = lane{2-0};
730 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
731 let Inst{7-6} = lane{1-0};
733 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
734 let Inst{7} = lane{0};
738 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
739 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
740 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
742 // ...with double-spaced registers:
743 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
744 let Inst{7-6} = lane{1-0};
746 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
747 let Inst{7} = lane{0};
751 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
752 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
754 // ...with address register writeback:
755 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
756 : NLdStLn<1, 0b10, op11_8, op7_4,
757 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
758 (ins addrmode6:$Rn, am6offset:$Rm,
759 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
760 IIC_VLD4ln, "vld4", Dt,
761 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
762 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
767 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
768 let Inst{7-5} = lane{2-0};
770 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
771 let Inst{7-6} = lane{1-0};
773 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
774 let Inst{7} = lane{0};
778 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
779 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
780 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
782 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
783 let Inst{7-6} = lane{1-0};
785 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
786 let Inst{7} = lane{0};
790 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
791 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
793 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
795 // VLD1DUP : Vector Load (single element to all lanes)
796 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
797 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6:$Rn),
798 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
799 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6:$Rn)))))]> {
803 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
804 let Pattern = [(set QPR:$dst,
805 (Ty (NEONvdup (i32 (LoadOp addrmode6:$addr)))))];
808 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
809 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
810 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
812 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
813 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
814 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
816 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
818 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
819 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
820 (ins addrmode6:$Rn), IIC_VLD1dup,
821 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
826 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
827 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
828 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
830 // ...with address register writeback:
831 class VLD1DUPWB<bits<4> op7_4, string Dt>
832 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
833 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu,
834 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
837 class VLD1QDUPWB<bits<4> op7_4, string Dt>
838 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
839 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu,
840 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
844 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
845 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
846 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
848 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
849 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
850 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
852 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
853 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
854 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
856 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
857 class VLD2DUP<bits<4> op7_4, string Dt>
858 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
859 (ins addrmode6:$Rn), IIC_VLD2dup,
860 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
865 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
866 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
867 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
869 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
870 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
871 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
873 // ...with double-spaced registers (not used for codegen):
874 def VLD2DUPd8Q : VLD2DUP<{0,0,1,?}, "8">;
875 def VLD2DUPd16Q : VLD2DUP<{0,1,1,?}, "16">;
876 def VLD2DUPd32Q : VLD2DUP<{1,0,1,?}, "32">;
878 // ...with address register writeback:
879 class VLD2DUPWB<bits<4> op7_4, string Dt>
880 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
881 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2dupu,
882 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
886 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
887 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
888 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
890 def VLD2DUPd8Q_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
891 def VLD2DUPd16Q_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
892 def VLD2DUPd32Q_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
894 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
895 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
896 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
898 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
899 class VLD3DUP<bits<4> op7_4, string Dt>
900 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
901 (ins addrmode6:$Rn), IIC_VLD3dup,
902 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
907 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
908 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
909 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
911 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
912 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
913 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
915 // ...with double-spaced registers (not used for codegen):
916 def VLD3DUPd8T : VLD3DUP<{0,0,1,?}, "8">;
917 def VLD3DUPd16T : VLD3DUP<{0,1,1,?}, "16">;
918 def VLD3DUPd32T : VLD3DUP<{1,0,1,?}, "32">;
920 // ...with address register writeback:
921 class VLD3DUPWB<bits<4> op7_4, string Dt>
922 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
923 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3dupu,
924 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
925 "$Rn.addr = $wb", []> {
929 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
930 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
931 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
933 def VLD3DUPd8T_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
934 def VLD3DUPd16T_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
935 def VLD3DUPd32T_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
937 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
938 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
939 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
941 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
942 class VLD4DUP<bits<4> op7_4, string Dt>
943 : NLdSt<1, 0b10, 0b1111, op7_4,
944 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
945 (ins addrmode6:$Rn), IIC_VLD4dup,
946 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
950 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8"> { let Inst{4} = Rn{4}; }
951 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16"> { let Inst{4} = Rn{4}; }
952 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> {
957 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
958 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
959 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
961 // ...with double-spaced registers (not used for codegen):
962 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8"> { let Inst{4} = Rn{4}; }
963 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16"> { let Inst{4} = Rn{4}; }
964 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> {
969 // ...with address register writeback:
970 class VLD4DUPWB<bits<4> op7_4, string Dt>
971 : NLdSt<1, 0b10, 0b1111, op7_4,
972 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
973 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4dupu,
974 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
975 "$Rn.addr = $wb", []>;
977 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8"> { let Inst{4} = Rn{4}; }
978 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16"> { let Inst{4} = Rn{4}; }
979 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> {
984 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8"> { let Inst{4} = Rn{4}; }
985 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16"> { let Inst{4} = Rn{4}; }
986 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> {
991 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
992 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
993 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
995 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
997 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
999 // Classes for VST* pseudo-instructions with multi-register operands.
1000 // These are expanded to real instructions after register allocation.
1001 class VSTQPseudo<InstrItinClass itin>
1002 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1003 class VSTQWBPseudo<InstrItinClass itin>
1004 : PseudoNLdSt<(outs GPR:$wb),
1005 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1006 "$addr.addr = $wb">;
1007 class VSTQQPseudo<InstrItinClass itin>
1008 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1009 class VSTQQWBPseudo<InstrItinClass itin>
1010 : PseudoNLdSt<(outs GPR:$wb),
1011 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1012 "$addr.addr = $wb">;
1013 class VSTQQQQWBPseudo<InstrItinClass itin>
1014 : PseudoNLdSt<(outs GPR:$wb),
1015 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1016 "$addr.addr = $wb">;
1018 // VST1 : Vector Store (multiple single elements)
1019 class VST1D<bits<4> op7_4, string Dt>
1020 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1021 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1023 let Inst{4} = Rn{4};
1025 class VST1Q<bits<4> op7_4, string Dt>
1026 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1027 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1028 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1030 let Inst{5-4} = Rn{5-4};
1033 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1034 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1035 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1036 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1038 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1039 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1040 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1041 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1043 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1044 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1045 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1046 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1048 // ...with address register writeback:
1049 class VST1DWB<bits<4> op7_4, string Dt>
1050 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1051 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1052 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1053 let Inst{4} = Rn{4};
1055 class VST1QWB<bits<4> op7_4, string Dt>
1056 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1057 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1058 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1059 "$Rn.addr = $wb", []> {
1060 let Inst{5-4} = Rn{5-4};
1063 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1064 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1065 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1066 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1068 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1069 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1070 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1071 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1073 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1074 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1075 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1076 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1078 // ...with 3 registers (some of these are only for the disassembler):
1079 class VST1D3<bits<4> op7_4, string Dt>
1080 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1081 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1082 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1084 let Inst{4} = Rn{4};
1086 class VST1D3WB<bits<4> op7_4, string Dt>
1087 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1088 (ins addrmode6:$Rn, am6offset:$Rm,
1089 DPR:$Vd, DPR:$src2, DPR:$src3),
1090 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1091 "$Rn.addr = $wb", []> {
1092 let Inst{4} = Rn{4};
1095 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1096 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1097 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1098 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1100 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1101 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1102 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1103 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1105 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1106 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1108 // ...with 4 registers (some of these are only for the disassembler):
1109 class VST1D4<bits<4> op7_4, string Dt>
1110 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1111 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1112 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1115 let Inst{5-4} = Rn{5-4};
1117 class VST1D4WB<bits<4> op7_4, string Dt>
1118 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1119 (ins addrmode6:$Rn, am6offset:$Rm,
1120 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1121 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1122 "$Rn.addr = $wb", []> {
1123 let Inst{5-4} = Rn{5-4};
1126 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1127 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1128 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1129 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1131 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1132 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1133 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1134 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1136 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1137 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1139 // VST2 : Vector Store (multiple 2-element structures)
1140 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1141 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1142 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1143 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1145 let Inst{5-4} = Rn{5-4};
1147 class VST2Q<bits<4> op7_4, string Dt>
1148 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1149 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1150 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1153 let Inst{5-4} = Rn{5-4};
1156 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1157 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1158 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1160 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1161 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1162 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1164 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1165 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1166 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1168 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1169 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1170 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1172 // ...with address register writeback:
1173 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1174 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1175 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1176 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1177 "$Rn.addr = $wb", []> {
1178 let Inst{5-4} = Rn{5-4};
1180 class VST2QWB<bits<4> op7_4, string Dt>
1181 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1182 (ins addrmode6:$Rn, am6offset:$Rm,
1183 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1184 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1185 "$Rn.addr = $wb", []> {
1186 let Inst{5-4} = Rn{5-4};
1189 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1190 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1191 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1193 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1194 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1195 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1197 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1198 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1199 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1201 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1202 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1203 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1205 // ...with double-spaced registers (for disassembly only):
1206 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1207 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1208 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1209 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1210 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1211 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1213 // VST3 : Vector Store (multiple 3-element structures)
1214 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1215 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1216 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1217 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1219 let Inst{4} = Rn{4};
1222 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1223 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1224 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1226 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1227 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1228 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1230 // ...with address register writeback:
1231 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1232 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1233 (ins addrmode6:$Rn, am6offset:$Rm,
1234 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1235 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1236 "$Rn.addr = $wb", []> {
1237 let Inst{4} = Rn{4};
1240 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1241 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1242 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1244 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1245 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1246 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1248 // ...with double-spaced registers (non-updating versions for disassembly only):
1249 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1250 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1251 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1252 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1253 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1254 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1256 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1257 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1258 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1260 // ...alternate versions to be allocated odd register numbers:
1261 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1262 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1263 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1265 // VST4 : Vector Store (multiple 4-element structures)
1266 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1267 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1268 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1269 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1272 let Inst{5-4} = Rn{5-4};
1275 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1276 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1277 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1279 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1280 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1281 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1283 // ...with address register writeback:
1284 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1285 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1286 (ins addrmode6:$Rn, am6offset:$Rm,
1287 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1288 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1289 "$Rn.addr = $wb", []> {
1290 let Inst{5-4} = Rn{5-4};
1293 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1294 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1295 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1297 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1298 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1299 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1301 // ...with double-spaced registers (non-updating versions for disassembly only):
1302 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1303 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1304 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1305 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1306 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1307 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1309 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1310 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1311 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1313 // ...alternate versions to be allocated odd register numbers:
1314 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1315 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1316 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1318 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1320 // Classes for VST*LN pseudo-instructions with multi-register operands.
1321 // These are expanded to real instructions after register allocation.
1322 class VSTQLNPseudo<InstrItinClass itin>
1323 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1325 class VSTQLNWBPseudo<InstrItinClass itin>
1326 : PseudoNLdSt<(outs GPR:$wb),
1327 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1328 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1329 class VSTQQLNPseudo<InstrItinClass itin>
1330 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1332 class VSTQQLNWBPseudo<InstrItinClass itin>
1333 : PseudoNLdSt<(outs GPR:$wb),
1334 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1335 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1336 class VSTQQQQLNPseudo<InstrItinClass itin>
1337 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1339 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1340 : PseudoNLdSt<(outs GPR:$wb),
1341 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1342 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1344 // VST1LN : Vector Store (single element from one lane)
1345 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1346 PatFrag StoreOp, SDNode ExtractOp>
1347 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1348 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1349 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1350 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1353 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1354 : VSTQLNPseudo<IIC_VST1ln> {
1355 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1359 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1361 let Inst{7-5} = lane{2-0};
1363 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1365 let Inst{7-6} = lane{1-0};
1366 let Inst{4} = Rn{5};
1368 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1369 let Inst{7} = lane{0};
1370 let Inst{5-4} = Rn{5-4};
1373 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1374 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1375 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1377 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1379 // ...with address register writeback:
1380 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1381 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1382 (ins addrmode6:$Rn, am6offset:$Rm,
1383 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1384 "\\{$Vd[$lane]\\}, $Rn$Rm",
1385 "$Rn.addr = $wb", []>;
1387 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1388 let Inst{7-5} = lane{2-0};
1390 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1391 let Inst{7-6} = lane{1-0};
1392 let Inst{4} = Rn{5};
1394 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1395 let Inst{7} = lane{0};
1396 let Inst{5-4} = Rn{5-4};
1399 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1400 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1401 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1403 // VST2LN : Vector Store (single 2-element structure from one lane)
1404 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1405 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1406 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1407 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1410 let Inst{4} = Rn{4};
1413 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1414 let Inst{7-5} = lane{2-0};
1416 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1417 let Inst{7-6} = lane{1-0};
1419 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1420 let Inst{7} = lane{0};
1423 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1424 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1425 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1427 // ...with double-spaced registers:
1428 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1429 let Inst{7-6} = lane{1-0};
1430 let Inst{4} = Rn{4};
1432 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1433 let Inst{7} = lane{0};
1434 let Inst{4} = Rn{4};
1437 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1438 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1440 // ...with address register writeback:
1441 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1442 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1443 (ins addrmode6:$addr, am6offset:$offset,
1444 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1445 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1446 "$addr.addr = $wb", []> {
1447 let Inst{4} = Rn{4};
1450 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1451 let Inst{7-5} = lane{2-0};
1453 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1454 let Inst{7-6} = lane{1-0};
1456 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1457 let Inst{7} = lane{0};
1460 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1461 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1462 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1464 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1465 let Inst{7-6} = lane{1-0};
1467 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1468 let Inst{7} = lane{0};
1471 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1472 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1474 // VST3LN : Vector Store (single 3-element structure from one lane)
1475 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1476 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1477 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1478 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1479 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1483 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1484 let Inst{7-5} = lane{2-0};
1486 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1487 let Inst{7-6} = lane{1-0};
1489 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1490 let Inst{7} = lane{0};
1493 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1494 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1495 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1497 // ...with double-spaced registers:
1498 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1499 let Inst{7-6} = lane{1-0};
1501 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1502 let Inst{7} = lane{0};
1505 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1506 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1508 // ...with address register writeback:
1509 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1510 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1511 (ins addrmode6:$Rn, am6offset:$Rm,
1512 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1513 IIC_VST3lnu, "vst3", Dt,
1514 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1515 "$Rn.addr = $wb", []>;
1517 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1518 let Inst{7-5} = lane{2-0};
1520 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1521 let Inst{7-6} = lane{1-0};
1523 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1524 let Inst{7} = lane{0};
1527 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1528 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1529 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1531 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1532 let Inst{7-6} = lane{1-0};
1534 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1535 let Inst{7} = lane{0};
1538 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1539 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1541 // VST4LN : Vector Store (single 4-element structure from one lane)
1542 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1543 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1544 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1545 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1546 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1549 let Inst{4} = Rn{4};
1552 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1553 let Inst{7-5} = lane{2-0};
1555 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1556 let Inst{7-6} = lane{1-0};
1558 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1559 let Inst{7} = lane{0};
1560 let Inst{5} = Rn{5};
1563 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1564 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1565 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1567 // ...with double-spaced registers:
1568 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1569 let Inst{7-6} = lane{1-0};
1571 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1572 let Inst{7} = lane{0};
1573 let Inst{5} = Rn{5};
1576 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1577 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1579 // ...with address register writeback:
1580 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1581 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1582 (ins addrmode6:$Rn, am6offset:$Rm,
1583 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1584 IIC_VST4lnu, "vst4", Dt,
1585 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1586 "$Rn.addr = $wb", []> {
1587 let Inst{4} = Rn{4};
1590 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1591 let Inst{7-5} = lane{2-0};
1593 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1594 let Inst{7-6} = lane{1-0};
1596 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1597 let Inst{7} = lane{0};
1598 let Inst{5} = Rn{5};
1601 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1602 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1603 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1605 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1606 let Inst{7-6} = lane{1-0};
1608 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1609 let Inst{7} = lane{0};
1610 let Inst{5} = Rn{5};
1613 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1614 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1616 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1619 //===----------------------------------------------------------------------===//
1620 // NEON pattern fragments
1621 //===----------------------------------------------------------------------===//
1623 // Extract D sub-registers of Q registers.
1624 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1625 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1626 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1628 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1629 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1630 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1632 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1633 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1634 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1636 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1637 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1638 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1641 // Extract S sub-registers of Q/D registers.
1642 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1643 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1644 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1647 // Translate lane numbers from Q registers to D subregs.
1648 def SubReg_i8_lane : SDNodeXForm<imm, [{
1649 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1651 def SubReg_i16_lane : SDNodeXForm<imm, [{
1652 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1654 def SubReg_i32_lane : SDNodeXForm<imm, [{
1655 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1658 //===----------------------------------------------------------------------===//
1659 // Instruction Classes
1660 //===----------------------------------------------------------------------===//
1662 // Basic 2-register operations: single-, double- and quad-register.
1663 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1664 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1665 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1666 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1667 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
1668 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
1669 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1670 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1671 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1672 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1673 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
1674 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
1675 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1676 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1677 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1678 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1679 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
1680 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
1682 // Basic 2-register intrinsics, both double- and quad-register.
1683 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1684 bits<2> op17_16, bits<5> op11_7, bit op4,
1685 InstrItinClass itin, string OpcodeStr, string Dt,
1686 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1687 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1688 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1689 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1690 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1691 bits<2> op17_16, bits<5> op11_7, bit op4,
1692 InstrItinClass itin, string OpcodeStr, string Dt,
1693 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1694 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1695 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1696 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1698 // Narrow 2-register operations.
1699 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1700 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1701 InstrItinClass itin, string OpcodeStr, string Dt,
1702 ValueType TyD, ValueType TyQ, SDNode OpNode>
1703 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1704 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1705 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
1707 // Narrow 2-register intrinsics.
1708 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1709 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1710 InstrItinClass itin, string OpcodeStr, string Dt,
1711 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1712 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
1713 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1714 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
1716 // Long 2-register operations (currently only used for VMOVL).
1717 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1718 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1719 InstrItinClass itin, string OpcodeStr, string Dt,
1720 ValueType TyQ, ValueType TyD, SDNode OpNode>
1721 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
1722 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
1723 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
1725 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1726 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1727 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
1728 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1729 OpcodeStr, Dt, "$dst1, $dst2",
1730 "$src1 = $dst1, $src2 = $dst2", []>;
1731 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1732 InstrItinClass itin, string OpcodeStr, string Dt>
1733 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
1734 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
1735 "$src1 = $dst1, $src2 = $dst2", []>;
1737 // Basic 3-register operations: single-, double- and quad-register.
1738 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1739 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1740 SDNode OpNode, bit Commutable>
1741 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1742 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1743 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1744 let isCommutable = Commutable;
1747 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1748 InstrItinClass itin, string OpcodeStr, string Dt,
1749 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1750 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1751 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1752 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1753 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1754 let isCommutable = Commutable;
1756 // Same as N3VD but no data type.
1757 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1758 InstrItinClass itin, string OpcodeStr,
1759 ValueType ResTy, ValueType OpTy,
1760 SDNode OpNode, bit Commutable>
1761 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1762 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1763 OpcodeStr, "$Vd, $Vn, $Vm", "",
1764 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1765 let isCommutable = Commutable;
1768 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1769 InstrItinClass itin, string OpcodeStr, string Dt,
1770 ValueType Ty, SDNode ShOp>
1771 : N3V<0, 1, op21_20, op11_8, 1, 0,
1772 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1773 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1774 [(set (Ty DPR:$dst),
1775 (Ty (ShOp (Ty DPR:$src1),
1776 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1777 let isCommutable = 0;
1779 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1780 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1781 : N3V<0, 1, op21_20, op11_8, 1, 0,
1782 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1783 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1784 [(set (Ty DPR:$dst),
1785 (Ty (ShOp (Ty DPR:$src1),
1786 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1787 let isCommutable = 0;
1790 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1791 InstrItinClass itin, string OpcodeStr, string Dt,
1792 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1793 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1794 (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
1795 OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
1796 [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
1797 let isCommutable = Commutable;
1799 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1800 InstrItinClass itin, string OpcodeStr,
1801 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1802 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1803 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1804 OpcodeStr, "$dst, $src1, $src2", "",
1805 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1806 let isCommutable = Commutable;
1808 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1809 InstrItinClass itin, string OpcodeStr, string Dt,
1810 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1811 : N3V<1, 1, op21_20, op11_8, 1, 0,
1812 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1813 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1814 [(set (ResTy QPR:$dst),
1815 (ResTy (ShOp (ResTy QPR:$src1),
1816 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1818 let isCommutable = 0;
1820 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1821 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1822 : N3V<1, 1, op21_20, op11_8, 1, 0,
1823 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1824 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1825 [(set (ResTy QPR:$dst),
1826 (ResTy (ShOp (ResTy QPR:$src1),
1827 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1829 let isCommutable = 0;
1832 // Basic 3-register intrinsics, both double- and quad-register.
1833 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1834 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1835 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1836 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1837 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1838 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1839 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1840 let isCommutable = Commutable;
1842 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1843 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1844 : N3V<0, 1, op21_20, op11_8, 1, 0,
1845 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1846 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1847 [(set (Ty DPR:$dst),
1848 (Ty (IntOp (Ty DPR:$src1),
1849 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1851 let isCommutable = 0;
1853 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1854 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1855 : N3V<0, 1, op21_20, op11_8, 1, 0,
1856 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1857 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1858 [(set (Ty DPR:$dst),
1859 (Ty (IntOp (Ty DPR:$src1),
1860 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1861 let isCommutable = 0;
1863 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1864 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1865 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1866 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1867 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1868 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1869 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1870 let isCommutable = 0;
1873 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1874 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1875 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1876 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1877 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1878 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1879 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1880 let isCommutable = Commutable;
1882 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1883 string OpcodeStr, string Dt,
1884 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1885 : N3V<1, 1, op21_20, op11_8, 1, 0,
1886 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1887 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1888 [(set (ResTy QPR:$dst),
1889 (ResTy (IntOp (ResTy QPR:$src1),
1890 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1892 let isCommutable = 0;
1894 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1895 string OpcodeStr, string Dt,
1896 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1897 : N3V<1, 1, op21_20, op11_8, 1, 0,
1898 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1899 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1900 [(set (ResTy QPR:$dst),
1901 (ResTy (IntOp (ResTy QPR:$src1),
1902 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1904 let isCommutable = 0;
1906 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1907 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1908 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1909 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1910 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1911 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1912 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1913 let isCommutable = 0;
1916 // Multiply-Add/Sub operations: single-, double- and quad-register.
1917 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1918 InstrItinClass itin, string OpcodeStr, string Dt,
1919 ValueType Ty, SDNode MulOp, SDNode OpNode>
1920 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1921 (outs DPR_VFP2:$dst),
1922 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1923 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1925 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1926 InstrItinClass itin, string OpcodeStr, string Dt,
1927 ValueType Ty, SDNode MulOp, SDNode OpNode>
1928 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1929 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1930 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1931 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1932 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1934 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1935 string OpcodeStr, string Dt,
1936 ValueType Ty, SDNode MulOp, SDNode ShOp>
1937 : N3V<0, 1, op21_20, op11_8, 1, 0,
1939 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1941 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1942 [(set (Ty DPR:$dst),
1943 (Ty (ShOp (Ty DPR:$src1),
1944 (Ty (MulOp DPR:$src2,
1945 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1947 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1948 string OpcodeStr, string Dt,
1949 ValueType Ty, SDNode MulOp, SDNode ShOp>
1950 : N3V<0, 1, op21_20, op11_8, 1, 0,
1952 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1954 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1956 (Ty (ShOp (Ty DPR:$src1),
1958 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1961 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1962 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1963 SDNode MulOp, SDNode OpNode>
1964 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1965 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1966 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1967 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1968 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1969 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1970 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1971 SDNode MulOp, SDNode ShOp>
1972 : N3V<1, 1, op21_20, op11_8, 1, 0,
1974 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1976 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1977 [(set (ResTy QPR:$dst),
1978 (ResTy (ShOp (ResTy QPR:$src1),
1979 (ResTy (MulOp QPR:$src2,
1980 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1982 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1983 string OpcodeStr, string Dt,
1984 ValueType ResTy, ValueType OpTy,
1985 SDNode MulOp, SDNode ShOp>
1986 : N3V<1, 1, op21_20, op11_8, 1, 0,
1988 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1990 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1991 [(set (ResTy QPR:$dst),
1992 (ResTy (ShOp (ResTy QPR:$src1),
1993 (ResTy (MulOp QPR:$src2,
1994 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1997 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1998 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1999 InstrItinClass itin, string OpcodeStr, string Dt,
2000 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2001 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2002 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2003 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2004 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2005 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2006 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2007 InstrItinClass itin, string OpcodeStr, string Dt,
2008 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2009 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2010 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2011 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2012 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2013 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2015 // Neon 3-argument intrinsics, both double- and quad-register.
2016 // The destination register is also used as the first source operand register.
2017 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2018 InstrItinClass itin, string OpcodeStr, string Dt,
2019 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2020 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2021 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
2022 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
2023 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
2024 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
2025 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2026 InstrItinClass itin, string OpcodeStr, string Dt,
2027 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2028 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2029 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
2030 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
2031 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
2032 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
2034 // Long Multiply-Add/Sub operations.
2035 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2036 InstrItinClass itin, string OpcodeStr, string Dt,
2037 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2038 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2039 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2040 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2041 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2042 (TyQ (MulOp (TyD DPR:$Vn),
2043 (TyD DPR:$Vm)))))]>;
2044 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2045 InstrItinClass itin, string OpcodeStr, string Dt,
2046 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2047 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
2048 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
2050 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
2052 (OpNode (TyQ QPR:$src1),
2053 (TyQ (MulOp (TyD DPR:$src2),
2054 (TyD (NEONvduplane (TyD DPR_VFP2:$src3),
2056 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2057 InstrItinClass itin, string OpcodeStr, string Dt,
2058 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2059 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst),
2060 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
2062 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
2064 (OpNode (TyQ QPR:$src1),
2065 (TyQ (MulOp (TyD DPR:$src2),
2066 (TyD (NEONvduplane (TyD DPR_8:$src3),
2069 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2070 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2071 InstrItinClass itin, string OpcodeStr, string Dt,
2072 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2074 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2075 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2076 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2077 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2078 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2079 (TyD DPR:$Vm)))))))]>;
2081 // Neon Long 3-argument intrinsic. The destination register is
2082 // a quad-register and is also used as the first source operand register.
2083 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2084 InstrItinClass itin, string OpcodeStr, string Dt,
2085 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2086 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2087 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2088 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2090 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2091 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2092 string OpcodeStr, string Dt,
2093 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2094 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2096 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
2098 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
2099 [(set (ResTy QPR:$dst),
2100 (ResTy (IntOp (ResTy QPR:$src1),
2102 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
2104 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2105 InstrItinClass itin, string OpcodeStr, string Dt,
2106 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2107 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2109 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
2111 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
2112 [(set (ResTy QPR:$dst),
2113 (ResTy (IntOp (ResTy QPR:$src1),
2115 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
2118 // Narrowing 3-register intrinsics.
2119 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2120 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2121 Intrinsic IntOp, bit Commutable>
2122 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2123 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
2124 OpcodeStr, Dt, "$dst, $src1, $src2", "",
2125 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
2126 let isCommutable = Commutable;
2129 // Long 3-register operations.
2130 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2131 InstrItinClass itin, string OpcodeStr, string Dt,
2132 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2133 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2134 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
2135 OpcodeStr, Dt, "$dst, $src1, $src2", "",
2136 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> {
2137 let isCommutable = Commutable;
2139 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2140 InstrItinClass itin, string OpcodeStr, string Dt,
2141 ValueType TyQ, ValueType TyD, SDNode OpNode>
2142 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2143 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
2144 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2146 (TyQ (OpNode (TyD DPR:$src1),
2147 (TyD (NEONvduplane (TyD DPR_VFP2:$src2),imm:$lane)))))]>;
2148 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2149 InstrItinClass itin, string OpcodeStr, string Dt,
2150 ValueType TyQ, ValueType TyD, SDNode OpNode>
2151 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2152 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
2153 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2155 (TyQ (OpNode (TyD DPR:$src1),
2156 (TyD (NEONvduplane (TyD DPR_8:$src2), imm:$lane)))))]>;
2158 // Long 3-register operations with explicitly extended operands.
2159 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2160 InstrItinClass itin, string OpcodeStr, string Dt,
2161 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2163 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2164 (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
2165 OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
2166 [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
2167 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
2168 let isCommutable = Commutable;
2171 // Long 3-register intrinsics with explicit extend (VABDL).
2172 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2173 InstrItinClass itin, string OpcodeStr, string Dt,
2174 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2176 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2177 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
2178 OpcodeStr, Dt, "$dst, $src1, $src2", "",
2179 [(set QPR:$dst, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src1),
2180 (TyD DPR:$src2))))))]> {
2181 let isCommutable = Commutable;
2184 // Long 3-register intrinsics.
2185 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2186 InstrItinClass itin, string OpcodeStr, string Dt,
2187 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2188 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2189 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
2190 OpcodeStr, Dt, "$dst, $src1, $src2", "",
2191 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
2192 let isCommutable = Commutable;
2194 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2195 string OpcodeStr, string Dt,
2196 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2197 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2198 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
2199 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2200 [(set (ResTy QPR:$dst),
2201 (ResTy (IntOp (OpTy DPR:$src1),
2202 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
2204 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2205 InstrItinClass itin, string OpcodeStr, string Dt,
2206 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2207 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2208 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
2209 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
2210 [(set (ResTy QPR:$dst),
2211 (ResTy (IntOp (OpTy DPR:$src1),
2212 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
2215 // Wide 3-register operations.
2216 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2217 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2218 SDNode OpNode, SDNode ExtOp, bit Commutable>
2219 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2220 (outs QPR:$Qd), (ins QPR:$Qn, DPR:$Dm), N3RegFrm, IIC_VSUBiD,
2221 OpcodeStr, Dt, "$Qd, $Qn, $Dm", "",
2222 [(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
2223 (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
2224 let isCommutable = Commutable;
2227 // Pairwise long 2-register intrinsics, both double- and quad-register.
2228 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2229 bits<2> op17_16, bits<5> op11_7, bit op4,
2230 string OpcodeStr, string Dt,
2231 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2232 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
2233 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2234 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
2235 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2236 bits<2> op17_16, bits<5> op11_7, bit op4,
2237 string OpcodeStr, string Dt,
2238 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
2240 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2241 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
2243 // Pairwise long 2-register accumulate intrinsics,
2244 // both double- and quad-register.
2245 // The destination register is also used as the first source operand register.
2246 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2247 bits<2> op17_16, bits<5> op11_7, bit op4,
2248 string OpcodeStr, string Dt,
2249 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2250 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2251 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2252 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2253 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2254 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2255 bits<2> op17_16, bits<5> op11_7, bit op4,
2256 string OpcodeStr, string Dt,
2257 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2258 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2259 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2260 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2261 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2263 // Shift by immediate,
2264 // both double- and quad-register.
2265 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2266 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2267 ValueType Ty, SDNode OpNode>
2268 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2269 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
2270 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2271 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
2272 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2273 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2274 ValueType Ty, SDNode OpNode>
2275 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2276 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
2277 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2278 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
2280 // Long shift by immediate.
2281 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2282 string OpcodeStr, string Dt,
2283 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2284 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2285 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
2286 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2287 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
2288 (i32 imm:$SIMM))))]>;
2290 // Narrow shift by immediate.
2291 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2292 InstrItinClass itin, string OpcodeStr, string Dt,
2293 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2294 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2295 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
2296 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
2297 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
2298 (i32 imm:$SIMM))))]>;
2300 // Shift right by immediate and accumulate,
2301 // both double- and quad-register.
2302 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2303 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2304 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2305 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2306 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2307 [(set DPR:$Vd, (Ty (add DPR:$src1,
2308 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2309 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2310 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2311 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2312 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2313 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2314 [(set QPR:$Vd, (Ty (add QPR:$src1,
2315 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2317 // Shift by immediate and insert,
2318 // both double- and quad-register.
2319 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2320 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2321 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2322 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2323 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2324 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2325 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2326 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2327 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2328 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2329 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2330 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2332 // Convert, with fractional bits immediate,
2333 // both double- and quad-register.
2334 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2335 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2337 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2338 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2339 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2340 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2341 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2342 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2344 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2345 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2346 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2347 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2349 //===----------------------------------------------------------------------===//
2351 //===----------------------------------------------------------------------===//
2353 // Abbreviations used in multiclass suffixes:
2354 // Q = quarter int (8 bit) elements
2355 // H = half int (16 bit) elements
2356 // S = single int (32 bit) elements
2357 // D = double int (64 bit) elements
2359 // Neon 2-register vector operations -- for disassembly only.
2361 // First with only element sizes of 8, 16 and 32 bits:
2362 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2363 bits<5> op11_7, bit op4, string opc, string Dt,
2364 string asm, SDNode OpNode> {
2365 // 64-bit vector types.
2366 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2367 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2368 opc, !strconcat(Dt, "8"), asm, "",
2369 [(set DPR:$dst, (v8i8 (OpNode (v8i8 DPR:$src))))]>;
2370 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2371 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2372 opc, !strconcat(Dt, "16"), asm, "",
2373 [(set DPR:$dst, (v4i16 (OpNode (v4i16 DPR:$src))))]>;
2374 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2375 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2376 opc, !strconcat(Dt, "32"), asm, "",
2377 [(set DPR:$dst, (v2i32 (OpNode (v2i32 DPR:$src))))]>;
2378 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2379 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2380 opc, "f32", asm, "",
2381 [(set DPR:$dst, (v2f32 (OpNode (v2f32 DPR:$src))))]> {
2382 let Inst{10} = 1; // overwrite F = 1
2385 // 128-bit vector types.
2386 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2387 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2388 opc, !strconcat(Dt, "8"), asm, "",
2389 [(set QPR:$dst, (v16i8 (OpNode (v16i8 QPR:$src))))]>;
2390 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2391 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2392 opc, !strconcat(Dt, "16"), asm, "",
2393 [(set QPR:$dst, (v8i16 (OpNode (v8i16 QPR:$src))))]>;
2394 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2395 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2396 opc, !strconcat(Dt, "32"), asm, "",
2397 [(set QPR:$dst, (v4i32 (OpNode (v4i32 QPR:$src))))]>;
2398 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2399 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2400 opc, "f32", asm, "",
2401 [(set QPR:$dst, (v4f32 (OpNode (v4f32 QPR:$src))))]> {
2402 let Inst{10} = 1; // overwrite F = 1
2406 // Neon 3-register vector operations.
2408 // First with only element sizes of 8, 16 and 32 bits:
2409 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2410 InstrItinClass itinD16, InstrItinClass itinD32,
2411 InstrItinClass itinQ16, InstrItinClass itinQ32,
2412 string OpcodeStr, string Dt,
2413 SDNode OpNode, bit Commutable = 0> {
2414 // 64-bit vector types.
2415 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2416 OpcodeStr, !strconcat(Dt, "8"),
2417 v8i8, v8i8, OpNode, Commutable>;
2418 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2419 OpcodeStr, !strconcat(Dt, "16"),
2420 v4i16, v4i16, OpNode, Commutable>;
2421 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2422 OpcodeStr, !strconcat(Dt, "32"),
2423 v2i32, v2i32, OpNode, Commutable>;
2425 // 128-bit vector types.
2426 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2427 OpcodeStr, !strconcat(Dt, "8"),
2428 v16i8, v16i8, OpNode, Commutable>;
2429 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2430 OpcodeStr, !strconcat(Dt, "16"),
2431 v8i16, v8i16, OpNode, Commutable>;
2432 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2433 OpcodeStr, !strconcat(Dt, "32"),
2434 v4i32, v4i32, OpNode, Commutable>;
2437 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2438 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2440 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2442 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2443 v8i16, v4i16, ShOp>;
2444 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2445 v4i32, v2i32, ShOp>;
2448 // ....then also with element size 64 bits:
2449 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2450 InstrItinClass itinD, InstrItinClass itinQ,
2451 string OpcodeStr, string Dt,
2452 SDNode OpNode, bit Commutable = 0>
2453 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2454 OpcodeStr, Dt, OpNode, Commutable> {
2455 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2456 OpcodeStr, !strconcat(Dt, "64"),
2457 v1i64, v1i64, OpNode, Commutable>;
2458 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2459 OpcodeStr, !strconcat(Dt, "64"),
2460 v2i64, v2i64, OpNode, Commutable>;
2464 // Neon Narrowing 2-register vector operations,
2465 // source operand element sizes of 16, 32 and 64 bits:
2466 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2467 bits<5> op11_7, bit op6, bit op4,
2468 InstrItinClass itin, string OpcodeStr, string Dt,
2470 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2471 itin, OpcodeStr, !strconcat(Dt, "16"),
2472 v8i8, v8i16, OpNode>;
2473 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2474 itin, OpcodeStr, !strconcat(Dt, "32"),
2475 v4i16, v4i32, OpNode>;
2476 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2477 itin, OpcodeStr, !strconcat(Dt, "64"),
2478 v2i32, v2i64, OpNode>;
2481 // Neon Narrowing 2-register vector intrinsics,
2482 // source operand element sizes of 16, 32 and 64 bits:
2483 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2484 bits<5> op11_7, bit op6, bit op4,
2485 InstrItinClass itin, string OpcodeStr, string Dt,
2487 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2488 itin, OpcodeStr, !strconcat(Dt, "16"),
2489 v8i8, v8i16, IntOp>;
2490 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2491 itin, OpcodeStr, !strconcat(Dt, "32"),
2492 v4i16, v4i32, IntOp>;
2493 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2494 itin, OpcodeStr, !strconcat(Dt, "64"),
2495 v2i32, v2i64, IntOp>;
2499 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2500 // source operand element sizes of 16, 32 and 64 bits:
2501 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2502 string OpcodeStr, string Dt, SDNode OpNode> {
2503 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2504 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2505 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2506 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2507 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2508 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2512 // Neon 3-register vector intrinsics.
2514 // First with only element sizes of 16 and 32 bits:
2515 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2516 InstrItinClass itinD16, InstrItinClass itinD32,
2517 InstrItinClass itinQ16, InstrItinClass itinQ32,
2518 string OpcodeStr, string Dt,
2519 Intrinsic IntOp, bit Commutable = 0> {
2520 // 64-bit vector types.
2521 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2522 OpcodeStr, !strconcat(Dt, "16"),
2523 v4i16, v4i16, IntOp, Commutable>;
2524 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2525 OpcodeStr, !strconcat(Dt, "32"),
2526 v2i32, v2i32, IntOp, Commutable>;
2528 // 128-bit vector types.
2529 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2530 OpcodeStr, !strconcat(Dt, "16"),
2531 v8i16, v8i16, IntOp, Commutable>;
2532 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2533 OpcodeStr, !strconcat(Dt, "32"),
2534 v4i32, v4i32, IntOp, Commutable>;
2536 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2537 InstrItinClass itinD16, InstrItinClass itinD32,
2538 InstrItinClass itinQ16, InstrItinClass itinQ32,
2539 string OpcodeStr, string Dt,
2541 // 64-bit vector types.
2542 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2543 OpcodeStr, !strconcat(Dt, "16"),
2544 v4i16, v4i16, IntOp>;
2545 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2546 OpcodeStr, !strconcat(Dt, "32"),
2547 v2i32, v2i32, IntOp>;
2549 // 128-bit vector types.
2550 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2551 OpcodeStr, !strconcat(Dt, "16"),
2552 v8i16, v8i16, IntOp>;
2553 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2554 OpcodeStr, !strconcat(Dt, "32"),
2555 v4i32, v4i32, IntOp>;
2558 multiclass N3VIntSL_HS<bits<4> op11_8,
2559 InstrItinClass itinD16, InstrItinClass itinD32,
2560 InstrItinClass itinQ16, InstrItinClass itinQ32,
2561 string OpcodeStr, string Dt, Intrinsic IntOp> {
2562 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2563 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2564 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2565 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2566 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2567 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2568 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2569 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2572 // ....then also with element size of 8 bits:
2573 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2574 InstrItinClass itinD16, InstrItinClass itinD32,
2575 InstrItinClass itinQ16, InstrItinClass itinQ32,
2576 string OpcodeStr, string Dt,
2577 Intrinsic IntOp, bit Commutable = 0>
2578 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2579 OpcodeStr, Dt, IntOp, Commutable> {
2580 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2581 OpcodeStr, !strconcat(Dt, "8"),
2582 v8i8, v8i8, IntOp, Commutable>;
2583 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2584 OpcodeStr, !strconcat(Dt, "8"),
2585 v16i8, v16i8, IntOp, Commutable>;
2587 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2588 InstrItinClass itinD16, InstrItinClass itinD32,
2589 InstrItinClass itinQ16, InstrItinClass itinQ32,
2590 string OpcodeStr, string Dt,
2592 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2593 OpcodeStr, Dt, IntOp> {
2594 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2595 OpcodeStr, !strconcat(Dt, "8"),
2597 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2598 OpcodeStr, !strconcat(Dt, "8"),
2599 v16i8, v16i8, IntOp>;
2603 // ....then also with element size of 64 bits:
2604 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2605 InstrItinClass itinD16, InstrItinClass itinD32,
2606 InstrItinClass itinQ16, InstrItinClass itinQ32,
2607 string OpcodeStr, string Dt,
2608 Intrinsic IntOp, bit Commutable = 0>
2609 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2610 OpcodeStr, Dt, IntOp, Commutable> {
2611 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2612 OpcodeStr, !strconcat(Dt, "64"),
2613 v1i64, v1i64, IntOp, Commutable>;
2614 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2615 OpcodeStr, !strconcat(Dt, "64"),
2616 v2i64, v2i64, IntOp, Commutable>;
2618 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2619 InstrItinClass itinD16, InstrItinClass itinD32,
2620 InstrItinClass itinQ16, InstrItinClass itinQ32,
2621 string OpcodeStr, string Dt,
2623 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2624 OpcodeStr, Dt, IntOp> {
2625 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2626 OpcodeStr, !strconcat(Dt, "64"),
2627 v1i64, v1i64, IntOp>;
2628 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2629 OpcodeStr, !strconcat(Dt, "64"),
2630 v2i64, v2i64, IntOp>;
2633 // Neon Narrowing 3-register vector intrinsics,
2634 // source operand element sizes of 16, 32 and 64 bits:
2635 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2636 string OpcodeStr, string Dt,
2637 Intrinsic IntOp, bit Commutable = 0> {
2638 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2639 OpcodeStr, !strconcat(Dt, "16"),
2640 v8i8, v8i16, IntOp, Commutable>;
2641 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2642 OpcodeStr, !strconcat(Dt, "32"),
2643 v4i16, v4i32, IntOp, Commutable>;
2644 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2645 OpcodeStr, !strconcat(Dt, "64"),
2646 v2i32, v2i64, IntOp, Commutable>;
2650 // Neon Long 3-register vector operations.
2652 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2653 InstrItinClass itin16, InstrItinClass itin32,
2654 string OpcodeStr, string Dt,
2655 SDNode OpNode, bit Commutable = 0> {
2656 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2657 OpcodeStr, !strconcat(Dt, "8"),
2658 v8i16, v8i8, OpNode, Commutable>;
2659 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2660 OpcodeStr, !strconcat(Dt, "16"),
2661 v4i32, v4i16, OpNode, Commutable>;
2662 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2663 OpcodeStr, !strconcat(Dt, "32"),
2664 v2i64, v2i32, OpNode, Commutable>;
2667 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2668 InstrItinClass itin, string OpcodeStr, string Dt,
2670 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2671 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2672 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2673 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2676 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2677 InstrItinClass itin16, InstrItinClass itin32,
2678 string OpcodeStr, string Dt,
2679 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2680 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2681 OpcodeStr, !strconcat(Dt, "8"),
2682 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2683 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2684 OpcodeStr, !strconcat(Dt, "16"),
2685 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2686 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2687 OpcodeStr, !strconcat(Dt, "32"),
2688 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2691 // Neon Long 3-register vector intrinsics.
2693 // First with only element sizes of 16 and 32 bits:
2694 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2695 InstrItinClass itin16, InstrItinClass itin32,
2696 string OpcodeStr, string Dt,
2697 Intrinsic IntOp, bit Commutable = 0> {
2698 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2699 OpcodeStr, !strconcat(Dt, "16"),
2700 v4i32, v4i16, IntOp, Commutable>;
2701 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2702 OpcodeStr, !strconcat(Dt, "32"),
2703 v2i64, v2i32, IntOp, Commutable>;
2706 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2707 InstrItinClass itin, string OpcodeStr, string Dt,
2709 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2710 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2711 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2712 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2715 // ....then also with element size of 8 bits:
2716 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2717 InstrItinClass itin16, InstrItinClass itin32,
2718 string OpcodeStr, string Dt,
2719 Intrinsic IntOp, bit Commutable = 0>
2720 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2721 IntOp, Commutable> {
2722 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2723 OpcodeStr, !strconcat(Dt, "8"),
2724 v8i16, v8i8, IntOp, Commutable>;
2727 // ....with explicit extend (VABDL).
2728 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2729 InstrItinClass itin, string OpcodeStr, string Dt,
2730 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2731 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2732 OpcodeStr, !strconcat(Dt, "8"),
2733 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2734 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2735 OpcodeStr, !strconcat(Dt, "16"),
2736 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2737 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2738 OpcodeStr, !strconcat(Dt, "32"),
2739 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2743 // Neon Wide 3-register vector intrinsics,
2744 // source operand element sizes of 8, 16 and 32 bits:
2745 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2746 string OpcodeStr, string Dt,
2747 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2748 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2749 OpcodeStr, !strconcat(Dt, "8"),
2750 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2751 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2752 OpcodeStr, !strconcat(Dt, "16"),
2753 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2754 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2755 OpcodeStr, !strconcat(Dt, "32"),
2756 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2760 // Neon Multiply-Op vector operations,
2761 // element sizes of 8, 16 and 32 bits:
2762 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2763 InstrItinClass itinD16, InstrItinClass itinD32,
2764 InstrItinClass itinQ16, InstrItinClass itinQ32,
2765 string OpcodeStr, string Dt, SDNode OpNode> {
2766 // 64-bit vector types.
2767 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2768 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2769 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2770 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2771 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2772 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2774 // 128-bit vector types.
2775 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2776 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2777 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2778 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2779 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2780 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2783 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2784 InstrItinClass itinD16, InstrItinClass itinD32,
2785 InstrItinClass itinQ16, InstrItinClass itinQ32,
2786 string OpcodeStr, string Dt, SDNode ShOp> {
2787 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2788 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2789 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2790 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2791 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2792 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2794 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2795 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2799 // Neon Intrinsic-Op vector operations,
2800 // element sizes of 8, 16 and 32 bits:
2801 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2802 InstrItinClass itinD, InstrItinClass itinQ,
2803 string OpcodeStr, string Dt, Intrinsic IntOp,
2805 // 64-bit vector types.
2806 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2807 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2808 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2809 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2810 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2811 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2813 // 128-bit vector types.
2814 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2815 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2816 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2817 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2818 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2819 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2822 // Neon 3-argument intrinsics,
2823 // element sizes of 8, 16 and 32 bits:
2824 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2825 InstrItinClass itinD, InstrItinClass itinQ,
2826 string OpcodeStr, string Dt, Intrinsic IntOp> {
2827 // 64-bit vector types.
2828 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2829 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2830 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2831 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2832 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2833 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2835 // 128-bit vector types.
2836 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2837 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2838 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2839 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2840 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2841 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2845 // Neon Long Multiply-Op vector operations,
2846 // element sizes of 8, 16 and 32 bits:
2847 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2848 InstrItinClass itin16, InstrItinClass itin32,
2849 string OpcodeStr, string Dt, SDNode MulOp,
2851 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2852 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2853 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2854 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2855 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2856 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2859 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2860 string Dt, SDNode MulOp, SDNode OpNode> {
2861 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2862 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2863 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2864 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2868 // Neon Long 3-argument intrinsics.
2870 // First with only element sizes of 16 and 32 bits:
2871 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2872 InstrItinClass itin16, InstrItinClass itin32,
2873 string OpcodeStr, string Dt, Intrinsic IntOp> {
2874 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2875 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2876 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2877 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2880 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2881 string OpcodeStr, string Dt, Intrinsic IntOp> {
2882 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2883 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2884 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2885 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2888 // ....then also with element size of 8 bits:
2889 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2890 InstrItinClass itin16, InstrItinClass itin32,
2891 string OpcodeStr, string Dt, Intrinsic IntOp>
2892 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2893 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2894 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2897 // ....with explicit extend (VABAL).
2898 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2899 InstrItinClass itin, string OpcodeStr, string Dt,
2900 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2901 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2902 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2903 IntOp, ExtOp, OpNode>;
2904 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2905 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2906 IntOp, ExtOp, OpNode>;
2907 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2908 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2909 IntOp, ExtOp, OpNode>;
2913 // Neon 2-register vector intrinsics,
2914 // element sizes of 8, 16 and 32 bits:
2915 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2916 bits<5> op11_7, bit op4,
2917 InstrItinClass itinD, InstrItinClass itinQ,
2918 string OpcodeStr, string Dt, Intrinsic IntOp> {
2919 // 64-bit vector types.
2920 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2921 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2922 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2923 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2924 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2925 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2927 // 128-bit vector types.
2928 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2929 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2930 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2931 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2932 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2933 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2937 // Neon Pairwise long 2-register intrinsics,
2938 // element sizes of 8, 16 and 32 bits:
2939 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2940 bits<5> op11_7, bit op4,
2941 string OpcodeStr, string Dt, Intrinsic IntOp> {
2942 // 64-bit vector types.
2943 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2944 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2945 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2946 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2947 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2948 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2950 // 128-bit vector types.
2951 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2952 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2953 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2954 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2955 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2956 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2960 // Neon Pairwise long 2-register accumulate intrinsics,
2961 // element sizes of 8, 16 and 32 bits:
2962 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2963 bits<5> op11_7, bit op4,
2964 string OpcodeStr, string Dt, Intrinsic IntOp> {
2965 // 64-bit vector types.
2966 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2967 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2968 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2969 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2970 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2971 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2973 // 128-bit vector types.
2974 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2976 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2977 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2978 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2979 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2983 // Neon 2-register vector shift by immediate,
2984 // with f of either N2RegVShLFrm or N2RegVShRFrm
2985 // element sizes of 8, 16, 32 and 64 bits:
2986 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2987 InstrItinClass itin, string OpcodeStr, string Dt,
2988 SDNode OpNode, Format f> {
2989 // 64-bit vector types.
2990 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2991 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2992 let Inst{21-19} = 0b001; // imm6 = 001xxx
2994 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2995 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2996 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2998 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2999 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3000 let Inst{21} = 0b1; // imm6 = 1xxxxx
3002 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
3003 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3006 // 128-bit vector types.
3007 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3008 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3009 let Inst{21-19} = 0b001; // imm6 = 001xxx
3011 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3012 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3013 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3015 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3016 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3017 let Inst{21} = 0b1; // imm6 = 1xxxxx
3019 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
3020 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3024 // Neon Shift-Accumulate vector operations,
3025 // element sizes of 8, 16, 32 and 64 bits:
3026 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3027 string OpcodeStr, string Dt, SDNode ShOp> {
3028 // 64-bit vector types.
3029 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3030 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3031 let Inst{21-19} = 0b001; // imm6 = 001xxx
3033 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3034 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3035 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3037 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3038 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3039 let Inst{21} = 0b1; // imm6 = 1xxxxx
3041 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
3042 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3045 // 128-bit vector types.
3046 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3047 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3048 let Inst{21-19} = 0b001; // imm6 = 001xxx
3050 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3051 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3052 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3054 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3055 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3056 let Inst{21} = 0b1; // imm6 = 1xxxxx
3058 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
3059 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3064 // Neon Shift-Insert vector operations,
3065 // with f of either N2RegVShLFrm or N2RegVShRFrm
3066 // element sizes of 8, 16, 32 and 64 bits:
3067 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3068 string OpcodeStr, SDNode ShOp,
3070 // 64-bit vector types.
3071 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
3072 f, OpcodeStr, "8", v8i8, ShOp> {
3073 let Inst{21-19} = 0b001; // imm6 = 001xxx
3075 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
3076 f, OpcodeStr, "16", v4i16, ShOp> {
3077 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3079 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
3080 f, OpcodeStr, "32", v2i32, ShOp> {
3081 let Inst{21} = 0b1; // imm6 = 1xxxxx
3083 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
3084 f, OpcodeStr, "64", v1i64, ShOp>;
3087 // 128-bit vector types.
3088 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
3089 f, OpcodeStr, "8", v16i8, ShOp> {
3090 let Inst{21-19} = 0b001; // imm6 = 001xxx
3092 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
3093 f, OpcodeStr, "16", v8i16, ShOp> {
3094 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3096 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
3097 f, OpcodeStr, "32", v4i32, ShOp> {
3098 let Inst{21} = 0b1; // imm6 = 1xxxxx
3100 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
3101 f, OpcodeStr, "64", v2i64, ShOp>;
3105 // Neon Shift Long operations,
3106 // element sizes of 8, 16, 32 bits:
3107 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3108 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3109 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3110 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3111 let Inst{21-19} = 0b001; // imm6 = 001xxx
3113 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3114 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3115 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3117 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3118 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3119 let Inst{21} = 0b1; // imm6 = 1xxxxx
3123 // Neon Shift Narrow operations,
3124 // element sizes of 16, 32, 64 bits:
3125 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3126 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3128 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3129 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
3130 let Inst{21-19} = 0b001; // imm6 = 001xxx
3132 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3133 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
3134 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3136 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3137 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
3138 let Inst{21} = 0b1; // imm6 = 1xxxxx
3142 //===----------------------------------------------------------------------===//
3143 // Instruction Definitions.
3144 //===----------------------------------------------------------------------===//
3146 // Vector Add Operations.
3148 // VADD : Vector Add (integer and floating-point)
3149 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3151 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3152 v2f32, v2f32, fadd, 1>;
3153 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3154 v4f32, v4f32, fadd, 1>;
3155 // VADDL : Vector Add Long (Q = D + D)
3156 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3157 "vaddl", "s", add, sext, 1>;
3158 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3159 "vaddl", "u", add, zext, 1>;
3160 // VADDW : Vector Add Wide (Q = Q + D)
3161 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3162 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3163 // VHADD : Vector Halving Add
3164 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3165 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3166 "vhadd", "s", int_arm_neon_vhadds, 1>;
3167 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3168 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3169 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3170 // VRHADD : Vector Rounding Halving Add
3171 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3172 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3173 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3174 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3175 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3176 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3177 // VQADD : Vector Saturating Add
3178 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3179 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3180 "vqadd", "s", int_arm_neon_vqadds, 1>;
3181 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3182 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3183 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3184 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3185 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3186 int_arm_neon_vaddhn, 1>;
3187 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3188 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3189 int_arm_neon_vraddhn, 1>;
3191 // Vector Multiply Operations.
3193 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3194 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3195 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3196 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3197 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3198 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3199 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3200 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3201 v2f32, v2f32, fmul, 1>;
3202 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3203 v4f32, v4f32, fmul, 1>;
3204 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3205 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3206 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3209 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3210 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3211 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3212 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3213 (DSubReg_i16_reg imm:$lane))),
3214 (SubReg_i16_lane imm:$lane)))>;
3215 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3216 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3217 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3218 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3219 (DSubReg_i32_reg imm:$lane))),
3220 (SubReg_i32_lane imm:$lane)))>;
3221 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3222 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3223 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3224 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3225 (DSubReg_i32_reg imm:$lane))),
3226 (SubReg_i32_lane imm:$lane)))>;
3228 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3229 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3230 IIC_VMULi16Q, IIC_VMULi32Q,
3231 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3232 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3233 IIC_VMULi16Q, IIC_VMULi32Q,
3234 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3235 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3236 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3238 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3239 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3240 (DSubReg_i16_reg imm:$lane))),
3241 (SubReg_i16_lane imm:$lane)))>;
3242 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3243 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3245 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3246 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3247 (DSubReg_i32_reg imm:$lane))),
3248 (SubReg_i32_lane imm:$lane)))>;
3250 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3251 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3252 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3253 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3254 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3255 IIC_VMULi16Q, IIC_VMULi32Q,
3256 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3257 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3258 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3260 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3261 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3262 (DSubReg_i16_reg imm:$lane))),
3263 (SubReg_i16_lane imm:$lane)))>;
3264 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3265 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3267 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3268 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3269 (DSubReg_i32_reg imm:$lane))),
3270 (SubReg_i32_lane imm:$lane)))>;
3272 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3273 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3274 "vmull", "s", NEONvmulls, 1>;
3275 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3276 "vmull", "u", NEONvmullu, 1>;
3277 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3278 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3279 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3280 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3282 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3283 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3284 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3285 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3286 "vqdmull", "s", int_arm_neon_vqdmull>;
3288 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3290 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3291 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3292 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3293 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3295 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3297 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3298 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3299 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3301 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3302 v4f32, v2f32, fmul, fadd>;
3304 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3305 (mul (v8i16 QPR:$src2),
3306 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3307 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3308 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3309 (DSubReg_i16_reg imm:$lane))),
3310 (SubReg_i16_lane imm:$lane)))>;
3312 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3313 (mul (v4i32 QPR:$src2),
3314 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3315 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3316 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3317 (DSubReg_i32_reg imm:$lane))),
3318 (SubReg_i32_lane imm:$lane)))>;
3320 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
3321 (fmul (v4f32 QPR:$src2),
3322 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3323 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3325 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3326 (DSubReg_i32_reg imm:$lane))),
3327 (SubReg_i32_lane imm:$lane)))>;
3329 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3330 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3331 "vmlal", "s", NEONvmulls, add>;
3332 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3333 "vmlal", "u", NEONvmullu, add>;
3335 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3336 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3338 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3339 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3340 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3341 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3343 // VMLS : Vector Multiply Subtract (integer and floating-point)
3344 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3345 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3346 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3348 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3350 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3351 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3352 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3354 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3355 v4f32, v2f32, fmul, fsub>;
3357 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3358 (mul (v8i16 QPR:$src2),
3359 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3360 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3361 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3362 (DSubReg_i16_reg imm:$lane))),
3363 (SubReg_i16_lane imm:$lane)))>;
3365 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3366 (mul (v4i32 QPR:$src2),
3367 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3368 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3369 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3370 (DSubReg_i32_reg imm:$lane))),
3371 (SubReg_i32_lane imm:$lane)))>;
3373 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
3374 (fmul (v4f32 QPR:$src2),
3375 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3376 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3377 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3378 (DSubReg_i32_reg imm:$lane))),
3379 (SubReg_i32_lane imm:$lane)))>;
3381 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3382 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3383 "vmlsl", "s", NEONvmulls, sub>;
3384 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3385 "vmlsl", "u", NEONvmullu, sub>;
3387 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3388 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3390 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3391 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3392 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3393 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3395 // Vector Subtract Operations.
3397 // VSUB : Vector Subtract (integer and floating-point)
3398 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3399 "vsub", "i", sub, 0>;
3400 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3401 v2f32, v2f32, fsub, 0>;
3402 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3403 v4f32, v4f32, fsub, 0>;
3404 // VSUBL : Vector Subtract Long (Q = D - D)
3405 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3406 "vsubl", "s", sub, sext, 0>;
3407 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3408 "vsubl", "u", sub, zext, 0>;
3409 // VSUBW : Vector Subtract Wide (Q = Q - D)
3410 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3411 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3412 // VHSUB : Vector Halving Subtract
3413 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3414 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3415 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3416 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3417 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3418 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3419 // VQSUB : Vector Saturing Subtract
3420 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3421 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3422 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3423 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3424 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3425 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3426 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3427 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3428 int_arm_neon_vsubhn, 0>;
3429 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3430 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3431 int_arm_neon_vrsubhn, 0>;
3433 // Vector Comparisons.
3435 // VCEQ : Vector Compare Equal
3436 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3437 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3438 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3440 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3443 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3444 "$dst, $src, #0", NEONvceqz>;
3446 // VCGE : Vector Compare Greater Than or Equal
3447 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3448 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3449 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3450 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3451 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3453 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3456 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3457 "$dst, $src, #0", NEONvcgez>;
3458 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3459 "$dst, $src, #0", NEONvclez>;
3461 // VCGT : Vector Compare Greater Than
3462 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3463 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3464 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3465 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3466 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3468 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3471 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3472 "$dst, $src, #0", NEONvcgtz>;
3473 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3474 "$dst, $src, #0", NEONvcltz>;
3476 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3477 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3478 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3479 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3480 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3481 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3482 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3483 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3484 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3485 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3486 // VTST : Vector Test Bits
3487 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3488 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3490 // Vector Bitwise Operations.
3492 def vnotd : PatFrag<(ops node:$in),
3493 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3494 def vnotq : PatFrag<(ops node:$in),
3495 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3498 // VAND : Vector Bitwise AND
3499 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3500 v2i32, v2i32, and, 1>;
3501 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3502 v4i32, v4i32, and, 1>;
3504 // VEOR : Vector Bitwise Exclusive OR
3505 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3506 v2i32, v2i32, xor, 1>;
3507 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3508 v4i32, v4i32, xor, 1>;
3510 // VORR : Vector Bitwise OR
3511 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3512 v2i32, v2i32, or, 1>;
3513 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3514 v4i32, v4i32, or, 1>;
3516 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3517 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3519 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3521 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3522 let Inst{9} = SIMM{9};
3525 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3526 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3528 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3530 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3531 let Inst{10-9} = SIMM{10-9};
3534 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3535 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3537 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3539 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3540 let Inst{9} = SIMM{9};
3543 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3544 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3546 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3548 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3549 let Inst{10-9} = SIMM{10-9};
3553 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3554 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
3555 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3556 "vbic", "$dst, $src1, $src2", "",
3557 [(set DPR:$dst, (v2i32 (and DPR:$src1,
3558 (vnotd DPR:$src2))))]>;
3559 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
3560 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3561 "vbic", "$dst, $src1, $src2", "",
3562 [(set QPR:$dst, (v4i32 (and QPR:$src1,
3563 (vnotq QPR:$src2))))]>;
3565 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3566 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3568 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3570 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3571 let Inst{9} = SIMM{9};
3574 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3575 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3577 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3579 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3580 let Inst{10-9} = SIMM{10-9};
3583 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3584 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3586 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3588 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3589 let Inst{9} = SIMM{9};
3592 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3593 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3595 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3597 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3598 let Inst{10-9} = SIMM{10-9};
3601 // VORN : Vector Bitwise OR NOT
3602 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
3603 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
3604 "vorn", "$dst, $src1, $src2", "",
3605 [(set DPR:$dst, (v2i32 (or DPR:$src1,
3606 (vnotd DPR:$src2))))]>;
3607 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
3608 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
3609 "vorn", "$dst, $src1, $src2", "",
3610 [(set QPR:$dst, (v4i32 (or QPR:$src1,
3611 (vnotq QPR:$src2))))]>;
3613 // VMVN : Vector Bitwise NOT (Immediate)
3615 let isReMaterializable = 1 in {
3617 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
3618 (ins nModImm:$SIMM), IIC_VMOVImm,
3619 "vmvn", "i16", "$dst, $SIMM", "",
3620 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3621 let Inst{9} = SIMM{9};
3624 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
3625 (ins nModImm:$SIMM), IIC_VMOVImm,
3626 "vmvn", "i16", "$dst, $SIMM", "",
3627 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3628 let Inst{9} = SIMM{9};
3631 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
3632 (ins nModImm:$SIMM), IIC_VMOVImm,
3633 "vmvn", "i32", "$dst, $SIMM", "",
3634 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3635 let Inst{11-8} = SIMM{11-8};
3638 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
3639 (ins nModImm:$SIMM), IIC_VMOVImm,
3640 "vmvn", "i32", "$dst, $SIMM", "",
3641 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3642 let Inst{11-8} = SIMM{11-8};
3646 // VMVN : Vector Bitwise NOT
3647 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3648 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
3649 "vmvn", "$dst, $src", "",
3650 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
3651 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3652 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
3653 "vmvn", "$dst, $src", "",
3654 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
3655 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3656 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3658 // VBSL : Vector Bitwise Select
3659 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3660 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3661 N3RegFrm, IIC_VCNTiD,
3662 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3664 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3665 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3666 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3667 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3668 N3RegFrm, IIC_VCNTiQ,
3669 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3671 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3672 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3674 // VBIF : Vector Bitwise Insert if False
3675 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3676 // FIXME: This instruction's encoding MAY NOT BE correct.
3677 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3678 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3679 N3RegFrm, IIC_VBINiD,
3680 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3681 [/* For disassembly only; pattern left blank */]>;
3682 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3683 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3684 N3RegFrm, IIC_VBINiQ,
3685 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3686 [/* For disassembly only; pattern left blank */]>;
3688 // VBIT : Vector Bitwise Insert if True
3689 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3690 // FIXME: This instruction's encoding MAY NOT BE correct.
3691 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3692 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3693 N3RegFrm, IIC_VBINiD,
3694 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3695 [/* For disassembly only; pattern left blank */]>;
3696 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3697 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3698 N3RegFrm, IIC_VBINiQ,
3699 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3700 [/* For disassembly only; pattern left blank */]>;
3702 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3703 // for equivalent operations with different register constraints; it just
3706 // Vector Absolute Differences.
3708 // VABD : Vector Absolute Difference
3709 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3710 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3711 "vabd", "s", int_arm_neon_vabds, 1>;
3712 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3713 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3714 "vabd", "u", int_arm_neon_vabdu, 1>;
3715 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3716 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3717 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3718 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3720 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3721 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3722 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3723 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3724 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3726 // VABA : Vector Absolute Difference and Accumulate
3727 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3728 "vaba", "s", int_arm_neon_vabds, add>;
3729 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3730 "vaba", "u", int_arm_neon_vabdu, add>;
3732 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3733 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3734 "vabal", "s", int_arm_neon_vabds, zext, add>;
3735 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3736 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3738 // Vector Maximum and Minimum.
3740 // VMAX : Vector Maximum
3741 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3742 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3743 "vmax", "s", int_arm_neon_vmaxs, 1>;
3744 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3745 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3746 "vmax", "u", int_arm_neon_vmaxu, 1>;
3747 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3749 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3750 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3752 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3754 // VMIN : Vector Minimum
3755 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3756 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3757 "vmin", "s", int_arm_neon_vmins, 1>;
3758 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3759 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3760 "vmin", "u", int_arm_neon_vminu, 1>;
3761 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3763 v2f32, v2f32, int_arm_neon_vmins, 1>;
3764 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3766 v4f32, v4f32, int_arm_neon_vmins, 1>;
3768 // Vector Pairwise Operations.
3770 // VPADD : Vector Pairwise Add
3771 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3773 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3774 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3776 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3777 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3779 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3780 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3781 IIC_VPBIND, "vpadd", "f32",
3782 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3784 // VPADDL : Vector Pairwise Add Long
3785 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3786 int_arm_neon_vpaddls>;
3787 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3788 int_arm_neon_vpaddlu>;
3790 // VPADAL : Vector Pairwise Add and Accumulate Long
3791 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3792 int_arm_neon_vpadals>;
3793 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3794 int_arm_neon_vpadalu>;
3796 // VPMAX : Vector Pairwise Maximum
3797 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3798 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3799 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3800 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3801 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3802 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3803 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3804 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3805 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3806 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3807 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3808 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3809 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3810 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3812 // VPMIN : Vector Pairwise Minimum
3813 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3814 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3815 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3816 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3817 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3818 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3819 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3820 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3821 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3822 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3823 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3824 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3825 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3826 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3828 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3830 // VRECPE : Vector Reciprocal Estimate
3831 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3832 IIC_VUNAD, "vrecpe", "u32",
3833 v2i32, v2i32, int_arm_neon_vrecpe>;
3834 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3835 IIC_VUNAQ, "vrecpe", "u32",
3836 v4i32, v4i32, int_arm_neon_vrecpe>;
3837 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3838 IIC_VUNAD, "vrecpe", "f32",
3839 v2f32, v2f32, int_arm_neon_vrecpe>;
3840 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3841 IIC_VUNAQ, "vrecpe", "f32",
3842 v4f32, v4f32, int_arm_neon_vrecpe>;
3844 // VRECPS : Vector Reciprocal Step
3845 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3846 IIC_VRECSD, "vrecps", "f32",
3847 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3848 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3849 IIC_VRECSQ, "vrecps", "f32",
3850 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3852 // VRSQRTE : Vector Reciprocal Square Root Estimate
3853 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3854 IIC_VUNAD, "vrsqrte", "u32",
3855 v2i32, v2i32, int_arm_neon_vrsqrte>;
3856 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3857 IIC_VUNAQ, "vrsqrte", "u32",
3858 v4i32, v4i32, int_arm_neon_vrsqrte>;
3859 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3860 IIC_VUNAD, "vrsqrte", "f32",
3861 v2f32, v2f32, int_arm_neon_vrsqrte>;
3862 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3863 IIC_VUNAQ, "vrsqrte", "f32",
3864 v4f32, v4f32, int_arm_neon_vrsqrte>;
3866 // VRSQRTS : Vector Reciprocal Square Root Step
3867 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3868 IIC_VRECSD, "vrsqrts", "f32",
3869 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3870 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3871 IIC_VRECSQ, "vrsqrts", "f32",
3872 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3876 // VSHL : Vector Shift
3877 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3878 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3879 "vshl", "s", int_arm_neon_vshifts>;
3880 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3881 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3882 "vshl", "u", int_arm_neon_vshiftu>;
3883 // VSHL : Vector Shift Left (Immediate)
3884 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3886 // VSHR : Vector Shift Right (Immediate)
3887 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3889 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3892 // VSHLL : Vector Shift Left Long
3893 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3894 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3896 // VSHLL : Vector Shift Left Long (with maximum shift count)
3897 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3898 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3899 ValueType OpTy, SDNode OpNode>
3900 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3901 ResTy, OpTy, OpNode> {
3902 let Inst{21-16} = op21_16;
3904 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3905 v8i16, v8i8, NEONvshlli>;
3906 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3907 v4i32, v4i16, NEONvshlli>;
3908 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3909 v2i64, v2i32, NEONvshlli>;
3911 // VSHRN : Vector Shift Right and Narrow
3912 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3915 // VRSHL : Vector Rounding Shift
3916 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3917 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3918 "vrshl", "s", int_arm_neon_vrshifts>;
3919 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3920 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3921 "vrshl", "u", int_arm_neon_vrshiftu>;
3922 // VRSHR : Vector Rounding Shift Right
3923 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3925 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3928 // VRSHRN : Vector Rounding Shift Right and Narrow
3929 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3932 // VQSHL : Vector Saturating Shift
3933 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3934 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3935 "vqshl", "s", int_arm_neon_vqshifts>;
3936 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3937 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3938 "vqshl", "u", int_arm_neon_vqshiftu>;
3939 // VQSHL : Vector Saturating Shift Left (Immediate)
3940 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3942 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3944 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3945 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3948 // VQSHRN : Vector Saturating Shift Right and Narrow
3949 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3951 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3954 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3955 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3958 // VQRSHL : Vector Saturating Rounding Shift
3959 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3960 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3961 "vqrshl", "s", int_arm_neon_vqrshifts>;
3962 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3963 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3964 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3966 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3967 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3969 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3972 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3973 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3976 // VSRA : Vector Shift Right and Accumulate
3977 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3978 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3979 // VRSRA : Vector Rounding Shift Right and Accumulate
3980 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3981 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3983 // VSLI : Vector Shift Left and Insert
3984 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3985 // VSRI : Vector Shift Right and Insert
3986 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3988 // Vector Absolute and Saturating Absolute.
3990 // VABS : Vector Absolute Value
3991 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3992 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
3994 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3995 IIC_VUNAD, "vabs", "f32",
3996 v2f32, v2f32, int_arm_neon_vabs>;
3997 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
3998 IIC_VUNAQ, "vabs", "f32",
3999 v4f32, v4f32, int_arm_neon_vabs>;
4001 // VQABS : Vector Saturating Absolute Value
4002 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4003 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4004 int_arm_neon_vqabs>;
4008 def vnegd : PatFrag<(ops node:$in),
4009 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4010 def vnegq : PatFrag<(ops node:$in),
4011 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4013 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4014 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
4015 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
4016 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
4017 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4018 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
4019 IIC_VSHLiQ, OpcodeStr, Dt, "$dst, $src", "",
4020 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
4022 // VNEG : Vector Negate (integer)
4023 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4024 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4025 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4026 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4027 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4028 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4030 // VNEG : Vector Negate (floating-point)
4031 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4032 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
4033 "vneg", "f32", "$dst, $src", "",
4034 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
4035 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4036 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
4037 "vneg", "f32", "$dst, $src", "",
4038 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
4040 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4041 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4042 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4043 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4044 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4045 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4047 // VQNEG : Vector Saturating Negate
4048 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4049 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4050 int_arm_neon_vqneg>;
4052 // Vector Bit Counting Operations.
4054 // VCLS : Vector Count Leading Sign Bits
4055 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4056 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4058 // VCLZ : Vector Count Leading Zeros
4059 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4060 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4062 // VCNT : Vector Count One Bits
4063 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4064 IIC_VCNTiD, "vcnt", "8",
4065 v8i8, v8i8, int_arm_neon_vcnt>;
4066 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4067 IIC_VCNTiQ, "vcnt", "8",
4068 v16i8, v16i8, int_arm_neon_vcnt>;
4070 // Vector Swap -- for disassembly only.
4071 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4072 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
4073 "vswp", "$dst, $src", "", []>;
4074 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4075 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
4076 "vswp", "$dst, $src", "", []>;
4078 // Vector Move Operations.
4080 // VMOV : Vector Move (Register)
4082 let neverHasSideEffects = 1 in {
4083 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4084 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4085 let Vn{4-0} = Vm{4-0};
4087 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4088 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4089 let Vn{4-0} = Vm{4-0};
4092 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4093 // be expanded after register allocation is completed.
4094 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4097 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4099 } // neverHasSideEffects
4101 // VMOV : Vector Move (Immediate)
4103 let isReMaterializable = 1 in {
4104 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
4105 (ins nModImm:$SIMM), IIC_VMOVImm,
4106 "vmov", "i8", "$dst, $SIMM", "",
4107 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4108 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
4109 (ins nModImm:$SIMM), IIC_VMOVImm,
4110 "vmov", "i8", "$dst, $SIMM", "",
4111 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4113 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
4114 (ins nModImm:$SIMM), IIC_VMOVImm,
4115 "vmov", "i16", "$dst, $SIMM", "",
4116 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4117 let Inst{9} = SIMM{9};
4120 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
4121 (ins nModImm:$SIMM), IIC_VMOVImm,
4122 "vmov", "i16", "$dst, $SIMM", "",
4123 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4124 let Inst{9} = SIMM{9};
4127 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
4128 (ins nModImm:$SIMM), IIC_VMOVImm,
4129 "vmov", "i32", "$dst, $SIMM", "",
4130 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4131 let Inst{11-8} = SIMM{11-8};
4134 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
4135 (ins nModImm:$SIMM), IIC_VMOVImm,
4136 "vmov", "i32", "$dst, $SIMM", "",
4137 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4138 let Inst{11-8} = SIMM{11-8};
4141 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
4142 (ins nModImm:$SIMM), IIC_VMOVImm,
4143 "vmov", "i64", "$dst, $SIMM", "",
4144 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4145 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
4146 (ins nModImm:$SIMM), IIC_VMOVImm,
4147 "vmov", "i64", "$dst, $SIMM", "",
4148 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4149 } // isReMaterializable
4151 // VMOV : Vector Get Lane (move scalar to ARM core register)
4153 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4154 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4155 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4156 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4158 let Inst{21} = lane{2};
4159 let Inst{6-5} = lane{1-0};
4161 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4162 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4163 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4164 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4166 let Inst{21} = lane{1};
4167 let Inst{6} = lane{0};
4169 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4170 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4171 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4172 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4174 let Inst{21} = lane{2};
4175 let Inst{6-5} = lane{1-0};
4177 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4178 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4179 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4180 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4182 let Inst{21} = lane{1};
4183 let Inst{6} = lane{0};
4185 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4186 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4187 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4188 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4190 let Inst{21} = lane{0};
4192 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4193 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4194 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4195 (DSubReg_i8_reg imm:$lane))),
4196 (SubReg_i8_lane imm:$lane))>;
4197 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4198 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4199 (DSubReg_i16_reg imm:$lane))),
4200 (SubReg_i16_lane imm:$lane))>;
4201 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4202 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4203 (DSubReg_i8_reg imm:$lane))),
4204 (SubReg_i8_lane imm:$lane))>;
4205 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4206 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4207 (DSubReg_i16_reg imm:$lane))),
4208 (SubReg_i16_lane imm:$lane))>;
4209 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4210 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4211 (DSubReg_i32_reg imm:$lane))),
4212 (SubReg_i32_lane imm:$lane))>;
4213 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4214 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4215 (SSubReg_f32_reg imm:$src2))>;
4216 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4217 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4218 (SSubReg_f32_reg imm:$src2))>;
4219 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4220 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4221 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4222 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4225 // VMOV : Vector Set Lane (move ARM core register to scalar)
4227 let Constraints = "$src1 = $V" in {
4228 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4229 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4230 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4231 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4232 GPR:$R, imm:$lane))]> {
4233 let Inst{21} = lane{2};
4234 let Inst{6-5} = lane{1-0};
4236 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4237 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4238 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4239 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4240 GPR:$R, imm:$lane))]> {
4241 let Inst{21} = lane{1};
4242 let Inst{6} = lane{0};
4244 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4245 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4246 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4247 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4248 GPR:$R, imm:$lane))]> {
4249 let Inst{21} = lane{0};
4252 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4253 (v16i8 (INSERT_SUBREG QPR:$src1,
4254 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4255 (DSubReg_i8_reg imm:$lane))),
4256 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4257 (DSubReg_i8_reg imm:$lane)))>;
4258 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4259 (v8i16 (INSERT_SUBREG QPR:$src1,
4260 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4261 (DSubReg_i16_reg imm:$lane))),
4262 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4263 (DSubReg_i16_reg imm:$lane)))>;
4264 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4265 (v4i32 (INSERT_SUBREG QPR:$src1,
4266 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4267 (DSubReg_i32_reg imm:$lane))),
4268 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4269 (DSubReg_i32_reg imm:$lane)))>;
4271 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4272 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4273 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4274 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4275 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4276 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4278 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4279 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4280 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4281 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4283 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4284 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4285 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4286 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4287 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4288 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4290 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4291 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4292 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4293 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4294 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4295 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4297 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4298 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4299 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4301 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4302 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4303 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4305 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4306 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4307 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4310 // VDUP : Vector Duplicate (from ARM core register to all elements)
4312 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4313 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
4314 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4315 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4316 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4317 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
4318 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
4319 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
4321 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4322 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4323 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4324 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4325 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4326 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4328 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
4329 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4330 [(set DPR:$dst, (v2f32 (NEONvdup
4331 (f32 (bitconvert GPR:$src)))))]>;
4332 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
4333 IIC_VMOVIS, "vdup", "32", "$dst, $src",
4334 [(set QPR:$dst, (v4f32 (NEONvdup
4335 (f32 (bitconvert GPR:$src)))))]>;
4337 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4339 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4341 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4342 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
4343 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
4345 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4346 ValueType ResTy, ValueType OpTy>
4347 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
4348 IIC_VMOVQ, OpcodeStr, Dt, "$dst, $src[$lane]",
4349 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
4352 // Inst{19-16} is partially specified depending on the element size.
4354 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4355 let Inst{19-17} = lane{2-0};
4357 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4358 let Inst{19-18} = lane{1-0};
4360 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4361 let Inst{19} = lane{0};
4363 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4364 let Inst{19} = lane{0};
4366 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4367 let Inst{19-17} = lane{2-0};
4369 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4370 let Inst{19-18} = lane{1-0};
4372 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4373 let Inst{19} = lane{0};
4375 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4376 let Inst{19} = lane{0};
4379 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4380 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4381 (DSubReg_i8_reg imm:$lane))),
4382 (SubReg_i8_lane imm:$lane)))>;
4383 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4384 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4385 (DSubReg_i16_reg imm:$lane))),
4386 (SubReg_i16_lane imm:$lane)))>;
4387 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4388 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4389 (DSubReg_i32_reg imm:$lane))),
4390 (SubReg_i32_lane imm:$lane)))>;
4391 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4392 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4393 (DSubReg_i32_reg imm:$lane))),
4394 (SubReg_i32_lane imm:$lane)))>;
4396 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4397 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4398 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4399 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4401 // VMOVN : Vector Narrowing Move
4402 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4403 "vmovn", "i", trunc>;
4404 // VQMOVN : Vector Saturating Narrowing Move
4405 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4406 "vqmovn", "s", int_arm_neon_vqmovns>;
4407 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4408 "vqmovn", "u", int_arm_neon_vqmovnu>;
4409 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4410 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4411 // VMOVL : Vector Lengthening Move
4412 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4413 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4415 // Vector Conversions.
4417 // VCVT : Vector Convert Between Floating-Point and Integers
4418 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4419 v2i32, v2f32, fp_to_sint>;
4420 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4421 v2i32, v2f32, fp_to_uint>;
4422 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4423 v2f32, v2i32, sint_to_fp>;
4424 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4425 v2f32, v2i32, uint_to_fp>;
4427 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4428 v4i32, v4f32, fp_to_sint>;
4429 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4430 v4i32, v4f32, fp_to_uint>;
4431 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4432 v4f32, v4i32, sint_to_fp>;
4433 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4434 v4f32, v4i32, uint_to_fp>;
4436 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4437 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4438 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4439 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4440 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4441 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4442 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4443 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4444 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4446 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4447 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4448 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4449 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4450 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4451 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4452 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4453 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4457 // VREV64 : Vector Reverse elements within 64-bit doublewords
4459 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4460 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4461 (ins DPR:$Vm), IIC_VMOVD,
4462 OpcodeStr, Dt, "$Vd, $Vm", "",
4463 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4464 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4465 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4466 (ins QPR:$Vm), IIC_VMOVQ,
4467 OpcodeStr, Dt, "$Vd, $Vm", "",
4468 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4470 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4471 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4472 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4473 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4475 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4476 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4477 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4478 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4480 // VREV32 : Vector Reverse elements within 32-bit words
4482 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4483 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4484 (ins DPR:$Vm), IIC_VMOVD,
4485 OpcodeStr, Dt, "$Vd, $Vm", "",
4486 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4487 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4488 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4489 (ins QPR:$Vm), IIC_VMOVQ,
4490 OpcodeStr, Dt, "$Vd, $Vm", "",
4491 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4493 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4494 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4496 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4497 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4499 // VREV16 : Vector Reverse elements within 16-bit halfwords
4501 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4502 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4503 (ins DPR:$Vm), IIC_VMOVD,
4504 OpcodeStr, Dt, "$Vd, $Vm", "",
4505 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4506 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4507 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4508 (ins QPR:$Vm), IIC_VMOVQ,
4509 OpcodeStr, Dt, "$Vd, $Vm", "",
4510 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4512 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4513 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4515 // Other Vector Shuffles.
4517 // VEXT : Vector Extract
4519 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4520 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4521 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4522 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4523 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4524 (Ty DPR:$Vm), imm:$index)))]> {
4526 let Inst{11-8} = index{3-0};
4529 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4530 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4531 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4532 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4533 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4534 (Ty QPR:$Vm), imm:$index)))]> {
4536 let Inst{11-8} = index{3-0};
4539 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4540 let Inst{11-8} = index{3-0};
4542 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4543 let Inst{11-9} = index{2-0};
4546 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4547 let Inst{11-10} = index{1-0};
4548 let Inst{9-8} = 0b00;
4550 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4551 let Inst{11} = index{0};
4552 let Inst{10-8} = 0b000;
4555 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4556 let Inst{11-8} = index{3-0};
4558 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4559 let Inst{11-9} = index{2-0};
4562 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4563 let Inst{11-10} = index{1-0};
4564 let Inst{9-8} = 0b00;
4566 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4567 let Inst{11} = index{0};
4568 let Inst{10-8} = 0b000;
4571 // VTRN : Vector Transpose
4573 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4574 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4575 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4577 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4578 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4579 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4581 // VUZP : Vector Unzip (Deinterleave)
4583 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4584 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4585 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4587 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4588 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4589 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4591 // VZIP : Vector Zip (Interleave)
4593 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4594 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4595 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4597 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4598 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4599 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4601 // Vector Table Lookup and Table Extension.
4603 // VTBL : Vector Table Lookup
4605 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4606 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4607 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4608 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4609 let hasExtraSrcRegAllocReq = 1 in {
4611 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4612 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4613 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4615 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4616 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4617 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4619 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4620 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4622 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4623 } // hasExtraSrcRegAllocReq = 1
4626 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4628 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4630 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4632 // VTBX : Vector Table Extension
4634 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4635 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4636 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4637 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4638 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4639 let hasExtraSrcRegAllocReq = 1 in {
4641 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4642 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4643 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4645 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4646 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4647 NVTBLFrm, IIC_VTBX3,
4648 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4651 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4652 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4653 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4655 } // hasExtraSrcRegAllocReq = 1
4658 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4659 IIC_VTBX2, "$orig = $dst", []>;
4661 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4662 IIC_VTBX3, "$orig = $dst", []>;
4664 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4665 IIC_VTBX4, "$orig = $dst", []>;
4667 //===----------------------------------------------------------------------===//
4668 // NEON instructions for single-precision FP math
4669 //===----------------------------------------------------------------------===//
4671 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
4672 : NEONFPPat<(ResTy (OpNode SPR:$a)),
4673 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
4677 class N3VSPat<SDNode OpNode, NeonI Inst>
4678 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4679 (EXTRACT_SUBREG (v2f32
4680 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4682 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4686 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4687 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4688 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4690 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4692 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
4696 // These need separate instructions because they must use DPR_VFP2 register
4697 // class which have SPR sub-registers.
4699 // Vector Add Operations used for single-precision FP
4700 let neverHasSideEffects = 1 in
4701 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
4702 def : N3VSPat<fadd, VADDfd_sfp>;
4704 // Vector Sub Operations used for single-precision FP
4705 let neverHasSideEffects = 1 in
4706 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
4707 def : N3VSPat<fsub, VSUBfd_sfp>;
4709 // Vector Multiply Operations used for single-precision FP
4710 let neverHasSideEffects = 1 in
4711 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
4712 def : N3VSPat<fmul, VMULfd_sfp>;
4714 // Vector Multiply-Accumulate/Subtract used for single-precision FP
4715 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
4716 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
4718 //let neverHasSideEffects = 1 in
4719 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
4720 // v2f32, fmul, fadd>;
4721 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
4723 //let neverHasSideEffects = 1 in
4724 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
4725 // v2f32, fmul, fsub>;
4726 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
4728 // Vector Absolute used for single-precision FP
4729 let neverHasSideEffects = 1 in
4730 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
4731 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4732 "vabs", "f32", "$dst, $src", "", []>;
4733 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
4735 // Vector Negate used for single-precision FP
4736 let neverHasSideEffects = 1 in
4737 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4738 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
4739 "vneg", "f32", "$dst, $src", "", []>;
4740 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
4742 // Vector Maximum used for single-precision FP
4743 let neverHasSideEffects = 1 in
4744 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4745 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4746 "vmax", "f32", "$dst, $src1, $src2", "", []>;
4747 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
4749 // Vector Minimum used for single-precision FP
4750 let neverHasSideEffects = 1 in
4751 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
4752 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
4753 "vmin", "f32", "$dst, $src1, $src2", "", []>;
4754 def : N3VSPat<NEONfmin, VMINfd_sfp>;
4756 // Vector Convert between single-precision FP and integer
4757 let neverHasSideEffects = 1 in
4758 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4759 v2i32, v2f32, fp_to_sint>;
4760 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
4762 let neverHasSideEffects = 1 in
4763 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4764 v2i32, v2f32, fp_to_uint>;
4765 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
4767 let neverHasSideEffects = 1 in
4768 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4769 v2f32, v2i32, sint_to_fp>;
4770 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
4772 let neverHasSideEffects = 1 in
4773 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4774 v2f32, v2i32, uint_to_fp>;
4775 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
4777 //===----------------------------------------------------------------------===//
4778 // Non-Instruction Patterns
4779 //===----------------------------------------------------------------------===//
4782 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4783 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4784 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4785 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4786 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4787 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4788 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4789 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4790 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4791 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4792 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4793 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4794 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4795 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4796 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4797 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4798 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4799 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4800 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4801 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4802 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4803 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4804 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4805 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4806 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4807 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4808 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4809 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4810 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4811 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4813 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4814 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4815 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4816 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4817 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4818 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4819 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4820 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4821 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4822 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4823 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4824 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4825 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4826 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4827 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4828 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4829 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4830 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4831 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4832 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4833 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4834 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4835 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4836 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4837 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4838 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4839 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4840 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4841 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4842 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;