1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; }
38 def nImmSplatNotI16 : Operand<i32> {
39 let ParserMatchClass = nImmSplatNotI16AsmOperand;
41 def nImmSplatNotI32AsmOperand : AsmOperandClass { let Name = "NEONi32splatNot"; }
42 def nImmSplatNotI32 : Operand<i32> {
43 let ParserMatchClass = nImmSplatNotI32AsmOperand;
45 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
46 def nImmVMOVI32 : Operand<i32> {
47 let PrintMethod = "printNEONModImmOperand";
48 let ParserMatchClass = nImmVMOVI32AsmOperand;
51 def nImmVMOVI16AsmOperandByteReplicate :
53 let Name = "NEONi16vmovByteReplicate";
54 let PredicateMethod = "isNEONi16ByteReplicate";
55 let RenderMethod = "addNEONvmovByteReplicateOperands";
57 def nImmVMOVI32AsmOperandByteReplicate :
59 let Name = "NEONi32vmovByteReplicate";
60 let PredicateMethod = "isNEONi32ByteReplicate";
61 let RenderMethod = "addNEONvmovByteReplicateOperands";
63 def nImmVMVNI16AsmOperandByteReplicate :
65 let Name = "NEONi16invByteReplicate";
66 let PredicateMethod = "isNEONi16ByteReplicate";
67 let RenderMethod = "addNEONinvByteReplicateOperands";
69 def nImmVMVNI32AsmOperandByteReplicate :
71 let Name = "NEONi32invByteReplicate";
72 let PredicateMethod = "isNEONi32ByteReplicate";
73 let RenderMethod = "addNEONinvByteReplicateOperands";
76 def nImmVMOVI16ByteReplicate : Operand<i32> {
77 let PrintMethod = "printNEONModImmOperand";
78 let ParserMatchClass = nImmVMOVI16AsmOperandByteReplicate;
80 def nImmVMOVI32ByteReplicate : Operand<i32> {
81 let PrintMethod = "printNEONModImmOperand";
82 let ParserMatchClass = nImmVMOVI32AsmOperandByteReplicate;
84 def nImmVMVNI16ByteReplicate : Operand<i32> {
85 let PrintMethod = "printNEONModImmOperand";
86 let ParserMatchClass = nImmVMVNI16AsmOperandByteReplicate;
88 def nImmVMVNI32ByteReplicate : Operand<i32> {
89 let PrintMethod = "printNEONModImmOperand";
90 let ParserMatchClass = nImmVMVNI32AsmOperandByteReplicate;
93 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
94 def nImmVMOVI32Neg : Operand<i32> {
95 let PrintMethod = "printNEONModImmOperand";
96 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
98 def nImmVMOVF32 : Operand<i32> {
99 let PrintMethod = "printFPImmOperand";
100 let ParserMatchClass = FPImmOperand;
102 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
103 def nImmSplatI64 : Operand<i32> {
104 let PrintMethod = "printNEONModImmOperand";
105 let ParserMatchClass = nImmSplatI64AsmOperand;
108 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
109 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
110 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
111 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
112 return ((uint64_t)Imm) < 8;
114 let ParserMatchClass = VectorIndex8Operand;
115 let PrintMethod = "printVectorIndex";
116 let MIOperandInfo = (ops i32imm);
118 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
119 return ((uint64_t)Imm) < 4;
121 let ParserMatchClass = VectorIndex16Operand;
122 let PrintMethod = "printVectorIndex";
123 let MIOperandInfo = (ops i32imm);
125 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
126 return ((uint64_t)Imm) < 2;
128 let ParserMatchClass = VectorIndex32Operand;
129 let PrintMethod = "printVectorIndex";
130 let MIOperandInfo = (ops i32imm);
133 // Register list of one D register.
134 def VecListOneDAsmOperand : AsmOperandClass {
135 let Name = "VecListOneD";
136 let ParserMethod = "parseVectorList";
137 let RenderMethod = "addVecListOperands";
139 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
140 let ParserMatchClass = VecListOneDAsmOperand;
142 // Register list of two sequential D registers.
143 def VecListDPairAsmOperand : AsmOperandClass {
144 let Name = "VecListDPair";
145 let ParserMethod = "parseVectorList";
146 let RenderMethod = "addVecListOperands";
148 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
149 let ParserMatchClass = VecListDPairAsmOperand;
151 // Register list of three sequential D registers.
152 def VecListThreeDAsmOperand : AsmOperandClass {
153 let Name = "VecListThreeD";
154 let ParserMethod = "parseVectorList";
155 let RenderMethod = "addVecListOperands";
157 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
158 let ParserMatchClass = VecListThreeDAsmOperand;
160 // Register list of four sequential D registers.
161 def VecListFourDAsmOperand : AsmOperandClass {
162 let Name = "VecListFourD";
163 let ParserMethod = "parseVectorList";
164 let RenderMethod = "addVecListOperands";
166 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
167 let ParserMatchClass = VecListFourDAsmOperand;
169 // Register list of two D registers spaced by 2 (two sequential Q registers).
170 def VecListDPairSpacedAsmOperand : AsmOperandClass {
171 let Name = "VecListDPairSpaced";
172 let ParserMethod = "parseVectorList";
173 let RenderMethod = "addVecListOperands";
175 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
176 let ParserMatchClass = VecListDPairSpacedAsmOperand;
178 // Register list of three D registers spaced by 2 (three Q registers).
179 def VecListThreeQAsmOperand : AsmOperandClass {
180 let Name = "VecListThreeQ";
181 let ParserMethod = "parseVectorList";
182 let RenderMethod = "addVecListOperands";
184 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
185 let ParserMatchClass = VecListThreeQAsmOperand;
187 // Register list of three D registers spaced by 2 (three Q registers).
188 def VecListFourQAsmOperand : AsmOperandClass {
189 let Name = "VecListFourQ";
190 let ParserMethod = "parseVectorList";
191 let RenderMethod = "addVecListOperands";
193 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
194 let ParserMatchClass = VecListFourQAsmOperand;
197 // Register list of one D register, with "all lanes" subscripting.
198 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
199 let Name = "VecListOneDAllLanes";
200 let ParserMethod = "parseVectorList";
201 let RenderMethod = "addVecListOperands";
203 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
204 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
206 // Register list of two D registers, with "all lanes" subscripting.
207 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
208 let Name = "VecListDPairAllLanes";
209 let ParserMethod = "parseVectorList";
210 let RenderMethod = "addVecListOperands";
212 def VecListDPairAllLanes : RegisterOperand<DPair,
213 "printVectorListTwoAllLanes"> {
214 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
216 // Register list of two D registers spaced by 2 (two sequential Q registers).
217 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
218 let Name = "VecListDPairSpacedAllLanes";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListOperands";
222 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
223 "printVectorListTwoSpacedAllLanes"> {
224 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
226 // Register list of three D registers, with "all lanes" subscripting.
227 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
228 let Name = "VecListThreeDAllLanes";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListOperands";
232 def VecListThreeDAllLanes : RegisterOperand<DPR,
233 "printVectorListThreeAllLanes"> {
234 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
236 // Register list of three D registers spaced by 2 (three sequential Q regs).
237 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
238 let Name = "VecListThreeQAllLanes";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListOperands";
242 def VecListThreeQAllLanes : RegisterOperand<DPR,
243 "printVectorListThreeSpacedAllLanes"> {
244 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
246 // Register list of four D registers, with "all lanes" subscripting.
247 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
248 let Name = "VecListFourDAllLanes";
249 let ParserMethod = "parseVectorList";
250 let RenderMethod = "addVecListOperands";
252 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
253 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
255 // Register list of four D registers spaced by 2 (four sequential Q regs).
256 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
257 let Name = "VecListFourQAllLanes";
258 let ParserMethod = "parseVectorList";
259 let RenderMethod = "addVecListOperands";
261 def VecListFourQAllLanes : RegisterOperand<DPR,
262 "printVectorListFourSpacedAllLanes"> {
263 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
267 // Register list of one D register, with byte lane subscripting.
268 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListOneDByteIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListOneDByteIndexed : Operand<i32> {
274 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // ...with half-word lane subscripting.
278 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListOneDHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListOneDHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListOneDWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListOneDWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
298 // Register list of two D registers with byte lane subscripting.
299 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
300 let Name = "VecListTwoDByteIndexed";
301 let ParserMethod = "parseVectorList";
302 let RenderMethod = "addVecListIndexedOperands";
304 def VecListTwoDByteIndexed : Operand<i32> {
305 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
308 // ...with half-word lane subscripting.
309 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
310 let Name = "VecListTwoDHWordIndexed";
311 let ParserMethod = "parseVectorList";
312 let RenderMethod = "addVecListIndexedOperands";
314 def VecListTwoDHWordIndexed : Operand<i32> {
315 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
318 // ...with word lane subscripting.
319 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
320 let Name = "VecListTwoDWordIndexed";
321 let ParserMethod = "parseVectorList";
322 let RenderMethod = "addVecListIndexedOperands";
324 def VecListTwoDWordIndexed : Operand<i32> {
325 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
328 // Register list of two Q registers with half-word lane subscripting.
329 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
330 let Name = "VecListTwoQHWordIndexed";
331 let ParserMethod = "parseVectorList";
332 let RenderMethod = "addVecListIndexedOperands";
334 def VecListTwoQHWordIndexed : Operand<i32> {
335 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
338 // ...with word lane subscripting.
339 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
340 let Name = "VecListTwoQWordIndexed";
341 let ParserMethod = "parseVectorList";
342 let RenderMethod = "addVecListIndexedOperands";
344 def VecListTwoQWordIndexed : Operand<i32> {
345 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of three D registers with byte lane subscripting.
351 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListThreeDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListThreeDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListThreeDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListThreeDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListThreeDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListThreeDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of three Q registers with half-word lane subscripting.
381 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListThreeQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListThreeQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListThreeQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListThreeQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 // Register list of four D registers with byte lane subscripting.
402 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
403 let Name = "VecListFourDByteIndexed";
404 let ParserMethod = "parseVectorList";
405 let RenderMethod = "addVecListIndexedOperands";
407 def VecListFourDByteIndexed : Operand<i32> {
408 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
409 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
411 // ...with half-word lane subscripting.
412 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
413 let Name = "VecListFourDHWordIndexed";
414 let ParserMethod = "parseVectorList";
415 let RenderMethod = "addVecListIndexedOperands";
417 def VecListFourDHWordIndexed : Operand<i32> {
418 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
419 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
421 // ...with word lane subscripting.
422 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
423 let Name = "VecListFourDWordIndexed";
424 let ParserMethod = "parseVectorList";
425 let RenderMethod = "addVecListIndexedOperands";
427 def VecListFourDWordIndexed : Operand<i32> {
428 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
429 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
431 // Register list of four Q registers with half-word lane subscripting.
432 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
433 let Name = "VecListFourQHWordIndexed";
434 let ParserMethod = "parseVectorList";
435 let RenderMethod = "addVecListIndexedOperands";
437 def VecListFourQHWordIndexed : Operand<i32> {
438 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
439 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
441 // ...with word lane subscripting.
442 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
443 let Name = "VecListFourQWordIndexed";
444 let ParserMethod = "parseVectorList";
445 let RenderMethod = "addVecListIndexedOperands";
447 def VecListFourQWordIndexed : Operand<i32> {
448 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
449 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
452 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
453 return cast<LoadSDNode>(N)->getAlignment() >= 8;
455 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
456 (store node:$val, node:$ptr), [{
457 return cast<StoreSDNode>(N)->getAlignment() >= 8;
459 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
460 return cast<LoadSDNode>(N)->getAlignment() == 4;
462 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
463 (store node:$val, node:$ptr), [{
464 return cast<StoreSDNode>(N)->getAlignment() == 4;
466 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
467 return cast<LoadSDNode>(N)->getAlignment() == 2;
469 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
470 (store node:$val, node:$ptr), [{
471 return cast<StoreSDNode>(N)->getAlignment() == 2;
473 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
474 return cast<LoadSDNode>(N)->getAlignment() == 1;
476 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
477 (store node:$val, node:$ptr), [{
478 return cast<StoreSDNode>(N)->getAlignment() == 1;
480 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
481 return cast<LoadSDNode>(N)->getAlignment() < 4;
483 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
484 (store node:$val, node:$ptr), [{
485 return cast<StoreSDNode>(N)->getAlignment() < 4;
488 //===----------------------------------------------------------------------===//
489 // NEON-specific DAG Nodes.
490 //===----------------------------------------------------------------------===//
492 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
493 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
495 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
496 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
497 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
498 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
499 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
500 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
501 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
502 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
503 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
504 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
505 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
507 // Types for vector shift by immediates. The "SHX" version is for long and
508 // narrow operations where the source and destination vectors have different
509 // types. The "SHINS" version is for shift and insert operations.
510 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
512 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
514 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
515 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
517 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
518 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
519 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
520 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
522 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
523 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
524 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
526 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
527 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
528 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
529 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
530 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
531 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
533 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
534 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
535 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
537 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
538 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
540 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
542 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
543 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
545 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
546 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
547 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
548 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
550 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
552 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
553 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
555 def NEONvbsl : SDNode<"ARMISD::VBSL",
556 SDTypeProfile<1, 3, [SDTCisVec<0>,
559 SDTCisSameAs<0, 3>]>>;
561 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
563 // VDUPLANE can produce a quad-register result from a double-register source,
564 // so the result is not constrained to match the source.
565 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
566 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
569 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
570 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
571 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
573 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
574 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
575 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
576 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
578 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
580 SDTCisSameAs<0, 3>]>;
581 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
582 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
583 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
585 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
586 SDTCisSameAs<1, 2>]>;
587 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
588 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
590 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
591 SDTCisSameAs<0, 2>]>;
592 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
593 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
595 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
596 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
597 unsigned EltBits = 0;
598 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
599 return (EltBits == 32 && EltVal == 0);
602 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
603 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
604 unsigned EltBits = 0;
605 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
606 return (EltBits == 8 && EltVal == 0xff);
609 //===----------------------------------------------------------------------===//
610 // NEON load / store instructions
611 //===----------------------------------------------------------------------===//
613 // Use VLDM to load a Q register as a D register pair.
614 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
616 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
618 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
620 // Use VSTM to store a Q register as a D register pair.
621 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
623 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
625 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
627 // Classes for VLD* pseudo-instructions with multi-register operands.
628 // These are expanded to real instructions after register allocation.
629 class VLDQPseudo<InstrItinClass itin>
630 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
631 class VLDQWBPseudo<InstrItinClass itin>
632 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
633 (ins addrmode6:$addr, am6offset:$offset), itin,
635 class VLDQWBfixedPseudo<InstrItinClass itin>
636 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
637 (ins addrmode6:$addr), itin,
639 class VLDQWBregisterPseudo<InstrItinClass itin>
640 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
641 (ins addrmode6:$addr, rGPR:$offset), itin,
644 class VLDQQPseudo<InstrItinClass itin>
645 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
646 class VLDQQWBPseudo<InstrItinClass itin>
647 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
648 (ins addrmode6:$addr, am6offset:$offset), itin,
650 class VLDQQWBfixedPseudo<InstrItinClass itin>
651 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
652 (ins addrmode6:$addr), itin,
654 class VLDQQWBregisterPseudo<InstrItinClass itin>
655 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
656 (ins addrmode6:$addr, rGPR:$offset), itin,
660 class VLDQQQQPseudo<InstrItinClass itin>
661 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
663 class VLDQQQQWBPseudo<InstrItinClass itin>
664 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
665 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
666 "$addr.addr = $wb, $src = $dst">;
668 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
670 // VLD1 : Vector Load (multiple single elements)
671 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
672 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
673 (ins AddrMode:$Rn), IIC_VLD1,
674 "vld1", Dt, "$Vd, $Rn", "", []> {
677 let DecoderMethod = "DecodeVLDST1Instruction";
679 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode>
680 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
681 (ins AddrMode:$Rn), IIC_VLD1x2,
682 "vld1", Dt, "$Vd, $Rn", "", []> {
684 let Inst{5-4} = Rn{5-4};
685 let DecoderMethod = "DecodeVLDST1Instruction";
688 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
689 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
690 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
691 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
693 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
694 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
695 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
696 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
698 // ...with address register writeback:
699 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
700 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
701 (ins AddrMode:$Rn), IIC_VLD1u,
702 "vld1", Dt, "$Vd, $Rn!",
703 "$Rn.addr = $wb", []> {
704 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
706 let DecoderMethod = "DecodeVLDST1Instruction";
708 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
709 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
710 "vld1", Dt, "$Vd, $Rn, $Rm",
711 "$Rn.addr = $wb", []> {
713 let DecoderMethod = "DecodeVLDST1Instruction";
716 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
717 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
718 (ins AddrMode:$Rn), IIC_VLD1x2u,
719 "vld1", Dt, "$Vd, $Rn!",
720 "$Rn.addr = $wb", []> {
721 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
722 let Inst{5-4} = Rn{5-4};
723 let DecoderMethod = "DecodeVLDST1Instruction";
725 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
726 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
727 "vld1", Dt, "$Vd, $Rn, $Rm",
728 "$Rn.addr = $wb", []> {
729 let Inst{5-4} = Rn{5-4};
730 let DecoderMethod = "DecodeVLDST1Instruction";
734 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
735 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
736 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
737 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
738 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
739 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
740 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
741 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
743 // ...with 3 registers
744 class VLD1D3<bits<4> op7_4, string Dt, Operand AddrMode>
745 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
746 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
747 "$Vd, $Rn", "", []> {
750 let DecoderMethod = "DecodeVLDST1Instruction";
752 multiclass VLD1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
753 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
754 (ins AddrMode:$Rn), IIC_VLD1x2u,
755 "vld1", Dt, "$Vd, $Rn!",
756 "$Rn.addr = $wb", []> {
757 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
759 let DecoderMethod = "DecodeVLDST1Instruction";
761 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
762 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
763 "vld1", Dt, "$Vd, $Rn, $Rm",
764 "$Rn.addr = $wb", []> {
766 let DecoderMethod = "DecodeVLDST1Instruction";
770 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
771 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
772 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
773 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
775 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
776 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
777 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
778 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
780 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
781 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
782 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
784 // ...with 4 registers
785 class VLD1D4<bits<4> op7_4, string Dt, Operand AddrMode>
786 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
787 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
788 "$Vd, $Rn", "", []> {
790 let Inst{5-4} = Rn{5-4};
791 let DecoderMethod = "DecodeVLDST1Instruction";
793 multiclass VLD1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
794 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
795 (ins AddrMode:$Rn), IIC_VLD1x2u,
796 "vld1", Dt, "$Vd, $Rn!",
797 "$Rn.addr = $wb", []> {
798 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
799 let Inst{5-4} = Rn{5-4};
800 let DecoderMethod = "DecodeVLDST1Instruction";
802 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
803 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
804 "vld1", Dt, "$Vd, $Rn, $Rm",
805 "$Rn.addr = $wb", []> {
806 let Inst{5-4} = Rn{5-4};
807 let DecoderMethod = "DecodeVLDST1Instruction";
811 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
812 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
813 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
814 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
816 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
817 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
818 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
819 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
821 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
822 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
823 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
825 // VLD2 : Vector Load (multiple 2-element structures)
826 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
827 InstrItinClass itin, Operand AddrMode>
828 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
829 (ins AddrMode:$Rn), itin,
830 "vld2", Dt, "$Vd, $Rn", "", []> {
832 let Inst{5-4} = Rn{5-4};
833 let DecoderMethod = "DecodeVLDST2Instruction";
836 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
837 addrmode6align64or128>;
838 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
839 addrmode6align64or128>;
840 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
841 addrmode6align64or128>;
843 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
844 addrmode6align64or128or256>;
845 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
846 addrmode6align64or128or256>;
847 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
848 addrmode6align64or128or256>;
850 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
851 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
852 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
854 // ...with address register writeback:
855 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
856 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
857 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
858 (ins AddrMode:$Rn), itin,
859 "vld2", Dt, "$Vd, $Rn!",
860 "$Rn.addr = $wb", []> {
861 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
862 let Inst{5-4} = Rn{5-4};
863 let DecoderMethod = "DecodeVLDST2Instruction";
865 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
866 (ins AddrMode:$Rn, rGPR:$Rm), itin,
867 "vld2", Dt, "$Vd, $Rn, $Rm",
868 "$Rn.addr = $wb", []> {
869 let Inst{5-4} = Rn{5-4};
870 let DecoderMethod = "DecodeVLDST2Instruction";
874 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
875 addrmode6align64or128>;
876 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
877 addrmode6align64or128>;
878 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
879 addrmode6align64or128>;
881 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
882 addrmode6align64or128or256>;
883 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
884 addrmode6align64or128or256>;
885 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
886 addrmode6align64or128or256>;
888 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
889 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
890 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
891 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
892 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
893 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
895 // ...with double-spaced registers
896 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
897 addrmode6align64or128>;
898 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
899 addrmode6align64or128>;
900 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
901 addrmode6align64or128>;
902 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
903 addrmode6align64or128>;
904 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
905 addrmode6align64or128>;
906 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
907 addrmode6align64or128>;
909 // VLD3 : Vector Load (multiple 3-element structures)
910 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
911 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
912 (ins addrmode6:$Rn), IIC_VLD3,
913 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
916 let DecoderMethod = "DecodeVLDST3Instruction";
919 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
920 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
921 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
923 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
924 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
925 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
927 // ...with address register writeback:
928 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
929 : NLdSt<0, 0b10, op11_8, op7_4,
930 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
931 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
932 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
933 "$Rn.addr = $wb", []> {
935 let DecoderMethod = "DecodeVLDST3Instruction";
938 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
939 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
940 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
942 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
943 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
944 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
946 // ...with double-spaced registers:
947 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
948 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
949 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
950 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
951 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
952 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
954 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
955 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
956 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
958 // ...alternate versions to be allocated odd register numbers:
959 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
960 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
961 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
963 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
964 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
965 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
967 // VLD4 : Vector Load (multiple 4-element structures)
968 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
969 : NLdSt<0, 0b10, op11_8, op7_4,
970 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
971 (ins addrmode6:$Rn), IIC_VLD4,
972 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
974 let Inst{5-4} = Rn{5-4};
975 let DecoderMethod = "DecodeVLDST4Instruction";
978 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
979 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
980 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
982 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
983 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
984 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
986 // ...with address register writeback:
987 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
988 : NLdSt<0, 0b10, op11_8, op7_4,
989 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
990 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
991 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
992 "$Rn.addr = $wb", []> {
993 let Inst{5-4} = Rn{5-4};
994 let DecoderMethod = "DecodeVLDST4Instruction";
997 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
998 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
999 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
1001 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1002 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1003 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
1005 // ...with double-spaced registers:
1006 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1007 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1008 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1009 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1010 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1011 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1013 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1014 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1015 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1017 // ...alternate versions to be allocated odd register numbers:
1018 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1019 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1020 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1022 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1023 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1024 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1026 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1028 // Classes for VLD*LN pseudo-instructions with multi-register operands.
1029 // These are expanded to real instructions after register allocation.
1030 class VLDQLNPseudo<InstrItinClass itin>
1031 : PseudoNLdSt<(outs QPR:$dst),
1032 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1033 itin, "$src = $dst">;
1034 class VLDQLNWBPseudo<InstrItinClass itin>
1035 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1036 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1037 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1038 class VLDQQLNPseudo<InstrItinClass itin>
1039 : PseudoNLdSt<(outs QQPR:$dst),
1040 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1041 itin, "$src = $dst">;
1042 class VLDQQLNWBPseudo<InstrItinClass itin>
1043 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
1044 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1045 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1046 class VLDQQQQLNPseudo<InstrItinClass itin>
1047 : PseudoNLdSt<(outs QQQQPR:$dst),
1048 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1049 itin, "$src = $dst">;
1050 class VLDQQQQLNWBPseudo<InstrItinClass itin>
1051 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
1052 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1053 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1055 // VLD1LN : Vector Load (single element to one lane)
1056 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1058 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1059 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1060 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1062 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1063 (i32 (LoadOp addrmode6:$Rn)),
1066 let DecoderMethod = "DecodeVLD1LN";
1068 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1070 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1071 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1072 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1074 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1075 (i32 (LoadOp addrmode6oneL32:$Rn)),
1078 let DecoderMethod = "DecodeVLD1LN";
1080 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1081 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1082 (i32 (LoadOp addrmode6:$addr)),
1086 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1087 let Inst{7-5} = lane{2-0};
1089 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1090 let Inst{7-6} = lane{1-0};
1091 let Inst{5-4} = Rn{5-4};
1093 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1094 let Inst{7} = lane{0};
1095 let Inst{5-4} = Rn{5-4};
1098 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1099 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1100 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1102 def : Pat<(vector_insert (v2f32 DPR:$src),
1103 (f32 (load addrmode6:$addr)), imm:$lane),
1104 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1105 def : Pat<(vector_insert (v4f32 QPR:$src),
1106 (f32 (load addrmode6:$addr)), imm:$lane),
1107 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1109 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1111 // ...with address register writeback:
1112 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1113 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1114 (ins addrmode6:$Rn, am6offset:$Rm,
1115 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1116 "\\{$Vd[$lane]\\}, $Rn$Rm",
1117 "$src = $Vd, $Rn.addr = $wb", []> {
1118 let DecoderMethod = "DecodeVLD1LN";
1121 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1122 let Inst{7-5} = lane{2-0};
1124 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1125 let Inst{7-6} = lane{1-0};
1126 let Inst{4} = Rn{4};
1128 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1129 let Inst{7} = lane{0};
1130 let Inst{5} = Rn{4};
1131 let Inst{4} = Rn{4};
1134 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1135 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1136 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1138 // VLD2LN : Vector Load (single 2-element structure to one lane)
1139 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1140 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1141 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1142 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1143 "$src1 = $Vd, $src2 = $dst2", []> {
1145 let Inst{4} = Rn{4};
1146 let DecoderMethod = "DecodeVLD2LN";
1149 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1150 let Inst{7-5} = lane{2-0};
1152 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1153 let Inst{7-6} = lane{1-0};
1155 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1156 let Inst{7} = lane{0};
1159 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1160 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1161 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1163 // ...with double-spaced registers:
1164 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1165 let Inst{7-6} = lane{1-0};
1167 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1168 let Inst{7} = lane{0};
1171 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1172 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1174 // ...with address register writeback:
1175 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1176 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1177 (ins addrmode6:$Rn, am6offset:$Rm,
1178 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1179 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1180 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1181 let Inst{4} = Rn{4};
1182 let DecoderMethod = "DecodeVLD2LN";
1185 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1186 let Inst{7-5} = lane{2-0};
1188 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1189 let Inst{7-6} = lane{1-0};
1191 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1192 let Inst{7} = lane{0};
1195 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1196 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1197 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1199 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1200 let Inst{7-6} = lane{1-0};
1202 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1203 let Inst{7} = lane{0};
1206 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1207 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1209 // VLD3LN : Vector Load (single 3-element structure to one lane)
1210 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1211 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1212 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1213 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1214 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1215 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1217 let DecoderMethod = "DecodeVLD3LN";
1220 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1221 let Inst{7-5} = lane{2-0};
1223 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1224 let Inst{7-6} = lane{1-0};
1226 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1227 let Inst{7} = lane{0};
1230 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1231 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1232 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1234 // ...with double-spaced registers:
1235 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1236 let Inst{7-6} = lane{1-0};
1238 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1239 let Inst{7} = lane{0};
1242 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1243 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1245 // ...with address register writeback:
1246 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1247 : NLdStLn<1, 0b10, op11_8, op7_4,
1248 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1249 (ins addrmode6:$Rn, am6offset:$Rm,
1250 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1251 IIC_VLD3lnu, "vld3", Dt,
1252 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1253 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1255 let DecoderMethod = "DecodeVLD3LN";
1258 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1259 let Inst{7-5} = lane{2-0};
1261 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1262 let Inst{7-6} = lane{1-0};
1264 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1265 let Inst{7} = lane{0};
1268 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1269 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1270 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1272 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1273 let Inst{7-6} = lane{1-0};
1275 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1276 let Inst{7} = lane{0};
1279 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1280 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1282 // VLD4LN : Vector Load (single 4-element structure to one lane)
1283 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1284 : NLdStLn<1, 0b10, op11_8, op7_4,
1285 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1286 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1287 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1288 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1289 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1291 let Inst{4} = Rn{4};
1292 let DecoderMethod = "DecodeVLD4LN";
1295 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1296 let Inst{7-5} = lane{2-0};
1298 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1299 let Inst{7-6} = lane{1-0};
1301 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1302 let Inst{7} = lane{0};
1303 let Inst{5} = Rn{5};
1306 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1307 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1308 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1310 // ...with double-spaced registers:
1311 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1312 let Inst{7-6} = lane{1-0};
1314 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1315 let Inst{7} = lane{0};
1316 let Inst{5} = Rn{5};
1319 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1320 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1322 // ...with address register writeback:
1323 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1324 : NLdStLn<1, 0b10, op11_8, op7_4,
1325 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1326 (ins addrmode6:$Rn, am6offset:$Rm,
1327 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1328 IIC_VLD4lnu, "vld4", Dt,
1329 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1330 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1332 let Inst{4} = Rn{4};
1333 let DecoderMethod = "DecodeVLD4LN" ;
1336 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1337 let Inst{7-5} = lane{2-0};
1339 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1340 let Inst{7-6} = lane{1-0};
1342 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1343 let Inst{7} = lane{0};
1344 let Inst{5} = Rn{5};
1347 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1348 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1349 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1351 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1352 let Inst{7-6} = lane{1-0};
1354 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1355 let Inst{7} = lane{0};
1356 let Inst{5} = Rn{5};
1359 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1360 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1362 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1364 // VLD1DUP : Vector Load (single element to all lanes)
1365 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1367 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1369 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1370 [(set VecListOneDAllLanes:$Vd,
1371 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1373 let Inst{4} = Rn{4};
1374 let DecoderMethod = "DecodeVLD1DupInstruction";
1376 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1377 addrmode6dupalignNone>;
1378 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1379 addrmode6dupalign16>;
1380 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1381 addrmode6dupalign32>;
1383 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1384 (VLD1DUPd32 addrmode6:$addr)>;
1386 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1388 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1389 (ins AddrMode:$Rn), IIC_VLD1dup,
1390 "vld1", Dt, "$Vd, $Rn", "",
1391 [(set VecListDPairAllLanes:$Vd,
1392 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1394 let Inst{4} = Rn{4};
1395 let DecoderMethod = "DecodeVLD1DupInstruction";
1398 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1399 addrmode6dupalignNone>;
1400 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1401 addrmode6dupalign16>;
1402 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1403 addrmode6dupalign32>;
1405 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1406 (VLD1DUPq32 addrmode6:$addr)>;
1408 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1409 // ...with address register writeback:
1410 multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1411 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1412 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1413 (ins AddrMode:$Rn), IIC_VLD1dupu,
1414 "vld1", Dt, "$Vd, $Rn!",
1415 "$Rn.addr = $wb", []> {
1416 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1417 let Inst{4} = Rn{4};
1418 let DecoderMethod = "DecodeVLD1DupInstruction";
1420 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1421 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1422 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1423 "vld1", Dt, "$Vd, $Rn, $Rm",
1424 "$Rn.addr = $wb", []> {
1425 let Inst{4} = Rn{4};
1426 let DecoderMethod = "DecodeVLD1DupInstruction";
1429 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1430 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1431 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1432 (ins AddrMode:$Rn), IIC_VLD1dupu,
1433 "vld1", Dt, "$Vd, $Rn!",
1434 "$Rn.addr = $wb", []> {
1435 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1436 let Inst{4} = Rn{4};
1437 let DecoderMethod = "DecodeVLD1DupInstruction";
1439 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1440 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1441 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1442 "vld1", Dt, "$Vd, $Rn, $Rm",
1443 "$Rn.addr = $wb", []> {
1444 let Inst{4} = Rn{4};
1445 let DecoderMethod = "DecodeVLD1DupInstruction";
1449 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1450 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1451 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1453 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1454 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1455 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1457 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1458 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1459 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1460 (ins AddrMode:$Rn), IIC_VLD2dup,
1461 "vld2", Dt, "$Vd, $Rn", "", []> {
1463 let Inst{4} = Rn{4};
1464 let DecoderMethod = "DecodeVLD2DupInstruction";
1467 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1468 addrmode6dupalign16>;
1469 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1470 addrmode6dupalign32>;
1471 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1472 addrmode6dupalign64>;
1474 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1475 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
1476 // ...with double-spaced registers
1477 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1478 addrmode6dupalign16>;
1479 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1480 addrmode6dupalign32>;
1481 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1482 addrmode6dupalign64>;
1484 // ...with address register writeback:
1485 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy,
1487 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1488 (outs VdTy:$Vd, GPR:$wb),
1489 (ins AddrMode:$Rn), IIC_VLD2dupu,
1490 "vld2", Dt, "$Vd, $Rn!",
1491 "$Rn.addr = $wb", []> {
1492 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1493 let Inst{4} = Rn{4};
1494 let DecoderMethod = "DecodeVLD2DupInstruction";
1496 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1497 (outs VdTy:$Vd, GPR:$wb),
1498 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1499 "vld2", Dt, "$Vd, $Rn, $Rm",
1500 "$Rn.addr = $wb", []> {
1501 let Inst{4} = Rn{4};
1502 let DecoderMethod = "DecodeVLD2DupInstruction";
1506 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1507 addrmode6dupalign16>;
1508 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1509 addrmode6dupalign32>;
1510 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1511 addrmode6dupalign64>;
1513 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1514 addrmode6dupalign16>;
1515 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1516 addrmode6dupalign32>;
1517 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1518 addrmode6dupalign64>;
1520 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1521 class VLD3DUP<bits<4> op7_4, string Dt>
1522 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1523 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1524 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1527 let DecoderMethod = "DecodeVLD3DupInstruction";
1530 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1531 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1532 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1534 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1535 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1536 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1538 // ...with double-spaced registers (not used for codegen):
1539 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1540 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1541 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1543 // ...with address register writeback:
1544 class VLD3DUPWB<bits<4> op7_4, string Dt, Operand AddrMode>
1545 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1546 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1547 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1548 "$Rn.addr = $wb", []> {
1550 let DecoderMethod = "DecodeVLD3DupInstruction";
1553 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1554 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1555 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1557 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1558 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1559 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1561 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1562 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1563 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1565 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1566 class VLD4DUP<bits<4> op7_4, string Dt>
1567 : NLdSt<1, 0b10, 0b1111, op7_4,
1568 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1569 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1570 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1572 let Inst{4} = Rn{4};
1573 let DecoderMethod = "DecodeVLD4DupInstruction";
1576 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1577 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1578 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1581 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1582 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1584 // ...with double-spaced registers (not used for codegen):
1585 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1586 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1587 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1589 // ...with address register writeback:
1590 class VLD4DUPWB<bits<4> op7_4, string Dt>
1591 : NLdSt<1, 0b10, 0b1111, op7_4,
1592 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1593 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1594 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1595 "$Rn.addr = $wb", []> {
1596 let Inst{4} = Rn{4};
1597 let DecoderMethod = "DecodeVLD4DupInstruction";
1600 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1601 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1602 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1604 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1605 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1606 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1608 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1609 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1610 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1612 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1614 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1616 // Classes for VST* pseudo-instructions with multi-register operands.
1617 // These are expanded to real instructions after register allocation.
1618 class VSTQPseudo<InstrItinClass itin>
1619 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1620 class VSTQWBPseudo<InstrItinClass itin>
1621 : PseudoNLdSt<(outs GPR:$wb),
1622 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1623 "$addr.addr = $wb">;
1624 class VSTQWBfixedPseudo<InstrItinClass itin>
1625 : PseudoNLdSt<(outs GPR:$wb),
1626 (ins addrmode6:$addr, QPR:$src), itin,
1627 "$addr.addr = $wb">;
1628 class VSTQWBregisterPseudo<InstrItinClass itin>
1629 : PseudoNLdSt<(outs GPR:$wb),
1630 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1631 "$addr.addr = $wb">;
1632 class VSTQQPseudo<InstrItinClass itin>
1633 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1634 class VSTQQWBPseudo<InstrItinClass itin>
1635 : PseudoNLdSt<(outs GPR:$wb),
1636 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1637 "$addr.addr = $wb">;
1638 class VSTQQWBfixedPseudo<InstrItinClass itin>
1639 : PseudoNLdSt<(outs GPR:$wb),
1640 (ins addrmode6:$addr, QQPR:$src), itin,
1641 "$addr.addr = $wb">;
1642 class VSTQQWBregisterPseudo<InstrItinClass itin>
1643 : PseudoNLdSt<(outs GPR:$wb),
1644 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1645 "$addr.addr = $wb">;
1647 class VSTQQQQPseudo<InstrItinClass itin>
1648 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1649 class VSTQQQQWBPseudo<InstrItinClass itin>
1650 : PseudoNLdSt<(outs GPR:$wb),
1651 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1652 "$addr.addr = $wb">;
1654 // VST1 : Vector Store (multiple single elements)
1655 class VST1D<bits<4> op7_4, string Dt, Operand AddrMode>
1656 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1657 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1659 let Inst{4} = Rn{4};
1660 let DecoderMethod = "DecodeVLDST1Instruction";
1662 class VST1Q<bits<4> op7_4, string Dt, Operand AddrMode>
1663 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1664 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1666 let Inst{5-4} = Rn{5-4};
1667 let DecoderMethod = "DecodeVLDST1Instruction";
1670 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1671 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1672 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1673 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1675 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1676 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1677 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1678 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1680 // ...with address register writeback:
1681 multiclass VST1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1682 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1683 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1684 "vst1", Dt, "$Vd, $Rn!",
1685 "$Rn.addr = $wb", []> {
1686 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1687 let Inst{4} = Rn{4};
1688 let DecoderMethod = "DecodeVLDST1Instruction";
1690 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1691 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1693 "vst1", Dt, "$Vd, $Rn, $Rm",
1694 "$Rn.addr = $wb", []> {
1695 let Inst{4} = Rn{4};
1696 let DecoderMethod = "DecodeVLDST1Instruction";
1699 multiclass VST1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1700 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1701 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1702 "vst1", Dt, "$Vd, $Rn!",
1703 "$Rn.addr = $wb", []> {
1704 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1705 let Inst{5-4} = Rn{5-4};
1706 let DecoderMethod = "DecodeVLDST1Instruction";
1708 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1709 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1711 "vst1", Dt, "$Vd, $Rn, $Rm",
1712 "$Rn.addr = $wb", []> {
1713 let Inst{5-4} = Rn{5-4};
1714 let DecoderMethod = "DecodeVLDST1Instruction";
1718 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1719 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1720 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1721 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1723 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1724 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1725 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1726 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1728 // ...with 3 registers
1729 class VST1D3<bits<4> op7_4, string Dt, Operand AddrMode>
1730 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1731 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1732 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1734 let Inst{4} = Rn{4};
1735 let DecoderMethod = "DecodeVLDST1Instruction";
1737 multiclass VST1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1738 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1739 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1740 "vst1", Dt, "$Vd, $Rn!",
1741 "$Rn.addr = $wb", []> {
1742 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1743 let Inst{5-4} = Rn{5-4};
1744 let DecoderMethod = "DecodeVLDST1Instruction";
1746 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1747 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1749 "vst1", Dt, "$Vd, $Rn, $Rm",
1750 "$Rn.addr = $wb", []> {
1751 let Inst{5-4} = Rn{5-4};
1752 let DecoderMethod = "DecodeVLDST1Instruction";
1756 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1757 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1758 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1759 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1761 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1762 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1763 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1764 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1766 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1767 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1768 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1770 // ...with 4 registers
1771 class VST1D4<bits<4> op7_4, string Dt, Operand AddrMode>
1772 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1773 (ins AddrMode:$Rn, VecListFourD:$Vd),
1774 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1777 let Inst{5-4} = Rn{5-4};
1778 let DecoderMethod = "DecodeVLDST1Instruction";
1780 multiclass VST1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1781 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1782 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1783 "vst1", Dt, "$Vd, $Rn!",
1784 "$Rn.addr = $wb", []> {
1785 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1786 let Inst{5-4} = Rn{5-4};
1787 let DecoderMethod = "DecodeVLDST1Instruction";
1789 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1790 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1792 "vst1", Dt, "$Vd, $Rn, $Rm",
1793 "$Rn.addr = $wb", []> {
1794 let Inst{5-4} = Rn{5-4};
1795 let DecoderMethod = "DecodeVLDST1Instruction";
1799 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1800 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1801 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1802 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1804 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1805 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1806 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1807 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1809 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1810 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1811 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1813 // VST2 : Vector Store (multiple 2-element structures)
1814 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1815 InstrItinClass itin, Operand AddrMode>
1816 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1817 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1819 let Inst{5-4} = Rn{5-4};
1820 let DecoderMethod = "DecodeVLDST2Instruction";
1823 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1824 addrmode6align64or128>;
1825 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1826 addrmode6align64or128>;
1827 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1828 addrmode6align64or128>;
1830 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1831 addrmode6align64or128or256>;
1832 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1833 addrmode6align64or128or256>;
1834 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1835 addrmode6align64or128or256>;
1837 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1838 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1839 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1841 // ...with address register writeback:
1842 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1843 RegisterOperand VdTy, Operand AddrMode> {
1844 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1845 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1846 "vst2", Dt, "$Vd, $Rn!",
1847 "$Rn.addr = $wb", []> {
1848 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1849 let Inst{5-4} = Rn{5-4};
1850 let DecoderMethod = "DecodeVLDST2Instruction";
1852 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1853 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1854 "vst2", Dt, "$Vd, $Rn, $Rm",
1855 "$Rn.addr = $wb", []> {
1856 let Inst{5-4} = Rn{5-4};
1857 let DecoderMethod = "DecodeVLDST2Instruction";
1860 multiclass VST2QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1861 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1862 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1863 "vst2", Dt, "$Vd, $Rn!",
1864 "$Rn.addr = $wb", []> {
1865 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1866 let Inst{5-4} = Rn{5-4};
1867 let DecoderMethod = "DecodeVLDST2Instruction";
1869 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1870 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1872 "vst2", Dt, "$Vd, $Rn, $Rm",
1873 "$Rn.addr = $wb", []> {
1874 let Inst{5-4} = Rn{5-4};
1875 let DecoderMethod = "DecodeVLDST2Instruction";
1879 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1880 addrmode6align64or128>;
1881 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1882 addrmode6align64or128>;
1883 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1884 addrmode6align64or128>;
1886 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1887 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1888 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1890 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1891 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1892 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1893 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1894 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1895 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1897 // ...with double-spaced registers
1898 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1899 addrmode6align64or128>;
1900 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1901 addrmode6align64or128>;
1902 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1903 addrmode6align64or128>;
1904 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1905 addrmode6align64or128>;
1906 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1907 addrmode6align64or128>;
1908 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1909 addrmode6align64or128>;
1911 // VST3 : Vector Store (multiple 3-element structures)
1912 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1913 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1914 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1915 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1917 let Inst{4} = Rn{4};
1918 let DecoderMethod = "DecodeVLDST3Instruction";
1921 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1922 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1923 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1925 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1926 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1927 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1929 // ...with address register writeback:
1930 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1931 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1932 (ins addrmode6:$Rn, am6offset:$Rm,
1933 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1934 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1935 "$Rn.addr = $wb", []> {
1936 let Inst{4} = Rn{4};
1937 let DecoderMethod = "DecodeVLDST3Instruction";
1940 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1941 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1942 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1944 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1945 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1946 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1948 // ...with double-spaced registers:
1949 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1950 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1951 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1952 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1953 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1954 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1956 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1957 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1958 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1960 // ...alternate versions to be allocated odd register numbers:
1961 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1962 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1963 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1965 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1966 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1967 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1969 // VST4 : Vector Store (multiple 4-element structures)
1970 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1971 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1972 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1973 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1976 let Inst{5-4} = Rn{5-4};
1977 let DecoderMethod = "DecodeVLDST4Instruction";
1980 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1981 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1982 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1984 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1985 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1986 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1988 // ...with address register writeback:
1989 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1990 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1991 (ins addrmode6:$Rn, am6offset:$Rm,
1992 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1993 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1994 "$Rn.addr = $wb", []> {
1995 let Inst{5-4} = Rn{5-4};
1996 let DecoderMethod = "DecodeVLDST4Instruction";
1999 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
2000 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
2001 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
2003 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2004 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2005 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
2007 // ...with double-spaced registers:
2008 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2009 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2010 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2011 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
2012 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2013 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2015 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2016 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2017 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2019 // ...alternate versions to be allocated odd register numbers:
2020 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2021 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2022 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2024 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2025 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2026 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2028 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2030 // Classes for VST*LN pseudo-instructions with multi-register operands.
2031 // These are expanded to real instructions after register allocation.
2032 class VSTQLNPseudo<InstrItinClass itin>
2033 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2035 class VSTQLNWBPseudo<InstrItinClass itin>
2036 : PseudoNLdSt<(outs GPR:$wb),
2037 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2038 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2039 class VSTQQLNPseudo<InstrItinClass itin>
2040 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2042 class VSTQQLNWBPseudo<InstrItinClass itin>
2043 : PseudoNLdSt<(outs GPR:$wb),
2044 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
2045 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2046 class VSTQQQQLNPseudo<InstrItinClass itin>
2047 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2049 class VSTQQQQLNWBPseudo<InstrItinClass itin>
2050 : PseudoNLdSt<(outs GPR:$wb),
2051 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
2052 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2054 // VST1LN : Vector Store (single element from one lane)
2055 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2056 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
2057 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2058 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2059 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2060 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2062 let DecoderMethod = "DecodeVST1LN";
2064 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2065 : VSTQLNPseudo<IIC_VST1ln> {
2066 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2070 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2071 NEONvgetlaneu, addrmode6> {
2072 let Inst{7-5} = lane{2-0};
2074 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
2075 NEONvgetlaneu, addrmode6> {
2076 let Inst{7-6} = lane{1-0};
2077 let Inst{4} = Rn{4};
2080 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2082 let Inst{7} = lane{0};
2083 let Inst{5-4} = Rn{5-4};
2086 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2087 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2088 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2090 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2091 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2092 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2093 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2095 // ...with address register writeback:
2096 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2097 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
2098 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2099 (ins AdrMode:$Rn, am6offset:$Rm,
2100 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2101 "\\{$Vd[$lane]\\}, $Rn$Rm",
2103 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2104 AdrMode:$Rn, am6offset:$Rm))]> {
2105 let DecoderMethod = "DecodeVST1LN";
2107 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2108 : VSTQLNWBPseudo<IIC_VST1lnu> {
2109 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2110 addrmode6:$addr, am6offset:$offset))];
2113 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2114 NEONvgetlaneu, addrmode6> {
2115 let Inst{7-5} = lane{2-0};
2117 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2118 NEONvgetlaneu, addrmode6> {
2119 let Inst{7-6} = lane{1-0};
2120 let Inst{4} = Rn{4};
2122 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2123 extractelt, addrmode6oneL32> {
2124 let Inst{7} = lane{0};
2125 let Inst{5-4} = Rn{5-4};
2128 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2129 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2130 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2132 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2134 // VST2LN : Vector Store (single 2-element structure from one lane)
2135 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2136 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2137 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2138 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2141 let Inst{4} = Rn{4};
2142 let DecoderMethod = "DecodeVST2LN";
2145 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2146 let Inst{7-5} = lane{2-0};
2148 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2149 let Inst{7-6} = lane{1-0};
2151 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2152 let Inst{7} = lane{0};
2155 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2156 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2157 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2159 // ...with double-spaced registers:
2160 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2161 let Inst{7-6} = lane{1-0};
2162 let Inst{4} = Rn{4};
2164 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2165 let Inst{7} = lane{0};
2166 let Inst{4} = Rn{4};
2169 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2170 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2172 // ...with address register writeback:
2173 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2174 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2175 (ins addrmode6:$Rn, am6offset:$Rm,
2176 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2177 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2178 "$Rn.addr = $wb", []> {
2179 let Inst{4} = Rn{4};
2180 let DecoderMethod = "DecodeVST2LN";
2183 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2184 let Inst{7-5} = lane{2-0};
2186 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2187 let Inst{7-6} = lane{1-0};
2189 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2190 let Inst{7} = lane{0};
2193 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2194 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2195 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2197 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2198 let Inst{7-6} = lane{1-0};
2200 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2201 let Inst{7} = lane{0};
2204 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2205 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2207 // VST3LN : Vector Store (single 3-element structure from one lane)
2208 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2209 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2210 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2211 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2212 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2214 let DecoderMethod = "DecodeVST3LN";
2217 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2218 let Inst{7-5} = lane{2-0};
2220 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2221 let Inst{7-6} = lane{1-0};
2223 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2224 let Inst{7} = lane{0};
2227 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2228 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2229 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2231 // ...with double-spaced registers:
2232 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2233 let Inst{7-6} = lane{1-0};
2235 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2236 let Inst{7} = lane{0};
2239 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2240 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2242 // ...with address register writeback:
2243 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2244 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2245 (ins addrmode6:$Rn, am6offset:$Rm,
2246 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2247 IIC_VST3lnu, "vst3", Dt,
2248 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2249 "$Rn.addr = $wb", []> {
2250 let DecoderMethod = "DecodeVST3LN";
2253 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2254 let Inst{7-5} = lane{2-0};
2256 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2257 let Inst{7-6} = lane{1-0};
2259 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2260 let Inst{7} = lane{0};
2263 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2264 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2265 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2267 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2268 let Inst{7-6} = lane{1-0};
2270 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2271 let Inst{7} = lane{0};
2274 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2275 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2277 // VST4LN : Vector Store (single 4-element structure from one lane)
2278 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2279 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2280 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2281 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2282 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2285 let Inst{4} = Rn{4};
2286 let DecoderMethod = "DecodeVST4LN";
2289 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2290 let Inst{7-5} = lane{2-0};
2292 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2293 let Inst{7-6} = lane{1-0};
2295 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2296 let Inst{7} = lane{0};
2297 let Inst{5} = Rn{5};
2300 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2301 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2302 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2304 // ...with double-spaced registers:
2305 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2306 let Inst{7-6} = lane{1-0};
2308 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2309 let Inst{7} = lane{0};
2310 let Inst{5} = Rn{5};
2313 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2314 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2316 // ...with address register writeback:
2317 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2318 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2319 (ins addrmode6:$Rn, am6offset:$Rm,
2320 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2321 IIC_VST4lnu, "vst4", Dt,
2322 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2323 "$Rn.addr = $wb", []> {
2324 let Inst{4} = Rn{4};
2325 let DecoderMethod = "DecodeVST4LN";
2328 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2329 let Inst{7-5} = lane{2-0};
2331 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2332 let Inst{7-6} = lane{1-0};
2334 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2335 let Inst{7} = lane{0};
2336 let Inst{5} = Rn{5};
2339 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2340 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2341 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2343 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2344 let Inst{7-6} = lane{1-0};
2346 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2347 let Inst{7} = lane{0};
2348 let Inst{5} = Rn{5};
2351 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2352 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2354 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2356 // Use vld1/vst1 for unaligned f64 load / store
2357 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2358 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2359 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2360 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2361 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2362 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2363 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2364 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2365 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2366 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2367 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2368 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2370 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2371 // load / store if it's legal.
2372 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2373 (VLD1q64 addrmode6:$addr)>;
2374 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2375 (VST1q64 addrmode6:$addr, QPR:$value)>;
2376 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2377 (VLD1q32 addrmode6:$addr)>, Requires<[IsLE]>;
2378 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2379 (VST1q32 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2380 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2381 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2382 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2383 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2384 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2385 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2386 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2387 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2389 //===----------------------------------------------------------------------===//
2390 // NEON pattern fragments
2391 //===----------------------------------------------------------------------===//
2393 // Extract D sub-registers of Q registers.
2394 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2395 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2396 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2398 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2399 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2400 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2402 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2403 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2404 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2406 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2407 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2408 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2411 // Extract S sub-registers of Q/D registers.
2412 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2413 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2414 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2417 // Translate lane numbers from Q registers to D subregs.
2418 def SubReg_i8_lane : SDNodeXForm<imm, [{
2419 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2421 def SubReg_i16_lane : SDNodeXForm<imm, [{
2422 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2424 def SubReg_i32_lane : SDNodeXForm<imm, [{
2425 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2428 //===----------------------------------------------------------------------===//
2429 // Instruction Classes
2430 //===----------------------------------------------------------------------===//
2432 // Basic 2-register operations: double- and quad-register.
2433 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2434 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2435 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2436 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2437 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2439 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2440 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2441 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2442 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2443 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2446 // Basic 2-register intrinsics, both double- and quad-register.
2447 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2448 bits<2> op17_16, bits<5> op11_7, bit op4,
2449 InstrItinClass itin, string OpcodeStr, string Dt,
2450 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2451 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2452 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2454 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2455 bits<2> op17_16, bits<5> op11_7, bit op4,
2456 InstrItinClass itin, string OpcodeStr, string Dt,
2457 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2459 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2462 // Same as above, but not predicated.
2463 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2464 InstrItinClass itin, string OpcodeStr, string Dt,
2465 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2466 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2467 itin, OpcodeStr, Dt,
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2470 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2471 InstrItinClass itin, string OpcodeStr, string Dt,
2472 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2473 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2474 itin, OpcodeStr, Dt,
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2477 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2478 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2479 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2480 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2482 itin, OpcodeStr, Dt,
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2485 // Same as N2VQIntXnp but with Vd as a src register.
2486 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2487 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2488 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2489 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2490 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2491 itin, OpcodeStr, Dt,
2492 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2493 let Constraints = "$src = $Vd";
2496 // Narrow 2-register operations.
2497 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2498 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2499 InstrItinClass itin, string OpcodeStr, string Dt,
2500 ValueType TyD, ValueType TyQ, SDNode OpNode>
2501 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2502 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2505 // Narrow 2-register intrinsics.
2506 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2507 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2508 InstrItinClass itin, string OpcodeStr, string Dt,
2509 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2510 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2511 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2512 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2514 // Long 2-register operations (currently only used for VMOVL).
2515 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2516 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2517 InstrItinClass itin, string OpcodeStr, string Dt,
2518 ValueType TyQ, ValueType TyD, SDNode OpNode>
2519 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2520 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2523 // Long 2-register intrinsics.
2524 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2525 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2526 InstrItinClass itin, string OpcodeStr, string Dt,
2527 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2528 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2529 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2530 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2532 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2533 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2534 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2535 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2536 OpcodeStr, Dt, "$Vd, $Vm",
2537 "$src1 = $Vd, $src2 = $Vm", []>;
2538 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2539 InstrItinClass itin, string OpcodeStr, string Dt>
2540 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2541 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2542 "$src1 = $Vd, $src2 = $Vm", []>;
2544 // Basic 3-register operations: double- and quad-register.
2545 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2546 InstrItinClass itin, string OpcodeStr, string Dt,
2547 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2548 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2549 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2552 // All of these have a two-operand InstAlias.
2553 let TwoOperandAliasConstraint = "$Vn = $Vd";
2554 let isCommutable = Commutable;
2556 // Same as N3VD but no data type.
2557 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2558 InstrItinClass itin, string OpcodeStr,
2559 ValueType ResTy, ValueType OpTy,
2560 SDNode OpNode, bit Commutable>
2561 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2562 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2563 OpcodeStr, "$Vd, $Vn, $Vm", "",
2564 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2565 // All of these have a two-operand InstAlias.
2566 let TwoOperandAliasConstraint = "$Vn = $Vd";
2567 let isCommutable = Commutable;
2570 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2571 InstrItinClass itin, string OpcodeStr, string Dt,
2572 ValueType Ty, SDNode ShOp>
2573 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2575 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2577 (Ty (ShOp (Ty DPR:$Vn),
2578 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2579 // All of these have a two-operand InstAlias.
2580 let TwoOperandAliasConstraint = "$Vn = $Vd";
2581 let isCommutable = 0;
2583 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2584 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2585 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2586 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2587 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2589 (Ty (ShOp (Ty DPR:$Vn),
2590 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2591 // All of these have a two-operand InstAlias.
2592 let TwoOperandAliasConstraint = "$Vn = $Vd";
2593 let isCommutable = 0;
2596 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2597 InstrItinClass itin, string OpcodeStr, string Dt,
2598 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2599 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2600 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2601 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2602 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2603 // All of these have a two-operand InstAlias.
2604 let TwoOperandAliasConstraint = "$Vn = $Vd";
2605 let isCommutable = Commutable;
2607 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2608 InstrItinClass itin, string OpcodeStr,
2609 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2610 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2611 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2612 OpcodeStr, "$Vd, $Vn, $Vm", "",
2613 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2614 // All of these have a two-operand InstAlias.
2615 let TwoOperandAliasConstraint = "$Vn = $Vd";
2616 let isCommutable = Commutable;
2618 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2619 InstrItinClass itin, string OpcodeStr, string Dt,
2620 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2621 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2623 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2624 [(set (ResTy QPR:$Vd),
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2626 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2628 // All of these have a two-operand InstAlias.
2629 let TwoOperandAliasConstraint = "$Vn = $Vd";
2630 let isCommutable = 0;
2632 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2633 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2634 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2636 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2637 [(set (ResTy QPR:$Vd),
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2639 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2641 // All of these have a two-operand InstAlias.
2642 let TwoOperandAliasConstraint = "$Vn = $Vd";
2643 let isCommutable = 0;
2646 // Basic 3-register intrinsics, both double- and quad-register.
2647 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2648 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2649 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2650 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2651 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2652 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2653 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2654 // All of these have a two-operand InstAlias.
2655 let TwoOperandAliasConstraint = "$Vn = $Vd";
2656 let isCommutable = Commutable;
2659 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2660 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2661 string Dt, ValueType ResTy, ValueType OpTy,
2662 SDPatternOperator IntOp, bit Commutable>
2663 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2664 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2665 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2667 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2668 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2669 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2670 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2671 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2673 (Ty (IntOp (Ty DPR:$Vn),
2674 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2676 let isCommutable = 0;
2679 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2680 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2681 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2682 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2683 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2685 (Ty (IntOp (Ty DPR:$Vn),
2686 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2687 let isCommutable = 0;
2689 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2690 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2691 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2692 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2693 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2694 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2695 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2696 let TwoOperandAliasConstraint = "$Vm = $Vd";
2697 let isCommutable = 0;
2700 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2701 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2702 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2703 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2704 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2705 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2706 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2707 // All of these have a two-operand InstAlias.
2708 let TwoOperandAliasConstraint = "$Vn = $Vd";
2709 let isCommutable = Commutable;
2712 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2713 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2714 string Dt, ValueType ResTy, ValueType OpTy,
2715 SDPatternOperator IntOp, bit Commutable>
2716 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2717 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2718 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2720 // Same as N3VQIntnp but with Vd as a src register.
2721 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2722 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2723 string Dt, ValueType ResTy, ValueType OpTy,
2724 SDPatternOperator IntOp, bit Commutable>
2725 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2726 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2727 f, itin, OpcodeStr, Dt,
2728 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2729 (OpTy QPR:$Vm))))]> {
2730 let Constraints = "$src = $Vd";
2733 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2734 string OpcodeStr, string Dt,
2735 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2736 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2738 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2739 [(set (ResTy QPR:$Vd),
2740 (ResTy (IntOp (ResTy QPR:$Vn),
2741 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2743 let isCommutable = 0;
2745 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2746 string OpcodeStr, string Dt,
2747 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2748 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2750 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2751 [(set (ResTy QPR:$Vd),
2752 (ResTy (IntOp (ResTy QPR:$Vn),
2753 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2755 let isCommutable = 0;
2757 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2758 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2759 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2760 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2761 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2762 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2763 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2764 let TwoOperandAliasConstraint = "$Vm = $Vd";
2765 let isCommutable = 0;
2768 // Multiply-Add/Sub operations: double- and quad-register.
2769 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2770 InstrItinClass itin, string OpcodeStr, string Dt,
2771 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2772 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2773 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2774 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2775 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2776 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2778 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2779 string OpcodeStr, string Dt,
2780 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2781 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2783 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2785 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2787 (Ty (ShOp (Ty DPR:$src1),
2789 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2791 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2792 string OpcodeStr, string Dt,
2793 ValueType Ty, SDNode MulOp, SDNode ShOp>
2794 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2796 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2798 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2800 (Ty (ShOp (Ty DPR:$src1),
2802 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2805 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2806 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2807 SDPatternOperator MulOp, SDPatternOperator OpNode>
2808 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2809 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2810 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2811 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2812 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2813 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2814 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2815 SDPatternOperator MulOp, SDPatternOperator ShOp>
2816 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2818 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2820 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2821 [(set (ResTy QPR:$Vd),
2822 (ResTy (ShOp (ResTy QPR:$src1),
2823 (ResTy (MulOp QPR:$Vn,
2824 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2826 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2827 string OpcodeStr, string Dt,
2828 ValueType ResTy, ValueType OpTy,
2829 SDNode MulOp, SDNode ShOp>
2830 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2832 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2834 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2835 [(set (ResTy QPR:$Vd),
2836 (ResTy (ShOp (ResTy QPR:$src1),
2837 (ResTy (MulOp QPR:$Vn,
2838 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2841 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2842 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2843 InstrItinClass itin, string OpcodeStr, string Dt,
2844 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2845 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2846 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2847 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2848 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2849 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2850 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2851 InstrItinClass itin, string OpcodeStr, string Dt,
2852 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2853 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2854 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2855 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2856 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2857 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2859 // Neon 3-argument intrinsics, both double- and quad-register.
2860 // The destination register is also used as the first source operand register.
2861 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2862 InstrItinClass itin, string OpcodeStr, string Dt,
2863 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2864 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2865 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2866 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2867 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2868 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2869 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2870 InstrItinClass itin, string OpcodeStr, string Dt,
2871 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2872 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2873 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2874 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2875 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2876 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2878 // Long Multiply-Add/Sub operations.
2879 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2880 InstrItinClass itin, string OpcodeStr, string Dt,
2881 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2882 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2883 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2884 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2885 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2886 (TyQ (MulOp (TyD DPR:$Vn),
2887 (TyD DPR:$Vm)))))]>;
2888 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2889 InstrItinClass itin, string OpcodeStr, string Dt,
2890 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2891 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2894 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2896 (OpNode (TyQ QPR:$src1),
2897 (TyQ (MulOp (TyD DPR:$Vn),
2898 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2900 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2901 InstrItinClass itin, string OpcodeStr, string Dt,
2902 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2903 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2906 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2908 (OpNode (TyQ QPR:$src1),
2909 (TyQ (MulOp (TyD DPR:$Vn),
2910 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2913 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2914 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2915 InstrItinClass itin, string OpcodeStr, string Dt,
2916 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2918 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2919 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2920 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2921 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2922 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2923 (TyD DPR:$Vm)))))))]>;
2925 // Neon Long 3-argument intrinsic. The destination register is
2926 // a quad-register and is also used as the first source operand register.
2927 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2928 InstrItinClass itin, string OpcodeStr, string Dt,
2929 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2930 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2931 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2932 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2934 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2935 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2936 string OpcodeStr, string Dt,
2937 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2938 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2942 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2943 [(set (ResTy QPR:$Vd),
2944 (ResTy (IntOp (ResTy QPR:$src1),
2946 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2948 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2949 InstrItinClass itin, string OpcodeStr, string Dt,
2950 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2951 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2955 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2956 [(set (ResTy QPR:$Vd),
2957 (ResTy (IntOp (ResTy QPR:$src1),
2959 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2962 // Narrowing 3-register intrinsics.
2963 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2964 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2965 SDPatternOperator IntOp, bit Commutable>
2966 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2967 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2968 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2969 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2970 let isCommutable = Commutable;
2973 // Long 3-register operations.
2974 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2975 InstrItinClass itin, string OpcodeStr, string Dt,
2976 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2977 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2978 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2979 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2980 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2981 let isCommutable = Commutable;
2984 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2985 InstrItinClass itin, string OpcodeStr, string Dt,
2986 ValueType TyQ, ValueType TyD, SDNode OpNode>
2987 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2989 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2991 (TyQ (OpNode (TyD DPR:$Vn),
2992 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2993 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2994 InstrItinClass itin, string OpcodeStr, string Dt,
2995 ValueType TyQ, ValueType TyD, SDNode OpNode>
2996 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2998 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3000 (TyQ (OpNode (TyD DPR:$Vn),
3001 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
3003 // Long 3-register operations with explicitly extended operands.
3004 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3005 InstrItinClass itin, string OpcodeStr, string Dt,
3006 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3008 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3009 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3010 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3012 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3013 let isCommutable = Commutable;
3016 // Long 3-register intrinsics with explicit extend (VABDL).
3017 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3018 InstrItinClass itin, string OpcodeStr, string Dt,
3019 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3021 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3022 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3023 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3025 (TyD DPR:$Vm))))))]> {
3026 let isCommutable = Commutable;
3029 // Long 3-register intrinsics.
3030 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3031 InstrItinClass itin, string OpcodeStr, string Dt,
3032 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
3033 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3034 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3035 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3036 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3037 let isCommutable = Commutable;
3040 // Same as above, but not predicated.
3041 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
3042 bit op4, InstrItinClass itin, string OpcodeStr,
3043 string Dt, ValueType ResTy, ValueType OpTy,
3044 SDPatternOperator IntOp, bit Commutable>
3045 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
3046 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3047 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3049 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
3050 string OpcodeStr, string Dt,
3051 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3052 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3054 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3055 [(set (ResTy QPR:$Vd),
3056 (ResTy (IntOp (OpTy DPR:$Vn),
3057 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
3059 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
3060 InstrItinClass itin, string OpcodeStr, string Dt,
3061 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3062 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3064 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3065 [(set (ResTy QPR:$Vd),
3066 (ResTy (IntOp (OpTy DPR:$Vn),
3067 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
3070 // Wide 3-register operations.
3071 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3072 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
3073 SDNode OpNode, SDNode ExtOp, bit Commutable>
3074 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3075 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3076 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3077 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3078 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3079 // All of these have a two-operand InstAlias.
3080 let TwoOperandAliasConstraint = "$Vn = $Vd";
3081 let isCommutable = Commutable;
3084 // Pairwise long 2-register intrinsics, both double- and quad-register.
3085 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3086 bits<2> op17_16, bits<5> op11_7, bit op4,
3087 string OpcodeStr, string Dt,
3088 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3089 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3090 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3091 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3092 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3093 bits<2> op17_16, bits<5> op11_7, bit op4,
3094 string OpcodeStr, string Dt,
3095 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3096 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3097 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3098 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3100 // Pairwise long 2-register accumulate intrinsics,
3101 // both double- and quad-register.
3102 // The destination register is also used as the first source operand register.
3103 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3104 bits<2> op17_16, bits<5> op11_7, bit op4,
3105 string OpcodeStr, string Dt,
3106 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3107 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3108 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3109 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3110 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3111 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3112 bits<2> op17_16, bits<5> op11_7, bit op4,
3113 string OpcodeStr, string Dt,
3114 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3115 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3116 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3117 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3118 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3120 // Shift by immediate,
3121 // both double- and quad-register.
3122 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3123 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3124 Format f, InstrItinClass itin, Operand ImmTy,
3125 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3126 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3127 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3128 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3129 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3130 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3131 Format f, InstrItinClass itin, Operand ImmTy,
3132 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3133 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3134 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3135 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3136 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3139 // Long shift by immediate.
3140 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3141 string OpcodeStr, string Dt,
3142 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3143 SDPatternOperator OpNode>
3144 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3146 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3149 // Narrow shift by immediate.
3150 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3151 InstrItinClass itin, string OpcodeStr, string Dt,
3152 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3153 SDPatternOperator OpNode>
3154 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3156 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3157 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3158 (i32 ImmTy:$SIMM))))]>;
3160 // Shift right by immediate and accumulate,
3161 // both double- and quad-register.
3162 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3163 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3164 Operand ImmTy, string OpcodeStr, string Dt,
3165 ValueType Ty, SDNode ShOp>
3166 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3167 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3168 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3169 [(set DPR:$Vd, (Ty (add DPR:$src1,
3170 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3171 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3172 Operand ImmTy, string OpcodeStr, string Dt,
3173 ValueType Ty, SDNode ShOp>
3174 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3175 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3176 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3177 [(set QPR:$Vd, (Ty (add QPR:$src1,
3178 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3181 // Shift by immediate and insert,
3182 // both double- and quad-register.
3183 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3184 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3185 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3186 ValueType Ty,SDNode ShOp>
3187 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3188 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3189 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3190 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3191 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3192 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3193 ValueType Ty,SDNode ShOp>
3194 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3195 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3196 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3197 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3200 // Convert, with fractional bits immediate,
3201 // both double- and quad-register.
3202 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3203 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3204 SDPatternOperator IntOp>
3205 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3206 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3207 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3208 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3209 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3210 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3211 SDPatternOperator IntOp>
3212 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3213 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3214 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3215 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3217 //===----------------------------------------------------------------------===//
3219 //===----------------------------------------------------------------------===//
3221 // Abbreviations used in multiclass suffixes:
3222 // Q = quarter int (8 bit) elements
3223 // H = half int (16 bit) elements
3224 // S = single int (32 bit) elements
3225 // D = double int (64 bit) elements
3227 // Neon 2-register vector operations and intrinsics.
3229 // Neon 2-register comparisons.
3230 // source operand element sizes of 8, 16 and 32 bits:
3231 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3232 bits<5> op11_7, bit op4, string opc, string Dt,
3233 string asm, SDNode OpNode> {
3234 // 64-bit vector types.
3235 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3236 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3237 opc, !strconcat(Dt, "8"), asm, "",
3238 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3239 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3240 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3241 opc, !strconcat(Dt, "16"), asm, "",
3242 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3243 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3244 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3245 opc, !strconcat(Dt, "32"), asm, "",
3246 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3247 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3248 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3249 opc, "f32", asm, "",
3250 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3251 let Inst{10} = 1; // overwrite F = 1
3254 // 128-bit vector types.
3255 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3256 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3257 opc, !strconcat(Dt, "8"), asm, "",
3258 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3259 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3260 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3261 opc, !strconcat(Dt, "16"), asm, "",
3262 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3263 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3264 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3265 opc, !strconcat(Dt, "32"), asm, "",
3266 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3267 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3268 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3269 opc, "f32", asm, "",
3270 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3271 let Inst{10} = 1; // overwrite F = 1
3276 // Neon 2-register vector intrinsics,
3277 // element sizes of 8, 16 and 32 bits:
3278 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3279 bits<5> op11_7, bit op4,
3280 InstrItinClass itinD, InstrItinClass itinQ,
3281 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3282 // 64-bit vector types.
3283 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3284 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3285 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3286 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3287 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3288 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3290 // 128-bit vector types.
3291 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3292 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3293 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3294 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3295 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3296 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3300 // Neon Narrowing 2-register vector operations,
3301 // source operand element sizes of 16, 32 and 64 bits:
3302 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3303 bits<5> op11_7, bit op6, bit op4,
3304 InstrItinClass itin, string OpcodeStr, string Dt,
3306 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3307 itin, OpcodeStr, !strconcat(Dt, "16"),
3308 v8i8, v8i16, OpNode>;
3309 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3310 itin, OpcodeStr, !strconcat(Dt, "32"),
3311 v4i16, v4i32, OpNode>;
3312 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3313 itin, OpcodeStr, !strconcat(Dt, "64"),
3314 v2i32, v2i64, OpNode>;
3317 // Neon Narrowing 2-register vector intrinsics,
3318 // source operand element sizes of 16, 32 and 64 bits:
3319 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3320 bits<5> op11_7, bit op6, bit op4,
3321 InstrItinClass itin, string OpcodeStr, string Dt,
3322 SDPatternOperator IntOp> {
3323 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3324 itin, OpcodeStr, !strconcat(Dt, "16"),
3325 v8i8, v8i16, IntOp>;
3326 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3327 itin, OpcodeStr, !strconcat(Dt, "32"),
3328 v4i16, v4i32, IntOp>;
3329 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3330 itin, OpcodeStr, !strconcat(Dt, "64"),
3331 v2i32, v2i64, IntOp>;
3335 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3336 // source operand element sizes of 16, 32 and 64 bits:
3337 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3338 string OpcodeStr, string Dt, SDNode OpNode> {
3339 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3340 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3341 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3342 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3343 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3344 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3348 // Neon 3-register vector operations.
3350 // First with only element sizes of 8, 16 and 32 bits:
3351 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3352 InstrItinClass itinD16, InstrItinClass itinD32,
3353 InstrItinClass itinQ16, InstrItinClass itinQ32,
3354 string OpcodeStr, string Dt,
3355 SDNode OpNode, bit Commutable = 0> {
3356 // 64-bit vector types.
3357 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3358 OpcodeStr, !strconcat(Dt, "8"),
3359 v8i8, v8i8, OpNode, Commutable>;
3360 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3361 OpcodeStr, !strconcat(Dt, "16"),
3362 v4i16, v4i16, OpNode, Commutable>;
3363 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3364 OpcodeStr, !strconcat(Dt, "32"),
3365 v2i32, v2i32, OpNode, Commutable>;
3367 // 128-bit vector types.
3368 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3369 OpcodeStr, !strconcat(Dt, "8"),
3370 v16i8, v16i8, OpNode, Commutable>;
3371 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3372 OpcodeStr, !strconcat(Dt, "16"),
3373 v8i16, v8i16, OpNode, Commutable>;
3374 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3375 OpcodeStr, !strconcat(Dt, "32"),
3376 v4i32, v4i32, OpNode, Commutable>;
3379 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3380 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3381 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3382 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3383 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3384 v4i32, v2i32, ShOp>;
3387 // ....then also with element size 64 bits:
3388 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3389 InstrItinClass itinD, InstrItinClass itinQ,
3390 string OpcodeStr, string Dt,
3391 SDNode OpNode, bit Commutable = 0>
3392 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3393 OpcodeStr, Dt, OpNode, Commutable> {
3394 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3395 OpcodeStr, !strconcat(Dt, "64"),
3396 v1i64, v1i64, OpNode, Commutable>;
3397 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3398 OpcodeStr, !strconcat(Dt, "64"),
3399 v2i64, v2i64, OpNode, Commutable>;
3403 // Neon 3-register vector intrinsics.
3405 // First with only element sizes of 16 and 32 bits:
3406 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3407 InstrItinClass itinD16, InstrItinClass itinD32,
3408 InstrItinClass itinQ16, InstrItinClass itinQ32,
3409 string OpcodeStr, string Dt,
3410 SDPatternOperator IntOp, bit Commutable = 0> {
3411 // 64-bit vector types.
3412 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3413 OpcodeStr, !strconcat(Dt, "16"),
3414 v4i16, v4i16, IntOp, Commutable>;
3415 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3416 OpcodeStr, !strconcat(Dt, "32"),
3417 v2i32, v2i32, IntOp, Commutable>;
3419 // 128-bit vector types.
3420 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3421 OpcodeStr, !strconcat(Dt, "16"),
3422 v8i16, v8i16, IntOp, Commutable>;
3423 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3424 OpcodeStr, !strconcat(Dt, "32"),
3425 v4i32, v4i32, IntOp, Commutable>;
3427 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3428 InstrItinClass itinD16, InstrItinClass itinD32,
3429 InstrItinClass itinQ16, InstrItinClass itinQ32,
3430 string OpcodeStr, string Dt,
3431 SDPatternOperator IntOp> {
3432 // 64-bit vector types.
3433 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3434 OpcodeStr, !strconcat(Dt, "16"),
3435 v4i16, v4i16, IntOp>;
3436 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3437 OpcodeStr, !strconcat(Dt, "32"),
3438 v2i32, v2i32, IntOp>;
3440 // 128-bit vector types.
3441 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3442 OpcodeStr, !strconcat(Dt, "16"),
3443 v8i16, v8i16, IntOp>;
3444 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3445 OpcodeStr, !strconcat(Dt, "32"),
3446 v4i32, v4i32, IntOp>;
3449 multiclass N3VIntSL_HS<bits<4> op11_8,
3450 InstrItinClass itinD16, InstrItinClass itinD32,
3451 InstrItinClass itinQ16, InstrItinClass itinQ32,
3452 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3453 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3454 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3455 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3456 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3457 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3458 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3459 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3460 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3463 // ....then also with element size of 8 bits:
3464 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3465 InstrItinClass itinD16, InstrItinClass itinD32,
3466 InstrItinClass itinQ16, InstrItinClass itinQ32,
3467 string OpcodeStr, string Dt,
3468 SDPatternOperator IntOp, bit Commutable = 0>
3469 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3470 OpcodeStr, Dt, IntOp, Commutable> {
3471 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3472 OpcodeStr, !strconcat(Dt, "8"),
3473 v8i8, v8i8, IntOp, Commutable>;
3474 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3475 OpcodeStr, !strconcat(Dt, "8"),
3476 v16i8, v16i8, IntOp, Commutable>;
3478 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3479 InstrItinClass itinD16, InstrItinClass itinD32,
3480 InstrItinClass itinQ16, InstrItinClass itinQ32,
3481 string OpcodeStr, string Dt,
3482 SDPatternOperator IntOp>
3483 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3484 OpcodeStr, Dt, IntOp> {
3485 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3486 OpcodeStr, !strconcat(Dt, "8"),
3488 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3489 OpcodeStr, !strconcat(Dt, "8"),
3490 v16i8, v16i8, IntOp>;
3494 // ....then also with element size of 64 bits:
3495 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3496 InstrItinClass itinD16, InstrItinClass itinD32,
3497 InstrItinClass itinQ16, InstrItinClass itinQ32,
3498 string OpcodeStr, string Dt,
3499 SDPatternOperator IntOp, bit Commutable = 0>
3500 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3501 OpcodeStr, Dt, IntOp, Commutable> {
3502 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3503 OpcodeStr, !strconcat(Dt, "64"),
3504 v1i64, v1i64, IntOp, Commutable>;
3505 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3506 OpcodeStr, !strconcat(Dt, "64"),
3507 v2i64, v2i64, IntOp, Commutable>;
3509 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3510 InstrItinClass itinD16, InstrItinClass itinD32,
3511 InstrItinClass itinQ16, InstrItinClass itinQ32,
3512 string OpcodeStr, string Dt,
3513 SDPatternOperator IntOp>
3514 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3515 OpcodeStr, Dt, IntOp> {
3516 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3517 OpcodeStr, !strconcat(Dt, "64"),
3518 v1i64, v1i64, IntOp>;
3519 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3520 OpcodeStr, !strconcat(Dt, "64"),
3521 v2i64, v2i64, IntOp>;
3524 // Neon Narrowing 3-register vector intrinsics,
3525 // source operand element sizes of 16, 32 and 64 bits:
3526 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3527 string OpcodeStr, string Dt,
3528 SDPatternOperator IntOp, bit Commutable = 0> {
3529 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3530 OpcodeStr, !strconcat(Dt, "16"),
3531 v8i8, v8i16, IntOp, Commutable>;
3532 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3533 OpcodeStr, !strconcat(Dt, "32"),
3534 v4i16, v4i32, IntOp, Commutable>;
3535 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3536 OpcodeStr, !strconcat(Dt, "64"),
3537 v2i32, v2i64, IntOp, Commutable>;
3541 // Neon Long 3-register vector operations.
3543 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3544 InstrItinClass itin16, InstrItinClass itin32,
3545 string OpcodeStr, string Dt,
3546 SDNode OpNode, bit Commutable = 0> {
3547 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3548 OpcodeStr, !strconcat(Dt, "8"),
3549 v8i16, v8i8, OpNode, Commutable>;
3550 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3551 OpcodeStr, !strconcat(Dt, "16"),
3552 v4i32, v4i16, OpNode, Commutable>;
3553 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3554 OpcodeStr, !strconcat(Dt, "32"),
3555 v2i64, v2i32, OpNode, Commutable>;
3558 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3559 InstrItinClass itin, string OpcodeStr, string Dt,
3561 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3562 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3563 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3564 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3567 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3568 InstrItinClass itin16, InstrItinClass itin32,
3569 string OpcodeStr, string Dt,
3570 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3571 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3572 OpcodeStr, !strconcat(Dt, "8"),
3573 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3574 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3575 OpcodeStr, !strconcat(Dt, "16"),
3576 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3577 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3578 OpcodeStr, !strconcat(Dt, "32"),
3579 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3582 // Neon Long 3-register vector intrinsics.
3584 // First with only element sizes of 16 and 32 bits:
3585 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3586 InstrItinClass itin16, InstrItinClass itin32,
3587 string OpcodeStr, string Dt,
3588 SDPatternOperator IntOp, bit Commutable = 0> {
3589 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3590 OpcodeStr, !strconcat(Dt, "16"),
3591 v4i32, v4i16, IntOp, Commutable>;
3592 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3593 OpcodeStr, !strconcat(Dt, "32"),
3594 v2i64, v2i32, IntOp, Commutable>;
3597 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3598 InstrItinClass itin, string OpcodeStr, string Dt,
3599 SDPatternOperator IntOp> {
3600 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3601 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3602 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3603 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3606 // ....then also with element size of 8 bits:
3607 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3608 InstrItinClass itin16, InstrItinClass itin32,
3609 string OpcodeStr, string Dt,
3610 SDPatternOperator IntOp, bit Commutable = 0>
3611 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3612 IntOp, Commutable> {
3613 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3614 OpcodeStr, !strconcat(Dt, "8"),
3615 v8i16, v8i8, IntOp, Commutable>;
3618 // ....with explicit extend (VABDL).
3619 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3620 InstrItinClass itin, string OpcodeStr, string Dt,
3621 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3622 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3623 OpcodeStr, !strconcat(Dt, "8"),
3624 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3625 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3626 OpcodeStr, !strconcat(Dt, "16"),
3627 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3628 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3629 OpcodeStr, !strconcat(Dt, "32"),
3630 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3634 // Neon Wide 3-register vector intrinsics,
3635 // source operand element sizes of 8, 16 and 32 bits:
3636 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3637 string OpcodeStr, string Dt,
3638 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3639 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3640 OpcodeStr, !strconcat(Dt, "8"),
3641 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3642 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3643 OpcodeStr, !strconcat(Dt, "16"),
3644 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3645 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3646 OpcodeStr, !strconcat(Dt, "32"),
3647 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3651 // Neon Multiply-Op vector operations,
3652 // element sizes of 8, 16 and 32 bits:
3653 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3654 InstrItinClass itinD16, InstrItinClass itinD32,
3655 InstrItinClass itinQ16, InstrItinClass itinQ32,
3656 string OpcodeStr, string Dt, SDNode OpNode> {
3657 // 64-bit vector types.
3658 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3659 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3660 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3661 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3662 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3663 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3665 // 128-bit vector types.
3666 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3667 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3668 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3669 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3670 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3671 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3674 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3675 InstrItinClass itinD16, InstrItinClass itinD32,
3676 InstrItinClass itinQ16, InstrItinClass itinQ32,
3677 string OpcodeStr, string Dt, SDNode ShOp> {
3678 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3679 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3680 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3681 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3682 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3683 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3685 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3686 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3690 // Neon Intrinsic-Op vector operations,
3691 // element sizes of 8, 16 and 32 bits:
3692 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3693 InstrItinClass itinD, InstrItinClass itinQ,
3694 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3696 // 64-bit vector types.
3697 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3698 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3699 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3700 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3701 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3702 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3704 // 128-bit vector types.
3705 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3706 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3707 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3708 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3709 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3710 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3713 // Neon 3-argument intrinsics,
3714 // element sizes of 8, 16 and 32 bits:
3715 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3716 InstrItinClass itinD, InstrItinClass itinQ,
3717 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3718 // 64-bit vector types.
3719 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3720 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3721 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3722 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3723 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3724 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3726 // 128-bit vector types.
3727 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3728 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3729 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3730 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3731 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3732 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3736 // Neon Long Multiply-Op vector operations,
3737 // element sizes of 8, 16 and 32 bits:
3738 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3739 InstrItinClass itin16, InstrItinClass itin32,
3740 string OpcodeStr, string Dt, SDNode MulOp,
3742 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3743 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3744 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3745 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3746 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3747 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3750 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3751 string Dt, SDNode MulOp, SDNode OpNode> {
3752 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3753 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3754 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3755 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3759 // Neon Long 3-argument intrinsics.
3761 // First with only element sizes of 16 and 32 bits:
3762 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3763 InstrItinClass itin16, InstrItinClass itin32,
3764 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3765 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3766 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3767 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3768 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3771 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3772 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3773 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3774 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3775 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3776 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3779 // ....then also with element size of 8 bits:
3780 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3781 InstrItinClass itin16, InstrItinClass itin32,
3782 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3783 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3784 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3785 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3788 // ....with explicit extend (VABAL).
3789 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3790 InstrItinClass itin, string OpcodeStr, string Dt,
3791 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3792 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3793 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3794 IntOp, ExtOp, OpNode>;
3795 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3796 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3797 IntOp, ExtOp, OpNode>;
3798 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3799 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3800 IntOp, ExtOp, OpNode>;
3804 // Neon Pairwise long 2-register intrinsics,
3805 // element sizes of 8, 16 and 32 bits:
3806 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3807 bits<5> op11_7, bit op4,
3808 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3809 // 64-bit vector types.
3810 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3811 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3812 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3813 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3814 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3815 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3817 // 128-bit vector types.
3818 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3819 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3820 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3821 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3822 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3823 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3827 // Neon Pairwise long 2-register accumulate intrinsics,
3828 // element sizes of 8, 16 and 32 bits:
3829 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3830 bits<5> op11_7, bit op4,
3831 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3832 // 64-bit vector types.
3833 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3834 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3835 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3836 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3837 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3838 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3840 // 128-bit vector types.
3841 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3842 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3843 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3844 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3845 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3846 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3850 // Neon 2-register vector shift by immediate,
3851 // with f of either N2RegVShLFrm or N2RegVShRFrm
3852 // element sizes of 8, 16, 32 and 64 bits:
3853 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3854 InstrItinClass itin, string OpcodeStr, string Dt,
3856 // 64-bit vector types.
3857 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3858 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3859 let Inst{21-19} = 0b001; // imm6 = 001xxx
3861 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3862 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3863 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3865 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3866 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3867 let Inst{21} = 0b1; // imm6 = 1xxxxx
3869 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3870 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3873 // 128-bit vector types.
3874 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3875 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3876 let Inst{21-19} = 0b001; // imm6 = 001xxx
3878 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3879 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3880 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3882 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3883 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3884 let Inst{21} = 0b1; // imm6 = 1xxxxx
3886 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3887 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3890 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3891 InstrItinClass itin, string OpcodeStr, string Dt,
3892 string baseOpc, SDNode OpNode> {
3893 // 64-bit vector types.
3894 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3895 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3896 let Inst{21-19} = 0b001; // imm6 = 001xxx
3898 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3899 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3900 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3902 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3903 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3904 let Inst{21} = 0b1; // imm6 = 1xxxxx
3906 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3907 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3910 // 128-bit vector types.
3911 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3912 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3913 let Inst{21-19} = 0b001; // imm6 = 001xxx
3915 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3916 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3917 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3919 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3920 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3921 let Inst{21} = 0b1; // imm6 = 1xxxxx
3923 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3924 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3928 // Neon Shift-Accumulate vector operations,
3929 // element sizes of 8, 16, 32 and 64 bits:
3930 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3931 string OpcodeStr, string Dt, SDNode ShOp> {
3932 // 64-bit vector types.
3933 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3934 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3935 let Inst{21-19} = 0b001; // imm6 = 001xxx
3937 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3938 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3939 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3941 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3942 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3943 let Inst{21} = 0b1; // imm6 = 1xxxxx
3945 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3946 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3949 // 128-bit vector types.
3950 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3951 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3952 let Inst{21-19} = 0b001; // imm6 = 001xxx
3954 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3955 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3956 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3958 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3959 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3960 let Inst{21} = 0b1; // imm6 = 1xxxxx
3962 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3963 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3967 // Neon Shift-Insert vector operations,
3968 // with f of either N2RegVShLFrm or N2RegVShRFrm
3969 // element sizes of 8, 16, 32 and 64 bits:
3970 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3972 // 64-bit vector types.
3973 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3974 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3975 let Inst{21-19} = 0b001; // imm6 = 001xxx
3977 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3978 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3979 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3981 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3982 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3983 let Inst{21} = 0b1; // imm6 = 1xxxxx
3985 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3986 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3989 // 128-bit vector types.
3990 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3991 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3992 let Inst{21-19} = 0b001; // imm6 = 001xxx
3994 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3995 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3996 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3998 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3999 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
4000 let Inst{21} = 0b1; // imm6 = 1xxxxx
4002 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
4003 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
4006 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
4008 // 64-bit vector types.
4009 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4010 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
4011 let Inst{21-19} = 0b001; // imm6 = 001xxx
4013 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4014 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
4015 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4017 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4018 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
4019 let Inst{21} = 0b1; // imm6 = 1xxxxx
4021 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4022 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
4025 // 128-bit vector types.
4026 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4027 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
4028 let Inst{21-19} = 0b001; // imm6 = 001xxx
4030 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4031 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
4032 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4034 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4035 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
4036 let Inst{21} = 0b1; // imm6 = 1xxxxx
4038 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4039 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
4043 // Neon Shift Long operations,
4044 // element sizes of 8, 16, 32 bits:
4045 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4046 bit op4, string OpcodeStr, string Dt,
4047 SDPatternOperator OpNode> {
4048 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4049 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
4050 let Inst{21-19} = 0b001; // imm6 = 001xxx
4052 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4053 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
4054 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4056 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4057 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
4058 let Inst{21} = 0b1; // imm6 = 1xxxxx
4062 // Neon Shift Narrow operations,
4063 // element sizes of 16, 32, 64 bits:
4064 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4065 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
4066 SDPatternOperator OpNode> {
4067 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4068 OpcodeStr, !strconcat(Dt, "16"),
4069 v8i8, v8i16, shr_imm8, OpNode> {
4070 let Inst{21-19} = 0b001; // imm6 = 001xxx
4072 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4073 OpcodeStr, !strconcat(Dt, "32"),
4074 v4i16, v4i32, shr_imm16, OpNode> {
4075 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4077 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4078 OpcodeStr, !strconcat(Dt, "64"),
4079 v2i32, v2i64, shr_imm32, OpNode> {
4080 let Inst{21} = 0b1; // imm6 = 1xxxxx
4084 //===----------------------------------------------------------------------===//
4085 // Instruction Definitions.
4086 //===----------------------------------------------------------------------===//
4088 // Vector Add Operations.
4090 // VADD : Vector Add (integer and floating-point)
4091 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
4093 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
4094 v2f32, v2f32, fadd, 1>;
4095 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
4096 v4f32, v4f32, fadd, 1>;
4097 // VADDL : Vector Add Long (Q = D + D)
4098 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4099 "vaddl", "s", add, sext, 1>;
4100 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4101 "vaddl", "u", add, zext, 1>;
4102 // VADDW : Vector Add Wide (Q = Q + D)
4103 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4104 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4105 // VHADD : Vector Halving Add
4106 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4107 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4108 "vhadd", "s", int_arm_neon_vhadds, 1>;
4109 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4110 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4111 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4112 // VRHADD : Vector Rounding Halving Add
4113 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4114 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4115 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4116 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4117 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4118 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4119 // VQADD : Vector Saturating Add
4120 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4121 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4122 "vqadd", "s", int_arm_neon_vqadds, 1>;
4123 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4124 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4125 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4126 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4127 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4128 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4129 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4130 int_arm_neon_vraddhn, 1>;
4132 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4133 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4134 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4135 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4136 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4137 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4139 // Vector Multiply Operations.
4141 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4142 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4143 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4144 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4145 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4146 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4147 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4148 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4149 v2f32, v2f32, fmul, 1>;
4150 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4151 v4f32, v4f32, fmul, 1>;
4152 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4153 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4154 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4157 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4158 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4159 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4160 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4161 (DSubReg_i16_reg imm:$lane))),
4162 (SubReg_i16_lane imm:$lane)))>;
4163 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4164 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4165 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4166 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4167 (DSubReg_i32_reg imm:$lane))),
4168 (SubReg_i32_lane imm:$lane)))>;
4169 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4170 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4171 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4172 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4173 (DSubReg_i32_reg imm:$lane))),
4174 (SubReg_i32_lane imm:$lane)))>;
4177 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4179 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4181 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4183 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4187 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4188 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4189 IIC_VMULi16Q, IIC_VMULi32Q,
4190 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4191 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4192 IIC_VMULi16Q, IIC_VMULi32Q,
4193 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4194 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4195 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4197 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4198 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4199 (DSubReg_i16_reg imm:$lane))),
4200 (SubReg_i16_lane imm:$lane)))>;
4201 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4202 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4204 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4205 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4206 (DSubReg_i32_reg imm:$lane))),
4207 (SubReg_i32_lane imm:$lane)))>;
4209 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4210 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4211 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4212 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4213 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4214 IIC_VMULi16Q, IIC_VMULi32Q,
4215 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4216 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4217 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4219 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4220 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4221 (DSubReg_i16_reg imm:$lane))),
4222 (SubReg_i16_lane imm:$lane)))>;
4223 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4224 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4226 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4227 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4228 (DSubReg_i32_reg imm:$lane))),
4229 (SubReg_i32_lane imm:$lane)))>;
4231 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4232 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4233 DecoderNamespace = "NEONData" in {
4234 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4235 "vmull", "s", NEONvmulls, 1>;
4236 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4237 "vmull", "u", NEONvmullu, 1>;
4238 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4239 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4240 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4241 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4242 Requires<[HasV8, HasCrypto]>;
4244 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4245 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4247 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4248 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4249 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4250 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4251 "vqdmull", "s", int_arm_neon_vqdmull>;
4253 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4255 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4256 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4257 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4258 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4259 v2f32, fmul_su, fadd_mlx>,
4260 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4261 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4262 v4f32, fmul_su, fadd_mlx>,
4263 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4264 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4265 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4266 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4267 v2f32, fmul_su, fadd_mlx>,
4268 Requires<[HasNEON, UseFPVMLx]>;
4269 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4270 v4f32, v2f32, fmul_su, fadd_mlx>,
4271 Requires<[HasNEON, UseFPVMLx]>;
4273 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4274 (mul (v8i16 QPR:$src2),
4275 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4276 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4277 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4278 (DSubReg_i16_reg imm:$lane))),
4279 (SubReg_i16_lane imm:$lane)))>;
4281 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4282 (mul (v4i32 QPR:$src2),
4283 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4284 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4285 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4286 (DSubReg_i32_reg imm:$lane))),
4287 (SubReg_i32_lane imm:$lane)))>;
4289 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4290 (fmul_su (v4f32 QPR:$src2),
4291 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4292 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4294 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4295 (DSubReg_i32_reg imm:$lane))),
4296 (SubReg_i32_lane imm:$lane)))>,
4297 Requires<[HasNEON, UseFPVMLx]>;
4299 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4300 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4301 "vmlal", "s", NEONvmulls, add>;
4302 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4303 "vmlal", "u", NEONvmullu, add>;
4305 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4306 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4308 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4309 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4310 "vqdmlal", "s", null_frag>;
4311 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4313 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4314 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4315 (v4i16 DPR:$Vm))))),
4316 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4317 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4318 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4319 (v2i32 DPR:$Vm))))),
4320 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4321 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4322 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4323 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4325 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4326 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4327 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4328 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4330 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4332 // VMLS : Vector Multiply Subtract (integer and floating-point)
4333 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4334 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4335 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4336 v2f32, fmul_su, fsub_mlx>,
4337 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4338 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4339 v4f32, fmul_su, fsub_mlx>,
4340 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4341 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4342 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4343 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4344 v2f32, fmul_su, fsub_mlx>,
4345 Requires<[HasNEON, UseFPVMLx]>;
4346 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4347 v4f32, v2f32, fmul_su, fsub_mlx>,
4348 Requires<[HasNEON, UseFPVMLx]>;
4350 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4351 (mul (v8i16 QPR:$src2),
4352 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4353 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4354 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4355 (DSubReg_i16_reg imm:$lane))),
4356 (SubReg_i16_lane imm:$lane)))>;
4358 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4359 (mul (v4i32 QPR:$src2),
4360 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4361 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4362 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4363 (DSubReg_i32_reg imm:$lane))),
4364 (SubReg_i32_lane imm:$lane)))>;
4366 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4367 (fmul_su (v4f32 QPR:$src2),
4368 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4369 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4370 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4371 (DSubReg_i32_reg imm:$lane))),
4372 (SubReg_i32_lane imm:$lane)))>,
4373 Requires<[HasNEON, UseFPVMLx]>;
4375 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4376 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4377 "vmlsl", "s", NEONvmulls, sub>;
4378 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4379 "vmlsl", "u", NEONvmullu, sub>;
4381 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4382 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4384 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4385 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4386 "vqdmlsl", "s", null_frag>;
4387 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b0111, "vqdmlsl", "s", null_frag>;
4389 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4390 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4391 (v4i16 DPR:$Vm))))),
4392 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4393 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4394 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4395 (v2i32 DPR:$Vm))))),
4396 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4397 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4398 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4399 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4401 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4402 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4403 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4404 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4406 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4408 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4409 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4410 v2f32, fmul_su, fadd_mlx>,
4411 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4413 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4414 v4f32, fmul_su, fadd_mlx>,
4415 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4417 // Fused Vector Multiply Subtract (floating-point)
4418 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4419 v2f32, fmul_su, fsub_mlx>,
4420 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4421 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4422 v4f32, fmul_su, fsub_mlx>,
4423 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4425 // Match @llvm.fma.* intrinsics
4426 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4427 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4428 Requires<[HasVFP4]>;
4429 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4430 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4431 Requires<[HasVFP4]>;
4432 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4433 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4434 Requires<[HasVFP4]>;
4435 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4436 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4437 Requires<[HasVFP4]>;
4439 // Vector Subtract Operations.
4441 // VSUB : Vector Subtract (integer and floating-point)
4442 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4443 "vsub", "i", sub, 0>;
4444 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4445 v2f32, v2f32, fsub, 0>;
4446 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4447 v4f32, v4f32, fsub, 0>;
4448 // VSUBL : Vector Subtract Long (Q = D - D)
4449 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4450 "vsubl", "s", sub, sext, 0>;
4451 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4452 "vsubl", "u", sub, zext, 0>;
4453 // VSUBW : Vector Subtract Wide (Q = Q - D)
4454 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4455 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4456 // VHSUB : Vector Halving Subtract
4457 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4458 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4459 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4460 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4461 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4462 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4463 // VQSUB : Vector Saturing Subtract
4464 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4465 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4466 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4467 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4468 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4469 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4470 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4471 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4472 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4473 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4474 int_arm_neon_vrsubhn, 0>;
4476 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4477 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4478 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4479 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4480 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4481 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4483 // Vector Comparisons.
4485 // VCEQ : Vector Compare Equal
4486 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4487 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4488 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4490 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4493 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4494 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4495 "$Vd, $Vm, #0", NEONvceqz>;
4497 // VCGE : Vector Compare Greater Than or Equal
4498 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4499 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4500 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4501 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4502 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4504 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4507 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4508 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4509 "$Vd, $Vm, #0", NEONvcgez>;
4510 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4511 "$Vd, $Vm, #0", NEONvclez>;
4514 // VCGT : Vector Compare Greater Than
4515 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4516 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4517 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4518 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4519 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4521 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4524 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4525 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4526 "$Vd, $Vm, #0", NEONvcgtz>;
4527 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4528 "$Vd, $Vm, #0", NEONvcltz>;
4531 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4532 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4533 "f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
4534 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4535 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
4536 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4537 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4538 "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
4539 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4540 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
4541 // VTST : Vector Test Bits
4542 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4543 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4545 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4546 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4547 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4548 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4549 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4550 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4551 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4552 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4554 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4555 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4556 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4557 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4558 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4559 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4560 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4561 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4563 // Vector Bitwise Operations.
4565 def vnotd : PatFrag<(ops node:$in),
4566 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4567 def vnotq : PatFrag<(ops node:$in),
4568 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4571 // VAND : Vector Bitwise AND
4572 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4573 v2i32, v2i32, and, 1>;
4574 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4575 v4i32, v4i32, and, 1>;
4577 // VEOR : Vector Bitwise Exclusive OR
4578 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4579 v2i32, v2i32, xor, 1>;
4580 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4581 v4i32, v4i32, xor, 1>;
4583 // VORR : Vector Bitwise OR
4584 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4585 v2i32, v2i32, or, 1>;
4586 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4587 v4i32, v4i32, or, 1>;
4589 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4590 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4592 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4594 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4595 let Inst{9} = SIMM{9};
4598 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4599 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4601 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4603 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4604 let Inst{10-9} = SIMM{10-9};
4607 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4608 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4610 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4612 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4613 let Inst{9} = SIMM{9};
4616 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4617 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4619 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4621 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4622 let Inst{10-9} = SIMM{10-9};
4626 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4627 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4628 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4629 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4630 "vbic", "$Vd, $Vn, $Vm", "",
4631 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4632 (vnotd DPR:$Vm))))]>;
4633 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4634 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4635 "vbic", "$Vd, $Vn, $Vm", "",
4636 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4637 (vnotq QPR:$Vm))))]>;
4640 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4641 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4643 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4645 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4646 let Inst{9} = SIMM{9};
4649 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4650 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4652 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4654 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4655 let Inst{10-9} = SIMM{10-9};
4658 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4659 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4661 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4663 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4664 let Inst{9} = SIMM{9};
4667 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4668 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4670 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4672 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4673 let Inst{10-9} = SIMM{10-9};
4676 // VORN : Vector Bitwise OR NOT
4677 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4678 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4679 "vorn", "$Vd, $Vn, $Vm", "",
4680 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4681 (vnotd DPR:$Vm))))]>;
4682 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4683 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4684 "vorn", "$Vd, $Vn, $Vm", "",
4685 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4686 (vnotq QPR:$Vm))))]>;
4688 // VMVN : Vector Bitwise NOT (Immediate)
4690 let isReMaterializable = 1 in {
4692 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4693 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4694 "vmvn", "i16", "$Vd, $SIMM", "",
4695 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4696 let Inst{9} = SIMM{9};
4699 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4700 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4701 "vmvn", "i16", "$Vd, $SIMM", "",
4702 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4703 let Inst{9} = SIMM{9};
4706 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4707 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4708 "vmvn", "i32", "$Vd, $SIMM", "",
4709 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4710 let Inst{11-8} = SIMM{11-8};
4713 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4714 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4715 "vmvn", "i32", "$Vd, $SIMM", "",
4716 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4717 let Inst{11-8} = SIMM{11-8};
4721 // VMVN : Vector Bitwise NOT
4722 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4723 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4724 "vmvn", "$Vd, $Vm", "",
4725 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4726 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4727 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4728 "vmvn", "$Vd, $Vm", "",
4729 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4730 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4731 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4733 // VBSL : Vector Bitwise Select
4734 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4735 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4736 N3RegFrm, IIC_VCNTiD,
4737 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4739 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4740 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4741 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4742 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4743 Requires<[HasNEON]>;
4744 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4745 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4746 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4747 Requires<[HasNEON]>;
4748 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4749 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4750 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4751 Requires<[HasNEON]>;
4752 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4753 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4754 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4755 Requires<[HasNEON]>;
4756 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4757 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4758 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4759 Requires<[HasNEON]>;
4761 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4762 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4763 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4764 Requires<[HasNEON]>;
4766 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4767 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4768 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4769 Requires<[HasNEON]>;
4771 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4772 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4773 N3RegFrm, IIC_VCNTiQ,
4774 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4776 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4778 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4779 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4780 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4781 Requires<[HasNEON]>;
4782 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4783 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4784 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4785 Requires<[HasNEON]>;
4786 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4787 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4788 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4789 Requires<[HasNEON]>;
4790 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4791 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4792 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4793 Requires<[HasNEON]>;
4794 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4795 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4796 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4797 Requires<[HasNEON]>;
4799 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4800 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4801 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4802 Requires<[HasNEON]>;
4803 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4804 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4805 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4806 Requires<[HasNEON]>;
4808 // VBIF : Vector Bitwise Insert if False
4809 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4810 // FIXME: This instruction's encoding MAY NOT BE correct.
4811 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4812 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4813 N3RegFrm, IIC_VBINiD,
4814 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4816 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4817 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4818 N3RegFrm, IIC_VBINiQ,
4819 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4822 // VBIT : Vector Bitwise Insert if True
4823 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4824 // FIXME: This instruction's encoding MAY NOT BE correct.
4825 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4826 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4827 N3RegFrm, IIC_VBINiD,
4828 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4830 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4831 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4832 N3RegFrm, IIC_VBINiQ,
4833 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4836 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4837 // for equivalent operations with different register constraints; it just
4840 // Vector Absolute Differences.
4842 // VABD : Vector Absolute Difference
4843 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4844 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4845 "vabd", "s", int_arm_neon_vabds, 1>;
4846 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4847 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4848 "vabd", "u", int_arm_neon_vabdu, 1>;
4849 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4850 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4851 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4852 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4854 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4855 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4856 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4857 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4858 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4860 // VABA : Vector Absolute Difference and Accumulate
4861 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4862 "vaba", "s", int_arm_neon_vabds, add>;
4863 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4864 "vaba", "u", int_arm_neon_vabdu, add>;
4866 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4867 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4868 "vabal", "s", int_arm_neon_vabds, zext, add>;
4869 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4870 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4872 // Vector Maximum and Minimum.
4874 // VMAX : Vector Maximum
4875 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4876 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4877 "vmax", "s", int_arm_neon_vmaxs, 1>;
4878 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4879 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4880 "vmax", "u", int_arm_neon_vmaxu, 1>;
4881 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4883 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4884 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4886 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4889 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4890 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4891 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4892 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4893 Requires<[HasV8, HasNEON]>;
4894 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4895 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4896 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4897 Requires<[HasV8, HasNEON]>;
4900 // VMIN : Vector Minimum
4901 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4902 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4903 "vmin", "s", int_arm_neon_vmins, 1>;
4904 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4905 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4906 "vmin", "u", int_arm_neon_vminu, 1>;
4907 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4909 v2f32, v2f32, int_arm_neon_vmins, 1>;
4910 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4912 v4f32, v4f32, int_arm_neon_vmins, 1>;
4915 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4916 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4917 N3RegFrm, NoItinerary, "vminnm", "f32",
4918 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4919 Requires<[HasV8, HasNEON]>;
4920 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4921 N3RegFrm, NoItinerary, "vminnm", "f32",
4922 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4923 Requires<[HasV8, HasNEON]>;
4926 // Vector Pairwise Operations.
4928 // VPADD : Vector Pairwise Add
4929 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4931 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4932 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4934 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4935 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4937 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4938 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4939 IIC_VPBIND, "vpadd", "f32",
4940 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4942 // VPADDL : Vector Pairwise Add Long
4943 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4944 int_arm_neon_vpaddls>;
4945 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4946 int_arm_neon_vpaddlu>;
4948 // VPADAL : Vector Pairwise Add and Accumulate Long
4949 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4950 int_arm_neon_vpadals>;
4951 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4952 int_arm_neon_vpadalu>;
4954 // VPMAX : Vector Pairwise Maximum
4955 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4956 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4957 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4958 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4959 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4960 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4961 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4962 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4963 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4964 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4965 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4966 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4967 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4968 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4970 // VPMIN : Vector Pairwise Minimum
4971 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4972 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4973 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4974 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4975 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4976 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4977 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4978 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4979 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4980 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4981 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4982 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4983 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4984 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4986 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4988 // VRECPE : Vector Reciprocal Estimate
4989 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4990 IIC_VUNAD, "vrecpe", "u32",
4991 v2i32, v2i32, int_arm_neon_vrecpe>;
4992 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4993 IIC_VUNAQ, "vrecpe", "u32",
4994 v4i32, v4i32, int_arm_neon_vrecpe>;
4995 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4996 IIC_VUNAD, "vrecpe", "f32",
4997 v2f32, v2f32, int_arm_neon_vrecpe>;
4998 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4999 IIC_VUNAQ, "vrecpe", "f32",
5000 v4f32, v4f32, int_arm_neon_vrecpe>;
5002 // VRECPS : Vector Reciprocal Step
5003 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5004 IIC_VRECSD, "vrecps", "f32",
5005 v2f32, v2f32, int_arm_neon_vrecps, 1>;
5006 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5007 IIC_VRECSQ, "vrecps", "f32",
5008 v4f32, v4f32, int_arm_neon_vrecps, 1>;
5010 // VRSQRTE : Vector Reciprocal Square Root Estimate
5011 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5012 IIC_VUNAD, "vrsqrte", "u32",
5013 v2i32, v2i32, int_arm_neon_vrsqrte>;
5014 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5015 IIC_VUNAQ, "vrsqrte", "u32",
5016 v4i32, v4i32, int_arm_neon_vrsqrte>;
5017 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5018 IIC_VUNAD, "vrsqrte", "f32",
5019 v2f32, v2f32, int_arm_neon_vrsqrte>;
5020 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5021 IIC_VUNAQ, "vrsqrte", "f32",
5022 v4f32, v4f32, int_arm_neon_vrsqrte>;
5024 // VRSQRTS : Vector Reciprocal Square Root Step
5025 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5026 IIC_VRECSD, "vrsqrts", "f32",
5027 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
5028 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5029 IIC_VRECSQ, "vrsqrts", "f32",
5030 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
5034 // VSHL : Vector Shift
5035 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
5036 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5037 "vshl", "s", int_arm_neon_vshifts>;
5038 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
5039 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5040 "vshl", "u", int_arm_neon_vshiftu>;
5042 // VSHL : Vector Shift Left (Immediate)
5043 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
5045 // VSHR : Vector Shift Right (Immediate)
5046 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
5048 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
5051 // VSHLL : Vector Shift Left Long
5052 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5053 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
5054 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5055 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
5057 // VSHLL : Vector Shift Left Long (with maximum shift count)
5058 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
5059 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
5060 ValueType OpTy, Operand ImmTy>
5061 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
5062 ResTy, OpTy, ImmTy, null_frag> {
5063 let Inst{21-16} = op21_16;
5064 let DecoderMethod = "DecodeVSHLMaxInstruction";
5066 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
5068 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
5069 v4i32, v4i16, imm16>;
5070 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
5071 v2i64, v2i32, imm32>;
5073 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5074 (VSHLLi8 DPR:$Rn, 8)>;
5075 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5076 (VSHLLi16 DPR:$Rn, 16)>;
5077 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5078 (VSHLLi32 DPR:$Rn, 32)>;
5079 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5080 (VSHLLi8 DPR:$Rn, 8)>;
5081 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5082 (VSHLLi16 DPR:$Rn, 16)>;
5083 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5084 (VSHLLi32 DPR:$Rn, 32)>;
5086 // VSHRN : Vector Shift Right and Narrow
5087 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
5088 PatFrag<(ops node:$Rn, node:$amt),
5089 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
5091 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5092 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5093 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5094 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5095 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5096 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5098 // VRSHL : Vector Rounding Shift
5099 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
5100 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5101 "vrshl", "s", int_arm_neon_vrshifts>;
5102 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
5103 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5104 "vrshl", "u", int_arm_neon_vrshiftu>;
5105 // VRSHR : Vector Rounding Shift Right
5106 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
5108 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
5111 // VRSHRN : Vector Rounding Shift Right and Narrow
5112 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
5115 // VQSHL : Vector Saturating Shift
5116 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
5117 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5118 "vqshl", "s", int_arm_neon_vqshifts>;
5119 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
5120 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5121 "vqshl", "u", int_arm_neon_vqshiftu>;
5122 // VQSHL : Vector Saturating Shift Left (Immediate)
5123 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5124 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5126 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5127 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5129 // VQSHRN : Vector Saturating Shift Right and Narrow
5130 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5132 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5135 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5136 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5139 // VQRSHL : Vector Saturating Rounding Shift
5140 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5141 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5142 "vqrshl", "s", int_arm_neon_vqrshifts>;
5143 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5144 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5145 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5147 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5148 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5150 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5153 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5154 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5157 // VSRA : Vector Shift Right and Accumulate
5158 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5159 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5160 // VRSRA : Vector Rounding Shift Right and Accumulate
5161 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5162 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5164 // VSLI : Vector Shift Left and Insert
5165 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5167 // VSRI : Vector Shift Right and Insert
5168 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5170 // Vector Absolute and Saturating Absolute.
5172 // VABS : Vector Absolute Value
5173 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5174 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5176 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5178 v2f32, v2f32, fabs>;
5179 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5181 v4f32, v4f32, fabs>;
5183 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5184 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5185 (NEONvshrs DPR:$src, (i32 7))))))),
5186 (VABSv8i8 DPR:$src)>;
5187 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5188 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5189 (NEONvshrs DPR:$src, (i32 15))))))),
5190 (VABSv4i16 DPR:$src)>;
5191 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5192 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5193 (VABSv2i32 DPR:$src)>;
5194 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5195 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5196 (NEONvshrs QPR:$src, (i32 7))))))),
5197 (VABSv16i8 QPR:$src)>;
5198 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5199 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5200 (NEONvshrs QPR:$src, (i32 15))))))),
5201 (VABSv8i16 QPR:$src)>;
5202 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5203 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5204 (VABSv4i32 QPR:$src)>;
5206 // VQABS : Vector Saturating Absolute Value
5207 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5208 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5209 int_arm_neon_vqabs>;
5213 def vnegd : PatFrag<(ops node:$in),
5214 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5215 def vnegq : PatFrag<(ops node:$in),
5216 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5218 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5219 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5220 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5221 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5222 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5223 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5224 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5225 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5227 // VNEG : Vector Negate (integer)
5228 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5229 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5230 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5231 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5232 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5233 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5235 // VNEG : Vector Negate (floating-point)
5236 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5237 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5238 "vneg", "f32", "$Vd, $Vm", "",
5239 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5240 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5241 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5242 "vneg", "f32", "$Vd, $Vm", "",
5243 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5245 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5246 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5247 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5248 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5249 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5250 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5252 // VQNEG : Vector Saturating Negate
5253 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5254 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5255 int_arm_neon_vqneg>;
5257 // Vector Bit Counting Operations.
5259 // VCLS : Vector Count Leading Sign Bits
5260 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5261 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5263 // VCLZ : Vector Count Leading Zeros
5264 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5265 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5267 // VCNT : Vector Count One Bits
5268 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5269 IIC_VCNTiD, "vcnt", "8",
5271 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5272 IIC_VCNTiQ, "vcnt", "8",
5273 v16i8, v16i8, ctpop>;
5276 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5277 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5278 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5280 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5281 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5282 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5285 // Vector Move Operations.
5287 // VMOV : Vector Move (Register)
5288 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5289 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5290 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5291 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5293 // VMOV : Vector Move (Immediate)
5295 let isReMaterializable = 1 in {
5296 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5297 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5298 "vmov", "i8", "$Vd, $SIMM", "",
5299 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5300 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5301 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5302 "vmov", "i8", "$Vd, $SIMM", "",
5303 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5305 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5306 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5307 "vmov", "i16", "$Vd, $SIMM", "",
5308 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5309 let Inst{9} = SIMM{9};
5312 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5313 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5314 "vmov", "i16", "$Vd, $SIMM", "",
5315 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5316 let Inst{9} = SIMM{9};
5319 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5320 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5321 "vmov", "i32", "$Vd, $SIMM", "",
5322 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5323 let Inst{11-8} = SIMM{11-8};
5326 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5327 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5328 "vmov", "i32", "$Vd, $SIMM", "",
5329 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5330 let Inst{11-8} = SIMM{11-8};
5333 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5334 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5335 "vmov", "i64", "$Vd, $SIMM", "",
5336 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5337 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5338 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5339 "vmov", "i64", "$Vd, $SIMM", "",
5340 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5342 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5343 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5344 "vmov", "f32", "$Vd, $SIMM", "",
5345 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5346 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5347 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5348 "vmov", "f32", "$Vd, $SIMM", "",
5349 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5350 } // isReMaterializable
5352 // Add support for bytes replication feature, so it could be GAS compatible.
5353 // E.g. instructions below:
5354 // "vmov.i32 d0, 0xffffffff"
5355 // "vmov.i32 d0, 0xabababab"
5356 // "vmov.i16 d0, 0xabab"
5357 // are incorrect, but we could deal with such cases.
5358 // For last two instructions, for example, it should emit:
5359 // "vmov.i8 d0, 0xab"
5360 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5361 (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5362 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5363 (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5364 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5365 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5366 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5367 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5369 // Also add same support for VMVN instructions. So instruction:
5370 // "vmvn.i32 d0, 0xabababab"
5372 // "vmov.i8 d0, 0x54"
5373 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5374 (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5375 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5376 (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5377 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5378 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5379 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5380 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5382 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
5383 // require zero cycles to execute so they should be used wherever possible for
5384 // setting a register to zero.
5386 // Even without these pseudo-insts we would probably end up with the correct
5387 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
5388 // since they are sometimes rather expensive (in general).
5390 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
5391 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5392 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5393 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5395 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5396 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5397 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5401 // VMOV : Vector Get Lane (move scalar to ARM core register)
5403 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5404 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5405 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5406 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5408 let Inst{21} = lane{2};
5409 let Inst{6-5} = lane{1-0};
5411 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5412 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5413 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5414 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5416 let Inst{21} = lane{1};
5417 let Inst{6} = lane{0};
5419 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5420 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5421 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5422 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5424 let Inst{21} = lane{2};
5425 let Inst{6-5} = lane{1-0};
5427 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5428 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5429 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5430 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5432 let Inst{21} = lane{1};
5433 let Inst{6} = lane{0};
5435 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5436 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5437 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5438 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5440 Requires<[HasVFP2, HasFastVGETLNi32]> {
5441 let Inst{21} = lane{0};
5443 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5444 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5445 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5446 (DSubReg_i8_reg imm:$lane))),
5447 (SubReg_i8_lane imm:$lane))>;
5448 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5449 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5450 (DSubReg_i16_reg imm:$lane))),
5451 (SubReg_i16_lane imm:$lane))>;
5452 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5453 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5454 (DSubReg_i8_reg imm:$lane))),
5455 (SubReg_i8_lane imm:$lane))>;
5456 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5457 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5458 (DSubReg_i16_reg imm:$lane))),
5459 (SubReg_i16_lane imm:$lane))>;
5460 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5461 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5462 (DSubReg_i32_reg imm:$lane))),
5463 (SubReg_i32_lane imm:$lane))>,
5464 Requires<[HasNEON, HasFastVGETLNi32]>;
5465 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5467 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5468 Requires<[HasNEON, HasSlowVGETLNi32]>;
5469 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5471 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5472 Requires<[HasNEON, HasSlowVGETLNi32]>;
5473 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5474 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5475 (SSubReg_f32_reg imm:$src2))>;
5476 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5477 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5478 (SSubReg_f32_reg imm:$src2))>;
5479 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5480 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5481 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5482 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5485 // VMOV : Vector Set Lane (move ARM core register to scalar)
5487 let Constraints = "$src1 = $V" in {
5488 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5489 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5490 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5491 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5492 GPR:$R, imm:$lane))]> {
5493 let Inst{21} = lane{2};
5494 let Inst{6-5} = lane{1-0};
5496 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5497 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5498 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5499 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5500 GPR:$R, imm:$lane))]> {
5501 let Inst{21} = lane{1};
5502 let Inst{6} = lane{0};
5504 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5505 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5506 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5507 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5508 GPR:$R, imm:$lane))]>,
5509 Requires<[HasVFP2]> {
5510 let Inst{21} = lane{0};
5511 // This instruction is equivalent as
5512 // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm)
5513 let isInsertSubreg = 1;
5516 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5517 (v16i8 (INSERT_SUBREG QPR:$src1,
5518 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5519 (DSubReg_i8_reg imm:$lane))),
5520 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5521 (DSubReg_i8_reg imm:$lane)))>;
5522 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5523 (v8i16 (INSERT_SUBREG QPR:$src1,
5524 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5525 (DSubReg_i16_reg imm:$lane))),
5526 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5527 (DSubReg_i16_reg imm:$lane)))>;
5528 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5529 (v4i32 (INSERT_SUBREG QPR:$src1,
5530 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5531 (DSubReg_i32_reg imm:$lane))),
5532 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5533 (DSubReg_i32_reg imm:$lane)))>;
5535 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5536 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5537 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5538 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5539 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5540 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5542 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5543 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5544 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5545 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5547 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5548 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5549 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5550 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5551 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5552 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5554 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5555 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5556 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5557 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5558 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5559 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5561 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5562 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5563 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5565 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5566 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5567 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5569 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5570 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5571 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5574 // VDUP : Vector Duplicate (from ARM core register to all elements)
5576 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5577 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5578 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5579 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5580 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5581 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5582 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5583 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5585 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5586 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5587 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5588 Requires<[HasNEON, HasFastVDUP32]>;
5589 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5590 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5591 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5593 // NEONvdup patterns for uarchs with fast VDUP.32.
5594 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5595 Requires<[HasNEON,HasFastVDUP32]>;
5596 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5598 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5599 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5600 Requires<[HasNEON,HasSlowVDUP32]>;
5601 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5602 Requires<[HasNEON,HasSlowVDUP32]>;
5604 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5606 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5607 ValueType Ty, Operand IdxTy>
5608 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5609 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5610 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5612 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5613 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5614 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5615 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5616 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5617 VectorIndex32:$lane)))]>;
5619 // Inst{19-16} is partially specified depending on the element size.
5621 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5623 let Inst{19-17} = lane{2-0};
5625 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5627 let Inst{19-18} = lane{1-0};
5629 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5631 let Inst{19} = lane{0};
5633 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5635 let Inst{19-17} = lane{2-0};
5637 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5639 let Inst{19-18} = lane{1-0};
5641 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5643 let Inst{19} = lane{0};
5646 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5647 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5649 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5650 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5652 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5653 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5654 (DSubReg_i8_reg imm:$lane))),
5655 (SubReg_i8_lane imm:$lane)))>;
5656 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5657 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5658 (DSubReg_i16_reg imm:$lane))),
5659 (SubReg_i16_lane imm:$lane)))>;
5660 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5661 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5662 (DSubReg_i32_reg imm:$lane))),
5663 (SubReg_i32_lane imm:$lane)))>;
5664 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5665 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5666 (DSubReg_i32_reg imm:$lane))),
5667 (SubReg_i32_lane imm:$lane)))>;
5669 def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
5670 (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5671 SPR:$src, ssub_0), (i32 0)))>;
5672 def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
5673 (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5674 SPR:$src, ssub_0), (i32 0)))>;
5676 // VMOVN : Vector Narrowing Move
5677 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5678 "vmovn", "i", trunc>;
5679 // VQMOVN : Vector Saturating Narrowing Move
5680 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5681 "vqmovn", "s", int_arm_neon_vqmovns>;
5682 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5683 "vqmovn", "u", int_arm_neon_vqmovnu>;
5684 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5685 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5686 // VMOVL : Vector Lengthening Move
5687 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5688 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5689 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5690 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5691 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5693 // Vector Conversions.
5695 // VCVT : Vector Convert Between Floating-Point and Integers
5696 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5697 v2i32, v2f32, fp_to_sint>;
5698 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5699 v2i32, v2f32, fp_to_uint>;
5700 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5701 v2f32, v2i32, sint_to_fp>;
5702 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5703 v2f32, v2i32, uint_to_fp>;
5705 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5706 v4i32, v4f32, fp_to_sint>;
5707 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5708 v4i32, v4f32, fp_to_uint>;
5709 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5710 v4f32, v4i32, sint_to_fp>;
5711 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5712 v4f32, v4i32, uint_to_fp>;
5715 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5716 SDPatternOperator IntU> {
5717 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5718 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5719 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5720 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5721 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5722 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5723 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5724 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5725 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5729 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5730 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5731 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5732 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5734 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5735 let DecoderMethod = "DecodeVCVTD" in {
5736 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5737 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5738 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5739 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5740 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5741 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5742 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5743 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5746 let DecoderMethod = "DecodeVCVTQ" in {
5747 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5748 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5749 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5750 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5751 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5752 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5753 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5754 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5757 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5758 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5759 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5760 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5761 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5762 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5763 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5764 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5766 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5767 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5768 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5769 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5770 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5771 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5772 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5773 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5776 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5777 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5778 IIC_VUNAQ, "vcvt", "f16.f32",
5779 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5780 Requires<[HasNEON, HasFP16]>;
5781 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5782 IIC_VUNAQ, "vcvt", "f32.f16",
5783 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5784 Requires<[HasNEON, HasFP16]>;
5788 // VREV64 : Vector Reverse elements within 64-bit doublewords
5790 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5791 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5792 (ins DPR:$Vm), IIC_VMOVD,
5793 OpcodeStr, Dt, "$Vd, $Vm", "",
5794 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5795 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5796 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5797 (ins QPR:$Vm), IIC_VMOVQ,
5798 OpcodeStr, Dt, "$Vd, $Vm", "",
5799 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5801 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5802 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5803 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5804 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5806 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5807 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5808 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5809 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5811 // VREV32 : Vector Reverse elements within 32-bit words
5813 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5814 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5815 (ins DPR:$Vm), IIC_VMOVD,
5816 OpcodeStr, Dt, "$Vd, $Vm", "",
5817 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5818 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5819 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5820 (ins QPR:$Vm), IIC_VMOVQ,
5821 OpcodeStr, Dt, "$Vd, $Vm", "",
5822 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5824 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5825 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5827 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5828 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5830 // VREV16 : Vector Reverse elements within 16-bit halfwords
5832 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5833 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5834 (ins DPR:$Vm), IIC_VMOVD,
5835 OpcodeStr, Dt, "$Vd, $Vm", "",
5836 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5837 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5838 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5839 (ins QPR:$Vm), IIC_VMOVQ,
5840 OpcodeStr, Dt, "$Vd, $Vm", "",
5841 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5843 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5844 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5846 // Other Vector Shuffles.
5848 // Aligned extractions: really just dropping registers
5850 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5851 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5852 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5854 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5856 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5858 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5860 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5862 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5865 // VEXT : Vector Extract
5868 // All of these have a two-operand InstAlias.
5869 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5870 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5871 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5872 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5873 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5874 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5875 (Ty DPR:$Vm), imm:$index)))]> {
5878 let Inst{10-8} = index{2-0};
5881 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5882 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5883 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5884 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5885 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5886 (Ty QPR:$Vm), imm:$index)))]> {
5888 let Inst{11-8} = index{3-0};
5892 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5893 let Inst{10-8} = index{2-0};
5895 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5896 let Inst{10-9} = index{1-0};
5899 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5900 let Inst{10} = index{0};
5901 let Inst{9-8} = 0b00;
5903 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5906 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5908 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5909 let Inst{11-8} = index{3-0};
5911 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5912 let Inst{11-9} = index{2-0};
5915 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5916 let Inst{11-10} = index{1-0};
5917 let Inst{9-8} = 0b00;
5919 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5920 let Inst{11} = index{0};
5921 let Inst{10-8} = 0b000;
5923 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5926 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5928 // VTRN : Vector Transpose
5930 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5931 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5932 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5934 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5935 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5936 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5938 // VUZP : Vector Unzip (Deinterleave)
5940 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5941 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5942 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5943 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5944 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5946 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5947 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5948 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5950 // VZIP : Vector Zip (Interleave)
5952 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5953 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5954 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5955 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5956 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5958 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5959 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5960 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5962 // Vector Table Lookup and Table Extension.
5964 // VTBL : Vector Table Lookup
5965 let DecoderMethod = "DecodeTBLInstruction" in {
5967 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5968 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5969 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5970 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5971 let hasExtraSrcRegAllocReq = 1 in {
5973 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5974 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5975 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5977 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5978 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5979 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5981 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5982 (ins VecListFourD:$Vn, DPR:$Vm),
5984 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5985 } // hasExtraSrcRegAllocReq = 1
5988 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5990 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5992 // VTBX : Vector Table Extension
5994 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5995 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5996 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5997 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5998 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5999 let hasExtraSrcRegAllocReq = 1 in {
6001 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
6002 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
6003 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
6005 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
6006 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
6007 NVTBLFrm, IIC_VTBX3,
6008 "vtbx", "8", "$Vd, $Vn, $Vm",
6011 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
6012 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
6013 "vtbx", "8", "$Vd, $Vn, $Vm",
6015 } // hasExtraSrcRegAllocReq = 1
6018 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6019 IIC_VTBX3, "$orig = $dst", []>;
6021 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6022 IIC_VTBX4, "$orig = $dst", []>;
6023 } // DecoderMethod = "DecodeTBLInstruction"
6025 // VRINT : Vector Rounding
6026 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
6027 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
6028 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
6029 !strconcat("vrint", op), "f32",
6030 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
6031 let Inst{9-7} = op9_7;
6033 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
6034 !strconcat("vrint", op), "f32",
6035 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
6036 let Inst{9-7} = op9_7;
6040 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
6041 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
6042 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
6043 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
6046 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
6047 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
6048 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
6049 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
6050 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
6051 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
6053 // Cryptography instructions
6054 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
6055 DecoderNamespace = "v8Crypto", hasSideEffects = 0 in {
6056 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
6057 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6058 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6059 Requires<[HasV8, HasCrypto]>;
6060 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
6061 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6062 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6063 Requires<[HasV8, HasCrypto]>;
6064 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6065 SDPatternOperator Int>
6066 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6067 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6068 Requires<[HasV8, HasCrypto]>;
6069 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6070 SDPatternOperator Int>
6071 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6072 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6073 Requires<[HasV8, HasCrypto]>;
6074 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
6075 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
6076 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
6077 Requires<[HasV8, HasCrypto]>;
6080 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
6081 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
6082 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
6083 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
6085 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
6086 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
6087 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
6088 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
6089 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
6090 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
6091 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
6092 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
6093 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
6094 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
6096 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
6097 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6098 (SHA1H (SUBREG_TO_REG (i64 0),
6099 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6103 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6104 (SHA1C v4i32:$hash_abcd,
6105 (SUBREG_TO_REG (i64 0),
6106 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6110 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6111 (SHA1M v4i32:$hash_abcd,
6112 (SUBREG_TO_REG (i64 0),
6113 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6117 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6118 (SHA1P v4i32:$hash_abcd,
6119 (SUBREG_TO_REG (i64 0),
6120 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6124 //===----------------------------------------------------------------------===//
6125 // NEON instructions for single-precision FP math
6126 //===----------------------------------------------------------------------===//
6128 class N2VSPat<SDNode OpNode, NeonI Inst>
6129 : NEONFPPat<(f32 (OpNode SPR:$a)),
6131 (v2f32 (COPY_TO_REGCLASS (Inst
6133 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6134 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
6136 class N3VSPat<SDNode OpNode, NeonI Inst>
6137 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
6139 (v2f32 (COPY_TO_REGCLASS (Inst
6141 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6144 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6145 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6147 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
6148 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
6150 (v2f32 (COPY_TO_REGCLASS (Inst
6152 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6155 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6158 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6159 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6161 def : N3VSPat<fadd, VADDfd>;
6162 def : N3VSPat<fsub, VSUBfd>;
6163 def : N3VSPat<fmul, VMULfd>;
6164 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
6165 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6166 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
6167 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6168 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
6169 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6170 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
6171 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6172 def : N2VSPat<fabs, VABSfd>;
6173 def : N2VSPat<fneg, VNEGfd>;
6174 def : N3VSPat<NEONfmax, VMAXfd>;
6175 def : N3VSPat<NEONfmin, VMINfd>;
6176 def : N2VSPat<arm_ftosi, VCVTf2sd>;
6177 def : N2VSPat<arm_ftoui, VCVTf2ud>;
6178 def : N2VSPat<arm_sitof, VCVTs2fd>;
6179 def : N2VSPat<arm_uitof, VCVTu2fd>;
6181 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6182 def : Pat<(f32 (bitconvert GPR:$a)),
6183 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6184 Requires<[HasNEON, DontUseVMOVSR]>;
6186 //===----------------------------------------------------------------------===//
6187 // Non-Instruction Patterns
6188 //===----------------------------------------------------------------------===//
6191 let Predicates = [IsLE] in {
6192 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6193 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6194 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6196 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6197 let Predicates = [IsLE] in {
6198 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6199 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6200 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6201 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6202 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6204 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6205 let Predicates = [IsLE] in {
6206 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6207 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6208 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6209 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6210 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6211 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6212 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6213 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6214 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6215 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6217 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6218 let Predicates = [IsLE] in {
6219 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6220 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6221 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6222 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6223 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6224 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6226 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6227 let Predicates = [IsLE] in {
6228 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6229 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6232 let Predicates = [IsLE] in {
6233 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6234 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6235 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6237 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6238 let Predicates = [IsLE] in {
6239 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6240 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6241 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6242 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6243 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6245 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6246 let Predicates = [IsLE] in {
6247 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6248 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6249 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6250 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6251 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6252 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6253 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6254 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6255 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6256 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6257 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6259 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6260 let Predicates = [IsLE] in {
6261 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6262 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6263 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6265 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6266 let Predicates = [IsLE] in {
6267 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6268 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6269 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6270 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6273 let Predicates = [IsBE] in {
6274 // 64 bit conversions
6275 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6276 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6277 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6278 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6279 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6280 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6281 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6282 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6283 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (VREV64d16 DPR:$src)>;
6284 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (VREV32d16 DPR:$src)>;
6285 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (VREV16d8 DPR:$src)>;
6286 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (VREV64d16 DPR:$src)>;
6287 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (VREV32d16 DPR:$src)>;
6288 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (VREV64d8 DPR:$src)>;
6289 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (VREV32d8 DPR:$src)>;
6290 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (VREV16d8 DPR:$src)>;
6291 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (VREV64d8 DPR:$src)>;
6292 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (VREV32d8 DPR:$src)>;
6293 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>;
6294 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>;
6295 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>;
6296 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>;
6297 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>;
6298 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>;
6299 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>;
6300 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>;
6302 // 128 bit conversions
6303 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6304 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6305 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6306 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6307 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6308 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6309 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6310 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6311 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
6312 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
6313 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
6314 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
6315 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
6316 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>;
6317 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
6318 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
6319 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>;
6320 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>;
6321 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
6322 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
6323 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
6324 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
6325 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
6326 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
6327 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
6328 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
6331 // Fold extracting an element out of a v2i32 into a vfp register.
6332 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6333 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6335 // Vector lengthening move with load, matching extending loads.
6337 // extload, zextload and sextload for a standard lengthening load. Example:
6338 // Lengthen_Single<"8", "i16", "8"> =
6339 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6340 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6341 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6342 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6343 let AddedComplexity = 10 in {
6344 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6345 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6346 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6347 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6349 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6350 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6351 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6352 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6354 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6355 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6356 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6357 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6361 // extload, zextload and sextload for a lengthening load which only uses
6362 // half the lanes available. Example:
6363 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6364 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6365 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6366 // (f64 (IMPLICIT_DEF)), (i32 0))),
6368 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6369 string InsnLanes, string InsnTy> {
6370 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6371 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6372 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6373 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6375 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6376 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6377 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6378 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6380 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6381 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6382 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6383 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6387 // The following class definition is basically a copy of the
6388 // Lengthen_HalfSingle definition above, however with an additional parameter
6389 // "RevLanes" to select the correct VREV32dXX instruction. This is to convert
6390 // data loaded by VLD1LN into proper vector format in big endian mode.
6391 multiclass Lengthen_HalfSingle_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6392 string InsnLanes, string InsnTy, string RevLanes> {
6393 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6394 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6395 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6396 (!cast<Instruction>("VREV32d" # RevLanes)
6397 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6399 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6400 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6401 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6402 (!cast<Instruction>("VREV32d" # RevLanes)
6403 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6405 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6406 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6407 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6408 (!cast<Instruction>("VREV32d" # RevLanes)
6409 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6413 // extload, zextload and sextload for a lengthening load followed by another
6414 // lengthening load, to quadruple the initial length.
6416 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6417 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6418 // (EXTRACT_SUBREG (VMOVLuv4i32
6419 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6420 // (f64 (IMPLICIT_DEF)),
6424 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6425 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6427 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6428 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6429 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6430 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6431 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6433 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6434 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6435 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6436 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6437 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6439 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6440 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6441 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6442 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6443 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6447 // The following class definition is basically a copy of the
6448 // Lengthen_Double definition above, however with an additional parameter
6449 // "RevLanes" to select the correct VREV32dXX instruction. This is to convert
6450 // data loaded by VLD1LN into proper vector format in big endian mode.
6451 multiclass Lengthen_Double_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6452 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6453 string Insn2Ty, string RevLanes> {
6454 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6455 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6456 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6457 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6458 (!cast<Instruction>("VREV32d" # RevLanes)
6459 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6461 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6462 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6463 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6464 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6465 (!cast<Instruction>("VREV32d" # RevLanes)
6466 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6468 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6469 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6470 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6471 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6472 (!cast<Instruction>("VREV32d" # RevLanes)
6473 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6477 // extload, zextload and sextload for a lengthening load followed by another
6478 // lengthening load, to quadruple the initial length, but which ends up only
6479 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6481 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6482 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6483 // (EXTRACT_SUBREG (VMOVLuv4i32
6484 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6485 // (f64 (IMPLICIT_DEF)), (i32 0))),
6488 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6489 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6491 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6492 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6493 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6494 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6495 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6498 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6499 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6500 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6501 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6502 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6505 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6506 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6507 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6508 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6509 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6514 // The following class definition is basically a copy of the
6515 // Lengthen_HalfDouble definition above, however with an additional VREV16d8
6516 // instruction to convert data loaded by VLD1LN into proper vector format
6517 // in big endian mode.
6518 multiclass Lengthen_HalfDouble_Big_Endian<string DestLanes, string DestTy, string SrcTy,
6519 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6521 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6522 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6523 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6524 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6525 (!cast<Instruction>("VREV16d8")
6526 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6529 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6530 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6531 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6532 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6533 (!cast<Instruction>("VREV16d8")
6534 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6537 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6538 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6539 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6540 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6541 (!cast<Instruction>("VREV16d8")
6542 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))),
6547 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6548 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6549 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6551 let Predicates = [IsLE] in {
6552 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6553 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6555 // Double lengthening - v4i8 -> v4i16 -> v4i32
6556 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6557 // v2i8 -> v2i16 -> v2i32
6558 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6559 // v2i16 -> v2i32 -> v2i64
6560 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6563 let Predicates = [IsBE] in {
6564 defm : Lengthen_HalfSingle_Big_Endian<"4", "i16", "i8", "8", "i16", "8">; // v4i8 -> v4i16
6565 defm : Lengthen_HalfSingle_Big_Endian<"2", "i32", "i16", "4", "i32", "16">; // v2i16 -> v2i32
6567 // Double lengthening - v4i8 -> v4i16 -> v4i32
6568 defm : Lengthen_Double_Big_Endian<"4", "i32", "i8", "8", "i16", "4", "i32", "8">;
6569 // v2i8 -> v2i16 -> v2i32
6570 defm : Lengthen_HalfDouble_Big_Endian<"2", "i32", "i8", "8", "i16", "4", "i32">;
6571 // v2i16 -> v2i32 -> v2i64
6572 defm : Lengthen_Double_Big_Endian<"2", "i64", "i16", "4", "i32", "2", "i64", "16">;
6575 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6576 let Predicates = [IsLE] in {
6577 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6578 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6579 (VLD1LNd16 addrmode6:$addr,
6580 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6581 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6582 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6583 (VLD1LNd16 addrmode6:$addr,
6584 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6585 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6586 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6587 (VLD1LNd16 addrmode6:$addr,
6588 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6590 // The following patterns are basically a copy of the patterns above,
6591 // however with an additional VREV16d instruction to convert data
6592 // loaded by VLD1LN into proper vector format in big endian mode.
6593 let Predicates = [IsBE] in {
6594 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6595 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6596 (!cast<Instruction>("VREV16d8")
6597 (VLD1LNd16 addrmode6:$addr,
6598 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6599 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6600 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6601 (!cast<Instruction>("VREV16d8")
6602 (VLD1LNd16 addrmode6:$addr,
6603 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6604 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6605 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6606 (!cast<Instruction>("VREV16d8")
6607 (VLD1LNd16 addrmode6:$addr,
6608 (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>;
6611 //===----------------------------------------------------------------------===//
6612 // Assembler aliases
6615 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6616 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6617 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6618 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6620 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6621 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6622 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6623 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6624 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6625 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6626 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6627 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6628 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6629 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6630 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6631 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6632 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6633 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6634 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6635 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6636 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6637 // ... two-operand aliases
6638 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6639 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6640 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6641 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6642 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6643 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6644 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6645 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6646 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6647 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6648 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6649 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6651 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
6652 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
6653 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
6654 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
6655 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
6656 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
6657 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
6658 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
6661 // VLD1 single-lane pseudo-instructions. These need special handling for
6662 // the lane index that an InstAlias can't handle, so we use these instead.
6663 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6664 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6666 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6667 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6669 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6670 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6673 def VLD1LNdWB_fixed_Asm_8 :
6674 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6675 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6677 def VLD1LNdWB_fixed_Asm_16 :
6678 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6679 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6681 def VLD1LNdWB_fixed_Asm_32 :
6682 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6683 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6685 def VLD1LNdWB_register_Asm_8 :
6686 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6687 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6688 rGPR:$Rm, pred:$p)>;
6689 def VLD1LNdWB_register_Asm_16 :
6690 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6691 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6692 rGPR:$Rm, pred:$p)>;
6693 def VLD1LNdWB_register_Asm_32 :
6694 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6695 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6696 rGPR:$Rm, pred:$p)>;
6699 // VST1 single-lane pseudo-instructions. These need special handling for
6700 // the lane index that an InstAlias can't handle, so we use these instead.
6701 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6702 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6704 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6705 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6707 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6708 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6711 def VST1LNdWB_fixed_Asm_8 :
6712 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6713 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6715 def VST1LNdWB_fixed_Asm_16 :
6716 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6717 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6719 def VST1LNdWB_fixed_Asm_32 :
6720 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6721 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6723 def VST1LNdWB_register_Asm_8 :
6724 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6725 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6726 rGPR:$Rm, pred:$p)>;
6727 def VST1LNdWB_register_Asm_16 :
6728 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6729 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6730 rGPR:$Rm, pred:$p)>;
6731 def VST1LNdWB_register_Asm_32 :
6732 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6733 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6734 rGPR:$Rm, pred:$p)>;
6736 // VLD2 single-lane pseudo-instructions. These need special handling for
6737 // the lane index that an InstAlias can't handle, so we use these instead.
6738 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6739 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6741 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6742 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6744 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6745 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
6746 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6747 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6749 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6750 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6753 def VLD2LNdWB_fixed_Asm_8 :
6754 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6755 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6757 def VLD2LNdWB_fixed_Asm_16 :
6758 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6759 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6761 def VLD2LNdWB_fixed_Asm_32 :
6762 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6763 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6765 def VLD2LNqWB_fixed_Asm_16 :
6766 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6767 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6769 def VLD2LNqWB_fixed_Asm_32 :
6770 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6771 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6773 def VLD2LNdWB_register_Asm_8 :
6774 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6775 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6776 rGPR:$Rm, pred:$p)>;
6777 def VLD2LNdWB_register_Asm_16 :
6778 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6779 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6780 rGPR:$Rm, pred:$p)>;
6781 def VLD2LNdWB_register_Asm_32 :
6782 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6783 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6784 rGPR:$Rm, pred:$p)>;
6785 def VLD2LNqWB_register_Asm_16 :
6786 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6787 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6788 rGPR:$Rm, pred:$p)>;
6789 def VLD2LNqWB_register_Asm_32 :
6790 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6791 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6792 rGPR:$Rm, pred:$p)>;
6795 // VST2 single-lane pseudo-instructions. These need special handling for
6796 // the lane index that an InstAlias can't handle, so we use these instead.
6797 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6798 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6800 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6801 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6803 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6804 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6806 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6807 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6809 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6810 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6813 def VST2LNdWB_fixed_Asm_8 :
6814 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6815 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6817 def VST2LNdWB_fixed_Asm_16 :
6818 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6819 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6821 def VST2LNdWB_fixed_Asm_32 :
6822 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6823 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6825 def VST2LNqWB_fixed_Asm_16 :
6826 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6827 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6829 def VST2LNqWB_fixed_Asm_32 :
6830 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6831 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6833 def VST2LNdWB_register_Asm_8 :
6834 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6835 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6836 rGPR:$Rm, pred:$p)>;
6837 def VST2LNdWB_register_Asm_16 :
6838 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6839 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6840 rGPR:$Rm, pred:$p)>;
6841 def VST2LNdWB_register_Asm_32 :
6842 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6843 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6844 rGPR:$Rm, pred:$p)>;
6845 def VST2LNqWB_register_Asm_16 :
6846 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6847 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6848 rGPR:$Rm, pred:$p)>;
6849 def VST2LNqWB_register_Asm_32 :
6850 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6851 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6852 rGPR:$Rm, pred:$p)>;
6854 // VLD3 all-lanes pseudo-instructions. These need special handling for
6855 // the lane index that an InstAlias can't handle, so we use these instead.
6856 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6857 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6859 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6860 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6862 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6863 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6865 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6866 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6868 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6869 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6871 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6872 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6875 def VLD3DUPdWB_fixed_Asm_8 :
6876 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6877 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6879 def VLD3DUPdWB_fixed_Asm_16 :
6880 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6881 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6883 def VLD3DUPdWB_fixed_Asm_32 :
6884 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6885 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6887 def VLD3DUPqWB_fixed_Asm_8 :
6888 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6889 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6891 def VLD3DUPqWB_fixed_Asm_16 :
6892 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6893 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6895 def VLD3DUPqWB_fixed_Asm_32 :
6896 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6897 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6899 def VLD3DUPdWB_register_Asm_8 :
6900 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6901 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6902 rGPR:$Rm, pred:$p)>;
6903 def VLD3DUPdWB_register_Asm_16 :
6904 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6905 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6906 rGPR:$Rm, pred:$p)>;
6907 def VLD3DUPdWB_register_Asm_32 :
6908 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6909 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6910 rGPR:$Rm, pred:$p)>;
6911 def VLD3DUPqWB_register_Asm_8 :
6912 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6913 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6914 rGPR:$Rm, pred:$p)>;
6915 def VLD3DUPqWB_register_Asm_16 :
6916 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6917 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6918 rGPR:$Rm, pred:$p)>;
6919 def VLD3DUPqWB_register_Asm_32 :
6920 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6921 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6922 rGPR:$Rm, pred:$p)>;
6925 // VLD3 single-lane pseudo-instructions. These need special handling for
6926 // the lane index that an InstAlias can't handle, so we use these instead.
6927 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6928 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6930 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6931 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6933 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6934 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6936 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6937 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6939 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6940 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6943 def VLD3LNdWB_fixed_Asm_8 :
6944 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6945 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6947 def VLD3LNdWB_fixed_Asm_16 :
6948 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6949 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6951 def VLD3LNdWB_fixed_Asm_32 :
6952 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6953 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6955 def VLD3LNqWB_fixed_Asm_16 :
6956 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6957 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6959 def VLD3LNqWB_fixed_Asm_32 :
6960 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6961 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6963 def VLD3LNdWB_register_Asm_8 :
6964 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6965 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6966 rGPR:$Rm, pred:$p)>;
6967 def VLD3LNdWB_register_Asm_16 :
6968 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6969 (ins VecListThreeDHWordIndexed:$list,
6970 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6971 def VLD3LNdWB_register_Asm_32 :
6972 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6973 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6974 rGPR:$Rm, pred:$p)>;
6975 def VLD3LNqWB_register_Asm_16 :
6976 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6977 (ins VecListThreeQHWordIndexed:$list,
6978 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6979 def VLD3LNqWB_register_Asm_32 :
6980 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6981 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6982 rGPR:$Rm, pred:$p)>;
6984 // VLD3 multiple structure pseudo-instructions. These need special handling for
6985 // the vector operands that the normal instructions don't yet model.
6986 // FIXME: Remove these when the register classes and instructions are updated.
6987 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6988 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6989 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6990 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6991 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6992 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6993 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6994 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6995 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6996 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6997 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6998 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7000 def VLD3dWB_fixed_Asm_8 :
7001 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7002 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7003 def VLD3dWB_fixed_Asm_16 :
7004 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7005 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7006 def VLD3dWB_fixed_Asm_32 :
7007 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7008 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7009 def VLD3qWB_fixed_Asm_8 :
7010 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
7011 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7012 def VLD3qWB_fixed_Asm_16 :
7013 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
7014 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7015 def VLD3qWB_fixed_Asm_32 :
7016 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
7017 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7018 def VLD3dWB_register_Asm_8 :
7019 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7020 (ins VecListThreeD:$list, addrmode6align64:$addr,
7021 rGPR:$Rm, pred:$p)>;
7022 def VLD3dWB_register_Asm_16 :
7023 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7024 (ins VecListThreeD:$list, addrmode6align64:$addr,
7025 rGPR:$Rm, pred:$p)>;
7026 def VLD3dWB_register_Asm_32 :
7027 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7028 (ins VecListThreeD:$list, addrmode6align64:$addr,
7029 rGPR:$Rm, pred:$p)>;
7030 def VLD3qWB_register_Asm_8 :
7031 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
7032 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7033 rGPR:$Rm, pred:$p)>;
7034 def VLD3qWB_register_Asm_16 :
7035 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
7036 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7037 rGPR:$Rm, pred:$p)>;
7038 def VLD3qWB_register_Asm_32 :
7039 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
7040 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7041 rGPR:$Rm, pred:$p)>;
7043 // VST3 single-lane pseudo-instructions. These need special handling for
7044 // the lane index that an InstAlias can't handle, so we use these instead.
7045 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7046 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7048 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7049 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7051 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7052 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7054 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7055 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7057 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7058 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7061 def VST3LNdWB_fixed_Asm_8 :
7062 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7063 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7065 def VST3LNdWB_fixed_Asm_16 :
7066 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7067 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
7069 def VST3LNdWB_fixed_Asm_32 :
7070 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7071 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7073 def VST3LNqWB_fixed_Asm_16 :
7074 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7075 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
7077 def VST3LNqWB_fixed_Asm_32 :
7078 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7079 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7081 def VST3LNdWB_register_Asm_8 :
7082 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7083 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
7084 rGPR:$Rm, pred:$p)>;
7085 def VST3LNdWB_register_Asm_16 :
7086 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7087 (ins VecListThreeDHWordIndexed:$list,
7088 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7089 def VST3LNdWB_register_Asm_32 :
7090 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7091 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
7092 rGPR:$Rm, pred:$p)>;
7093 def VST3LNqWB_register_Asm_16 :
7094 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7095 (ins VecListThreeQHWordIndexed:$list,
7096 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
7097 def VST3LNqWB_register_Asm_32 :
7098 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7099 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
7100 rGPR:$Rm, pred:$p)>;
7103 // VST3 multiple structure pseudo-instructions. These need special handling for
7104 // the vector operands that the normal instructions don't yet model.
7105 // FIXME: Remove these when the register classes and instructions are updated.
7106 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7107 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7108 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7109 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7110 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7111 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7112 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
7113 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7114 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
7115 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7116 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
7117 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7119 def VST3dWB_fixed_Asm_8 :
7120 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7121 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7122 def VST3dWB_fixed_Asm_16 :
7123 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7124 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7125 def VST3dWB_fixed_Asm_32 :
7126 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7127 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
7128 def VST3qWB_fixed_Asm_8 :
7129 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
7130 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7131 def VST3qWB_fixed_Asm_16 :
7132 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
7133 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7134 def VST3qWB_fixed_Asm_32 :
7135 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
7136 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
7137 def VST3dWB_register_Asm_8 :
7138 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7139 (ins VecListThreeD:$list, addrmode6align64:$addr,
7140 rGPR:$Rm, pred:$p)>;
7141 def VST3dWB_register_Asm_16 :
7142 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7143 (ins VecListThreeD:$list, addrmode6align64:$addr,
7144 rGPR:$Rm, pred:$p)>;
7145 def VST3dWB_register_Asm_32 :
7146 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7147 (ins VecListThreeD:$list, addrmode6align64:$addr,
7148 rGPR:$Rm, pred:$p)>;
7149 def VST3qWB_register_Asm_8 :
7150 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
7151 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7152 rGPR:$Rm, pred:$p)>;
7153 def VST3qWB_register_Asm_16 :
7154 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
7155 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7156 rGPR:$Rm, pred:$p)>;
7157 def VST3qWB_register_Asm_32 :
7158 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
7159 (ins VecListThreeQ:$list, addrmode6align64:$addr,
7160 rGPR:$Rm, pred:$p)>;
7162 // VLD4 all-lanes pseudo-instructions. These need special handling for
7163 // the lane index that an InstAlias can't handle, so we use these instead.
7164 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7165 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7167 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7168 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7170 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7171 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
7173 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7174 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7176 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7177 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7179 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7180 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
7183 def VLD4DUPdWB_fixed_Asm_8 :
7184 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7185 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7187 def VLD4DUPdWB_fixed_Asm_16 :
7188 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7189 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7191 def VLD4DUPdWB_fixed_Asm_32 :
7192 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7193 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
7195 def VLD4DUPqWB_fixed_Asm_8 :
7196 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7197 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7199 def VLD4DUPqWB_fixed_Asm_16 :
7200 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7201 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7203 def VLD4DUPqWB_fixed_Asm_32 :
7204 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7205 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
7207 def VLD4DUPdWB_register_Asm_8 :
7208 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7209 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
7210 rGPR:$Rm, pred:$p)>;
7211 def VLD4DUPdWB_register_Asm_16 :
7212 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7213 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
7214 rGPR:$Rm, pred:$p)>;
7215 def VLD4DUPdWB_register_Asm_32 :
7216 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7217 (ins VecListFourDAllLanes:$list,
7218 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
7219 def VLD4DUPqWB_register_Asm_8 :
7220 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7221 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7222 rGPR:$Rm, pred:$p)>;
7223 def VLD4DUPqWB_register_Asm_16 :
7224 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7225 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7226 rGPR:$Rm, pred:$p)>;
7227 def VLD4DUPqWB_register_Asm_32 :
7228 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7229 (ins VecListFourQAllLanes:$list,
7230 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
7233 // VLD4 single-lane pseudo-instructions. These need special handling for
7234 // the lane index that an InstAlias can't handle, so we use these instead.
7235 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7236 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7238 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7239 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7241 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7242 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7244 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7245 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7247 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7248 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7251 def VLD4LNdWB_fixed_Asm_8 :
7252 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7253 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7255 def VLD4LNdWB_fixed_Asm_16 :
7256 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7257 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7259 def VLD4LNdWB_fixed_Asm_32 :
7260 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7261 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7263 def VLD4LNqWB_fixed_Asm_16 :
7264 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7265 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7267 def VLD4LNqWB_fixed_Asm_32 :
7268 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7269 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7271 def VLD4LNdWB_register_Asm_8 :
7272 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7273 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7274 rGPR:$Rm, pred:$p)>;
7275 def VLD4LNdWB_register_Asm_16 :
7276 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7277 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7278 rGPR:$Rm, pred:$p)>;
7279 def VLD4LNdWB_register_Asm_32 :
7280 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7281 (ins VecListFourDWordIndexed:$list,
7282 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7283 def VLD4LNqWB_register_Asm_16 :
7284 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7285 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7286 rGPR:$Rm, pred:$p)>;
7287 def VLD4LNqWB_register_Asm_32 :
7288 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7289 (ins VecListFourQWordIndexed:$list,
7290 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7294 // VLD4 multiple structure pseudo-instructions. These need special handling for
7295 // the vector operands that the normal instructions don't yet model.
7296 // FIXME: Remove these when the register classes and instructions are updated.
7297 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7298 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7300 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7301 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7303 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7304 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7306 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7307 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7309 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7310 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7312 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7313 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7316 def VLD4dWB_fixed_Asm_8 :
7317 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7318 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7320 def VLD4dWB_fixed_Asm_16 :
7321 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7322 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7324 def VLD4dWB_fixed_Asm_32 :
7325 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7326 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7328 def VLD4qWB_fixed_Asm_8 :
7329 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7330 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7332 def VLD4qWB_fixed_Asm_16 :
7333 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7334 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7336 def VLD4qWB_fixed_Asm_32 :
7337 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7338 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7340 def VLD4dWB_register_Asm_8 :
7341 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7342 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7343 rGPR:$Rm, pred:$p)>;
7344 def VLD4dWB_register_Asm_16 :
7345 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7346 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7347 rGPR:$Rm, pred:$p)>;
7348 def VLD4dWB_register_Asm_32 :
7349 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7350 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7351 rGPR:$Rm, pred:$p)>;
7352 def VLD4qWB_register_Asm_8 :
7353 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7354 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7355 rGPR:$Rm, pred:$p)>;
7356 def VLD4qWB_register_Asm_16 :
7357 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7358 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7359 rGPR:$Rm, pred:$p)>;
7360 def VLD4qWB_register_Asm_32 :
7361 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7362 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7363 rGPR:$Rm, pred:$p)>;
7365 // VST4 single-lane pseudo-instructions. These need special handling for
7366 // the lane index that an InstAlias can't handle, so we use these instead.
7367 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7368 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7370 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7371 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7373 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7374 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7376 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7377 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7379 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7380 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7383 def VST4LNdWB_fixed_Asm_8 :
7384 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7385 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7387 def VST4LNdWB_fixed_Asm_16 :
7388 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7389 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7391 def VST4LNdWB_fixed_Asm_32 :
7392 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7393 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7395 def VST4LNqWB_fixed_Asm_16 :
7396 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7397 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7399 def VST4LNqWB_fixed_Asm_32 :
7400 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7401 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7403 def VST4LNdWB_register_Asm_8 :
7404 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7405 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7406 rGPR:$Rm, pred:$p)>;
7407 def VST4LNdWB_register_Asm_16 :
7408 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7409 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7410 rGPR:$Rm, pred:$p)>;
7411 def VST4LNdWB_register_Asm_32 :
7412 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7413 (ins VecListFourDWordIndexed:$list,
7414 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7415 def VST4LNqWB_register_Asm_16 :
7416 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7417 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7418 rGPR:$Rm, pred:$p)>;
7419 def VST4LNqWB_register_Asm_32 :
7420 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7421 (ins VecListFourQWordIndexed:$list,
7422 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7425 // VST4 multiple structure pseudo-instructions. These need special handling for
7426 // the vector operands that the normal instructions don't yet model.
7427 // FIXME: Remove these when the register classes and instructions are updated.
7428 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7429 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7431 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7432 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7434 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7435 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7437 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7438 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7440 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7441 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7443 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7444 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7447 def VST4dWB_fixed_Asm_8 :
7448 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7449 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7451 def VST4dWB_fixed_Asm_16 :
7452 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7453 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7455 def VST4dWB_fixed_Asm_32 :
7456 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7457 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7459 def VST4qWB_fixed_Asm_8 :
7460 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7461 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7463 def VST4qWB_fixed_Asm_16 :
7464 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7465 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7467 def VST4qWB_fixed_Asm_32 :
7468 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7469 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7471 def VST4dWB_register_Asm_8 :
7472 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7473 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7474 rGPR:$Rm, pred:$p)>;
7475 def VST4dWB_register_Asm_16 :
7476 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7477 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7478 rGPR:$Rm, pred:$p)>;
7479 def VST4dWB_register_Asm_32 :
7480 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7481 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7482 rGPR:$Rm, pred:$p)>;
7483 def VST4qWB_register_Asm_8 :
7484 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7485 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7486 rGPR:$Rm, pred:$p)>;
7487 def VST4qWB_register_Asm_16 :
7488 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7489 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7490 rGPR:$Rm, pred:$p)>;
7491 def VST4qWB_register_Asm_32 :
7492 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7493 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7494 rGPR:$Rm, pred:$p)>;
7496 // VMOV/VMVN takes an optional datatype suffix
7497 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7498 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
7499 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7500 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7502 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7503 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
7504 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7505 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7507 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7508 // D-register versions.
7509 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
7510 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7511 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
7512 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7513 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
7514 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7515 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
7516 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7517 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
7518 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7519 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
7520 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7521 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
7522 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7523 // Q-register versions.
7524 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
7525 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7526 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
7527 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7528 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
7529 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7530 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
7531 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7532 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
7533 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7534 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
7535 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7536 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
7537 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7539 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7540 // D-register versions.
7541 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7542 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7543 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7544 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7545 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7546 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7547 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7548 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7549 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7550 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7551 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7552 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7553 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7554 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7555 // Q-register versions.
7556 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7557 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7558 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7559 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7560 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7561 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7562 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7563 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7564 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7565 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7566 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7567 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7568 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7569 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7571 // VSWP allows, but does not require, a type suffix.
7572 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7573 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7574 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7575 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7577 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7578 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7579 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7580 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7581 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7582 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7583 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7584 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7585 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7586 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7587 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7588 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7589 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7591 // "vmov Rd, #-imm" can be handled via "vmvn".
7592 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7593 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7594 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7595 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7596 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7597 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7598 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7599 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7601 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7602 // these should restrict to just the Q register variants, but the register
7603 // classes are enough to match correctly regardless, so we keep it simple
7604 // and just use MnemonicAlias.
7605 def : NEONMnemonicAlias<"vbicq", "vbic">;
7606 def : NEONMnemonicAlias<"vandq", "vand">;
7607 def : NEONMnemonicAlias<"veorq", "veor">;
7608 def : NEONMnemonicAlias<"vorrq", "vorr">;
7610 def : NEONMnemonicAlias<"vmovq", "vmov">;
7611 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7612 // Explicit versions for floating point so that the FPImm variants get
7613 // handled early. The parser gets confused otherwise.
7614 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7615 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7617 def : NEONMnemonicAlias<"vaddq", "vadd">;
7618 def : NEONMnemonicAlias<"vsubq", "vsub">;
7620 def : NEONMnemonicAlias<"vminq", "vmin">;
7621 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7623 def : NEONMnemonicAlias<"vmulq", "vmul">;
7625 def : NEONMnemonicAlias<"vabsq", "vabs">;
7627 def : NEONMnemonicAlias<"vshlq", "vshl">;
7628 def : NEONMnemonicAlias<"vshrq", "vshr">;
7630 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7632 def : NEONMnemonicAlias<"vcleq", "vcle">;
7633 def : NEONMnemonicAlias<"vceqq", "vceq">;
7635 def : NEONMnemonicAlias<"vzipq", "vzip">;
7636 def : NEONMnemonicAlias<"vswpq", "vswp">;
7638 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7639 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7642 // Alias for loading floating point immediates that aren't representable
7643 // using the vmov.f32 encoding but the bitpattern is representable using
7644 // the .i32 encoding.
7645 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7646 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7647 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7648 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;