1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
43 def nImmSplatI64 : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmSplatI64AsmOperand;
48 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
49 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
50 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
51 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
52 return ((uint64_t)Imm) < 8;
54 let ParserMatchClass = VectorIndex8Operand;
55 let PrintMethod = "printVectorIndex";
56 let MIOperandInfo = (ops i32imm);
58 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
59 return ((uint64_t)Imm) < 4;
61 let ParserMatchClass = VectorIndex16Operand;
62 let PrintMethod = "printVectorIndex";
63 let MIOperandInfo = (ops i32imm);
65 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
66 return ((uint64_t)Imm) < 2;
68 let ParserMatchClass = VectorIndex32Operand;
69 let PrintMethod = "printVectorIndex";
70 let MIOperandInfo = (ops i32imm);
73 def VecListOneDAsmOperand : AsmOperandClass {
74 let Name = "VecListOneD";
75 let ParserMethod = "parseVectorList";
77 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
78 let ParserMatchClass = VecListOneDAsmOperand;
80 // Register list of two sequential D registers.
81 def VecListTwoDAsmOperand : AsmOperandClass {
82 let Name = "VecListTwoD";
83 let ParserMethod = "parseVectorList";
85 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
86 let ParserMatchClass = VecListTwoDAsmOperand;
88 // Register list of three sequential D registers.
89 def VecListThreeDAsmOperand : AsmOperandClass {
90 let Name = "VecListThreeD";
91 let ParserMethod = "parseVectorList";
93 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
94 let ParserMatchClass = VecListThreeDAsmOperand;
96 // Register list of four sequential D registers.
97 def VecListFourDAsmOperand : AsmOperandClass {
98 let Name = "VecListFourD";
99 let ParserMethod = "parseVectorList";
101 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
102 let ParserMatchClass = VecListFourDAsmOperand;
104 // Register list of two D registers spaced by 2 (two sequential Q registers).
105 def VecListTwoQAsmOperand : AsmOperandClass {
106 let Name = "VecListTwoQ";
107 let ParserMethod = "parseVectorList";
109 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
110 let ParserMatchClass = VecListTwoQAsmOperand;
113 //===----------------------------------------------------------------------===//
114 // NEON-specific DAG Nodes.
115 //===----------------------------------------------------------------------===//
117 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
118 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
120 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
121 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
122 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
123 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
124 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
125 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
126 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
127 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
128 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
129 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
130 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
132 // Types for vector shift by immediates. The "SHX" version is for long and
133 // narrow operations where the source and destination vectors have different
134 // types. The "SHINS" version is for shift and insert operations.
135 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
137 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
139 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
140 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
142 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
143 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
144 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
145 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
146 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
147 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
148 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
150 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
151 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
152 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
154 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
155 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
156 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
157 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
158 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
159 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
161 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
162 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
163 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
165 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
166 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
168 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
170 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
171 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
173 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
174 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
175 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
177 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
179 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
180 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
182 def NEONvbsl : SDNode<"ARMISD::VBSL",
183 SDTypeProfile<1, 3, [SDTCisVec<0>,
186 SDTCisSameAs<0, 3>]>>;
188 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
190 // VDUPLANE can produce a quad-register result from a double-register source,
191 // so the result is not constrained to match the source.
192 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
193 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
196 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
197 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
198 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
200 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
201 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
202 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
203 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
205 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
207 SDTCisSameAs<0, 3>]>;
208 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
209 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
210 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
212 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
213 SDTCisSameAs<1, 2>]>;
214 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
215 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
217 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
218 SDTCisSameAs<0, 2>]>;
219 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
220 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
222 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
223 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
224 unsigned EltBits = 0;
225 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
226 return (EltBits == 32 && EltVal == 0);
229 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
230 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
231 unsigned EltBits = 0;
232 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
233 return (EltBits == 8 && EltVal == 0xff);
236 //===----------------------------------------------------------------------===//
237 // NEON load / store instructions
238 //===----------------------------------------------------------------------===//
240 // Use VLDM to load a Q register as a D register pair.
241 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
243 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
245 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
247 // Use VSTM to store a Q register as a D register pair.
248 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
250 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
252 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
254 // Classes for VLD* pseudo-instructions with multi-register operands.
255 // These are expanded to real instructions after register allocation.
256 class VLDQPseudo<InstrItinClass itin>
257 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
258 class VLDQWBPseudo<InstrItinClass itin>
259 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
260 (ins addrmode6:$addr, am6offset:$offset), itin,
262 class VLDQWBfixedPseudo<InstrItinClass itin>
263 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
264 (ins addrmode6:$addr), itin,
266 class VLDQWBregisterPseudo<InstrItinClass itin>
267 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
268 (ins addrmode6:$addr, rGPR:$offset), itin,
270 class VLDQQPseudo<InstrItinClass itin>
271 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
272 class VLDQQWBPseudo<InstrItinClass itin>
273 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
274 (ins addrmode6:$addr, am6offset:$offset), itin,
276 class VLDQQQQPseudo<InstrItinClass itin>
277 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
279 class VLDQQQQWBPseudo<InstrItinClass itin>
280 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
281 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
282 "$addr.addr = $wb, $src = $dst">;
284 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
286 // VLD1 : Vector Load (multiple single elements)
287 class VLD1D<bits<4> op7_4, string Dt>
288 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
289 (ins addrmode6:$Rn), IIC_VLD1,
290 "vld1", Dt, "$Vd, $Rn", "", []> {
293 let DecoderMethod = "DecodeVLDInstruction";
295 class VLD1Q<bits<4> op7_4, string Dt>
296 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
297 (ins addrmode6:$Rn), IIC_VLD1x2,
298 "vld1", Dt, "$Vd, $Rn", "", []> {
300 let Inst{5-4} = Rn{5-4};
301 let DecoderMethod = "DecodeVLDInstruction";
304 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
305 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
306 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
307 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
309 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
310 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
311 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
312 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
314 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
315 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
316 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
317 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
319 // ...with address register writeback:
320 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
321 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
322 (ins addrmode6:$Rn), IIC_VLD1u,
323 "vld1", Dt, "$Vd, $Rn!",
324 "$Rn.addr = $wb", []> {
325 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
327 let DecoderMethod = "DecodeVLDInstruction";
329 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
330 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
331 "vld1", Dt, "$Vd, $Rn, $Rm",
332 "$Rn.addr = $wb", []> {
334 let DecoderMethod = "DecodeVLDInstruction";
337 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
338 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
339 (ins addrmode6:$Rn), IIC_VLD1x2u,
340 "vld1", Dt, "$Vd, $Rn!",
341 "$Rn.addr = $wb", []> {
342 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
343 let Inst{5-4} = Rn{5-4};
344 let DecoderMethod = "DecodeVLDInstruction";
346 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
347 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
348 "vld1", Dt, "$Vd, $Rn, $Rm",
349 "$Rn.addr = $wb", []> {
350 let Inst{5-4} = Rn{5-4};
351 let DecoderMethod = "DecodeVLDInstruction";
355 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
356 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
357 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
358 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
359 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
360 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
361 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
362 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
364 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
365 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
366 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
367 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
368 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
369 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
370 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
371 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
373 // ...with 3 registers
374 class VLD1D3<bits<4> op7_4, string Dt>
375 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
376 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
377 "$Vd, $Rn", "", []> {
380 let DecoderMethod = "DecodeVLDInstruction";
382 class VLD1D3WB<bits<4> op7_4, string Dt>
383 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
384 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
385 "$Vd, $Rn$Rm", "$Rn.addr = $wb", []> {
387 let DecoderMethod = "DecodeVLDInstruction";
390 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
391 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
392 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
393 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
395 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
396 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
397 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
398 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
400 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
401 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
403 // ...with 4 registers
404 class VLD1D4<bits<4> op7_4, string Dt>
405 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
406 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
407 "$Vd, $Rn", "", []> {
409 let Inst{5-4} = Rn{5-4};
410 let DecoderMethod = "DecodeVLDInstruction";
412 class VLD1D4WB<bits<4> op7_4, string Dt>
413 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
414 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
415 "$Vd, $Rn$Rm", "$Rn.addr = $wb",
417 let Inst{5-4} = Rn{5-4};
418 let DecoderMethod = "DecodeVLDInstruction";
421 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
422 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
423 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
424 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
426 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
427 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
428 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
429 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
431 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
432 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
434 // VLD2 : Vector Load (multiple 2-element structures)
435 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
436 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
437 (ins addrmode6:$Rn), IIC_VLD2,
438 "vld2", Dt, "$Vd, $Rn", "", []> {
440 let Inst{5-4} = Rn{5-4};
441 let DecoderMethod = "DecodeVLDInstruction";
443 class VLD2Q<bits<4> op7_4, string Dt, RegisterOperand VdTy>
444 : NLdSt<0, 0b10, 0b0011, op7_4,
446 (ins addrmode6:$Rn), IIC_VLD2x2,
447 "vld2", Dt, "$Vd, $Rn", "", []> {
449 let Inst{5-4} = Rn{5-4};
450 let DecoderMethod = "DecodeVLDInstruction";
453 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
454 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
455 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
457 def VLD2q8 : VLD2Q<{0,0,?,?}, "8", VecListFourD>;
458 def VLD2q16 : VLD2Q<{0,1,?,?}, "16", VecListFourD>;
459 def VLD2q32 : VLD2Q<{1,0,?,?}, "32", VecListFourD>;
461 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
462 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
463 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
465 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
466 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
467 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
469 // ...with address register writeback:
470 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
471 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
472 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
473 "vld2", Dt, "$Vd, $Rn$Rm",
474 "$Rn.addr = $wb", []> {
475 let Inst{5-4} = Rn{5-4};
476 let DecoderMethod = "DecodeVLDInstruction";
478 class VLD2QWB<bits<4> op7_4, string Dt, RegisterOperand VdTy>
479 : NLdSt<0, 0b10, 0b0011, op7_4,
480 (outs VdTy:$Vd, GPR:$wb),
481 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
482 "vld2", Dt, "$Vd, $Rn$Rm",
483 "$Rn.addr = $wb", []> {
484 let Inst{5-4} = Rn{5-4};
485 let DecoderMethod = "DecodeVLDInstruction";
488 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
489 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
490 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
492 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8", VecListFourD>;
493 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16", VecListFourD>;
494 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32", VecListFourD>;
496 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
497 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
498 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
500 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
501 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
502 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
504 // ...with double-spaced registers
505 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
506 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
507 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
508 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
509 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
510 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
512 // VLD3 : Vector Load (multiple 3-element structures)
513 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
514 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
515 (ins addrmode6:$Rn), IIC_VLD3,
516 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
519 let DecoderMethod = "DecodeVLDInstruction";
522 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
523 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
524 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
526 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
527 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
528 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
530 // ...with address register writeback:
531 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
532 : NLdSt<0, 0b10, op11_8, op7_4,
533 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
534 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
535 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
536 "$Rn.addr = $wb", []> {
538 let DecoderMethod = "DecodeVLDInstruction";
541 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
542 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
543 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
545 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
546 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
547 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
549 // ...with double-spaced registers:
550 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
551 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
552 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
553 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
554 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
555 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
557 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
558 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
559 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
561 // ...alternate versions to be allocated odd register numbers:
562 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
563 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
564 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
566 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
567 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
568 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
570 // VLD4 : Vector Load (multiple 4-element structures)
571 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
572 : NLdSt<0, 0b10, op11_8, op7_4,
573 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
574 (ins addrmode6:$Rn), IIC_VLD4,
575 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
577 let Inst{5-4} = Rn{5-4};
578 let DecoderMethod = "DecodeVLDInstruction";
581 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
582 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
583 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
585 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
586 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
587 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
589 // ...with address register writeback:
590 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
591 : NLdSt<0, 0b10, op11_8, op7_4,
592 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
593 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
594 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
595 "$Rn.addr = $wb", []> {
596 let Inst{5-4} = Rn{5-4};
597 let DecoderMethod = "DecodeVLDInstruction";
600 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
601 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
602 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
604 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
605 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
606 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
608 // ...with double-spaced registers:
609 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
610 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
611 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
612 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
613 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
614 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
616 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
617 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
618 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
620 // ...alternate versions to be allocated odd register numbers:
621 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
622 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
623 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
625 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
626 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
627 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
629 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
631 // Classes for VLD*LN pseudo-instructions with multi-register operands.
632 // These are expanded to real instructions after register allocation.
633 class VLDQLNPseudo<InstrItinClass itin>
634 : PseudoNLdSt<(outs QPR:$dst),
635 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
636 itin, "$src = $dst">;
637 class VLDQLNWBPseudo<InstrItinClass itin>
638 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
639 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
640 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
641 class VLDQQLNPseudo<InstrItinClass itin>
642 : PseudoNLdSt<(outs QQPR:$dst),
643 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
644 itin, "$src = $dst">;
645 class VLDQQLNWBPseudo<InstrItinClass itin>
646 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
647 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
648 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
649 class VLDQQQQLNPseudo<InstrItinClass itin>
650 : PseudoNLdSt<(outs QQQQPR:$dst),
651 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
652 itin, "$src = $dst">;
653 class VLDQQQQLNWBPseudo<InstrItinClass itin>
654 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
655 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
656 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
658 // VLD1LN : Vector Load (single element to one lane)
659 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
661 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
662 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
663 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
665 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
666 (i32 (LoadOp addrmode6:$Rn)),
669 let DecoderMethod = "DecodeVLD1LN";
671 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
673 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
674 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
675 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
677 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
678 (i32 (LoadOp addrmode6oneL32:$Rn)),
681 let DecoderMethod = "DecodeVLD1LN";
683 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
684 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
685 (i32 (LoadOp addrmode6:$addr)),
689 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
690 let Inst{7-5} = lane{2-0};
692 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
693 let Inst{7-6} = lane{1-0};
696 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
697 let Inst{7} = lane{0};
702 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
703 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
704 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
706 def : Pat<(vector_insert (v2f32 DPR:$src),
707 (f32 (load addrmode6:$addr)), imm:$lane),
708 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
709 def : Pat<(vector_insert (v4f32 QPR:$src),
710 (f32 (load addrmode6:$addr)), imm:$lane),
711 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
713 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
715 // ...with address register writeback:
716 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
717 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
718 (ins addrmode6:$Rn, am6offset:$Rm,
719 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
720 "\\{$Vd[$lane]\\}, $Rn$Rm",
721 "$src = $Vd, $Rn.addr = $wb", []> {
722 let DecoderMethod = "DecodeVLD1LN";
725 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
726 let Inst{7-5} = lane{2-0};
728 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
729 let Inst{7-6} = lane{1-0};
732 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
733 let Inst{7} = lane{0};
738 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
739 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
740 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
742 // VLD2LN : Vector Load (single 2-element structure to one lane)
743 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
744 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
745 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
746 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
747 "$src1 = $Vd, $src2 = $dst2", []> {
750 let DecoderMethod = "DecodeVLD2LN";
753 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
754 let Inst{7-5} = lane{2-0};
756 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
757 let Inst{7-6} = lane{1-0};
759 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
760 let Inst{7} = lane{0};
763 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
764 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
765 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
767 // ...with double-spaced registers:
768 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
769 let Inst{7-6} = lane{1-0};
771 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
772 let Inst{7} = lane{0};
775 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
776 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
778 // ...with address register writeback:
779 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
780 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
781 (ins addrmode6:$Rn, am6offset:$Rm,
782 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
783 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
784 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
786 let DecoderMethod = "DecodeVLD2LN";
789 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
790 let Inst{7-5} = lane{2-0};
792 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
793 let Inst{7-6} = lane{1-0};
795 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
796 let Inst{7} = lane{0};
799 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
800 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
801 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
803 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
804 let Inst{7-6} = lane{1-0};
806 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
807 let Inst{7} = lane{0};
810 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
811 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
813 // VLD3LN : Vector Load (single 3-element structure to one lane)
814 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
815 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
816 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
817 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
818 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
819 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
821 let DecoderMethod = "DecodeVLD3LN";
824 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
825 let Inst{7-5} = lane{2-0};
827 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
828 let Inst{7-6} = lane{1-0};
830 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
831 let Inst{7} = lane{0};
834 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
835 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
836 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
838 // ...with double-spaced registers:
839 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
840 let Inst{7-6} = lane{1-0};
842 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
843 let Inst{7} = lane{0};
846 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
847 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
849 // ...with address register writeback:
850 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
851 : NLdStLn<1, 0b10, op11_8, op7_4,
852 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
853 (ins addrmode6:$Rn, am6offset:$Rm,
854 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
855 IIC_VLD3lnu, "vld3", Dt,
856 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
857 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
859 let DecoderMethod = "DecodeVLD3LN";
862 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
863 let Inst{7-5} = lane{2-0};
865 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
866 let Inst{7-6} = lane{1-0};
868 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
869 let Inst{7} = lane{0};
872 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
873 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
874 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
876 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
877 let Inst{7-6} = lane{1-0};
879 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
880 let Inst{7} = lane{0};
883 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
884 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
886 // VLD4LN : Vector Load (single 4-element structure to one lane)
887 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
888 : NLdStLn<1, 0b10, op11_8, op7_4,
889 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
890 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
891 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
892 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
893 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
896 let DecoderMethod = "DecodeVLD4LN";
899 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
900 let Inst{7-5} = lane{2-0};
902 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
903 let Inst{7-6} = lane{1-0};
905 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
906 let Inst{7} = lane{0};
910 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
911 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
912 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
914 // ...with double-spaced registers:
915 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
916 let Inst{7-6} = lane{1-0};
918 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
919 let Inst{7} = lane{0};
923 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
924 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
926 // ...with address register writeback:
927 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
928 : NLdStLn<1, 0b10, op11_8, op7_4,
929 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
930 (ins addrmode6:$Rn, am6offset:$Rm,
931 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
932 IIC_VLD4lnu, "vld4", Dt,
933 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
934 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
937 let DecoderMethod = "DecodeVLD4LN" ;
940 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
941 let Inst{7-5} = lane{2-0};
943 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
944 let Inst{7-6} = lane{1-0};
946 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
947 let Inst{7} = lane{0};
951 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
952 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
953 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
955 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
956 let Inst{7-6} = lane{1-0};
958 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
959 let Inst{7} = lane{0};
963 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
964 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
966 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
968 // VLD1DUP : Vector Load (single element to all lanes)
969 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
970 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
971 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
972 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
975 let DecoderMethod = "DecodeVLD1DupInstruction";
977 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
978 let Pattern = [(set QPR:$dst,
979 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
982 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
983 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
984 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
986 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
987 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
988 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
990 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
991 (VLD1DUPd32 addrmode6:$addr)>;
992 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
993 (VLD1DUPq32Pseudo addrmode6:$addr)>;
995 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
997 class VLD1QDUP<bits<4> op7_4, string Dt>
998 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
999 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1000 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1002 let Inst{4} = Rn{4};
1003 let DecoderMethod = "DecodeVLD1DupInstruction";
1006 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1007 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1008 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1010 // ...with address register writeback:
1011 class VLD1DUPWB<bits<4> op7_4, string Dt>
1012 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
1013 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1014 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1015 let Inst{4} = Rn{4};
1016 let DecoderMethod = "DecodeVLD1DupInstruction";
1018 class VLD1QDUPWB<bits<4> op7_4, string Dt>
1019 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1020 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1021 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1022 let Inst{4} = Rn{4};
1023 let DecoderMethod = "DecodeVLD1DupInstruction";
1026 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
1027 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
1028 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
1030 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
1031 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
1032 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
1034 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1035 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1036 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1038 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1039 class VLD2DUP<bits<4> op7_4, string Dt>
1040 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
1041 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1042 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1044 let Inst{4} = Rn{4};
1045 let DecoderMethod = "DecodeVLD2DupInstruction";
1048 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
1049 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
1050 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
1052 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1053 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1054 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1056 // ...with double-spaced registers (not used for codegen):
1057 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
1058 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
1059 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1061 // ...with address register writeback:
1062 class VLD2DUPWB<bits<4> op7_4, string Dt>
1063 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1064 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1065 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1066 let Inst{4} = Rn{4};
1067 let DecoderMethod = "DecodeVLD2DupInstruction";
1070 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1071 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1072 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1074 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1075 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1076 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1078 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1079 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1080 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1082 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1083 class VLD3DUP<bits<4> op7_4, string Dt>
1084 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1085 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1086 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1089 let DecoderMethod = "DecodeVLD3DupInstruction";
1092 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1093 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1094 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1096 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1097 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1098 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1100 // ...with double-spaced registers (not used for codegen):
1101 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1102 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1103 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1105 // ...with address register writeback:
1106 class VLD3DUPWB<bits<4> op7_4, string Dt>
1107 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1108 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1109 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1110 "$Rn.addr = $wb", []> {
1112 let DecoderMethod = "DecodeVLD3DupInstruction";
1115 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1116 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1117 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1119 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1120 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1121 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1123 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1124 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1125 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1127 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1128 class VLD4DUP<bits<4> op7_4, string Dt>
1129 : NLdSt<1, 0b10, 0b1111, op7_4,
1130 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1131 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1132 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1134 let Inst{4} = Rn{4};
1135 let DecoderMethod = "DecodeVLD4DupInstruction";
1138 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1139 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1140 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1142 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1143 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1144 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1146 // ...with double-spaced registers (not used for codegen):
1147 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1148 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1149 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1151 // ...with address register writeback:
1152 class VLD4DUPWB<bits<4> op7_4, string Dt>
1153 : NLdSt<1, 0b10, 0b1111, op7_4,
1154 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1155 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1156 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1157 "$Rn.addr = $wb", []> {
1158 let Inst{4} = Rn{4};
1159 let DecoderMethod = "DecodeVLD4DupInstruction";
1162 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1163 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1164 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1166 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1167 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1168 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1170 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1171 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1172 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1174 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1176 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1178 // Classes for VST* pseudo-instructions with multi-register operands.
1179 // These are expanded to real instructions after register allocation.
1180 class VSTQPseudo<InstrItinClass itin>
1181 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1182 class VSTQWBPseudo<InstrItinClass itin>
1183 : PseudoNLdSt<(outs GPR:$wb),
1184 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1185 "$addr.addr = $wb">;
1186 class VSTQQPseudo<InstrItinClass itin>
1187 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1188 class VSTQQWBPseudo<InstrItinClass itin>
1189 : PseudoNLdSt<(outs GPR:$wb),
1190 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1191 "$addr.addr = $wb">;
1192 class VSTQQQQPseudo<InstrItinClass itin>
1193 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1194 class VSTQQQQWBPseudo<InstrItinClass itin>
1195 : PseudoNLdSt<(outs GPR:$wb),
1196 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1197 "$addr.addr = $wb">;
1199 // VST1 : Vector Store (multiple single elements)
1200 class VST1D<bits<4> op7_4, string Dt>
1201 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1202 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1204 let Inst{4} = Rn{4};
1205 let DecoderMethod = "DecodeVSTInstruction";
1207 class VST1Q<bits<4> op7_4, string Dt>
1208 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1209 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1210 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1212 let Inst{5-4} = Rn{5-4};
1213 let DecoderMethod = "DecodeVSTInstruction";
1216 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1217 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1218 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1219 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1221 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1222 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1223 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1224 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1226 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1227 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1228 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1229 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1231 // ...with address register writeback:
1232 class VST1DWB<bits<4> op7_4, string Dt>
1233 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1234 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1235 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1236 let Inst{4} = Rn{4};
1237 let DecoderMethod = "DecodeVSTInstruction";
1239 class VST1QWB<bits<4> op7_4, string Dt>
1240 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1241 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1242 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1243 "$Rn.addr = $wb", []> {
1244 let Inst{5-4} = Rn{5-4};
1245 let DecoderMethod = "DecodeVSTInstruction";
1248 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1249 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1250 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1251 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1253 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1254 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1255 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1256 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1258 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1259 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1260 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1261 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1263 // ...with 3 registers
1264 class VST1D3<bits<4> op7_4, string Dt>
1265 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1266 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1267 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1269 let Inst{4} = Rn{4};
1270 let DecoderMethod = "DecodeVSTInstruction";
1272 class VST1D3WB<bits<4> op7_4, string Dt>
1273 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1274 (ins addrmode6:$Rn, am6offset:$Rm,
1275 DPR:$Vd, DPR:$src2, DPR:$src3),
1276 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1277 "$Rn.addr = $wb", []> {
1278 let Inst{4} = Rn{4};
1279 let DecoderMethod = "DecodeVSTInstruction";
1282 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1283 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1284 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1285 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1287 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1288 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1289 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1290 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1292 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1293 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1295 // ...with 4 registers
1296 class VST1D4<bits<4> op7_4, string Dt>
1297 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1298 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1299 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1302 let Inst{5-4} = Rn{5-4};
1303 let DecoderMethod = "DecodeVSTInstruction";
1305 class VST1D4WB<bits<4> op7_4, string Dt>
1306 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1307 (ins addrmode6:$Rn, am6offset:$Rm,
1308 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1309 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1310 "$Rn.addr = $wb", []> {
1311 let Inst{5-4} = Rn{5-4};
1312 let DecoderMethod = "DecodeVSTInstruction";
1315 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1316 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1317 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1318 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1320 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1321 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1322 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1323 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1325 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1326 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1328 // VST2 : Vector Store (multiple 2-element structures)
1329 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1330 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1331 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1332 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1334 let Inst{5-4} = Rn{5-4};
1335 let DecoderMethod = "DecodeVSTInstruction";
1337 class VST2Q<bits<4> op7_4, string Dt>
1338 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1339 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1340 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1343 let Inst{5-4} = Rn{5-4};
1344 let DecoderMethod = "DecodeVSTInstruction";
1347 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1348 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1349 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1351 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1352 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1353 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1355 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1356 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1357 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1359 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1360 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1361 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1363 // ...with address register writeback:
1364 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1365 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1366 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1367 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1368 "$Rn.addr = $wb", []> {
1369 let Inst{5-4} = Rn{5-4};
1370 let DecoderMethod = "DecodeVSTInstruction";
1372 class VST2QWB<bits<4> op7_4, string Dt>
1373 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1374 (ins addrmode6:$Rn, am6offset:$Rm,
1375 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1376 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1377 "$Rn.addr = $wb", []> {
1378 let Inst{5-4} = Rn{5-4};
1379 let DecoderMethod = "DecodeVSTInstruction";
1382 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1383 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1384 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1386 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1387 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1388 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1390 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1391 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1392 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1394 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1395 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1396 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1398 // ...with double-spaced registers
1399 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1400 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1401 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1402 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1403 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1404 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1406 // VST3 : Vector Store (multiple 3-element structures)
1407 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1408 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1409 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1410 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1412 let Inst{4} = Rn{4};
1413 let DecoderMethod = "DecodeVSTInstruction";
1416 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1417 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1418 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1420 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1421 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1422 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1424 // ...with address register writeback:
1425 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1426 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1427 (ins addrmode6:$Rn, am6offset:$Rm,
1428 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1429 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1430 "$Rn.addr = $wb", []> {
1431 let Inst{4} = Rn{4};
1432 let DecoderMethod = "DecodeVSTInstruction";
1435 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1436 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1437 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1439 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1440 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1441 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1443 // ...with double-spaced registers:
1444 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1445 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1446 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1447 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1448 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1449 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1451 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1452 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1453 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1455 // ...alternate versions to be allocated odd register numbers:
1456 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1457 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1458 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1460 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1461 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1462 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1464 // VST4 : Vector Store (multiple 4-element structures)
1465 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1466 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1467 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1468 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1471 let Inst{5-4} = Rn{5-4};
1472 let DecoderMethod = "DecodeVSTInstruction";
1475 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1476 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1477 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1479 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1480 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1481 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1483 // ...with address register writeback:
1484 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1485 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1486 (ins addrmode6:$Rn, am6offset:$Rm,
1487 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1488 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1489 "$Rn.addr = $wb", []> {
1490 let Inst{5-4} = Rn{5-4};
1491 let DecoderMethod = "DecodeVSTInstruction";
1494 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1495 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1496 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1498 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1499 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1500 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1502 // ...with double-spaced registers:
1503 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1504 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1505 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1506 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1507 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1508 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1510 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1511 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1512 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1514 // ...alternate versions to be allocated odd register numbers:
1515 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1516 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1517 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1519 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1520 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1521 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1523 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1525 // Classes for VST*LN pseudo-instructions with multi-register operands.
1526 // These are expanded to real instructions after register allocation.
1527 class VSTQLNPseudo<InstrItinClass itin>
1528 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1530 class VSTQLNWBPseudo<InstrItinClass itin>
1531 : PseudoNLdSt<(outs GPR:$wb),
1532 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1533 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1534 class VSTQQLNPseudo<InstrItinClass itin>
1535 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1537 class VSTQQLNWBPseudo<InstrItinClass itin>
1538 : PseudoNLdSt<(outs GPR:$wb),
1539 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1540 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1541 class VSTQQQQLNPseudo<InstrItinClass itin>
1542 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1544 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1545 : PseudoNLdSt<(outs GPR:$wb),
1546 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1547 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1549 // VST1LN : Vector Store (single element from one lane)
1550 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1551 PatFrag StoreOp, SDNode ExtractOp>
1552 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1553 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1554 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1555 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1557 let DecoderMethod = "DecodeVST1LN";
1559 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1560 PatFrag StoreOp, SDNode ExtractOp>
1561 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1562 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1563 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1564 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1566 let DecoderMethod = "DecodeVST1LN";
1568 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1569 : VSTQLNPseudo<IIC_VST1ln> {
1570 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1574 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1576 let Inst{7-5} = lane{2-0};
1578 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1580 let Inst{7-6} = lane{1-0};
1581 let Inst{4} = Rn{5};
1584 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1585 let Inst{7} = lane{0};
1586 let Inst{5-4} = Rn{5-4};
1589 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1590 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1591 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1593 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1594 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1595 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1596 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1598 // ...with address register writeback:
1599 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1600 PatFrag StoreOp, SDNode ExtractOp>
1601 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1602 (ins addrmode6:$Rn, am6offset:$Rm,
1603 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1604 "\\{$Vd[$lane]\\}, $Rn$Rm",
1606 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1607 addrmode6:$Rn, am6offset:$Rm))]> {
1608 let DecoderMethod = "DecodeVST1LN";
1610 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1611 : VSTQLNWBPseudo<IIC_VST1lnu> {
1612 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1613 addrmode6:$addr, am6offset:$offset))];
1616 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1618 let Inst{7-5} = lane{2-0};
1620 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1622 let Inst{7-6} = lane{1-0};
1623 let Inst{4} = Rn{5};
1625 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1627 let Inst{7} = lane{0};
1628 let Inst{5-4} = Rn{5-4};
1631 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1632 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1633 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1635 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1637 // VST2LN : Vector Store (single 2-element structure from one lane)
1638 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1639 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1640 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1641 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1644 let Inst{4} = Rn{4};
1645 let DecoderMethod = "DecodeVST2LN";
1648 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1649 let Inst{7-5} = lane{2-0};
1651 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1652 let Inst{7-6} = lane{1-0};
1654 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1655 let Inst{7} = lane{0};
1658 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1659 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1660 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1662 // ...with double-spaced registers:
1663 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1664 let Inst{7-6} = lane{1-0};
1665 let Inst{4} = Rn{4};
1667 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1668 let Inst{7} = lane{0};
1669 let Inst{4} = Rn{4};
1672 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1673 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1675 // ...with address register writeback:
1676 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1677 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1678 (ins addrmode6:$addr, am6offset:$offset,
1679 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1680 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1681 "$addr.addr = $wb", []> {
1682 let Inst{4} = Rn{4};
1683 let DecoderMethod = "DecodeVST2LN";
1686 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1687 let Inst{7-5} = lane{2-0};
1689 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1690 let Inst{7-6} = lane{1-0};
1692 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1693 let Inst{7} = lane{0};
1696 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1697 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1698 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1700 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1701 let Inst{7-6} = lane{1-0};
1703 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1704 let Inst{7} = lane{0};
1707 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1708 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1710 // VST3LN : Vector Store (single 3-element structure from one lane)
1711 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1712 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1713 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1714 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1715 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1717 let DecoderMethod = "DecodeVST3LN";
1720 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1721 let Inst{7-5} = lane{2-0};
1723 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1724 let Inst{7-6} = lane{1-0};
1726 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1727 let Inst{7} = lane{0};
1730 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1731 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1732 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1734 // ...with double-spaced registers:
1735 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1736 let Inst{7-6} = lane{1-0};
1738 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1739 let Inst{7} = lane{0};
1742 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1743 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1745 // ...with address register writeback:
1746 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1747 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1748 (ins addrmode6:$Rn, am6offset:$Rm,
1749 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1750 IIC_VST3lnu, "vst3", Dt,
1751 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1752 "$Rn.addr = $wb", []> {
1753 let DecoderMethod = "DecodeVST3LN";
1756 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1757 let Inst{7-5} = lane{2-0};
1759 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1760 let Inst{7-6} = lane{1-0};
1762 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1763 let Inst{7} = lane{0};
1766 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1767 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1768 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1770 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1771 let Inst{7-6} = lane{1-0};
1773 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1774 let Inst{7} = lane{0};
1777 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1778 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1780 // VST4LN : Vector Store (single 4-element structure from one lane)
1781 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1782 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1783 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1784 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1785 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1788 let Inst{4} = Rn{4};
1789 let DecoderMethod = "DecodeVST4LN";
1792 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1793 let Inst{7-5} = lane{2-0};
1795 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1796 let Inst{7-6} = lane{1-0};
1798 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1799 let Inst{7} = lane{0};
1800 let Inst{5} = Rn{5};
1803 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1804 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1805 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1807 // ...with double-spaced registers:
1808 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1809 let Inst{7-6} = lane{1-0};
1811 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1812 let Inst{7} = lane{0};
1813 let Inst{5} = Rn{5};
1816 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1817 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1819 // ...with address register writeback:
1820 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1821 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1822 (ins addrmode6:$Rn, am6offset:$Rm,
1823 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1824 IIC_VST4lnu, "vst4", Dt,
1825 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1826 "$Rn.addr = $wb", []> {
1827 let Inst{4} = Rn{4};
1828 let DecoderMethod = "DecodeVST4LN";
1831 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1832 let Inst{7-5} = lane{2-0};
1834 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1835 let Inst{7-6} = lane{1-0};
1837 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1838 let Inst{7} = lane{0};
1839 let Inst{5} = Rn{5};
1842 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1843 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1844 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1846 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1847 let Inst{7-6} = lane{1-0};
1849 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1850 let Inst{7} = lane{0};
1851 let Inst{5} = Rn{5};
1854 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1855 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1857 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1860 //===----------------------------------------------------------------------===//
1861 // NEON pattern fragments
1862 //===----------------------------------------------------------------------===//
1864 // Extract D sub-registers of Q registers.
1865 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1866 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1867 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1869 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1870 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1871 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1873 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1874 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1875 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1877 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1878 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1879 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1882 // Extract S sub-registers of Q/D registers.
1883 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1884 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1885 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1888 // Translate lane numbers from Q registers to D subregs.
1889 def SubReg_i8_lane : SDNodeXForm<imm, [{
1890 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1892 def SubReg_i16_lane : SDNodeXForm<imm, [{
1893 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1895 def SubReg_i32_lane : SDNodeXForm<imm, [{
1896 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1899 //===----------------------------------------------------------------------===//
1900 // Instruction Classes
1901 //===----------------------------------------------------------------------===//
1903 // Basic 2-register operations: double- and quad-register.
1904 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1905 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1906 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1907 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1908 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1909 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1910 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1911 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1912 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1913 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1914 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1915 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1917 // Basic 2-register intrinsics, both double- and quad-register.
1918 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1919 bits<2> op17_16, bits<5> op11_7, bit op4,
1920 InstrItinClass itin, string OpcodeStr, string Dt,
1921 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1922 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1923 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1924 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1925 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1926 bits<2> op17_16, bits<5> op11_7, bit op4,
1927 InstrItinClass itin, string OpcodeStr, string Dt,
1928 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1929 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1930 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1931 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1933 // Narrow 2-register operations.
1934 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1935 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1936 InstrItinClass itin, string OpcodeStr, string Dt,
1937 ValueType TyD, ValueType TyQ, SDNode OpNode>
1938 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1939 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1940 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1942 // Narrow 2-register intrinsics.
1943 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1944 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1945 InstrItinClass itin, string OpcodeStr, string Dt,
1946 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1947 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1948 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1949 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1951 // Long 2-register operations (currently only used for VMOVL).
1952 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1953 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1954 InstrItinClass itin, string OpcodeStr, string Dt,
1955 ValueType TyQ, ValueType TyD, SDNode OpNode>
1956 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1957 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1958 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1960 // Long 2-register intrinsics.
1961 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1962 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1963 InstrItinClass itin, string OpcodeStr, string Dt,
1964 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1965 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1966 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1967 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1969 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1970 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1971 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1972 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1973 OpcodeStr, Dt, "$Vd, $Vm",
1974 "$src1 = $Vd, $src2 = $Vm", []>;
1975 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1976 InstrItinClass itin, string OpcodeStr, string Dt>
1977 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1978 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1979 "$src1 = $Vd, $src2 = $Vm", []>;
1981 // Basic 3-register operations: double- and quad-register.
1982 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1983 InstrItinClass itin, string OpcodeStr, string Dt,
1984 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1985 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1986 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1987 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1988 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1989 let isCommutable = Commutable;
1991 // Same as N3VD but no data type.
1992 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1993 InstrItinClass itin, string OpcodeStr,
1994 ValueType ResTy, ValueType OpTy,
1995 SDNode OpNode, bit Commutable>
1996 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1997 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1998 OpcodeStr, "$Vd, $Vn, $Vm", "",
1999 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2000 let isCommutable = Commutable;
2003 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2004 InstrItinClass itin, string OpcodeStr, string Dt,
2005 ValueType Ty, SDNode ShOp>
2006 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2007 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2008 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2010 (Ty (ShOp (Ty DPR:$Vn),
2011 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2012 let isCommutable = 0;
2014 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2015 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2016 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2017 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2018 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2020 (Ty (ShOp (Ty DPR:$Vn),
2021 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2022 let isCommutable = 0;
2025 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2026 InstrItinClass itin, string OpcodeStr, string Dt,
2027 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2028 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2029 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2030 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2031 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2032 let isCommutable = Commutable;
2034 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2035 InstrItinClass itin, string OpcodeStr,
2036 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2037 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2038 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2039 OpcodeStr, "$Vd, $Vn, $Vm", "",
2040 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2041 let isCommutable = Commutable;
2043 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2044 InstrItinClass itin, string OpcodeStr, string Dt,
2045 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2046 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2047 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2048 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2049 [(set (ResTy QPR:$Vd),
2050 (ResTy (ShOp (ResTy QPR:$Vn),
2051 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2053 let isCommutable = 0;
2055 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2056 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2057 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2058 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2059 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2060 [(set (ResTy QPR:$Vd),
2061 (ResTy (ShOp (ResTy QPR:$Vn),
2062 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2064 let isCommutable = 0;
2067 // Basic 3-register intrinsics, both double- and quad-register.
2068 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2069 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2070 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2071 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2072 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2073 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2074 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2075 let isCommutable = Commutable;
2077 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2078 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2079 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2080 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2081 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2083 (Ty (IntOp (Ty DPR:$Vn),
2084 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2086 let isCommutable = 0;
2088 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2089 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2090 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2091 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2092 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2094 (Ty (IntOp (Ty DPR:$Vn),
2095 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2096 let isCommutable = 0;
2098 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2099 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2100 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2101 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2102 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2103 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2104 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2105 let isCommutable = 0;
2108 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2109 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2110 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2111 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2112 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2113 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2114 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2115 let isCommutable = Commutable;
2117 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2118 string OpcodeStr, string Dt,
2119 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2120 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2121 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2122 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2123 [(set (ResTy QPR:$Vd),
2124 (ResTy (IntOp (ResTy QPR:$Vn),
2125 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2127 let isCommutable = 0;
2129 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2130 string OpcodeStr, string Dt,
2131 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2132 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2133 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2134 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2135 [(set (ResTy QPR:$Vd),
2136 (ResTy (IntOp (ResTy QPR:$Vn),
2137 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2139 let isCommutable = 0;
2141 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2142 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2143 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2144 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2145 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2146 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2147 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2148 let isCommutable = 0;
2151 // Multiply-Add/Sub operations: double- and quad-register.
2152 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2153 InstrItinClass itin, string OpcodeStr, string Dt,
2154 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2155 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2156 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2157 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2158 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2159 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2161 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2162 string OpcodeStr, string Dt,
2163 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2164 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2166 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2168 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2170 (Ty (ShOp (Ty DPR:$src1),
2172 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2174 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2175 string OpcodeStr, string Dt,
2176 ValueType Ty, SDNode MulOp, SDNode ShOp>
2177 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2179 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2181 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2183 (Ty (ShOp (Ty DPR:$src1),
2185 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2188 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2189 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2190 SDPatternOperator MulOp, SDPatternOperator OpNode>
2191 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2192 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2193 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2194 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2195 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2196 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2197 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2198 SDPatternOperator MulOp, SDPatternOperator ShOp>
2199 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2201 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2203 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2204 [(set (ResTy QPR:$Vd),
2205 (ResTy (ShOp (ResTy QPR:$src1),
2206 (ResTy (MulOp QPR:$Vn,
2207 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2209 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2210 string OpcodeStr, string Dt,
2211 ValueType ResTy, ValueType OpTy,
2212 SDNode MulOp, SDNode ShOp>
2213 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2215 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2217 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2218 [(set (ResTy QPR:$Vd),
2219 (ResTy (ShOp (ResTy QPR:$src1),
2220 (ResTy (MulOp QPR:$Vn,
2221 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2224 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2225 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2226 InstrItinClass itin, string OpcodeStr, string Dt,
2227 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2228 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2229 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2230 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2231 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2232 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2233 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2234 InstrItinClass itin, string OpcodeStr, string Dt,
2235 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2236 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2237 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2238 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2239 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2240 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2242 // Neon 3-argument intrinsics, both double- and quad-register.
2243 // The destination register is also used as the first source operand register.
2244 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2245 InstrItinClass itin, string OpcodeStr, string Dt,
2246 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2247 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2248 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2249 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2250 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2251 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2252 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2253 InstrItinClass itin, string OpcodeStr, string Dt,
2254 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2255 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2256 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2257 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2258 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2259 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2261 // Long Multiply-Add/Sub operations.
2262 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2263 InstrItinClass itin, string OpcodeStr, string Dt,
2264 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2265 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2266 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2267 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2268 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2269 (TyQ (MulOp (TyD DPR:$Vn),
2270 (TyD DPR:$Vm)))))]>;
2271 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2272 InstrItinClass itin, string OpcodeStr, string Dt,
2273 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2274 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2275 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2277 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2279 (OpNode (TyQ QPR:$src1),
2280 (TyQ (MulOp (TyD DPR:$Vn),
2281 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2283 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2284 InstrItinClass itin, string OpcodeStr, string Dt,
2285 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2286 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2287 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2289 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2291 (OpNode (TyQ QPR:$src1),
2292 (TyQ (MulOp (TyD DPR:$Vn),
2293 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2296 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2297 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2298 InstrItinClass itin, string OpcodeStr, string Dt,
2299 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2301 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2302 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2303 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2304 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2305 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2306 (TyD DPR:$Vm)))))))]>;
2308 // Neon Long 3-argument intrinsic. The destination register is
2309 // a quad-register and is also used as the first source operand register.
2310 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2311 InstrItinClass itin, string OpcodeStr, string Dt,
2312 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2313 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2314 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2315 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2317 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2318 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2319 string OpcodeStr, string Dt,
2320 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2321 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2323 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2325 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2326 [(set (ResTy QPR:$Vd),
2327 (ResTy (IntOp (ResTy QPR:$src1),
2329 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2331 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2332 InstrItinClass itin, string OpcodeStr, string Dt,
2333 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2334 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2336 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2338 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2339 [(set (ResTy QPR:$Vd),
2340 (ResTy (IntOp (ResTy QPR:$src1),
2342 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2345 // Narrowing 3-register intrinsics.
2346 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2347 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2348 Intrinsic IntOp, bit Commutable>
2349 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2350 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2351 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2352 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2353 let isCommutable = Commutable;
2356 // Long 3-register operations.
2357 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2358 InstrItinClass itin, string OpcodeStr, string Dt,
2359 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2360 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2361 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2362 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2363 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2364 let isCommutable = Commutable;
2366 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2367 InstrItinClass itin, string OpcodeStr, string Dt,
2368 ValueType TyQ, ValueType TyD, SDNode OpNode>
2369 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2370 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2371 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2373 (TyQ (OpNode (TyD DPR:$Vn),
2374 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2375 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2376 InstrItinClass itin, string OpcodeStr, string Dt,
2377 ValueType TyQ, ValueType TyD, SDNode OpNode>
2378 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2379 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2380 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2382 (TyQ (OpNode (TyD DPR:$Vn),
2383 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2385 // Long 3-register operations with explicitly extended operands.
2386 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2387 InstrItinClass itin, string OpcodeStr, string Dt,
2388 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2390 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2391 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2392 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2393 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2394 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2395 let isCommutable = Commutable;
2398 // Long 3-register intrinsics with explicit extend (VABDL).
2399 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2400 InstrItinClass itin, string OpcodeStr, string Dt,
2401 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2403 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2404 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2405 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2406 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2407 (TyD DPR:$Vm))))))]> {
2408 let isCommutable = Commutable;
2411 // Long 3-register intrinsics.
2412 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2413 InstrItinClass itin, string OpcodeStr, string Dt,
2414 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2415 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2416 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2417 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2418 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2419 let isCommutable = Commutable;
2421 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2422 string OpcodeStr, string Dt,
2423 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2424 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2425 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2426 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2427 [(set (ResTy QPR:$Vd),
2428 (ResTy (IntOp (OpTy DPR:$Vn),
2429 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2431 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2432 InstrItinClass itin, string OpcodeStr, string Dt,
2433 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2434 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2435 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2436 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2437 [(set (ResTy QPR:$Vd),
2438 (ResTy (IntOp (OpTy DPR:$Vn),
2439 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2442 // Wide 3-register operations.
2443 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2444 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2445 SDNode OpNode, SDNode ExtOp, bit Commutable>
2446 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2447 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2448 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2449 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2450 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2451 let isCommutable = Commutable;
2454 // Pairwise long 2-register intrinsics, both double- and quad-register.
2455 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2456 bits<2> op17_16, bits<5> op11_7, bit op4,
2457 string OpcodeStr, string Dt,
2458 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2459 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2460 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2461 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2462 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2463 bits<2> op17_16, bits<5> op11_7, bit op4,
2464 string OpcodeStr, string Dt,
2465 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2466 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2467 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2468 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2470 // Pairwise long 2-register accumulate intrinsics,
2471 // both double- and quad-register.
2472 // The destination register is also used as the first source operand register.
2473 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2474 bits<2> op17_16, bits<5> op11_7, bit op4,
2475 string OpcodeStr, string Dt,
2476 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2477 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2478 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2479 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2480 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2481 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2482 bits<2> op17_16, bits<5> op11_7, bit op4,
2483 string OpcodeStr, string Dt,
2484 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2485 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2486 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2487 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2488 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2490 // Shift by immediate,
2491 // both double- and quad-register.
2492 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2493 Format f, InstrItinClass itin, Operand ImmTy,
2494 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2495 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2496 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2497 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2498 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2499 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2500 Format f, InstrItinClass itin, Operand ImmTy,
2501 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2502 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2503 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2504 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2505 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2507 // Long shift by immediate.
2508 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2509 string OpcodeStr, string Dt,
2510 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2511 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2512 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2513 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2514 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2515 (i32 imm:$SIMM))))]>;
2517 // Narrow shift by immediate.
2518 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2519 InstrItinClass itin, string OpcodeStr, string Dt,
2520 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2521 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2522 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2523 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2524 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2525 (i32 imm:$SIMM))))]>;
2527 // Shift right by immediate and accumulate,
2528 // both double- and quad-register.
2529 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2530 Operand ImmTy, string OpcodeStr, string Dt,
2531 ValueType Ty, SDNode ShOp>
2532 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2533 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2534 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2535 [(set DPR:$Vd, (Ty (add DPR:$src1,
2536 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2537 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2538 Operand ImmTy, string OpcodeStr, string Dt,
2539 ValueType Ty, SDNode ShOp>
2540 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2541 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2542 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2543 [(set QPR:$Vd, (Ty (add QPR:$src1,
2544 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2546 // Shift by immediate and insert,
2547 // both double- and quad-register.
2548 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2549 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2550 ValueType Ty,SDNode ShOp>
2551 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2552 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2553 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2554 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2555 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2556 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2557 ValueType Ty,SDNode ShOp>
2558 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2559 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2560 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2561 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2563 // Convert, with fractional bits immediate,
2564 // both double- and quad-register.
2565 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2566 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2568 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2569 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2570 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2571 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2572 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2573 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2575 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2576 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2577 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2578 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2580 //===----------------------------------------------------------------------===//
2582 //===----------------------------------------------------------------------===//
2584 // Abbreviations used in multiclass suffixes:
2585 // Q = quarter int (8 bit) elements
2586 // H = half int (16 bit) elements
2587 // S = single int (32 bit) elements
2588 // D = double int (64 bit) elements
2590 // Neon 2-register vector operations and intrinsics.
2592 // Neon 2-register comparisons.
2593 // source operand element sizes of 8, 16 and 32 bits:
2594 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2595 bits<5> op11_7, bit op4, string opc, string Dt,
2596 string asm, SDNode OpNode> {
2597 // 64-bit vector types.
2598 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2599 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2600 opc, !strconcat(Dt, "8"), asm, "",
2601 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2602 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2603 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2604 opc, !strconcat(Dt, "16"), asm, "",
2605 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2606 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2607 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2608 opc, !strconcat(Dt, "32"), asm, "",
2609 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2610 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2611 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2612 opc, "f32", asm, "",
2613 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2614 let Inst{10} = 1; // overwrite F = 1
2617 // 128-bit vector types.
2618 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2619 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2620 opc, !strconcat(Dt, "8"), asm, "",
2621 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2622 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2623 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2624 opc, !strconcat(Dt, "16"), asm, "",
2625 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2626 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2627 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2628 opc, !strconcat(Dt, "32"), asm, "",
2629 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2630 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2631 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2632 opc, "f32", asm, "",
2633 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2634 let Inst{10} = 1; // overwrite F = 1
2639 // Neon 2-register vector intrinsics,
2640 // element sizes of 8, 16 and 32 bits:
2641 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2642 bits<5> op11_7, bit op4,
2643 InstrItinClass itinD, InstrItinClass itinQ,
2644 string OpcodeStr, string Dt, Intrinsic IntOp> {
2645 // 64-bit vector types.
2646 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2647 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2648 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2649 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2650 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2651 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2653 // 128-bit vector types.
2654 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2655 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2656 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2657 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2658 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2659 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2663 // Neon Narrowing 2-register vector operations,
2664 // source operand element sizes of 16, 32 and 64 bits:
2665 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2666 bits<5> op11_7, bit op6, bit op4,
2667 InstrItinClass itin, string OpcodeStr, string Dt,
2669 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2670 itin, OpcodeStr, !strconcat(Dt, "16"),
2671 v8i8, v8i16, OpNode>;
2672 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2673 itin, OpcodeStr, !strconcat(Dt, "32"),
2674 v4i16, v4i32, OpNode>;
2675 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2676 itin, OpcodeStr, !strconcat(Dt, "64"),
2677 v2i32, v2i64, OpNode>;
2680 // Neon Narrowing 2-register vector intrinsics,
2681 // source operand element sizes of 16, 32 and 64 bits:
2682 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2683 bits<5> op11_7, bit op6, bit op4,
2684 InstrItinClass itin, string OpcodeStr, string Dt,
2686 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2687 itin, OpcodeStr, !strconcat(Dt, "16"),
2688 v8i8, v8i16, IntOp>;
2689 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2690 itin, OpcodeStr, !strconcat(Dt, "32"),
2691 v4i16, v4i32, IntOp>;
2692 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2693 itin, OpcodeStr, !strconcat(Dt, "64"),
2694 v2i32, v2i64, IntOp>;
2698 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2699 // source operand element sizes of 16, 32 and 64 bits:
2700 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2701 string OpcodeStr, string Dt, SDNode OpNode> {
2702 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2703 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2704 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2705 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2706 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2707 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2711 // Neon 3-register vector operations.
2713 // First with only element sizes of 8, 16 and 32 bits:
2714 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2715 InstrItinClass itinD16, InstrItinClass itinD32,
2716 InstrItinClass itinQ16, InstrItinClass itinQ32,
2717 string OpcodeStr, string Dt,
2718 SDNode OpNode, bit Commutable = 0> {
2719 // 64-bit vector types.
2720 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2721 OpcodeStr, !strconcat(Dt, "8"),
2722 v8i8, v8i8, OpNode, Commutable>;
2723 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2724 OpcodeStr, !strconcat(Dt, "16"),
2725 v4i16, v4i16, OpNode, Commutable>;
2726 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2727 OpcodeStr, !strconcat(Dt, "32"),
2728 v2i32, v2i32, OpNode, Commutable>;
2730 // 128-bit vector types.
2731 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2732 OpcodeStr, !strconcat(Dt, "8"),
2733 v16i8, v16i8, OpNode, Commutable>;
2734 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2735 OpcodeStr, !strconcat(Dt, "16"),
2736 v8i16, v8i16, OpNode, Commutable>;
2737 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2738 OpcodeStr, !strconcat(Dt, "32"),
2739 v4i32, v4i32, OpNode, Commutable>;
2742 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2743 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2745 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2747 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2748 v8i16, v4i16, ShOp>;
2749 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2750 v4i32, v2i32, ShOp>;
2753 // ....then also with element size 64 bits:
2754 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2755 InstrItinClass itinD, InstrItinClass itinQ,
2756 string OpcodeStr, string Dt,
2757 SDNode OpNode, bit Commutable = 0>
2758 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2759 OpcodeStr, Dt, OpNode, Commutable> {
2760 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2761 OpcodeStr, !strconcat(Dt, "64"),
2762 v1i64, v1i64, OpNode, Commutable>;
2763 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2764 OpcodeStr, !strconcat(Dt, "64"),
2765 v2i64, v2i64, OpNode, Commutable>;
2769 // Neon 3-register vector intrinsics.
2771 // First with only element sizes of 16 and 32 bits:
2772 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2773 InstrItinClass itinD16, InstrItinClass itinD32,
2774 InstrItinClass itinQ16, InstrItinClass itinQ32,
2775 string OpcodeStr, string Dt,
2776 Intrinsic IntOp, bit Commutable = 0> {
2777 // 64-bit vector types.
2778 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2779 OpcodeStr, !strconcat(Dt, "16"),
2780 v4i16, v4i16, IntOp, Commutable>;
2781 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2782 OpcodeStr, !strconcat(Dt, "32"),
2783 v2i32, v2i32, IntOp, Commutable>;
2785 // 128-bit vector types.
2786 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2787 OpcodeStr, !strconcat(Dt, "16"),
2788 v8i16, v8i16, IntOp, Commutable>;
2789 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2790 OpcodeStr, !strconcat(Dt, "32"),
2791 v4i32, v4i32, IntOp, Commutable>;
2793 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2794 InstrItinClass itinD16, InstrItinClass itinD32,
2795 InstrItinClass itinQ16, InstrItinClass itinQ32,
2796 string OpcodeStr, string Dt,
2798 // 64-bit vector types.
2799 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2800 OpcodeStr, !strconcat(Dt, "16"),
2801 v4i16, v4i16, IntOp>;
2802 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2803 OpcodeStr, !strconcat(Dt, "32"),
2804 v2i32, v2i32, IntOp>;
2806 // 128-bit vector types.
2807 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2808 OpcodeStr, !strconcat(Dt, "16"),
2809 v8i16, v8i16, IntOp>;
2810 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2811 OpcodeStr, !strconcat(Dt, "32"),
2812 v4i32, v4i32, IntOp>;
2815 multiclass N3VIntSL_HS<bits<4> op11_8,
2816 InstrItinClass itinD16, InstrItinClass itinD32,
2817 InstrItinClass itinQ16, InstrItinClass itinQ32,
2818 string OpcodeStr, string Dt, Intrinsic IntOp> {
2819 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2820 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2821 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2822 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2823 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2824 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2825 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2826 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2829 // ....then also with element size of 8 bits:
2830 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2831 InstrItinClass itinD16, InstrItinClass itinD32,
2832 InstrItinClass itinQ16, InstrItinClass itinQ32,
2833 string OpcodeStr, string Dt,
2834 Intrinsic IntOp, bit Commutable = 0>
2835 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2836 OpcodeStr, Dt, IntOp, Commutable> {
2837 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2838 OpcodeStr, !strconcat(Dt, "8"),
2839 v8i8, v8i8, IntOp, Commutable>;
2840 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2841 OpcodeStr, !strconcat(Dt, "8"),
2842 v16i8, v16i8, IntOp, Commutable>;
2844 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2845 InstrItinClass itinD16, InstrItinClass itinD32,
2846 InstrItinClass itinQ16, InstrItinClass itinQ32,
2847 string OpcodeStr, string Dt,
2849 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2850 OpcodeStr, Dt, IntOp> {
2851 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2852 OpcodeStr, !strconcat(Dt, "8"),
2854 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2855 OpcodeStr, !strconcat(Dt, "8"),
2856 v16i8, v16i8, IntOp>;
2860 // ....then also with element size of 64 bits:
2861 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2862 InstrItinClass itinD16, InstrItinClass itinD32,
2863 InstrItinClass itinQ16, InstrItinClass itinQ32,
2864 string OpcodeStr, string Dt,
2865 Intrinsic IntOp, bit Commutable = 0>
2866 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2867 OpcodeStr, Dt, IntOp, Commutable> {
2868 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2869 OpcodeStr, !strconcat(Dt, "64"),
2870 v1i64, v1i64, IntOp, Commutable>;
2871 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2872 OpcodeStr, !strconcat(Dt, "64"),
2873 v2i64, v2i64, IntOp, Commutable>;
2875 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2876 InstrItinClass itinD16, InstrItinClass itinD32,
2877 InstrItinClass itinQ16, InstrItinClass itinQ32,
2878 string OpcodeStr, string Dt,
2880 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2881 OpcodeStr, Dt, IntOp> {
2882 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2883 OpcodeStr, !strconcat(Dt, "64"),
2884 v1i64, v1i64, IntOp>;
2885 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2886 OpcodeStr, !strconcat(Dt, "64"),
2887 v2i64, v2i64, IntOp>;
2890 // Neon Narrowing 3-register vector intrinsics,
2891 // source operand element sizes of 16, 32 and 64 bits:
2892 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2893 string OpcodeStr, string Dt,
2894 Intrinsic IntOp, bit Commutable = 0> {
2895 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2896 OpcodeStr, !strconcat(Dt, "16"),
2897 v8i8, v8i16, IntOp, Commutable>;
2898 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2899 OpcodeStr, !strconcat(Dt, "32"),
2900 v4i16, v4i32, IntOp, Commutable>;
2901 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2902 OpcodeStr, !strconcat(Dt, "64"),
2903 v2i32, v2i64, IntOp, Commutable>;
2907 // Neon Long 3-register vector operations.
2909 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2910 InstrItinClass itin16, InstrItinClass itin32,
2911 string OpcodeStr, string Dt,
2912 SDNode OpNode, bit Commutable = 0> {
2913 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2914 OpcodeStr, !strconcat(Dt, "8"),
2915 v8i16, v8i8, OpNode, Commutable>;
2916 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2917 OpcodeStr, !strconcat(Dt, "16"),
2918 v4i32, v4i16, OpNode, Commutable>;
2919 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2920 OpcodeStr, !strconcat(Dt, "32"),
2921 v2i64, v2i32, OpNode, Commutable>;
2924 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2925 InstrItinClass itin, string OpcodeStr, string Dt,
2927 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2928 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2929 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2930 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2933 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2934 InstrItinClass itin16, InstrItinClass itin32,
2935 string OpcodeStr, string Dt,
2936 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2937 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2938 OpcodeStr, !strconcat(Dt, "8"),
2939 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2940 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2941 OpcodeStr, !strconcat(Dt, "16"),
2942 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2943 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2944 OpcodeStr, !strconcat(Dt, "32"),
2945 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2948 // Neon Long 3-register vector intrinsics.
2950 // First with only element sizes of 16 and 32 bits:
2951 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2952 InstrItinClass itin16, InstrItinClass itin32,
2953 string OpcodeStr, string Dt,
2954 Intrinsic IntOp, bit Commutable = 0> {
2955 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2956 OpcodeStr, !strconcat(Dt, "16"),
2957 v4i32, v4i16, IntOp, Commutable>;
2958 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2959 OpcodeStr, !strconcat(Dt, "32"),
2960 v2i64, v2i32, IntOp, Commutable>;
2963 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2964 InstrItinClass itin, string OpcodeStr, string Dt,
2966 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2967 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2968 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2969 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2972 // ....then also with element size of 8 bits:
2973 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2974 InstrItinClass itin16, InstrItinClass itin32,
2975 string OpcodeStr, string Dt,
2976 Intrinsic IntOp, bit Commutable = 0>
2977 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2978 IntOp, Commutable> {
2979 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2980 OpcodeStr, !strconcat(Dt, "8"),
2981 v8i16, v8i8, IntOp, Commutable>;
2984 // ....with explicit extend (VABDL).
2985 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2986 InstrItinClass itin, string OpcodeStr, string Dt,
2987 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2988 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2989 OpcodeStr, !strconcat(Dt, "8"),
2990 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2991 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2992 OpcodeStr, !strconcat(Dt, "16"),
2993 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2994 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2995 OpcodeStr, !strconcat(Dt, "32"),
2996 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3000 // Neon Wide 3-register vector intrinsics,
3001 // source operand element sizes of 8, 16 and 32 bits:
3002 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3003 string OpcodeStr, string Dt,
3004 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3005 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3006 OpcodeStr, !strconcat(Dt, "8"),
3007 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3008 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3009 OpcodeStr, !strconcat(Dt, "16"),
3010 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3011 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3012 OpcodeStr, !strconcat(Dt, "32"),
3013 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3017 // Neon Multiply-Op vector operations,
3018 // element sizes of 8, 16 and 32 bits:
3019 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3020 InstrItinClass itinD16, InstrItinClass itinD32,
3021 InstrItinClass itinQ16, InstrItinClass itinQ32,
3022 string OpcodeStr, string Dt, SDNode OpNode> {
3023 // 64-bit vector types.
3024 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3025 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3026 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3027 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3028 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3029 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3031 // 128-bit vector types.
3032 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3033 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3034 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3035 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3036 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3037 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3040 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3041 InstrItinClass itinD16, InstrItinClass itinD32,
3042 InstrItinClass itinQ16, InstrItinClass itinQ32,
3043 string OpcodeStr, string Dt, SDNode ShOp> {
3044 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3045 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3046 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3047 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3048 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3049 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3051 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3052 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3056 // Neon Intrinsic-Op vector operations,
3057 // element sizes of 8, 16 and 32 bits:
3058 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3059 InstrItinClass itinD, InstrItinClass itinQ,
3060 string OpcodeStr, string Dt, Intrinsic IntOp,
3062 // 64-bit vector types.
3063 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3064 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3065 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3066 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3067 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3068 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3070 // 128-bit vector types.
3071 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3072 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3073 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3074 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3075 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3076 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3079 // Neon 3-argument intrinsics,
3080 // element sizes of 8, 16 and 32 bits:
3081 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3082 InstrItinClass itinD, InstrItinClass itinQ,
3083 string OpcodeStr, string Dt, Intrinsic IntOp> {
3084 // 64-bit vector types.
3085 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3086 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3087 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3088 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3089 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3090 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3092 // 128-bit vector types.
3093 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3094 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3095 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3096 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3097 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3098 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3102 // Neon Long Multiply-Op vector operations,
3103 // element sizes of 8, 16 and 32 bits:
3104 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3105 InstrItinClass itin16, InstrItinClass itin32,
3106 string OpcodeStr, string Dt, SDNode MulOp,
3108 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3109 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3110 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3111 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3112 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3113 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3116 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3117 string Dt, SDNode MulOp, SDNode OpNode> {
3118 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3119 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3120 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3121 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3125 // Neon Long 3-argument intrinsics.
3127 // First with only element sizes of 16 and 32 bits:
3128 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3129 InstrItinClass itin16, InstrItinClass itin32,
3130 string OpcodeStr, string Dt, Intrinsic IntOp> {
3131 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3132 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3133 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3134 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3137 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3138 string OpcodeStr, string Dt, Intrinsic IntOp> {
3139 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3140 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3141 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3142 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3145 // ....then also with element size of 8 bits:
3146 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3147 InstrItinClass itin16, InstrItinClass itin32,
3148 string OpcodeStr, string Dt, Intrinsic IntOp>
3149 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3150 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3151 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3154 // ....with explicit extend (VABAL).
3155 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3156 InstrItinClass itin, string OpcodeStr, string Dt,
3157 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3158 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3159 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3160 IntOp, ExtOp, OpNode>;
3161 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3162 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3163 IntOp, ExtOp, OpNode>;
3164 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3165 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3166 IntOp, ExtOp, OpNode>;
3170 // Neon Pairwise long 2-register intrinsics,
3171 // element sizes of 8, 16 and 32 bits:
3172 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3173 bits<5> op11_7, bit op4,
3174 string OpcodeStr, string Dt, Intrinsic IntOp> {
3175 // 64-bit vector types.
3176 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3177 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3178 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3179 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3180 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3181 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3183 // 128-bit vector types.
3184 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3185 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3186 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3187 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3188 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3189 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3193 // Neon Pairwise long 2-register accumulate intrinsics,
3194 // element sizes of 8, 16 and 32 bits:
3195 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3196 bits<5> op11_7, bit op4,
3197 string OpcodeStr, string Dt, Intrinsic IntOp> {
3198 // 64-bit vector types.
3199 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3200 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3201 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3202 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3203 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3204 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3206 // 128-bit vector types.
3207 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3208 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3209 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3210 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3211 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3212 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3216 // Neon 2-register vector shift by immediate,
3217 // with f of either N2RegVShLFrm or N2RegVShRFrm
3218 // element sizes of 8, 16, 32 and 64 bits:
3219 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3220 InstrItinClass itin, string OpcodeStr, string Dt,
3222 // 64-bit vector types.
3223 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3224 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3225 let Inst{21-19} = 0b001; // imm6 = 001xxx
3227 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3228 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3229 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3231 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3232 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3233 let Inst{21} = 0b1; // imm6 = 1xxxxx
3235 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3236 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3239 // 128-bit vector types.
3240 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3241 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3242 let Inst{21-19} = 0b001; // imm6 = 001xxx
3244 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3245 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3246 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3248 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3249 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3250 let Inst{21} = 0b1; // imm6 = 1xxxxx
3252 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3253 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3256 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3257 InstrItinClass itin, string OpcodeStr, string Dt,
3259 // 64-bit vector types.
3260 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3261 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3262 let Inst{21-19} = 0b001; // imm6 = 001xxx
3264 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3265 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3266 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3268 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3269 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3270 let Inst{21} = 0b1; // imm6 = 1xxxxx
3272 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3273 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3276 // 128-bit vector types.
3277 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3278 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3279 let Inst{21-19} = 0b001; // imm6 = 001xxx
3281 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3282 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3283 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3285 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3286 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3287 let Inst{21} = 0b1; // imm6 = 1xxxxx
3289 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3290 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3294 // Neon Shift-Accumulate vector operations,
3295 // element sizes of 8, 16, 32 and 64 bits:
3296 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3297 string OpcodeStr, string Dt, SDNode ShOp> {
3298 // 64-bit vector types.
3299 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3300 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3301 let Inst{21-19} = 0b001; // imm6 = 001xxx
3303 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3304 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3305 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3307 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3308 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3309 let Inst{21} = 0b1; // imm6 = 1xxxxx
3311 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3312 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3315 // 128-bit vector types.
3316 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3317 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3318 let Inst{21-19} = 0b001; // imm6 = 001xxx
3320 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3321 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3322 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3324 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3325 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3326 let Inst{21} = 0b1; // imm6 = 1xxxxx
3328 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3329 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3333 // Neon Shift-Insert vector operations,
3334 // with f of either N2RegVShLFrm or N2RegVShRFrm
3335 // element sizes of 8, 16, 32 and 64 bits:
3336 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3338 // 64-bit vector types.
3339 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3340 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3341 let Inst{21-19} = 0b001; // imm6 = 001xxx
3343 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3344 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3345 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3347 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3348 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3349 let Inst{21} = 0b1; // imm6 = 1xxxxx
3351 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3352 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3355 // 128-bit vector types.
3356 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3357 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3358 let Inst{21-19} = 0b001; // imm6 = 001xxx
3360 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3361 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3362 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3364 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3365 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3366 let Inst{21} = 0b1; // imm6 = 1xxxxx
3368 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3369 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3372 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3374 // 64-bit vector types.
3375 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3376 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3377 let Inst{21-19} = 0b001; // imm6 = 001xxx
3379 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3380 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3381 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3383 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3384 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3385 let Inst{21} = 0b1; // imm6 = 1xxxxx
3387 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3388 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3391 // 128-bit vector types.
3392 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3393 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3394 let Inst{21-19} = 0b001; // imm6 = 001xxx
3396 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3397 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3398 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3400 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3401 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3402 let Inst{21} = 0b1; // imm6 = 1xxxxx
3404 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3405 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3409 // Neon Shift Long operations,
3410 // element sizes of 8, 16, 32 bits:
3411 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3412 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3413 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3414 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3415 let Inst{21-19} = 0b001; // imm6 = 001xxx
3417 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3418 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3419 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3421 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3422 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3423 let Inst{21} = 0b1; // imm6 = 1xxxxx
3427 // Neon Shift Narrow operations,
3428 // element sizes of 16, 32, 64 bits:
3429 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3430 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3432 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3433 OpcodeStr, !strconcat(Dt, "16"),
3434 v8i8, v8i16, shr_imm8, OpNode> {
3435 let Inst{21-19} = 0b001; // imm6 = 001xxx
3437 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3438 OpcodeStr, !strconcat(Dt, "32"),
3439 v4i16, v4i32, shr_imm16, OpNode> {
3440 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3442 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3443 OpcodeStr, !strconcat(Dt, "64"),
3444 v2i32, v2i64, shr_imm32, OpNode> {
3445 let Inst{21} = 0b1; // imm6 = 1xxxxx
3449 //===----------------------------------------------------------------------===//
3450 // Instruction Definitions.
3451 //===----------------------------------------------------------------------===//
3453 // Vector Add Operations.
3455 // VADD : Vector Add (integer and floating-point)
3456 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3458 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3459 v2f32, v2f32, fadd, 1>;
3460 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3461 v4f32, v4f32, fadd, 1>;
3462 // VADDL : Vector Add Long (Q = D + D)
3463 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3464 "vaddl", "s", add, sext, 1>;
3465 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3466 "vaddl", "u", add, zext, 1>;
3467 // VADDW : Vector Add Wide (Q = Q + D)
3468 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3469 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3470 // VHADD : Vector Halving Add
3471 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3472 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3473 "vhadd", "s", int_arm_neon_vhadds, 1>;
3474 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3475 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3476 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3477 // VRHADD : Vector Rounding Halving Add
3478 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3479 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3480 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3481 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3482 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3483 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3484 // VQADD : Vector Saturating Add
3485 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3486 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3487 "vqadd", "s", int_arm_neon_vqadds, 1>;
3488 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3489 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3490 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3491 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3492 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3493 int_arm_neon_vaddhn, 1>;
3494 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3495 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3496 int_arm_neon_vraddhn, 1>;
3498 // Vector Multiply Operations.
3500 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3501 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3502 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3503 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3504 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3505 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3506 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3507 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3508 v2f32, v2f32, fmul, 1>;
3509 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3510 v4f32, v4f32, fmul, 1>;
3511 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3512 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3513 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3516 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3517 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3518 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3519 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3520 (DSubReg_i16_reg imm:$lane))),
3521 (SubReg_i16_lane imm:$lane)))>;
3522 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3523 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3524 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3525 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3526 (DSubReg_i32_reg imm:$lane))),
3527 (SubReg_i32_lane imm:$lane)))>;
3528 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3529 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3530 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3531 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3532 (DSubReg_i32_reg imm:$lane))),
3533 (SubReg_i32_lane imm:$lane)))>;
3535 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3536 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3537 IIC_VMULi16Q, IIC_VMULi32Q,
3538 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3539 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3540 IIC_VMULi16Q, IIC_VMULi32Q,
3541 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3542 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3543 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3545 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3546 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3547 (DSubReg_i16_reg imm:$lane))),
3548 (SubReg_i16_lane imm:$lane)))>;
3549 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3550 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3552 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3553 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3554 (DSubReg_i32_reg imm:$lane))),
3555 (SubReg_i32_lane imm:$lane)))>;
3557 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3558 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3559 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3560 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3561 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3562 IIC_VMULi16Q, IIC_VMULi32Q,
3563 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3564 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3565 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3567 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3568 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3569 (DSubReg_i16_reg imm:$lane))),
3570 (SubReg_i16_lane imm:$lane)))>;
3571 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3572 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3574 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3575 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3576 (DSubReg_i32_reg imm:$lane))),
3577 (SubReg_i32_lane imm:$lane)))>;
3579 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3580 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3581 "vmull", "s", NEONvmulls, 1>;
3582 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3583 "vmull", "u", NEONvmullu, 1>;
3584 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3585 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3586 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3587 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3589 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3590 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3591 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3592 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3593 "vqdmull", "s", int_arm_neon_vqdmull>;
3595 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3597 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3598 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3599 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3600 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3601 v2f32, fmul_su, fadd_mlx>,
3602 Requires<[HasNEON, UseFPVMLx]>;
3603 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3604 v4f32, fmul_su, fadd_mlx>,
3605 Requires<[HasNEON, UseFPVMLx]>;
3606 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3607 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3608 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3609 v2f32, fmul_su, fadd_mlx>,
3610 Requires<[HasNEON, UseFPVMLx]>;
3611 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3612 v4f32, v2f32, fmul_su, fadd_mlx>,
3613 Requires<[HasNEON, UseFPVMLx]>;
3615 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3616 (mul (v8i16 QPR:$src2),
3617 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3618 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3619 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3620 (DSubReg_i16_reg imm:$lane))),
3621 (SubReg_i16_lane imm:$lane)))>;
3623 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3624 (mul (v4i32 QPR:$src2),
3625 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3626 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3627 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3628 (DSubReg_i32_reg imm:$lane))),
3629 (SubReg_i32_lane imm:$lane)))>;
3631 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3632 (fmul_su (v4f32 QPR:$src2),
3633 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3634 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3636 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3637 (DSubReg_i32_reg imm:$lane))),
3638 (SubReg_i32_lane imm:$lane)))>,
3639 Requires<[HasNEON, UseFPVMLx]>;
3641 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3642 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3643 "vmlal", "s", NEONvmulls, add>;
3644 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3645 "vmlal", "u", NEONvmullu, add>;
3647 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3648 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3650 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3651 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3652 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3653 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3655 // VMLS : Vector Multiply Subtract (integer and floating-point)
3656 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3657 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3658 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3659 v2f32, fmul_su, fsub_mlx>,
3660 Requires<[HasNEON, UseFPVMLx]>;
3661 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3662 v4f32, fmul_su, fsub_mlx>,
3663 Requires<[HasNEON, UseFPVMLx]>;
3664 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3665 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3666 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3667 v2f32, fmul_su, fsub_mlx>,
3668 Requires<[HasNEON, UseFPVMLx]>;
3669 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3670 v4f32, v2f32, fmul_su, fsub_mlx>,
3671 Requires<[HasNEON, UseFPVMLx]>;
3673 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3674 (mul (v8i16 QPR:$src2),
3675 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3676 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3677 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3678 (DSubReg_i16_reg imm:$lane))),
3679 (SubReg_i16_lane imm:$lane)))>;
3681 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3682 (mul (v4i32 QPR:$src2),
3683 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3684 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3685 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3686 (DSubReg_i32_reg imm:$lane))),
3687 (SubReg_i32_lane imm:$lane)))>;
3689 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3690 (fmul_su (v4f32 QPR:$src2),
3691 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3692 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3693 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3694 (DSubReg_i32_reg imm:$lane))),
3695 (SubReg_i32_lane imm:$lane)))>,
3696 Requires<[HasNEON, UseFPVMLx]>;
3698 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3699 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3700 "vmlsl", "s", NEONvmulls, sub>;
3701 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3702 "vmlsl", "u", NEONvmullu, sub>;
3704 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3705 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3707 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3708 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3709 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3710 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3712 // Vector Subtract Operations.
3714 // VSUB : Vector Subtract (integer and floating-point)
3715 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3716 "vsub", "i", sub, 0>;
3717 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3718 v2f32, v2f32, fsub, 0>;
3719 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3720 v4f32, v4f32, fsub, 0>;
3721 // VSUBL : Vector Subtract Long (Q = D - D)
3722 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3723 "vsubl", "s", sub, sext, 0>;
3724 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3725 "vsubl", "u", sub, zext, 0>;
3726 // VSUBW : Vector Subtract Wide (Q = Q - D)
3727 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3728 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3729 // VHSUB : Vector Halving Subtract
3730 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3731 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3732 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3733 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3734 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3735 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3736 // VQSUB : Vector Saturing Subtract
3737 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3738 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3739 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3740 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3741 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3742 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3743 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3744 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3745 int_arm_neon_vsubhn, 0>;
3746 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3747 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3748 int_arm_neon_vrsubhn, 0>;
3750 // Vector Comparisons.
3752 // VCEQ : Vector Compare Equal
3753 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3754 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3755 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3757 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3760 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3761 "$Vd, $Vm, #0", NEONvceqz>;
3763 // VCGE : Vector Compare Greater Than or Equal
3764 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3765 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3766 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3767 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3768 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3770 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3773 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3774 "$Vd, $Vm, #0", NEONvcgez>;
3775 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3776 "$Vd, $Vm, #0", NEONvclez>;
3778 // VCGT : Vector Compare Greater Than
3779 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3780 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3781 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3782 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3783 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3785 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3788 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3789 "$Vd, $Vm, #0", NEONvcgtz>;
3790 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3791 "$Vd, $Vm, #0", NEONvcltz>;
3793 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3794 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3795 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3796 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3797 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3798 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3799 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3800 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3801 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3802 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3803 // VTST : Vector Test Bits
3804 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3805 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3807 // Vector Bitwise Operations.
3809 def vnotd : PatFrag<(ops node:$in),
3810 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3811 def vnotq : PatFrag<(ops node:$in),
3812 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3815 // VAND : Vector Bitwise AND
3816 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3817 v2i32, v2i32, and, 1>;
3818 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3819 v4i32, v4i32, and, 1>;
3821 // VEOR : Vector Bitwise Exclusive OR
3822 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3823 v2i32, v2i32, xor, 1>;
3824 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3825 v4i32, v4i32, xor, 1>;
3827 // VORR : Vector Bitwise OR
3828 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3829 v2i32, v2i32, or, 1>;
3830 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3831 v4i32, v4i32, or, 1>;
3833 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3834 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3836 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3838 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3839 let Inst{9} = SIMM{9};
3842 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3843 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3845 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3847 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3848 let Inst{10-9} = SIMM{10-9};
3851 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3852 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3854 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3856 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3857 let Inst{9} = SIMM{9};
3860 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3861 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3863 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3865 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3866 let Inst{10-9} = SIMM{10-9};
3870 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3871 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3872 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3873 "vbic", "$Vd, $Vn, $Vm", "",
3874 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3875 (vnotd DPR:$Vm))))]>;
3876 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3877 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3878 "vbic", "$Vd, $Vn, $Vm", "",
3879 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3880 (vnotq QPR:$Vm))))]>;
3882 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3883 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3885 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3887 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3888 let Inst{9} = SIMM{9};
3891 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3892 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3894 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3896 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3897 let Inst{10-9} = SIMM{10-9};
3900 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3901 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3903 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3905 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3906 let Inst{9} = SIMM{9};
3909 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3910 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3912 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3914 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3915 let Inst{10-9} = SIMM{10-9};
3918 // VORN : Vector Bitwise OR NOT
3919 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3920 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3921 "vorn", "$Vd, $Vn, $Vm", "",
3922 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3923 (vnotd DPR:$Vm))))]>;
3924 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3925 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3926 "vorn", "$Vd, $Vn, $Vm", "",
3927 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3928 (vnotq QPR:$Vm))))]>;
3930 // VMVN : Vector Bitwise NOT (Immediate)
3932 let isReMaterializable = 1 in {
3934 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3935 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3936 "vmvn", "i16", "$Vd, $SIMM", "",
3937 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3938 let Inst{9} = SIMM{9};
3941 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3942 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3943 "vmvn", "i16", "$Vd, $SIMM", "",
3944 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3945 let Inst{9} = SIMM{9};
3948 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3949 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3950 "vmvn", "i32", "$Vd, $SIMM", "",
3951 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3952 let Inst{11-8} = SIMM{11-8};
3955 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3956 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3957 "vmvn", "i32", "$Vd, $SIMM", "",
3958 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3959 let Inst{11-8} = SIMM{11-8};
3963 // VMVN : Vector Bitwise NOT
3964 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3965 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3966 "vmvn", "$Vd, $Vm", "",
3967 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3968 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3969 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3970 "vmvn", "$Vd, $Vm", "",
3971 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3972 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3973 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3975 // VBSL : Vector Bitwise Select
3976 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3977 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3978 N3RegFrm, IIC_VCNTiD,
3979 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3981 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3983 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3984 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3985 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3987 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3988 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3989 N3RegFrm, IIC_VCNTiQ,
3990 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3992 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3994 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3995 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3996 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3998 // VBIF : Vector Bitwise Insert if False
3999 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4000 // FIXME: This instruction's encoding MAY NOT BE correct.
4001 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4002 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4003 N3RegFrm, IIC_VBINiD,
4004 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4006 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4007 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4008 N3RegFrm, IIC_VBINiQ,
4009 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4012 // VBIT : Vector Bitwise Insert if True
4013 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4014 // FIXME: This instruction's encoding MAY NOT BE correct.
4015 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4016 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4017 N3RegFrm, IIC_VBINiD,
4018 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4020 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4021 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4022 N3RegFrm, IIC_VBINiQ,
4023 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4026 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4027 // for equivalent operations with different register constraints; it just
4030 // Vector Absolute Differences.
4032 // VABD : Vector Absolute Difference
4033 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4034 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4035 "vabd", "s", int_arm_neon_vabds, 1>;
4036 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4037 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4038 "vabd", "u", int_arm_neon_vabdu, 1>;
4039 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4040 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4041 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4042 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4044 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4045 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4046 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4047 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4048 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4050 // VABA : Vector Absolute Difference and Accumulate
4051 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4052 "vaba", "s", int_arm_neon_vabds, add>;
4053 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4054 "vaba", "u", int_arm_neon_vabdu, add>;
4056 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4057 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4058 "vabal", "s", int_arm_neon_vabds, zext, add>;
4059 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4060 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4062 // Vector Maximum and Minimum.
4064 // VMAX : Vector Maximum
4065 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4066 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4067 "vmax", "s", int_arm_neon_vmaxs, 1>;
4068 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4069 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4070 "vmax", "u", int_arm_neon_vmaxu, 1>;
4071 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4073 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4074 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4076 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4078 // VMIN : Vector Minimum
4079 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4080 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4081 "vmin", "s", int_arm_neon_vmins, 1>;
4082 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4083 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4084 "vmin", "u", int_arm_neon_vminu, 1>;
4085 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4087 v2f32, v2f32, int_arm_neon_vmins, 1>;
4088 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4090 v4f32, v4f32, int_arm_neon_vmins, 1>;
4092 // Vector Pairwise Operations.
4094 // VPADD : Vector Pairwise Add
4095 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4097 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4098 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4100 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4101 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4103 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4104 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4105 IIC_VPBIND, "vpadd", "f32",
4106 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4108 // VPADDL : Vector Pairwise Add Long
4109 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4110 int_arm_neon_vpaddls>;
4111 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4112 int_arm_neon_vpaddlu>;
4114 // VPADAL : Vector Pairwise Add and Accumulate Long
4115 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4116 int_arm_neon_vpadals>;
4117 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4118 int_arm_neon_vpadalu>;
4120 // VPMAX : Vector Pairwise Maximum
4121 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4122 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4123 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4124 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4125 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4126 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4127 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4128 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4129 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4130 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4131 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4132 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4133 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4134 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4136 // VPMIN : Vector Pairwise Minimum
4137 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4138 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4139 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4140 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4141 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4142 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4143 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4144 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4145 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4146 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4147 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4148 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4149 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4150 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4152 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4154 // VRECPE : Vector Reciprocal Estimate
4155 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4156 IIC_VUNAD, "vrecpe", "u32",
4157 v2i32, v2i32, int_arm_neon_vrecpe>;
4158 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4159 IIC_VUNAQ, "vrecpe", "u32",
4160 v4i32, v4i32, int_arm_neon_vrecpe>;
4161 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4162 IIC_VUNAD, "vrecpe", "f32",
4163 v2f32, v2f32, int_arm_neon_vrecpe>;
4164 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4165 IIC_VUNAQ, "vrecpe", "f32",
4166 v4f32, v4f32, int_arm_neon_vrecpe>;
4168 // VRECPS : Vector Reciprocal Step
4169 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4170 IIC_VRECSD, "vrecps", "f32",
4171 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4172 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4173 IIC_VRECSQ, "vrecps", "f32",
4174 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4176 // VRSQRTE : Vector Reciprocal Square Root Estimate
4177 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4178 IIC_VUNAD, "vrsqrte", "u32",
4179 v2i32, v2i32, int_arm_neon_vrsqrte>;
4180 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4181 IIC_VUNAQ, "vrsqrte", "u32",
4182 v4i32, v4i32, int_arm_neon_vrsqrte>;
4183 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4184 IIC_VUNAD, "vrsqrte", "f32",
4185 v2f32, v2f32, int_arm_neon_vrsqrte>;
4186 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4187 IIC_VUNAQ, "vrsqrte", "f32",
4188 v4f32, v4f32, int_arm_neon_vrsqrte>;
4190 // VRSQRTS : Vector Reciprocal Square Root Step
4191 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4192 IIC_VRECSD, "vrsqrts", "f32",
4193 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4194 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4195 IIC_VRECSQ, "vrsqrts", "f32",
4196 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4200 // VSHL : Vector Shift
4201 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4202 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4203 "vshl", "s", int_arm_neon_vshifts>;
4204 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4205 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4206 "vshl", "u", int_arm_neon_vshiftu>;
4208 // VSHL : Vector Shift Left (Immediate)
4209 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4211 // VSHR : Vector Shift Right (Immediate)
4212 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4213 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4215 // VSHLL : Vector Shift Left Long
4216 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4217 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4219 // VSHLL : Vector Shift Left Long (with maximum shift count)
4220 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4221 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4222 ValueType OpTy, SDNode OpNode>
4223 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4224 ResTy, OpTy, OpNode> {
4225 let Inst{21-16} = op21_16;
4226 let DecoderMethod = "DecodeVSHLMaxInstruction";
4228 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4229 v8i16, v8i8, NEONvshlli>;
4230 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4231 v4i32, v4i16, NEONvshlli>;
4232 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4233 v2i64, v2i32, NEONvshlli>;
4235 // VSHRN : Vector Shift Right and Narrow
4236 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4239 // VRSHL : Vector Rounding Shift
4240 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4241 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4242 "vrshl", "s", int_arm_neon_vrshifts>;
4243 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4244 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4245 "vrshl", "u", int_arm_neon_vrshiftu>;
4246 // VRSHR : Vector Rounding Shift Right
4247 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4248 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4250 // VRSHRN : Vector Rounding Shift Right and Narrow
4251 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4254 // VQSHL : Vector Saturating Shift
4255 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4256 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4257 "vqshl", "s", int_arm_neon_vqshifts>;
4258 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4259 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4260 "vqshl", "u", int_arm_neon_vqshiftu>;
4261 // VQSHL : Vector Saturating Shift Left (Immediate)
4262 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4263 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4265 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4266 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4268 // VQSHRN : Vector Saturating Shift Right and Narrow
4269 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4271 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4274 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4275 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4278 // VQRSHL : Vector Saturating Rounding Shift
4279 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4280 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4281 "vqrshl", "s", int_arm_neon_vqrshifts>;
4282 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4283 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4284 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4286 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4287 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4289 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4292 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4293 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4296 // VSRA : Vector Shift Right and Accumulate
4297 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4298 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4299 // VRSRA : Vector Rounding Shift Right and Accumulate
4300 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4301 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4303 // VSLI : Vector Shift Left and Insert
4304 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4306 // VSRI : Vector Shift Right and Insert
4307 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4309 // Vector Absolute and Saturating Absolute.
4311 // VABS : Vector Absolute Value
4312 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4313 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4315 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4316 IIC_VUNAD, "vabs", "f32",
4317 v2f32, v2f32, int_arm_neon_vabs>;
4318 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4319 IIC_VUNAQ, "vabs", "f32",
4320 v4f32, v4f32, int_arm_neon_vabs>;
4322 // VQABS : Vector Saturating Absolute Value
4323 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4324 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4325 int_arm_neon_vqabs>;
4329 def vnegd : PatFrag<(ops node:$in),
4330 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4331 def vnegq : PatFrag<(ops node:$in),
4332 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4334 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4335 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4336 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4337 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4338 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4339 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4340 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4341 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4343 // VNEG : Vector Negate (integer)
4344 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4345 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4346 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4347 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4348 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4349 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4351 // VNEG : Vector Negate (floating-point)
4352 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4353 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4354 "vneg", "f32", "$Vd, $Vm", "",
4355 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4356 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4357 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4358 "vneg", "f32", "$Vd, $Vm", "",
4359 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4361 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4362 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4363 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4364 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4365 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4366 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4368 // VQNEG : Vector Saturating Negate
4369 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4370 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4371 int_arm_neon_vqneg>;
4373 // Vector Bit Counting Operations.
4375 // VCLS : Vector Count Leading Sign Bits
4376 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4377 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4379 // VCLZ : Vector Count Leading Zeros
4380 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4381 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4383 // VCNT : Vector Count One Bits
4384 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4385 IIC_VCNTiD, "vcnt", "8",
4386 v8i8, v8i8, int_arm_neon_vcnt>;
4387 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4388 IIC_VCNTiQ, "vcnt", "8",
4389 v16i8, v16i8, int_arm_neon_vcnt>;
4392 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4393 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4394 "vswp", "$Vd, $Vm", "", []>;
4395 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4396 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4397 "vswp", "$Vd, $Vm", "", []>;
4399 // Vector Move Operations.
4401 // VMOV : Vector Move (Register)
4402 def : InstAlias<"vmov${p} $Vd, $Vm",
4403 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4404 def : InstAlias<"vmov${p} $Vd, $Vm",
4405 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4407 // VMOV : Vector Move (Immediate)
4409 let isReMaterializable = 1 in {
4410 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4411 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4412 "vmov", "i8", "$Vd, $SIMM", "",
4413 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4414 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4415 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4416 "vmov", "i8", "$Vd, $SIMM", "",
4417 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4419 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4420 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4421 "vmov", "i16", "$Vd, $SIMM", "",
4422 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4423 let Inst{9} = SIMM{9};
4426 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4427 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4428 "vmov", "i16", "$Vd, $SIMM", "",
4429 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4430 let Inst{9} = SIMM{9};
4433 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4434 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4435 "vmov", "i32", "$Vd, $SIMM", "",
4436 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4437 let Inst{11-8} = SIMM{11-8};
4440 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4441 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4442 "vmov", "i32", "$Vd, $SIMM", "",
4443 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4444 let Inst{11-8} = SIMM{11-8};
4447 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4448 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4449 "vmov", "i64", "$Vd, $SIMM", "",
4450 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4451 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4452 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4453 "vmov", "i64", "$Vd, $SIMM", "",
4454 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4455 } // isReMaterializable
4457 // VMOV : Vector Get Lane (move scalar to ARM core register)
4459 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4460 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4461 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4462 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4464 let Inst{21} = lane{2};
4465 let Inst{6-5} = lane{1-0};
4467 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4468 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4469 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4470 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4472 let Inst{21} = lane{1};
4473 let Inst{6} = lane{0};
4475 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4476 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4477 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4478 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4480 let Inst{21} = lane{2};
4481 let Inst{6-5} = lane{1-0};
4483 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4484 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4485 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4486 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4488 let Inst{21} = lane{1};
4489 let Inst{6} = lane{0};
4491 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4492 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4493 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4494 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4496 let Inst{21} = lane{0};
4498 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4499 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4500 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4501 (DSubReg_i8_reg imm:$lane))),
4502 (SubReg_i8_lane imm:$lane))>;
4503 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4504 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4505 (DSubReg_i16_reg imm:$lane))),
4506 (SubReg_i16_lane imm:$lane))>;
4507 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4508 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4509 (DSubReg_i8_reg imm:$lane))),
4510 (SubReg_i8_lane imm:$lane))>;
4511 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4512 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4513 (DSubReg_i16_reg imm:$lane))),
4514 (SubReg_i16_lane imm:$lane))>;
4515 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4516 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4517 (DSubReg_i32_reg imm:$lane))),
4518 (SubReg_i32_lane imm:$lane))>;
4519 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4520 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4521 (SSubReg_f32_reg imm:$src2))>;
4522 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4523 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4524 (SSubReg_f32_reg imm:$src2))>;
4525 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4526 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4527 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4528 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4531 // VMOV : Vector Set Lane (move ARM core register to scalar)
4533 let Constraints = "$src1 = $V" in {
4534 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4535 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4536 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4537 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4538 GPR:$R, imm:$lane))]> {
4539 let Inst{21} = lane{2};
4540 let Inst{6-5} = lane{1-0};
4542 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4543 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4544 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4545 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4546 GPR:$R, imm:$lane))]> {
4547 let Inst{21} = lane{1};
4548 let Inst{6} = lane{0};
4550 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4551 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4552 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4553 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4554 GPR:$R, imm:$lane))]> {
4555 let Inst{21} = lane{0};
4558 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4559 (v16i8 (INSERT_SUBREG QPR:$src1,
4560 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4561 (DSubReg_i8_reg imm:$lane))),
4562 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4563 (DSubReg_i8_reg imm:$lane)))>;
4564 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4565 (v8i16 (INSERT_SUBREG QPR:$src1,
4566 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4567 (DSubReg_i16_reg imm:$lane))),
4568 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4569 (DSubReg_i16_reg imm:$lane)))>;
4570 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4571 (v4i32 (INSERT_SUBREG QPR:$src1,
4572 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4573 (DSubReg_i32_reg imm:$lane))),
4574 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4575 (DSubReg_i32_reg imm:$lane)))>;
4577 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4578 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4579 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4580 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4581 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4582 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4584 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4585 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4586 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4587 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4589 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4590 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4591 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4592 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4593 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4594 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4596 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4597 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4598 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4599 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4600 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4601 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4603 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4604 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4605 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4607 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4608 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4609 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4611 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4612 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4613 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4616 // VDUP : Vector Duplicate (from ARM core register to all elements)
4618 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4619 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4620 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4621 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4622 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4623 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4624 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4625 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4627 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4628 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4629 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4630 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4631 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4632 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4634 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4635 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4637 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4639 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4640 ValueType Ty, Operand IdxTy>
4641 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4642 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4643 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4645 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4646 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4647 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4648 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4649 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4650 VectorIndex32:$lane)))]>;
4652 // Inst{19-16} is partially specified depending on the element size.
4654 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4656 let Inst{19-17} = lane{2-0};
4658 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4660 let Inst{19-18} = lane{1-0};
4662 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4664 let Inst{19} = lane{0};
4666 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4668 let Inst{19-17} = lane{2-0};
4670 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4672 let Inst{19-18} = lane{1-0};
4674 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4676 let Inst{19} = lane{0};
4679 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4680 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4682 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4683 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4685 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4686 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4687 (DSubReg_i8_reg imm:$lane))),
4688 (SubReg_i8_lane imm:$lane)))>;
4689 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4690 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4691 (DSubReg_i16_reg imm:$lane))),
4692 (SubReg_i16_lane imm:$lane)))>;
4693 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4694 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4695 (DSubReg_i32_reg imm:$lane))),
4696 (SubReg_i32_lane imm:$lane)))>;
4697 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4698 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4699 (DSubReg_i32_reg imm:$lane))),
4700 (SubReg_i32_lane imm:$lane)))>;
4702 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4703 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4704 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4705 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4707 // VMOVN : Vector Narrowing Move
4708 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4709 "vmovn", "i", trunc>;
4710 // VQMOVN : Vector Saturating Narrowing Move
4711 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4712 "vqmovn", "s", int_arm_neon_vqmovns>;
4713 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4714 "vqmovn", "u", int_arm_neon_vqmovnu>;
4715 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4716 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4717 // VMOVL : Vector Lengthening Move
4718 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4719 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4721 // Vector Conversions.
4723 // VCVT : Vector Convert Between Floating-Point and Integers
4724 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4725 v2i32, v2f32, fp_to_sint>;
4726 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4727 v2i32, v2f32, fp_to_uint>;
4728 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4729 v2f32, v2i32, sint_to_fp>;
4730 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4731 v2f32, v2i32, uint_to_fp>;
4733 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4734 v4i32, v4f32, fp_to_sint>;
4735 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4736 v4i32, v4f32, fp_to_uint>;
4737 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4738 v4f32, v4i32, sint_to_fp>;
4739 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4740 v4f32, v4i32, uint_to_fp>;
4742 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4743 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4744 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4745 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4746 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4747 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4748 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4749 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4750 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4752 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4753 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4754 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4755 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4756 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4757 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4758 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4759 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4761 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4762 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4763 IIC_VUNAQ, "vcvt", "f16.f32",
4764 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4765 Requires<[HasNEON, HasFP16]>;
4766 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4767 IIC_VUNAQ, "vcvt", "f32.f16",
4768 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4769 Requires<[HasNEON, HasFP16]>;
4773 // VREV64 : Vector Reverse elements within 64-bit doublewords
4775 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4776 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4777 (ins DPR:$Vm), IIC_VMOVD,
4778 OpcodeStr, Dt, "$Vd, $Vm", "",
4779 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4780 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4781 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4782 (ins QPR:$Vm), IIC_VMOVQ,
4783 OpcodeStr, Dt, "$Vd, $Vm", "",
4784 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4786 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4787 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4788 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4789 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4791 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4792 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4793 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4794 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4796 // VREV32 : Vector Reverse elements within 32-bit words
4798 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4799 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4800 (ins DPR:$Vm), IIC_VMOVD,
4801 OpcodeStr, Dt, "$Vd, $Vm", "",
4802 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4803 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4804 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4805 (ins QPR:$Vm), IIC_VMOVQ,
4806 OpcodeStr, Dt, "$Vd, $Vm", "",
4807 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4809 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4810 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4812 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4813 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4815 // VREV16 : Vector Reverse elements within 16-bit halfwords
4817 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4818 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4819 (ins DPR:$Vm), IIC_VMOVD,
4820 OpcodeStr, Dt, "$Vd, $Vm", "",
4821 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4822 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4823 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4824 (ins QPR:$Vm), IIC_VMOVQ,
4825 OpcodeStr, Dt, "$Vd, $Vm", "",
4826 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4828 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4829 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4831 // Other Vector Shuffles.
4833 // Aligned extractions: really just dropping registers
4835 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4836 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4837 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4839 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4841 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4843 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4845 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4847 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4850 // VEXT : Vector Extract
4852 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4853 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4854 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4855 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4856 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4857 (Ty DPR:$Vm), imm:$index)))]> {
4859 let Inst{11-8} = index{3-0};
4862 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4863 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4864 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4865 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4866 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4867 (Ty QPR:$Vm), imm:$index)))]> {
4869 let Inst{11-8} = index{3-0};
4872 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4873 let Inst{11-8} = index{3-0};
4875 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4876 let Inst{11-9} = index{2-0};
4879 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4880 let Inst{11-10} = index{1-0};
4881 let Inst{9-8} = 0b00;
4883 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4886 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4888 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4889 let Inst{11-8} = index{3-0};
4891 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4892 let Inst{11-9} = index{2-0};
4895 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4896 let Inst{11-10} = index{1-0};
4897 let Inst{9-8} = 0b00;
4899 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4902 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4904 // VTRN : Vector Transpose
4906 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4907 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4908 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4910 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4911 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4912 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4914 // VUZP : Vector Unzip (Deinterleave)
4916 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4917 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4918 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4920 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4921 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4922 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4924 // VZIP : Vector Zip (Interleave)
4926 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4927 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4928 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4930 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4931 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4932 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4934 // Vector Table Lookup and Table Extension.
4936 // VTBL : Vector Table Lookup
4937 let DecoderMethod = "DecodeTBLInstruction" in {
4939 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4940 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4941 "vtbl", "8", "$Vd, $Vn, $Vm", "",
4942 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
4943 let hasExtraSrcRegAllocReq = 1 in {
4945 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4946 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4947 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4949 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4950 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4951 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4953 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4954 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4956 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4957 } // hasExtraSrcRegAllocReq = 1
4960 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4962 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4964 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4966 // VTBX : Vector Table Extension
4968 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4969 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4970 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
4971 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4972 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
4973 let hasExtraSrcRegAllocReq = 1 in {
4975 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4976 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4977 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4979 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4980 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4981 NVTBLFrm, IIC_VTBX3,
4982 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4985 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4986 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4987 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4989 } // hasExtraSrcRegAllocReq = 1
4992 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4993 IIC_VTBX2, "$orig = $dst", []>;
4995 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4996 IIC_VTBX3, "$orig = $dst", []>;
4998 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4999 IIC_VTBX4, "$orig = $dst", []>;
5000 } // DecoderMethod = "DecodeTBLInstruction"
5002 //===----------------------------------------------------------------------===//
5003 // NEON instructions for single-precision FP math
5004 //===----------------------------------------------------------------------===//
5006 class N2VSPat<SDNode OpNode, NeonI Inst>
5007 : NEONFPPat<(f32 (OpNode SPR:$a)),
5009 (v2f32 (COPY_TO_REGCLASS (Inst
5011 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5012 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5014 class N3VSPat<SDNode OpNode, NeonI Inst>
5015 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5017 (v2f32 (COPY_TO_REGCLASS (Inst
5019 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5022 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5023 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5025 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5026 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5028 (v2f32 (COPY_TO_REGCLASS (Inst
5030 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5033 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5036 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5037 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5039 def : N3VSPat<fadd, VADDfd>;
5040 def : N3VSPat<fsub, VSUBfd>;
5041 def : N3VSPat<fmul, VMULfd>;
5042 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5043 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5044 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5045 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5046 def : N2VSPat<fabs, VABSfd>;
5047 def : N2VSPat<fneg, VNEGfd>;
5048 def : N3VSPat<NEONfmax, VMAXfd>;
5049 def : N3VSPat<NEONfmin, VMINfd>;
5050 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5051 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5052 def : N2VSPat<arm_sitof, VCVTs2fd>;
5053 def : N2VSPat<arm_uitof, VCVTu2fd>;
5055 //===----------------------------------------------------------------------===//
5056 // Non-Instruction Patterns
5057 //===----------------------------------------------------------------------===//
5060 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5061 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5062 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5063 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5064 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5065 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5066 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5067 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5068 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5069 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5070 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5071 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5072 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5073 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5074 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5075 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5076 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5077 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5078 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5079 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5080 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5081 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5082 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5083 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5084 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5085 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5086 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5087 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5088 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5089 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5091 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5092 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5093 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5094 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5095 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5096 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5097 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5098 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5099 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5100 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5101 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5102 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5103 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5104 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5105 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5106 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5107 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5108 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5109 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5110 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5111 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5112 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5113 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5114 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5115 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5116 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5117 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5118 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5119 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5120 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;