1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
402 return cast<LoadSDNode>(N)->getAlignment() >= 8;
404 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 8;
408 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
409 return cast<LoadSDNode>(N)->getAlignment() == 4;
411 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() == 4;
415 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() == 2;
418 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
419 (store node:$val, node:$ptr), [{
420 return cast<StoreSDNode>(N)->getAlignment() == 2;
422 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 return cast<LoadSDNode>(N)->getAlignment() == 1;
425 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() == 1;
429 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() < 4;
432 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
433 (store node:$val, node:$ptr), [{
434 return cast<StoreSDNode>(N)->getAlignment() < 4;
437 //===----------------------------------------------------------------------===//
438 // NEON-specific DAG Nodes.
439 //===----------------------------------------------------------------------===//
441 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
442 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
444 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
445 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
446 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
447 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
448 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
449 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
450 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
451 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
452 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
453 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
454 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
456 // Types for vector shift by immediates. The "SHX" version is for long and
457 // narrow operations where the source and destination vectors have different
458 // types. The "SHINS" version is for shift and insert operations.
459 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
461 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
463 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
464 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
466 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
467 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
468 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
469 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
470 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
471 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
472 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
474 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
475 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
476 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
478 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
479 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
480 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
481 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
482 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
483 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
485 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
486 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
487 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
489 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
490 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
492 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
494 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
495 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
497 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
498 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
499 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
500 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
502 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
504 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
505 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
507 def NEONvbsl : SDNode<"ARMISD::VBSL",
508 SDTypeProfile<1, 3, [SDTCisVec<0>,
511 SDTCisSameAs<0, 3>]>>;
513 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
515 // VDUPLANE can produce a quad-register result from a double-register source,
516 // so the result is not constrained to match the source.
517 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
518 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
521 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
522 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
523 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
525 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
526 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
527 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
528 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
530 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
532 SDTCisSameAs<0, 3>]>;
533 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
534 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
535 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
537 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
538 SDTCisSameAs<1, 2>]>;
539 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
540 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
542 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
543 SDTCisSameAs<0, 2>]>;
544 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
545 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
547 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
548 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
549 unsigned EltBits = 0;
550 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
551 return (EltBits == 32 && EltVal == 0);
554 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
555 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
556 unsigned EltBits = 0;
557 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
558 return (EltBits == 8 && EltVal == 0xff);
561 //===----------------------------------------------------------------------===//
562 // NEON load / store instructions
563 //===----------------------------------------------------------------------===//
565 // Use VLDM to load a Q register as a D register pair.
566 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
568 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
570 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
572 // Use VSTM to store a Q register as a D register pair.
573 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
575 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
577 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
579 // Classes for VLD* pseudo-instructions with multi-register operands.
580 // These are expanded to real instructions after register allocation.
581 class VLDQPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
583 class VLDQWBPseudo<InstrItinClass itin>
584 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
585 (ins addrmode6:$addr, am6offset:$offset), itin,
587 class VLDQWBfixedPseudo<InstrItinClass itin>
588 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
589 (ins addrmode6:$addr), itin,
591 class VLDQWBregisterPseudo<InstrItinClass itin>
592 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
593 (ins addrmode6:$addr, rGPR:$offset), itin,
596 class VLDQQPseudo<InstrItinClass itin>
597 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
598 class VLDQQWBPseudo<InstrItinClass itin>
599 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
600 (ins addrmode6:$addr, am6offset:$offset), itin,
602 class VLDQQWBfixedPseudo<InstrItinClass itin>
603 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
604 (ins addrmode6:$addr), itin,
606 class VLDQQWBregisterPseudo<InstrItinClass itin>
607 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
608 (ins addrmode6:$addr, rGPR:$offset), itin,
612 class VLDQQQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
615 class VLDQQQQWBPseudo<InstrItinClass itin>
616 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
617 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
618 "$addr.addr = $wb, $src = $dst">;
620 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
622 // VLD1 : Vector Load (multiple single elements)
623 class VLD1D<bits<4> op7_4, string Dt>
624 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
625 (ins addrmode6:$Rn), IIC_VLD1,
626 "vld1", Dt, "$Vd, $Rn", "", []> {
629 let DecoderMethod = "DecodeVLDInstruction";
631 class VLD1Q<bits<4> op7_4, string Dt>
632 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
633 (ins addrmode6:$Rn), IIC_VLD1x2,
634 "vld1", Dt, "$Vd, $Rn", "", []> {
636 let Inst{5-4} = Rn{5-4};
637 let DecoderMethod = "DecodeVLDInstruction";
640 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
641 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
642 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
643 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
645 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
646 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
647 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
648 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
650 // ...with address register writeback:
651 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
652 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
653 (ins addrmode6:$Rn), IIC_VLD1u,
654 "vld1", Dt, "$Vd, $Rn!",
655 "$Rn.addr = $wb", []> {
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
658 let DecoderMethod = "DecodeVLDInstruction";
659 let AsmMatchConverter = "cvtVLDwbFixed";
661 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
662 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
663 "vld1", Dt, "$Vd, $Rn, $Rm",
664 "$Rn.addr = $wb", []> {
666 let DecoderMethod = "DecodeVLDInstruction";
667 let AsmMatchConverter = "cvtVLDwbRegister";
670 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
671 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
672 (ins addrmode6:$Rn), IIC_VLD1x2u,
673 "vld1", Dt, "$Vd, $Rn!",
674 "$Rn.addr = $wb", []> {
675 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
676 let Inst{5-4} = Rn{5-4};
677 let DecoderMethod = "DecodeVLDInstruction";
678 let AsmMatchConverter = "cvtVLDwbFixed";
680 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
681 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
682 "vld1", Dt, "$Vd, $Rn, $Rm",
683 "$Rn.addr = $wb", []> {
684 let Inst{5-4} = Rn{5-4};
685 let DecoderMethod = "DecodeVLDInstruction";
686 let AsmMatchConverter = "cvtVLDwbRegister";
690 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
691 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
692 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
693 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
694 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
695 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
696 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
697 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
699 // ...with 3 registers
700 class VLD1D3<bits<4> op7_4, string Dt>
701 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
702 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
703 "$Vd, $Rn", "", []> {
706 let DecoderMethod = "DecodeVLDInstruction";
708 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
709 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
710 (ins addrmode6:$Rn), IIC_VLD1x2u,
711 "vld1", Dt, "$Vd, $Rn!",
712 "$Rn.addr = $wb", []> {
713 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
715 let DecoderMethod = "DecodeVLDInstruction";
716 let AsmMatchConverter = "cvtVLDwbFixed";
718 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
719 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
720 "vld1", Dt, "$Vd, $Rn, $Rm",
721 "$Rn.addr = $wb", []> {
723 let DecoderMethod = "DecodeVLDInstruction";
724 let AsmMatchConverter = "cvtVLDwbRegister";
728 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
729 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
730 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
731 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
733 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
734 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
735 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
736 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
738 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
740 // ...with 4 registers
741 class VLD1D4<bits<4> op7_4, string Dt>
742 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
743 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
744 "$Vd, $Rn", "", []> {
746 let Inst{5-4} = Rn{5-4};
747 let DecoderMethod = "DecodeVLDInstruction";
749 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
750 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
751 (ins addrmode6:$Rn), IIC_VLD1x2u,
752 "vld1", Dt, "$Vd, $Rn!",
753 "$Rn.addr = $wb", []> {
754 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
755 let Inst{5-4} = Rn{5-4};
756 let DecoderMethod = "DecodeVLDInstruction";
757 let AsmMatchConverter = "cvtVLDwbFixed";
759 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
760 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
761 "vld1", Dt, "$Vd, $Rn, $Rm",
762 "$Rn.addr = $wb", []> {
763 let Inst{5-4} = Rn{5-4};
764 let DecoderMethod = "DecodeVLDInstruction";
765 let AsmMatchConverter = "cvtVLDwbRegister";
769 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
770 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
771 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
772 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
774 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
775 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
776 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
777 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
779 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
781 // VLD2 : Vector Load (multiple 2-element structures)
782 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
784 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
785 (ins addrmode6:$Rn), itin,
786 "vld2", Dt, "$Vd, $Rn", "", []> {
788 let Inst{5-4} = Rn{5-4};
789 let DecoderMethod = "DecodeVLDInstruction";
792 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
793 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
794 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
796 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
797 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
798 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
800 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
801 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
802 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
804 // ...with address register writeback:
805 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
806 RegisterOperand VdTy, InstrItinClass itin> {
807 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
808 (ins addrmode6:$Rn), itin,
809 "vld2", Dt, "$Vd, $Rn!",
810 "$Rn.addr = $wb", []> {
811 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
812 let Inst{5-4} = Rn{5-4};
813 let DecoderMethod = "DecodeVLDInstruction";
814 let AsmMatchConverter = "cvtVLDwbFixed";
816 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
817 (ins addrmode6:$Rn, rGPR:$Rm), itin,
818 "vld2", Dt, "$Vd, $Rn, $Rm",
819 "$Rn.addr = $wb", []> {
820 let Inst{5-4} = Rn{5-4};
821 let DecoderMethod = "DecodeVLDInstruction";
822 let AsmMatchConverter = "cvtVLDwbRegister";
826 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
827 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
828 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
830 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
831 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
832 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
834 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
835 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
836 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
837 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
838 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
839 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
841 // ...with double-spaced registers
842 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
843 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
844 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
845 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
846 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
847 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
849 // VLD3 : Vector Load (multiple 3-element structures)
850 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
851 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
852 (ins addrmode6:$Rn), IIC_VLD3,
853 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
856 let DecoderMethod = "DecodeVLDInstruction";
859 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
860 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
861 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
863 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
864 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
865 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
867 // ...with address register writeback:
868 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
869 : NLdSt<0, 0b10, op11_8, op7_4,
870 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
871 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
872 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
873 "$Rn.addr = $wb", []> {
875 let DecoderMethod = "DecodeVLDInstruction";
878 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
879 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
880 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
882 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
883 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
884 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
886 // ...with double-spaced registers:
887 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
888 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
889 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
890 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
891 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
892 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
894 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
895 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
896 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
898 // ...alternate versions to be allocated odd register numbers:
899 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
900 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
901 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
903 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
904 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
905 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
907 // VLD4 : Vector Load (multiple 4-element structures)
908 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
909 : NLdSt<0, 0b10, op11_8, op7_4,
910 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
911 (ins addrmode6:$Rn), IIC_VLD4,
912 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
914 let Inst{5-4} = Rn{5-4};
915 let DecoderMethod = "DecodeVLDInstruction";
918 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
919 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
920 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
922 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
923 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
924 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
926 // ...with address register writeback:
927 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
928 : NLdSt<0, 0b10, op11_8, op7_4,
929 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
930 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
931 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
932 "$Rn.addr = $wb", []> {
933 let Inst{5-4} = Rn{5-4};
934 let DecoderMethod = "DecodeVLDInstruction";
937 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
938 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
939 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
941 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
942 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
943 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
945 // ...with double-spaced registers:
946 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
947 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
948 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
949 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
950 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
951 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
953 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
954 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
955 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
957 // ...alternate versions to be allocated odd register numbers:
958 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
959 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
960 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
962 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
963 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
964 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
966 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
968 // Classes for VLD*LN pseudo-instructions with multi-register operands.
969 // These are expanded to real instructions after register allocation.
970 class VLDQLNPseudo<InstrItinClass itin>
971 : PseudoNLdSt<(outs QPR:$dst),
972 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
973 itin, "$src = $dst">;
974 class VLDQLNWBPseudo<InstrItinClass itin>
975 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
976 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
977 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
978 class VLDQQLNPseudo<InstrItinClass itin>
979 : PseudoNLdSt<(outs QQPR:$dst),
980 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
981 itin, "$src = $dst">;
982 class VLDQQLNWBPseudo<InstrItinClass itin>
983 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
984 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
985 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
986 class VLDQQQQLNPseudo<InstrItinClass itin>
987 : PseudoNLdSt<(outs QQQQPR:$dst),
988 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
989 itin, "$src = $dst">;
990 class VLDQQQQLNWBPseudo<InstrItinClass itin>
991 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
992 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
993 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
995 // VLD1LN : Vector Load (single element to one lane)
996 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
998 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
999 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1000 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1002 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1003 (i32 (LoadOp addrmode6:$Rn)),
1006 let DecoderMethod = "DecodeVLD1LN";
1008 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1010 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1011 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1012 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1014 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1015 (i32 (LoadOp addrmode6oneL32:$Rn)),
1018 let DecoderMethod = "DecodeVLD1LN";
1020 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1021 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1022 (i32 (LoadOp addrmode6:$addr)),
1026 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1027 let Inst{7-5} = lane{2-0};
1029 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1030 let Inst{7-6} = lane{1-0};
1031 let Inst{5-4} = Rn{5-4};
1033 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1034 let Inst{7} = lane{0};
1035 let Inst{5-4} = Rn{5-4};
1038 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1039 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1040 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1042 def : Pat<(vector_insert (v2f32 DPR:$src),
1043 (f32 (load addrmode6:$addr)), imm:$lane),
1044 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1045 def : Pat<(vector_insert (v4f32 QPR:$src),
1046 (f32 (load addrmode6:$addr)), imm:$lane),
1047 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1049 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1051 // ...with address register writeback:
1052 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1053 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1054 (ins addrmode6:$Rn, am6offset:$Rm,
1055 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1056 "\\{$Vd[$lane]\\}, $Rn$Rm",
1057 "$src = $Vd, $Rn.addr = $wb", []> {
1058 let DecoderMethod = "DecodeVLD1LN";
1061 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1062 let Inst{7-5} = lane{2-0};
1064 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1065 let Inst{7-6} = lane{1-0};
1066 let Inst{4} = Rn{4};
1068 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1069 let Inst{7} = lane{0};
1070 let Inst{5} = Rn{4};
1071 let Inst{4} = Rn{4};
1074 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1075 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1076 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1078 // VLD2LN : Vector Load (single 2-element structure to one lane)
1079 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1080 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1081 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1082 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1083 "$src1 = $Vd, $src2 = $dst2", []> {
1085 let Inst{4} = Rn{4};
1086 let DecoderMethod = "DecodeVLD2LN";
1089 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1090 let Inst{7-5} = lane{2-0};
1092 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1093 let Inst{7-6} = lane{1-0};
1095 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1096 let Inst{7} = lane{0};
1099 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1100 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1101 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1103 // ...with double-spaced registers:
1104 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1105 let Inst{7-6} = lane{1-0};
1107 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1108 let Inst{7} = lane{0};
1111 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1112 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1114 // ...with address register writeback:
1115 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1116 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1117 (ins addrmode6:$Rn, am6offset:$Rm,
1118 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1119 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1120 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1121 let Inst{4} = Rn{4};
1122 let DecoderMethod = "DecodeVLD2LN";
1125 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1126 let Inst{7-5} = lane{2-0};
1128 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1129 let Inst{7-6} = lane{1-0};
1131 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1132 let Inst{7} = lane{0};
1135 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1136 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1137 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1139 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1140 let Inst{7-6} = lane{1-0};
1142 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1143 let Inst{7} = lane{0};
1146 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1147 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1149 // VLD3LN : Vector Load (single 3-element structure to one lane)
1150 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1151 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1152 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1153 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1154 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1155 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1157 let DecoderMethod = "DecodeVLD3LN";
1160 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1161 let Inst{7-5} = lane{2-0};
1163 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1164 let Inst{7-6} = lane{1-0};
1166 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1167 let Inst{7} = lane{0};
1170 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1171 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1172 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1174 // ...with double-spaced registers:
1175 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1176 let Inst{7-6} = lane{1-0};
1178 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1179 let Inst{7} = lane{0};
1182 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1183 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1185 // ...with address register writeback:
1186 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1187 : NLdStLn<1, 0b10, op11_8, op7_4,
1188 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1189 (ins addrmode6:$Rn, am6offset:$Rm,
1190 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1191 IIC_VLD3lnu, "vld3", Dt,
1192 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1193 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1195 let DecoderMethod = "DecodeVLD3LN";
1198 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1199 let Inst{7-5} = lane{2-0};
1201 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1202 let Inst{7-6} = lane{1-0};
1204 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1205 let Inst{7} = lane{0};
1208 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1209 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1210 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1212 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1213 let Inst{7-6} = lane{1-0};
1215 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1216 let Inst{7} = lane{0};
1219 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1220 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1222 // VLD4LN : Vector Load (single 4-element structure to one lane)
1223 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1224 : NLdStLn<1, 0b10, op11_8, op7_4,
1225 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1226 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1227 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1228 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1229 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1231 let Inst{4} = Rn{4};
1232 let DecoderMethod = "DecodeVLD4LN";
1235 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1236 let Inst{7-5} = lane{2-0};
1238 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1239 let Inst{7-6} = lane{1-0};
1241 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1242 let Inst{7} = lane{0};
1243 let Inst{5} = Rn{5};
1246 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1247 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1248 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1250 // ...with double-spaced registers:
1251 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1252 let Inst{7-6} = lane{1-0};
1254 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1255 let Inst{7} = lane{0};
1256 let Inst{5} = Rn{5};
1259 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1260 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1262 // ...with address register writeback:
1263 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1264 : NLdStLn<1, 0b10, op11_8, op7_4,
1265 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1266 (ins addrmode6:$Rn, am6offset:$Rm,
1267 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1268 IIC_VLD4lnu, "vld4", Dt,
1269 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1270 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1272 let Inst{4} = Rn{4};
1273 let DecoderMethod = "DecodeVLD4LN" ;
1276 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1277 let Inst{7-5} = lane{2-0};
1279 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1280 let Inst{7-6} = lane{1-0};
1282 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1283 let Inst{7} = lane{0};
1284 let Inst{5} = Rn{5};
1287 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1288 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1289 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1291 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1292 let Inst{7-6} = lane{1-0};
1294 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1295 let Inst{7} = lane{0};
1296 let Inst{5} = Rn{5};
1299 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1300 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1302 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1304 // VLD1DUP : Vector Load (single element to all lanes)
1305 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1306 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1307 (ins addrmode6dup:$Rn),
1308 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1309 [(set VecListOneDAllLanes:$Vd,
1310 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1312 let Inst{4} = Rn{4};
1313 let DecoderMethod = "DecodeVLD1DupInstruction";
1315 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1316 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1317 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1319 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1320 (VLD1DUPd32 addrmode6:$addr)>;
1322 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1323 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1324 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1325 "vld1", Dt, "$Vd, $Rn", "",
1326 [(set VecListDPairAllLanes:$Vd,
1327 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1329 let Inst{4} = Rn{4};
1330 let DecoderMethod = "DecodeVLD1DupInstruction";
1333 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1334 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1335 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1337 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1338 (VLD1DUPq32 addrmode6:$addr)>;
1340 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1341 // ...with address register writeback:
1342 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1343 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1344 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1345 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1346 "vld1", Dt, "$Vd, $Rn!",
1347 "$Rn.addr = $wb", []> {
1348 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1349 let Inst{4} = Rn{4};
1350 let DecoderMethod = "DecodeVLD1DupInstruction";
1351 let AsmMatchConverter = "cvtVLDwbFixed";
1353 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1354 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1355 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1356 "vld1", Dt, "$Vd, $Rn, $Rm",
1357 "$Rn.addr = $wb", []> {
1358 let Inst{4} = Rn{4};
1359 let DecoderMethod = "DecodeVLD1DupInstruction";
1360 let AsmMatchConverter = "cvtVLDwbRegister";
1363 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1364 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1365 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1366 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1367 "vld1", Dt, "$Vd, $Rn!",
1368 "$Rn.addr = $wb", []> {
1369 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1370 let Inst{4} = Rn{4};
1371 let DecoderMethod = "DecodeVLD1DupInstruction";
1372 let AsmMatchConverter = "cvtVLDwbFixed";
1374 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1375 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1376 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1377 "vld1", Dt, "$Vd, $Rn, $Rm",
1378 "$Rn.addr = $wb", []> {
1379 let Inst{4} = Rn{4};
1380 let DecoderMethod = "DecodeVLD1DupInstruction";
1381 let AsmMatchConverter = "cvtVLDwbRegister";
1385 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1386 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1387 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1389 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1390 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1391 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1393 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1394 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1395 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1396 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1397 "vld2", Dt, "$Vd, $Rn", "", []> {
1399 let Inst{4} = Rn{4};
1400 let DecoderMethod = "DecodeVLD2DupInstruction";
1403 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1404 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1405 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1407 // ...with double-spaced registers
1408 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1409 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1410 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1412 // ...with address register writeback:
1413 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1414 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1415 (outs VdTy:$Vd, GPR:$wb),
1416 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1417 "vld2", Dt, "$Vd, $Rn!",
1418 "$Rn.addr = $wb", []> {
1419 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1420 let Inst{4} = Rn{4};
1421 let DecoderMethod = "DecodeVLD2DupInstruction";
1422 let AsmMatchConverter = "cvtVLDwbFixed";
1424 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1425 (outs VdTy:$Vd, GPR:$wb),
1426 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1427 "vld2", Dt, "$Vd, $Rn, $Rm",
1428 "$Rn.addr = $wb", []> {
1429 let Inst{4} = Rn{4};
1430 let DecoderMethod = "DecodeVLD2DupInstruction";
1431 let AsmMatchConverter = "cvtVLDwbRegister";
1435 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1436 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1437 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1439 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1440 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1441 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1443 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1444 class VLD3DUP<bits<4> op7_4, string Dt>
1445 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1446 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1447 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1450 let DecoderMethod = "DecodeVLD3DupInstruction";
1453 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1454 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1455 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1457 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1458 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1459 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1461 // ...with double-spaced registers (not used for codegen):
1462 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1463 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1464 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1466 // ...with address register writeback:
1467 class VLD3DUPWB<bits<4> op7_4, string Dt>
1468 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1469 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1470 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1471 "$Rn.addr = $wb", []> {
1473 let DecoderMethod = "DecodeVLD3DupInstruction";
1476 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1477 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1478 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1480 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1481 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1482 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1484 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1485 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1486 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1488 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1489 class VLD4DUP<bits<4> op7_4, string Dt>
1490 : NLdSt<1, 0b10, 0b1111, op7_4,
1491 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1492 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1493 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1495 let Inst{4} = Rn{4};
1496 let DecoderMethod = "DecodeVLD4DupInstruction";
1499 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1500 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1501 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1503 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1504 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1505 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1507 // ...with double-spaced registers (not used for codegen):
1508 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1509 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1510 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1512 // ...with address register writeback:
1513 class VLD4DUPWB<bits<4> op7_4, string Dt>
1514 : NLdSt<1, 0b10, 0b1111, op7_4,
1515 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1516 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1517 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1518 "$Rn.addr = $wb", []> {
1519 let Inst{4} = Rn{4};
1520 let DecoderMethod = "DecodeVLD4DupInstruction";
1523 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1524 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1525 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1527 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1528 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1529 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1531 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1532 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1533 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1535 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1537 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1539 // Classes for VST* pseudo-instructions with multi-register operands.
1540 // These are expanded to real instructions after register allocation.
1541 class VSTQPseudo<InstrItinClass itin>
1542 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1543 class VSTQWBPseudo<InstrItinClass itin>
1544 : PseudoNLdSt<(outs GPR:$wb),
1545 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1546 "$addr.addr = $wb">;
1547 class VSTQWBfixedPseudo<InstrItinClass itin>
1548 : PseudoNLdSt<(outs GPR:$wb),
1549 (ins addrmode6:$addr, QPR:$src), itin,
1550 "$addr.addr = $wb">;
1551 class VSTQWBregisterPseudo<InstrItinClass itin>
1552 : PseudoNLdSt<(outs GPR:$wb),
1553 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1554 "$addr.addr = $wb">;
1555 class VSTQQPseudo<InstrItinClass itin>
1556 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1557 class VSTQQWBPseudo<InstrItinClass itin>
1558 : PseudoNLdSt<(outs GPR:$wb),
1559 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1560 "$addr.addr = $wb">;
1561 class VSTQQWBfixedPseudo<InstrItinClass itin>
1562 : PseudoNLdSt<(outs GPR:$wb),
1563 (ins addrmode6:$addr, QQPR:$src), itin,
1564 "$addr.addr = $wb">;
1565 class VSTQQWBregisterPseudo<InstrItinClass itin>
1566 : PseudoNLdSt<(outs GPR:$wb),
1567 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1568 "$addr.addr = $wb">;
1570 class VSTQQQQPseudo<InstrItinClass itin>
1571 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1572 class VSTQQQQWBPseudo<InstrItinClass itin>
1573 : PseudoNLdSt<(outs GPR:$wb),
1574 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1575 "$addr.addr = $wb">;
1577 // VST1 : Vector Store (multiple single elements)
1578 class VST1D<bits<4> op7_4, string Dt>
1579 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1580 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1582 let Inst{4} = Rn{4};
1583 let DecoderMethod = "DecodeVSTInstruction";
1585 class VST1Q<bits<4> op7_4, string Dt>
1586 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1587 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1589 let Inst{5-4} = Rn{5-4};
1590 let DecoderMethod = "DecodeVSTInstruction";
1593 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1594 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1595 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1596 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1598 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1599 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1600 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1601 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1603 // ...with address register writeback:
1604 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1605 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1606 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1607 "vst1", Dt, "$Vd, $Rn!",
1608 "$Rn.addr = $wb", []> {
1609 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1610 let Inst{4} = Rn{4};
1611 let DecoderMethod = "DecodeVSTInstruction";
1612 let AsmMatchConverter = "cvtVSTwbFixed";
1614 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1615 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1617 "vst1", Dt, "$Vd, $Rn, $Rm",
1618 "$Rn.addr = $wb", []> {
1619 let Inst{4} = Rn{4};
1620 let DecoderMethod = "DecodeVSTInstruction";
1621 let AsmMatchConverter = "cvtVSTwbRegister";
1624 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1625 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1626 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1627 "vst1", Dt, "$Vd, $Rn!",
1628 "$Rn.addr = $wb", []> {
1629 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1630 let Inst{5-4} = Rn{5-4};
1631 let DecoderMethod = "DecodeVSTInstruction";
1632 let AsmMatchConverter = "cvtVSTwbFixed";
1634 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1635 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1637 "vst1", Dt, "$Vd, $Rn, $Rm",
1638 "$Rn.addr = $wb", []> {
1639 let Inst{5-4} = Rn{5-4};
1640 let DecoderMethod = "DecodeVSTInstruction";
1641 let AsmMatchConverter = "cvtVSTwbRegister";
1645 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1646 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1647 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1648 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1650 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1651 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1652 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1653 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1655 // ...with 3 registers
1656 class VST1D3<bits<4> op7_4, string Dt>
1657 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1658 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1659 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1661 let Inst{4} = Rn{4};
1662 let DecoderMethod = "DecodeVSTInstruction";
1664 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1665 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1666 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1667 "vst1", Dt, "$Vd, $Rn!",
1668 "$Rn.addr = $wb", []> {
1669 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1670 let Inst{5-4} = Rn{5-4};
1671 let DecoderMethod = "DecodeVSTInstruction";
1672 let AsmMatchConverter = "cvtVSTwbFixed";
1674 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1675 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1677 "vst1", Dt, "$Vd, $Rn, $Rm",
1678 "$Rn.addr = $wb", []> {
1679 let Inst{5-4} = Rn{5-4};
1680 let DecoderMethod = "DecodeVSTInstruction";
1681 let AsmMatchConverter = "cvtVSTwbRegister";
1685 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1686 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1687 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1688 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1690 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1691 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1692 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1693 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1695 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1696 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1697 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1699 // ...with 4 registers
1700 class VST1D4<bits<4> op7_4, string Dt>
1701 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1702 (ins addrmode6:$Rn, VecListFourD:$Vd),
1703 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1706 let Inst{5-4} = Rn{5-4};
1707 let DecoderMethod = "DecodeVSTInstruction";
1709 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1710 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1711 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1712 "vst1", Dt, "$Vd, $Rn!",
1713 "$Rn.addr = $wb", []> {
1714 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1715 let Inst{5-4} = Rn{5-4};
1716 let DecoderMethod = "DecodeVSTInstruction";
1717 let AsmMatchConverter = "cvtVSTwbFixed";
1719 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1720 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1722 "vst1", Dt, "$Vd, $Rn, $Rm",
1723 "$Rn.addr = $wb", []> {
1724 let Inst{5-4} = Rn{5-4};
1725 let DecoderMethod = "DecodeVSTInstruction";
1726 let AsmMatchConverter = "cvtVSTwbRegister";
1730 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1731 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1732 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1733 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1735 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1736 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1737 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1738 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1740 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1741 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1742 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1744 // VST2 : Vector Store (multiple 2-element structures)
1745 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1746 InstrItinClass itin>
1747 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1748 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1750 let Inst{5-4} = Rn{5-4};
1751 let DecoderMethod = "DecodeVSTInstruction";
1754 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1755 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1756 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1758 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1759 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1760 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1762 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1763 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1764 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1766 // ...with address register writeback:
1767 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1768 RegisterOperand VdTy> {
1769 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1770 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1771 "vst2", Dt, "$Vd, $Rn!",
1772 "$Rn.addr = $wb", []> {
1773 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1774 let Inst{5-4} = Rn{5-4};
1775 let DecoderMethod = "DecodeVSTInstruction";
1776 let AsmMatchConverter = "cvtVSTwbFixed";
1778 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1779 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1780 "vst2", Dt, "$Vd, $Rn, $Rm",
1781 "$Rn.addr = $wb", []> {
1782 let Inst{5-4} = Rn{5-4};
1783 let DecoderMethod = "DecodeVSTInstruction";
1784 let AsmMatchConverter = "cvtVSTwbRegister";
1787 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1788 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1789 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1790 "vst2", Dt, "$Vd, $Rn!",
1791 "$Rn.addr = $wb", []> {
1792 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1793 let Inst{5-4} = Rn{5-4};
1794 let DecoderMethod = "DecodeVSTInstruction";
1795 let AsmMatchConverter = "cvtVSTwbFixed";
1797 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1798 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1800 "vst2", Dt, "$Vd, $Rn, $Rm",
1801 "$Rn.addr = $wb", []> {
1802 let Inst{5-4} = Rn{5-4};
1803 let DecoderMethod = "DecodeVSTInstruction";
1804 let AsmMatchConverter = "cvtVSTwbRegister";
1808 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1809 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1810 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1812 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1813 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1814 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1816 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1817 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1818 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1819 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1820 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1821 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1823 // ...with double-spaced registers
1824 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1825 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1826 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1827 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1828 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1829 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1831 // VST3 : Vector Store (multiple 3-element structures)
1832 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1833 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1834 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1835 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1837 let Inst{4} = Rn{4};
1838 let DecoderMethod = "DecodeVSTInstruction";
1841 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1842 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1843 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1845 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1846 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1847 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1849 // ...with address register writeback:
1850 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1851 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1852 (ins addrmode6:$Rn, am6offset:$Rm,
1853 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1854 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1855 "$Rn.addr = $wb", []> {
1856 let Inst{4} = Rn{4};
1857 let DecoderMethod = "DecodeVSTInstruction";
1860 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1861 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1862 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1864 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1865 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1866 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1868 // ...with double-spaced registers:
1869 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1870 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1871 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1872 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1873 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1874 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1876 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1877 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1878 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1880 // ...alternate versions to be allocated odd register numbers:
1881 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1882 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1883 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1885 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1886 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1887 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1889 // VST4 : Vector Store (multiple 4-element structures)
1890 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1891 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1892 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1893 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1896 let Inst{5-4} = Rn{5-4};
1897 let DecoderMethod = "DecodeVSTInstruction";
1900 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1901 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1902 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1904 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1905 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1906 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1908 // ...with address register writeback:
1909 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1910 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1911 (ins addrmode6:$Rn, am6offset:$Rm,
1912 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1913 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1914 "$Rn.addr = $wb", []> {
1915 let Inst{5-4} = Rn{5-4};
1916 let DecoderMethod = "DecodeVSTInstruction";
1919 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1920 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1921 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1923 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1924 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1925 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1927 // ...with double-spaced registers:
1928 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1929 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1930 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1931 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1932 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1933 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1935 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1936 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1937 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1939 // ...alternate versions to be allocated odd register numbers:
1940 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1941 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1942 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1944 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1945 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1946 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1948 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1950 // Classes for VST*LN pseudo-instructions with multi-register operands.
1951 // These are expanded to real instructions after register allocation.
1952 class VSTQLNPseudo<InstrItinClass itin>
1953 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1955 class VSTQLNWBPseudo<InstrItinClass itin>
1956 : PseudoNLdSt<(outs GPR:$wb),
1957 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1958 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1959 class VSTQQLNPseudo<InstrItinClass itin>
1960 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1962 class VSTQQLNWBPseudo<InstrItinClass itin>
1963 : PseudoNLdSt<(outs GPR:$wb),
1964 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1965 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1966 class VSTQQQQLNPseudo<InstrItinClass itin>
1967 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1969 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1970 : PseudoNLdSt<(outs GPR:$wb),
1971 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1972 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1974 // VST1LN : Vector Store (single element from one lane)
1975 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1976 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
1977 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1978 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
1979 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1980 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
1982 let DecoderMethod = "DecodeVST1LN";
1984 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1985 : VSTQLNPseudo<IIC_VST1ln> {
1986 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1990 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1991 NEONvgetlaneu, addrmode6> {
1992 let Inst{7-5} = lane{2-0};
1994 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1995 NEONvgetlaneu, addrmode6> {
1996 let Inst{7-6} = lane{1-0};
1997 let Inst{4} = Rn{4};
2000 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2002 let Inst{7} = lane{0};
2003 let Inst{5-4} = Rn{5-4};
2006 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2007 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2008 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2010 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2011 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2012 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2013 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2015 // ...with address register writeback:
2016 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2017 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
2018 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2019 (ins AdrMode:$Rn, am6offset:$Rm,
2020 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2021 "\\{$Vd[$lane]\\}, $Rn$Rm",
2023 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2024 AdrMode:$Rn, am6offset:$Rm))]> {
2025 let DecoderMethod = "DecodeVST1LN";
2027 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2028 : VSTQLNWBPseudo<IIC_VST1lnu> {
2029 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2030 addrmode6:$addr, am6offset:$offset))];
2033 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2034 NEONvgetlaneu, addrmode6> {
2035 let Inst{7-5} = lane{2-0};
2037 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2038 NEONvgetlaneu, addrmode6> {
2039 let Inst{7-6} = lane{1-0};
2040 let Inst{4} = Rn{4};
2042 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2043 extractelt, addrmode6oneL32> {
2044 let Inst{7} = lane{0};
2045 let Inst{5-4} = Rn{5-4};
2048 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2049 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2050 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2052 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2054 // VST2LN : Vector Store (single 2-element structure from one lane)
2055 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2056 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2057 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2058 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2061 let Inst{4} = Rn{4};
2062 let DecoderMethod = "DecodeVST2LN";
2065 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2066 let Inst{7-5} = lane{2-0};
2068 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2069 let Inst{7-6} = lane{1-0};
2071 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2072 let Inst{7} = lane{0};
2075 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2076 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2077 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2079 // ...with double-spaced registers:
2080 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2081 let Inst{7-6} = lane{1-0};
2082 let Inst{4} = Rn{4};
2084 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2085 let Inst{7} = lane{0};
2086 let Inst{4} = Rn{4};
2089 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2090 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2092 // ...with address register writeback:
2093 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2094 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2095 (ins addrmode6:$Rn, am6offset:$Rm,
2096 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2097 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2098 "$Rn.addr = $wb", []> {
2099 let Inst{4} = Rn{4};
2100 let DecoderMethod = "DecodeVST2LN";
2103 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2104 let Inst{7-5} = lane{2-0};
2106 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2107 let Inst{7-6} = lane{1-0};
2109 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2110 let Inst{7} = lane{0};
2113 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2114 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2115 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2117 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2118 let Inst{7-6} = lane{1-0};
2120 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2121 let Inst{7} = lane{0};
2124 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2125 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2127 // VST3LN : Vector Store (single 3-element structure from one lane)
2128 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2129 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2130 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2131 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2132 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2134 let DecoderMethod = "DecodeVST3LN";
2137 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2138 let Inst{7-5} = lane{2-0};
2140 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2141 let Inst{7-6} = lane{1-0};
2143 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2144 let Inst{7} = lane{0};
2147 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2148 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2149 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2151 // ...with double-spaced registers:
2152 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2153 let Inst{7-6} = lane{1-0};
2155 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2156 let Inst{7} = lane{0};
2159 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2160 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2162 // ...with address register writeback:
2163 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2164 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2165 (ins addrmode6:$Rn, am6offset:$Rm,
2166 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2167 IIC_VST3lnu, "vst3", Dt,
2168 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2169 "$Rn.addr = $wb", []> {
2170 let DecoderMethod = "DecodeVST3LN";
2173 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2174 let Inst{7-5} = lane{2-0};
2176 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2177 let Inst{7-6} = lane{1-0};
2179 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2180 let Inst{7} = lane{0};
2183 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2184 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2185 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2187 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2188 let Inst{7-6} = lane{1-0};
2190 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2191 let Inst{7} = lane{0};
2194 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2195 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2197 // VST4LN : Vector Store (single 4-element structure from one lane)
2198 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2199 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2200 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2201 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2202 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2205 let Inst{4} = Rn{4};
2206 let DecoderMethod = "DecodeVST4LN";
2209 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2210 let Inst{7-5} = lane{2-0};
2212 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2213 let Inst{7-6} = lane{1-0};
2215 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2216 let Inst{7} = lane{0};
2217 let Inst{5} = Rn{5};
2220 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2221 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2222 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2224 // ...with double-spaced registers:
2225 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2226 let Inst{7-6} = lane{1-0};
2228 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2229 let Inst{7} = lane{0};
2230 let Inst{5} = Rn{5};
2233 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2234 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2236 // ...with address register writeback:
2237 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2238 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2239 (ins addrmode6:$Rn, am6offset:$Rm,
2240 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2241 IIC_VST4lnu, "vst4", Dt,
2242 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2243 "$Rn.addr = $wb", []> {
2244 let Inst{4} = Rn{4};
2245 let DecoderMethod = "DecodeVST4LN";
2248 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2249 let Inst{7-5} = lane{2-0};
2251 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2252 let Inst{7-6} = lane{1-0};
2254 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2255 let Inst{7} = lane{0};
2256 let Inst{5} = Rn{5};
2259 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2260 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2261 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2263 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2264 let Inst{7-6} = lane{1-0};
2266 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2267 let Inst{7} = lane{0};
2268 let Inst{5} = Rn{5};
2271 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2272 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2274 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2276 // Use vld1/vst1 for unaligned f64 load / store
2277 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2278 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2279 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2280 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2281 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2282 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2283 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2284 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2285 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2286 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2287 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2288 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2290 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2291 // load / store if it's legal.
2292 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2293 (VLD1q64 addrmode6:$addr)>;
2294 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2295 (VST1q64 addrmode6:$addr, QPR:$value)>;
2296 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2297 (VLD1q32 addrmode6:$addr)>;
2298 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2299 (VST1q32 addrmode6:$addr, QPR:$value)>;
2300 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2301 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2302 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2303 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2304 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2305 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2306 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2307 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2309 //===----------------------------------------------------------------------===//
2310 // NEON pattern fragments
2311 //===----------------------------------------------------------------------===//
2313 // Extract D sub-registers of Q registers.
2314 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2315 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2316 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2318 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2319 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2320 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2322 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2323 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2324 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2326 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2327 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2328 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2331 // Extract S sub-registers of Q/D registers.
2332 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2333 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2334 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2337 // Translate lane numbers from Q registers to D subregs.
2338 def SubReg_i8_lane : SDNodeXForm<imm, [{
2339 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2341 def SubReg_i16_lane : SDNodeXForm<imm, [{
2342 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2344 def SubReg_i32_lane : SDNodeXForm<imm, [{
2345 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2348 //===----------------------------------------------------------------------===//
2349 // Instruction Classes
2350 //===----------------------------------------------------------------------===//
2352 // Basic 2-register operations: double- and quad-register.
2353 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2354 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2355 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2356 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2357 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2358 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2359 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2360 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2361 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2362 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2363 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2364 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2366 // Basic 2-register intrinsics, both double- and quad-register.
2367 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2368 bits<2> op17_16, bits<5> op11_7, bit op4,
2369 InstrItinClass itin, string OpcodeStr, string Dt,
2370 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2371 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2372 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2373 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2374 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2375 bits<2> op17_16, bits<5> op11_7, bit op4,
2376 InstrItinClass itin, string OpcodeStr, string Dt,
2377 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2378 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2379 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2380 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2382 // Narrow 2-register operations.
2383 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2384 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2385 InstrItinClass itin, string OpcodeStr, string Dt,
2386 ValueType TyD, ValueType TyQ, SDNode OpNode>
2387 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2388 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2389 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2391 // Narrow 2-register intrinsics.
2392 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2393 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2394 InstrItinClass itin, string OpcodeStr, string Dt,
2395 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2396 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2397 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2398 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2400 // Long 2-register operations (currently only used for VMOVL).
2401 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2402 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2403 InstrItinClass itin, string OpcodeStr, string Dt,
2404 ValueType TyQ, ValueType TyD, SDNode OpNode>
2405 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2406 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2407 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2409 // Long 2-register intrinsics.
2410 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2411 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2412 InstrItinClass itin, string OpcodeStr, string Dt,
2413 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2414 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2415 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2416 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2418 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2419 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2420 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2421 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2422 OpcodeStr, Dt, "$Vd, $Vm",
2423 "$src1 = $Vd, $src2 = $Vm", []>;
2424 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2425 InstrItinClass itin, string OpcodeStr, string Dt>
2426 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2427 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2428 "$src1 = $Vd, $src2 = $Vm", []>;
2430 // Basic 3-register operations: double- and quad-register.
2431 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2432 InstrItinClass itin, string OpcodeStr, string Dt,
2433 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2434 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2435 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2436 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2437 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2438 // All of these have a two-operand InstAlias.
2439 let TwoOperandAliasConstraint = "$Vn = $Vd";
2440 let isCommutable = Commutable;
2442 // Same as N3VD but no data type.
2443 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2444 InstrItinClass itin, string OpcodeStr,
2445 ValueType ResTy, ValueType OpTy,
2446 SDNode OpNode, bit Commutable>
2447 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2448 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2449 OpcodeStr, "$Vd, $Vn, $Vm", "",
2450 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2451 // All of these have a two-operand InstAlias.
2452 let TwoOperandAliasConstraint = "$Vn = $Vd";
2453 let isCommutable = Commutable;
2456 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2457 InstrItinClass itin, string OpcodeStr, string Dt,
2458 ValueType Ty, SDNode ShOp>
2459 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2460 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2461 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2463 (Ty (ShOp (Ty DPR:$Vn),
2464 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2465 // All of these have a two-operand InstAlias.
2466 let TwoOperandAliasConstraint = "$Vn = $Vd";
2467 let isCommutable = 0;
2469 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2470 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2471 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2472 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2473 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2475 (Ty (ShOp (Ty DPR:$Vn),
2476 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2477 // All of these have a two-operand InstAlias.
2478 let TwoOperandAliasConstraint = "$Vn = $Vd";
2479 let isCommutable = 0;
2482 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2483 InstrItinClass itin, string OpcodeStr, string Dt,
2484 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2485 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2486 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2487 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2488 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2489 // All of these have a two-operand InstAlias.
2490 let TwoOperandAliasConstraint = "$Vn = $Vd";
2491 let isCommutable = Commutable;
2493 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2494 InstrItinClass itin, string OpcodeStr,
2495 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2496 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2497 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2498 OpcodeStr, "$Vd, $Vn, $Vm", "",
2499 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2500 // All of these have a two-operand InstAlias.
2501 let TwoOperandAliasConstraint = "$Vn = $Vd";
2502 let isCommutable = Commutable;
2504 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2505 InstrItinClass itin, string OpcodeStr, string Dt,
2506 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2507 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2508 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2509 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2510 [(set (ResTy QPR:$Vd),
2511 (ResTy (ShOp (ResTy QPR:$Vn),
2512 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2514 // All of these have a two-operand InstAlias.
2515 let TwoOperandAliasConstraint = "$Vn = $Vd";
2516 let isCommutable = 0;
2518 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2519 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2520 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2521 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2522 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2523 [(set (ResTy QPR:$Vd),
2524 (ResTy (ShOp (ResTy QPR:$Vn),
2525 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2527 // All of these have a two-operand InstAlias.
2528 let TwoOperandAliasConstraint = "$Vn = $Vd";
2529 let isCommutable = 0;
2532 // Basic 3-register intrinsics, both double- and quad-register.
2533 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2534 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2535 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2536 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2537 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2538 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2539 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2540 // All of these have a two-operand InstAlias.
2541 let TwoOperandAliasConstraint = "$Vn = $Vd";
2542 let isCommutable = Commutable;
2544 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2545 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2546 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2547 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2548 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2550 (Ty (IntOp (Ty DPR:$Vn),
2551 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2553 let isCommutable = 0;
2555 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2556 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2557 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2558 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2559 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2561 (Ty (IntOp (Ty DPR:$Vn),
2562 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2563 let isCommutable = 0;
2565 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2566 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2567 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2568 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2569 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2570 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2571 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2572 let TwoOperandAliasConstraint = "$Vm = $Vd";
2573 let isCommutable = 0;
2576 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2577 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2578 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2579 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2580 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2581 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2582 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2583 // All of these have a two-operand InstAlias.
2584 let TwoOperandAliasConstraint = "$Vn = $Vd";
2585 let isCommutable = Commutable;
2587 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2588 string OpcodeStr, string Dt,
2589 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2590 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2591 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2592 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2593 [(set (ResTy QPR:$Vd),
2594 (ResTy (IntOp (ResTy QPR:$Vn),
2595 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2597 let isCommutable = 0;
2599 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2600 string OpcodeStr, string Dt,
2601 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2602 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2603 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2604 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2605 [(set (ResTy QPR:$Vd),
2606 (ResTy (IntOp (ResTy QPR:$Vn),
2607 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2609 let isCommutable = 0;
2611 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2612 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2613 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2614 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2615 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2616 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2617 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2618 let TwoOperandAliasConstraint = "$Vm = $Vd";
2619 let isCommutable = 0;
2622 // Multiply-Add/Sub operations: double- and quad-register.
2623 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2624 InstrItinClass itin, string OpcodeStr, string Dt,
2625 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2626 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2627 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2628 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2629 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2630 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2632 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2633 string OpcodeStr, string Dt,
2634 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2635 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2637 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2639 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2641 (Ty (ShOp (Ty DPR:$src1),
2643 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2645 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2646 string OpcodeStr, string Dt,
2647 ValueType Ty, SDNode MulOp, SDNode ShOp>
2648 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2650 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2652 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2654 (Ty (ShOp (Ty DPR:$src1),
2656 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2659 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2660 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2661 SDPatternOperator MulOp, SDPatternOperator OpNode>
2662 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2663 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2664 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2665 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2666 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2667 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2668 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2669 SDPatternOperator MulOp, SDPatternOperator ShOp>
2670 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2672 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2674 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2675 [(set (ResTy QPR:$Vd),
2676 (ResTy (ShOp (ResTy QPR:$src1),
2677 (ResTy (MulOp QPR:$Vn,
2678 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2680 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2681 string OpcodeStr, string Dt,
2682 ValueType ResTy, ValueType OpTy,
2683 SDNode MulOp, SDNode ShOp>
2684 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2686 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2688 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2689 [(set (ResTy QPR:$Vd),
2690 (ResTy (ShOp (ResTy QPR:$src1),
2691 (ResTy (MulOp QPR:$Vn,
2692 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2695 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2696 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2697 InstrItinClass itin, string OpcodeStr, string Dt,
2698 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2699 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2700 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2701 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2702 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2703 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2704 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2705 InstrItinClass itin, string OpcodeStr, string Dt,
2706 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2707 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2708 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2709 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2710 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2711 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2713 // Neon 3-argument intrinsics, both double- and quad-register.
2714 // The destination register is also used as the first source operand register.
2715 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2716 InstrItinClass itin, string OpcodeStr, string Dt,
2717 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2718 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2719 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2720 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2721 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2722 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2723 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2724 InstrItinClass itin, string OpcodeStr, string Dt,
2725 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2726 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2727 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2728 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2729 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2730 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2732 // Long Multiply-Add/Sub operations.
2733 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2734 InstrItinClass itin, string OpcodeStr, string Dt,
2735 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2736 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2737 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2738 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2739 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2740 (TyQ (MulOp (TyD DPR:$Vn),
2741 (TyD DPR:$Vm)))))]>;
2742 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2743 InstrItinClass itin, string OpcodeStr, string Dt,
2744 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2745 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2746 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2748 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2750 (OpNode (TyQ QPR:$src1),
2751 (TyQ (MulOp (TyD DPR:$Vn),
2752 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2754 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2755 InstrItinClass itin, string OpcodeStr, string Dt,
2756 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2757 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2758 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2760 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2762 (OpNode (TyQ QPR:$src1),
2763 (TyQ (MulOp (TyD DPR:$Vn),
2764 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2767 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2768 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2769 InstrItinClass itin, string OpcodeStr, string Dt,
2770 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2772 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2773 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2774 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2775 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2776 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2777 (TyD DPR:$Vm)))))))]>;
2779 // Neon Long 3-argument intrinsic. The destination register is
2780 // a quad-register and is also used as the first source operand register.
2781 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2782 InstrItinClass itin, string OpcodeStr, string Dt,
2783 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2784 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2785 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2786 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2788 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2789 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2790 string OpcodeStr, string Dt,
2791 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2792 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2794 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2796 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2797 [(set (ResTy QPR:$Vd),
2798 (ResTy (IntOp (ResTy QPR:$src1),
2800 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2802 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2803 InstrItinClass itin, string OpcodeStr, string Dt,
2804 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2805 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2807 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2809 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2810 [(set (ResTy QPR:$Vd),
2811 (ResTy (IntOp (ResTy QPR:$src1),
2813 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2816 // Narrowing 3-register intrinsics.
2817 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2818 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2819 SDPatternOperator IntOp, bit Commutable>
2820 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2821 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2822 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2823 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2824 let isCommutable = Commutable;
2827 // Long 3-register operations.
2828 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2829 InstrItinClass itin, string OpcodeStr, string Dt,
2830 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2831 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2832 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2833 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2834 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2835 let isCommutable = Commutable;
2837 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2838 InstrItinClass itin, string OpcodeStr, string Dt,
2839 ValueType TyQ, ValueType TyD, SDNode OpNode>
2840 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2841 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2842 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2844 (TyQ (OpNode (TyD DPR:$Vn),
2845 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2846 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2847 InstrItinClass itin, string OpcodeStr, string Dt,
2848 ValueType TyQ, ValueType TyD, SDNode OpNode>
2849 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2850 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2851 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2853 (TyQ (OpNode (TyD DPR:$Vn),
2854 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2856 // Long 3-register operations with explicitly extended operands.
2857 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2858 InstrItinClass itin, string OpcodeStr, string Dt,
2859 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2861 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2862 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2863 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2864 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2865 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2866 let isCommutable = Commutable;
2869 // Long 3-register intrinsics with explicit extend (VABDL).
2870 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2871 InstrItinClass itin, string OpcodeStr, string Dt,
2872 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2874 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2875 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2876 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2877 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2878 (TyD DPR:$Vm))))))]> {
2879 let isCommutable = Commutable;
2882 // Long 3-register intrinsics.
2883 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2884 InstrItinClass itin, string OpcodeStr, string Dt,
2885 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
2886 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2887 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2888 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2889 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2890 let isCommutable = Commutable;
2892 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2893 string OpcodeStr, string Dt,
2894 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2895 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2896 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2897 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2898 [(set (ResTy QPR:$Vd),
2899 (ResTy (IntOp (OpTy DPR:$Vn),
2900 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2902 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2903 InstrItinClass itin, string OpcodeStr, string Dt,
2904 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2905 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2906 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2907 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2908 [(set (ResTy QPR:$Vd),
2909 (ResTy (IntOp (OpTy DPR:$Vn),
2910 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2913 // Wide 3-register operations.
2914 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2915 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2916 SDNode OpNode, SDNode ExtOp, bit Commutable>
2917 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2918 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2919 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2920 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2921 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2922 // All of these have a two-operand InstAlias.
2923 let TwoOperandAliasConstraint = "$Vn = $Vd";
2924 let isCommutable = Commutable;
2927 // Pairwise long 2-register intrinsics, both double- and quad-register.
2928 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2929 bits<2> op17_16, bits<5> op11_7, bit op4,
2930 string OpcodeStr, string Dt,
2931 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2932 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2933 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2934 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2935 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2936 bits<2> op17_16, bits<5> op11_7, bit op4,
2937 string OpcodeStr, string Dt,
2938 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2939 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2940 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2941 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2943 // Pairwise long 2-register accumulate intrinsics,
2944 // both double- and quad-register.
2945 // The destination register is also used as the first source operand register.
2946 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2947 bits<2> op17_16, bits<5> op11_7, bit op4,
2948 string OpcodeStr, string Dt,
2949 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2950 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2951 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2952 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2953 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2954 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2955 bits<2> op17_16, bits<5> op11_7, bit op4,
2956 string OpcodeStr, string Dt,
2957 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2958 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2959 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2960 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2961 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2963 // Shift by immediate,
2964 // both double- and quad-register.
2965 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
2966 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2967 Format f, InstrItinClass itin, Operand ImmTy,
2968 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2969 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2970 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2971 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2972 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2973 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2974 Format f, InstrItinClass itin, Operand ImmTy,
2975 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2976 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2977 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2978 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2979 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2982 // Long shift by immediate.
2983 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2984 string OpcodeStr, string Dt,
2985 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2986 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2987 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2988 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2989 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2990 (i32 imm:$SIMM))))]>;
2992 // Narrow shift by immediate.
2993 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2994 InstrItinClass itin, string OpcodeStr, string Dt,
2995 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2996 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2997 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2998 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2999 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3000 (i32 imm:$SIMM))))]>;
3002 // Shift right by immediate and accumulate,
3003 // both double- and quad-register.
3004 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3005 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3006 Operand ImmTy, string OpcodeStr, string Dt,
3007 ValueType Ty, SDNode ShOp>
3008 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3009 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3010 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3011 [(set DPR:$Vd, (Ty (add DPR:$src1,
3012 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3013 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3014 Operand ImmTy, string OpcodeStr, string Dt,
3015 ValueType Ty, SDNode ShOp>
3016 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3017 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3018 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3019 [(set QPR:$Vd, (Ty (add QPR:$src1,
3020 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3023 // Shift by immediate and insert,
3024 // both double- and quad-register.
3025 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3026 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3027 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3028 ValueType Ty,SDNode ShOp>
3029 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3030 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3031 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3032 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3033 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3034 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3035 ValueType Ty,SDNode ShOp>
3036 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3037 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3038 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3039 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3042 // Convert, with fractional bits immediate,
3043 // both double- and quad-register.
3044 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3045 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3046 SDPatternOperator IntOp>
3047 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3048 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3049 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3050 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3051 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3052 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3053 SDPatternOperator IntOp>
3054 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3055 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3056 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3057 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3059 //===----------------------------------------------------------------------===//
3061 //===----------------------------------------------------------------------===//
3063 // Abbreviations used in multiclass suffixes:
3064 // Q = quarter int (8 bit) elements
3065 // H = half int (16 bit) elements
3066 // S = single int (32 bit) elements
3067 // D = double int (64 bit) elements
3069 // Neon 2-register vector operations and intrinsics.
3071 // Neon 2-register comparisons.
3072 // source operand element sizes of 8, 16 and 32 bits:
3073 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3074 bits<5> op11_7, bit op4, string opc, string Dt,
3075 string asm, SDNode OpNode> {
3076 // 64-bit vector types.
3077 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3078 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3079 opc, !strconcat(Dt, "8"), asm, "",
3080 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3081 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3082 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3083 opc, !strconcat(Dt, "16"), asm, "",
3084 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3085 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3086 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3087 opc, !strconcat(Dt, "32"), asm, "",
3088 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3089 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3090 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3091 opc, "f32", asm, "",
3092 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3093 let Inst{10} = 1; // overwrite F = 1
3096 // 128-bit vector types.
3097 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3098 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3099 opc, !strconcat(Dt, "8"), asm, "",
3100 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3101 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3102 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3103 opc, !strconcat(Dt, "16"), asm, "",
3104 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3105 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3106 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3107 opc, !strconcat(Dt, "32"), asm, "",
3108 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3109 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3110 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3111 opc, "f32", asm, "",
3112 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3113 let Inst{10} = 1; // overwrite F = 1
3118 // Neon 2-register vector intrinsics,
3119 // element sizes of 8, 16 and 32 bits:
3120 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3121 bits<5> op11_7, bit op4,
3122 InstrItinClass itinD, InstrItinClass itinQ,
3123 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3124 // 64-bit vector types.
3125 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3126 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3127 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3128 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3129 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3130 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3132 // 128-bit vector types.
3133 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3134 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3135 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3136 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3137 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3138 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3142 // Neon Narrowing 2-register vector operations,
3143 // source operand element sizes of 16, 32 and 64 bits:
3144 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3145 bits<5> op11_7, bit op6, bit op4,
3146 InstrItinClass itin, string OpcodeStr, string Dt,
3148 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3149 itin, OpcodeStr, !strconcat(Dt, "16"),
3150 v8i8, v8i16, OpNode>;
3151 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3152 itin, OpcodeStr, !strconcat(Dt, "32"),
3153 v4i16, v4i32, OpNode>;
3154 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3155 itin, OpcodeStr, !strconcat(Dt, "64"),
3156 v2i32, v2i64, OpNode>;
3159 // Neon Narrowing 2-register vector intrinsics,
3160 // source operand element sizes of 16, 32 and 64 bits:
3161 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3162 bits<5> op11_7, bit op6, bit op4,
3163 InstrItinClass itin, string OpcodeStr, string Dt,
3164 SDPatternOperator IntOp> {
3165 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3166 itin, OpcodeStr, !strconcat(Dt, "16"),
3167 v8i8, v8i16, IntOp>;
3168 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3169 itin, OpcodeStr, !strconcat(Dt, "32"),
3170 v4i16, v4i32, IntOp>;
3171 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3172 itin, OpcodeStr, !strconcat(Dt, "64"),
3173 v2i32, v2i64, IntOp>;
3177 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3178 // source operand element sizes of 16, 32 and 64 bits:
3179 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3180 string OpcodeStr, string Dt, SDNode OpNode> {
3181 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3182 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3183 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3184 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3185 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3186 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3190 // Neon 3-register vector operations.
3192 // First with only element sizes of 8, 16 and 32 bits:
3193 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3194 InstrItinClass itinD16, InstrItinClass itinD32,
3195 InstrItinClass itinQ16, InstrItinClass itinQ32,
3196 string OpcodeStr, string Dt,
3197 SDNode OpNode, bit Commutable = 0> {
3198 // 64-bit vector types.
3199 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3200 OpcodeStr, !strconcat(Dt, "8"),
3201 v8i8, v8i8, OpNode, Commutable>;
3202 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3203 OpcodeStr, !strconcat(Dt, "16"),
3204 v4i16, v4i16, OpNode, Commutable>;
3205 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3206 OpcodeStr, !strconcat(Dt, "32"),
3207 v2i32, v2i32, OpNode, Commutable>;
3209 // 128-bit vector types.
3210 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3211 OpcodeStr, !strconcat(Dt, "8"),
3212 v16i8, v16i8, OpNode, Commutable>;
3213 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3214 OpcodeStr, !strconcat(Dt, "16"),
3215 v8i16, v8i16, OpNode, Commutable>;
3216 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3217 OpcodeStr, !strconcat(Dt, "32"),
3218 v4i32, v4i32, OpNode, Commutable>;
3221 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3222 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3223 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3224 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3225 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3226 v4i32, v2i32, ShOp>;
3229 // ....then also with element size 64 bits:
3230 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3231 InstrItinClass itinD, InstrItinClass itinQ,
3232 string OpcodeStr, string Dt,
3233 SDNode OpNode, bit Commutable = 0>
3234 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3235 OpcodeStr, Dt, OpNode, Commutable> {
3236 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3237 OpcodeStr, !strconcat(Dt, "64"),
3238 v1i64, v1i64, OpNode, Commutable>;
3239 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3240 OpcodeStr, !strconcat(Dt, "64"),
3241 v2i64, v2i64, OpNode, Commutable>;
3245 // Neon 3-register vector intrinsics.
3247 // First with only element sizes of 16 and 32 bits:
3248 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3249 InstrItinClass itinD16, InstrItinClass itinD32,
3250 InstrItinClass itinQ16, InstrItinClass itinQ32,
3251 string OpcodeStr, string Dt,
3252 SDPatternOperator IntOp, bit Commutable = 0> {
3253 // 64-bit vector types.
3254 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3255 OpcodeStr, !strconcat(Dt, "16"),
3256 v4i16, v4i16, IntOp, Commutable>;
3257 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3258 OpcodeStr, !strconcat(Dt, "32"),
3259 v2i32, v2i32, IntOp, Commutable>;
3261 // 128-bit vector types.
3262 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3263 OpcodeStr, !strconcat(Dt, "16"),
3264 v8i16, v8i16, IntOp, Commutable>;
3265 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3266 OpcodeStr, !strconcat(Dt, "32"),
3267 v4i32, v4i32, IntOp, Commutable>;
3269 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3270 InstrItinClass itinD16, InstrItinClass itinD32,
3271 InstrItinClass itinQ16, InstrItinClass itinQ32,
3272 string OpcodeStr, string Dt,
3273 SDPatternOperator IntOp> {
3274 // 64-bit vector types.
3275 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3276 OpcodeStr, !strconcat(Dt, "16"),
3277 v4i16, v4i16, IntOp>;
3278 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3279 OpcodeStr, !strconcat(Dt, "32"),
3280 v2i32, v2i32, IntOp>;
3282 // 128-bit vector types.
3283 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3284 OpcodeStr, !strconcat(Dt, "16"),
3285 v8i16, v8i16, IntOp>;
3286 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3287 OpcodeStr, !strconcat(Dt, "32"),
3288 v4i32, v4i32, IntOp>;
3291 multiclass N3VIntSL_HS<bits<4> op11_8,
3292 InstrItinClass itinD16, InstrItinClass itinD32,
3293 InstrItinClass itinQ16, InstrItinClass itinQ32,
3294 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3295 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3296 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3297 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3298 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3299 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3300 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3301 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3302 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3305 // ....then also with element size of 8 bits:
3306 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3307 InstrItinClass itinD16, InstrItinClass itinD32,
3308 InstrItinClass itinQ16, InstrItinClass itinQ32,
3309 string OpcodeStr, string Dt,
3310 SDPatternOperator IntOp, bit Commutable = 0>
3311 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3312 OpcodeStr, Dt, IntOp, Commutable> {
3313 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3314 OpcodeStr, !strconcat(Dt, "8"),
3315 v8i8, v8i8, IntOp, Commutable>;
3316 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3317 OpcodeStr, !strconcat(Dt, "8"),
3318 v16i8, v16i8, IntOp, Commutable>;
3320 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3321 InstrItinClass itinD16, InstrItinClass itinD32,
3322 InstrItinClass itinQ16, InstrItinClass itinQ32,
3323 string OpcodeStr, string Dt,
3324 SDPatternOperator IntOp>
3325 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3326 OpcodeStr, Dt, IntOp> {
3327 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3328 OpcodeStr, !strconcat(Dt, "8"),
3330 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3331 OpcodeStr, !strconcat(Dt, "8"),
3332 v16i8, v16i8, IntOp>;
3336 // ....then also with element size of 64 bits:
3337 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3338 InstrItinClass itinD16, InstrItinClass itinD32,
3339 InstrItinClass itinQ16, InstrItinClass itinQ32,
3340 string OpcodeStr, string Dt,
3341 SDPatternOperator IntOp, bit Commutable = 0>
3342 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3343 OpcodeStr, Dt, IntOp, Commutable> {
3344 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3345 OpcodeStr, !strconcat(Dt, "64"),
3346 v1i64, v1i64, IntOp, Commutable>;
3347 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3348 OpcodeStr, !strconcat(Dt, "64"),
3349 v2i64, v2i64, IntOp, Commutable>;
3351 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3352 InstrItinClass itinD16, InstrItinClass itinD32,
3353 InstrItinClass itinQ16, InstrItinClass itinQ32,
3354 string OpcodeStr, string Dt,
3355 SDPatternOperator IntOp>
3356 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3357 OpcodeStr, Dt, IntOp> {
3358 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3359 OpcodeStr, !strconcat(Dt, "64"),
3360 v1i64, v1i64, IntOp>;
3361 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3362 OpcodeStr, !strconcat(Dt, "64"),
3363 v2i64, v2i64, IntOp>;
3366 // Neon Narrowing 3-register vector intrinsics,
3367 // source operand element sizes of 16, 32 and 64 bits:
3368 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3369 string OpcodeStr, string Dt,
3370 SDPatternOperator IntOp, bit Commutable = 0> {
3371 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3372 OpcodeStr, !strconcat(Dt, "16"),
3373 v8i8, v8i16, IntOp, Commutable>;
3374 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3375 OpcodeStr, !strconcat(Dt, "32"),
3376 v4i16, v4i32, IntOp, Commutable>;
3377 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3378 OpcodeStr, !strconcat(Dt, "64"),
3379 v2i32, v2i64, IntOp, Commutable>;
3383 // Neon Long 3-register vector operations.
3385 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3386 InstrItinClass itin16, InstrItinClass itin32,
3387 string OpcodeStr, string Dt,
3388 SDNode OpNode, bit Commutable = 0> {
3389 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3390 OpcodeStr, !strconcat(Dt, "8"),
3391 v8i16, v8i8, OpNode, Commutable>;
3392 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3393 OpcodeStr, !strconcat(Dt, "16"),
3394 v4i32, v4i16, OpNode, Commutable>;
3395 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3396 OpcodeStr, !strconcat(Dt, "32"),
3397 v2i64, v2i32, OpNode, Commutable>;
3400 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3401 InstrItinClass itin, string OpcodeStr, string Dt,
3403 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3404 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3405 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3406 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3409 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3410 InstrItinClass itin16, InstrItinClass itin32,
3411 string OpcodeStr, string Dt,
3412 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3413 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3414 OpcodeStr, !strconcat(Dt, "8"),
3415 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3416 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3417 OpcodeStr, !strconcat(Dt, "16"),
3418 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3419 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3420 OpcodeStr, !strconcat(Dt, "32"),
3421 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3424 // Neon Long 3-register vector intrinsics.
3426 // First with only element sizes of 16 and 32 bits:
3427 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3428 InstrItinClass itin16, InstrItinClass itin32,
3429 string OpcodeStr, string Dt,
3430 SDPatternOperator IntOp, bit Commutable = 0> {
3431 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3432 OpcodeStr, !strconcat(Dt, "16"),
3433 v4i32, v4i16, IntOp, Commutable>;
3434 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3435 OpcodeStr, !strconcat(Dt, "32"),
3436 v2i64, v2i32, IntOp, Commutable>;
3439 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3440 InstrItinClass itin, string OpcodeStr, string Dt,
3441 SDPatternOperator IntOp> {
3442 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3443 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3444 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3445 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3448 // ....then also with element size of 8 bits:
3449 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3450 InstrItinClass itin16, InstrItinClass itin32,
3451 string OpcodeStr, string Dt,
3452 SDPatternOperator IntOp, bit Commutable = 0>
3453 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3454 IntOp, Commutable> {
3455 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3456 OpcodeStr, !strconcat(Dt, "8"),
3457 v8i16, v8i8, IntOp, Commutable>;
3460 // ....with explicit extend (VABDL).
3461 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3462 InstrItinClass itin, string OpcodeStr, string Dt,
3463 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3464 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3465 OpcodeStr, !strconcat(Dt, "8"),
3466 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3467 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3468 OpcodeStr, !strconcat(Dt, "16"),
3469 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3470 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3471 OpcodeStr, !strconcat(Dt, "32"),
3472 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3476 // Neon Wide 3-register vector intrinsics,
3477 // source operand element sizes of 8, 16 and 32 bits:
3478 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3479 string OpcodeStr, string Dt,
3480 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3481 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3482 OpcodeStr, !strconcat(Dt, "8"),
3483 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3484 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3485 OpcodeStr, !strconcat(Dt, "16"),
3486 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3487 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3488 OpcodeStr, !strconcat(Dt, "32"),
3489 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3493 // Neon Multiply-Op vector operations,
3494 // element sizes of 8, 16 and 32 bits:
3495 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3496 InstrItinClass itinD16, InstrItinClass itinD32,
3497 InstrItinClass itinQ16, InstrItinClass itinQ32,
3498 string OpcodeStr, string Dt, SDNode OpNode> {
3499 // 64-bit vector types.
3500 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3501 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3502 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3503 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3504 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3505 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3507 // 128-bit vector types.
3508 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3509 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3510 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3511 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3512 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3513 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3516 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3517 InstrItinClass itinD16, InstrItinClass itinD32,
3518 InstrItinClass itinQ16, InstrItinClass itinQ32,
3519 string OpcodeStr, string Dt, SDNode ShOp> {
3520 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3521 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3522 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3523 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3524 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3525 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3527 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3528 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3532 // Neon Intrinsic-Op vector operations,
3533 // element sizes of 8, 16 and 32 bits:
3534 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3535 InstrItinClass itinD, InstrItinClass itinQ,
3536 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3538 // 64-bit vector types.
3539 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3540 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3541 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3542 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3543 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3544 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3546 // 128-bit vector types.
3547 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3548 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3549 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3550 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3551 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3552 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3555 // Neon 3-argument intrinsics,
3556 // element sizes of 8, 16 and 32 bits:
3557 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3558 InstrItinClass itinD, InstrItinClass itinQ,
3559 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3560 // 64-bit vector types.
3561 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3562 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3563 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3564 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3565 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3566 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3568 // 128-bit vector types.
3569 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3570 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3571 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3572 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3573 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3574 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3578 // Neon Long Multiply-Op vector operations,
3579 // element sizes of 8, 16 and 32 bits:
3580 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3581 InstrItinClass itin16, InstrItinClass itin32,
3582 string OpcodeStr, string Dt, SDNode MulOp,
3584 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3585 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3586 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3587 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3588 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3589 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3592 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3593 string Dt, SDNode MulOp, SDNode OpNode> {
3594 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3595 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3596 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3597 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3601 // Neon Long 3-argument intrinsics.
3603 // First with only element sizes of 16 and 32 bits:
3604 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3605 InstrItinClass itin16, InstrItinClass itin32,
3606 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3607 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3608 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3609 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3610 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3613 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3614 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3615 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3616 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3617 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3618 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3621 // ....then also with element size of 8 bits:
3622 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3623 InstrItinClass itin16, InstrItinClass itin32,
3624 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3625 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3626 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3627 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3630 // ....with explicit extend (VABAL).
3631 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3632 InstrItinClass itin, string OpcodeStr, string Dt,
3633 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3634 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3635 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3636 IntOp, ExtOp, OpNode>;
3637 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3638 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3639 IntOp, ExtOp, OpNode>;
3640 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3641 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3642 IntOp, ExtOp, OpNode>;
3646 // Neon Pairwise long 2-register intrinsics,
3647 // element sizes of 8, 16 and 32 bits:
3648 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3649 bits<5> op11_7, bit op4,
3650 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3651 // 64-bit vector types.
3652 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3653 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3654 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3655 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3656 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3657 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3659 // 128-bit vector types.
3660 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3661 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3662 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3663 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3664 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3665 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3669 // Neon Pairwise long 2-register accumulate intrinsics,
3670 // element sizes of 8, 16 and 32 bits:
3671 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3672 bits<5> op11_7, bit op4,
3673 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3674 // 64-bit vector types.
3675 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3676 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3677 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3678 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3679 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3680 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3682 // 128-bit vector types.
3683 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3684 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3685 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3686 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3687 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3688 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3692 // Neon 2-register vector shift by immediate,
3693 // with f of either N2RegVShLFrm or N2RegVShRFrm
3694 // element sizes of 8, 16, 32 and 64 bits:
3695 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3696 InstrItinClass itin, string OpcodeStr, string Dt,
3698 // 64-bit vector types.
3699 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3700 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3701 let Inst{21-19} = 0b001; // imm6 = 001xxx
3703 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3704 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3705 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3707 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3708 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3709 let Inst{21} = 0b1; // imm6 = 1xxxxx
3711 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3712 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3715 // 128-bit vector types.
3716 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3717 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3718 let Inst{21-19} = 0b001; // imm6 = 001xxx
3720 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3721 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3722 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3724 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3725 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3726 let Inst{21} = 0b1; // imm6 = 1xxxxx
3728 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3729 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3732 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3733 InstrItinClass itin, string OpcodeStr, string Dt,
3734 string baseOpc, SDNode OpNode> {
3735 // 64-bit vector types.
3736 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3737 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3738 let Inst{21-19} = 0b001; // imm6 = 001xxx
3740 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3741 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3742 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3744 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3745 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3746 let Inst{21} = 0b1; // imm6 = 1xxxxx
3748 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3749 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3752 // 128-bit vector types.
3753 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3754 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3755 let Inst{21-19} = 0b001; // imm6 = 001xxx
3757 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3758 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3759 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3761 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3762 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3763 let Inst{21} = 0b1; // imm6 = 1xxxxx
3765 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3766 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3770 // Neon Shift-Accumulate vector operations,
3771 // element sizes of 8, 16, 32 and 64 bits:
3772 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3773 string OpcodeStr, string Dt, SDNode ShOp> {
3774 // 64-bit vector types.
3775 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3776 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3777 let Inst{21-19} = 0b001; // imm6 = 001xxx
3779 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3780 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3781 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3783 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3784 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3785 let Inst{21} = 0b1; // imm6 = 1xxxxx
3787 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3788 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3791 // 128-bit vector types.
3792 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3793 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3794 let Inst{21-19} = 0b001; // imm6 = 001xxx
3796 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3797 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3798 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3800 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3801 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3802 let Inst{21} = 0b1; // imm6 = 1xxxxx
3804 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3805 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3809 // Neon Shift-Insert vector operations,
3810 // with f of either N2RegVShLFrm or N2RegVShRFrm
3811 // element sizes of 8, 16, 32 and 64 bits:
3812 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3814 // 64-bit vector types.
3815 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3816 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3817 let Inst{21-19} = 0b001; // imm6 = 001xxx
3819 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3820 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3821 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3823 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3824 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3825 let Inst{21} = 0b1; // imm6 = 1xxxxx
3827 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3828 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3831 // 128-bit vector types.
3832 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3833 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3834 let Inst{21-19} = 0b001; // imm6 = 001xxx
3836 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3837 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3838 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3840 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3841 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3842 let Inst{21} = 0b1; // imm6 = 1xxxxx
3844 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3845 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3848 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3850 // 64-bit vector types.
3851 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3852 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3853 let Inst{21-19} = 0b001; // imm6 = 001xxx
3855 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3856 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3857 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3859 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3860 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3861 let Inst{21} = 0b1; // imm6 = 1xxxxx
3863 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3864 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3867 // 128-bit vector types.
3868 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3869 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3870 let Inst{21-19} = 0b001; // imm6 = 001xxx
3872 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3873 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3874 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3876 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3877 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3878 let Inst{21} = 0b1; // imm6 = 1xxxxx
3880 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3881 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3885 // Neon Shift Long operations,
3886 // element sizes of 8, 16, 32 bits:
3887 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3888 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3889 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3890 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3891 let Inst{21-19} = 0b001; // imm6 = 001xxx
3893 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3894 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3895 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3897 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3898 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3899 let Inst{21} = 0b1; // imm6 = 1xxxxx
3903 // Neon Shift Narrow operations,
3904 // element sizes of 16, 32, 64 bits:
3905 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3906 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3908 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3909 OpcodeStr, !strconcat(Dt, "16"),
3910 v8i8, v8i16, shr_imm8, OpNode> {
3911 let Inst{21-19} = 0b001; // imm6 = 001xxx
3913 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3914 OpcodeStr, !strconcat(Dt, "32"),
3915 v4i16, v4i32, shr_imm16, OpNode> {
3916 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3918 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3919 OpcodeStr, !strconcat(Dt, "64"),
3920 v2i32, v2i64, shr_imm32, OpNode> {
3921 let Inst{21} = 0b1; // imm6 = 1xxxxx
3925 //===----------------------------------------------------------------------===//
3926 // Instruction Definitions.
3927 //===----------------------------------------------------------------------===//
3929 // Vector Add Operations.
3931 // VADD : Vector Add (integer and floating-point)
3932 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3934 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3935 v2f32, v2f32, fadd, 1>;
3936 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3937 v4f32, v4f32, fadd, 1>;
3938 // VADDL : Vector Add Long (Q = D + D)
3939 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3940 "vaddl", "s", add, sext, 1>;
3941 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3942 "vaddl", "u", add, zext, 1>;
3943 // VADDW : Vector Add Wide (Q = Q + D)
3944 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3945 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3946 // VHADD : Vector Halving Add
3947 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3948 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3949 "vhadd", "s", int_arm_neon_vhadds, 1>;
3950 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3951 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3952 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3953 // VRHADD : Vector Rounding Halving Add
3954 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3955 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3956 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3957 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3958 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3959 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3960 // VQADD : Vector Saturating Add
3961 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3962 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3963 "vqadd", "s", int_arm_neon_vqadds, 1>;
3964 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3965 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3966 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3967 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3968 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3969 int_arm_neon_vaddhn, 1>;
3970 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3971 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3972 int_arm_neon_vraddhn, 1>;
3974 // Vector Multiply Operations.
3976 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3977 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3978 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3979 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3980 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3981 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3982 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3983 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3984 v2f32, v2f32, fmul, 1>;
3985 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3986 v4f32, v4f32, fmul, 1>;
3987 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3988 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3989 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3992 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3993 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3994 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3995 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3996 (DSubReg_i16_reg imm:$lane))),
3997 (SubReg_i16_lane imm:$lane)))>;
3998 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3999 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4000 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4001 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4002 (DSubReg_i32_reg imm:$lane))),
4003 (SubReg_i32_lane imm:$lane)))>;
4004 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4005 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4006 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4007 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4008 (DSubReg_i32_reg imm:$lane))),
4009 (SubReg_i32_lane imm:$lane)))>;
4011 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4012 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4013 IIC_VMULi16Q, IIC_VMULi32Q,
4014 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4015 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4016 IIC_VMULi16Q, IIC_VMULi32Q,
4017 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4018 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4019 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4021 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4022 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4023 (DSubReg_i16_reg imm:$lane))),
4024 (SubReg_i16_lane imm:$lane)))>;
4025 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4026 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4028 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4029 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4030 (DSubReg_i32_reg imm:$lane))),
4031 (SubReg_i32_lane imm:$lane)))>;
4033 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4034 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4035 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4036 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4037 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4038 IIC_VMULi16Q, IIC_VMULi32Q,
4039 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4040 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4041 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4043 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4044 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4045 (DSubReg_i16_reg imm:$lane))),
4046 (SubReg_i16_lane imm:$lane)))>;
4047 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4048 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4050 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4051 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4052 (DSubReg_i32_reg imm:$lane))),
4053 (SubReg_i32_lane imm:$lane)))>;
4055 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4056 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4057 "vmull", "s", NEONvmulls, 1>;
4058 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4059 "vmull", "u", NEONvmullu, 1>;
4060 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4061 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4062 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4063 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4065 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4066 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4067 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4068 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4069 "vqdmull", "s", int_arm_neon_vqdmull>;
4071 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4073 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4074 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4075 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4076 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4077 v2f32, fmul_su, fadd_mlx>,
4078 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4079 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4080 v4f32, fmul_su, fadd_mlx>,
4081 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4082 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4083 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4084 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4085 v2f32, fmul_su, fadd_mlx>,
4086 Requires<[HasNEON, UseFPVMLx]>;
4087 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4088 v4f32, v2f32, fmul_su, fadd_mlx>,
4089 Requires<[HasNEON, UseFPVMLx]>;
4091 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4092 (mul (v8i16 QPR:$src2),
4093 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4094 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4095 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4096 (DSubReg_i16_reg imm:$lane))),
4097 (SubReg_i16_lane imm:$lane)))>;
4099 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4100 (mul (v4i32 QPR:$src2),
4101 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4102 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4103 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4104 (DSubReg_i32_reg imm:$lane))),
4105 (SubReg_i32_lane imm:$lane)))>;
4107 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4108 (fmul_su (v4f32 QPR:$src2),
4109 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4110 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4112 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4113 (DSubReg_i32_reg imm:$lane))),
4114 (SubReg_i32_lane imm:$lane)))>,
4115 Requires<[HasNEON, UseFPVMLx]>;
4117 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4118 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4119 "vmlal", "s", NEONvmulls, add>;
4120 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4121 "vmlal", "u", NEONvmullu, add>;
4123 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4124 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4126 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4127 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4128 "vqdmlal", "s", int_arm_neon_vqdmlal>;
4129 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
4131 // VMLS : Vector Multiply Subtract (integer and floating-point)
4132 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4133 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4134 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4135 v2f32, fmul_su, fsub_mlx>,
4136 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4137 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4138 v4f32, fmul_su, fsub_mlx>,
4139 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4140 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4141 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4142 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4143 v2f32, fmul_su, fsub_mlx>,
4144 Requires<[HasNEON, UseFPVMLx]>;
4145 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4146 v4f32, v2f32, fmul_su, fsub_mlx>,
4147 Requires<[HasNEON, UseFPVMLx]>;
4149 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4150 (mul (v8i16 QPR:$src2),
4151 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4152 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4153 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4154 (DSubReg_i16_reg imm:$lane))),
4155 (SubReg_i16_lane imm:$lane)))>;
4157 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4158 (mul (v4i32 QPR:$src2),
4159 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4160 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4161 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4162 (DSubReg_i32_reg imm:$lane))),
4163 (SubReg_i32_lane imm:$lane)))>;
4165 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4166 (fmul_su (v4f32 QPR:$src2),
4167 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4168 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4169 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4170 (DSubReg_i32_reg imm:$lane))),
4171 (SubReg_i32_lane imm:$lane)))>,
4172 Requires<[HasNEON, UseFPVMLx]>;
4174 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4175 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4176 "vmlsl", "s", NEONvmulls, sub>;
4177 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4178 "vmlsl", "u", NEONvmullu, sub>;
4180 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4181 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4183 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4184 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4185 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4186 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4188 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4189 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4190 v2f32, fmul_su, fadd_mlx>,
4191 Requires<[HasVFP4,UseFusedMAC]>;
4193 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4194 v4f32, fmul_su, fadd_mlx>,
4195 Requires<[HasVFP4,UseFusedMAC]>;
4197 // Fused Vector Multiply Subtract (floating-point)
4198 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4199 v2f32, fmul_su, fsub_mlx>,
4200 Requires<[HasVFP4,UseFusedMAC]>;
4201 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4202 v4f32, fmul_su, fsub_mlx>,
4203 Requires<[HasVFP4,UseFusedMAC]>;
4205 // Match @llvm.fma.* intrinsics
4206 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4207 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4208 Requires<[HasVFP4]>;
4209 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4210 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4211 Requires<[HasVFP4]>;
4212 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4213 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4214 Requires<[HasVFP4]>;
4215 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4216 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4217 Requires<[HasVFP4]>;
4219 // Vector Subtract Operations.
4221 // VSUB : Vector Subtract (integer and floating-point)
4222 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4223 "vsub", "i", sub, 0>;
4224 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4225 v2f32, v2f32, fsub, 0>;
4226 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4227 v4f32, v4f32, fsub, 0>;
4228 // VSUBL : Vector Subtract Long (Q = D - D)
4229 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4230 "vsubl", "s", sub, sext, 0>;
4231 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4232 "vsubl", "u", sub, zext, 0>;
4233 // VSUBW : Vector Subtract Wide (Q = Q - D)
4234 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4235 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4236 // VHSUB : Vector Halving Subtract
4237 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4238 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4239 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4240 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4241 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4242 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4243 // VQSUB : Vector Saturing Subtract
4244 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4245 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4246 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4247 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4248 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4249 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4250 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4251 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4252 int_arm_neon_vsubhn, 0>;
4253 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4254 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4255 int_arm_neon_vrsubhn, 0>;
4257 // Vector Comparisons.
4259 // VCEQ : Vector Compare Equal
4260 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4261 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4262 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4264 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4267 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4268 "$Vd, $Vm, #0", NEONvceqz>;
4270 // VCGE : Vector Compare Greater Than or Equal
4271 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4272 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4273 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4274 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4275 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4277 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4280 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4281 "$Vd, $Vm, #0", NEONvcgez>;
4282 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4283 "$Vd, $Vm, #0", NEONvclez>;
4285 // VCGT : Vector Compare Greater Than
4286 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4287 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4288 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4289 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4290 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4292 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4295 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4296 "$Vd, $Vm, #0", NEONvcgtz>;
4297 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4298 "$Vd, $Vm, #0", NEONvcltz>;
4300 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4301 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4302 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4303 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4304 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4305 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4306 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4307 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4308 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4309 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4310 // VTST : Vector Test Bits
4311 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4312 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4314 // Vector Bitwise Operations.
4316 def vnotd : PatFrag<(ops node:$in),
4317 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4318 def vnotq : PatFrag<(ops node:$in),
4319 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4322 // VAND : Vector Bitwise AND
4323 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4324 v2i32, v2i32, and, 1>;
4325 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4326 v4i32, v4i32, and, 1>;
4328 // VEOR : Vector Bitwise Exclusive OR
4329 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4330 v2i32, v2i32, xor, 1>;
4331 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4332 v4i32, v4i32, xor, 1>;
4334 // VORR : Vector Bitwise OR
4335 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4336 v2i32, v2i32, or, 1>;
4337 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4338 v4i32, v4i32, or, 1>;
4340 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4341 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4343 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4345 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4346 let Inst{9} = SIMM{9};
4349 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4350 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4352 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4354 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4355 let Inst{10-9} = SIMM{10-9};
4358 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4359 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4361 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4363 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4364 let Inst{9} = SIMM{9};
4367 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4368 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4370 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4372 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4373 let Inst{10-9} = SIMM{10-9};
4377 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4378 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4379 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4380 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4381 "vbic", "$Vd, $Vn, $Vm", "",
4382 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4383 (vnotd DPR:$Vm))))]>;
4384 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4385 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4386 "vbic", "$Vd, $Vn, $Vm", "",
4387 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4388 (vnotq QPR:$Vm))))]>;
4391 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4392 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4394 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4396 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4397 let Inst{9} = SIMM{9};
4400 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4401 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4403 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4405 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4406 let Inst{10-9} = SIMM{10-9};
4409 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4410 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4412 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4414 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4415 let Inst{9} = SIMM{9};
4418 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4419 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4421 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4423 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4424 let Inst{10-9} = SIMM{10-9};
4427 // VORN : Vector Bitwise OR NOT
4428 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4429 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4430 "vorn", "$Vd, $Vn, $Vm", "",
4431 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4432 (vnotd DPR:$Vm))))]>;
4433 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4434 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4435 "vorn", "$Vd, $Vn, $Vm", "",
4436 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4437 (vnotq QPR:$Vm))))]>;
4439 // VMVN : Vector Bitwise NOT (Immediate)
4441 let isReMaterializable = 1 in {
4443 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4444 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4445 "vmvn", "i16", "$Vd, $SIMM", "",
4446 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4447 let Inst{9} = SIMM{9};
4450 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4451 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4452 "vmvn", "i16", "$Vd, $SIMM", "",
4453 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4454 let Inst{9} = SIMM{9};
4457 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4458 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4459 "vmvn", "i32", "$Vd, $SIMM", "",
4460 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4461 let Inst{11-8} = SIMM{11-8};
4464 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4465 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4466 "vmvn", "i32", "$Vd, $SIMM", "",
4467 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4468 let Inst{11-8} = SIMM{11-8};
4472 // VMVN : Vector Bitwise NOT
4473 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4474 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4475 "vmvn", "$Vd, $Vm", "",
4476 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4477 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4478 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4479 "vmvn", "$Vd, $Vm", "",
4480 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4481 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4482 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4484 // VBSL : Vector Bitwise Select
4485 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4486 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4487 N3RegFrm, IIC_VCNTiD,
4488 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4490 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4492 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4493 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4494 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4496 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4497 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4498 N3RegFrm, IIC_VCNTiQ,
4499 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4501 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4503 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4504 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4505 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4507 // VBIF : Vector Bitwise Insert if False
4508 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4509 // FIXME: This instruction's encoding MAY NOT BE correct.
4510 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4511 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4512 N3RegFrm, IIC_VBINiD,
4513 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4515 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4516 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4517 N3RegFrm, IIC_VBINiQ,
4518 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4521 // VBIT : Vector Bitwise Insert if True
4522 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4523 // FIXME: This instruction's encoding MAY NOT BE correct.
4524 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4525 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4526 N3RegFrm, IIC_VBINiD,
4527 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4529 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4530 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4531 N3RegFrm, IIC_VBINiQ,
4532 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4535 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4536 // for equivalent operations with different register constraints; it just
4539 // Vector Absolute Differences.
4541 // VABD : Vector Absolute Difference
4542 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4543 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4544 "vabd", "s", int_arm_neon_vabds, 1>;
4545 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4546 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4547 "vabd", "u", int_arm_neon_vabdu, 1>;
4548 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4549 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4550 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4551 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4553 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4554 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4555 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4556 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4557 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4559 // VABA : Vector Absolute Difference and Accumulate
4560 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4561 "vaba", "s", int_arm_neon_vabds, add>;
4562 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4563 "vaba", "u", int_arm_neon_vabdu, add>;
4565 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4566 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4567 "vabal", "s", int_arm_neon_vabds, zext, add>;
4568 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4569 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4571 // Vector Maximum and Minimum.
4573 // VMAX : Vector Maximum
4574 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4575 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4576 "vmax", "s", int_arm_neon_vmaxs, 1>;
4577 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4578 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4579 "vmax", "u", int_arm_neon_vmaxu, 1>;
4580 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4582 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4583 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4585 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4587 // VMIN : Vector Minimum
4588 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4589 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4590 "vmin", "s", int_arm_neon_vmins, 1>;
4591 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4592 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4593 "vmin", "u", int_arm_neon_vminu, 1>;
4594 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4596 v2f32, v2f32, int_arm_neon_vmins, 1>;
4597 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4599 v4f32, v4f32, int_arm_neon_vmins, 1>;
4601 // Vector Pairwise Operations.
4603 // VPADD : Vector Pairwise Add
4604 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4606 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4607 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4609 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4610 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4612 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4613 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4614 IIC_VPBIND, "vpadd", "f32",
4615 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4617 // VPADDL : Vector Pairwise Add Long
4618 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4619 int_arm_neon_vpaddls>;
4620 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4621 int_arm_neon_vpaddlu>;
4623 // VPADAL : Vector Pairwise Add and Accumulate Long
4624 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4625 int_arm_neon_vpadals>;
4626 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4627 int_arm_neon_vpadalu>;
4629 // VPMAX : Vector Pairwise Maximum
4630 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4631 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4632 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4633 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4634 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4635 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4636 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4637 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4638 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4639 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4640 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4641 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4642 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4643 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4645 // VPMIN : Vector Pairwise Minimum
4646 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4647 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4648 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4649 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4650 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4651 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4652 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4653 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4654 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4655 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4656 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4657 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4658 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4659 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4661 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4663 // VRECPE : Vector Reciprocal Estimate
4664 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4665 IIC_VUNAD, "vrecpe", "u32",
4666 v2i32, v2i32, int_arm_neon_vrecpe>;
4667 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4668 IIC_VUNAQ, "vrecpe", "u32",
4669 v4i32, v4i32, int_arm_neon_vrecpe>;
4670 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4671 IIC_VUNAD, "vrecpe", "f32",
4672 v2f32, v2f32, int_arm_neon_vrecpe>;
4673 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4674 IIC_VUNAQ, "vrecpe", "f32",
4675 v4f32, v4f32, int_arm_neon_vrecpe>;
4677 // VRECPS : Vector Reciprocal Step
4678 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4679 IIC_VRECSD, "vrecps", "f32",
4680 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4681 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4682 IIC_VRECSQ, "vrecps", "f32",
4683 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4685 // VRSQRTE : Vector Reciprocal Square Root Estimate
4686 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4687 IIC_VUNAD, "vrsqrte", "u32",
4688 v2i32, v2i32, int_arm_neon_vrsqrte>;
4689 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4690 IIC_VUNAQ, "vrsqrte", "u32",
4691 v4i32, v4i32, int_arm_neon_vrsqrte>;
4692 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4693 IIC_VUNAD, "vrsqrte", "f32",
4694 v2f32, v2f32, int_arm_neon_vrsqrte>;
4695 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4696 IIC_VUNAQ, "vrsqrte", "f32",
4697 v4f32, v4f32, int_arm_neon_vrsqrte>;
4699 // VRSQRTS : Vector Reciprocal Square Root Step
4700 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4701 IIC_VRECSD, "vrsqrts", "f32",
4702 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4703 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4704 IIC_VRECSQ, "vrsqrts", "f32",
4705 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4709 // VSHL : Vector Shift
4710 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4711 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4712 "vshl", "s", int_arm_neon_vshifts>;
4713 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4714 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4715 "vshl", "u", int_arm_neon_vshiftu>;
4717 // VSHL : Vector Shift Left (Immediate)
4718 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4720 // VSHR : Vector Shift Right (Immediate)
4721 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4723 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4726 // VSHLL : Vector Shift Left Long
4727 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4728 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4730 // VSHLL : Vector Shift Left Long (with maximum shift count)
4731 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4732 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4733 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4734 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4735 ResTy, OpTy, ImmTy, OpNode> {
4736 let Inst{21-16} = op21_16;
4737 let DecoderMethod = "DecodeVSHLMaxInstruction";
4739 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4740 v8i16, v8i8, imm8, NEONvshlli>;
4741 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4742 v4i32, v4i16, imm16, NEONvshlli>;
4743 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4744 v2i64, v2i32, imm32, NEONvshlli>;
4746 // VSHRN : Vector Shift Right and Narrow
4747 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4750 // VRSHL : Vector Rounding Shift
4751 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4752 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4753 "vrshl", "s", int_arm_neon_vrshifts>;
4754 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4755 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4756 "vrshl", "u", int_arm_neon_vrshiftu>;
4757 // VRSHR : Vector Rounding Shift Right
4758 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
4760 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
4763 // VRSHRN : Vector Rounding Shift Right and Narrow
4764 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4767 // VQSHL : Vector Saturating Shift
4768 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4769 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4770 "vqshl", "s", int_arm_neon_vqshifts>;
4771 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4772 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4773 "vqshl", "u", int_arm_neon_vqshiftu>;
4774 // VQSHL : Vector Saturating Shift Left (Immediate)
4775 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4776 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4778 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4779 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4781 // VQSHRN : Vector Saturating Shift Right and Narrow
4782 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4784 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4787 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4788 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4791 // VQRSHL : Vector Saturating Rounding Shift
4792 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4793 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4794 "vqrshl", "s", int_arm_neon_vqrshifts>;
4795 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4796 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4797 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4799 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4800 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4802 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4805 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4806 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4809 // VSRA : Vector Shift Right and Accumulate
4810 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4811 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4812 // VRSRA : Vector Rounding Shift Right and Accumulate
4813 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4814 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4816 // VSLI : Vector Shift Left and Insert
4817 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4819 // VSRI : Vector Shift Right and Insert
4820 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4822 // Vector Absolute and Saturating Absolute.
4824 // VABS : Vector Absolute Value
4825 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4826 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4828 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4829 IIC_VUNAD, "vabs", "f32",
4830 v2f32, v2f32, int_arm_neon_vabs>;
4831 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4832 IIC_VUNAQ, "vabs", "f32",
4833 v4f32, v4f32, int_arm_neon_vabs>;
4835 // VQABS : Vector Saturating Absolute Value
4836 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4837 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4838 int_arm_neon_vqabs>;
4842 def vnegd : PatFrag<(ops node:$in),
4843 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4844 def vnegq : PatFrag<(ops node:$in),
4845 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4847 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4848 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4849 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4850 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4851 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4852 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4853 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4854 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4856 // VNEG : Vector Negate (integer)
4857 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4858 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4859 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4860 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4861 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4862 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4864 // VNEG : Vector Negate (floating-point)
4865 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4866 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4867 "vneg", "f32", "$Vd, $Vm", "",
4868 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4869 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4870 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4871 "vneg", "f32", "$Vd, $Vm", "",
4872 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4874 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4875 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4876 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4877 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4878 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4879 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4881 // VQNEG : Vector Saturating Negate
4882 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4883 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4884 int_arm_neon_vqneg>;
4886 // Vector Bit Counting Operations.
4888 // VCLS : Vector Count Leading Sign Bits
4889 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4890 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4892 // VCLZ : Vector Count Leading Zeros
4893 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4894 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4896 // VCNT : Vector Count One Bits
4897 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4898 IIC_VCNTiD, "vcnt", "8",
4900 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4901 IIC_VCNTiQ, "vcnt", "8",
4902 v16i8, v16i8, ctpop>;
4905 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4906 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
4907 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
4909 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4910 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
4911 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
4914 // Vector Move Operations.
4916 // VMOV : Vector Move (Register)
4917 def : InstAlias<"vmov${p} $Vd, $Vm",
4918 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4919 def : InstAlias<"vmov${p} $Vd, $Vm",
4920 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4922 // VMOV : Vector Move (Immediate)
4924 let isReMaterializable = 1 in {
4925 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4926 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4927 "vmov", "i8", "$Vd, $SIMM", "",
4928 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4929 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4930 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4931 "vmov", "i8", "$Vd, $SIMM", "",
4932 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4934 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4935 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4936 "vmov", "i16", "$Vd, $SIMM", "",
4937 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4938 let Inst{9} = SIMM{9};
4941 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4942 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4943 "vmov", "i16", "$Vd, $SIMM", "",
4944 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4945 let Inst{9} = SIMM{9};
4948 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4949 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4950 "vmov", "i32", "$Vd, $SIMM", "",
4951 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4952 let Inst{11-8} = SIMM{11-8};
4955 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4956 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4957 "vmov", "i32", "$Vd, $SIMM", "",
4958 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4959 let Inst{11-8} = SIMM{11-8};
4962 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4963 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4964 "vmov", "i64", "$Vd, $SIMM", "",
4965 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4966 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4967 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4968 "vmov", "i64", "$Vd, $SIMM", "",
4969 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4971 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4972 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4973 "vmov", "f32", "$Vd, $SIMM", "",
4974 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4975 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4976 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4977 "vmov", "f32", "$Vd, $SIMM", "",
4978 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4979 } // isReMaterializable
4981 // VMOV : Vector Get Lane (move scalar to ARM core register)
4983 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4984 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4985 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4986 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4988 let Inst{21} = lane{2};
4989 let Inst{6-5} = lane{1-0};
4991 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4992 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4993 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4994 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4996 let Inst{21} = lane{1};
4997 let Inst{6} = lane{0};
4999 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5000 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5001 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5002 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5004 let Inst{21} = lane{2};
5005 let Inst{6-5} = lane{1-0};
5007 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5008 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5009 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5010 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5012 let Inst{21} = lane{1};
5013 let Inst{6} = lane{0};
5015 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5016 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5017 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5018 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5020 let Inst{21} = lane{0};
5022 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5023 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5024 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5025 (DSubReg_i8_reg imm:$lane))),
5026 (SubReg_i8_lane imm:$lane))>;
5027 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5028 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5029 (DSubReg_i16_reg imm:$lane))),
5030 (SubReg_i16_lane imm:$lane))>;
5031 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5032 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5033 (DSubReg_i8_reg imm:$lane))),
5034 (SubReg_i8_lane imm:$lane))>;
5035 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5036 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5037 (DSubReg_i16_reg imm:$lane))),
5038 (SubReg_i16_lane imm:$lane))>;
5039 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5040 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5041 (DSubReg_i32_reg imm:$lane))),
5042 (SubReg_i32_lane imm:$lane))>;
5043 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5044 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5045 (SSubReg_f32_reg imm:$src2))>;
5046 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5047 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5048 (SSubReg_f32_reg imm:$src2))>;
5049 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5050 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5051 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5052 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5055 // VMOV : Vector Set Lane (move ARM core register to scalar)
5057 let Constraints = "$src1 = $V" in {
5058 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5059 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5060 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5061 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5062 GPR:$R, imm:$lane))]> {
5063 let Inst{21} = lane{2};
5064 let Inst{6-5} = lane{1-0};
5066 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5067 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5068 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5069 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5070 GPR:$R, imm:$lane))]> {
5071 let Inst{21} = lane{1};
5072 let Inst{6} = lane{0};
5074 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5075 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5076 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5077 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5078 GPR:$R, imm:$lane))]> {
5079 let Inst{21} = lane{0};
5082 def VSETLNi8Q : PseudoNeonI<(outs QPR:$V),
5083 (ins QPR:$src1, GPR:$R, VectorIndex8:$lane),
5085 [(set QPR:$V, (vector_insert (v16i8 QPR:$src1),
5086 GPR:$R, imm:$lane))]>;
5087 def VSETLNi16Q : PseudoNeonI<(outs QPR:$V),
5088 (ins QPR:$src1, GPR:$R, VectorIndex16:$lane),
5090 [(set QPR:$V, (vector_insert (v8i16 QPR:$src1),
5091 GPR:$R, imm:$lane))]>;
5094 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5095 (v4i32 (INSERT_SUBREG QPR:$src1,
5097 (SSubReg_f32_reg imm:$lane)))>;
5099 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5100 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5101 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5102 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5103 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5104 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5106 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5107 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5108 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5109 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5111 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5112 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5113 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5114 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5115 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5116 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5118 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5119 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5120 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5121 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5122 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5123 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5125 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5126 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5127 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5129 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5130 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5131 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5133 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5134 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5135 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5138 // VDUP : Vector Duplicate (from ARM core register to all elements)
5140 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5141 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5142 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5143 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5144 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5145 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5146 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5147 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5149 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5150 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5151 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
5152 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5153 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5154 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5156 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
5157 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5159 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5161 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5162 ValueType Ty, Operand IdxTy>
5163 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5164 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5165 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5167 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5168 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5169 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5170 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5171 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5172 VectorIndex32:$lane)))]>;
5174 // Inst{19-16} is partially specified depending on the element size.
5176 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5178 let Inst{19-17} = lane{2-0};
5180 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5182 let Inst{19-18} = lane{1-0};
5184 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5186 let Inst{19} = lane{0};
5188 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5190 let Inst{19-17} = lane{2-0};
5192 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5194 let Inst{19-18} = lane{1-0};
5196 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5198 let Inst{19} = lane{0};
5201 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5202 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5204 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5205 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5207 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5208 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5209 (DSubReg_i8_reg imm:$lane))),
5210 (SubReg_i8_lane imm:$lane)))>;
5211 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5212 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5213 (DSubReg_i16_reg imm:$lane))),
5214 (SubReg_i16_lane imm:$lane)))>;
5215 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5216 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5217 (DSubReg_i32_reg imm:$lane))),
5218 (SubReg_i32_lane imm:$lane)))>;
5219 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5220 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5221 (DSubReg_i32_reg imm:$lane))),
5222 (SubReg_i32_lane imm:$lane)))>;
5224 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5225 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5226 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5227 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5229 // VMOVN : Vector Narrowing Move
5230 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5231 "vmovn", "i", trunc>;
5232 // VQMOVN : Vector Saturating Narrowing Move
5233 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5234 "vqmovn", "s", int_arm_neon_vqmovns>;
5235 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5236 "vqmovn", "u", int_arm_neon_vqmovnu>;
5237 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5238 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5239 // VMOVL : Vector Lengthening Move
5240 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5241 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5242 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5243 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5244 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5246 // Vector Conversions.
5248 // VCVT : Vector Convert Between Floating-Point and Integers
5249 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5250 v2i32, v2f32, fp_to_sint>;
5251 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5252 v2i32, v2f32, fp_to_uint>;
5253 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5254 v2f32, v2i32, sint_to_fp>;
5255 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5256 v2f32, v2i32, uint_to_fp>;
5258 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5259 v4i32, v4f32, fp_to_sint>;
5260 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5261 v4i32, v4f32, fp_to_uint>;
5262 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5263 v4f32, v4i32, sint_to_fp>;
5264 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5265 v4f32, v4i32, uint_to_fp>;
5267 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5268 let DecoderMethod = "DecodeVCVTD" in {
5269 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5270 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5271 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5272 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5273 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5274 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5275 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5276 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5279 let DecoderMethod = "DecodeVCVTQ" in {
5280 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5281 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5282 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5283 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5284 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5285 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5286 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5287 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5290 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5291 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5292 IIC_VUNAQ, "vcvt", "f16.f32",
5293 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5294 Requires<[HasNEON, HasFP16]>;
5295 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5296 IIC_VUNAQ, "vcvt", "f32.f16",
5297 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5298 Requires<[HasNEON, HasFP16]>;
5302 // VREV64 : Vector Reverse elements within 64-bit doublewords
5304 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5305 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5306 (ins DPR:$Vm), IIC_VMOVD,
5307 OpcodeStr, Dt, "$Vd, $Vm", "",
5308 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5309 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5310 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5311 (ins QPR:$Vm), IIC_VMOVQ,
5312 OpcodeStr, Dt, "$Vd, $Vm", "",
5313 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5315 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5316 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5317 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5318 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5320 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5321 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5322 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5323 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5325 // VREV32 : Vector Reverse elements within 32-bit words
5327 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5328 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5329 (ins DPR:$Vm), IIC_VMOVD,
5330 OpcodeStr, Dt, "$Vd, $Vm", "",
5331 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5332 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5333 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5334 (ins QPR:$Vm), IIC_VMOVQ,
5335 OpcodeStr, Dt, "$Vd, $Vm", "",
5336 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5338 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5339 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5341 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5342 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5344 // VREV16 : Vector Reverse elements within 16-bit halfwords
5346 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5347 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5348 (ins DPR:$Vm), IIC_VMOVD,
5349 OpcodeStr, Dt, "$Vd, $Vm", "",
5350 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5351 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5352 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5353 (ins QPR:$Vm), IIC_VMOVQ,
5354 OpcodeStr, Dt, "$Vd, $Vm", "",
5355 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5357 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5358 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5360 // Other Vector Shuffles.
5362 // Aligned extractions: really just dropping registers
5364 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5365 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5366 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5368 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5370 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5372 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5374 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5376 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5379 // VEXT : Vector Extract
5382 // All of these have a two-operand InstAlias.
5383 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5384 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5385 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5386 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5387 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5388 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5389 (Ty DPR:$Vm), imm:$index)))]> {
5391 let Inst{11-8} = index{3-0};
5394 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5395 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5396 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5397 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5398 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5399 (Ty QPR:$Vm), imm:$index)))]> {
5401 let Inst{11-8} = index{3-0};
5405 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5406 let Inst{11-8} = index{3-0};
5408 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5409 let Inst{11-9} = index{2-0};
5412 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5413 let Inst{11-10} = index{1-0};
5414 let Inst{9-8} = 0b00;
5416 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5419 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5421 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5422 let Inst{11-8} = index{3-0};
5424 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5425 let Inst{11-9} = index{2-0};
5428 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5429 let Inst{11-10} = index{1-0};
5430 let Inst{9-8} = 0b00;
5432 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5433 let Inst{11} = index{0};
5434 let Inst{10-8} = 0b000;
5436 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5439 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5441 // VTRN : Vector Transpose
5443 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5444 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5445 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5447 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5448 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5449 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5451 // VUZP : Vector Unzip (Deinterleave)
5453 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5454 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5455 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5456 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5457 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5459 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5460 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5461 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5463 // VZIP : Vector Zip (Interleave)
5465 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5466 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5467 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5468 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5469 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5471 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5472 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5473 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5475 // Vector Table Lookup and Table Extension.
5477 // VTBL : Vector Table Lookup
5478 let DecoderMethod = "DecodeTBLInstruction" in {
5480 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5481 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5482 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5483 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5484 let hasExtraSrcRegAllocReq = 1 in {
5486 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5487 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5488 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5490 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5491 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5492 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5494 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5495 (ins VecListFourD:$Vn, DPR:$Vm),
5497 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5498 } // hasExtraSrcRegAllocReq = 1
5501 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5503 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5505 // VTBX : Vector Table Extension
5507 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5508 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5509 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5510 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5511 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5512 let hasExtraSrcRegAllocReq = 1 in {
5514 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5515 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5516 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5518 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5519 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5520 NVTBLFrm, IIC_VTBX3,
5521 "vtbx", "8", "$Vd, $Vn, $Vm",
5524 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5525 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5526 "vtbx", "8", "$Vd, $Vn, $Vm",
5528 } // hasExtraSrcRegAllocReq = 1
5531 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5532 IIC_VTBX3, "$orig = $dst", []>;
5534 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5535 IIC_VTBX4, "$orig = $dst", []>;
5536 } // DecoderMethod = "DecodeTBLInstruction"
5538 //===----------------------------------------------------------------------===//
5539 // NEON instructions for single-precision FP math
5540 //===----------------------------------------------------------------------===//
5542 class N2VSPat<SDNode OpNode, NeonI Inst>
5543 : NEONFPPat<(f32 (OpNode SPR:$a)),
5545 (v2f32 (COPY_TO_REGCLASS (Inst
5547 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5548 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5550 class N3VSPat<SDNode OpNode, NeonI Inst>
5551 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5553 (v2f32 (COPY_TO_REGCLASS (Inst
5555 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5558 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5559 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5561 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5562 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5564 (v2f32 (COPY_TO_REGCLASS (Inst
5566 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5569 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5572 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5573 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5575 def : N3VSPat<fadd, VADDfd>;
5576 def : N3VSPat<fsub, VSUBfd>;
5577 def : N3VSPat<fmul, VMULfd>;
5578 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5579 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5580 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5581 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5582 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
5583 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5584 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
5585 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5586 def : N2VSPat<fabs, VABSfd>;
5587 def : N2VSPat<fneg, VNEGfd>;
5588 def : N3VSPat<NEONfmax, VMAXfd>;
5589 def : N3VSPat<NEONfmin, VMINfd>;
5590 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5591 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5592 def : N2VSPat<arm_sitof, VCVTs2fd>;
5593 def : N2VSPat<arm_uitof, VCVTu2fd>;
5595 //===----------------------------------------------------------------------===//
5596 // Non-Instruction Patterns
5597 //===----------------------------------------------------------------------===//
5600 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5601 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5602 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5603 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5604 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5605 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5606 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5607 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5608 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5609 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5610 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5611 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5612 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5613 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5614 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5615 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5616 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5617 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5618 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5619 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5620 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5621 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5622 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5623 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5624 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5625 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5626 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5627 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5628 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5629 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5631 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5632 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5633 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5634 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5635 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5636 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5637 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5638 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5639 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5640 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5641 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5642 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5643 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5644 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5645 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5646 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5647 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5648 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5649 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5650 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5651 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5652 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5653 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5654 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5655 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5656 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5657 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5658 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5659 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5660 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5662 // Vector lengthening move with load, matching extending loads.
5664 // extload, zextload and sextload for a standard lengthening load. Example:
5665 // Lengthen_Single<"8", "i16", "8"> =
5666 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
5667 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
5668 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
5669 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
5670 let AddedComplexity = 10 in {
5671 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5672 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
5673 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5674 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
5676 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5677 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
5678 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
5679 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
5681 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5682 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
5683 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
5684 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
5688 // extload, zextload and sextload for a lengthening load which only uses
5689 // half the lanes available. Example:
5690 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
5691 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
5692 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5693 // (f64 (IMPLICIT_DEF)), (i32 0))),
5695 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
5696 string InsnLanes, string InsnTy> {
5697 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5698 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
5699 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5700 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5702 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5703 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
5704 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
5705 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5707 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5708 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
5709 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
5710 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5714 // extload, zextload and sextload for a lengthening load followed by another
5715 // lengthening load, to quadruple the initial length.
5717 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
5718 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
5719 // (EXTRACT_SUBREG (VMOVLuv4i32
5720 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5721 // (f64 (IMPLICIT_DEF)),
5725 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
5726 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5728 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5729 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
5730 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5731 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5732 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5734 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5735 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
5736 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5737 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5738 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5740 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5741 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
5742 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5743 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
5744 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5748 // extload, zextload and sextload for a lengthening load followed by another
5749 // lengthening load, to quadruple the initial length, but which ends up only
5750 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
5752 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
5753 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
5754 // (EXTRACT_SUBREG (VMOVLuv4i32
5755 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
5756 // (f64 (IMPLICIT_DEF)), (i32 0))),
5759 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
5760 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5762 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5763 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
5764 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5765 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5766 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5769 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5770 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
5771 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5772 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
5773 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5776 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
5777 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
5778 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5779 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
5780 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5785 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
5786 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
5787 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
5789 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
5790 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
5792 // Double lengthening - v4i8 -> v4i16 -> v4i32
5793 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
5794 // v2i8 -> v2i16 -> v2i32
5795 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
5796 // v2i16 -> v2i32 -> v2i64
5797 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
5799 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
5800 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
5801 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5802 (VLD1LNd16 addrmode6:$addr,
5803 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
5804 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
5805 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
5806 (VLD1LNd16 addrmode6:$addr,
5807 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
5808 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
5809 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
5810 (VLD1LNd16 addrmode6:$addr,
5811 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
5813 //===----------------------------------------------------------------------===//
5814 // Assembler aliases
5817 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5818 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5819 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5820 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5822 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5823 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5824 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5825 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5826 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5827 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5828 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5829 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5830 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5831 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5832 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5833 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5834 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5835 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5836 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5837 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5838 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5839 // ... two-operand aliases
5840 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5841 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5842 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5843 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5844 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5845 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5846 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5847 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5848 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5849 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5850 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5851 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5853 // VLD1 single-lane pseudo-instructions. These need special handling for
5854 // the lane index that an InstAlias can't handle, so we use these instead.
5855 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
5856 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5857 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
5858 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5859 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
5860 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5862 def VLD1LNdWB_fixed_Asm_8 :
5863 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
5864 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5865 def VLD1LNdWB_fixed_Asm_16 :
5866 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
5867 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5868 def VLD1LNdWB_fixed_Asm_32 :
5869 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
5870 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5871 def VLD1LNdWB_register_Asm_8 :
5872 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
5873 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5874 rGPR:$Rm, pred:$p)>;
5875 def VLD1LNdWB_register_Asm_16 :
5876 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
5877 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5878 rGPR:$Rm, pred:$p)>;
5879 def VLD1LNdWB_register_Asm_32 :
5880 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
5881 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5882 rGPR:$Rm, pred:$p)>;
5885 // VST1 single-lane pseudo-instructions. These need special handling for
5886 // the lane index that an InstAlias can't handle, so we use these instead.
5887 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
5888 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5889 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
5890 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5891 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
5892 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5894 def VST1LNdWB_fixed_Asm_8 :
5895 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
5896 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5897 def VST1LNdWB_fixed_Asm_16 :
5898 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
5899 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5900 def VST1LNdWB_fixed_Asm_32 :
5901 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
5902 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5903 def VST1LNdWB_register_Asm_8 :
5904 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
5905 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5906 rGPR:$Rm, pred:$p)>;
5907 def VST1LNdWB_register_Asm_16 :
5908 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
5909 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5910 rGPR:$Rm, pred:$p)>;
5911 def VST1LNdWB_register_Asm_32 :
5912 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
5913 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5914 rGPR:$Rm, pred:$p)>;
5916 // VLD2 single-lane pseudo-instructions. These need special handling for
5917 // the lane index that an InstAlias can't handle, so we use these instead.
5918 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
5919 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5920 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
5921 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5922 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
5923 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5924 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
5925 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5926 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
5927 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5929 def VLD2LNdWB_fixed_Asm_8 :
5930 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
5931 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5932 def VLD2LNdWB_fixed_Asm_16 :
5933 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
5934 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5935 def VLD2LNdWB_fixed_Asm_32 :
5936 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
5937 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5938 def VLD2LNqWB_fixed_Asm_16 :
5939 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
5940 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5941 def VLD2LNqWB_fixed_Asm_32 :
5942 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
5943 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5944 def VLD2LNdWB_register_Asm_8 :
5945 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
5946 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5947 rGPR:$Rm, pred:$p)>;
5948 def VLD2LNdWB_register_Asm_16 :
5949 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
5950 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5951 rGPR:$Rm, pred:$p)>;
5952 def VLD2LNdWB_register_Asm_32 :
5953 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
5954 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5955 rGPR:$Rm, pred:$p)>;
5956 def VLD2LNqWB_register_Asm_16 :
5957 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
5958 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5959 rGPR:$Rm, pred:$p)>;
5960 def VLD2LNqWB_register_Asm_32 :
5961 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
5962 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5963 rGPR:$Rm, pred:$p)>;
5966 // VST2 single-lane pseudo-instructions. These need special handling for
5967 // the lane index that an InstAlias can't handle, so we use these instead.
5968 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
5969 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5970 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
5971 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5972 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
5973 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5974 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
5975 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5976 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
5977 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5979 def VST2LNdWB_fixed_Asm_8 :
5980 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
5981 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5982 def VST2LNdWB_fixed_Asm_16 :
5983 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
5984 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5985 def VST2LNdWB_fixed_Asm_32 :
5986 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
5987 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5988 def VST2LNqWB_fixed_Asm_16 :
5989 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
5990 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5991 def VST2LNqWB_fixed_Asm_32 :
5992 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
5993 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5994 def VST2LNdWB_register_Asm_8 :
5995 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
5996 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5997 rGPR:$Rm, pred:$p)>;
5998 def VST2LNdWB_register_Asm_16 :
5999 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6000 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6001 rGPR:$Rm, pred:$p)>;
6002 def VST2LNdWB_register_Asm_32 :
6003 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6004 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6005 rGPR:$Rm, pred:$p)>;
6006 def VST2LNqWB_register_Asm_16 :
6007 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6008 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6009 rGPR:$Rm, pred:$p)>;
6010 def VST2LNqWB_register_Asm_32 :
6011 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6012 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6013 rGPR:$Rm, pred:$p)>;
6015 // VLD3 all-lanes pseudo-instructions. These need special handling for
6016 // the lane index that an InstAlias can't handle, so we use these instead.
6017 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6018 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6019 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6020 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6021 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6022 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6023 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6024 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6025 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6026 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6027 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6028 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6030 def VLD3DUPdWB_fixed_Asm_8 :
6031 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6032 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6033 def VLD3DUPdWB_fixed_Asm_16 :
6034 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6035 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6036 def VLD3DUPdWB_fixed_Asm_32 :
6037 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6038 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6039 def VLD3DUPqWB_fixed_Asm_8 :
6040 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6041 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6042 def VLD3DUPqWB_fixed_Asm_16 :
6043 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6044 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6045 def VLD3DUPqWB_fixed_Asm_32 :
6046 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6047 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6048 def VLD3DUPdWB_register_Asm_8 :
6049 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6050 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6051 rGPR:$Rm, pred:$p)>;
6052 def VLD3DUPdWB_register_Asm_16 :
6053 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6054 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6055 rGPR:$Rm, pred:$p)>;
6056 def VLD3DUPdWB_register_Asm_32 :
6057 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6058 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6059 rGPR:$Rm, pred:$p)>;
6060 def VLD3DUPqWB_register_Asm_8 :
6061 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6062 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6063 rGPR:$Rm, pred:$p)>;
6064 def VLD3DUPqWB_register_Asm_16 :
6065 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6066 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6067 rGPR:$Rm, pred:$p)>;
6068 def VLD3DUPqWB_register_Asm_32 :
6069 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6070 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6071 rGPR:$Rm, pred:$p)>;
6074 // VLD3 single-lane pseudo-instructions. These need special handling for
6075 // the lane index that an InstAlias can't handle, so we use these instead.
6076 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6077 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6078 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6079 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6080 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6081 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6082 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6083 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6084 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6085 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6087 def VLD3LNdWB_fixed_Asm_8 :
6088 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6089 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6090 def VLD3LNdWB_fixed_Asm_16 :
6091 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6092 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6093 def VLD3LNdWB_fixed_Asm_32 :
6094 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6095 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6096 def VLD3LNqWB_fixed_Asm_16 :
6097 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6098 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6099 def VLD3LNqWB_fixed_Asm_32 :
6100 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6101 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6102 def VLD3LNdWB_register_Asm_8 :
6103 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6104 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6105 rGPR:$Rm, pred:$p)>;
6106 def VLD3LNdWB_register_Asm_16 :
6107 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6108 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6109 rGPR:$Rm, pred:$p)>;
6110 def VLD3LNdWB_register_Asm_32 :
6111 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6112 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6113 rGPR:$Rm, pred:$p)>;
6114 def VLD3LNqWB_register_Asm_16 :
6115 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6116 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6117 rGPR:$Rm, pred:$p)>;
6118 def VLD3LNqWB_register_Asm_32 :
6119 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6120 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6121 rGPR:$Rm, pred:$p)>;
6123 // VLD3 multiple structure pseudo-instructions. These need special handling for
6124 // the vector operands that the normal instructions don't yet model.
6125 // FIXME: Remove these when the register classes and instructions are updated.
6126 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6127 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6128 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6129 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6130 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6131 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6132 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6133 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6134 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6135 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6136 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6137 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6139 def VLD3dWB_fixed_Asm_8 :
6140 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6141 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6142 def VLD3dWB_fixed_Asm_16 :
6143 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6144 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6145 def VLD3dWB_fixed_Asm_32 :
6146 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6147 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6148 def VLD3qWB_fixed_Asm_8 :
6149 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6150 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6151 def VLD3qWB_fixed_Asm_16 :
6152 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6153 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6154 def VLD3qWB_fixed_Asm_32 :
6155 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6156 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6157 def VLD3dWB_register_Asm_8 :
6158 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6159 (ins VecListThreeD:$list, addrmode6:$addr,
6160 rGPR:$Rm, pred:$p)>;
6161 def VLD3dWB_register_Asm_16 :
6162 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6163 (ins VecListThreeD:$list, addrmode6:$addr,
6164 rGPR:$Rm, pred:$p)>;
6165 def VLD3dWB_register_Asm_32 :
6166 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6167 (ins VecListThreeD:$list, addrmode6:$addr,
6168 rGPR:$Rm, pred:$p)>;
6169 def VLD3qWB_register_Asm_8 :
6170 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6171 (ins VecListThreeQ:$list, addrmode6:$addr,
6172 rGPR:$Rm, pred:$p)>;
6173 def VLD3qWB_register_Asm_16 :
6174 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6175 (ins VecListThreeQ:$list, addrmode6:$addr,
6176 rGPR:$Rm, pred:$p)>;
6177 def VLD3qWB_register_Asm_32 :
6178 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6179 (ins VecListThreeQ:$list, addrmode6:$addr,
6180 rGPR:$Rm, pred:$p)>;
6182 // VST3 single-lane pseudo-instructions. These need special handling for
6183 // the lane index that an InstAlias can't handle, so we use these instead.
6184 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6185 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6186 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6187 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6188 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6189 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6190 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6191 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6192 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6193 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6195 def VST3LNdWB_fixed_Asm_8 :
6196 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6197 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6198 def VST3LNdWB_fixed_Asm_16 :
6199 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6200 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6201 def VST3LNdWB_fixed_Asm_32 :
6202 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6203 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6204 def VST3LNqWB_fixed_Asm_16 :
6205 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6206 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6207 def VST3LNqWB_fixed_Asm_32 :
6208 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6209 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6210 def VST3LNdWB_register_Asm_8 :
6211 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6212 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6213 rGPR:$Rm, pred:$p)>;
6214 def VST3LNdWB_register_Asm_16 :
6215 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6216 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6217 rGPR:$Rm, pred:$p)>;
6218 def VST3LNdWB_register_Asm_32 :
6219 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6220 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6221 rGPR:$Rm, pred:$p)>;
6222 def VST3LNqWB_register_Asm_16 :
6223 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6224 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6225 rGPR:$Rm, pred:$p)>;
6226 def VST3LNqWB_register_Asm_32 :
6227 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6228 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6229 rGPR:$Rm, pred:$p)>;
6232 // VST3 multiple structure pseudo-instructions. These need special handling for
6233 // the vector operands that the normal instructions don't yet model.
6234 // FIXME: Remove these when the register classes and instructions are updated.
6235 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6236 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6237 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6238 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6239 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6240 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6241 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6242 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6243 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6244 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6245 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6246 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6248 def VST3dWB_fixed_Asm_8 :
6249 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6250 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6251 def VST3dWB_fixed_Asm_16 :
6252 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6253 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6254 def VST3dWB_fixed_Asm_32 :
6255 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6256 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6257 def VST3qWB_fixed_Asm_8 :
6258 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6259 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6260 def VST3qWB_fixed_Asm_16 :
6261 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6262 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6263 def VST3qWB_fixed_Asm_32 :
6264 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6265 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6266 def VST3dWB_register_Asm_8 :
6267 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6268 (ins VecListThreeD:$list, addrmode6:$addr,
6269 rGPR:$Rm, pred:$p)>;
6270 def VST3dWB_register_Asm_16 :
6271 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6272 (ins VecListThreeD:$list, addrmode6:$addr,
6273 rGPR:$Rm, pred:$p)>;
6274 def VST3dWB_register_Asm_32 :
6275 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6276 (ins VecListThreeD:$list, addrmode6:$addr,
6277 rGPR:$Rm, pred:$p)>;
6278 def VST3qWB_register_Asm_8 :
6279 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6280 (ins VecListThreeQ:$list, addrmode6:$addr,
6281 rGPR:$Rm, pred:$p)>;
6282 def VST3qWB_register_Asm_16 :
6283 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6284 (ins VecListThreeQ:$list, addrmode6:$addr,
6285 rGPR:$Rm, pred:$p)>;
6286 def VST3qWB_register_Asm_32 :
6287 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6288 (ins VecListThreeQ:$list, addrmode6:$addr,
6289 rGPR:$Rm, pred:$p)>;
6291 // VLD4 all-lanes pseudo-instructions. These need special handling for
6292 // the lane index that an InstAlias can't handle, so we use these instead.
6293 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6294 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6295 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6296 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6297 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6298 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6299 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6300 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6301 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6302 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6303 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6304 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6306 def VLD4DUPdWB_fixed_Asm_8 :
6307 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6308 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6309 def VLD4DUPdWB_fixed_Asm_16 :
6310 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6311 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6312 def VLD4DUPdWB_fixed_Asm_32 :
6313 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6314 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6315 def VLD4DUPqWB_fixed_Asm_8 :
6316 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6317 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6318 def VLD4DUPqWB_fixed_Asm_16 :
6319 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6320 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6321 def VLD4DUPqWB_fixed_Asm_32 :
6322 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6323 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6324 def VLD4DUPdWB_register_Asm_8 :
6325 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6326 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6327 rGPR:$Rm, pred:$p)>;
6328 def VLD4DUPdWB_register_Asm_16 :
6329 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6330 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6331 rGPR:$Rm, pred:$p)>;
6332 def VLD4DUPdWB_register_Asm_32 :
6333 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6334 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6335 rGPR:$Rm, pred:$p)>;
6336 def VLD4DUPqWB_register_Asm_8 :
6337 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6338 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6339 rGPR:$Rm, pred:$p)>;
6340 def VLD4DUPqWB_register_Asm_16 :
6341 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6342 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6343 rGPR:$Rm, pred:$p)>;
6344 def VLD4DUPqWB_register_Asm_32 :
6345 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6346 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6347 rGPR:$Rm, pred:$p)>;
6350 // VLD4 single-lane pseudo-instructions. These need special handling for
6351 // the lane index that an InstAlias can't handle, so we use these instead.
6352 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6353 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6354 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6355 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6356 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6357 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6358 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6359 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6360 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6361 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6363 def VLD4LNdWB_fixed_Asm_8 :
6364 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6365 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6366 def VLD4LNdWB_fixed_Asm_16 :
6367 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6368 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6369 def VLD4LNdWB_fixed_Asm_32 :
6370 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6371 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6372 def VLD4LNqWB_fixed_Asm_16 :
6373 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6374 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6375 def VLD4LNqWB_fixed_Asm_32 :
6376 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6377 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6378 def VLD4LNdWB_register_Asm_8 :
6379 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6380 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6381 rGPR:$Rm, pred:$p)>;
6382 def VLD4LNdWB_register_Asm_16 :
6383 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6384 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6385 rGPR:$Rm, pred:$p)>;
6386 def VLD4LNdWB_register_Asm_32 :
6387 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6388 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6389 rGPR:$Rm, pred:$p)>;
6390 def VLD4LNqWB_register_Asm_16 :
6391 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6392 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6393 rGPR:$Rm, pred:$p)>;
6394 def VLD4LNqWB_register_Asm_32 :
6395 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6396 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6397 rGPR:$Rm, pred:$p)>;
6401 // VLD4 multiple structure pseudo-instructions. These need special handling for
6402 // the vector operands that the normal instructions don't yet model.
6403 // FIXME: Remove these when the register classes and instructions are updated.
6404 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6405 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6406 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6407 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6408 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6409 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6410 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6411 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6412 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6413 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6414 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6415 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6417 def VLD4dWB_fixed_Asm_8 :
6418 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6419 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6420 def VLD4dWB_fixed_Asm_16 :
6421 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6422 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6423 def VLD4dWB_fixed_Asm_32 :
6424 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6425 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6426 def VLD4qWB_fixed_Asm_8 :
6427 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6428 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6429 def VLD4qWB_fixed_Asm_16 :
6430 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6431 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6432 def VLD4qWB_fixed_Asm_32 :
6433 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6434 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6435 def VLD4dWB_register_Asm_8 :
6436 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6437 (ins VecListFourD:$list, addrmode6:$addr,
6438 rGPR:$Rm, pred:$p)>;
6439 def VLD4dWB_register_Asm_16 :
6440 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6441 (ins VecListFourD:$list, addrmode6:$addr,
6442 rGPR:$Rm, pred:$p)>;
6443 def VLD4dWB_register_Asm_32 :
6444 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6445 (ins VecListFourD:$list, addrmode6:$addr,
6446 rGPR:$Rm, pred:$p)>;
6447 def VLD4qWB_register_Asm_8 :
6448 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6449 (ins VecListFourQ:$list, addrmode6:$addr,
6450 rGPR:$Rm, pred:$p)>;
6451 def VLD4qWB_register_Asm_16 :
6452 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6453 (ins VecListFourQ:$list, addrmode6:$addr,
6454 rGPR:$Rm, pred:$p)>;
6455 def VLD4qWB_register_Asm_32 :
6456 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6457 (ins VecListFourQ:$list, addrmode6:$addr,
6458 rGPR:$Rm, pred:$p)>;
6460 // VST4 single-lane pseudo-instructions. These need special handling for
6461 // the lane index that an InstAlias can't handle, so we use these instead.
6462 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6463 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6464 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6465 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6466 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6467 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6468 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6469 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6470 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6471 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6473 def VST4LNdWB_fixed_Asm_8 :
6474 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6475 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6476 def VST4LNdWB_fixed_Asm_16 :
6477 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6478 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6479 def VST4LNdWB_fixed_Asm_32 :
6480 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6481 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6482 def VST4LNqWB_fixed_Asm_16 :
6483 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6484 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6485 def VST4LNqWB_fixed_Asm_32 :
6486 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6487 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6488 def VST4LNdWB_register_Asm_8 :
6489 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6490 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6491 rGPR:$Rm, pred:$p)>;
6492 def VST4LNdWB_register_Asm_16 :
6493 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6494 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6495 rGPR:$Rm, pred:$p)>;
6496 def VST4LNdWB_register_Asm_32 :
6497 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6498 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6499 rGPR:$Rm, pred:$p)>;
6500 def VST4LNqWB_register_Asm_16 :
6501 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6502 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6503 rGPR:$Rm, pred:$p)>;
6504 def VST4LNqWB_register_Asm_32 :
6505 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6506 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6507 rGPR:$Rm, pred:$p)>;
6510 // VST4 multiple structure pseudo-instructions. These need special handling for
6511 // the vector operands that the normal instructions don't yet model.
6512 // FIXME: Remove these when the register classes and instructions are updated.
6513 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6514 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6515 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6516 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6517 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6518 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6519 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6520 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6521 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6522 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6523 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6524 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6526 def VST4dWB_fixed_Asm_8 :
6527 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6528 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6529 def VST4dWB_fixed_Asm_16 :
6530 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6531 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6532 def VST4dWB_fixed_Asm_32 :
6533 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6534 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6535 def VST4qWB_fixed_Asm_8 :
6536 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6537 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6538 def VST4qWB_fixed_Asm_16 :
6539 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6540 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6541 def VST4qWB_fixed_Asm_32 :
6542 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6543 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6544 def VST4dWB_register_Asm_8 :
6545 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6546 (ins VecListFourD:$list, addrmode6:$addr,
6547 rGPR:$Rm, pred:$p)>;
6548 def VST4dWB_register_Asm_16 :
6549 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6550 (ins VecListFourD:$list, addrmode6:$addr,
6551 rGPR:$Rm, pred:$p)>;
6552 def VST4dWB_register_Asm_32 :
6553 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6554 (ins VecListFourD:$list, addrmode6:$addr,
6555 rGPR:$Rm, pred:$p)>;
6556 def VST4qWB_register_Asm_8 :
6557 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6558 (ins VecListFourQ:$list, addrmode6:$addr,
6559 rGPR:$Rm, pred:$p)>;
6560 def VST4qWB_register_Asm_16 :
6561 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6562 (ins VecListFourQ:$list, addrmode6:$addr,
6563 rGPR:$Rm, pred:$p)>;
6564 def VST4qWB_register_Asm_32 :
6565 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6566 (ins VecListFourQ:$list, addrmode6:$addr,
6567 rGPR:$Rm, pred:$p)>;
6569 // VMOV takes an optional datatype suffix
6570 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6571 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6572 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6573 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6575 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6576 // D-register versions.
6577 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6578 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6579 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6580 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6581 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6582 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6583 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6584 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6585 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6586 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6587 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6588 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6589 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6590 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6591 // Q-register versions.
6592 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6593 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6594 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6595 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6596 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6597 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6598 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6599 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6600 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6601 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6602 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6603 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6604 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6605 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6607 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6608 // D-register versions.
6609 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
6610 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6611 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
6612 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6613 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
6614 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6615 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
6616 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6617 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
6618 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6619 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
6620 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6621 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
6622 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6623 // Q-register versions.
6624 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
6625 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6626 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
6627 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6628 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
6629 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6630 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
6631 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6632 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
6633 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6634 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
6635 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6636 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
6637 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6639 // VSWP allows, but does not require, a type suffix.
6640 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6641 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
6642 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6643 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6645 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
6646 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6647 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6648 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6649 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6650 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6651 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6652 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6653 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6654 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6655 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6656 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6657 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6659 // "vmov Rd, #-imm" can be handled via "vmvn".
6660 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6661 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6662 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6663 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6664 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6665 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6666 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6667 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6669 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6670 // these should restrict to just the Q register variants, but the register
6671 // classes are enough to match correctly regardless, so we keep it simple
6672 // and just use MnemonicAlias.
6673 def : NEONMnemonicAlias<"vbicq", "vbic">;
6674 def : NEONMnemonicAlias<"vandq", "vand">;
6675 def : NEONMnemonicAlias<"veorq", "veor">;
6676 def : NEONMnemonicAlias<"vorrq", "vorr">;
6678 def : NEONMnemonicAlias<"vmovq", "vmov">;
6679 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
6680 // Explicit versions for floating point so that the FPImm variants get
6681 // handled early. The parser gets confused otherwise.
6682 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6683 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
6685 def : NEONMnemonicAlias<"vaddq", "vadd">;
6686 def : NEONMnemonicAlias<"vsubq", "vsub">;
6688 def : NEONMnemonicAlias<"vminq", "vmin">;
6689 def : NEONMnemonicAlias<"vmaxq", "vmax">;
6691 def : NEONMnemonicAlias<"vmulq", "vmul">;
6693 def : NEONMnemonicAlias<"vabsq", "vabs">;
6695 def : NEONMnemonicAlias<"vshlq", "vshl">;
6696 def : NEONMnemonicAlias<"vshrq", "vshr">;
6698 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6700 def : NEONMnemonicAlias<"vcleq", "vcle">;
6701 def : NEONMnemonicAlias<"vceqq", "vceq">;
6703 def : NEONMnemonicAlias<"vzipq", "vzip">;
6704 def : NEONMnemonicAlias<"vswpq", "vswp">;
6706 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6707 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
6710 // Alias for loading floating point immediates that aren't representable
6711 // using the vmov.f32 encoding but the bitpattern is representable using
6712 // the .i32 encoding.
6713 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6714 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
6715 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6716 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;