1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
23 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
24 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
25 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
26 return ((uint64_t)Imm) < 8;
28 let ParserMatchClass = VectorIndex8Operand;
29 let PrintMethod = "printVectorIndex";
30 let MIOperandInfo = (ops i32imm);
32 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
33 return ((uint64_t)Imm) < 4;
35 let ParserMatchClass = VectorIndex16Operand;
36 let PrintMethod = "printVectorIndex";
37 let MIOperandInfo = (ops i32imm);
39 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
40 return ((uint64_t)Imm) < 2;
42 let ParserMatchClass = VectorIndex32Operand;
43 let PrintMethod = "printVectorIndex";
44 let MIOperandInfo = (ops i32imm);
47 //===----------------------------------------------------------------------===//
48 // NEON-specific DAG Nodes.
49 //===----------------------------------------------------------------------===//
51 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
52 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
54 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
55 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
56 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
57 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
58 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
59 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
60 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
61 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
62 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
63 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
64 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
66 // Types for vector shift by immediates. The "SHX" version is for long and
67 // narrow operations where the source and destination vectors have different
68 // types. The "SHINS" version is for shift and insert operations.
69 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
71 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
73 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
74 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
76 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
77 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
78 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
79 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
80 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
81 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
82 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
84 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
85 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
86 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
88 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
89 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
90 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
91 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
92 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
93 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
95 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
96 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
97 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
99 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
100 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
102 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
104 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
105 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
107 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
108 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
109 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
111 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
113 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
114 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
116 def NEONvbsl : SDNode<"ARMISD::VBSL",
117 SDTypeProfile<1, 3, [SDTCisVec<0>,
120 SDTCisSameAs<0, 3>]>>;
122 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
124 // VDUPLANE can produce a quad-register result from a double-register source,
125 // so the result is not constrained to match the source.
126 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
127 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
130 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
131 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
132 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
134 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
135 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
136 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
137 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
139 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
141 SDTCisSameAs<0, 3>]>;
142 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
143 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
144 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
146 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
147 SDTCisSameAs<1, 2>]>;
148 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
149 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
151 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
152 SDTCisSameAs<0, 2>]>;
153 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
154 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
156 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
157 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
158 unsigned EltBits = 0;
159 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
160 return (EltBits == 32 && EltVal == 0);
163 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
164 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
165 unsigned EltBits = 0;
166 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
167 return (EltBits == 8 && EltVal == 0xff);
170 //===----------------------------------------------------------------------===//
171 // NEON load / store instructions
172 //===----------------------------------------------------------------------===//
174 // Use VLDM to load a Q register as a D register pair.
175 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
177 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
179 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
181 // Use VSTM to store a Q register as a D register pair.
182 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
184 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
186 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
188 // Classes for VLD* pseudo-instructions with multi-register operands.
189 // These are expanded to real instructions after register allocation.
190 class VLDQPseudo<InstrItinClass itin>
191 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
192 class VLDQWBPseudo<InstrItinClass itin>
193 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
194 (ins addrmode6:$addr, am6offset:$offset), itin,
196 class VLDQQPseudo<InstrItinClass itin>
197 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
198 class VLDQQWBPseudo<InstrItinClass itin>
199 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
200 (ins addrmode6:$addr, am6offset:$offset), itin,
202 class VLDQQQQPseudo<InstrItinClass itin>
203 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
205 class VLDQQQQWBPseudo<InstrItinClass itin>
206 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
207 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
208 "$addr.addr = $wb, $src = $dst">;
210 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
212 // VLD1 : Vector Load (multiple single elements)
213 class VLD1D<bits<4> op7_4, string Dt>
214 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
215 (ins addrmode6:$Rn), IIC_VLD1,
216 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
219 let DecoderMethod = "DecodeVLDInstruction";
221 class VLD1Q<bits<4> op7_4, string Dt>
222 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
223 (ins addrmode6:$Rn), IIC_VLD1x2,
224 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
226 let Inst{5-4} = Rn{5-4};
227 let DecoderMethod = "DecodeVLDInstruction";
230 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
231 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
232 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
233 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
235 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
236 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
237 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
238 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
240 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
241 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
242 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
243 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
245 // ...with address register writeback:
246 class VLD1DWB<bits<4> op7_4, string Dt>
247 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
248 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
249 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
250 "$Rn.addr = $wb", []> {
252 let DecoderMethod = "DecodeVLDInstruction";
254 class VLD1QWB<bits<4> op7_4, string Dt>
255 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
256 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
257 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
258 "$Rn.addr = $wb", []> {
259 let Inst{5-4} = Rn{5-4};
260 let DecoderMethod = "DecodeVLDInstruction";
263 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
264 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
265 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
266 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
268 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
269 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
270 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
271 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
273 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
274 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
275 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
276 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
278 // ...with 3 registers (some of these are only for the disassembler):
279 class VLD1D3<bits<4> op7_4, string Dt>
280 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
281 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
282 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
285 let DecoderMethod = "DecodeVLDInstruction";
287 class VLD1D3WB<bits<4> op7_4, string Dt>
288 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
289 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
290 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
292 let DecoderMethod = "DecodeVLDInstruction";
295 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
296 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
297 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
298 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
300 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
301 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
302 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
303 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
305 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
306 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
308 // ...with 4 registers (some of these are only for the disassembler):
309 class VLD1D4<bits<4> op7_4, string Dt>
310 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
311 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
312 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
314 let Inst{5-4} = Rn{5-4};
315 let DecoderMethod = "DecodeVLDInstruction";
317 class VLD1D4WB<bits<4> op7_4, string Dt>
318 : NLdSt<0,0b10,0b0010,op7_4,
319 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
320 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
321 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
323 let Inst{5-4} = Rn{5-4};
324 let DecoderMethod = "DecodeVLDInstruction";
327 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
328 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
329 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
330 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
332 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
333 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
334 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
335 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
337 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
338 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
340 // VLD2 : Vector Load (multiple 2-element structures)
341 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
342 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
343 (ins addrmode6:$Rn), IIC_VLD2,
344 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
346 let Inst{5-4} = Rn{5-4};
347 let DecoderMethod = "DecodeVLDInstruction";
349 class VLD2Q<bits<4> op7_4, string Dt>
350 : NLdSt<0, 0b10, 0b0011, op7_4,
351 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
352 (ins addrmode6:$Rn), IIC_VLD2x2,
353 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
355 let Inst{5-4} = Rn{5-4};
356 let DecoderMethod = "DecodeVLDInstruction";
359 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
360 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
361 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
363 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
364 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
365 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
367 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
368 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
369 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
371 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
372 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
373 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
375 // ...with address register writeback:
376 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
377 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
378 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
379 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
380 "$Rn.addr = $wb", []> {
381 let Inst{5-4} = Rn{5-4};
382 let DecoderMethod = "DecodeVLDInstruction";
384 class VLD2QWB<bits<4> op7_4, string Dt>
385 : NLdSt<0, 0b10, 0b0011, op7_4,
386 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
387 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
388 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
389 "$Rn.addr = $wb", []> {
390 let Inst{5-4} = Rn{5-4};
391 let DecoderMethod = "DecodeVLDInstruction";
394 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
395 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
396 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
398 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
399 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
400 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
402 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
403 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
404 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
406 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
407 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
408 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
410 // ...with double-spaced registers (for disassembly only):
411 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
412 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
413 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
414 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
415 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
416 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
418 // VLD3 : Vector Load (multiple 3-element structures)
419 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
420 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
421 (ins addrmode6:$Rn), IIC_VLD3,
422 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
425 let DecoderMethod = "DecodeVLDInstruction";
428 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
429 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
430 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
432 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
433 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
434 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
436 // ...with address register writeback:
437 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
438 : NLdSt<0, 0b10, op11_8, op7_4,
439 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
440 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
441 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
442 "$Rn.addr = $wb", []> {
444 let DecoderMethod = "DecodeVLDInstruction";
447 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
448 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
449 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
451 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
452 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
453 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
455 // ...with double-spaced registers:
456 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
457 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
458 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
459 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
460 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
461 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
463 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
464 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
465 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
467 // ...alternate versions to be allocated odd register numbers:
468 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
469 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
470 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
472 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
473 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
474 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
476 // VLD4 : Vector Load (multiple 4-element structures)
477 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
478 : NLdSt<0, 0b10, op11_8, op7_4,
479 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
480 (ins addrmode6:$Rn), IIC_VLD4,
481 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
483 let Inst{5-4} = Rn{5-4};
484 let DecoderMethod = "DecodeVLDInstruction";
487 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
488 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
489 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
491 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
492 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
493 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
495 // ...with address register writeback:
496 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
497 : NLdSt<0, 0b10, op11_8, op7_4,
498 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
499 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
500 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
501 "$Rn.addr = $wb", []> {
502 let Inst{5-4} = Rn{5-4};
503 let DecoderMethod = "DecodeVLDInstruction";
506 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
507 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
508 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
510 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
511 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
512 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
514 // ...with double-spaced registers:
515 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
516 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
517 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
518 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
519 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
520 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
522 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
523 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
524 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
526 // ...alternate versions to be allocated odd register numbers:
527 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
528 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
529 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
531 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
532 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
533 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
535 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
537 // Classes for VLD*LN pseudo-instructions with multi-register operands.
538 // These are expanded to real instructions after register allocation.
539 class VLDQLNPseudo<InstrItinClass itin>
540 : PseudoNLdSt<(outs QPR:$dst),
541 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
542 itin, "$src = $dst">;
543 class VLDQLNWBPseudo<InstrItinClass itin>
544 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
545 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
546 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
547 class VLDQQLNPseudo<InstrItinClass itin>
548 : PseudoNLdSt<(outs QQPR:$dst),
549 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
550 itin, "$src = $dst">;
551 class VLDQQLNWBPseudo<InstrItinClass itin>
552 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
553 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
554 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
555 class VLDQQQQLNPseudo<InstrItinClass itin>
556 : PseudoNLdSt<(outs QQQQPR:$dst),
557 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
558 itin, "$src = $dst">;
559 class VLDQQQQLNWBPseudo<InstrItinClass itin>
560 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
561 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
562 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
564 // VLD1LN : Vector Load (single element to one lane)
565 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
567 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
568 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
569 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
571 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
572 (i32 (LoadOp addrmode6:$Rn)),
575 let DecoderMethod = "DecodeVLD1LN";
577 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
579 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
580 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
581 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
583 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
584 (i32 (LoadOp addrmode6oneL32:$Rn)),
587 let DecoderMethod = "DecodeVLD1LN";
589 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
590 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
591 (i32 (LoadOp addrmode6:$addr)),
595 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
596 let Inst{7-5} = lane{2-0};
598 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
599 let Inst{7-6} = lane{1-0};
602 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
603 let Inst{7} = lane{0};
608 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
609 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
610 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
612 def : Pat<(vector_insert (v2f32 DPR:$src),
613 (f32 (load addrmode6:$addr)), imm:$lane),
614 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
615 def : Pat<(vector_insert (v4f32 QPR:$src),
616 (f32 (load addrmode6:$addr)), imm:$lane),
617 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
619 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
621 // ...with address register writeback:
622 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
623 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
624 (ins addrmode6:$Rn, am6offset:$Rm,
625 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
626 "\\{$Vd[$lane]\\}, $Rn$Rm",
627 "$src = $Vd, $Rn.addr = $wb", []> {
628 let DecoderMethod = "DecodeVLD1LN";
631 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
632 let Inst{7-5} = lane{2-0};
634 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
635 let Inst{7-6} = lane{1-0};
638 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
639 let Inst{7} = lane{0};
644 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
645 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
646 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
648 // VLD2LN : Vector Load (single 2-element structure to one lane)
649 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
650 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
651 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
652 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
653 "$src1 = $Vd, $src2 = $dst2", []> {
656 let DecoderMethod = "DecodeVLD2LN";
659 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
660 let Inst{7-5} = lane{2-0};
662 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
663 let Inst{7-6} = lane{1-0};
665 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
666 let Inst{7} = lane{0};
669 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
670 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
671 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
673 // ...with double-spaced registers:
674 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
675 let Inst{7-6} = lane{1-0};
677 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
678 let Inst{7} = lane{0};
681 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
682 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
684 // ...with address register writeback:
685 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
686 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
687 (ins addrmode6:$Rn, am6offset:$Rm,
688 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
689 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
690 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
692 let DecoderMethod = "DecodeVLD2LN";
695 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
696 let Inst{7-5} = lane{2-0};
698 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
699 let Inst{7-6} = lane{1-0};
701 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
702 let Inst{7} = lane{0};
705 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
706 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
707 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
709 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
710 let Inst{7-6} = lane{1-0};
712 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
713 let Inst{7} = lane{0};
716 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
717 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
719 // VLD3LN : Vector Load (single 3-element structure to one lane)
720 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
721 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
722 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
723 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
724 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
725 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
727 let DecoderMethod = "DecodeVLD3LN";
730 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
731 let Inst{7-5} = lane{2-0};
733 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
734 let Inst{7-6} = lane{1-0};
736 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
737 let Inst{7} = lane{0};
740 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
741 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
742 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
744 // ...with double-spaced registers:
745 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
746 let Inst{7-6} = lane{1-0};
748 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
749 let Inst{7} = lane{0};
752 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
753 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
755 // ...with address register writeback:
756 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
757 : NLdStLn<1, 0b10, op11_8, op7_4,
758 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
759 (ins addrmode6:$Rn, am6offset:$Rm,
760 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
761 IIC_VLD3lnu, "vld3", Dt,
762 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
763 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
765 let DecoderMethod = "DecodeVLD3LN";
768 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
769 let Inst{7-5} = lane{2-0};
771 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
772 let Inst{7-6} = lane{1-0};
774 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
775 let Inst{7} = lane{0};
778 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
779 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
780 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
782 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
783 let Inst{7-6} = lane{1-0};
785 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
786 let Inst{7} = lane{0};
789 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
790 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
792 // VLD4LN : Vector Load (single 4-element structure to one lane)
793 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
794 : NLdStLn<1, 0b10, op11_8, op7_4,
795 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
796 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
797 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
798 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
799 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
802 let DecoderMethod = "DecodeVLD4LN";
805 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
806 let Inst{7-5} = lane{2-0};
808 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
809 let Inst{7-6} = lane{1-0};
811 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
812 let Inst{7} = lane{0};
816 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
817 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
818 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
820 // ...with double-spaced registers:
821 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
822 let Inst{7-6} = lane{1-0};
824 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
825 let Inst{7} = lane{0};
829 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
830 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
832 // ...with address register writeback:
833 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
834 : NLdStLn<1, 0b10, op11_8, op7_4,
835 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
836 (ins addrmode6:$Rn, am6offset:$Rm,
837 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
838 IIC_VLD4lnu, "vld4", Dt,
839 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
840 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
843 let DecoderMethod = "DecodeVLD4LN" ;
846 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
847 let Inst{7-5} = lane{2-0};
849 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
850 let Inst{7-6} = lane{1-0};
852 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
853 let Inst{7} = lane{0};
857 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
858 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
859 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
861 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
862 let Inst{7-6} = lane{1-0};
864 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
865 let Inst{7} = lane{0};
869 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
870 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
872 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
874 // VLD1DUP : Vector Load (single element to all lanes)
875 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
876 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
877 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
878 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
881 let DecoderMethod = "DecodeVLD1DupInstruction";
883 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
884 let Pattern = [(set QPR:$dst,
885 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
888 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
889 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
890 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
892 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
893 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
894 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
896 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
897 (VLD1DUPd32 addrmode6:$addr)>;
898 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
899 (VLD1DUPq32Pseudo addrmode6:$addr)>;
901 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
903 class VLD1QDUP<bits<4> op7_4, string Dt>
904 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
905 (ins addrmode6dup:$Rn), IIC_VLD1dup,
906 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
909 let DecoderMethod = "DecodeVLD1DupInstruction";
912 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
913 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
914 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
916 // ...with address register writeback:
917 class VLD1DUPWB<bits<4> op7_4, string Dt>
918 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
919 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
920 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
922 let DecoderMethod = "DecodeVLD1DupInstruction";
924 class VLD1QDUPWB<bits<4> op7_4, string Dt>
925 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
926 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
927 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
929 let DecoderMethod = "DecodeVLD1DupInstruction";
932 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
933 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
934 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
936 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
937 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
938 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
940 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
941 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
942 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
944 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
945 class VLD2DUP<bits<4> op7_4, string Dt>
946 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
947 (ins addrmode6dup:$Rn), IIC_VLD2dup,
948 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
951 let DecoderMethod = "DecodeVLD2DupInstruction";
954 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
955 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
956 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
958 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
959 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
960 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
962 // ...with double-spaced registers (not used for codegen):
963 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
964 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
965 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
967 // ...with address register writeback:
968 class VLD2DUPWB<bits<4> op7_4, string Dt>
969 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
970 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
971 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
973 let DecoderMethod = "DecodeVLD2DupInstruction";
976 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
977 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
978 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
980 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
981 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
982 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
984 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
985 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
986 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
988 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
989 class VLD3DUP<bits<4> op7_4, string Dt>
990 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
991 (ins addrmode6dup:$Rn), IIC_VLD3dup,
992 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
995 let DecoderMethod = "DecodeVLD3DupInstruction";
998 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
999 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1000 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1002 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1003 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1004 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1006 // ...with double-spaced registers (not used for codegen):
1007 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1008 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1009 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1011 // ...with address register writeback:
1012 class VLD3DUPWB<bits<4> op7_4, string Dt>
1013 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1014 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1015 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1016 "$Rn.addr = $wb", []> {
1018 let DecoderMethod = "DecodeVLD3DupInstruction";
1021 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1022 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1023 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1025 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1026 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1027 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1029 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1030 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1031 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1033 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1034 class VLD4DUP<bits<4> op7_4, string Dt>
1035 : NLdSt<1, 0b10, 0b1111, op7_4,
1036 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1037 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1038 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1040 let Inst{4} = Rn{4};
1041 let DecoderMethod = "DecodeVLD4DupInstruction";
1044 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1045 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1046 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1048 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1049 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1050 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1052 // ...with double-spaced registers (not used for codegen):
1053 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1054 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1055 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1057 // ...with address register writeback:
1058 class VLD4DUPWB<bits<4> op7_4, string Dt>
1059 : NLdSt<1, 0b10, 0b1111, op7_4,
1060 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1061 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1062 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1063 "$Rn.addr = $wb", []> {
1064 let Inst{4} = Rn{4};
1065 let DecoderMethod = "DecodeVLD4DupInstruction";
1068 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1069 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1070 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1072 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1073 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1074 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1076 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1077 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1078 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1080 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1082 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1084 // Classes for VST* pseudo-instructions with multi-register operands.
1085 // These are expanded to real instructions after register allocation.
1086 class VSTQPseudo<InstrItinClass itin>
1087 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1088 class VSTQWBPseudo<InstrItinClass itin>
1089 : PseudoNLdSt<(outs GPR:$wb),
1090 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1091 "$addr.addr = $wb">;
1092 class VSTQQPseudo<InstrItinClass itin>
1093 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1094 class VSTQQWBPseudo<InstrItinClass itin>
1095 : PseudoNLdSt<(outs GPR:$wb),
1096 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1097 "$addr.addr = $wb">;
1098 class VSTQQQQPseudo<InstrItinClass itin>
1099 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1100 class VSTQQQQWBPseudo<InstrItinClass itin>
1101 : PseudoNLdSt<(outs GPR:$wb),
1102 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1103 "$addr.addr = $wb">;
1105 // VST1 : Vector Store (multiple single elements)
1106 class VST1D<bits<4> op7_4, string Dt>
1107 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1108 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1110 let Inst{4} = Rn{4};
1111 let DecoderMethod = "DecodeVSTInstruction";
1113 class VST1Q<bits<4> op7_4, string Dt>
1114 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1115 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1116 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1118 let Inst{5-4} = Rn{5-4};
1119 let DecoderMethod = "DecodeVSTInstruction";
1122 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1123 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1124 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1125 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1127 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1128 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1129 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1130 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1132 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1133 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1134 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1135 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1137 // ...with address register writeback:
1138 class VST1DWB<bits<4> op7_4, string Dt>
1139 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1140 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1141 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1142 let Inst{4} = Rn{4};
1143 let DecoderMethod = "DecodeVSTInstruction";
1145 class VST1QWB<bits<4> op7_4, string Dt>
1146 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1147 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1148 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1149 "$Rn.addr = $wb", []> {
1150 let Inst{5-4} = Rn{5-4};
1151 let DecoderMethod = "DecodeVSTInstruction";
1154 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1155 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1156 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1157 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1159 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1160 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1161 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1162 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1164 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1165 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1166 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1167 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1169 // ...with 3 registers (some of these are only for the disassembler):
1170 class VST1D3<bits<4> op7_4, string Dt>
1171 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1172 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1173 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1175 let Inst{4} = Rn{4};
1176 let DecoderMethod = "DecodeVSTInstruction";
1178 class VST1D3WB<bits<4> op7_4, string Dt>
1179 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1180 (ins addrmode6:$Rn, am6offset:$Rm,
1181 DPR:$Vd, DPR:$src2, DPR:$src3),
1182 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1183 "$Rn.addr = $wb", []> {
1184 let Inst{4} = Rn{4};
1185 let DecoderMethod = "DecodeVSTInstruction";
1188 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1189 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1190 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1191 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1193 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1194 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1195 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1196 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1198 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1199 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1201 // ...with 4 registers (some of these are only for the disassembler):
1202 class VST1D4<bits<4> op7_4, string Dt>
1203 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1204 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1205 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1208 let Inst{5-4} = Rn{5-4};
1209 let DecoderMethod = "DecodeVSTInstruction";
1211 class VST1D4WB<bits<4> op7_4, string Dt>
1212 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1213 (ins addrmode6:$Rn, am6offset:$Rm,
1214 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1215 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1216 "$Rn.addr = $wb", []> {
1217 let Inst{5-4} = Rn{5-4};
1218 let DecoderMethod = "DecodeVSTInstruction";
1221 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1222 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1223 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1224 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1226 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1227 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1228 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1229 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1231 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1232 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1234 // VST2 : Vector Store (multiple 2-element structures)
1235 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1236 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1237 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1238 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1240 let Inst{5-4} = Rn{5-4};
1241 let DecoderMethod = "DecodeVSTInstruction";
1243 class VST2Q<bits<4> op7_4, string Dt>
1244 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1245 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1246 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1249 let Inst{5-4} = Rn{5-4};
1250 let DecoderMethod = "DecodeVSTInstruction";
1253 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1254 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1255 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1257 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1258 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1259 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1261 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1262 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1263 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1265 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1266 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1267 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1269 // ...with address register writeback:
1270 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1271 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1272 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1273 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1274 "$Rn.addr = $wb", []> {
1275 let Inst{5-4} = Rn{5-4};
1276 let DecoderMethod = "DecodeVSTInstruction";
1278 class VST2QWB<bits<4> op7_4, string Dt>
1279 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1280 (ins addrmode6:$Rn, am6offset:$Rm,
1281 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1282 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1283 "$Rn.addr = $wb", []> {
1284 let Inst{5-4} = Rn{5-4};
1285 let DecoderMethod = "DecodeVSTInstruction";
1288 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1289 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1290 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1292 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1293 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1294 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1296 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1297 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1298 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1300 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1301 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1302 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1304 // ...with double-spaced registers (for disassembly only):
1305 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1306 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1307 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1308 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1309 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1310 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1312 // VST3 : Vector Store (multiple 3-element structures)
1313 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1314 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1315 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1316 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1318 let Inst{4} = Rn{4};
1319 let DecoderMethod = "DecodeVSTInstruction";
1322 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1323 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1324 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1326 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1327 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1328 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1330 // ...with address register writeback:
1331 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1332 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1333 (ins addrmode6:$Rn, am6offset:$Rm,
1334 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1335 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1336 "$Rn.addr = $wb", []> {
1337 let Inst{4} = Rn{4};
1338 let DecoderMethod = "DecodeVSTInstruction";
1341 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1342 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1343 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1345 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1346 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1347 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1349 // ...with double-spaced registers:
1350 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1351 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1352 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1353 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1354 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1355 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1357 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1358 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1359 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1361 // ...alternate versions to be allocated odd register numbers:
1362 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1363 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1364 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1366 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1367 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1368 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1370 // VST4 : Vector Store (multiple 4-element structures)
1371 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1372 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1373 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1374 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1377 let Inst{5-4} = Rn{5-4};
1378 let DecoderMethod = "DecodeVSTInstruction";
1381 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1382 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1383 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1385 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1386 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1387 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1389 // ...with address register writeback:
1390 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1391 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1392 (ins addrmode6:$Rn, am6offset:$Rm,
1393 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1394 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1395 "$Rn.addr = $wb", []> {
1396 let Inst{5-4} = Rn{5-4};
1397 let DecoderMethod = "DecodeVSTInstruction";
1400 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1401 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1402 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1404 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1405 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1406 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1408 // ...with double-spaced registers:
1409 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1410 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1411 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1412 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1413 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1414 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1416 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1417 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1418 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1420 // ...alternate versions to be allocated odd register numbers:
1421 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1422 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1423 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1425 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1426 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1427 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1429 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1431 // Classes for VST*LN pseudo-instructions with multi-register operands.
1432 // These are expanded to real instructions after register allocation.
1433 class VSTQLNPseudo<InstrItinClass itin>
1434 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1436 class VSTQLNWBPseudo<InstrItinClass itin>
1437 : PseudoNLdSt<(outs GPR:$wb),
1438 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1439 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1440 class VSTQQLNPseudo<InstrItinClass itin>
1441 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1443 class VSTQQLNWBPseudo<InstrItinClass itin>
1444 : PseudoNLdSt<(outs GPR:$wb),
1445 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1446 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1447 class VSTQQQQLNPseudo<InstrItinClass itin>
1448 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1450 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1451 : PseudoNLdSt<(outs GPR:$wb),
1452 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1453 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1455 // VST1LN : Vector Store (single element from one lane)
1456 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1457 PatFrag StoreOp, SDNode ExtractOp>
1458 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1459 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1460 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1461 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1463 let DecoderMethod = "DecodeVST1LN";
1465 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1466 PatFrag StoreOp, SDNode ExtractOp>
1467 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1468 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1469 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1470 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1472 let DecoderMethod = "DecodeVST1LN";
1474 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1475 : VSTQLNPseudo<IIC_VST1ln> {
1476 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1480 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1482 let Inst{7-5} = lane{2-0};
1484 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1486 let Inst{7-6} = lane{1-0};
1487 let Inst{4} = Rn{5};
1490 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1491 let Inst{7} = lane{0};
1492 let Inst{5-4} = Rn{5-4};
1495 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1496 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1497 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1499 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1500 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1501 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1502 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1504 // ...with address register writeback:
1505 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1506 PatFrag StoreOp, SDNode ExtractOp>
1507 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1508 (ins addrmode6:$Rn, am6offset:$Rm,
1509 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1510 "\\{$Vd[$lane]\\}, $Rn$Rm",
1512 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1513 addrmode6:$Rn, am6offset:$Rm))]> {
1514 let DecoderMethod = "DecodeVST1LN";
1516 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1517 : VSTQLNWBPseudo<IIC_VST1lnu> {
1518 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1519 addrmode6:$addr, am6offset:$offset))];
1522 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1524 let Inst{7-5} = lane{2-0};
1526 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1528 let Inst{7-6} = lane{1-0};
1529 let Inst{4} = Rn{5};
1531 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1533 let Inst{7} = lane{0};
1534 let Inst{5-4} = Rn{5-4};
1537 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1538 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1539 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1541 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1543 // VST2LN : Vector Store (single 2-element structure from one lane)
1544 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1545 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1546 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1547 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1550 let Inst{4} = Rn{4};
1551 let DecoderMethod = "DecodeVST2LN";
1554 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1555 let Inst{7-5} = lane{2-0};
1557 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1558 let Inst{7-6} = lane{1-0};
1560 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1561 let Inst{7} = lane{0};
1564 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1565 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1566 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1568 // ...with double-spaced registers:
1569 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1570 let Inst{7-6} = lane{1-0};
1571 let Inst{4} = Rn{4};
1573 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1574 let Inst{7} = lane{0};
1575 let Inst{4} = Rn{4};
1578 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1579 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1581 // ...with address register writeback:
1582 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1583 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1584 (ins addrmode6:$addr, am6offset:$offset,
1585 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1586 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1587 "$addr.addr = $wb", []> {
1588 let Inst{4} = Rn{4};
1589 let DecoderMethod = "DecodeVST2LN";
1592 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1593 let Inst{7-5} = lane{2-0};
1595 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1596 let Inst{7-6} = lane{1-0};
1598 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1599 let Inst{7} = lane{0};
1602 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1603 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1604 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1606 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1607 let Inst{7-6} = lane{1-0};
1609 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1610 let Inst{7} = lane{0};
1613 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1614 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1616 // VST3LN : Vector Store (single 3-element structure from one lane)
1617 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1618 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1619 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1620 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1621 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1623 let DecoderMethod = "DecodeVST3LN";
1626 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1627 let Inst{7-5} = lane{2-0};
1629 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1630 let Inst{7-6} = lane{1-0};
1632 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1633 let Inst{7} = lane{0};
1636 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1637 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1638 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1640 // ...with double-spaced registers:
1641 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1642 let Inst{7-6} = lane{1-0};
1644 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1645 let Inst{7} = lane{0};
1648 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1649 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1651 // ...with address register writeback:
1652 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1653 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1654 (ins addrmode6:$Rn, am6offset:$Rm,
1655 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1656 IIC_VST3lnu, "vst3", Dt,
1657 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1658 "$Rn.addr = $wb", []> {
1659 let DecoderMethod = "DecodeVST3LN";
1662 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1663 let Inst{7-5} = lane{2-0};
1665 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1666 let Inst{7-6} = lane{1-0};
1668 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1669 let Inst{7} = lane{0};
1672 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1673 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1674 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1676 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1677 let Inst{7-6} = lane{1-0};
1679 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1680 let Inst{7} = lane{0};
1683 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1684 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1686 // VST4LN : Vector Store (single 4-element structure from one lane)
1687 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1688 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1689 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1690 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1691 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1694 let Inst{4} = Rn{4};
1695 let DecoderMethod = "DecodeVST4LN";
1698 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1699 let Inst{7-5} = lane{2-0};
1701 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1702 let Inst{7-6} = lane{1-0};
1704 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1705 let Inst{7} = lane{0};
1706 let Inst{5} = Rn{5};
1709 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1710 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1711 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1713 // ...with double-spaced registers:
1714 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1715 let Inst{7-6} = lane{1-0};
1717 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1718 let Inst{7} = lane{0};
1719 let Inst{5} = Rn{5};
1722 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1723 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1725 // ...with address register writeback:
1726 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1727 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1728 (ins addrmode6:$Rn, am6offset:$Rm,
1729 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1730 IIC_VST4lnu, "vst4", Dt,
1731 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1732 "$Rn.addr = $wb", []> {
1733 let Inst{4} = Rn{4};
1734 let DecoderMethod = "DecodeVST4LN";
1737 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1738 let Inst{7-5} = lane{2-0};
1740 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1741 let Inst{7-6} = lane{1-0};
1743 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1744 let Inst{7} = lane{0};
1745 let Inst{5} = Rn{5};
1748 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1749 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1750 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1752 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1753 let Inst{7-6} = lane{1-0};
1755 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1756 let Inst{7} = lane{0};
1757 let Inst{5} = Rn{5};
1760 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1761 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1763 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1766 //===----------------------------------------------------------------------===//
1767 // NEON pattern fragments
1768 //===----------------------------------------------------------------------===//
1770 // Extract D sub-registers of Q registers.
1771 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1772 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1773 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1775 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1776 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1777 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1779 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1780 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1781 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1783 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1784 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1785 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1788 // Extract S sub-registers of Q/D registers.
1789 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1790 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1791 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1794 // Translate lane numbers from Q registers to D subregs.
1795 def SubReg_i8_lane : SDNodeXForm<imm, [{
1796 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1798 def SubReg_i16_lane : SDNodeXForm<imm, [{
1799 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1801 def SubReg_i32_lane : SDNodeXForm<imm, [{
1802 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1805 //===----------------------------------------------------------------------===//
1806 // Instruction Classes
1807 //===----------------------------------------------------------------------===//
1809 // Basic 2-register operations: double- and quad-register.
1810 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1811 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1812 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1813 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1814 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1815 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1816 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1817 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1818 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1819 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1820 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1821 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1823 // Basic 2-register intrinsics, both double- and quad-register.
1824 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1825 bits<2> op17_16, bits<5> op11_7, bit op4,
1826 InstrItinClass itin, string OpcodeStr, string Dt,
1827 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1828 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1829 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1830 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1831 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1832 bits<2> op17_16, bits<5> op11_7, bit op4,
1833 InstrItinClass itin, string OpcodeStr, string Dt,
1834 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1835 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1836 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1837 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1839 // Narrow 2-register operations.
1840 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1841 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1842 InstrItinClass itin, string OpcodeStr, string Dt,
1843 ValueType TyD, ValueType TyQ, SDNode OpNode>
1844 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1845 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1846 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1848 // Narrow 2-register intrinsics.
1849 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1850 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1851 InstrItinClass itin, string OpcodeStr, string Dt,
1852 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1853 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1854 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1855 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1857 // Long 2-register operations (currently only used for VMOVL).
1858 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1859 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1860 InstrItinClass itin, string OpcodeStr, string Dt,
1861 ValueType TyQ, ValueType TyD, SDNode OpNode>
1862 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1863 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1864 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1866 // Long 2-register intrinsics.
1867 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1868 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1869 InstrItinClass itin, string OpcodeStr, string Dt,
1870 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1871 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1872 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1873 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1875 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1876 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1877 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1878 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1879 OpcodeStr, Dt, "$Vd, $Vm",
1880 "$src1 = $Vd, $src2 = $Vm", []>;
1881 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1882 InstrItinClass itin, string OpcodeStr, string Dt>
1883 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1884 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1885 "$src1 = $Vd, $src2 = $Vm", []>;
1887 // Basic 3-register operations: double- and quad-register.
1888 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1889 InstrItinClass itin, string OpcodeStr, string Dt,
1890 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1891 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1892 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1893 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1894 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1895 let isCommutable = Commutable;
1897 // Same as N3VD but no data type.
1898 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1899 InstrItinClass itin, string OpcodeStr,
1900 ValueType ResTy, ValueType OpTy,
1901 SDNode OpNode, bit Commutable>
1902 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1903 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1904 OpcodeStr, "$Vd, $Vn, $Vm", "",
1905 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1906 let isCommutable = Commutable;
1909 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1910 InstrItinClass itin, string OpcodeStr, string Dt,
1911 ValueType Ty, SDNode ShOp>
1912 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1913 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1914 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1916 (Ty (ShOp (Ty DPR:$Vn),
1917 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1918 let isCommutable = 0;
1920 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1921 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1922 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1923 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1924 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1926 (Ty (ShOp (Ty DPR:$Vn),
1927 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1928 let isCommutable = 0;
1931 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1932 InstrItinClass itin, string OpcodeStr, string Dt,
1933 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1934 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1935 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1936 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1937 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1938 let isCommutable = Commutable;
1940 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1941 InstrItinClass itin, string OpcodeStr,
1942 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1943 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1944 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1945 OpcodeStr, "$Vd, $Vn, $Vm", "",
1946 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1947 let isCommutable = Commutable;
1949 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1950 InstrItinClass itin, string OpcodeStr, string Dt,
1951 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1952 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
1953 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1954 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1955 [(set (ResTy QPR:$Vd),
1956 (ResTy (ShOp (ResTy QPR:$Vn),
1957 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1959 let isCommutable = 0;
1961 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1962 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1963 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
1964 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1965 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1966 [(set (ResTy QPR:$Vd),
1967 (ResTy (ShOp (ResTy QPR:$Vn),
1968 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1970 let isCommutable = 0;
1973 // Basic 3-register intrinsics, both double- and quad-register.
1974 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1975 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1976 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1977 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1978 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1979 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1980 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1981 let isCommutable = Commutable;
1983 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1984 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1985 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1986 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1987 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1989 (Ty (IntOp (Ty DPR:$Vn),
1990 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1992 let isCommutable = 0;
1994 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1995 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1996 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1997 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1998 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2000 (Ty (IntOp (Ty DPR:$Vn),
2001 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2002 let isCommutable = 0;
2004 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2005 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2006 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2007 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2008 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2009 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2010 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2011 let isCommutable = 0;
2014 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2015 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2016 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2017 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2018 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2019 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2020 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2021 let isCommutable = Commutable;
2023 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2024 string OpcodeStr, string Dt,
2025 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2026 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2027 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2028 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2029 [(set (ResTy QPR:$Vd),
2030 (ResTy (IntOp (ResTy QPR:$Vn),
2031 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2033 let isCommutable = 0;
2035 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2036 string OpcodeStr, string Dt,
2037 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2038 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2039 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2040 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2041 [(set (ResTy QPR:$Vd),
2042 (ResTy (IntOp (ResTy QPR:$Vn),
2043 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2045 let isCommutable = 0;
2047 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2048 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2049 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2050 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2051 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2052 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2053 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2054 let isCommutable = 0;
2057 // Multiply-Add/Sub operations: double- and quad-register.
2058 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2059 InstrItinClass itin, string OpcodeStr, string Dt,
2060 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2061 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2062 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2063 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2064 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2065 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2067 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2068 string OpcodeStr, string Dt,
2069 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2070 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2072 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2074 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2076 (Ty (ShOp (Ty DPR:$src1),
2078 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2080 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2081 string OpcodeStr, string Dt,
2082 ValueType Ty, SDNode MulOp, SDNode ShOp>
2083 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2085 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2087 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2089 (Ty (ShOp (Ty DPR:$src1),
2091 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2094 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2095 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2096 SDPatternOperator MulOp, SDPatternOperator OpNode>
2097 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2098 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2099 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2100 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2101 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2102 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2103 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2104 SDPatternOperator MulOp, SDPatternOperator ShOp>
2105 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2107 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2109 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2110 [(set (ResTy QPR:$Vd),
2111 (ResTy (ShOp (ResTy QPR:$src1),
2112 (ResTy (MulOp QPR:$Vn,
2113 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2115 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2116 string OpcodeStr, string Dt,
2117 ValueType ResTy, ValueType OpTy,
2118 SDNode MulOp, SDNode ShOp>
2119 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2121 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2123 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2124 [(set (ResTy QPR:$Vd),
2125 (ResTy (ShOp (ResTy QPR:$src1),
2126 (ResTy (MulOp QPR:$Vn,
2127 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2130 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2131 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2132 InstrItinClass itin, string OpcodeStr, string Dt,
2133 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2134 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2135 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2136 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2137 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2138 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2139 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2140 InstrItinClass itin, string OpcodeStr, string Dt,
2141 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2142 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2143 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2144 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2145 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2146 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2148 // Neon 3-argument intrinsics, both double- and quad-register.
2149 // The destination register is also used as the first source operand register.
2150 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2151 InstrItinClass itin, string OpcodeStr, string Dt,
2152 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2153 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2154 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2155 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2156 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2157 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2158 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2159 InstrItinClass itin, string OpcodeStr, string Dt,
2160 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2161 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2162 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2163 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2164 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2165 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2167 // Long Multiply-Add/Sub operations.
2168 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2169 InstrItinClass itin, string OpcodeStr, string Dt,
2170 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2171 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2172 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2173 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2174 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2175 (TyQ (MulOp (TyD DPR:$Vn),
2176 (TyD DPR:$Vm)))))]>;
2177 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2178 InstrItinClass itin, string OpcodeStr, string Dt,
2179 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2180 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2181 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2183 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2185 (OpNode (TyQ QPR:$src1),
2186 (TyQ (MulOp (TyD DPR:$Vn),
2187 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2189 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2190 InstrItinClass itin, string OpcodeStr, string Dt,
2191 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2192 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2193 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2195 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2197 (OpNode (TyQ QPR:$src1),
2198 (TyQ (MulOp (TyD DPR:$Vn),
2199 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2202 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2203 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2204 InstrItinClass itin, string OpcodeStr, string Dt,
2205 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2207 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2208 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2209 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2210 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2211 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2212 (TyD DPR:$Vm)))))))]>;
2214 // Neon Long 3-argument intrinsic. The destination register is
2215 // a quad-register and is also used as the first source operand register.
2216 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2217 InstrItinClass itin, string OpcodeStr, string Dt,
2218 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2219 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2220 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2221 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2223 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2224 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2225 string OpcodeStr, string Dt,
2226 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2227 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2229 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2231 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2232 [(set (ResTy QPR:$Vd),
2233 (ResTy (IntOp (ResTy QPR:$src1),
2235 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2237 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2238 InstrItinClass itin, string OpcodeStr, string Dt,
2239 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2240 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2242 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2244 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2245 [(set (ResTy QPR:$Vd),
2246 (ResTy (IntOp (ResTy QPR:$src1),
2248 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2251 // Narrowing 3-register intrinsics.
2252 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2253 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2254 Intrinsic IntOp, bit Commutable>
2255 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2256 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2257 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2258 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2259 let isCommutable = Commutable;
2262 // Long 3-register operations.
2263 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2264 InstrItinClass itin, string OpcodeStr, string Dt,
2265 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2266 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2267 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2268 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2269 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2270 let isCommutable = Commutable;
2272 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2273 InstrItinClass itin, string OpcodeStr, string Dt,
2274 ValueType TyQ, ValueType TyD, SDNode OpNode>
2275 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2276 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2277 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2279 (TyQ (OpNode (TyD DPR:$Vn),
2280 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2281 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2282 InstrItinClass itin, string OpcodeStr, string Dt,
2283 ValueType TyQ, ValueType TyD, SDNode OpNode>
2284 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2285 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2286 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2288 (TyQ (OpNode (TyD DPR:$Vn),
2289 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2291 // Long 3-register operations with explicitly extended operands.
2292 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2293 InstrItinClass itin, string OpcodeStr, string Dt,
2294 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2296 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2297 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2298 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2299 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2300 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2301 let isCommutable = Commutable;
2304 // Long 3-register intrinsics with explicit extend (VABDL).
2305 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2306 InstrItinClass itin, string OpcodeStr, string Dt,
2307 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2309 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2310 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2311 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2312 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2313 (TyD DPR:$Vm))))))]> {
2314 let isCommutable = Commutable;
2317 // Long 3-register intrinsics.
2318 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2319 InstrItinClass itin, string OpcodeStr, string Dt,
2320 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2321 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2322 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2323 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2324 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2325 let isCommutable = Commutable;
2327 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2328 string OpcodeStr, string Dt,
2329 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2330 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2331 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2332 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2333 [(set (ResTy QPR:$Vd),
2334 (ResTy (IntOp (OpTy DPR:$Vn),
2335 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2337 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2338 InstrItinClass itin, string OpcodeStr, string Dt,
2339 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2340 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2341 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2342 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2343 [(set (ResTy QPR:$Vd),
2344 (ResTy (IntOp (OpTy DPR:$Vn),
2345 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2348 // Wide 3-register operations.
2349 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2350 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2351 SDNode OpNode, SDNode ExtOp, bit Commutable>
2352 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2353 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2354 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2355 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2356 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2357 let isCommutable = Commutable;
2360 // Pairwise long 2-register intrinsics, both double- and quad-register.
2361 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2362 bits<2> op17_16, bits<5> op11_7, bit op4,
2363 string OpcodeStr, string Dt,
2364 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2365 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2366 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2367 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2368 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2369 bits<2> op17_16, bits<5> op11_7, bit op4,
2370 string OpcodeStr, string Dt,
2371 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2372 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2373 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2374 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2376 // Pairwise long 2-register accumulate intrinsics,
2377 // both double- and quad-register.
2378 // The destination register is also used as the first source operand register.
2379 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2380 bits<2> op17_16, bits<5> op11_7, bit op4,
2381 string OpcodeStr, string Dt,
2382 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2383 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2384 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2385 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2386 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2387 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2388 bits<2> op17_16, bits<5> op11_7, bit op4,
2389 string OpcodeStr, string Dt,
2390 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2391 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2392 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2393 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2394 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2396 // Shift by immediate,
2397 // both double- and quad-register.
2398 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2399 Format f, InstrItinClass itin, Operand ImmTy,
2400 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2401 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2402 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2403 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2404 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2405 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2406 Format f, InstrItinClass itin, Operand ImmTy,
2407 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2408 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2409 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2410 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2411 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2413 // Long shift by immediate.
2414 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2415 string OpcodeStr, string Dt,
2416 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2417 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2418 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2419 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2420 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2421 (i32 imm:$SIMM))))]>;
2423 // Narrow shift by immediate.
2424 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2425 InstrItinClass itin, string OpcodeStr, string Dt,
2426 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2427 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2428 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2429 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2430 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2431 (i32 imm:$SIMM))))]>;
2433 // Shift right by immediate and accumulate,
2434 // both double- and quad-register.
2435 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2436 Operand ImmTy, string OpcodeStr, string Dt,
2437 ValueType Ty, SDNode ShOp>
2438 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2439 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2440 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2441 [(set DPR:$Vd, (Ty (add DPR:$src1,
2442 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2443 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2444 Operand ImmTy, string OpcodeStr, string Dt,
2445 ValueType Ty, SDNode ShOp>
2446 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2447 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2448 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2449 [(set QPR:$Vd, (Ty (add QPR:$src1,
2450 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2452 // Shift by immediate and insert,
2453 // both double- and quad-register.
2454 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2455 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2456 ValueType Ty,SDNode ShOp>
2457 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2458 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2459 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2460 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2461 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2462 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2463 ValueType Ty,SDNode ShOp>
2464 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2465 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2466 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2467 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2469 // Convert, with fractional bits immediate,
2470 // both double- and quad-register.
2471 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2472 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2474 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2475 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2476 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2477 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2478 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2479 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2481 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2482 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2483 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2484 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2486 //===----------------------------------------------------------------------===//
2488 //===----------------------------------------------------------------------===//
2490 // Abbreviations used in multiclass suffixes:
2491 // Q = quarter int (8 bit) elements
2492 // H = half int (16 bit) elements
2493 // S = single int (32 bit) elements
2494 // D = double int (64 bit) elements
2496 // Neon 2-register vector operations and intrinsics.
2498 // Neon 2-register comparisons.
2499 // source operand element sizes of 8, 16 and 32 bits:
2500 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2501 bits<5> op11_7, bit op4, string opc, string Dt,
2502 string asm, SDNode OpNode> {
2503 // 64-bit vector types.
2504 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2505 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2506 opc, !strconcat(Dt, "8"), asm, "",
2507 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2508 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2509 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2510 opc, !strconcat(Dt, "16"), asm, "",
2511 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2512 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2513 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2514 opc, !strconcat(Dt, "32"), asm, "",
2515 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2516 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2517 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2518 opc, "f32", asm, "",
2519 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2520 let Inst{10} = 1; // overwrite F = 1
2523 // 128-bit vector types.
2524 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2525 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2526 opc, !strconcat(Dt, "8"), asm, "",
2527 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2528 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2529 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2530 opc, !strconcat(Dt, "16"), asm, "",
2531 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2532 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2533 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2534 opc, !strconcat(Dt, "32"), asm, "",
2535 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2536 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2537 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2538 opc, "f32", asm, "",
2539 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2540 let Inst{10} = 1; // overwrite F = 1
2545 // Neon 2-register vector intrinsics,
2546 // element sizes of 8, 16 and 32 bits:
2547 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2548 bits<5> op11_7, bit op4,
2549 InstrItinClass itinD, InstrItinClass itinQ,
2550 string OpcodeStr, string Dt, Intrinsic IntOp> {
2551 // 64-bit vector types.
2552 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2553 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2554 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2555 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2556 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2557 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2559 // 128-bit vector types.
2560 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2561 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2562 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2563 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2564 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2565 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2569 // Neon Narrowing 2-register vector operations,
2570 // source operand element sizes of 16, 32 and 64 bits:
2571 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2572 bits<5> op11_7, bit op6, bit op4,
2573 InstrItinClass itin, string OpcodeStr, string Dt,
2575 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2576 itin, OpcodeStr, !strconcat(Dt, "16"),
2577 v8i8, v8i16, OpNode>;
2578 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2579 itin, OpcodeStr, !strconcat(Dt, "32"),
2580 v4i16, v4i32, OpNode>;
2581 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2582 itin, OpcodeStr, !strconcat(Dt, "64"),
2583 v2i32, v2i64, OpNode>;
2586 // Neon Narrowing 2-register vector intrinsics,
2587 // source operand element sizes of 16, 32 and 64 bits:
2588 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2589 bits<5> op11_7, bit op6, bit op4,
2590 InstrItinClass itin, string OpcodeStr, string Dt,
2592 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2593 itin, OpcodeStr, !strconcat(Dt, "16"),
2594 v8i8, v8i16, IntOp>;
2595 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2596 itin, OpcodeStr, !strconcat(Dt, "32"),
2597 v4i16, v4i32, IntOp>;
2598 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2599 itin, OpcodeStr, !strconcat(Dt, "64"),
2600 v2i32, v2i64, IntOp>;
2604 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2605 // source operand element sizes of 16, 32 and 64 bits:
2606 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2607 string OpcodeStr, string Dt, SDNode OpNode> {
2608 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2609 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2610 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2611 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2612 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2613 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2617 // Neon 3-register vector operations.
2619 // First with only element sizes of 8, 16 and 32 bits:
2620 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2621 InstrItinClass itinD16, InstrItinClass itinD32,
2622 InstrItinClass itinQ16, InstrItinClass itinQ32,
2623 string OpcodeStr, string Dt,
2624 SDNode OpNode, bit Commutable = 0> {
2625 // 64-bit vector types.
2626 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2627 OpcodeStr, !strconcat(Dt, "8"),
2628 v8i8, v8i8, OpNode, Commutable>;
2629 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2630 OpcodeStr, !strconcat(Dt, "16"),
2631 v4i16, v4i16, OpNode, Commutable>;
2632 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2633 OpcodeStr, !strconcat(Dt, "32"),
2634 v2i32, v2i32, OpNode, Commutable>;
2636 // 128-bit vector types.
2637 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2638 OpcodeStr, !strconcat(Dt, "8"),
2639 v16i8, v16i8, OpNode, Commutable>;
2640 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2641 OpcodeStr, !strconcat(Dt, "16"),
2642 v8i16, v8i16, OpNode, Commutable>;
2643 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2644 OpcodeStr, !strconcat(Dt, "32"),
2645 v4i32, v4i32, OpNode, Commutable>;
2648 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2649 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2651 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2653 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2654 v8i16, v4i16, ShOp>;
2655 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2656 v4i32, v2i32, ShOp>;
2659 // ....then also with element size 64 bits:
2660 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2661 InstrItinClass itinD, InstrItinClass itinQ,
2662 string OpcodeStr, string Dt,
2663 SDNode OpNode, bit Commutable = 0>
2664 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2665 OpcodeStr, Dt, OpNode, Commutable> {
2666 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2667 OpcodeStr, !strconcat(Dt, "64"),
2668 v1i64, v1i64, OpNode, Commutable>;
2669 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2670 OpcodeStr, !strconcat(Dt, "64"),
2671 v2i64, v2i64, OpNode, Commutable>;
2675 // Neon 3-register vector intrinsics.
2677 // First with only element sizes of 16 and 32 bits:
2678 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2679 InstrItinClass itinD16, InstrItinClass itinD32,
2680 InstrItinClass itinQ16, InstrItinClass itinQ32,
2681 string OpcodeStr, string Dt,
2682 Intrinsic IntOp, bit Commutable = 0> {
2683 // 64-bit vector types.
2684 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2685 OpcodeStr, !strconcat(Dt, "16"),
2686 v4i16, v4i16, IntOp, Commutable>;
2687 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2688 OpcodeStr, !strconcat(Dt, "32"),
2689 v2i32, v2i32, IntOp, Commutable>;
2691 // 128-bit vector types.
2692 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2693 OpcodeStr, !strconcat(Dt, "16"),
2694 v8i16, v8i16, IntOp, Commutable>;
2695 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2696 OpcodeStr, !strconcat(Dt, "32"),
2697 v4i32, v4i32, IntOp, Commutable>;
2699 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2700 InstrItinClass itinD16, InstrItinClass itinD32,
2701 InstrItinClass itinQ16, InstrItinClass itinQ32,
2702 string OpcodeStr, string Dt,
2704 // 64-bit vector types.
2705 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2706 OpcodeStr, !strconcat(Dt, "16"),
2707 v4i16, v4i16, IntOp>;
2708 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2709 OpcodeStr, !strconcat(Dt, "32"),
2710 v2i32, v2i32, IntOp>;
2712 // 128-bit vector types.
2713 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2714 OpcodeStr, !strconcat(Dt, "16"),
2715 v8i16, v8i16, IntOp>;
2716 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2717 OpcodeStr, !strconcat(Dt, "32"),
2718 v4i32, v4i32, IntOp>;
2721 multiclass N3VIntSL_HS<bits<4> op11_8,
2722 InstrItinClass itinD16, InstrItinClass itinD32,
2723 InstrItinClass itinQ16, InstrItinClass itinQ32,
2724 string OpcodeStr, string Dt, Intrinsic IntOp> {
2725 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2726 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2727 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2728 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2729 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2730 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2731 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2732 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2735 // ....then also with element size of 8 bits:
2736 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2737 InstrItinClass itinD16, InstrItinClass itinD32,
2738 InstrItinClass itinQ16, InstrItinClass itinQ32,
2739 string OpcodeStr, string Dt,
2740 Intrinsic IntOp, bit Commutable = 0>
2741 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2742 OpcodeStr, Dt, IntOp, Commutable> {
2743 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2744 OpcodeStr, !strconcat(Dt, "8"),
2745 v8i8, v8i8, IntOp, Commutable>;
2746 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2747 OpcodeStr, !strconcat(Dt, "8"),
2748 v16i8, v16i8, IntOp, Commutable>;
2750 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2751 InstrItinClass itinD16, InstrItinClass itinD32,
2752 InstrItinClass itinQ16, InstrItinClass itinQ32,
2753 string OpcodeStr, string Dt,
2755 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2756 OpcodeStr, Dt, IntOp> {
2757 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2758 OpcodeStr, !strconcat(Dt, "8"),
2760 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2761 OpcodeStr, !strconcat(Dt, "8"),
2762 v16i8, v16i8, IntOp>;
2766 // ....then also with element size of 64 bits:
2767 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2768 InstrItinClass itinD16, InstrItinClass itinD32,
2769 InstrItinClass itinQ16, InstrItinClass itinQ32,
2770 string OpcodeStr, string Dt,
2771 Intrinsic IntOp, bit Commutable = 0>
2772 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2773 OpcodeStr, Dt, IntOp, Commutable> {
2774 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2775 OpcodeStr, !strconcat(Dt, "64"),
2776 v1i64, v1i64, IntOp, Commutable>;
2777 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2778 OpcodeStr, !strconcat(Dt, "64"),
2779 v2i64, v2i64, IntOp, Commutable>;
2781 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2782 InstrItinClass itinD16, InstrItinClass itinD32,
2783 InstrItinClass itinQ16, InstrItinClass itinQ32,
2784 string OpcodeStr, string Dt,
2786 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2787 OpcodeStr, Dt, IntOp> {
2788 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2789 OpcodeStr, !strconcat(Dt, "64"),
2790 v1i64, v1i64, IntOp>;
2791 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2792 OpcodeStr, !strconcat(Dt, "64"),
2793 v2i64, v2i64, IntOp>;
2796 // Neon Narrowing 3-register vector intrinsics,
2797 // source operand element sizes of 16, 32 and 64 bits:
2798 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2799 string OpcodeStr, string Dt,
2800 Intrinsic IntOp, bit Commutable = 0> {
2801 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2802 OpcodeStr, !strconcat(Dt, "16"),
2803 v8i8, v8i16, IntOp, Commutable>;
2804 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2805 OpcodeStr, !strconcat(Dt, "32"),
2806 v4i16, v4i32, IntOp, Commutable>;
2807 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2808 OpcodeStr, !strconcat(Dt, "64"),
2809 v2i32, v2i64, IntOp, Commutable>;
2813 // Neon Long 3-register vector operations.
2815 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2816 InstrItinClass itin16, InstrItinClass itin32,
2817 string OpcodeStr, string Dt,
2818 SDNode OpNode, bit Commutable = 0> {
2819 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2820 OpcodeStr, !strconcat(Dt, "8"),
2821 v8i16, v8i8, OpNode, Commutable>;
2822 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2823 OpcodeStr, !strconcat(Dt, "16"),
2824 v4i32, v4i16, OpNode, Commutable>;
2825 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2826 OpcodeStr, !strconcat(Dt, "32"),
2827 v2i64, v2i32, OpNode, Commutable>;
2830 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2831 InstrItinClass itin, string OpcodeStr, string Dt,
2833 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2834 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2835 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2836 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2839 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2840 InstrItinClass itin16, InstrItinClass itin32,
2841 string OpcodeStr, string Dt,
2842 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2843 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2844 OpcodeStr, !strconcat(Dt, "8"),
2845 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2846 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2847 OpcodeStr, !strconcat(Dt, "16"),
2848 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2849 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2850 OpcodeStr, !strconcat(Dt, "32"),
2851 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2854 // Neon Long 3-register vector intrinsics.
2856 // First with only element sizes of 16 and 32 bits:
2857 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2858 InstrItinClass itin16, InstrItinClass itin32,
2859 string OpcodeStr, string Dt,
2860 Intrinsic IntOp, bit Commutable = 0> {
2861 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2862 OpcodeStr, !strconcat(Dt, "16"),
2863 v4i32, v4i16, IntOp, Commutable>;
2864 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2865 OpcodeStr, !strconcat(Dt, "32"),
2866 v2i64, v2i32, IntOp, Commutable>;
2869 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2870 InstrItinClass itin, string OpcodeStr, string Dt,
2872 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2873 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2874 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2875 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2878 // ....then also with element size of 8 bits:
2879 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2880 InstrItinClass itin16, InstrItinClass itin32,
2881 string OpcodeStr, string Dt,
2882 Intrinsic IntOp, bit Commutable = 0>
2883 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2884 IntOp, Commutable> {
2885 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2886 OpcodeStr, !strconcat(Dt, "8"),
2887 v8i16, v8i8, IntOp, Commutable>;
2890 // ....with explicit extend (VABDL).
2891 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2892 InstrItinClass itin, string OpcodeStr, string Dt,
2893 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2894 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2895 OpcodeStr, !strconcat(Dt, "8"),
2896 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2897 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2898 OpcodeStr, !strconcat(Dt, "16"),
2899 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2900 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2901 OpcodeStr, !strconcat(Dt, "32"),
2902 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2906 // Neon Wide 3-register vector intrinsics,
2907 // source operand element sizes of 8, 16 and 32 bits:
2908 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2909 string OpcodeStr, string Dt,
2910 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2911 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2912 OpcodeStr, !strconcat(Dt, "8"),
2913 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2914 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2915 OpcodeStr, !strconcat(Dt, "16"),
2916 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2917 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2918 OpcodeStr, !strconcat(Dt, "32"),
2919 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2923 // Neon Multiply-Op vector operations,
2924 // element sizes of 8, 16 and 32 bits:
2925 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2926 InstrItinClass itinD16, InstrItinClass itinD32,
2927 InstrItinClass itinQ16, InstrItinClass itinQ32,
2928 string OpcodeStr, string Dt, SDNode OpNode> {
2929 // 64-bit vector types.
2930 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2931 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2932 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2933 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2934 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2935 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2937 // 128-bit vector types.
2938 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2939 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2940 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2941 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2942 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2943 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2946 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2947 InstrItinClass itinD16, InstrItinClass itinD32,
2948 InstrItinClass itinQ16, InstrItinClass itinQ32,
2949 string OpcodeStr, string Dt, SDNode ShOp> {
2950 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2951 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2952 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2953 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2954 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2955 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2957 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2958 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2962 // Neon Intrinsic-Op vector operations,
2963 // element sizes of 8, 16 and 32 bits:
2964 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2965 InstrItinClass itinD, InstrItinClass itinQ,
2966 string OpcodeStr, string Dt, Intrinsic IntOp,
2968 // 64-bit vector types.
2969 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2970 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2971 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2972 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2973 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2974 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2976 // 128-bit vector types.
2977 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2978 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2979 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2980 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2981 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2982 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2985 // Neon 3-argument intrinsics,
2986 // element sizes of 8, 16 and 32 bits:
2987 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2988 InstrItinClass itinD, InstrItinClass itinQ,
2989 string OpcodeStr, string Dt, Intrinsic IntOp> {
2990 // 64-bit vector types.
2991 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2992 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2993 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2994 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2995 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2996 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2998 // 128-bit vector types.
2999 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3000 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3001 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3002 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3003 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3004 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3008 // Neon Long Multiply-Op vector operations,
3009 // element sizes of 8, 16 and 32 bits:
3010 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3011 InstrItinClass itin16, InstrItinClass itin32,
3012 string OpcodeStr, string Dt, SDNode MulOp,
3014 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3015 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3016 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3017 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3018 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3019 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3022 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3023 string Dt, SDNode MulOp, SDNode OpNode> {
3024 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3025 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3026 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3027 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3031 // Neon Long 3-argument intrinsics.
3033 // First with only element sizes of 16 and 32 bits:
3034 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3035 InstrItinClass itin16, InstrItinClass itin32,
3036 string OpcodeStr, string Dt, Intrinsic IntOp> {
3037 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3038 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3039 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3040 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3043 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3044 string OpcodeStr, string Dt, Intrinsic IntOp> {
3045 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3046 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3047 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3048 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3051 // ....then also with element size of 8 bits:
3052 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3053 InstrItinClass itin16, InstrItinClass itin32,
3054 string OpcodeStr, string Dt, Intrinsic IntOp>
3055 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3056 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3057 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3060 // ....with explicit extend (VABAL).
3061 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3062 InstrItinClass itin, string OpcodeStr, string Dt,
3063 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3064 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3065 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3066 IntOp, ExtOp, OpNode>;
3067 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3068 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3069 IntOp, ExtOp, OpNode>;
3070 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3071 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3072 IntOp, ExtOp, OpNode>;
3076 // Neon Pairwise long 2-register intrinsics,
3077 // element sizes of 8, 16 and 32 bits:
3078 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3079 bits<5> op11_7, bit op4,
3080 string OpcodeStr, string Dt, Intrinsic IntOp> {
3081 // 64-bit vector types.
3082 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3083 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3084 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3085 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3086 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3087 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3089 // 128-bit vector types.
3090 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3091 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3092 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3093 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3094 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3095 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3099 // Neon Pairwise long 2-register accumulate intrinsics,
3100 // element sizes of 8, 16 and 32 bits:
3101 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3102 bits<5> op11_7, bit op4,
3103 string OpcodeStr, string Dt, Intrinsic IntOp> {
3104 // 64-bit vector types.
3105 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3106 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3107 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3108 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3109 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3110 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3112 // 128-bit vector types.
3113 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3114 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3115 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3116 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3117 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3118 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3122 // Neon 2-register vector shift by immediate,
3123 // with f of either N2RegVShLFrm or N2RegVShRFrm
3124 // element sizes of 8, 16, 32 and 64 bits:
3125 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3126 InstrItinClass itin, string OpcodeStr, string Dt,
3128 // 64-bit vector types.
3129 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3130 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3131 let Inst{21-19} = 0b001; // imm6 = 001xxx
3133 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3134 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3135 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3137 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3138 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3139 let Inst{21} = 0b1; // imm6 = 1xxxxx
3141 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3142 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3145 // 128-bit vector types.
3146 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3147 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3148 let Inst{21-19} = 0b001; // imm6 = 001xxx
3150 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3151 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3152 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3154 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3155 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3156 let Inst{21} = 0b1; // imm6 = 1xxxxx
3158 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3159 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3162 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3163 InstrItinClass itin, string OpcodeStr, string Dt,
3165 // 64-bit vector types.
3166 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3167 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3168 let Inst{21-19} = 0b001; // imm6 = 001xxx
3170 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3171 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3172 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3174 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3175 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3176 let Inst{21} = 0b1; // imm6 = 1xxxxx
3178 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3179 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3182 // 128-bit vector types.
3183 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3184 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3185 let Inst{21-19} = 0b001; // imm6 = 001xxx
3187 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3188 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3189 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3191 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3192 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3193 let Inst{21} = 0b1; // imm6 = 1xxxxx
3195 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3196 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3200 // Neon Shift-Accumulate vector operations,
3201 // element sizes of 8, 16, 32 and 64 bits:
3202 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3203 string OpcodeStr, string Dt, SDNode ShOp> {
3204 // 64-bit vector types.
3205 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3206 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3207 let Inst{21-19} = 0b001; // imm6 = 001xxx
3209 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3210 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3211 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3213 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3214 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3215 let Inst{21} = 0b1; // imm6 = 1xxxxx
3217 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3218 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3221 // 128-bit vector types.
3222 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3223 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3224 let Inst{21-19} = 0b001; // imm6 = 001xxx
3226 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3227 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3228 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3230 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3231 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3232 let Inst{21} = 0b1; // imm6 = 1xxxxx
3234 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3235 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3239 // Neon Shift-Insert vector operations,
3240 // with f of either N2RegVShLFrm or N2RegVShRFrm
3241 // element sizes of 8, 16, 32 and 64 bits:
3242 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3244 // 64-bit vector types.
3245 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3246 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3247 let Inst{21-19} = 0b001; // imm6 = 001xxx
3249 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3250 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3251 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3253 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3254 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3255 let Inst{21} = 0b1; // imm6 = 1xxxxx
3257 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3258 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3261 // 128-bit vector types.
3262 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3263 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3264 let Inst{21-19} = 0b001; // imm6 = 001xxx
3266 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3267 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3268 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3270 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3271 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3272 let Inst{21} = 0b1; // imm6 = 1xxxxx
3274 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3275 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3278 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3280 // 64-bit vector types.
3281 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3282 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3283 let Inst{21-19} = 0b001; // imm6 = 001xxx
3285 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3286 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3287 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3289 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3290 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3291 let Inst{21} = 0b1; // imm6 = 1xxxxx
3293 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3294 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3297 // 128-bit vector types.
3298 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3299 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3300 let Inst{21-19} = 0b001; // imm6 = 001xxx
3302 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3303 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3304 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3306 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3307 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3308 let Inst{21} = 0b1; // imm6 = 1xxxxx
3310 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3311 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3315 // Neon Shift Long operations,
3316 // element sizes of 8, 16, 32 bits:
3317 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3318 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3319 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3320 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3321 let Inst{21-19} = 0b001; // imm6 = 001xxx
3323 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3324 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3325 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3327 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3328 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3329 let Inst{21} = 0b1; // imm6 = 1xxxxx
3333 // Neon Shift Narrow operations,
3334 // element sizes of 16, 32, 64 bits:
3335 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3336 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3338 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3339 OpcodeStr, !strconcat(Dt, "16"),
3340 v8i8, v8i16, shr_imm8, OpNode> {
3341 let Inst{21-19} = 0b001; // imm6 = 001xxx
3343 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3344 OpcodeStr, !strconcat(Dt, "32"),
3345 v4i16, v4i32, shr_imm16, OpNode> {
3346 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3348 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3349 OpcodeStr, !strconcat(Dt, "64"),
3350 v2i32, v2i64, shr_imm32, OpNode> {
3351 let Inst{21} = 0b1; // imm6 = 1xxxxx
3355 //===----------------------------------------------------------------------===//
3356 // Instruction Definitions.
3357 //===----------------------------------------------------------------------===//
3359 // Vector Add Operations.
3361 // VADD : Vector Add (integer and floating-point)
3362 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3364 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3365 v2f32, v2f32, fadd, 1>;
3366 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3367 v4f32, v4f32, fadd, 1>;
3368 // VADDL : Vector Add Long (Q = D + D)
3369 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3370 "vaddl", "s", add, sext, 1>;
3371 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3372 "vaddl", "u", add, zext, 1>;
3373 // VADDW : Vector Add Wide (Q = Q + D)
3374 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3375 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3376 // VHADD : Vector Halving Add
3377 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3378 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3379 "vhadd", "s", int_arm_neon_vhadds, 1>;
3380 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3381 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3382 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3383 // VRHADD : Vector Rounding Halving Add
3384 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3385 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3386 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3387 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3388 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3389 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3390 // VQADD : Vector Saturating Add
3391 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3392 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3393 "vqadd", "s", int_arm_neon_vqadds, 1>;
3394 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3395 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3396 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3397 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3398 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3399 int_arm_neon_vaddhn, 1>;
3400 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3401 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3402 int_arm_neon_vraddhn, 1>;
3404 // Vector Multiply Operations.
3406 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3407 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3408 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3409 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3410 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3411 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3412 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3413 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3414 v2f32, v2f32, fmul, 1>;
3415 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3416 v4f32, v4f32, fmul, 1>;
3417 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3418 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3419 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3422 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3423 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3424 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3425 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3426 (DSubReg_i16_reg imm:$lane))),
3427 (SubReg_i16_lane imm:$lane)))>;
3428 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3429 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3430 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3431 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3432 (DSubReg_i32_reg imm:$lane))),
3433 (SubReg_i32_lane imm:$lane)))>;
3434 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3435 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3436 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3437 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3438 (DSubReg_i32_reg imm:$lane))),
3439 (SubReg_i32_lane imm:$lane)))>;
3441 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3442 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3443 IIC_VMULi16Q, IIC_VMULi32Q,
3444 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3445 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3446 IIC_VMULi16Q, IIC_VMULi32Q,
3447 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3448 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3449 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3451 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3452 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3453 (DSubReg_i16_reg imm:$lane))),
3454 (SubReg_i16_lane imm:$lane)))>;
3455 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3456 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3458 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3459 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3460 (DSubReg_i32_reg imm:$lane))),
3461 (SubReg_i32_lane imm:$lane)))>;
3463 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3464 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3465 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3466 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3467 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3468 IIC_VMULi16Q, IIC_VMULi32Q,
3469 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3470 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3471 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3473 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3474 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3475 (DSubReg_i16_reg imm:$lane))),
3476 (SubReg_i16_lane imm:$lane)))>;
3477 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3478 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3480 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3481 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3482 (DSubReg_i32_reg imm:$lane))),
3483 (SubReg_i32_lane imm:$lane)))>;
3485 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3486 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3487 "vmull", "s", NEONvmulls, 1>;
3488 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3489 "vmull", "u", NEONvmullu, 1>;
3490 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3491 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3492 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3493 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3495 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3496 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3497 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3498 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3499 "vqdmull", "s", int_arm_neon_vqdmull>;
3501 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3503 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3504 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3505 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3506 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3507 v2f32, fmul_su, fadd_mlx>,
3508 Requires<[HasNEON, UseFPVMLx]>;
3509 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3510 v4f32, fmul_su, fadd_mlx>,
3511 Requires<[HasNEON, UseFPVMLx]>;
3512 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3513 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3514 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3515 v2f32, fmul_su, fadd_mlx>,
3516 Requires<[HasNEON, UseFPVMLx]>;
3517 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3518 v4f32, v2f32, fmul_su, fadd_mlx>,
3519 Requires<[HasNEON, UseFPVMLx]>;
3521 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3522 (mul (v8i16 QPR:$src2),
3523 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3524 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3525 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3526 (DSubReg_i16_reg imm:$lane))),
3527 (SubReg_i16_lane imm:$lane)))>;
3529 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3530 (mul (v4i32 QPR:$src2),
3531 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3532 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3533 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3534 (DSubReg_i32_reg imm:$lane))),
3535 (SubReg_i32_lane imm:$lane)))>;
3537 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3538 (fmul_su (v4f32 QPR:$src2),
3539 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3540 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3542 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3543 (DSubReg_i32_reg imm:$lane))),
3544 (SubReg_i32_lane imm:$lane)))>,
3545 Requires<[HasNEON, UseFPVMLx]>;
3547 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3548 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3549 "vmlal", "s", NEONvmulls, add>;
3550 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3551 "vmlal", "u", NEONvmullu, add>;
3553 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3554 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3556 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3557 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3558 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3559 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3561 // VMLS : Vector Multiply Subtract (integer and floating-point)
3562 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3563 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3564 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3565 v2f32, fmul_su, fsub_mlx>,
3566 Requires<[HasNEON, UseFPVMLx]>;
3567 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3568 v4f32, fmul_su, fsub_mlx>,
3569 Requires<[HasNEON, UseFPVMLx]>;
3570 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3571 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3572 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3573 v2f32, fmul_su, fsub_mlx>,
3574 Requires<[HasNEON, UseFPVMLx]>;
3575 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3576 v4f32, v2f32, fmul_su, fsub_mlx>,
3577 Requires<[HasNEON, UseFPVMLx]>;
3579 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3580 (mul (v8i16 QPR:$src2),
3581 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3582 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3583 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3584 (DSubReg_i16_reg imm:$lane))),
3585 (SubReg_i16_lane imm:$lane)))>;
3587 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3588 (mul (v4i32 QPR:$src2),
3589 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3590 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3591 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3592 (DSubReg_i32_reg imm:$lane))),
3593 (SubReg_i32_lane imm:$lane)))>;
3595 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3596 (fmul_su (v4f32 QPR:$src2),
3597 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3598 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3599 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3600 (DSubReg_i32_reg imm:$lane))),
3601 (SubReg_i32_lane imm:$lane)))>,
3602 Requires<[HasNEON, UseFPVMLx]>;
3604 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3605 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3606 "vmlsl", "s", NEONvmulls, sub>;
3607 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3608 "vmlsl", "u", NEONvmullu, sub>;
3610 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3611 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3613 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3614 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3615 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3616 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3618 // Vector Subtract Operations.
3620 // VSUB : Vector Subtract (integer and floating-point)
3621 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3622 "vsub", "i", sub, 0>;
3623 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3624 v2f32, v2f32, fsub, 0>;
3625 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3626 v4f32, v4f32, fsub, 0>;
3627 // VSUBL : Vector Subtract Long (Q = D - D)
3628 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3629 "vsubl", "s", sub, sext, 0>;
3630 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3631 "vsubl", "u", sub, zext, 0>;
3632 // VSUBW : Vector Subtract Wide (Q = Q - D)
3633 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3634 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3635 // VHSUB : Vector Halving Subtract
3636 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3637 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3638 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3639 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3640 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3641 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3642 // VQSUB : Vector Saturing Subtract
3643 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3644 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3645 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3646 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3647 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3648 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3649 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3650 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3651 int_arm_neon_vsubhn, 0>;
3652 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3653 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3654 int_arm_neon_vrsubhn, 0>;
3656 // Vector Comparisons.
3658 // VCEQ : Vector Compare Equal
3659 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3660 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3661 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3663 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3666 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3667 "$Vd, $Vm, #0", NEONvceqz>;
3669 // VCGE : Vector Compare Greater Than or Equal
3670 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3671 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3672 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3673 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3674 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3676 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3679 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3680 "$Vd, $Vm, #0", NEONvcgez>;
3681 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3682 "$Vd, $Vm, #0", NEONvclez>;
3684 // VCGT : Vector Compare Greater Than
3685 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3686 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3687 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3688 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3689 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3691 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3694 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3695 "$Vd, $Vm, #0", NEONvcgtz>;
3696 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3697 "$Vd, $Vm, #0", NEONvcltz>;
3699 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3700 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3701 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3702 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3703 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3704 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3705 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3706 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3707 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3708 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3709 // VTST : Vector Test Bits
3710 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3711 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3713 // Vector Bitwise Operations.
3715 def vnotd : PatFrag<(ops node:$in),
3716 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3717 def vnotq : PatFrag<(ops node:$in),
3718 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3721 // VAND : Vector Bitwise AND
3722 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3723 v2i32, v2i32, and, 1>;
3724 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3725 v4i32, v4i32, and, 1>;
3727 // VEOR : Vector Bitwise Exclusive OR
3728 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3729 v2i32, v2i32, xor, 1>;
3730 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3731 v4i32, v4i32, xor, 1>;
3733 // VORR : Vector Bitwise OR
3734 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3735 v2i32, v2i32, or, 1>;
3736 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3737 v4i32, v4i32, or, 1>;
3739 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3740 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3742 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3744 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3745 let Inst{9} = SIMM{9};
3748 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3749 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3751 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3753 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3754 let Inst{10-9} = SIMM{10-9};
3757 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3758 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3760 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3762 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3763 let Inst{9} = SIMM{9};
3766 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3767 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3769 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3771 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3772 let Inst{10-9} = SIMM{10-9};
3776 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3777 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3778 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3779 "vbic", "$Vd, $Vn, $Vm", "",
3780 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3781 (vnotd DPR:$Vm))))]>;
3782 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3783 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3784 "vbic", "$Vd, $Vn, $Vm", "",
3785 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3786 (vnotq QPR:$Vm))))]>;
3788 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3789 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3791 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3793 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3794 let Inst{9} = SIMM{9};
3797 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3798 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3800 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3802 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3803 let Inst{10-9} = SIMM{10-9};
3806 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3807 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3809 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3811 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3812 let Inst{9} = SIMM{9};
3815 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3816 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3818 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3820 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3821 let Inst{10-9} = SIMM{10-9};
3824 // VORN : Vector Bitwise OR NOT
3825 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3826 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3827 "vorn", "$Vd, $Vn, $Vm", "",
3828 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3829 (vnotd DPR:$Vm))))]>;
3830 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3831 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3832 "vorn", "$Vd, $Vn, $Vm", "",
3833 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3834 (vnotq QPR:$Vm))))]>;
3836 // VMVN : Vector Bitwise NOT (Immediate)
3838 let isReMaterializable = 1 in {
3840 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3841 (ins nModImm:$SIMM), IIC_VMOVImm,
3842 "vmvn", "i16", "$Vd, $SIMM", "",
3843 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3844 let Inst{9} = SIMM{9};
3847 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3848 (ins nModImm:$SIMM), IIC_VMOVImm,
3849 "vmvn", "i16", "$Vd, $SIMM", "",
3850 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3851 let Inst{9} = SIMM{9};
3854 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3855 (ins nModImm:$SIMM), IIC_VMOVImm,
3856 "vmvn", "i32", "$Vd, $SIMM", "",
3857 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3858 let Inst{11-8} = SIMM{11-8};
3861 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3862 (ins nModImm:$SIMM), IIC_VMOVImm,
3863 "vmvn", "i32", "$Vd, $SIMM", "",
3864 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3865 let Inst{11-8} = SIMM{11-8};
3869 // VMVN : Vector Bitwise NOT
3870 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3871 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3872 "vmvn", "$Vd, $Vm", "",
3873 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3874 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3875 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3876 "vmvn", "$Vd, $Vm", "",
3877 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3878 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3879 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3881 // VBSL : Vector Bitwise Select
3882 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3883 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3884 N3RegFrm, IIC_VCNTiD,
3885 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3887 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3889 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3890 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3891 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3893 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3894 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3895 N3RegFrm, IIC_VCNTiQ,
3896 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3898 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3900 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3901 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3902 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3904 // VBIF : Vector Bitwise Insert if False
3905 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3906 // FIXME: This instruction's encoding MAY NOT BE correct.
3907 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3908 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3909 N3RegFrm, IIC_VBINiD,
3910 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3911 [/* For disassembly only; pattern left blank */]>;
3912 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3913 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3914 N3RegFrm, IIC_VBINiQ,
3915 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3916 [/* For disassembly only; pattern left blank */]>;
3918 // VBIT : Vector Bitwise Insert if True
3919 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3920 // FIXME: This instruction's encoding MAY NOT BE correct.
3921 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3922 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3923 N3RegFrm, IIC_VBINiD,
3924 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3925 [/* For disassembly only; pattern left blank */]>;
3926 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3927 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3928 N3RegFrm, IIC_VBINiQ,
3929 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3930 [/* For disassembly only; pattern left blank */]>;
3932 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3933 // for equivalent operations with different register constraints; it just
3936 // Vector Absolute Differences.
3938 // VABD : Vector Absolute Difference
3939 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3940 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3941 "vabd", "s", int_arm_neon_vabds, 1>;
3942 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3943 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3944 "vabd", "u", int_arm_neon_vabdu, 1>;
3945 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3946 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3947 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3948 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3950 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3951 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3952 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3953 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3954 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3956 // VABA : Vector Absolute Difference and Accumulate
3957 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3958 "vaba", "s", int_arm_neon_vabds, add>;
3959 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3960 "vaba", "u", int_arm_neon_vabdu, add>;
3962 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3963 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3964 "vabal", "s", int_arm_neon_vabds, zext, add>;
3965 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3966 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3968 // Vector Maximum and Minimum.
3970 // VMAX : Vector Maximum
3971 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3972 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3973 "vmax", "s", int_arm_neon_vmaxs, 1>;
3974 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3975 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3976 "vmax", "u", int_arm_neon_vmaxu, 1>;
3977 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3979 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3980 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3982 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3984 // VMIN : Vector Minimum
3985 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3986 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3987 "vmin", "s", int_arm_neon_vmins, 1>;
3988 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3989 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3990 "vmin", "u", int_arm_neon_vminu, 1>;
3991 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3993 v2f32, v2f32, int_arm_neon_vmins, 1>;
3994 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3996 v4f32, v4f32, int_arm_neon_vmins, 1>;
3998 // Vector Pairwise Operations.
4000 // VPADD : Vector Pairwise Add
4001 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4003 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4004 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4006 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4007 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4009 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4010 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4011 IIC_VPBIND, "vpadd", "f32",
4012 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4014 // VPADDL : Vector Pairwise Add Long
4015 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4016 int_arm_neon_vpaddls>;
4017 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4018 int_arm_neon_vpaddlu>;
4020 // VPADAL : Vector Pairwise Add and Accumulate Long
4021 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4022 int_arm_neon_vpadals>;
4023 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4024 int_arm_neon_vpadalu>;
4026 // VPMAX : Vector Pairwise Maximum
4027 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4028 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4029 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4030 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4031 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4032 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4033 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4034 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4035 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4036 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4037 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4038 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4039 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4040 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4042 // VPMIN : Vector Pairwise Minimum
4043 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4044 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4045 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4046 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4047 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4048 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4049 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4050 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4051 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4052 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4053 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4054 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4055 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4056 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4058 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4060 // VRECPE : Vector Reciprocal Estimate
4061 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4062 IIC_VUNAD, "vrecpe", "u32",
4063 v2i32, v2i32, int_arm_neon_vrecpe>;
4064 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4065 IIC_VUNAQ, "vrecpe", "u32",
4066 v4i32, v4i32, int_arm_neon_vrecpe>;
4067 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4068 IIC_VUNAD, "vrecpe", "f32",
4069 v2f32, v2f32, int_arm_neon_vrecpe>;
4070 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4071 IIC_VUNAQ, "vrecpe", "f32",
4072 v4f32, v4f32, int_arm_neon_vrecpe>;
4074 // VRECPS : Vector Reciprocal Step
4075 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4076 IIC_VRECSD, "vrecps", "f32",
4077 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4078 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4079 IIC_VRECSQ, "vrecps", "f32",
4080 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4082 // VRSQRTE : Vector Reciprocal Square Root Estimate
4083 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4084 IIC_VUNAD, "vrsqrte", "u32",
4085 v2i32, v2i32, int_arm_neon_vrsqrte>;
4086 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4087 IIC_VUNAQ, "vrsqrte", "u32",
4088 v4i32, v4i32, int_arm_neon_vrsqrte>;
4089 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4090 IIC_VUNAD, "vrsqrte", "f32",
4091 v2f32, v2f32, int_arm_neon_vrsqrte>;
4092 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4093 IIC_VUNAQ, "vrsqrte", "f32",
4094 v4f32, v4f32, int_arm_neon_vrsqrte>;
4096 // VRSQRTS : Vector Reciprocal Square Root Step
4097 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4098 IIC_VRECSD, "vrsqrts", "f32",
4099 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4100 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4101 IIC_VRECSQ, "vrsqrts", "f32",
4102 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4106 // VSHL : Vector Shift
4107 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4108 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4109 "vshl", "s", int_arm_neon_vshifts>;
4110 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4111 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4112 "vshl", "u", int_arm_neon_vshiftu>;
4114 // VSHL : Vector Shift Left (Immediate)
4115 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4117 // VSHR : Vector Shift Right (Immediate)
4118 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4119 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4121 // VSHLL : Vector Shift Left Long
4122 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4123 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4125 // VSHLL : Vector Shift Left Long (with maximum shift count)
4126 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4127 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4128 ValueType OpTy, SDNode OpNode>
4129 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4130 ResTy, OpTy, OpNode> {
4131 let Inst{21-16} = op21_16;
4132 let DecoderMethod = "DecodeVSHLMaxInstruction";
4134 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4135 v8i16, v8i8, NEONvshlli>;
4136 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4137 v4i32, v4i16, NEONvshlli>;
4138 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4139 v2i64, v2i32, NEONvshlli>;
4141 // VSHRN : Vector Shift Right and Narrow
4142 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4145 // VRSHL : Vector Rounding Shift
4146 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4147 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4148 "vrshl", "s", int_arm_neon_vrshifts>;
4149 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4150 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4151 "vrshl", "u", int_arm_neon_vrshiftu>;
4152 // VRSHR : Vector Rounding Shift Right
4153 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4154 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4156 // VRSHRN : Vector Rounding Shift Right and Narrow
4157 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4160 // VQSHL : Vector Saturating Shift
4161 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4162 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4163 "vqshl", "s", int_arm_neon_vqshifts>;
4164 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4165 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4166 "vqshl", "u", int_arm_neon_vqshiftu>;
4167 // VQSHL : Vector Saturating Shift Left (Immediate)
4168 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4169 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4171 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4172 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4174 // VQSHRN : Vector Saturating Shift Right and Narrow
4175 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4177 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4180 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4181 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4184 // VQRSHL : Vector Saturating Rounding Shift
4185 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4186 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4187 "vqrshl", "s", int_arm_neon_vqrshifts>;
4188 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4189 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4190 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4192 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4193 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4195 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4198 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4199 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4202 // VSRA : Vector Shift Right and Accumulate
4203 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4204 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4205 // VRSRA : Vector Rounding Shift Right and Accumulate
4206 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4207 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4209 // VSLI : Vector Shift Left and Insert
4210 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4212 // VSRI : Vector Shift Right and Insert
4213 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4215 // Vector Absolute and Saturating Absolute.
4217 // VABS : Vector Absolute Value
4218 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4219 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4221 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4222 IIC_VUNAD, "vabs", "f32",
4223 v2f32, v2f32, int_arm_neon_vabs>;
4224 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4225 IIC_VUNAQ, "vabs", "f32",
4226 v4f32, v4f32, int_arm_neon_vabs>;
4228 // VQABS : Vector Saturating Absolute Value
4229 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4230 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4231 int_arm_neon_vqabs>;
4235 def vnegd : PatFrag<(ops node:$in),
4236 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4237 def vnegq : PatFrag<(ops node:$in),
4238 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4240 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4241 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4242 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4243 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4244 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4245 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4246 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4247 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4249 // VNEG : Vector Negate (integer)
4250 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4251 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4252 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4253 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4254 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4255 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4257 // VNEG : Vector Negate (floating-point)
4258 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4259 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4260 "vneg", "f32", "$Vd, $Vm", "",
4261 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4262 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4263 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4264 "vneg", "f32", "$Vd, $Vm", "",
4265 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4267 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4268 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4269 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4270 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4271 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4272 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4274 // VQNEG : Vector Saturating Negate
4275 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4276 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4277 int_arm_neon_vqneg>;
4279 // Vector Bit Counting Operations.
4281 // VCLS : Vector Count Leading Sign Bits
4282 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4283 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4285 // VCLZ : Vector Count Leading Zeros
4286 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4287 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4289 // VCNT : Vector Count One Bits
4290 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4291 IIC_VCNTiD, "vcnt", "8",
4292 v8i8, v8i8, int_arm_neon_vcnt>;
4293 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4294 IIC_VCNTiQ, "vcnt", "8",
4295 v16i8, v16i8, int_arm_neon_vcnt>;
4297 // Vector Swap -- for disassembly only.
4298 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4299 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4300 "vswp", "$Vd, $Vm", "", []>;
4301 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4302 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4303 "vswp", "$Vd, $Vm", "", []>;
4305 // Vector Move Operations.
4307 // VMOV : Vector Move (Register)
4308 def : InstAlias<"vmov${p} $Vd, $Vm",
4309 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4310 def : InstAlias<"vmov${p} $Vd, $Vm",
4311 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4313 // VMOV : Vector Move (Immediate)
4315 let isReMaterializable = 1 in {
4316 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4317 (ins nModImm:$SIMM), IIC_VMOVImm,
4318 "vmov", "i8", "$Vd, $SIMM", "",
4319 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4320 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4321 (ins nModImm:$SIMM), IIC_VMOVImm,
4322 "vmov", "i8", "$Vd, $SIMM", "",
4323 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4325 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4326 (ins nModImm:$SIMM), IIC_VMOVImm,
4327 "vmov", "i16", "$Vd, $SIMM", "",
4328 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4329 let Inst{9} = SIMM{9};
4332 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4333 (ins nModImm:$SIMM), IIC_VMOVImm,
4334 "vmov", "i16", "$Vd, $SIMM", "",
4335 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4336 let Inst{9} = SIMM{9};
4339 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4340 (ins nModImm:$SIMM), IIC_VMOVImm,
4341 "vmov", "i32", "$Vd, $SIMM", "",
4342 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4343 let Inst{11-8} = SIMM{11-8};
4346 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4347 (ins nModImm:$SIMM), IIC_VMOVImm,
4348 "vmov", "i32", "$Vd, $SIMM", "",
4349 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4350 let Inst{11-8} = SIMM{11-8};
4353 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4354 (ins nModImm:$SIMM), IIC_VMOVImm,
4355 "vmov", "i64", "$Vd, $SIMM", "",
4356 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4357 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4358 (ins nModImm:$SIMM), IIC_VMOVImm,
4359 "vmov", "i64", "$Vd, $SIMM", "",
4360 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4361 } // isReMaterializable
4363 // VMOV : Vector Get Lane (move scalar to ARM core register)
4365 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4366 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4367 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4368 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4370 let Inst{21} = lane{2};
4371 let Inst{6-5} = lane{1-0};
4373 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4374 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4375 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4376 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4378 let Inst{21} = lane{1};
4379 let Inst{6} = lane{0};
4381 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4382 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4383 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4384 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4386 let Inst{21} = lane{2};
4387 let Inst{6-5} = lane{1-0};
4389 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4390 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4391 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4392 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4394 let Inst{21} = lane{1};
4395 let Inst{6} = lane{0};
4397 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4398 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4399 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4400 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4402 let Inst{21} = lane{0};
4404 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4405 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4406 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4407 (DSubReg_i8_reg imm:$lane))),
4408 (SubReg_i8_lane imm:$lane))>;
4409 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4410 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4411 (DSubReg_i16_reg imm:$lane))),
4412 (SubReg_i16_lane imm:$lane))>;
4413 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4414 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4415 (DSubReg_i8_reg imm:$lane))),
4416 (SubReg_i8_lane imm:$lane))>;
4417 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4418 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4419 (DSubReg_i16_reg imm:$lane))),
4420 (SubReg_i16_lane imm:$lane))>;
4421 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4422 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4423 (DSubReg_i32_reg imm:$lane))),
4424 (SubReg_i32_lane imm:$lane))>;
4425 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4426 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4427 (SSubReg_f32_reg imm:$src2))>;
4428 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4429 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4430 (SSubReg_f32_reg imm:$src2))>;
4431 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4432 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4433 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4434 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4437 // VMOV : Vector Set Lane (move ARM core register to scalar)
4439 let Constraints = "$src1 = $V" in {
4440 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4441 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4442 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4443 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4444 GPR:$R, imm:$lane))]> {
4445 let Inst{21} = lane{2};
4446 let Inst{6-5} = lane{1-0};
4448 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4449 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4450 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4451 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4452 GPR:$R, imm:$lane))]> {
4453 let Inst{21} = lane{1};
4454 let Inst{6} = lane{0};
4456 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4457 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4458 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4459 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4460 GPR:$R, imm:$lane))]> {
4461 let Inst{21} = lane{0};
4464 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4465 (v16i8 (INSERT_SUBREG QPR:$src1,
4466 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4467 (DSubReg_i8_reg imm:$lane))),
4468 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4469 (DSubReg_i8_reg imm:$lane)))>;
4470 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4471 (v8i16 (INSERT_SUBREG QPR:$src1,
4472 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4473 (DSubReg_i16_reg imm:$lane))),
4474 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4475 (DSubReg_i16_reg imm:$lane)))>;
4476 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4477 (v4i32 (INSERT_SUBREG QPR:$src1,
4478 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4479 (DSubReg_i32_reg imm:$lane))),
4480 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4481 (DSubReg_i32_reg imm:$lane)))>;
4483 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4484 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4485 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4486 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4487 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4488 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4490 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4491 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4492 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4493 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4495 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4496 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4497 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4498 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4499 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4500 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4502 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4503 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4504 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4505 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4506 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4507 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4509 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4510 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4511 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4513 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4514 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4515 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4517 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4518 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4519 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4522 // VDUP : Vector Duplicate (from ARM core register to all elements)
4524 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4525 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4526 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4527 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4528 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4529 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4530 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4531 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4533 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4534 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4535 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4536 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4537 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4538 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4540 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4541 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4543 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4545 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4546 ValueType Ty, Operand IdxTy>
4547 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4548 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4549 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4551 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4552 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4553 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4554 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4555 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4556 VectorIndex32:$lane)))]>;
4558 // Inst{19-16} is partially specified depending on the element size.
4560 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4562 let Inst{19-17} = lane{2-0};
4564 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4566 let Inst{19-18} = lane{1-0};
4568 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4570 let Inst{19} = lane{0};
4572 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4574 let Inst{19-17} = lane{2-0};
4576 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4578 let Inst{19-18} = lane{1-0};
4580 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4582 let Inst{19} = lane{0};
4585 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4586 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4588 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4589 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4591 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4592 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4593 (DSubReg_i8_reg imm:$lane))),
4594 (SubReg_i8_lane imm:$lane)))>;
4595 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4596 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4597 (DSubReg_i16_reg imm:$lane))),
4598 (SubReg_i16_lane imm:$lane)))>;
4599 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4600 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4601 (DSubReg_i32_reg imm:$lane))),
4602 (SubReg_i32_lane imm:$lane)))>;
4603 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4604 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4605 (DSubReg_i32_reg imm:$lane))),
4606 (SubReg_i32_lane imm:$lane)))>;
4608 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4609 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4610 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4611 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4613 // VMOVN : Vector Narrowing Move
4614 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4615 "vmovn", "i", trunc>;
4616 // VQMOVN : Vector Saturating Narrowing Move
4617 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4618 "vqmovn", "s", int_arm_neon_vqmovns>;
4619 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4620 "vqmovn", "u", int_arm_neon_vqmovnu>;
4621 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4622 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4623 // VMOVL : Vector Lengthening Move
4624 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4625 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4627 // Vector Conversions.
4629 // VCVT : Vector Convert Between Floating-Point and Integers
4630 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4631 v2i32, v2f32, fp_to_sint>;
4632 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4633 v2i32, v2f32, fp_to_uint>;
4634 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4635 v2f32, v2i32, sint_to_fp>;
4636 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4637 v2f32, v2i32, uint_to_fp>;
4639 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4640 v4i32, v4f32, fp_to_sint>;
4641 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4642 v4i32, v4f32, fp_to_uint>;
4643 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4644 v4f32, v4i32, sint_to_fp>;
4645 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4646 v4f32, v4i32, uint_to_fp>;
4648 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4649 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4650 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4651 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4652 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4653 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4654 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4655 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4656 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4658 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4659 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4660 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4661 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4662 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4663 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4664 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4665 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4667 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4668 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4669 IIC_VUNAQ, "vcvt", "f16.f32",
4670 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4671 Requires<[HasNEON, HasFP16]>;
4672 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4673 IIC_VUNAQ, "vcvt", "f32.f16",
4674 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4675 Requires<[HasNEON, HasFP16]>;
4679 // VREV64 : Vector Reverse elements within 64-bit doublewords
4681 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4682 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4683 (ins DPR:$Vm), IIC_VMOVD,
4684 OpcodeStr, Dt, "$Vd, $Vm", "",
4685 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4686 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4687 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4688 (ins QPR:$Vm), IIC_VMOVQ,
4689 OpcodeStr, Dt, "$Vd, $Vm", "",
4690 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4692 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4693 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4694 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4695 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4697 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4698 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4699 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4700 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4702 // VREV32 : Vector Reverse elements within 32-bit words
4704 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4705 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4706 (ins DPR:$Vm), IIC_VMOVD,
4707 OpcodeStr, Dt, "$Vd, $Vm", "",
4708 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4709 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4710 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4711 (ins QPR:$Vm), IIC_VMOVQ,
4712 OpcodeStr, Dt, "$Vd, $Vm", "",
4713 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4715 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4716 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4718 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4719 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4721 // VREV16 : Vector Reverse elements within 16-bit halfwords
4723 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4724 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4725 (ins DPR:$Vm), IIC_VMOVD,
4726 OpcodeStr, Dt, "$Vd, $Vm", "",
4727 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4728 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4729 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4730 (ins QPR:$Vm), IIC_VMOVQ,
4731 OpcodeStr, Dt, "$Vd, $Vm", "",
4732 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4734 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4735 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4737 // Other Vector Shuffles.
4739 // Aligned extractions: really just dropping registers
4741 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4742 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4743 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4745 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4747 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4749 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4751 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4753 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4756 // VEXT : Vector Extract
4758 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4759 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4760 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4761 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4762 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4763 (Ty DPR:$Vm), imm:$index)))]> {
4765 let Inst{11-8} = index{3-0};
4768 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4769 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4770 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4771 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4772 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4773 (Ty QPR:$Vm), imm:$index)))]> {
4775 let Inst{11-8} = index{3-0};
4778 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4779 let Inst{11-8} = index{3-0};
4781 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4782 let Inst{11-9} = index{2-0};
4785 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4786 let Inst{11-10} = index{1-0};
4787 let Inst{9-8} = 0b00;
4789 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4792 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4794 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4795 let Inst{11-8} = index{3-0};
4797 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4798 let Inst{11-9} = index{2-0};
4801 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4802 let Inst{11-10} = index{1-0};
4803 let Inst{9-8} = 0b00;
4805 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4808 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4810 // VTRN : Vector Transpose
4812 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4813 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4814 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4816 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4817 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4818 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4820 // VUZP : Vector Unzip (Deinterleave)
4822 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4823 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4824 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4826 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4827 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4828 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4830 // VZIP : Vector Zip (Interleave)
4832 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4833 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4834 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4836 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4837 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4838 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4840 // Vector Table Lookup and Table Extension.
4842 // VTBL : Vector Table Lookup
4843 let DecoderMethod = "DecodeTBLInstruction" in {
4845 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4846 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4847 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4848 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4849 let hasExtraSrcRegAllocReq = 1 in {
4851 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4852 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4853 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4855 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4856 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4857 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4859 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4860 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4862 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4863 } // hasExtraSrcRegAllocReq = 1
4866 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4868 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4870 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4872 // VTBX : Vector Table Extension
4874 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4875 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4876 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4877 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4878 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4879 let hasExtraSrcRegAllocReq = 1 in {
4881 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4882 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4883 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4885 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4886 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4887 NVTBLFrm, IIC_VTBX3,
4888 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4891 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4892 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4893 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4895 } // hasExtraSrcRegAllocReq = 1
4898 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4899 IIC_VTBX2, "$orig = $dst", []>;
4901 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4902 IIC_VTBX3, "$orig = $dst", []>;
4904 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4905 IIC_VTBX4, "$orig = $dst", []>;
4906 } // DecoderMethod = "DecodeTBLInstruction"
4908 //===----------------------------------------------------------------------===//
4909 // NEON instructions for single-precision FP math
4910 //===----------------------------------------------------------------------===//
4912 class N2VSPat<SDNode OpNode, NeonI Inst>
4913 : NEONFPPat<(f32 (OpNode SPR:$a)),
4915 (v2f32 (COPY_TO_REGCLASS (Inst
4917 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4918 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4920 class N3VSPat<SDNode OpNode, NeonI Inst>
4921 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4923 (v2f32 (COPY_TO_REGCLASS (Inst
4925 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4928 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4929 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4931 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4932 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4934 (v2f32 (COPY_TO_REGCLASS (Inst
4936 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4939 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4942 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4943 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4945 def : N3VSPat<fadd, VADDfd>;
4946 def : N3VSPat<fsub, VSUBfd>;
4947 def : N3VSPat<fmul, VMULfd>;
4948 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4949 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4950 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4951 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4952 def : N2VSPat<fabs, VABSfd>;
4953 def : N2VSPat<fneg, VNEGfd>;
4954 def : N3VSPat<NEONfmax, VMAXfd>;
4955 def : N3VSPat<NEONfmin, VMINfd>;
4956 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4957 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4958 def : N2VSPat<arm_sitof, VCVTs2fd>;
4959 def : N2VSPat<arm_uitof, VCVTu2fd>;
4961 //===----------------------------------------------------------------------===//
4962 // Non-Instruction Patterns
4963 //===----------------------------------------------------------------------===//
4966 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4967 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4968 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4969 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4970 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4971 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4972 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4973 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4974 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4975 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4976 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4977 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4978 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4979 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4980 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4981 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4982 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4983 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4984 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4985 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4986 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4987 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4988 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4989 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4990 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4991 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4992 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4993 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4994 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4995 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4997 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4998 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4999 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5000 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5001 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5002 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5003 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5004 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5005 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5006 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5007 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5008 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5009 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5010 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5011 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5012 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5013 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5014 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5015 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5016 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5017 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5018 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5019 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5020 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5021 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5022 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5023 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5024 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5025 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5026 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;