1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 //===----------------------------------------------------------------------===//
72 // NEON operand definitions
73 //===----------------------------------------------------------------------===//
75 // addrmode_neonldstm := reg
77 /* TODO: Take advantage of vldm.
78 def addrmode_neonldstm : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
80 let PrintMethod = "printAddrNeonLdStMOperand";
81 let MIOperandInfo = (ops GPR, i32imm);
85 //===----------------------------------------------------------------------===//
86 // NEON load / store instructions
87 //===----------------------------------------------------------------------===//
89 /* TODO: Take advantage of vldm.
91 def VLDMD : NI<(outs),
92 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
93 "vldm${addr:submode} ${addr:base}, $dst1",
95 let Inst{27-25} = 0b110;
97 let Inst{11-9} = 0b101;
100 def VLDMS : NI<(outs),
101 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
102 "vldm${addr:submode} ${addr:base}, $dst1",
104 let Inst{27-25} = 0b110;
106 let Inst{11-9} = 0b101;
111 // Use vldmia to load a Q register as a D register pair.
112 def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
113 "vldmia $addr, ${dst:dregpair}",
114 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
115 let Inst{27-25} = 0b110;
116 let Inst{24} = 0; // P bit
117 let Inst{23} = 1; // U bit
119 let Inst{11-9} = 0b101;
122 // Use vstmia to store a Q register as a D register pair.
123 def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
124 "vstmia $addr, ${src:dregpair}",
125 [(store (v2f64 QPR:$src), GPR:$addr)]> {
126 let Inst{27-25} = 0b110;
127 let Inst{24} = 0; // P bit
128 let Inst{23} = 1; // U bit
130 let Inst{11-9} = 0b101;
134 // VLD1 : Vector Load (multiple single elements)
135 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
136 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
137 !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
138 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
139 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
140 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
141 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
142 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
144 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
145 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
146 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
147 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
148 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
150 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
151 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
152 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
153 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
154 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
156 // VST1 : Vector Store (multiple single elements)
157 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
158 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
159 !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
160 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
161 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
162 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
163 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
164 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
166 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
167 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
168 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
169 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
170 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
172 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
173 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
174 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
175 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
176 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
179 //===----------------------------------------------------------------------===//
180 // NEON pattern fragments
181 //===----------------------------------------------------------------------===//
183 // Extract D sub-registers of Q registers.
184 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
185 def SubReg_i8_reg : SDNodeXForm<imm, [{
186 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
188 def SubReg_i16_reg : SDNodeXForm<imm, [{
189 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
191 def SubReg_i32_reg : SDNodeXForm<imm, [{
192 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
194 def SubReg_f64_reg : SDNodeXForm<imm, [{
195 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
198 // Translate lane numbers from Q registers to D subregs.
199 def SubReg_i8_lane : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
202 def SubReg_i16_lane : SDNodeXForm<imm, [{
203 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
205 def SubReg_i32_lane : SDNodeXForm<imm, [{
206 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
209 //===----------------------------------------------------------------------===//
210 // Instruction Classes
211 //===----------------------------------------------------------------------===//
213 // Basic 2-register operations, both double- and quad-register.
214 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
215 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
216 ValueType ResTy, ValueType OpTy, SDNode OpNode>
217 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
218 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
219 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
220 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
221 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
222 ValueType ResTy, ValueType OpTy, SDNode OpNode>
223 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
224 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
225 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
227 // Basic 2-register intrinsics, both double- and quad-register.
228 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
229 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
230 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
231 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
232 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
233 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
234 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
235 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
236 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
237 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
238 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
239 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
241 // Narrow 2-register intrinsics.
242 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
243 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
244 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
245 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
246 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
247 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
249 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
250 // derived from N2VImm instead of N2V because of the way the size is encoded.)
251 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
252 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
254 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
255 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
256 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
258 // Basic 3-register operations, both double- and quad-register.
259 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
260 string OpcodeStr, ValueType ResTy, ValueType OpTy,
261 SDNode OpNode, bit Commutable>
262 : N3V<op24, op23, op21_20, op11_8, 0, op4,
263 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
264 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
265 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
266 let isCommutable = Commutable;
268 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
269 string OpcodeStr, ValueType ResTy, ValueType OpTy,
270 SDNode OpNode, bit Commutable>
271 : N3V<op24, op23, op21_20, op11_8, 1, op4,
272 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
273 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
274 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
275 let isCommutable = Commutable;
278 // Basic 3-register intrinsics, both double- and quad-register.
279 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
280 string OpcodeStr, ValueType ResTy, ValueType OpTy,
281 Intrinsic IntOp, bit Commutable>
282 : N3V<op24, op23, op21_20, op11_8, 0, op4,
283 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
284 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
285 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
286 let isCommutable = Commutable;
288 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
289 string OpcodeStr, ValueType ResTy, ValueType OpTy,
290 Intrinsic IntOp, bit Commutable>
291 : N3V<op24, op23, op21_20, op11_8, 1, op4,
292 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
293 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
294 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
295 let isCommutable = Commutable;
298 // Multiply-Add/Sub operations, both double- and quad-register.
299 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
300 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
301 : N3V<op24, op23, op21_20, op11_8, 0, op4,
302 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
303 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
304 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
305 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
306 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
307 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
308 : N3V<op24, op23, op21_20, op11_8, 1, op4,
309 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
310 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
311 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
312 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
314 // Neon 3-argument intrinsics, both double- and quad-register.
315 // The destination register is also used as the first source operand register.
316 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
317 string OpcodeStr, ValueType ResTy, ValueType OpTy,
319 : N3V<op24, op23, op21_20, op11_8, 0, op4,
320 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
321 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
322 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
323 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
324 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
325 string OpcodeStr, ValueType ResTy, ValueType OpTy,
327 : N3V<op24, op23, op21_20, op11_8, 1, op4,
328 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
329 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
330 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
331 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
333 // Neon Long 3-argument intrinsic. The destination register is
334 // a quad-register and is also used as the first source operand register.
335 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
336 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
337 : N3V<op24, op23, op21_20, op11_8, 0, op4,
338 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
339 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
341 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
343 // Narrowing 3-register intrinsics.
344 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
345 string OpcodeStr, ValueType TyD, ValueType TyQ,
346 Intrinsic IntOp, bit Commutable>
347 : N3V<op24, op23, op21_20, op11_8, 0, op4,
348 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
349 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
350 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
351 let isCommutable = Commutable;
354 // Long 3-register intrinsics.
355 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
356 string OpcodeStr, ValueType TyQ, ValueType TyD,
357 Intrinsic IntOp, bit Commutable>
358 : N3V<op24, op23, op21_20, op11_8, 0, op4,
359 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
360 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
361 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
362 let isCommutable = Commutable;
365 // Wide 3-register intrinsics.
366 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
367 string OpcodeStr, ValueType TyQ, ValueType TyD,
368 Intrinsic IntOp, bit Commutable>
369 : N3V<op24, op23, op21_20, op11_8, 0, op4,
370 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
371 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
372 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
373 let isCommutable = Commutable;
376 // Pairwise long 2-register intrinsics, both double- and quad-register.
377 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
378 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
379 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
380 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
381 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
382 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
383 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
384 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
385 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
386 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
387 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
388 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
390 // Pairwise long 2-register accumulate intrinsics,
391 // both double- and quad-register.
392 // The destination register is also used as the first source operand register.
393 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
394 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
395 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
396 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
397 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
398 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
399 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
400 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
401 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
402 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
403 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
404 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
405 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
406 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
408 // Shift by immediate,
409 // both double- and quad-register.
410 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
411 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
412 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
413 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
414 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
415 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
416 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
417 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
418 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
419 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
420 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
421 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
423 // Long shift by immediate.
424 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
425 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
426 ValueType OpTy, SDNode OpNode>
427 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
428 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
429 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
430 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
431 (i32 imm:$SIMM))))]>;
433 // Narrow shift by immediate.
434 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
435 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
436 ValueType OpTy, SDNode OpNode>
437 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
438 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
439 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
440 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
441 (i32 imm:$SIMM))))]>;
443 // Shift right by immediate and accumulate,
444 // both double- and quad-register.
445 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
446 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
447 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
448 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
449 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
450 [(set DPR:$dst, (Ty (add DPR:$src1,
451 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
452 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
453 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
454 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
455 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
456 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
457 [(set QPR:$dst, (Ty (add QPR:$src1,
458 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
460 // Shift by immediate and insert,
461 // both double- and quad-register.
462 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
463 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
464 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
465 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
466 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
467 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
468 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
469 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
470 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
471 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
472 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
473 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
475 // Convert, with fractional bits immediate,
476 // both double- and quad-register.
477 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
478 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
480 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
481 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
482 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
483 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
484 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
485 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
487 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
488 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
489 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
490 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
492 //===----------------------------------------------------------------------===//
494 //===----------------------------------------------------------------------===//
496 // Neon 3-register vector operations.
498 // First with only element sizes of 8, 16 and 32 bits:
499 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
500 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
501 // 64-bit vector types.
502 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
503 v8i8, v8i8, OpNode, Commutable>;
504 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
505 v4i16, v4i16, OpNode, Commutable>;
506 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
507 v2i32, v2i32, OpNode, Commutable>;
509 // 128-bit vector types.
510 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
511 v16i8, v16i8, OpNode, Commutable>;
512 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
513 v8i16, v8i16, OpNode, Commutable>;
514 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
515 v4i32, v4i32, OpNode, Commutable>;
518 // ....then also with element size 64 bits:
519 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
520 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
521 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
522 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
523 v1i64, v1i64, OpNode, Commutable>;
524 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
525 v2i64, v2i64, OpNode, Commutable>;
529 // Neon Narrowing 2-register vector intrinsics,
530 // source operand element sizes of 16, 32 and 64 bits:
531 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
532 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
534 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
535 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
536 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
537 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
538 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
539 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
543 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
544 // source operand element sizes of 16, 32 and 64 bits:
545 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
546 bit op4, string OpcodeStr, Intrinsic IntOp> {
547 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
548 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
549 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
550 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
551 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
552 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
556 // Neon 3-register vector intrinsics.
558 // First with only element sizes of 16 and 32 bits:
559 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
560 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
561 // 64-bit vector types.
562 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
563 v4i16, v4i16, IntOp, Commutable>;
564 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
565 v2i32, v2i32, IntOp, Commutable>;
567 // 128-bit vector types.
568 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
569 v8i16, v8i16, IntOp, Commutable>;
570 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
571 v4i32, v4i32, IntOp, Commutable>;
574 // ....then also with element size of 8 bits:
575 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
576 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
577 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
578 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
579 v8i8, v8i8, IntOp, Commutable>;
580 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
581 v16i8, v16i8, IntOp, Commutable>;
584 // ....then also with element size of 64 bits:
585 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
586 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
587 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
588 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
589 v1i64, v1i64, IntOp, Commutable>;
590 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
591 v2i64, v2i64, IntOp, Commutable>;
595 // Neon Narrowing 3-register vector intrinsics,
596 // source operand element sizes of 16, 32 and 64 bits:
597 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
598 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
599 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
600 v8i8, v8i16, IntOp, Commutable>;
601 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
602 v4i16, v4i32, IntOp, Commutable>;
603 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
604 v2i32, v2i64, IntOp, Commutable>;
608 // Neon Long 3-register vector intrinsics.
610 // First with only element sizes of 16 and 32 bits:
611 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
612 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
613 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
614 v4i32, v4i16, IntOp, Commutable>;
615 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
616 v2i64, v2i32, IntOp, Commutable>;
619 // ....then also with element size of 8 bits:
620 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
621 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
622 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
623 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
624 v8i16, v8i8, IntOp, Commutable>;
628 // Neon Wide 3-register vector intrinsics,
629 // source operand element sizes of 8, 16 and 32 bits:
630 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
631 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
632 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
633 v8i16, v8i8, IntOp, Commutable>;
634 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
635 v4i32, v4i16, IntOp, Commutable>;
636 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
637 v2i64, v2i32, IntOp, Commutable>;
641 // Neon Multiply-Op vector operations,
642 // element sizes of 8, 16 and 32 bits:
643 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
644 string OpcodeStr, SDNode OpNode> {
645 // 64-bit vector types.
646 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
647 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
648 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
649 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
650 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
651 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
653 // 128-bit vector types.
654 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
655 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
656 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
657 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
658 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
659 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
663 // Neon 3-argument intrinsics,
664 // element sizes of 8, 16 and 32 bits:
665 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
666 string OpcodeStr, Intrinsic IntOp> {
667 // 64-bit vector types.
668 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
669 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
670 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
671 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
672 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
673 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
675 // 128-bit vector types.
676 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
677 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
678 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
679 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
680 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
681 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
685 // Neon Long 3-argument intrinsics.
687 // First with only element sizes of 16 and 32 bits:
688 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
689 string OpcodeStr, Intrinsic IntOp> {
690 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
691 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
692 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
693 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
696 // ....then also with element size of 8 bits:
697 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
698 string OpcodeStr, Intrinsic IntOp>
699 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
700 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
701 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
705 // Neon 2-register vector intrinsics,
706 // element sizes of 8, 16 and 32 bits:
707 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
708 bits<5> op11_7, bit op4, string OpcodeStr,
710 // 64-bit vector types.
711 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
712 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
713 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
714 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
715 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
716 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
718 // 128-bit vector types.
719 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
720 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
721 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
722 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
723 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
724 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
728 // Neon Pairwise long 2-register intrinsics,
729 // element sizes of 8, 16 and 32 bits:
730 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
731 bits<5> op11_7, bit op4,
732 string OpcodeStr, Intrinsic IntOp> {
733 // 64-bit vector types.
734 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
735 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
736 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
737 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
738 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
739 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
741 // 128-bit vector types.
742 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
743 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
744 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
745 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
746 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
747 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
751 // Neon Pairwise long 2-register accumulate intrinsics,
752 // element sizes of 8, 16 and 32 bits:
753 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
754 bits<5> op11_7, bit op4,
755 string OpcodeStr, Intrinsic IntOp> {
756 // 64-bit vector types.
757 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
758 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
759 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
760 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
761 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
762 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
764 // 128-bit vector types.
765 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
766 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
767 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
768 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
769 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
770 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
774 // Neon 2-register vector shift by immediate,
775 // element sizes of 8, 16, 32 and 64 bits:
776 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
777 string OpcodeStr, SDNode OpNode> {
778 // 64-bit vector types.
779 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
780 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
781 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
782 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
783 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
784 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
785 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
786 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
788 // 128-bit vector types.
789 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
790 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
791 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
792 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
793 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
794 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
795 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
796 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
800 // Neon Shift-Accumulate vector operations,
801 // element sizes of 8, 16, 32 and 64 bits:
802 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
803 string OpcodeStr, SDNode ShOp> {
804 // 64-bit vector types.
805 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
806 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
807 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
808 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
809 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
810 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
811 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
812 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
814 // 128-bit vector types.
815 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
816 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
817 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
818 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
819 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
820 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
821 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
822 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
826 // Neon Shift-Insert vector operations,
827 // element sizes of 8, 16, 32 and 64 bits:
828 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
829 string OpcodeStr, SDNode ShOp> {
830 // 64-bit vector types.
831 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
832 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
833 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
834 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
835 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
836 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
837 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
838 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
840 // 128-bit vector types.
841 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
842 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
843 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
844 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
845 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
846 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
847 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
848 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
851 //===----------------------------------------------------------------------===//
852 // Instruction Definitions.
853 //===----------------------------------------------------------------------===//
855 // Vector Add Operations.
857 // VADD : Vector Add (integer and floating-point)
858 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
859 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
860 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
861 // VADDL : Vector Add Long (Q = D + D)
862 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
863 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
864 // VADDW : Vector Add Wide (Q = Q + D)
865 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
866 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
867 // VHADD : Vector Halving Add
868 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
869 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
870 // VRHADD : Vector Rounding Halving Add
871 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
872 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
873 // VQADD : Vector Saturating Add
874 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
875 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
876 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
877 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
878 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
879 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
881 // Vector Multiply Operations.
883 // VMUL : Vector Multiply (integer, polynomial and floating-point)
884 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
885 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
886 int_arm_neon_vmulp, 1>;
887 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
888 int_arm_neon_vmulp, 1>;
889 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
890 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
891 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
892 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
893 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
894 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
895 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
896 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
897 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
898 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
899 int_arm_neon_vmullp, 1>;
900 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
901 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
903 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
905 // VMLA : Vector Multiply Accumulate (integer and floating-point)
906 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
907 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
908 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
909 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
910 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
911 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
912 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
913 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
914 // VMLS : Vector Multiply Subtract (integer and floating-point)
915 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
916 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
917 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
918 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
919 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
920 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
921 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
922 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
924 // Vector Subtract Operations.
926 // VSUB : Vector Subtract (integer and floating-point)
927 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
928 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
929 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
930 // VSUBL : Vector Subtract Long (Q = D - D)
931 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
932 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
933 // VSUBW : Vector Subtract Wide (Q = Q - D)
934 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
935 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
936 // VHSUB : Vector Halving Subtract
937 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
938 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
939 // VQSUB : Vector Saturing Subtract
940 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
941 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
942 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
943 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
944 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
945 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
947 // Vector Comparisons.
949 // VCEQ : Vector Compare Equal
950 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
951 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
952 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
953 // VCGE : Vector Compare Greater Than or Equal
954 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
955 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
956 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
957 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
958 // VCGT : Vector Compare Greater Than
959 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
960 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
961 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
962 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
963 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
964 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
965 int_arm_neon_vacged, 0>;
966 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
967 int_arm_neon_vacgeq, 0>;
968 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
969 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
970 int_arm_neon_vacgtd, 0>;
971 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
972 int_arm_neon_vacgtq, 0>;
973 // VTST : Vector Test Bits
974 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
976 // Vector Bitwise Operations.
978 // VAND : Vector Bitwise AND
979 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
980 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
982 // VEOR : Vector Bitwise Exclusive OR
983 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
984 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
986 // VORR : Vector Bitwise OR
987 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
988 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
990 // VBIC : Vector Bitwise Bit Clear (AND NOT)
991 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
992 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
993 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
994 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
995 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
996 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
998 // VORN : Vector Bitwise OR NOT
999 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1000 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
1001 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1002 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1003 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
1004 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1006 // VMVN : Vector Bitwise NOT
1007 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1008 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
1009 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1010 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1011 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
1012 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1013 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1014 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1016 // VBSL : Vector Bitwise Select
1017 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1018 (ins DPR:$src1, DPR:$src2, DPR:$src3),
1019 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1021 (v2i32 (or (and DPR:$src2, DPR:$src1),
1022 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1023 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1024 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1025 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1027 (v4i32 (or (and QPR:$src2, QPR:$src1),
1028 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1030 // VBIF : Vector Bitwise Insert if False
1031 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1032 // VBIT : Vector Bitwise Insert if True
1033 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1034 // These are not yet implemented. The TwoAddress pass will not go looking
1035 // for equivalent operations with different register constraints; it just
1038 // Vector Absolute Differences.
1040 // VABD : Vector Absolute Difference
1041 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1042 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1043 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1044 int_arm_neon_vabdf, 0>;
1045 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1046 int_arm_neon_vabdf, 0>;
1048 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1049 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1050 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1052 // VABA : Vector Absolute Difference and Accumulate
1053 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1054 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1056 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1057 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1058 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1060 // Vector Maximum and Minimum.
1062 // VMAX : Vector Maximum
1063 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1064 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1065 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1066 int_arm_neon_vmaxf, 1>;
1067 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1068 int_arm_neon_vmaxf, 1>;
1070 // VMIN : Vector Minimum
1071 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1072 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1073 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1074 int_arm_neon_vminf, 1>;
1075 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1076 int_arm_neon_vminf, 1>;
1078 // Vector Pairwise Operations.
1080 // VPADD : Vector Pairwise Add
1081 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1082 int_arm_neon_vpaddi, 0>;
1083 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1084 int_arm_neon_vpaddi, 0>;
1085 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1086 int_arm_neon_vpaddi, 0>;
1087 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1088 int_arm_neon_vpaddf, 0>;
1090 // VPADDL : Vector Pairwise Add Long
1091 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1092 int_arm_neon_vpaddls>;
1093 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1094 int_arm_neon_vpaddlu>;
1096 // VPADAL : Vector Pairwise Add and Accumulate Long
1097 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1098 int_arm_neon_vpadals>;
1099 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1100 int_arm_neon_vpadalu>;
1102 // VPMAX : Vector Pairwise Maximum
1103 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1104 int_arm_neon_vpmaxs, 0>;
1105 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1106 int_arm_neon_vpmaxs, 0>;
1107 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1108 int_arm_neon_vpmaxs, 0>;
1109 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1110 int_arm_neon_vpmaxu, 0>;
1111 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1112 int_arm_neon_vpmaxu, 0>;
1113 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1114 int_arm_neon_vpmaxu, 0>;
1115 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1116 int_arm_neon_vpmaxf, 0>;
1118 // VPMIN : Vector Pairwise Minimum
1119 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1120 int_arm_neon_vpmins, 0>;
1121 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1122 int_arm_neon_vpmins, 0>;
1123 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1124 int_arm_neon_vpmins, 0>;
1125 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1126 int_arm_neon_vpminu, 0>;
1127 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1128 int_arm_neon_vpminu, 0>;
1129 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1130 int_arm_neon_vpminu, 0>;
1131 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1132 int_arm_neon_vpminf, 0>;
1134 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1136 // VRECPE : Vector Reciprocal Estimate
1137 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1138 v2i32, v2i32, int_arm_neon_vrecpe>;
1139 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1140 v4i32, v4i32, int_arm_neon_vrecpe>;
1141 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1142 v2f32, v2f32, int_arm_neon_vrecpef>;
1143 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1144 v4f32, v4f32, int_arm_neon_vrecpef>;
1146 // VRECPS : Vector Reciprocal Step
1147 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1148 int_arm_neon_vrecps, 1>;
1149 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1150 int_arm_neon_vrecps, 1>;
1152 // VRSQRTE : Vector Reciprocal Square Root Estimate
1153 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1154 v2i32, v2i32, int_arm_neon_vrsqrte>;
1155 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1156 v4i32, v4i32, int_arm_neon_vrsqrte>;
1157 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1158 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1159 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1160 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1162 // VRSQRTS : Vector Reciprocal Square Root Step
1163 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1164 int_arm_neon_vrsqrts, 1>;
1165 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1166 int_arm_neon_vrsqrts, 1>;
1170 // VSHL : Vector Shift
1171 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1172 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1173 // VSHL : Vector Shift Left (Immediate)
1174 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1175 // VSHR : Vector Shift Right (Immediate)
1176 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1177 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1179 // VSHLL : Vector Shift Left Long
1180 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1181 v8i16, v8i8, NEONvshlls>;
1182 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1183 v4i32, v4i16, NEONvshlls>;
1184 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1185 v2i64, v2i32, NEONvshlls>;
1186 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1187 v8i16, v8i8, NEONvshllu>;
1188 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1189 v4i32, v4i16, NEONvshllu>;
1190 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1191 v2i64, v2i32, NEONvshllu>;
1193 // VSHLL : Vector Shift Left Long (with maximum shift count)
1194 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1195 v8i16, v8i8, NEONvshlli>;
1196 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1197 v4i32, v4i16, NEONvshlli>;
1198 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1199 v2i64, v2i32, NEONvshlli>;
1201 // VSHRN : Vector Shift Right and Narrow
1202 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1203 v8i8, v8i16, NEONvshrn>;
1204 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1205 v4i16, v4i32, NEONvshrn>;
1206 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1207 v2i32, v2i64, NEONvshrn>;
1209 // VRSHL : Vector Rounding Shift
1210 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1211 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1212 // VRSHR : Vector Rounding Shift Right
1213 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1214 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1216 // VRSHRN : Vector Rounding Shift Right and Narrow
1217 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1218 v8i8, v8i16, NEONvrshrn>;
1219 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1220 v4i16, v4i32, NEONvrshrn>;
1221 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1222 v2i32, v2i64, NEONvrshrn>;
1224 // VQSHL : Vector Saturating Shift
1225 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1226 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1227 // VQSHL : Vector Saturating Shift Left (Immediate)
1228 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1229 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1230 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1231 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1233 // VQSHRN : Vector Saturating Shift Right and Narrow
1234 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1235 v8i8, v8i16, NEONvqshrns>;
1236 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1237 v4i16, v4i32, NEONvqshrns>;
1238 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1239 v2i32, v2i64, NEONvqshrns>;
1240 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1241 v8i8, v8i16, NEONvqshrnu>;
1242 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1243 v4i16, v4i32, NEONvqshrnu>;
1244 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1245 v2i32, v2i64, NEONvqshrnu>;
1247 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1248 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1249 v8i8, v8i16, NEONvqshrnsu>;
1250 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1251 v4i16, v4i32, NEONvqshrnsu>;
1252 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1253 v2i32, v2i64, NEONvqshrnsu>;
1255 // VQRSHL : Vector Saturating Rounding Shift
1256 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1257 int_arm_neon_vqrshifts, 0>;
1258 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1259 int_arm_neon_vqrshiftu, 0>;
1261 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1262 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1263 v8i8, v8i16, NEONvqrshrns>;
1264 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1265 v4i16, v4i32, NEONvqrshrns>;
1266 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1267 v2i32, v2i64, NEONvqrshrns>;
1268 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1269 v8i8, v8i16, NEONvqrshrnu>;
1270 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1271 v4i16, v4i32, NEONvqrshrnu>;
1272 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1273 v2i32, v2i64, NEONvqrshrnu>;
1275 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1276 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1277 v8i8, v8i16, NEONvqrshrnsu>;
1278 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1279 v4i16, v4i32, NEONvqrshrnsu>;
1280 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1281 v2i32, v2i64, NEONvqrshrnsu>;
1283 // VSRA : Vector Shift Right and Accumulate
1284 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1285 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1286 // VRSRA : Vector Rounding Shift Right and Accumulate
1287 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1288 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1290 // VSLI : Vector Shift Left and Insert
1291 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1292 // VSRI : Vector Shift Right and Insert
1293 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1295 // Vector Absolute and Saturating Absolute.
1297 // VABS : Vector Absolute Value
1298 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1300 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1301 v2f32, v2f32, int_arm_neon_vabsf>;
1302 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1303 v4f32, v4f32, int_arm_neon_vabsf>;
1305 // VQABS : Vector Saturating Absolute Value
1306 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1307 int_arm_neon_vqabs>;
1311 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1312 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1314 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1315 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1316 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1317 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1318 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1319 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1320 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1321 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1323 // VNEG : Vector Negate
1324 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1325 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1326 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1327 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1328 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1329 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1331 // VNEG : Vector Negate (floating-point)
1332 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1333 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1334 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1335 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1336 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1337 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1339 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1340 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1341 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1342 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1343 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1344 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1346 // VQNEG : Vector Saturating Negate
1347 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1348 int_arm_neon_vqneg>;
1350 // Vector Bit Counting Operations.
1352 // VCLS : Vector Count Leading Sign Bits
1353 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1355 // VCLZ : Vector Count Leading Zeros
1356 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1358 // VCNT : Vector Count One Bits
1359 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1360 v8i8, v8i8, int_arm_neon_vcnt>;
1361 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1362 v16i8, v16i8, int_arm_neon_vcnt>;
1364 // Vector Move Operations.
1366 // VMOV : Vector Move (Register)
1368 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1369 "vmov\t$dst, $src", "", []>;
1370 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1371 "vmov\t$dst, $src", "", []>;
1373 // VMOV : Vector Move (Immediate)
1375 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1376 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1377 return ARM::getVMOVImm(N, 1, *CurDAG);
1379 def vmovImm8 : PatLeaf<(build_vector), [{
1380 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1383 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1384 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1385 return ARM::getVMOVImm(N, 2, *CurDAG);
1387 def vmovImm16 : PatLeaf<(build_vector), [{
1388 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1389 }], VMOV_get_imm16>;
1391 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1392 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1393 return ARM::getVMOVImm(N, 4, *CurDAG);
1395 def vmovImm32 : PatLeaf<(build_vector), [{
1396 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1397 }], VMOV_get_imm32>;
1399 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1400 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1401 return ARM::getVMOVImm(N, 8, *CurDAG);
1403 def vmovImm64 : PatLeaf<(build_vector), [{
1404 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1405 }], VMOV_get_imm64>;
1407 // Note: Some of the cmode bits in the following VMOV instructions need to
1408 // be encoded based on the immed values.
1410 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1411 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1412 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1413 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1414 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1415 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1417 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1418 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1419 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1420 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1421 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1422 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1424 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1425 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1426 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1427 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1428 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1429 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1431 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1432 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1433 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1434 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1435 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1436 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1438 // VMOV : Vector Get Lane (move scalar to ARM core register)
1440 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1441 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1442 "vmov", ".s8\t$dst, $src[$lane]",
1443 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1445 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1446 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1447 "vmov", ".s16\t$dst, $src[$lane]",
1448 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1450 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1451 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1452 "vmov", ".u8\t$dst, $src[$lane]",
1453 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1455 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1456 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1457 "vmov", ".u16\t$dst, $src[$lane]",
1458 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1460 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1461 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1462 "vmov", ".32\t$dst, $src[$lane]",
1463 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1465 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1466 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1467 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1468 (SubReg_i8_reg imm:$lane))),
1469 (SubReg_i8_lane imm:$lane))>;
1470 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1471 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1472 (SubReg_i16_reg imm:$lane))),
1473 (SubReg_i16_lane imm:$lane))>;
1474 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1475 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1476 (SubReg_i8_reg imm:$lane))),
1477 (SubReg_i8_lane imm:$lane))>;
1478 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1479 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1480 (SubReg_i16_reg imm:$lane))),
1481 (SubReg_i16_lane imm:$lane))>;
1482 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1483 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1484 (SubReg_i32_reg imm:$lane))),
1485 (SubReg_i32_lane imm:$lane))>;
1486 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1487 // (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1488 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1489 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1492 // VMOV : Vector Set Lane (move ARM core register to scalar)
1494 let Constraints = "$src1 = $dst" in {
1495 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1496 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1497 "vmov", ".8\t$dst[$lane], $src2",
1498 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1499 GPR:$src2, imm:$lane))]>;
1500 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1501 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1502 "vmov", ".16\t$dst[$lane], $src2",
1503 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1504 GPR:$src2, imm:$lane))]>;
1505 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1506 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1507 "vmov", ".32\t$dst[$lane], $src2",
1508 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1509 GPR:$src2, imm:$lane))]>;
1511 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1512 (v16i8 (INSERT_SUBREG QPR:$src1,
1513 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1514 (SubReg_i8_reg imm:$lane))),
1515 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1516 (SubReg_i8_reg imm:$lane)))>;
1517 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1518 (v8i16 (INSERT_SUBREG QPR:$src1,
1519 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1520 (SubReg_i16_reg imm:$lane))),
1521 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1522 (SubReg_i16_reg imm:$lane)))>;
1523 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1524 (v4i32 (INSERT_SUBREG QPR:$src1,
1525 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1526 (SubReg_i32_reg imm:$lane))),
1527 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1528 (SubReg_i32_reg imm:$lane)))>;
1530 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1531 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1532 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1533 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1535 // VDUP : Vector Duplicate (from ARM core register to all elements)
1537 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1538 (vector_shuffle node:$lhs, node:$rhs), [{
1539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1540 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1543 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1544 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1545 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1546 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1547 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1548 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1549 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1550 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1552 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1553 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1554 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1555 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1556 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1557 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1559 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1560 "vdup", ".32\t$dst, $src",
1561 [(set DPR:$dst, (v2f32 (splat_lo
1563 (f32 (bitconvert GPR:$src))),
1565 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1566 "vdup", ".32\t$dst, $src",
1567 [(set QPR:$dst, (v4f32 (splat_lo
1569 (f32 (bitconvert GPR:$src))),
1572 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1574 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1576 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1579 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1580 (vector_shuffle node:$lhs, node:$rhs), [{
1581 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1582 return SVOp->isSplat();
1583 }], SHUFFLE_get_splat_lane>;
1585 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1586 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1587 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1588 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1589 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1591 // vector_shuffle requires that the source and destination types match, so
1592 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1593 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1594 ValueType ResTy, ValueType OpTy>
1595 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1596 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1597 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1598 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1600 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1601 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1602 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1603 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1604 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1605 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1606 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1607 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1609 // VMOVN : Vector Narrowing Move
1610 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1611 int_arm_neon_vmovn>;
1612 // VQMOVN : Vector Saturating Narrowing Move
1613 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1614 int_arm_neon_vqmovns>;
1615 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1616 int_arm_neon_vqmovnu>;
1617 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1618 int_arm_neon_vqmovnsu>;
1619 // VMOVL : Vector Lengthening Move
1620 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1621 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1623 // Vector Conversions.
1625 // VCVT : Vector Convert Between Floating-Point and Integers
1626 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1627 v2i32, v2f32, fp_to_sint>;
1628 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1629 v2i32, v2f32, fp_to_uint>;
1630 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1631 v2f32, v2i32, sint_to_fp>;
1632 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1633 v2f32, v2i32, uint_to_fp>;
1635 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1636 v4i32, v4f32, fp_to_sint>;
1637 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1638 v4i32, v4f32, fp_to_uint>;
1639 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1640 v4f32, v4i32, sint_to_fp>;
1641 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1642 v4f32, v4i32, uint_to_fp>;
1644 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1645 // Note: Some of the opcode bits in the following VCVT instructions need to
1646 // be encoded based on the immed values.
1647 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1648 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1649 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1650 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1651 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1652 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1653 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1654 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1656 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1657 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1658 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1659 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1660 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1661 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1662 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1663 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1665 // VREV : Vector Reverse
1667 def vrev64_shuffle : PatFrag<(ops node:$in),
1668 (vector_shuffle node:$in, undef), [{
1669 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1670 return ARM::isVREVMask(SVOp, 64);
1673 def vrev32_shuffle : PatFrag<(ops node:$in),
1674 (vector_shuffle node:$in, undef), [{
1675 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1676 return ARM::isVREVMask(SVOp, 32);
1679 def vrev16_shuffle : PatFrag<(ops node:$in),
1680 (vector_shuffle node:$in, undef), [{
1681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1682 return ARM::isVREVMask(SVOp, 16);
1685 // VREV64 : Vector Reverse elements within 64-bit doublewords
1687 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1688 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1689 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1690 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1691 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1692 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1693 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1694 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1696 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1697 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1698 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1699 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1701 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1702 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1703 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1704 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1706 // VREV32 : Vector Reverse elements within 32-bit words
1708 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1709 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1710 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1711 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1712 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1713 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1714 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1715 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1717 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1718 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1720 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1721 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1723 // VREV16 : Vector Reverse elements within 16-bit halfwords
1725 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1726 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1727 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1728 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1729 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1730 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1731 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1732 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1734 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1735 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1737 //===----------------------------------------------------------------------===//
1738 // Non-Instruction Patterns
1739 //===----------------------------------------------------------------------===//
1742 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1743 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1744 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1745 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1746 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1747 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1748 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1749 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1750 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1751 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1752 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1753 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1754 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1755 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1756 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1757 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1758 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1759 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1760 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1761 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1762 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1763 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1764 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1765 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1766 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1767 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1768 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1769 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1770 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1771 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1773 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1774 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1775 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1776 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1777 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1778 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1779 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1780 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1781 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1782 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1783 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1784 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1785 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1786 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1787 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1788 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1789 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1790 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1791 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1792 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1793 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1794 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1795 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1796 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1797 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1798 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1799 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1800 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1801 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1802 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;