1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
99 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
100 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
101 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
103 //===----------------------------------------------------------------------===//
104 // NEON operand definitions
105 //===----------------------------------------------------------------------===//
107 // addrmode_neonldstm := reg
109 /* TODO: Take advantage of vldm.
110 def addrmode_neonldstm : Operand<i32>,
111 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
112 let PrintMethod = "printAddrNeonLdStMOperand";
113 let MIOperandInfo = (ops GPR, i32imm);
117 //===----------------------------------------------------------------------===//
118 // NEON load / store instructions
119 //===----------------------------------------------------------------------===//
121 /* TODO: Take advantage of vldm.
123 def VLDMD : NI<(outs),
124 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
126 "vldm${addr:submode} ${addr:base}, $dst1",
128 let Inst{27-25} = 0b110;
130 let Inst{11-9} = 0b101;
133 def VLDMS : NI<(outs),
134 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
136 "vldm${addr:submode} ${addr:base}, $dst1",
138 let Inst{27-25} = 0b110;
140 let Inst{11-9} = 0b101;
145 // Use vldmia to load a Q register as a D register pair.
146 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
148 "vldmia $addr, ${dst:dregpair}",
149 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // Use vstmia to store a Q register as a D register pair.
158 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
160 "vstmia $addr, ${src:dregpair}",
161 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
162 let Inst{27-25} = 0b110;
163 let Inst{24} = 0; // P bit
164 let Inst{23} = 1; // U bit
166 let Inst{11-9} = 0b101;
169 // VLD1 : Vector Load (multiple single elements)
170 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
171 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
173 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
174 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
175 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
176 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
178 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
179 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
181 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
182 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
183 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
184 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
185 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
187 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
188 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
189 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
190 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
191 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
195 // VLD2 : Vector Load (multiple 2-element structures)
196 class VLD2D<string OpcodeStr>
197 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
199 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
201 def VLD2d8 : VLD2D<"vld2.8">;
202 def VLD2d16 : VLD2D<"vld2.16">;
203 def VLD2d32 : VLD2D<"vld2.32">;
205 // VLD3 : Vector Load (multiple 3-element structures)
206 class VLD3D<string OpcodeStr>
207 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
209 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
211 def VLD3d8 : VLD3D<"vld3.8">;
212 def VLD3d16 : VLD3D<"vld3.16">;
213 def VLD3d32 : VLD3D<"vld3.32">;
215 // VLD4 : Vector Load (multiple 4-element structures)
216 class VLD4D<string OpcodeStr>
217 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
218 (ins addrmode6:$addr),
220 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
222 def VLD4d8 : VLD4D<"vld4.8">;
223 def VLD4d16 : VLD4D<"vld4.16">;
224 def VLD4d32 : VLD4D<"vld4.32">;
227 // VST1 : Vector Store (multiple single elements)
228 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
229 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
231 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
232 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
233 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
234 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
236 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
237 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
239 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
240 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
241 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
242 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
243 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
245 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
246 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
247 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
248 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
249 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
251 let mayStore = 1 in {
253 // VST2 : Vector Store (multiple 2-element structures)
254 class VST2D<string OpcodeStr>
255 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
256 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
258 def VST2d8 : VST2D<"vst2.8">;
259 def VST2d16 : VST2D<"vst2.16">;
260 def VST2d32 : VST2D<"vst2.32">;
262 // VST3 : Vector Store (multiple 3-element structures)
263 class VST3D<string OpcodeStr>
264 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
266 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
268 def VST3d8 : VST3D<"vst3.8">;
269 def VST3d16 : VST3D<"vst3.16">;
270 def VST3d32 : VST3D<"vst3.32">;
272 // VST4 : Vector Store (multiple 4-element structures)
273 class VST4D<string OpcodeStr>
274 : NLdSt<(outs), (ins addrmode6:$addr,
275 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
276 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
278 def VST4d8 : VST4D<"vst4.8">;
279 def VST4d16 : VST4D<"vst4.16">;
280 def VST4d32 : VST4D<"vst4.32">;
284 //===----------------------------------------------------------------------===//
285 // NEON pattern fragments
286 //===----------------------------------------------------------------------===//
288 // Extract D sub-registers of Q registers.
289 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
290 def DSubReg_i8_reg : SDNodeXForm<imm, [{
291 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
293 def DSubReg_i16_reg : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
296 def DSubReg_i32_reg : SDNodeXForm<imm, [{
297 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
299 def DSubReg_f64_reg : SDNodeXForm<imm, [{
300 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
303 // Extract S sub-registers of Q registers.
304 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
305 def SSubReg_f32_reg : SDNodeXForm<imm, [{
306 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
309 // Translate lane numbers from Q registers to D subregs.
310 def SubReg_i8_lane : SDNodeXForm<imm, [{
311 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
313 def SubReg_i16_lane : SDNodeXForm<imm, [{
314 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
316 def SubReg_i32_lane : SDNodeXForm<imm, [{
317 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
320 //===----------------------------------------------------------------------===//
321 // Instruction Classes
322 //===----------------------------------------------------------------------===//
324 // Basic 2-register operations, both double- and quad-register.
325 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
326 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
327 ValueType ResTy, ValueType OpTy, SDNode OpNode>
328 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
329 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
330 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
331 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
332 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
333 ValueType ResTy, ValueType OpTy, SDNode OpNode>
334 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
335 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
336 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
338 // Basic 2-register operations, scalar single-precision.
339 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
340 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
341 ValueType ResTy, ValueType OpTy, SDNode OpNode>
342 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
343 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
344 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
346 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
347 : NEONFPPat<(ResTy (OpNode SPR:$a)),
349 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
352 // Basic 2-register intrinsics, both double- and quad-register.
353 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
354 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
355 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
356 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
357 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
358 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
359 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
360 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
361 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
362 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
363 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
364 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
366 // Basic 2-register intrinsics, scalar single-precision
367 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
368 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
369 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
370 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
371 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
372 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
374 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
375 : NEONFPPat<(f32 (OpNode SPR:$a)),
377 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
380 // Narrow 2-register intrinsics.
381 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
382 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
383 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
384 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
385 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
386 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
388 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
389 // derived from N2VImm instead of N2V because of the way the size is encoded.)
390 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
391 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
393 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
394 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
395 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
397 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
398 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
399 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
400 (ins DPR:$src1, DPR:$src2), NoItinerary,
401 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
402 "$src1 = $dst1, $src2 = $dst2", []>;
403 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
404 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
405 (ins QPR:$src1, QPR:$src2), NoItinerary,
406 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
407 "$src1 = $dst1, $src2 = $dst2", []>;
409 // Basic 3-register operations, both double- and quad-register.
410 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
411 string OpcodeStr, ValueType ResTy, ValueType OpTy,
412 SDNode OpNode, bit Commutable>
413 : N3V<op24, op23, op21_20, op11_8, 0, op4,
414 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
415 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
416 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
417 let isCommutable = Commutable;
419 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
420 string OpcodeStr, ValueType ResTy, ValueType OpTy,
421 SDNode OpNode, bit Commutable>
422 : N3V<op24, op23, op21_20, op11_8, 1, op4,
423 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
424 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
425 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
426 let isCommutable = Commutable;
429 // Basic 3-register operations, scalar single-precision
430 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
431 string OpcodeStr, ValueType ResTy, ValueType OpTy,
432 SDNode OpNode, bit Commutable>
433 : N3V<op24, op23, op21_20, op11_8, 0, op4,
434 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
435 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
436 let isCommutable = Commutable;
438 class N3VDsPat<SDNode OpNode, NeonI Inst>
439 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
441 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
442 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
445 // Basic 3-register intrinsics, both double- and quad-register.
446 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
447 string OpcodeStr, ValueType ResTy, ValueType OpTy,
448 Intrinsic IntOp, bit Commutable>
449 : N3V<op24, op23, op21_20, op11_8, 0, op4,
450 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
451 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
452 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
453 let isCommutable = Commutable;
455 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
456 string OpcodeStr, ValueType ResTy, ValueType OpTy,
457 Intrinsic IntOp, bit Commutable>
458 : N3V<op24, op23, op21_20, op11_8, 1, op4,
459 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
460 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
461 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
462 let isCommutable = Commutable;
465 // Multiply-Add/Sub operations, both double- and quad-register.
466 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
467 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
468 : N3V<op24, op23, op21_20, op11_8, 0, op4,
469 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
470 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
471 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
472 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
473 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
474 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
475 : N3V<op24, op23, op21_20, op11_8, 1, op4,
476 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
477 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
478 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
479 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
481 // Multiply-Add/Sub operations, scalar single-precision
482 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
483 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
484 : N3V<op24, op23, op21_20, op11_8, 0, op4,
485 (outs DPR_VFP2:$dst),
486 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
487 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
489 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
490 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
492 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
493 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
494 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
497 // Neon 3-argument intrinsics, both double- and quad-register.
498 // The destination register is also used as the first source operand register.
499 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
500 string OpcodeStr, ValueType ResTy, ValueType OpTy,
502 : N3V<op24, op23, op21_20, op11_8, 0, op4,
503 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
504 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
505 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
506 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
507 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
508 string OpcodeStr, ValueType ResTy, ValueType OpTy,
510 : N3V<op24, op23, op21_20, op11_8, 1, op4,
511 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
512 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
513 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
514 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
516 // Neon Long 3-argument intrinsic. The destination register is
517 // a quad-register and is also used as the first source operand register.
518 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
519 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
520 : N3V<op24, op23, op21_20, op11_8, 0, op4,
521 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
522 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
524 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
526 // Narrowing 3-register intrinsics.
527 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
528 string OpcodeStr, ValueType TyD, ValueType TyQ,
529 Intrinsic IntOp, bit Commutable>
530 : N3V<op24, op23, op21_20, op11_8, 0, op4,
531 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
532 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
533 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
534 let isCommutable = Commutable;
537 // Long 3-register intrinsics.
538 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
539 string OpcodeStr, ValueType TyQ, ValueType TyD,
540 Intrinsic IntOp, bit Commutable>
541 : N3V<op24, op23, op21_20, op11_8, 0, op4,
542 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
543 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
544 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
545 let isCommutable = Commutable;
548 // Wide 3-register intrinsics.
549 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
550 string OpcodeStr, ValueType TyQ, ValueType TyD,
551 Intrinsic IntOp, bit Commutable>
552 : N3V<op24, op23, op21_20, op11_8, 0, op4,
553 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
554 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
555 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
556 let isCommutable = Commutable;
559 // Pairwise long 2-register intrinsics, both double- and quad-register.
560 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
561 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
562 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
563 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
564 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
565 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
566 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
567 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
568 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
569 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
570 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
571 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
573 // Pairwise long 2-register accumulate intrinsics,
574 // both double- and quad-register.
575 // The destination register is also used as the first source operand register.
576 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
577 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
578 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
579 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
580 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
581 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
582 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
583 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
584 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
585 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
586 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
587 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
588 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
589 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
591 // Shift by immediate,
592 // both double- and quad-register.
593 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
594 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
595 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
596 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
597 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
598 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
599 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
600 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
601 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
602 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
603 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
604 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
606 // Long shift by immediate.
607 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
608 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
609 ValueType OpTy, SDNode OpNode>
610 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
611 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
612 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
613 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
614 (i32 imm:$SIMM))))]>;
616 // Narrow shift by immediate.
617 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
618 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
619 ValueType OpTy, SDNode OpNode>
620 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
621 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
622 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
623 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
624 (i32 imm:$SIMM))))]>;
626 // Shift right by immediate and accumulate,
627 // both double- and quad-register.
628 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
629 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
630 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
631 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
633 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
634 [(set DPR:$dst, (Ty (add DPR:$src1,
635 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
636 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
637 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
638 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
639 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
641 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
642 [(set QPR:$dst, (Ty (add QPR:$src1,
643 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
645 // Shift by immediate and insert,
646 // both double- and quad-register.
647 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
648 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
649 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
650 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
652 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
653 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
654 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
655 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
656 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
657 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
659 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
660 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
662 // Convert, with fractional bits immediate,
663 // both double- and quad-register.
664 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
665 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
667 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
668 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
669 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
670 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
671 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
672 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
674 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
675 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
676 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
677 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 // Neon 3-register vector operations.
685 // First with only element sizes of 8, 16 and 32 bits:
686 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
687 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
688 // 64-bit vector types.
689 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
690 v8i8, v8i8, OpNode, Commutable>;
691 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
692 v4i16, v4i16, OpNode, Commutable>;
693 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
694 v2i32, v2i32, OpNode, Commutable>;
696 // 128-bit vector types.
697 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
698 v16i8, v16i8, OpNode, Commutable>;
699 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
700 v8i16, v8i16, OpNode, Commutable>;
701 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
702 v4i32, v4i32, OpNode, Commutable>;
705 // ....then also with element size 64 bits:
706 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
707 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
708 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
709 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
710 v1i64, v1i64, OpNode, Commutable>;
711 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
712 v2i64, v2i64, OpNode, Commutable>;
716 // Neon Narrowing 2-register vector intrinsics,
717 // source operand element sizes of 16, 32 and 64 bits:
718 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
719 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
721 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
722 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
723 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
724 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
725 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
726 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
730 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
731 // source operand element sizes of 16, 32 and 64 bits:
732 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
733 bit op4, string OpcodeStr, Intrinsic IntOp> {
734 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
735 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
736 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
737 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
738 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
739 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
743 // Neon 3-register vector intrinsics.
745 // First with only element sizes of 16 and 32 bits:
746 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
747 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
748 // 64-bit vector types.
749 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
750 v4i16, v4i16, IntOp, Commutable>;
751 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
752 v2i32, v2i32, IntOp, Commutable>;
754 // 128-bit vector types.
755 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
756 v8i16, v8i16, IntOp, Commutable>;
757 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
758 v4i32, v4i32, IntOp, Commutable>;
761 // ....then also with element size of 8 bits:
762 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
763 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
764 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
765 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
766 v8i8, v8i8, IntOp, Commutable>;
767 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
768 v16i8, v16i8, IntOp, Commutable>;
771 // ....then also with element size of 64 bits:
772 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
773 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
774 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
775 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
776 v1i64, v1i64, IntOp, Commutable>;
777 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
778 v2i64, v2i64, IntOp, Commutable>;
782 // Neon Narrowing 3-register vector intrinsics,
783 // source operand element sizes of 16, 32 and 64 bits:
784 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
785 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
786 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
787 v8i8, v8i16, IntOp, Commutable>;
788 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
789 v4i16, v4i32, IntOp, Commutable>;
790 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
791 v2i32, v2i64, IntOp, Commutable>;
795 // Neon Long 3-register vector intrinsics.
797 // First with only element sizes of 16 and 32 bits:
798 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
799 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
800 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
801 v4i32, v4i16, IntOp, Commutable>;
802 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
803 v2i64, v2i32, IntOp, Commutable>;
806 // ....then also with element size of 8 bits:
807 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
808 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
809 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
810 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
811 v8i16, v8i8, IntOp, Commutable>;
815 // Neon Wide 3-register vector intrinsics,
816 // source operand element sizes of 8, 16 and 32 bits:
817 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
818 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
819 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
820 v8i16, v8i8, IntOp, Commutable>;
821 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
822 v4i32, v4i16, IntOp, Commutable>;
823 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
824 v2i64, v2i32, IntOp, Commutable>;
828 // Neon Multiply-Op vector operations,
829 // element sizes of 8, 16 and 32 bits:
830 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
831 string OpcodeStr, SDNode OpNode> {
832 // 64-bit vector types.
833 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
834 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
835 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
836 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
837 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
838 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
840 // 128-bit vector types.
841 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
842 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
843 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
844 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
845 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
846 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
850 // Neon 3-argument intrinsics,
851 // element sizes of 8, 16 and 32 bits:
852 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
853 string OpcodeStr, Intrinsic IntOp> {
854 // 64-bit vector types.
855 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
856 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
857 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
858 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
859 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
860 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
862 // 128-bit vector types.
863 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
864 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
865 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
866 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
867 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
868 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
872 // Neon Long 3-argument intrinsics.
874 // First with only element sizes of 16 and 32 bits:
875 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
876 string OpcodeStr, Intrinsic IntOp> {
877 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
878 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
879 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
880 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
883 // ....then also with element size of 8 bits:
884 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
885 string OpcodeStr, Intrinsic IntOp>
886 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
887 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
888 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
892 // Neon 2-register vector intrinsics,
893 // element sizes of 8, 16 and 32 bits:
894 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
895 bits<5> op11_7, bit op4, string OpcodeStr,
897 // 64-bit vector types.
898 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
899 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
900 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
901 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
902 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
903 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
905 // 128-bit vector types.
906 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
907 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
908 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
909 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
910 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
911 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
915 // Neon Pairwise long 2-register intrinsics,
916 // element sizes of 8, 16 and 32 bits:
917 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
918 bits<5> op11_7, bit op4,
919 string OpcodeStr, Intrinsic IntOp> {
920 // 64-bit vector types.
921 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
922 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
923 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
924 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
925 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
926 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
928 // 128-bit vector types.
929 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
930 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
931 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
932 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
933 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
934 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
938 // Neon Pairwise long 2-register accumulate intrinsics,
939 // element sizes of 8, 16 and 32 bits:
940 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
941 bits<5> op11_7, bit op4,
942 string OpcodeStr, Intrinsic IntOp> {
943 // 64-bit vector types.
944 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
945 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
946 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
947 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
948 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
949 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
951 // 128-bit vector types.
952 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
953 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
954 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
955 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
956 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
957 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
961 // Neon 2-register vector shift by immediate,
962 // element sizes of 8, 16, 32 and 64 bits:
963 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
964 string OpcodeStr, SDNode OpNode> {
965 // 64-bit vector types.
966 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
967 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
968 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
969 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
970 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
971 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
972 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
973 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
975 // 128-bit vector types.
976 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
977 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
978 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
979 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
980 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
981 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
982 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
983 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
987 // Neon Shift-Accumulate vector operations,
988 // element sizes of 8, 16, 32 and 64 bits:
989 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
990 string OpcodeStr, SDNode ShOp> {
991 // 64-bit vector types.
992 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
993 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
994 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
995 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
996 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
997 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
998 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
999 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1001 // 128-bit vector types.
1002 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1003 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1004 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1005 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1006 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1007 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1008 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1009 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1013 // Neon Shift-Insert vector operations,
1014 // element sizes of 8, 16, 32 and 64 bits:
1015 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1016 string OpcodeStr, SDNode ShOp> {
1017 // 64-bit vector types.
1018 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1019 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1020 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1021 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1022 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1023 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1024 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1025 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1027 // 128-bit vector types.
1028 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1029 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1030 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1031 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1032 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1033 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1034 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1035 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1038 //===----------------------------------------------------------------------===//
1039 // Instruction Definitions.
1040 //===----------------------------------------------------------------------===//
1042 // Vector Add Operations.
1044 // VADD : Vector Add (integer and floating-point)
1045 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1046 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1047 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1048 // VADDL : Vector Add Long (Q = D + D)
1049 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1050 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1051 // VADDW : Vector Add Wide (Q = Q + D)
1052 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1053 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1054 // VHADD : Vector Halving Add
1055 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1056 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1057 // VRHADD : Vector Rounding Halving Add
1058 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1059 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1060 // VQADD : Vector Saturating Add
1061 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1062 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1063 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1064 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1065 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1066 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1068 // Vector Multiply Operations.
1070 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1071 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1072 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1073 int_arm_neon_vmulp, 1>;
1074 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1075 int_arm_neon_vmulp, 1>;
1076 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1077 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1078 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1079 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1080 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1081 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1082 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1083 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1084 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1085 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1086 int_arm_neon_vmullp, 1>;
1087 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1088 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1090 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1092 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1093 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1094 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1095 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1096 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1097 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1098 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1099 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1100 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1101 // VMLS : Vector Multiply Subtract (integer and floating-point)
1102 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1103 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1104 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1105 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1106 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1107 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1108 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1109 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1111 // Vector Subtract Operations.
1113 // VSUB : Vector Subtract (integer and floating-point)
1114 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1115 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1116 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1117 // VSUBL : Vector Subtract Long (Q = D - D)
1118 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1119 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1120 // VSUBW : Vector Subtract Wide (Q = Q - D)
1121 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1122 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1123 // VHSUB : Vector Halving Subtract
1124 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1125 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1126 // VQSUB : Vector Saturing Subtract
1127 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1128 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1129 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1130 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1131 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1132 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1134 // Vector Comparisons.
1136 // VCEQ : Vector Compare Equal
1137 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1138 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1139 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1140 // VCGE : Vector Compare Greater Than or Equal
1141 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1142 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1143 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1144 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1145 // VCGT : Vector Compare Greater Than
1146 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1147 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1148 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1149 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1150 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1151 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1152 int_arm_neon_vacged, 0>;
1153 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1154 int_arm_neon_vacgeq, 0>;
1155 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1156 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1157 int_arm_neon_vacgtd, 0>;
1158 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1159 int_arm_neon_vacgtq, 0>;
1160 // VTST : Vector Test Bits
1161 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1163 // Vector Bitwise Operations.
1165 // VAND : Vector Bitwise AND
1166 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1167 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1169 // VEOR : Vector Bitwise Exclusive OR
1170 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1171 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1173 // VORR : Vector Bitwise OR
1174 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1175 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1177 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1178 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1179 (ins DPR:$src1, DPR:$src2), NoItinerary,
1180 "vbic\t$dst, $src1, $src2", "",
1181 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1182 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1183 (ins QPR:$src1, QPR:$src2), NoItinerary,
1184 "vbic\t$dst, $src1, $src2", "",
1185 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1187 // VORN : Vector Bitwise OR NOT
1188 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1189 (ins DPR:$src1, DPR:$src2), NoItinerary,
1190 "vorn\t$dst, $src1, $src2", "",
1191 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1192 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1193 (ins QPR:$src1, QPR:$src2), NoItinerary,
1194 "vorn\t$dst, $src1, $src2", "",
1195 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1197 // VMVN : Vector Bitwise NOT
1198 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1199 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1200 "vmvn\t$dst, $src", "",
1201 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1202 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1203 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1204 "vmvn\t$dst, $src", "",
1205 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1206 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1207 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1209 // VBSL : Vector Bitwise Select
1210 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1211 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1212 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1214 (v2i32 (or (and DPR:$src2, DPR:$src1),
1215 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1216 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1217 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1218 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1220 (v4i32 (or (and QPR:$src2, QPR:$src1),
1221 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1223 // VBIF : Vector Bitwise Insert if False
1224 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1225 // VBIT : Vector Bitwise Insert if True
1226 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1227 // These are not yet implemented. The TwoAddress pass will not go looking
1228 // for equivalent operations with different register constraints; it just
1231 // Vector Absolute Differences.
1233 // VABD : Vector Absolute Difference
1234 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1235 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1236 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1237 int_arm_neon_vabds, 0>;
1238 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1239 int_arm_neon_vabds, 0>;
1241 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1242 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1243 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1245 // VABA : Vector Absolute Difference and Accumulate
1246 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1247 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1249 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1250 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1251 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1253 // Vector Maximum and Minimum.
1255 // VMAX : Vector Maximum
1256 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1257 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1258 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1259 int_arm_neon_vmaxs, 1>;
1260 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1261 int_arm_neon_vmaxs, 1>;
1263 // VMIN : Vector Minimum
1264 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1265 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1266 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1267 int_arm_neon_vmins, 1>;
1268 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1269 int_arm_neon_vmins, 1>;
1271 // Vector Pairwise Operations.
1273 // VPADD : Vector Pairwise Add
1274 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1275 int_arm_neon_vpadd, 0>;
1276 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1277 int_arm_neon_vpadd, 0>;
1278 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1279 int_arm_neon_vpadd, 0>;
1280 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1281 int_arm_neon_vpadd, 0>;
1283 // VPADDL : Vector Pairwise Add Long
1284 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1285 int_arm_neon_vpaddls>;
1286 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1287 int_arm_neon_vpaddlu>;
1289 // VPADAL : Vector Pairwise Add and Accumulate Long
1290 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1291 int_arm_neon_vpadals>;
1292 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1293 int_arm_neon_vpadalu>;
1295 // VPMAX : Vector Pairwise Maximum
1296 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1297 int_arm_neon_vpmaxs, 0>;
1298 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1299 int_arm_neon_vpmaxs, 0>;
1300 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1301 int_arm_neon_vpmaxs, 0>;
1302 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1303 int_arm_neon_vpmaxu, 0>;
1304 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1305 int_arm_neon_vpmaxu, 0>;
1306 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1307 int_arm_neon_vpmaxu, 0>;
1308 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1309 int_arm_neon_vpmaxs, 0>;
1311 // VPMIN : Vector Pairwise Minimum
1312 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1313 int_arm_neon_vpmins, 0>;
1314 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1315 int_arm_neon_vpmins, 0>;
1316 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1317 int_arm_neon_vpmins, 0>;
1318 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1319 int_arm_neon_vpminu, 0>;
1320 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1321 int_arm_neon_vpminu, 0>;
1322 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1323 int_arm_neon_vpminu, 0>;
1324 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1325 int_arm_neon_vpmins, 0>;
1327 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1329 // VRECPE : Vector Reciprocal Estimate
1330 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1331 v2i32, v2i32, int_arm_neon_vrecpe>;
1332 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1333 v4i32, v4i32, int_arm_neon_vrecpe>;
1334 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1335 v2f32, v2f32, int_arm_neon_vrecpe>;
1336 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1337 v4f32, v4f32, int_arm_neon_vrecpe>;
1339 // VRECPS : Vector Reciprocal Step
1340 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1341 int_arm_neon_vrecps, 1>;
1342 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1343 int_arm_neon_vrecps, 1>;
1345 // VRSQRTE : Vector Reciprocal Square Root Estimate
1346 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1347 v2i32, v2i32, int_arm_neon_vrsqrte>;
1348 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1349 v4i32, v4i32, int_arm_neon_vrsqrte>;
1350 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1351 v2f32, v2f32, int_arm_neon_vrsqrte>;
1352 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1353 v4f32, v4f32, int_arm_neon_vrsqrte>;
1355 // VRSQRTS : Vector Reciprocal Square Root Step
1356 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1357 int_arm_neon_vrsqrts, 1>;
1358 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1359 int_arm_neon_vrsqrts, 1>;
1363 // VSHL : Vector Shift
1364 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1365 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1366 // VSHL : Vector Shift Left (Immediate)
1367 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1368 // VSHR : Vector Shift Right (Immediate)
1369 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1370 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1372 // VSHLL : Vector Shift Left Long
1373 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1374 v8i16, v8i8, NEONvshlls>;
1375 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1376 v4i32, v4i16, NEONvshlls>;
1377 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1378 v2i64, v2i32, NEONvshlls>;
1379 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1380 v8i16, v8i8, NEONvshllu>;
1381 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1382 v4i32, v4i16, NEONvshllu>;
1383 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1384 v2i64, v2i32, NEONvshllu>;
1386 // VSHLL : Vector Shift Left Long (with maximum shift count)
1387 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1388 v8i16, v8i8, NEONvshlli>;
1389 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1390 v4i32, v4i16, NEONvshlli>;
1391 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1392 v2i64, v2i32, NEONvshlli>;
1394 // VSHRN : Vector Shift Right and Narrow
1395 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1396 v8i8, v8i16, NEONvshrn>;
1397 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1398 v4i16, v4i32, NEONvshrn>;
1399 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1400 v2i32, v2i64, NEONvshrn>;
1402 // VRSHL : Vector Rounding Shift
1403 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1404 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1405 // VRSHR : Vector Rounding Shift Right
1406 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1407 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1409 // VRSHRN : Vector Rounding Shift Right and Narrow
1410 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1411 v8i8, v8i16, NEONvrshrn>;
1412 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1413 v4i16, v4i32, NEONvrshrn>;
1414 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1415 v2i32, v2i64, NEONvrshrn>;
1417 // VQSHL : Vector Saturating Shift
1418 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1419 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1420 // VQSHL : Vector Saturating Shift Left (Immediate)
1421 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1422 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1423 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1424 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1426 // VQSHRN : Vector Saturating Shift Right and Narrow
1427 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1428 v8i8, v8i16, NEONvqshrns>;
1429 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1430 v4i16, v4i32, NEONvqshrns>;
1431 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1432 v2i32, v2i64, NEONvqshrns>;
1433 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1434 v8i8, v8i16, NEONvqshrnu>;
1435 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1436 v4i16, v4i32, NEONvqshrnu>;
1437 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1438 v2i32, v2i64, NEONvqshrnu>;
1440 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1441 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1442 v8i8, v8i16, NEONvqshrnsu>;
1443 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1444 v4i16, v4i32, NEONvqshrnsu>;
1445 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1446 v2i32, v2i64, NEONvqshrnsu>;
1448 // VQRSHL : Vector Saturating Rounding Shift
1449 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1450 int_arm_neon_vqrshifts, 0>;
1451 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1452 int_arm_neon_vqrshiftu, 0>;
1454 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1455 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1456 v8i8, v8i16, NEONvqrshrns>;
1457 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1458 v4i16, v4i32, NEONvqrshrns>;
1459 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1460 v2i32, v2i64, NEONvqrshrns>;
1461 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1462 v8i8, v8i16, NEONvqrshrnu>;
1463 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1464 v4i16, v4i32, NEONvqrshrnu>;
1465 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1466 v2i32, v2i64, NEONvqrshrnu>;
1468 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1469 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1470 v8i8, v8i16, NEONvqrshrnsu>;
1471 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1472 v4i16, v4i32, NEONvqrshrnsu>;
1473 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1474 v2i32, v2i64, NEONvqrshrnsu>;
1476 // VSRA : Vector Shift Right and Accumulate
1477 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1478 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1479 // VRSRA : Vector Rounding Shift Right and Accumulate
1480 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1481 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1483 // VSLI : Vector Shift Left and Insert
1484 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1485 // VSRI : Vector Shift Right and Insert
1486 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1488 // Vector Absolute and Saturating Absolute.
1490 // VABS : Vector Absolute Value
1491 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1493 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1494 v2f32, v2f32, int_arm_neon_vabs>;
1495 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1496 v4f32, v4f32, int_arm_neon_vabs>;
1498 // VQABS : Vector Saturating Absolute Value
1499 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1500 int_arm_neon_vqabs>;
1504 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1505 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1507 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1508 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1510 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1511 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1512 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1513 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1515 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1516 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1518 // VNEG : Vector Negate
1519 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1520 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1521 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1522 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1523 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1524 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1526 // VNEG : Vector Negate (floating-point)
1527 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1528 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1529 "vneg.f32\t$dst, $src", "",
1530 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1531 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1532 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1533 "vneg.f32\t$dst, $src", "",
1534 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1536 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1537 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1538 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1539 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1540 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1541 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1543 // VQNEG : Vector Saturating Negate
1544 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1545 int_arm_neon_vqneg>;
1547 // Vector Bit Counting Operations.
1549 // VCLS : Vector Count Leading Sign Bits
1550 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1552 // VCLZ : Vector Count Leading Zeros
1553 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1555 // VCNT : Vector Count One Bits
1556 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1557 v8i8, v8i8, int_arm_neon_vcnt>;
1558 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1559 v16i8, v16i8, int_arm_neon_vcnt>;
1561 // Vector Move Operations.
1563 // VMOV : Vector Move (Register)
1565 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1566 NoItinerary, "vmov\t$dst, $src", "", []>;
1567 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1568 NoItinerary, "vmov\t$dst, $src", "", []>;
1570 // VMOV : Vector Move (Immediate)
1572 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1573 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1574 return ARM::getVMOVImm(N, 1, *CurDAG);
1576 def vmovImm8 : PatLeaf<(build_vector), [{
1577 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1580 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1581 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1582 return ARM::getVMOVImm(N, 2, *CurDAG);
1584 def vmovImm16 : PatLeaf<(build_vector), [{
1585 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1586 }], VMOV_get_imm16>;
1588 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1589 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1590 return ARM::getVMOVImm(N, 4, *CurDAG);
1592 def vmovImm32 : PatLeaf<(build_vector), [{
1593 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1594 }], VMOV_get_imm32>;
1596 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1597 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1598 return ARM::getVMOVImm(N, 8, *CurDAG);
1600 def vmovImm64 : PatLeaf<(build_vector), [{
1601 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1602 }], VMOV_get_imm64>;
1604 // Note: Some of the cmode bits in the following VMOV instructions need to
1605 // be encoded based on the immed values.
1607 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1608 (ins i8imm:$SIMM), NoItinerary,
1609 "vmov.i8\t$dst, $SIMM", "",
1610 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1611 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1612 (ins i8imm:$SIMM), NoItinerary,
1613 "vmov.i8\t$dst, $SIMM", "",
1614 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1616 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1617 (ins i16imm:$SIMM), NoItinerary,
1618 "vmov.i16\t$dst, $SIMM", "",
1619 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1620 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1621 (ins i16imm:$SIMM), NoItinerary,
1622 "vmov.i16\t$dst, $SIMM", "",
1623 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1625 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1626 (ins i32imm:$SIMM), NoItinerary,
1627 "vmov.i32\t$dst, $SIMM", "",
1628 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1629 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1630 (ins i32imm:$SIMM), NoItinerary,
1631 "vmov.i32\t$dst, $SIMM", "",
1632 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1634 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1635 (ins i64imm:$SIMM), NoItinerary,
1636 "vmov.i64\t$dst, $SIMM", "",
1637 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1638 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1639 (ins i64imm:$SIMM), NoItinerary,
1640 "vmov.i64\t$dst, $SIMM", "",
1641 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1643 // VMOV : Vector Get Lane (move scalar to ARM core register)
1645 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1646 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1647 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1648 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1650 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1651 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1652 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1653 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1655 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1656 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1657 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1658 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1660 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1661 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1662 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1663 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1665 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1666 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1667 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1668 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1670 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1671 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1672 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1673 (DSubReg_i8_reg imm:$lane))),
1674 (SubReg_i8_lane imm:$lane))>;
1675 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1676 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1677 (DSubReg_i16_reg imm:$lane))),
1678 (SubReg_i16_lane imm:$lane))>;
1679 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1680 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1681 (DSubReg_i8_reg imm:$lane))),
1682 (SubReg_i8_lane imm:$lane))>;
1683 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1684 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1685 (DSubReg_i16_reg imm:$lane))),
1686 (SubReg_i16_lane imm:$lane))>;
1687 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1688 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1689 (DSubReg_i32_reg imm:$lane))),
1690 (SubReg_i32_lane imm:$lane))>;
1691 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1692 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1693 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1694 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1695 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1696 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1699 // VMOV : Vector Set Lane (move ARM core register to scalar)
1701 let Constraints = "$src1 = $dst" in {
1702 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1703 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1704 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1705 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1706 GPR:$src2, imm:$lane))]>;
1707 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1708 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1709 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1710 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1711 GPR:$src2, imm:$lane))]>;
1712 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1713 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1714 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1715 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1716 GPR:$src2, imm:$lane))]>;
1718 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1719 (v16i8 (INSERT_SUBREG QPR:$src1,
1720 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1721 (DSubReg_i8_reg imm:$lane))),
1722 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1723 (DSubReg_i8_reg imm:$lane)))>;
1724 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1725 (v8i16 (INSERT_SUBREG QPR:$src1,
1726 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1727 (DSubReg_i16_reg imm:$lane))),
1728 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1729 (DSubReg_i16_reg imm:$lane)))>;
1730 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1731 (v4i32 (INSERT_SUBREG QPR:$src1,
1732 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1733 (DSubReg_i32_reg imm:$lane))),
1734 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1735 (DSubReg_i32_reg imm:$lane)))>;
1737 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1738 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1740 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1741 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1742 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1743 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1745 // VDUP : Vector Duplicate (from ARM core register to all elements)
1747 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1748 (vector_shuffle node:$lhs, node:$rhs), [{
1749 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1750 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1753 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1754 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1755 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1756 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1757 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1758 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1759 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1760 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1762 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1763 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1764 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1765 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1766 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1767 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1769 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1770 NoItinerary, "vdup", ".32\t$dst, $src",
1771 [(set DPR:$dst, (v2f32 (splat_lo
1773 (f32 (bitconvert GPR:$src))),
1775 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1776 NoItinerary, "vdup", ".32\t$dst, $src",
1777 [(set QPR:$dst, (v4f32 (splat_lo
1779 (f32 (bitconvert GPR:$src))),
1782 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1784 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1786 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1789 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1790 (vector_shuffle node:$lhs, node:$rhs), [{
1791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1792 return SVOp->isSplat();
1793 }], SHUFFLE_get_splat_lane>;
1795 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1796 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1797 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1798 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1799 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1801 // vector_shuffle requires that the source and destination types match, so
1802 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1803 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1804 ValueType ResTy, ValueType OpTy>
1805 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1806 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1807 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1808 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1810 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1811 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1812 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1813 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1814 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1815 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1816 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1817 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1819 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1820 (outs DPR:$dst), (ins SPR:$src),
1821 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1822 [(set DPR:$dst, (v2f32 (splat_lo
1823 (scalar_to_vector SPR:$src),
1826 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1827 (outs QPR:$dst), (ins SPR:$src),
1828 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1829 [(set QPR:$dst, (v4f32 (splat_lo
1830 (scalar_to_vector SPR:$src),
1833 // VMOVN : Vector Narrowing Move
1834 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1835 int_arm_neon_vmovn>;
1836 // VQMOVN : Vector Saturating Narrowing Move
1837 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1838 int_arm_neon_vqmovns>;
1839 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1840 int_arm_neon_vqmovnu>;
1841 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1842 int_arm_neon_vqmovnsu>;
1843 // VMOVL : Vector Lengthening Move
1844 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1845 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1847 // Vector Conversions.
1849 // VCVT : Vector Convert Between Floating-Point and Integers
1850 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1851 v2i32, v2f32, fp_to_sint>;
1852 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1853 v2i32, v2f32, fp_to_uint>;
1854 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1855 v2f32, v2i32, sint_to_fp>;
1856 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1857 v2f32, v2i32, uint_to_fp>;
1859 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1860 v4i32, v4f32, fp_to_sint>;
1861 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1862 v4i32, v4f32, fp_to_uint>;
1863 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1864 v4f32, v4i32, sint_to_fp>;
1865 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1866 v4f32, v4i32, uint_to_fp>;
1868 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1869 // Note: Some of the opcode bits in the following VCVT instructions need to
1870 // be encoded based on the immed values.
1871 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1872 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1873 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1874 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1875 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1876 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1877 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1878 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1880 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1881 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1882 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1883 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1884 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1885 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1886 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1887 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1891 // VREV64 : Vector Reverse elements within 64-bit doublewords
1893 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1894 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1895 (ins DPR:$src), NoItinerary,
1896 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1897 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1898 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1899 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1900 (ins QPR:$src), NoItinerary,
1901 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1902 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1904 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1905 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1906 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1907 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1909 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1910 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1911 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1912 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1914 // VREV32 : Vector Reverse elements within 32-bit words
1916 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1917 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1918 (ins DPR:$src), NoItinerary,
1919 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1920 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
1921 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1922 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1923 (ins QPR:$src), NoItinerary,
1924 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1925 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
1927 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1928 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1930 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1931 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1933 // VREV16 : Vector Reverse elements within 16-bit halfwords
1935 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1936 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1937 (ins DPR:$src), NoItinerary,
1938 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1939 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
1940 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1941 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1942 (ins QPR:$src), NoItinerary,
1943 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1944 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
1946 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1947 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1949 // VTRN : Vector Transpose
1951 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1952 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1953 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1955 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1956 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1957 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1959 // VUZP : Vector Unzip (Deinterleave)
1961 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1962 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1963 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1965 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1966 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1967 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
1969 // VZIP : Vector Zip (Interleave)
1971 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
1972 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
1973 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
1975 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
1976 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
1977 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
1979 // Vector Table Lookup and Table Extension.
1981 // VTBL : Vector Table Lookup
1983 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
1984 (ins DPR:$tbl1, DPR:$src), NoItinerary,
1985 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
1986 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
1988 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
1989 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
1990 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
1991 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
1992 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
1994 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
1995 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
1996 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
1997 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
1998 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2000 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2001 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2002 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2003 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2004 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2006 // VTBX : Vector Table Extension
2008 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2009 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2010 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2011 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2012 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2014 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2015 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2016 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2017 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2018 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2020 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2021 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2022 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2023 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2024 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2026 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2027 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2028 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2029 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2030 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2032 //===----------------------------------------------------------------------===//
2033 // NEON instructions for single-precision FP math
2034 //===----------------------------------------------------------------------===//
2036 // These need separate instructions because they must use DPR_VFP2 register
2037 // class which have SPR sub-registers.
2039 // Vector Add Operations used for single-precision FP
2040 let neverHasSideEffects = 1 in
2041 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2042 def : N3VDsPat<fadd, VADDfd_sfp>;
2044 // Vector Sub Operations used for single-precision FP
2045 let neverHasSideEffects = 1 in
2046 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2047 def : N3VDsPat<fsub, VSUBfd_sfp>;
2049 // Vector Multiply Operations used for single-precision FP
2050 let neverHasSideEffects = 1 in
2051 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2052 def : N3VDsPat<fmul, VMULfd_sfp>;
2054 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2055 let neverHasSideEffects = 1 in
2056 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2057 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2059 let neverHasSideEffects = 1 in
2060 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2061 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2063 // Vector Absolute used for single-precision FP
2064 let neverHasSideEffects = 1 in
2065 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2066 v2f32, v2f32, int_arm_neon_vabs>;
2067 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2069 // Vector Negate used for single-precision FP
2070 let neverHasSideEffects = 1 in
2071 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2072 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2073 "vneg.f32\t$dst, $src", "", []>;
2074 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2076 // Vector Convert between single-precision FP and integer
2077 let neverHasSideEffects = 1 in
2078 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2079 v2i32, v2f32, fp_to_sint>;
2080 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2082 let neverHasSideEffects = 1 in
2083 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2084 v2i32, v2f32, fp_to_uint>;
2085 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2087 let neverHasSideEffects = 1 in
2088 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2089 v2f32, v2i32, sint_to_fp>;
2090 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2092 let neverHasSideEffects = 1 in
2093 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2094 v2f32, v2i32, uint_to_fp>;
2095 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2097 //===----------------------------------------------------------------------===//
2098 // Non-Instruction Patterns
2099 //===----------------------------------------------------------------------===//
2102 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2103 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2104 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2105 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2106 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2107 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2108 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2109 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2110 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2111 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2112 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2113 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2114 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2115 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2116 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2117 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2118 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2119 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2120 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2121 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2122 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2123 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2124 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2125 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2126 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2127 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2128 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2129 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2130 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2131 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2133 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2134 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2135 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2136 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2137 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2138 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2139 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2140 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2141 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2142 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2143 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2144 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2145 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2146 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2147 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2148 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2149 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2150 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2151 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2152 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2153 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2154 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2155 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2156 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2157 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2158 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2159 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2160 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2161 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2162 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;