1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
98 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
99 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
101 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
102 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
103 unsigned EltBits = 0;
104 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
105 return (EltBits == 32 && EltVal == 0);
108 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
109 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
110 unsigned EltBits = 0;
111 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
112 return (EltBits == 8 && EltVal == 0xff);
115 //===----------------------------------------------------------------------===//
116 // NEON operand definitions
117 //===----------------------------------------------------------------------===//
119 def nModImm : Operand<i32> {
120 let PrintMethod = "printNEONModImmOperand";
123 //===----------------------------------------------------------------------===//
124 // NEON load / store instructions
125 //===----------------------------------------------------------------------===//
127 let mayLoad = 1, neverHasSideEffects = 1 in {
128 // Use vldmia to load a Q register as a D register pair.
129 // This is equivalent to VLDMD except that it has a Q register operand
130 // instead of a pair of D registers.
132 : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
133 IndexModeNone, IIC_fpLoadm,
134 "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
136 // Use vld1 to load a Q register as a D register pair.
137 // This alternative to VLDMQ allows an alignment to be specified.
138 // This is equivalent to VLD1q64 except that it has a Q register operand.
140 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
141 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
142 } // mayLoad = 1, neverHasSideEffects = 1
144 let mayStore = 1, neverHasSideEffects = 1 in {
145 // Use vstmia to store a Q register as a D register pair.
146 // This is equivalent to VSTMD except that it has a Q register operand
147 // instead of a pair of D registers.
149 : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
150 IndexModeNone, IIC_fpStorem,
151 "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
153 // Use vst1 to store a Q register as a D register pair.
154 // This alternative to VSTMQ allows an alignment to be specified.
155 // This is equivalent to VST1q64 except that it has a Q register operand.
157 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
158 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
159 } // mayStore = 1, neverHasSideEffects = 1
161 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
163 // VLD1 : Vector Load (multiple single elements)
164 class VLD1D<bits<4> op7_4, string Dt>
165 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
166 (ins addrmode6:$addr), IIC_VLD1,
167 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
168 class VLD1Q<bits<4> op7_4, string Dt>
169 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
170 (ins addrmode6:$addr), IIC_VLD1,
171 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
173 def VLD1d8 : VLD1D<0b0000, "8">;
174 def VLD1d16 : VLD1D<0b0100, "16">;
175 def VLD1d32 : VLD1D<0b1000, "32">;
176 def VLD1d64 : VLD1D<0b1100, "64">;
178 def VLD1q8 : VLD1Q<0b0000, "8">;
179 def VLD1q16 : VLD1Q<0b0100, "16">;
180 def VLD1q32 : VLD1Q<0b1000, "32">;
181 def VLD1q64 : VLD1Q<0b1100, "64">;
183 // ...with address register writeback:
184 class VLD1DWB<bits<4> op7_4, string Dt>
185 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
186 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
187 "vld1", Dt, "\\{$dst\\}, $addr$offset",
188 "$addr.addr = $wb", []>;
189 class VLD1QWB<bits<4> op7_4, string Dt>
190 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
191 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
192 "vld1", Dt, "${dst:dregpair}, $addr$offset",
193 "$addr.addr = $wb", []>;
195 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
196 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
197 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
198 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
200 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
201 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
202 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
203 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
205 // ...with 3 registers (some of these are only for the disassembler):
206 class VLD1D3<bits<4> op7_4, string Dt>
207 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
208 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
209 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
210 class VLD1D3WB<bits<4> op7_4, string Dt>
211 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
212 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
213 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
215 def VLD1d8T : VLD1D3<0b0000, "8">;
216 def VLD1d16T : VLD1D3<0b0100, "16">;
217 def VLD1d32T : VLD1D3<0b1000, "32">;
218 def VLD1d64T : VLD1D3<0b1100, "64">;
220 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
221 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
222 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
223 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
225 // ...with 4 registers (some of these are only for the disassembler):
226 class VLD1D4<bits<4> op7_4, string Dt>
227 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
228 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
229 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
230 class VLD1D4WB<bits<4> op7_4, string Dt>
231 : NLdSt<0,0b10,0b0010,op7_4,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
233 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
234 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
237 def VLD1d8Q : VLD1D4<0b0000, "8">;
238 def VLD1d16Q : VLD1D4<0b0100, "16">;
239 def VLD1d32Q : VLD1D4<0b1000, "32">;
240 def VLD1d64Q : VLD1D4<0b1100, "64">;
242 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
243 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
244 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
245 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
247 // VLD2 : Vector Load (multiple 2-element structures)
248 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
249 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
250 (ins addrmode6:$addr), IIC_VLD2,
251 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
252 class VLD2Q<bits<4> op7_4, string Dt>
253 : NLdSt<0, 0b10, 0b0011, op7_4,
254 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
255 (ins addrmode6:$addr), IIC_VLD2,
256 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
258 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
259 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
260 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
262 def VLD2q8 : VLD2Q<0b0000, "8">;
263 def VLD2q16 : VLD2Q<0b0100, "16">;
264 def VLD2q32 : VLD2Q<0b1000, "32">;
266 // ...with address register writeback:
267 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
268 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
269 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
270 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
271 "$addr.addr = $wb", []>;
272 class VLD2QWB<bits<4> op7_4, string Dt>
273 : NLdSt<0, 0b10, 0b0011, op7_4,
274 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
275 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
276 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
277 "$addr.addr = $wb", []>;
279 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
280 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
281 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
283 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
284 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
285 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
287 // ...with double-spaced registers (for disassembly only):
288 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
289 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
290 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
291 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
292 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
293 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
295 // VLD3 : Vector Load (multiple 3-element structures)
296 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
297 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
298 (ins addrmode6:$addr), IIC_VLD3,
299 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
301 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
302 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
303 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
305 // ...with address register writeback:
306 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
307 : NLdSt<0, 0b10, op11_8, op7_4,
308 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
309 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
310 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
311 "$addr.addr = $wb", []>;
313 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
314 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
315 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
317 // ...with double-spaced registers (non-updating versions for disassembly only):
318 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
319 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
320 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
321 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
322 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
323 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
325 // ...alternate versions to be allocated odd register numbers:
326 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
327 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
328 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
330 // VLD4 : Vector Load (multiple 4-element structures)
331 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
332 : NLdSt<0, 0b10, op11_8, op7_4,
333 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
334 (ins addrmode6:$addr), IIC_VLD4,
335 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
337 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
338 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
339 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
341 // ...with address register writeback:
342 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
343 : NLdSt<0, 0b10, op11_8, op7_4,
344 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
345 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
346 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
347 "$addr.addr = $wb", []>;
349 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
350 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
351 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
353 // ...with double-spaced registers (non-updating versions for disassembly only):
354 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
355 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
356 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
357 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
358 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
359 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
361 // ...alternate versions to be allocated odd register numbers:
362 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
363 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
364 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
366 // VLD1LN : Vector Load (single element to one lane)
367 // FIXME: Not yet implemented.
369 // VLD2LN : Vector Load (single 2-element structure to one lane)
370 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
371 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
372 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
373 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
374 "$src1 = $dst1, $src2 = $dst2", []>;
376 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
377 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
378 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
380 // ...with double-spaced registers:
381 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
382 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
384 // ...alternate versions to be allocated odd register numbers:
385 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
386 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
388 // ...with address register writeback:
389 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
390 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
391 (ins addrmode6:$addr, am6offset:$offset,
392 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
393 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
394 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
396 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
397 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
398 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
400 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
401 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
403 // VLD3LN : Vector Load (single 3-element structure to one lane)
404 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
405 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
406 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
407 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
408 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
409 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
411 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
412 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
413 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
415 // ...with double-spaced registers:
416 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
417 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
419 // ...alternate versions to be allocated odd register numbers:
420 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
421 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
423 // ...with address register writeback:
424 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
425 : NLdSt<1, 0b10, op11_8, op7_4,
426 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
427 (ins addrmode6:$addr, am6offset:$offset,
428 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
429 IIC_VLD3, "vld3", Dt,
430 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
431 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
434 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
435 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
436 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
438 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
439 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
441 // VLD4LN : Vector Load (single 4-element structure to one lane)
442 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
443 : NLdSt<1, 0b10, op11_8, op7_4,
444 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
445 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
446 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
447 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
448 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
450 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
451 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
452 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
454 // ...with double-spaced registers:
455 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
456 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
458 // ...alternate versions to be allocated odd register numbers:
459 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
460 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
462 // ...with address register writeback:
463 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
464 : NLdSt<1, 0b10, op11_8, op7_4,
465 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
466 (ins addrmode6:$addr, am6offset:$offset,
467 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
468 IIC_VLD4, "vld4", Dt,
469 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
470 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
473 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
474 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
475 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
477 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
478 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
480 // VLD1DUP : Vector Load (single element to all lanes)
481 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
482 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
483 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
484 // FIXME: Not yet implemented.
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
489 // VST1 : Vector Store (multiple single elements)
490 class VST1D<bits<4> op7_4, string Dt>
491 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
492 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
493 class VST1Q<bits<4> op7_4, string Dt>
494 : NLdSt<0,0b00,0b1010,op7_4, (outs),
495 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
496 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
498 def VST1d8 : VST1D<0b0000, "8">;
499 def VST1d16 : VST1D<0b0100, "16">;
500 def VST1d32 : VST1D<0b1000, "32">;
501 def VST1d64 : VST1D<0b1100, "64">;
503 def VST1q8 : VST1Q<0b0000, "8">;
504 def VST1q16 : VST1Q<0b0100, "16">;
505 def VST1q32 : VST1Q<0b1000, "32">;
506 def VST1q64 : VST1Q<0b1100, "64">;
508 // ...with address register writeback:
509 class VST1DWB<bits<4> op7_4, string Dt>
510 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
512 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
513 class VST1QWB<bits<4> op7_4, string Dt>
514 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
515 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
516 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
518 def VST1d8_UPD : VST1DWB<0b0000, "8">;
519 def VST1d16_UPD : VST1DWB<0b0100, "16">;
520 def VST1d32_UPD : VST1DWB<0b1000, "32">;
521 def VST1d64_UPD : VST1DWB<0b1100, "64">;
523 def VST1q8_UPD : VST1QWB<0b0000, "8">;
524 def VST1q16_UPD : VST1QWB<0b0100, "16">;
525 def VST1q32_UPD : VST1QWB<0b1000, "32">;
526 def VST1q64_UPD : VST1QWB<0b1100, "64">;
528 // ...with 3 registers (some of these are only for the disassembler):
529 class VST1D3<bits<4> op7_4, string Dt>
530 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
531 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
532 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
533 class VST1D3WB<bits<4> op7_4, string Dt>
534 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
535 (ins addrmode6:$addr, am6offset:$offset,
536 DPR:$src1, DPR:$src2, DPR:$src3),
537 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
538 "$addr.addr = $wb", []>;
540 def VST1d8T : VST1D3<0b0000, "8">;
541 def VST1d16T : VST1D3<0b0100, "16">;
542 def VST1d32T : VST1D3<0b1000, "32">;
543 def VST1d64T : VST1D3<0b1100, "64">;
545 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
546 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
547 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
548 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
550 // ...with 4 registers (some of these are only for the disassembler):
551 class VST1D4<bits<4> op7_4, string Dt>
552 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
553 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
554 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
556 class VST1D4WB<bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
558 (ins addrmode6:$addr, am6offset:$offset,
559 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
560 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
561 "$addr.addr = $wb", []>;
563 def VST1d8Q : VST1D4<0b0000, "8">;
564 def VST1d16Q : VST1D4<0b0100, "16">;
565 def VST1d32Q : VST1D4<0b1000, "32">;
566 def VST1d64Q : VST1D4<0b1100, "64">;
568 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
569 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
570 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
571 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
573 // VST2 : Vector Store (multiple 2-element structures)
574 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
575 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
576 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
577 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
578 class VST2Q<bits<4> op7_4, string Dt>
579 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
580 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
581 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
584 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
585 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
586 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
588 def VST2q8 : VST2Q<0b0000, "8">;
589 def VST2q16 : VST2Q<0b0100, "16">;
590 def VST2q32 : VST2Q<0b1000, "32">;
592 // ...with address register writeback:
593 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
594 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
595 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
596 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
597 "$addr.addr = $wb", []>;
598 class VST2QWB<bits<4> op7_4, string Dt>
599 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
600 (ins addrmode6:$addr, am6offset:$offset,
601 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
602 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
603 "$addr.addr = $wb", []>;
605 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
606 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
607 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
609 def VST2q8_UPD : VST2QWB<0b0000, "8">;
610 def VST2q16_UPD : VST2QWB<0b0100, "16">;
611 def VST2q32_UPD : VST2QWB<0b1000, "32">;
613 // ...with double-spaced registers (for disassembly only):
614 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
615 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
616 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
617 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
618 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
619 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
621 // VST3 : Vector Store (multiple 3-element structures)
622 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
623 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
624 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
625 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
627 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
628 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
629 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
631 // ...with address register writeback:
632 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
633 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
634 (ins addrmode6:$addr, am6offset:$offset,
635 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
636 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
637 "$addr.addr = $wb", []>;
639 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
640 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
641 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
643 // ...with double-spaced registers (non-updating versions for disassembly only):
644 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
645 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
646 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
647 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
648 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
649 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
651 // ...alternate versions to be allocated odd register numbers:
652 def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
653 def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
654 def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
656 // VST4 : Vector Store (multiple 4-element structures)
657 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
658 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
659 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
660 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
663 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
664 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
665 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
667 // ...with address register writeback:
668 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
669 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
670 (ins addrmode6:$addr, am6offset:$offset,
671 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
672 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
673 "$addr.addr = $wb", []>;
675 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
676 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
677 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
679 // ...with double-spaced registers (non-updating versions for disassembly only):
680 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
681 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
682 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
683 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
684 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
685 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
687 // ...alternate versions to be allocated odd register numbers:
688 def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
689 def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
690 def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
692 // VST1LN : Vector Store (single element from one lane)
693 // FIXME: Not yet implemented.
695 // VST2LN : Vector Store (single 2-element structure from one lane)
696 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
697 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
698 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
699 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
702 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
703 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
704 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
706 // ...with double-spaced registers:
707 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
708 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
710 // ...alternate versions to be allocated odd register numbers:
711 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
712 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
714 // ...with address register writeback:
715 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
716 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
717 (ins addrmode6:$addr, am6offset:$offset,
718 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
719 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
720 "$addr.addr = $wb", []>;
722 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
723 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
724 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
726 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
727 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
729 // VST3LN : Vector Store (single 3-element structure from one lane)
730 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
731 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
732 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
733 nohash_imm:$lane), IIC_VST, "vst3", Dt,
734 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
736 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
737 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
738 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
740 // ...with double-spaced registers:
741 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
742 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
744 // ...alternate versions to be allocated odd register numbers:
745 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
746 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
748 // ...with address register writeback:
749 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
750 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
751 (ins addrmode6:$addr, am6offset:$offset,
752 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
754 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
755 "$addr.addr = $wb", []>;
757 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
758 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
759 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
761 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
762 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
764 // VST4LN : Vector Store (single 4-element structure from one lane)
765 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
766 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
767 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
768 nohash_imm:$lane), IIC_VST, "vst4", Dt,
769 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
772 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
773 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
774 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
776 // ...with double-spaced registers:
777 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
778 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
780 // ...alternate versions to be allocated odd register numbers:
781 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
782 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
784 // ...with address register writeback:
785 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
786 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
787 (ins addrmode6:$addr, am6offset:$offset,
788 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
790 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
791 "$addr.addr = $wb", []>;
793 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
794 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
795 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
797 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
798 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
800 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
803 //===----------------------------------------------------------------------===//
804 // NEON pattern fragments
805 //===----------------------------------------------------------------------===//
807 // Extract D sub-registers of Q registers.
808 def DSubReg_i8_reg : SDNodeXForm<imm, [{
809 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
810 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
812 def DSubReg_i16_reg : SDNodeXForm<imm, [{
813 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
814 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
816 def DSubReg_i32_reg : SDNodeXForm<imm, [{
817 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
818 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
820 def DSubReg_f64_reg : SDNodeXForm<imm, [{
821 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
822 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
825 // Extract S sub-registers of Q/D registers.
826 def SSubReg_f32_reg : SDNodeXForm<imm, [{
827 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
828 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
831 // Translate lane numbers from Q registers to D subregs.
832 def SubReg_i8_lane : SDNodeXForm<imm, [{
833 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
835 def SubReg_i16_lane : SDNodeXForm<imm, [{
836 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
838 def SubReg_i32_lane : SDNodeXForm<imm, [{
839 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
842 //===----------------------------------------------------------------------===//
843 // Instruction Classes
844 //===----------------------------------------------------------------------===//
846 // Basic 2-register operations: single-, double- and quad-register.
847 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
848 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
849 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
850 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
851 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
852 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
853 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
854 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
855 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
856 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
857 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
858 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
859 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
860 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
861 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
862 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
863 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
864 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
866 // Basic 2-register intrinsics, both double- and quad-register.
867 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
868 bits<2> op17_16, bits<5> op11_7, bit op4,
869 InstrItinClass itin, string OpcodeStr, string Dt,
870 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
871 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
872 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
873 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
874 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
875 bits<2> op17_16, bits<5> op11_7, bit op4,
876 InstrItinClass itin, string OpcodeStr, string Dt,
877 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
878 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
879 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
880 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
882 // Narrow 2-register intrinsics.
883 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
884 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
885 InstrItinClass itin, string OpcodeStr, string Dt,
886 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
887 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
888 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
889 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
891 // Long 2-register intrinsics (currently only used for VMOVL).
892 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
893 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
894 InstrItinClass itin, string OpcodeStr, string Dt,
895 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
896 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
897 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
898 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
900 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
901 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
902 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
903 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
904 OpcodeStr, Dt, "$dst1, $dst2",
905 "$src1 = $dst1, $src2 = $dst2", []>;
906 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
907 InstrItinClass itin, string OpcodeStr, string Dt>
908 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
909 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
910 "$src1 = $dst1, $src2 = $dst2", []>;
912 // Basic 3-register operations: single-, double- and quad-register.
913 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
914 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
915 SDNode OpNode, bit Commutable>
916 : N3V<op24, op23, op21_20, op11_8, 0, op4,
917 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
918 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
919 let isCommutable = Commutable;
922 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
923 InstrItinClass itin, string OpcodeStr, string Dt,
924 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
925 : N3V<op24, op23, op21_20, op11_8, 0, op4,
926 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
927 OpcodeStr, Dt, "$dst, $src1, $src2", "",
928 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
929 let isCommutable = Commutable;
931 // Same as N3VD but no data type.
932 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
933 InstrItinClass itin, string OpcodeStr,
934 ValueType ResTy, ValueType OpTy,
935 SDNode OpNode, bit Commutable>
936 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
937 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
938 OpcodeStr, "$dst, $src1, $src2", "",
939 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
940 let isCommutable = Commutable;
943 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
944 InstrItinClass itin, string OpcodeStr, string Dt,
945 ValueType Ty, SDNode ShOp>
946 : N3V<0, 1, op21_20, op11_8, 1, 0,
947 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
948 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
950 (Ty (ShOp (Ty DPR:$src1),
951 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
952 let isCommutable = 0;
954 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
955 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
956 : N3V<0, 1, op21_20, op11_8, 1, 0,
957 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
958 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
960 (Ty (ShOp (Ty DPR:$src1),
961 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
962 let isCommutable = 0;
965 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
966 InstrItinClass itin, string OpcodeStr, string Dt,
967 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
968 : N3V<op24, op23, op21_20, op11_8, 1, op4,
969 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
970 OpcodeStr, Dt, "$dst, $src1, $src2", "",
971 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
972 let isCommutable = Commutable;
974 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
975 InstrItinClass itin, string OpcodeStr,
976 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
977 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
978 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
979 OpcodeStr, "$dst, $src1, $src2", "",
980 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
981 let isCommutable = Commutable;
983 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
984 InstrItinClass itin, string OpcodeStr, string Dt,
985 ValueType ResTy, ValueType OpTy, SDNode ShOp>
986 : N3V<1, 1, op21_20, op11_8, 1, 0,
987 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
988 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
989 [(set (ResTy QPR:$dst),
990 (ResTy (ShOp (ResTy QPR:$src1),
991 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
993 let isCommutable = 0;
995 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
996 ValueType ResTy, ValueType OpTy, SDNode ShOp>
997 : N3V<1, 1, op21_20, op11_8, 1, 0,
998 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
999 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1000 [(set (ResTy QPR:$dst),
1001 (ResTy (ShOp (ResTy QPR:$src1),
1002 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1004 let isCommutable = 0;
1007 // Basic 3-register intrinsics, both double- and quad-register.
1008 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1009 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1010 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1011 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1012 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1013 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1014 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1015 let isCommutable = Commutable;
1017 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1018 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1019 : N3V<0, 1, op21_20, op11_8, 1, 0,
1020 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1021 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1022 [(set (Ty DPR:$dst),
1023 (Ty (IntOp (Ty DPR:$src1),
1024 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1026 let isCommutable = 0;
1028 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1029 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1030 : N3V<0, 1, op21_20, op11_8, 1, 0,
1031 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1032 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1033 [(set (Ty DPR:$dst),
1034 (Ty (IntOp (Ty DPR:$src1),
1035 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1036 let isCommutable = 0;
1039 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1040 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1041 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1042 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1043 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1044 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1045 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1046 let isCommutable = Commutable;
1048 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1049 string OpcodeStr, string Dt,
1050 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1051 : N3V<1, 1, op21_20, op11_8, 1, 0,
1052 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1053 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1054 [(set (ResTy QPR:$dst),
1055 (ResTy (IntOp (ResTy QPR:$src1),
1056 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1058 let isCommutable = 0;
1060 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1061 string OpcodeStr, string Dt,
1062 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1063 : N3V<1, 1, op21_20, op11_8, 1, 0,
1064 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1065 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1066 [(set (ResTy QPR:$dst),
1067 (ResTy (IntOp (ResTy QPR:$src1),
1068 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1070 let isCommutable = 0;
1073 // Multiply-Add/Sub operations: single-, double- and quad-register.
1074 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1075 InstrItinClass itin, string OpcodeStr, string Dt,
1076 ValueType Ty, SDNode MulOp, SDNode OpNode>
1077 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1078 (outs DPR_VFP2:$dst),
1079 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1080 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1082 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1083 InstrItinClass itin, string OpcodeStr, string Dt,
1084 ValueType Ty, SDNode MulOp, SDNode OpNode>
1085 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1086 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1087 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1088 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1089 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1090 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1091 string OpcodeStr, string Dt,
1092 ValueType Ty, SDNode MulOp, SDNode ShOp>
1093 : N3V<0, 1, op21_20, op11_8, 1, 0,
1095 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1097 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1098 [(set (Ty DPR:$dst),
1099 (Ty (ShOp (Ty DPR:$src1),
1100 (Ty (MulOp DPR:$src2,
1101 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1103 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1104 string OpcodeStr, string Dt,
1105 ValueType Ty, SDNode MulOp, SDNode ShOp>
1106 : N3V<0, 1, op21_20, op11_8, 1, 0,
1108 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1110 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1111 [(set (Ty DPR:$dst),
1112 (Ty (ShOp (Ty DPR:$src1),
1113 (Ty (MulOp DPR:$src2,
1114 (Ty (NEONvduplane (Ty DPR_8:$src3),
1117 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1118 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1119 SDNode MulOp, SDNode OpNode>
1120 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1121 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1122 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1123 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1124 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1125 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1126 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1127 SDNode MulOp, SDNode ShOp>
1128 : N3V<1, 1, op21_20, op11_8, 1, 0,
1130 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1132 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1133 [(set (ResTy QPR:$dst),
1134 (ResTy (ShOp (ResTy QPR:$src1),
1135 (ResTy (MulOp QPR:$src2,
1136 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1138 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1139 string OpcodeStr, string Dt,
1140 ValueType ResTy, ValueType OpTy,
1141 SDNode MulOp, SDNode ShOp>
1142 : N3V<1, 1, op21_20, op11_8, 1, 0,
1144 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1146 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1147 [(set (ResTy QPR:$dst),
1148 (ResTy (ShOp (ResTy QPR:$src1),
1149 (ResTy (MulOp QPR:$src2,
1150 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1153 // Neon 3-argument intrinsics, both double- and quad-register.
1154 // The destination register is also used as the first source operand register.
1155 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1156 InstrItinClass itin, string OpcodeStr, string Dt,
1157 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1158 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1159 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1160 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1161 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1162 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1163 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1164 InstrItinClass itin, string OpcodeStr, string Dt,
1165 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1166 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1167 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1168 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1169 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1170 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1172 // Neon Long 3-argument intrinsic. The destination register is
1173 // a quad-register and is also used as the first source operand register.
1174 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1175 InstrItinClass itin, string OpcodeStr, string Dt,
1176 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1177 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1178 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1179 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1181 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1182 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1183 string OpcodeStr, string Dt,
1184 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1185 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1187 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1189 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1190 [(set (ResTy QPR:$dst),
1191 (ResTy (IntOp (ResTy QPR:$src1),
1193 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1195 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1196 InstrItinClass itin, string OpcodeStr, string Dt,
1197 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1198 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1200 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1202 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1203 [(set (ResTy QPR:$dst),
1204 (ResTy (IntOp (ResTy QPR:$src1),
1206 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1209 // Narrowing 3-register intrinsics.
1210 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1211 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1212 Intrinsic IntOp, bit Commutable>
1213 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1214 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1215 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1216 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1217 let isCommutable = Commutable;
1220 // Long 3-register intrinsics.
1221 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1222 InstrItinClass itin, string OpcodeStr, string Dt,
1223 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1224 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1225 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1226 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1227 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1228 let isCommutable = Commutable;
1230 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1231 string OpcodeStr, string Dt,
1232 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1233 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1234 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1235 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1236 [(set (ResTy QPR:$dst),
1237 (ResTy (IntOp (OpTy DPR:$src1),
1238 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1240 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1241 InstrItinClass itin, string OpcodeStr, string Dt,
1242 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1243 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1244 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1245 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1246 [(set (ResTy QPR:$dst),
1247 (ResTy (IntOp (OpTy DPR:$src1),
1248 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1251 // Wide 3-register intrinsics.
1252 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1253 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1254 Intrinsic IntOp, bit Commutable>
1255 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1256 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1257 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1258 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1259 let isCommutable = Commutable;
1262 // Pairwise long 2-register intrinsics, both double- and quad-register.
1263 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1264 bits<2> op17_16, bits<5> op11_7, bit op4,
1265 string OpcodeStr, string Dt,
1266 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1267 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1268 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1269 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1270 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1271 bits<2> op17_16, bits<5> op11_7, bit op4,
1272 string OpcodeStr, string Dt,
1273 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1274 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1275 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1276 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1278 // Pairwise long 2-register accumulate intrinsics,
1279 // both double- and quad-register.
1280 // The destination register is also used as the first source operand register.
1281 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1282 bits<2> op17_16, bits<5> op11_7, bit op4,
1283 string OpcodeStr, string Dt,
1284 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1285 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1286 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1287 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1288 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1289 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1290 bits<2> op17_16, bits<5> op11_7, bit op4,
1291 string OpcodeStr, string Dt,
1292 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1293 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1294 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1295 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1296 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1298 // Shift by immediate,
1299 // both double- and quad-register.
1300 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1301 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1302 ValueType Ty, SDNode OpNode>
1303 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1304 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1305 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1306 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1307 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1308 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1309 ValueType Ty, SDNode OpNode>
1310 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1311 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1312 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1313 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1315 // Long shift by immediate.
1316 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1317 string OpcodeStr, string Dt,
1318 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1319 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1320 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1321 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1322 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1323 (i32 imm:$SIMM))))]>;
1325 // Narrow shift by immediate.
1326 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1327 InstrItinClass itin, string OpcodeStr, string Dt,
1328 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1329 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1330 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1331 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1332 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1333 (i32 imm:$SIMM))))]>;
1335 // Shift right by immediate and accumulate,
1336 // both double- and quad-register.
1337 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1338 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1339 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1340 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1341 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1342 [(set DPR:$dst, (Ty (add DPR:$src1,
1343 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1344 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1345 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1346 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1347 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1348 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1349 [(set QPR:$dst, (Ty (add QPR:$src1,
1350 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1352 // Shift by immediate and insert,
1353 // both double- and quad-register.
1354 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1355 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1356 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1357 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1358 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1359 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1360 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1361 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1362 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1363 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1364 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1365 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1367 // Convert, with fractional bits immediate,
1368 // both double- and quad-register.
1369 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1370 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1372 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1373 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1374 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1375 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1376 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1377 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1379 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1380 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1381 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1382 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1384 //===----------------------------------------------------------------------===//
1386 //===----------------------------------------------------------------------===//
1388 // Abbreviations used in multiclass suffixes:
1389 // Q = quarter int (8 bit) elements
1390 // H = half int (16 bit) elements
1391 // S = single int (32 bit) elements
1392 // D = double int (64 bit) elements
1394 // Neon 2-register vector operations -- for disassembly only.
1396 // First with only element sizes of 8, 16 and 32 bits:
1397 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1398 bits<5> op11_7, bit op4, string opc, string Dt,
1400 // 64-bit vector types.
1401 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1402 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1403 opc, !strconcat(Dt, "8"), asm, "", []>;
1404 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1405 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1406 opc, !strconcat(Dt, "16"), asm, "", []>;
1407 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1408 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1409 opc, !strconcat(Dt, "32"), asm, "", []>;
1410 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1411 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1412 opc, "f32", asm, "", []> {
1413 let Inst{10} = 1; // overwrite F = 1
1416 // 128-bit vector types.
1417 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1418 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1419 opc, !strconcat(Dt, "8"), asm, "", []>;
1420 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1421 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1422 opc, !strconcat(Dt, "16"), asm, "", []>;
1423 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1424 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1425 opc, !strconcat(Dt, "32"), asm, "", []>;
1426 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1427 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1428 opc, "f32", asm, "", []> {
1429 let Inst{10} = 1; // overwrite F = 1
1433 // Neon 3-register vector operations.
1435 // First with only element sizes of 8, 16 and 32 bits:
1436 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1437 InstrItinClass itinD16, InstrItinClass itinD32,
1438 InstrItinClass itinQ16, InstrItinClass itinQ32,
1439 string OpcodeStr, string Dt,
1440 SDNode OpNode, bit Commutable = 0> {
1441 // 64-bit vector types.
1442 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1443 OpcodeStr, !strconcat(Dt, "8"),
1444 v8i8, v8i8, OpNode, Commutable>;
1445 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1446 OpcodeStr, !strconcat(Dt, "16"),
1447 v4i16, v4i16, OpNode, Commutable>;
1448 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1449 OpcodeStr, !strconcat(Dt, "32"),
1450 v2i32, v2i32, OpNode, Commutable>;
1452 // 128-bit vector types.
1453 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1454 OpcodeStr, !strconcat(Dt, "8"),
1455 v16i8, v16i8, OpNode, Commutable>;
1456 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1457 OpcodeStr, !strconcat(Dt, "16"),
1458 v8i16, v8i16, OpNode, Commutable>;
1459 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1460 OpcodeStr, !strconcat(Dt, "32"),
1461 v4i32, v4i32, OpNode, Commutable>;
1464 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1465 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1467 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1469 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1470 v8i16, v4i16, ShOp>;
1471 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1472 v4i32, v2i32, ShOp>;
1475 // ....then also with element size 64 bits:
1476 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1477 InstrItinClass itinD, InstrItinClass itinQ,
1478 string OpcodeStr, string Dt,
1479 SDNode OpNode, bit Commutable = 0>
1480 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1481 OpcodeStr, Dt, OpNode, Commutable> {
1482 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1483 OpcodeStr, !strconcat(Dt, "64"),
1484 v1i64, v1i64, OpNode, Commutable>;
1485 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1486 OpcodeStr, !strconcat(Dt, "64"),
1487 v2i64, v2i64, OpNode, Commutable>;
1491 // Neon Narrowing 2-register vector intrinsics,
1492 // source operand element sizes of 16, 32 and 64 bits:
1493 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1494 bits<5> op11_7, bit op6, bit op4,
1495 InstrItinClass itin, string OpcodeStr, string Dt,
1497 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1498 itin, OpcodeStr, !strconcat(Dt, "16"),
1499 v8i8, v8i16, IntOp>;
1500 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1501 itin, OpcodeStr, !strconcat(Dt, "32"),
1502 v4i16, v4i32, IntOp>;
1503 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1504 itin, OpcodeStr, !strconcat(Dt, "64"),
1505 v2i32, v2i64, IntOp>;
1509 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1510 // source operand element sizes of 16, 32 and 64 bits:
1511 multiclass N2VLInt_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1512 string OpcodeStr, string Dt, Intrinsic IntOp> {
1513 def v8i16 : N2VLInt<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1514 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1515 def v4i32 : N2VLInt<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1516 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1517 def v2i64 : N2VLInt<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1518 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1522 // Neon 3-register vector intrinsics.
1524 // First with only element sizes of 16 and 32 bits:
1525 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1526 InstrItinClass itinD16, InstrItinClass itinD32,
1527 InstrItinClass itinQ16, InstrItinClass itinQ32,
1528 string OpcodeStr, string Dt,
1529 Intrinsic IntOp, bit Commutable = 0> {
1530 // 64-bit vector types.
1531 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1532 OpcodeStr, !strconcat(Dt, "16"),
1533 v4i16, v4i16, IntOp, Commutable>;
1534 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1535 OpcodeStr, !strconcat(Dt, "32"),
1536 v2i32, v2i32, IntOp, Commutable>;
1538 // 128-bit vector types.
1539 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1540 OpcodeStr, !strconcat(Dt, "16"),
1541 v8i16, v8i16, IntOp, Commutable>;
1542 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1543 OpcodeStr, !strconcat(Dt, "32"),
1544 v4i32, v4i32, IntOp, Commutable>;
1547 multiclass N3VIntSL_HS<bits<4> op11_8,
1548 InstrItinClass itinD16, InstrItinClass itinD32,
1549 InstrItinClass itinQ16, InstrItinClass itinQ32,
1550 string OpcodeStr, string Dt, Intrinsic IntOp> {
1551 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1552 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1553 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1554 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1555 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1556 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1557 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1558 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1561 // ....then also with element size of 8 bits:
1562 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1563 InstrItinClass itinD16, InstrItinClass itinD32,
1564 InstrItinClass itinQ16, InstrItinClass itinQ32,
1565 string OpcodeStr, string Dt,
1566 Intrinsic IntOp, bit Commutable = 0>
1567 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1568 OpcodeStr, Dt, IntOp, Commutable> {
1569 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1570 OpcodeStr, !strconcat(Dt, "8"),
1571 v8i8, v8i8, IntOp, Commutable>;
1572 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1573 OpcodeStr, !strconcat(Dt, "8"),
1574 v16i8, v16i8, IntOp, Commutable>;
1577 // ....then also with element size of 64 bits:
1578 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1579 InstrItinClass itinD16, InstrItinClass itinD32,
1580 InstrItinClass itinQ16, InstrItinClass itinQ32,
1581 string OpcodeStr, string Dt,
1582 Intrinsic IntOp, bit Commutable = 0>
1583 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1584 OpcodeStr, Dt, IntOp, Commutable> {
1585 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1586 OpcodeStr, !strconcat(Dt, "64"),
1587 v1i64, v1i64, IntOp, Commutable>;
1588 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1589 OpcodeStr, !strconcat(Dt, "64"),
1590 v2i64, v2i64, IntOp, Commutable>;
1593 // Neon Narrowing 3-register vector intrinsics,
1594 // source operand element sizes of 16, 32 and 64 bits:
1595 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1596 string OpcodeStr, string Dt,
1597 Intrinsic IntOp, bit Commutable = 0> {
1598 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1599 OpcodeStr, !strconcat(Dt, "16"),
1600 v8i8, v8i16, IntOp, Commutable>;
1601 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1602 OpcodeStr, !strconcat(Dt, "32"),
1603 v4i16, v4i32, IntOp, Commutable>;
1604 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1605 OpcodeStr, !strconcat(Dt, "64"),
1606 v2i32, v2i64, IntOp, Commutable>;
1610 // Neon Long 3-register vector intrinsics.
1612 // First with only element sizes of 16 and 32 bits:
1613 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1614 InstrItinClass itin16, InstrItinClass itin32,
1615 string OpcodeStr, string Dt,
1616 Intrinsic IntOp, bit Commutable = 0> {
1617 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
1618 OpcodeStr, !strconcat(Dt, "16"),
1619 v4i32, v4i16, IntOp, Commutable>;
1620 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
1621 OpcodeStr, !strconcat(Dt, "32"),
1622 v2i64, v2i32, IntOp, Commutable>;
1625 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1626 InstrItinClass itin, string OpcodeStr, string Dt,
1628 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1629 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1630 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1631 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1634 // ....then also with element size of 8 bits:
1635 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1636 InstrItinClass itin16, InstrItinClass itin32,
1637 string OpcodeStr, string Dt,
1638 Intrinsic IntOp, bit Commutable = 0>
1639 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
1640 IntOp, Commutable> {
1641 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
1642 OpcodeStr, !strconcat(Dt, "8"),
1643 v8i16, v8i8, IntOp, Commutable>;
1647 // Neon Wide 3-register vector intrinsics,
1648 // source operand element sizes of 8, 16 and 32 bits:
1649 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1650 string OpcodeStr, string Dt,
1651 Intrinsic IntOp, bit Commutable = 0> {
1652 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1653 OpcodeStr, !strconcat(Dt, "8"),
1654 v8i16, v8i8, IntOp, Commutable>;
1655 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1656 OpcodeStr, !strconcat(Dt, "16"),
1657 v4i32, v4i16, IntOp, Commutable>;
1658 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1659 OpcodeStr, !strconcat(Dt, "32"),
1660 v2i64, v2i32, IntOp, Commutable>;
1664 // Neon Multiply-Op vector operations,
1665 // element sizes of 8, 16 and 32 bits:
1666 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1667 InstrItinClass itinD16, InstrItinClass itinD32,
1668 InstrItinClass itinQ16, InstrItinClass itinQ32,
1669 string OpcodeStr, string Dt, SDNode OpNode> {
1670 // 64-bit vector types.
1671 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1672 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1673 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1674 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1675 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1676 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1678 // 128-bit vector types.
1679 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1680 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1681 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1682 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1683 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1684 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1687 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1688 InstrItinClass itinD16, InstrItinClass itinD32,
1689 InstrItinClass itinQ16, InstrItinClass itinQ32,
1690 string OpcodeStr, string Dt, SDNode ShOp> {
1691 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1692 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1693 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1694 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1695 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1696 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1698 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1699 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1703 // Neon 3-argument intrinsics,
1704 // element sizes of 8, 16 and 32 bits:
1705 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1706 InstrItinClass itinD, InstrItinClass itinQ,
1707 string OpcodeStr, string Dt, Intrinsic IntOp> {
1708 // 64-bit vector types.
1709 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
1710 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1711 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
1712 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1713 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
1714 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1716 // 128-bit vector types.
1717 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
1718 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1719 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
1720 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1721 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
1722 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1726 // Neon Long 3-argument intrinsics.
1728 // First with only element sizes of 16 and 32 bits:
1729 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1730 InstrItinClass itin16, InstrItinClass itin32,
1731 string OpcodeStr, string Dt, Intrinsic IntOp> {
1732 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
1733 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1734 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
1735 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1738 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1739 string OpcodeStr, string Dt, Intrinsic IntOp> {
1740 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1741 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1742 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1743 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1746 // ....then also with element size of 8 bits:
1747 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1748 InstrItinClass itin16, InstrItinClass itin32,
1749 string OpcodeStr, string Dt, Intrinsic IntOp>
1750 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
1751 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
1752 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1756 // Neon 2-register vector intrinsics,
1757 // element sizes of 8, 16 and 32 bits:
1758 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1759 bits<5> op11_7, bit op4,
1760 InstrItinClass itinD, InstrItinClass itinQ,
1761 string OpcodeStr, string Dt, Intrinsic IntOp> {
1762 // 64-bit vector types.
1763 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1764 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1765 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1766 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1767 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1768 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1770 // 128-bit vector types.
1771 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1772 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1773 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1774 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1775 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1776 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1780 // Neon Pairwise long 2-register intrinsics,
1781 // element sizes of 8, 16 and 32 bits:
1782 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1783 bits<5> op11_7, bit op4,
1784 string OpcodeStr, string Dt, Intrinsic IntOp> {
1785 // 64-bit vector types.
1786 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1787 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1788 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1789 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1790 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1791 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1793 // 128-bit vector types.
1794 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1795 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1796 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1797 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1798 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1799 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1803 // Neon Pairwise long 2-register accumulate intrinsics,
1804 // element sizes of 8, 16 and 32 bits:
1805 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1806 bits<5> op11_7, bit op4,
1807 string OpcodeStr, string Dt, Intrinsic IntOp> {
1808 // 64-bit vector types.
1809 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1810 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1811 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1812 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1813 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1814 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1816 // 128-bit vector types.
1817 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1818 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1819 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1820 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1821 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1822 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1826 // Neon 2-register vector shift by immediate,
1827 // with f of either N2RegVShLFrm or N2RegVShRFrm
1828 // element sizes of 8, 16, 32 and 64 bits:
1829 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1830 InstrItinClass itin, string OpcodeStr, string Dt,
1831 SDNode OpNode, Format f> {
1832 // 64-bit vector types.
1833 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1834 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1835 let Inst{21-19} = 0b001; // imm6 = 001xxx
1837 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1838 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1839 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1841 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1842 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1843 let Inst{21} = 0b1; // imm6 = 1xxxxx
1845 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
1846 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1849 // 128-bit vector types.
1850 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1851 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1852 let Inst{21-19} = 0b001; // imm6 = 001xxx
1854 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1855 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1856 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1858 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1859 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1860 let Inst{21} = 0b1; // imm6 = 1xxxxx
1862 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
1863 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1867 // Neon Shift-Accumulate vector operations,
1868 // element sizes of 8, 16, 32 and 64 bits:
1869 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1870 string OpcodeStr, string Dt, SDNode ShOp> {
1871 // 64-bit vector types.
1872 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1873 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1874 let Inst{21-19} = 0b001; // imm6 = 001xxx
1876 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1877 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1878 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1880 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1881 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1882 let Inst{21} = 0b1; // imm6 = 1xxxxx
1884 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1885 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1888 // 128-bit vector types.
1889 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1890 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1891 let Inst{21-19} = 0b001; // imm6 = 001xxx
1893 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1894 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1895 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1897 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1898 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1899 let Inst{21} = 0b1; // imm6 = 1xxxxx
1901 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1902 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1907 // Neon Shift-Insert vector operations,
1908 // with f of either N2RegVShLFrm or N2RegVShRFrm
1909 // element sizes of 8, 16, 32 and 64 bits:
1910 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1911 string OpcodeStr, SDNode ShOp,
1913 // 64-bit vector types.
1914 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1915 f, OpcodeStr, "8", v8i8, ShOp> {
1916 let Inst{21-19} = 0b001; // imm6 = 001xxx
1918 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1919 f, OpcodeStr, "16", v4i16, ShOp> {
1920 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1922 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1923 f, OpcodeStr, "32", v2i32, ShOp> {
1924 let Inst{21} = 0b1; // imm6 = 1xxxxx
1926 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1927 f, OpcodeStr, "64", v1i64, ShOp>;
1930 // 128-bit vector types.
1931 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1932 f, OpcodeStr, "8", v16i8, ShOp> {
1933 let Inst{21-19} = 0b001; // imm6 = 001xxx
1935 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1936 f, OpcodeStr, "16", v8i16, ShOp> {
1937 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1939 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1940 f, OpcodeStr, "32", v4i32, ShOp> {
1941 let Inst{21} = 0b1; // imm6 = 1xxxxx
1943 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1944 f, OpcodeStr, "64", v2i64, ShOp>;
1948 // Neon Shift Long operations,
1949 // element sizes of 8, 16, 32 bits:
1950 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1951 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1952 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1953 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1954 let Inst{21-19} = 0b001; // imm6 = 001xxx
1956 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1957 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
1958 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1960 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1961 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
1962 let Inst{21} = 0b1; // imm6 = 1xxxxx
1966 // Neon Shift Narrow operations,
1967 // element sizes of 16, 32, 64 bits:
1968 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1969 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
1971 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1972 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
1973 let Inst{21-19} = 0b001; // imm6 = 001xxx
1975 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1976 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
1977 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1979 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
1980 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
1981 let Inst{21} = 0b1; // imm6 = 1xxxxx
1985 //===----------------------------------------------------------------------===//
1986 // Instruction Definitions.
1987 //===----------------------------------------------------------------------===//
1989 // Vector Add Operations.
1991 // VADD : Vector Add (integer and floating-point)
1992 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
1994 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
1995 v2f32, v2f32, fadd, 1>;
1996 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
1997 v4f32, v4f32, fadd, 1>;
1998 // VADDL : Vector Add Long (Q = D + D)
1999 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2000 "vaddl", "s", int_arm_neon_vaddls, 1>;
2001 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2002 "vaddl", "u", int_arm_neon_vaddlu, 1>;
2003 // VADDW : Vector Add Wide (Q = Q + D)
2004 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
2005 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
2006 // VHADD : Vector Halving Add
2007 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2008 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2009 "vhadd", "s", int_arm_neon_vhadds, 1>;
2010 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2011 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2012 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2013 // VRHADD : Vector Rounding Halving Add
2014 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2015 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2016 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2017 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2018 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2019 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2020 // VQADD : Vector Saturating Add
2021 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2022 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2023 "vqadd", "s", int_arm_neon_vqadds, 1>;
2024 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2025 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2026 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2027 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2028 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2029 int_arm_neon_vaddhn, 1>;
2030 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2031 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2032 int_arm_neon_vraddhn, 1>;
2034 // Vector Multiply Operations.
2036 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2037 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2038 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2039 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2040 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2041 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2042 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2043 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2044 v2f32, v2f32, fmul, 1>;
2045 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2046 v4f32, v4f32, fmul, 1>;
2047 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2048 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2049 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2052 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2053 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2054 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2055 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2056 (DSubReg_i16_reg imm:$lane))),
2057 (SubReg_i16_lane imm:$lane)))>;
2058 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2059 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2060 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2061 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2062 (DSubReg_i32_reg imm:$lane))),
2063 (SubReg_i32_lane imm:$lane)))>;
2064 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2065 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2066 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2067 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2068 (DSubReg_i32_reg imm:$lane))),
2069 (SubReg_i32_lane imm:$lane)))>;
2071 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2072 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2073 IIC_VMULi16Q, IIC_VMULi32Q,
2074 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2075 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2076 IIC_VMULi16Q, IIC_VMULi32Q,
2077 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2078 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2079 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2081 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2082 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2083 (DSubReg_i16_reg imm:$lane))),
2084 (SubReg_i16_lane imm:$lane)))>;
2085 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2086 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2088 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2089 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2090 (DSubReg_i32_reg imm:$lane))),
2091 (SubReg_i32_lane imm:$lane)))>;
2093 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2094 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2095 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2096 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2097 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2098 IIC_VMULi16Q, IIC_VMULi32Q,
2099 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2100 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2101 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2103 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2104 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2105 (DSubReg_i16_reg imm:$lane))),
2106 (SubReg_i16_lane imm:$lane)))>;
2107 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2108 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2110 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2111 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2112 (DSubReg_i32_reg imm:$lane))),
2113 (SubReg_i32_lane imm:$lane)))>;
2115 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2116 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2117 "vmull", "s", int_arm_neon_vmulls, 1>;
2118 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2119 "vmull", "u", int_arm_neon_vmullu, 1>;
2120 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2121 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2122 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2123 int_arm_neon_vmulls>;
2124 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2125 int_arm_neon_vmullu>;
2127 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2128 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2129 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2130 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2131 "vqdmull", "s", int_arm_neon_vqdmull>;
2133 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2135 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2136 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2137 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2138 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2140 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2142 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2143 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2144 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2146 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2147 v4f32, v2f32, fmul, fadd>;
2149 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2150 (mul (v8i16 QPR:$src2),
2151 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2152 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2153 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2154 (DSubReg_i16_reg imm:$lane))),
2155 (SubReg_i16_lane imm:$lane)))>;
2157 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2158 (mul (v4i32 QPR:$src2),
2159 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2160 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2161 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2162 (DSubReg_i32_reg imm:$lane))),
2163 (SubReg_i32_lane imm:$lane)))>;
2165 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2166 (fmul (v4f32 QPR:$src2),
2167 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2168 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2170 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2171 (DSubReg_i32_reg imm:$lane))),
2172 (SubReg_i32_lane imm:$lane)))>;
2174 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2175 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2176 "vmlal", "s", int_arm_neon_vmlals>;
2177 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2178 "vmlal", "u", int_arm_neon_vmlalu>;
2180 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2181 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2183 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2184 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2185 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2186 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2188 // VMLS : Vector Multiply Subtract (integer and floating-point)
2189 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2190 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2191 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2193 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2195 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2196 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2197 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2199 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2200 v4f32, v2f32, fmul, fsub>;
2202 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2203 (mul (v8i16 QPR:$src2),
2204 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2205 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2206 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2207 (DSubReg_i16_reg imm:$lane))),
2208 (SubReg_i16_lane imm:$lane)))>;
2210 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2211 (mul (v4i32 QPR:$src2),
2212 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2213 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2214 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2215 (DSubReg_i32_reg imm:$lane))),
2216 (SubReg_i32_lane imm:$lane)))>;
2218 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2219 (fmul (v4f32 QPR:$src2),
2220 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2221 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2222 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2223 (DSubReg_i32_reg imm:$lane))),
2224 (SubReg_i32_lane imm:$lane)))>;
2226 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2227 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2228 "vmlsl", "s", int_arm_neon_vmlsls>;
2229 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2230 "vmlsl", "u", int_arm_neon_vmlslu>;
2232 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2233 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2235 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2236 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2237 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2238 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2240 // Vector Subtract Operations.
2242 // VSUB : Vector Subtract (integer and floating-point)
2243 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2244 "vsub", "i", sub, 0>;
2245 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2246 v2f32, v2f32, fsub, 0>;
2247 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2248 v4f32, v4f32, fsub, 0>;
2249 // VSUBL : Vector Subtract Long (Q = D - D)
2250 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2251 "vsubl", "s", int_arm_neon_vsubls, 1>;
2252 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2253 "vsubl", "u", int_arm_neon_vsublu, 1>;
2254 // VSUBW : Vector Subtract Wide (Q = Q - D)
2255 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2256 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2257 // VHSUB : Vector Halving Subtract
2258 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2259 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2260 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2261 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2262 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2263 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2264 // VQSUB : Vector Saturing Subtract
2265 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2266 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2267 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2268 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2269 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2270 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2271 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2272 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2273 int_arm_neon_vsubhn, 0>;
2274 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2275 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2276 int_arm_neon_vrsubhn, 0>;
2278 // Vector Comparisons.
2280 // VCEQ : Vector Compare Equal
2281 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2282 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2283 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2285 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2287 // For disassembly only.
2288 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2291 // VCGE : Vector Compare Greater Than or Equal
2292 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2293 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2294 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2295 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2296 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2298 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2300 // For disassembly only.
2301 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2303 // For disassembly only.
2304 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2307 // VCGT : Vector Compare Greater Than
2308 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2309 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2310 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2311 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2312 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2314 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2316 // For disassembly only.
2317 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2319 // For disassembly only.
2320 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2323 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2324 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2325 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2326 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2327 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2328 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2329 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2330 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2331 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2332 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2333 // VTST : Vector Test Bits
2334 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2335 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2337 // Vector Bitwise Operations.
2339 def vnotd : PatFrag<(ops node:$in),
2340 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2341 def vnotq : PatFrag<(ops node:$in),
2342 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2345 // VAND : Vector Bitwise AND
2346 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2347 v2i32, v2i32, and, 1>;
2348 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2349 v4i32, v4i32, and, 1>;
2351 // VEOR : Vector Bitwise Exclusive OR
2352 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2353 v2i32, v2i32, xor, 1>;
2354 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2355 v4i32, v4i32, xor, 1>;
2357 // VORR : Vector Bitwise OR
2358 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2359 v2i32, v2i32, or, 1>;
2360 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2361 v4i32, v4i32, or, 1>;
2363 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2364 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2365 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2366 "vbic", "$dst, $src1, $src2", "",
2367 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2368 (vnotd DPR:$src2))))]>;
2369 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2370 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2371 "vbic", "$dst, $src1, $src2", "",
2372 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2373 (vnotq QPR:$src2))))]>;
2375 // VORN : Vector Bitwise OR NOT
2376 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2377 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2378 "vorn", "$dst, $src1, $src2", "",
2379 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2380 (vnotd DPR:$src2))))]>;
2381 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2382 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2383 "vorn", "$dst, $src1, $src2", "",
2384 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2385 (vnotq QPR:$src2))))]>;
2387 // VMVN : Vector Bitwise NOT (Immediate)
2389 let isReMaterializable = 1 in {
2390 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2391 (ins nModImm:$SIMM), IIC_VMOVImm,
2392 "vmvn", "i16", "$dst, $SIMM", "",
2393 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2394 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2395 (ins nModImm:$SIMM), IIC_VMOVImm,
2396 "vmvn", "i16", "$dst, $SIMM", "",
2397 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2399 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2400 (ins nModImm:$SIMM), IIC_VMOVImm,
2401 "vmvn", "i32", "$dst, $SIMM", "",
2402 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2403 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2404 (ins nModImm:$SIMM), IIC_VMOVImm,
2405 "vmvn", "i32", "$dst, $SIMM", "",
2406 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2409 // VMVN : Vector Bitwise NOT
2410 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2411 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2412 "vmvn", "$dst, $src", "",
2413 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2414 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2415 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2416 "vmvn", "$dst, $src", "",
2417 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2418 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2419 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2421 // VBSL : Vector Bitwise Select
2422 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2423 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2424 N3RegFrm, IIC_VCNTiD,
2425 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2427 (v2i32 (or (and DPR:$src2, DPR:$src1),
2428 (and DPR:$src3, (vnotd DPR:$src1)))))]>;
2429 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2430 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2431 N3RegFrm, IIC_VCNTiQ,
2432 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2434 (v4i32 (or (and QPR:$src2, QPR:$src1),
2435 (and QPR:$src3, (vnotq QPR:$src1)))))]>;
2437 // VBIF : Vector Bitwise Insert if False
2438 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2439 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2440 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2441 N3RegFrm, IIC_VBINiD,
2442 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2443 [/* For disassembly only; pattern left blank */]>;
2444 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2445 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2446 N3RegFrm, IIC_VBINiQ,
2447 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2448 [/* For disassembly only; pattern left blank */]>;
2450 // VBIT : Vector Bitwise Insert if True
2451 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2452 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2453 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2454 N3RegFrm, IIC_VBINiD,
2455 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2456 [/* For disassembly only; pattern left blank */]>;
2457 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2458 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2459 N3RegFrm, IIC_VBINiQ,
2460 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2461 [/* For disassembly only; pattern left blank */]>;
2463 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2464 // for equivalent operations with different register constraints; it just
2467 // Vector Absolute Differences.
2469 // VABD : Vector Absolute Difference
2470 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2471 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2472 "vabd", "s", int_arm_neon_vabds, 0>;
2473 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2474 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2475 "vabd", "u", int_arm_neon_vabdu, 0>;
2476 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2477 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2478 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2479 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2481 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2482 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2483 "vabdl", "s", int_arm_neon_vabdls, 0>;
2484 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2485 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2487 // VABA : Vector Absolute Difference and Accumulate
2488 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2489 "vaba", "s", int_arm_neon_vabas>;
2490 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2491 "vaba", "u", int_arm_neon_vabau>;
2493 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2494 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2495 "vabal", "s", int_arm_neon_vabals>;
2496 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2497 "vabal", "u", int_arm_neon_vabalu>;
2499 // Vector Maximum and Minimum.
2501 // VMAX : Vector Maximum
2502 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2503 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2504 "vmax", "s", int_arm_neon_vmaxs, 1>;
2505 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2506 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2507 "vmax", "u", int_arm_neon_vmaxu, 1>;
2508 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2510 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2511 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2513 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2515 // VMIN : Vector Minimum
2516 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2517 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2518 "vmin", "s", int_arm_neon_vmins, 1>;
2519 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2520 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2521 "vmin", "u", int_arm_neon_vminu, 1>;
2522 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2524 v2f32, v2f32, int_arm_neon_vmins, 1>;
2525 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2527 v4f32, v4f32, int_arm_neon_vmins, 1>;
2529 // Vector Pairwise Operations.
2531 // VPADD : Vector Pairwise Add
2532 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2534 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2535 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2537 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2538 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2540 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2541 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2542 IIC_VBIND, "vpadd", "f32",
2543 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2545 // VPADDL : Vector Pairwise Add Long
2546 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2547 int_arm_neon_vpaddls>;
2548 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2549 int_arm_neon_vpaddlu>;
2551 // VPADAL : Vector Pairwise Add and Accumulate Long
2552 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2553 int_arm_neon_vpadals>;
2554 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2555 int_arm_neon_vpadalu>;
2557 // VPMAX : Vector Pairwise Maximum
2558 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2559 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2560 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2561 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2562 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2563 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2564 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2565 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2566 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2567 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2568 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2569 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2570 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2571 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2573 // VPMIN : Vector Pairwise Minimum
2574 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2575 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2576 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2577 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2578 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2579 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2580 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2581 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
2582 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2583 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
2584 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2585 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
2586 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
2587 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
2589 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2591 // VRECPE : Vector Reciprocal Estimate
2592 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2593 IIC_VUNAD, "vrecpe", "u32",
2594 v2i32, v2i32, int_arm_neon_vrecpe>;
2595 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2596 IIC_VUNAQ, "vrecpe", "u32",
2597 v4i32, v4i32, int_arm_neon_vrecpe>;
2598 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2599 IIC_VUNAD, "vrecpe", "f32",
2600 v2f32, v2f32, int_arm_neon_vrecpe>;
2601 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2602 IIC_VUNAQ, "vrecpe", "f32",
2603 v4f32, v4f32, int_arm_neon_vrecpe>;
2605 // VRECPS : Vector Reciprocal Step
2606 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2607 IIC_VRECSD, "vrecps", "f32",
2608 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2609 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2610 IIC_VRECSQ, "vrecps", "f32",
2611 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2613 // VRSQRTE : Vector Reciprocal Square Root Estimate
2614 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2615 IIC_VUNAD, "vrsqrte", "u32",
2616 v2i32, v2i32, int_arm_neon_vrsqrte>;
2617 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2618 IIC_VUNAQ, "vrsqrte", "u32",
2619 v4i32, v4i32, int_arm_neon_vrsqrte>;
2620 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2621 IIC_VUNAD, "vrsqrte", "f32",
2622 v2f32, v2f32, int_arm_neon_vrsqrte>;
2623 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2624 IIC_VUNAQ, "vrsqrte", "f32",
2625 v4f32, v4f32, int_arm_neon_vrsqrte>;
2627 // VRSQRTS : Vector Reciprocal Square Root Step
2628 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2629 IIC_VRECSD, "vrsqrts", "f32",
2630 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2631 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2632 IIC_VRECSQ, "vrsqrts", "f32",
2633 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2637 // VSHL : Vector Shift
2638 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
2639 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2640 "vshl", "s", int_arm_neon_vshifts, 0>;
2641 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
2642 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2643 "vshl", "u", int_arm_neon_vshiftu, 0>;
2644 // VSHL : Vector Shift Left (Immediate)
2645 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
2647 // VSHR : Vector Shift Right (Immediate)
2648 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
2650 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
2653 // VSHLL : Vector Shift Left Long
2654 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2655 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2657 // VSHLL : Vector Shift Left Long (with maximum shift count)
2658 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2659 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2660 ValueType OpTy, SDNode OpNode>
2661 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2662 ResTy, OpTy, OpNode> {
2663 let Inst{21-16} = op21_16;
2665 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2666 v8i16, v8i8, NEONvshlli>;
2667 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2668 v4i32, v4i16, NEONvshlli>;
2669 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2670 v2i64, v2i32, NEONvshlli>;
2672 // VSHRN : Vector Shift Right and Narrow
2673 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2676 // VRSHL : Vector Rounding Shift
2677 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
2678 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2679 "vrshl", "s", int_arm_neon_vrshifts, 0>;
2680 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
2681 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2682 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2683 // VRSHR : Vector Rounding Shift Right
2684 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
2686 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
2689 // VRSHRN : Vector Rounding Shift Right and Narrow
2690 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2693 // VQSHL : Vector Saturating Shift
2694 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
2695 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2696 "vqshl", "s", int_arm_neon_vqshifts, 0>;
2697 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
2698 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2699 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2700 // VQSHL : Vector Saturating Shift Left (Immediate)
2701 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
2703 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
2705 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2706 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
2709 // VQSHRN : Vector Saturating Shift Right and Narrow
2710 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2712 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2715 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2716 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2719 // VQRSHL : Vector Saturating Rounding Shift
2720 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
2721 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2722 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
2723 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
2724 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2725 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
2727 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2728 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2730 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2733 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2734 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2737 // VSRA : Vector Shift Right and Accumulate
2738 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2739 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2740 // VRSRA : Vector Rounding Shift Right and Accumulate
2741 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2742 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2744 // VSLI : Vector Shift Left and Insert
2745 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
2746 // VSRI : Vector Shift Right and Insert
2747 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
2749 // Vector Absolute and Saturating Absolute.
2751 // VABS : Vector Absolute Value
2752 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2753 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2755 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2756 IIC_VUNAD, "vabs", "f32",
2757 v2f32, v2f32, int_arm_neon_vabs>;
2758 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2759 IIC_VUNAQ, "vabs", "f32",
2760 v4f32, v4f32, int_arm_neon_vabs>;
2762 // VQABS : Vector Saturating Absolute Value
2763 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2764 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2765 int_arm_neon_vqabs>;
2769 def vnegd : PatFrag<(ops node:$in),
2770 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
2771 def vnegq : PatFrag<(ops node:$in),
2772 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
2774 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2775 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2776 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2777 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
2778 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2779 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2780 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2781 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
2783 // VNEG : Vector Negate (integer)
2784 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2785 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2786 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2787 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2788 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2789 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2791 // VNEG : Vector Negate (floating-point)
2792 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2793 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2794 "vneg", "f32", "$dst, $src", "",
2795 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2796 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2797 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2798 "vneg", "f32", "$dst, $src", "",
2799 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2801 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
2802 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
2803 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
2804 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
2805 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
2806 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
2808 // VQNEG : Vector Saturating Negate
2809 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2810 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2811 int_arm_neon_vqneg>;
2813 // Vector Bit Counting Operations.
2815 // VCLS : Vector Count Leading Sign Bits
2816 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2817 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2819 // VCLZ : Vector Count Leading Zeros
2820 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2821 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2823 // VCNT : Vector Count One Bits
2824 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2825 IIC_VCNTiD, "vcnt", "8",
2826 v8i8, v8i8, int_arm_neon_vcnt>;
2827 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2828 IIC_VCNTiQ, "vcnt", "8",
2829 v16i8, v16i8, int_arm_neon_vcnt>;
2831 // Vector Swap -- for disassembly only.
2832 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2833 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2834 "vswp", "$dst, $src", "", []>;
2835 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2836 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2837 "vswp", "$dst, $src", "", []>;
2839 // Vector Move Operations.
2841 // VMOV : Vector Move (Register)
2843 let neverHasSideEffects = 1 in {
2844 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2845 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2846 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2847 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2849 // Pseudo vector move instructions for QQ and QQQQ registers. This should
2850 // be expanded after register allocation is completed.
2851 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
2852 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2854 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
2855 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2856 } // neverHasSideEffects
2858 // VMOV : Vector Move (Immediate)
2860 let isReMaterializable = 1 in {
2861 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2862 (ins nModImm:$SIMM), IIC_VMOVImm,
2863 "vmov", "i8", "$dst, $SIMM", "",
2864 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
2865 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2866 (ins nModImm:$SIMM), IIC_VMOVImm,
2867 "vmov", "i8", "$dst, $SIMM", "",
2868 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
2870 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
2871 (ins nModImm:$SIMM), IIC_VMOVImm,
2872 "vmov", "i16", "$dst, $SIMM", "",
2873 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
2874 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
2875 (ins nModImm:$SIMM), IIC_VMOVImm,
2876 "vmov", "i16", "$dst, $SIMM", "",
2877 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
2879 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
2880 (ins nModImm:$SIMM), IIC_VMOVImm,
2881 "vmov", "i32", "$dst, $SIMM", "",
2882 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
2883 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
2884 (ins nModImm:$SIMM), IIC_VMOVImm,
2885 "vmov", "i32", "$dst, $SIMM", "",
2886 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
2888 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2889 (ins nModImm:$SIMM), IIC_VMOVImm,
2890 "vmov", "i64", "$dst, $SIMM", "",
2891 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
2892 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2893 (ins nModImm:$SIMM), IIC_VMOVImm,
2894 "vmov", "i64", "$dst, $SIMM", "",
2895 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
2896 } // isReMaterializable
2898 // VMOV : Vector Get Lane (move scalar to ARM core register)
2900 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2901 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2902 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2903 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2905 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2906 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2907 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2908 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2910 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2911 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2912 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2913 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2915 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2916 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2917 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2918 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2920 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2921 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2922 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2923 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2925 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2926 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2927 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2928 (DSubReg_i8_reg imm:$lane))),
2929 (SubReg_i8_lane imm:$lane))>;
2930 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2931 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2932 (DSubReg_i16_reg imm:$lane))),
2933 (SubReg_i16_lane imm:$lane))>;
2934 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2935 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2936 (DSubReg_i8_reg imm:$lane))),
2937 (SubReg_i8_lane imm:$lane))>;
2938 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2939 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2940 (DSubReg_i16_reg imm:$lane))),
2941 (SubReg_i16_lane imm:$lane))>;
2942 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2943 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2944 (DSubReg_i32_reg imm:$lane))),
2945 (SubReg_i32_lane imm:$lane))>;
2946 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2947 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2948 (SSubReg_f32_reg imm:$src2))>;
2949 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2950 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2951 (SSubReg_f32_reg imm:$src2))>;
2952 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2953 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2954 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2955 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2958 // VMOV : Vector Set Lane (move ARM core register to scalar)
2960 let Constraints = "$src1 = $dst" in {
2961 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
2962 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2963 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
2964 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
2965 GPR:$src2, imm:$lane))]>;
2966 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
2967 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2968 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
2969 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
2970 GPR:$src2, imm:$lane))]>;
2971 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
2972 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
2973 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
2974 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
2975 GPR:$src2, imm:$lane))]>;
2977 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
2978 (v16i8 (INSERT_SUBREG QPR:$src1,
2979 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
2980 (DSubReg_i8_reg imm:$lane))),
2981 GPR:$src2, (SubReg_i8_lane imm:$lane))),
2982 (DSubReg_i8_reg imm:$lane)))>;
2983 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
2984 (v8i16 (INSERT_SUBREG QPR:$src1,
2985 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
2986 (DSubReg_i16_reg imm:$lane))),
2987 GPR:$src2, (SubReg_i16_lane imm:$lane))),
2988 (DSubReg_i16_reg imm:$lane)))>;
2989 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
2990 (v4i32 (INSERT_SUBREG QPR:$src1,
2991 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
2992 (DSubReg_i32_reg imm:$lane))),
2993 GPR:$src2, (SubReg_i32_lane imm:$lane))),
2994 (DSubReg_i32_reg imm:$lane)))>;
2996 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
2997 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
2998 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
2999 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3000 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3001 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3003 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3004 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3005 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3006 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3008 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3009 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3010 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3011 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3012 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3013 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3015 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3016 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3017 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3018 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3019 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3020 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3022 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3023 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3024 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3026 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3027 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3028 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3030 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3031 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3032 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3035 // VDUP : Vector Duplicate (from ARM core register to all elements)
3037 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3038 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3039 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3040 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3041 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3042 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3043 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3044 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3046 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3047 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3048 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3049 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3050 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3051 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3053 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3054 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3055 [(set DPR:$dst, (v2f32 (NEONvdup
3056 (f32 (bitconvert GPR:$src)))))]>;
3057 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3058 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3059 [(set QPR:$dst, (v4f32 (NEONvdup
3060 (f32 (bitconvert GPR:$src)))))]>;
3062 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3064 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3066 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3067 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3068 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3070 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3071 ValueType ResTy, ValueType OpTy>
3072 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3073 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3074 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3077 // Inst{19-16} is partially specified depending on the element size.
3079 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3080 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3081 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3082 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3083 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3084 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3085 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3086 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3088 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3089 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3090 (DSubReg_i8_reg imm:$lane))),
3091 (SubReg_i8_lane imm:$lane)))>;
3092 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3093 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3094 (DSubReg_i16_reg imm:$lane))),
3095 (SubReg_i16_lane imm:$lane)))>;
3096 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3097 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3098 (DSubReg_i32_reg imm:$lane))),
3099 (SubReg_i32_lane imm:$lane)))>;
3100 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3101 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3102 (DSubReg_i32_reg imm:$lane))),
3103 (SubReg_i32_lane imm:$lane)))>;
3105 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3106 (outs DPR:$dst), (ins SPR:$src),
3107 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3108 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3110 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3111 (outs QPR:$dst), (ins SPR:$src),
3112 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3113 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3115 // VMOVN : Vector Narrowing Move
3116 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3117 "vmovn", "i", int_arm_neon_vmovn>;
3118 // VQMOVN : Vector Saturating Narrowing Move
3119 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3120 "vqmovn", "s", int_arm_neon_vqmovns>;
3121 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3122 "vqmovn", "u", int_arm_neon_vqmovnu>;
3123 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3124 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3125 // VMOVL : Vector Lengthening Move
3126 defm VMOVLs : N2VLInt_QHS<0b01,0b10100,0,1, "vmovl", "s",
3127 int_arm_neon_vmovls>;
3128 defm VMOVLu : N2VLInt_QHS<0b11,0b10100,0,1, "vmovl", "u",
3129 int_arm_neon_vmovlu>;
3131 // Vector Conversions.
3133 // VCVT : Vector Convert Between Floating-Point and Integers
3134 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3135 v2i32, v2f32, fp_to_sint>;
3136 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3137 v2i32, v2f32, fp_to_uint>;
3138 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3139 v2f32, v2i32, sint_to_fp>;
3140 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3141 v2f32, v2i32, uint_to_fp>;
3143 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3144 v4i32, v4f32, fp_to_sint>;
3145 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3146 v4i32, v4f32, fp_to_uint>;
3147 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3148 v4f32, v4i32, sint_to_fp>;
3149 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3150 v4f32, v4i32, uint_to_fp>;
3152 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3153 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3154 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3155 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3156 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3157 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3158 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3159 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3160 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3162 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3163 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3164 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3165 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3166 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3167 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3168 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3169 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3173 // VREV64 : Vector Reverse elements within 64-bit doublewords
3175 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3176 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3177 (ins DPR:$src), IIC_VMOVD,
3178 OpcodeStr, Dt, "$dst, $src", "",
3179 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3180 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3181 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3182 (ins QPR:$src), IIC_VMOVD,
3183 OpcodeStr, Dt, "$dst, $src", "",
3184 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3186 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3187 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3188 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3189 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3191 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3192 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3193 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3194 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3196 // VREV32 : Vector Reverse elements within 32-bit words
3198 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3199 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3200 (ins DPR:$src), IIC_VMOVD,
3201 OpcodeStr, Dt, "$dst, $src", "",
3202 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3203 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3204 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3205 (ins QPR:$src), IIC_VMOVD,
3206 OpcodeStr, Dt, "$dst, $src", "",
3207 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3209 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3210 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3212 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3213 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3215 // VREV16 : Vector Reverse elements within 16-bit halfwords
3217 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3218 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3219 (ins DPR:$src), IIC_VMOVD,
3220 OpcodeStr, Dt, "$dst, $src", "",
3221 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3222 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3223 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3224 (ins QPR:$src), IIC_VMOVD,
3225 OpcodeStr, Dt, "$dst, $src", "",
3226 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3228 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3229 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3231 // Other Vector Shuffles.
3233 // VEXT : Vector Extract
3235 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3236 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3237 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3238 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3239 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3240 (Ty DPR:$rhs), imm:$index)))]>;
3242 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3243 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3244 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3245 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3246 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3247 (Ty QPR:$rhs), imm:$index)))]>;
3249 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3250 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3251 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3252 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3254 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3255 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3256 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3257 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3259 // VTRN : Vector Transpose
3261 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3262 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3263 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3265 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3266 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3267 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3269 // VUZP : Vector Unzip (Deinterleave)
3271 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3272 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3273 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3275 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3276 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3277 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3279 // VZIP : Vector Zip (Interleave)
3281 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3282 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3283 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3285 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3286 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3287 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3289 // Vector Table Lookup and Table Extension.
3291 // VTBL : Vector Table Lookup
3293 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3294 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3295 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3296 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3297 let hasExtraSrcRegAllocReq = 1 in {
3299 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3300 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3301 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3303 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3304 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3305 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3307 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3308 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3310 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3311 } // hasExtraSrcRegAllocReq = 1
3313 // VTBX : Vector Table Extension
3315 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3316 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3317 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3318 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3319 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3320 let hasExtraSrcRegAllocReq = 1 in {
3322 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3323 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3324 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3326 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3327 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3328 NVTBLFrm, IIC_VTBX3,
3329 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3330 "$orig = $dst", []>;
3332 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3333 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3334 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3335 "$orig = $dst", []>;
3336 } // hasExtraSrcRegAllocReq = 1
3338 //===----------------------------------------------------------------------===//
3339 // NEON instructions for single-precision FP math
3340 //===----------------------------------------------------------------------===//
3342 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3343 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3344 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3348 class N3VSPat<SDNode OpNode, NeonI Inst>
3349 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3350 (EXTRACT_SUBREG (v2f32
3351 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3353 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3357 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3358 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3359 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3361 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3363 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3367 // These need separate instructions because they must use DPR_VFP2 register
3368 // class which have SPR sub-registers.
3370 // Vector Add Operations used for single-precision FP
3371 let neverHasSideEffects = 1 in
3372 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3373 def : N3VSPat<fadd, VADDfd_sfp>;
3375 // Vector Sub Operations used for single-precision FP
3376 let neverHasSideEffects = 1 in
3377 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3378 def : N3VSPat<fsub, VSUBfd_sfp>;
3380 // Vector Multiply Operations used for single-precision FP
3381 let neverHasSideEffects = 1 in
3382 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3383 def : N3VSPat<fmul, VMULfd_sfp>;
3385 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3386 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3387 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3389 //let neverHasSideEffects = 1 in
3390 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3391 // v2f32, fmul, fadd>;
3392 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3394 //let neverHasSideEffects = 1 in
3395 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3396 // v2f32, fmul, fsub>;
3397 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3399 // Vector Absolute used for single-precision FP
3400 let neverHasSideEffects = 1 in
3401 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3402 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3403 "vabs", "f32", "$dst, $src", "", []>;
3404 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3406 // Vector Negate used for single-precision FP
3407 let neverHasSideEffects = 1 in
3408 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3409 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3410 "vneg", "f32", "$dst, $src", "", []>;
3411 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3413 // Vector Maximum used for single-precision FP
3414 let neverHasSideEffects = 1 in
3415 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3416 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3417 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3418 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3420 // Vector Minimum used for single-precision FP
3421 let neverHasSideEffects = 1 in
3422 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3423 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3424 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3425 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3427 // Vector Convert between single-precision FP and integer
3428 let neverHasSideEffects = 1 in
3429 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3430 v2i32, v2f32, fp_to_sint>;
3431 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3433 let neverHasSideEffects = 1 in
3434 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3435 v2i32, v2f32, fp_to_uint>;
3436 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3438 let neverHasSideEffects = 1 in
3439 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3440 v2f32, v2i32, sint_to_fp>;
3441 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3443 let neverHasSideEffects = 1 in
3444 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3445 v2f32, v2i32, uint_to_fp>;
3446 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3448 //===----------------------------------------------------------------------===//
3449 // Non-Instruction Patterns
3450 //===----------------------------------------------------------------------===//
3453 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3454 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3455 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3456 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3457 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3458 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3459 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3460 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3461 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3462 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3463 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3464 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3465 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3466 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3467 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3468 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3469 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3470 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3471 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3472 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3473 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3474 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3475 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3476 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3477 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3478 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3479 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3480 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3481 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3482 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3484 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3485 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3486 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3487 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3488 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3489 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3490 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3491 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3492 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3493 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3494 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3495 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3496 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3497 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3498 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3499 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3500 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3501 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3502 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3503 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3504 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3505 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3506 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3507 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3508 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3509 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3510 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3511 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3512 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3513 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;