1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
402 return cast<LoadSDNode>(N)->getAlignment() >= 8;
404 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 8;
408 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
409 return cast<LoadSDNode>(N)->getAlignment() == 4;
411 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() == 4;
415 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() == 2;
418 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
419 (store node:$val, node:$ptr), [{
420 return cast<StoreSDNode>(N)->getAlignment() == 2;
422 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 return cast<LoadSDNode>(N)->getAlignment() == 1;
425 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() == 1;
429 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() < 4;
432 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
433 (store node:$val, node:$ptr), [{
434 return cast<StoreSDNode>(N)->getAlignment() < 4;
437 //===----------------------------------------------------------------------===//
438 // NEON-specific DAG Nodes.
439 //===----------------------------------------------------------------------===//
441 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
442 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
444 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
445 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
446 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
447 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
448 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
449 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
450 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
451 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
452 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
453 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
454 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
456 // Types for vector shift by immediates. The "SHX" version is for long and
457 // narrow operations where the source and destination vectors have different
458 // types. The "SHINS" version is for shift and insert operations.
459 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
461 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
463 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
464 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
466 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
467 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
468 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
469 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
471 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
472 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
473 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
475 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
476 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
477 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
478 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
479 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
480 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
482 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
483 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
484 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
486 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
487 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
489 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
491 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
492 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
494 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
495 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
496 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
497 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
499 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
501 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
502 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
504 def NEONvbsl : SDNode<"ARMISD::VBSL",
505 SDTypeProfile<1, 3, [SDTCisVec<0>,
508 SDTCisSameAs<0, 3>]>>;
510 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
512 // VDUPLANE can produce a quad-register result from a double-register source,
513 // so the result is not constrained to match the source.
514 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
515 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
518 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
519 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
520 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
522 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
523 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
524 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
525 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
527 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
529 SDTCisSameAs<0, 3>]>;
530 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
531 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
532 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
534 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
535 SDTCisSameAs<1, 2>]>;
536 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
537 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
539 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
540 SDTCisSameAs<0, 2>]>;
541 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
542 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
544 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
545 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
546 unsigned EltBits = 0;
547 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
548 return (EltBits == 32 && EltVal == 0);
551 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
552 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
553 unsigned EltBits = 0;
554 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
555 return (EltBits == 8 && EltVal == 0xff);
558 //===----------------------------------------------------------------------===//
559 // NEON load / store instructions
560 //===----------------------------------------------------------------------===//
562 // Use VLDM to load a Q register as a D register pair.
563 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
565 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
567 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
569 // Use VSTM to store a Q register as a D register pair.
570 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
572 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
574 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
576 // Classes for VLD* pseudo-instructions with multi-register operands.
577 // These are expanded to real instructions after register allocation.
578 class VLDQPseudo<InstrItinClass itin>
579 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
580 class VLDQWBPseudo<InstrItinClass itin>
581 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset), itin,
584 class VLDQWBfixedPseudo<InstrItinClass itin>
585 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
586 (ins addrmode6:$addr), itin,
588 class VLDQWBregisterPseudo<InstrItinClass itin>
589 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
590 (ins addrmode6:$addr, rGPR:$offset), itin,
593 class VLDQQPseudo<InstrItinClass itin>
594 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
595 class VLDQQWBPseudo<InstrItinClass itin>
596 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
597 (ins addrmode6:$addr, am6offset:$offset), itin,
599 class VLDQQWBfixedPseudo<InstrItinClass itin>
600 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
601 (ins addrmode6:$addr), itin,
603 class VLDQQWBregisterPseudo<InstrItinClass itin>
604 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
605 (ins addrmode6:$addr, rGPR:$offset), itin,
609 class VLDQQQQPseudo<InstrItinClass itin>
610 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
612 class VLDQQQQWBPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
614 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
615 "$addr.addr = $wb, $src = $dst">;
617 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
619 // VLD1 : Vector Load (multiple single elements)
620 class VLD1D<bits<4> op7_4, string Dt>
621 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
622 (ins addrmode6:$Rn), IIC_VLD1,
623 "vld1", Dt, "$Vd, $Rn", "", []> {
626 let DecoderMethod = "DecodeVLDST1Instruction";
628 class VLD1Q<bits<4> op7_4, string Dt>
629 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
630 (ins addrmode6:$Rn), IIC_VLD1x2,
631 "vld1", Dt, "$Vd, $Rn", "", []> {
633 let Inst{5-4} = Rn{5-4};
634 let DecoderMethod = "DecodeVLDST1Instruction";
637 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
638 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
639 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
640 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
642 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
643 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
644 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
645 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
647 // ...with address register writeback:
648 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
649 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
650 (ins addrmode6:$Rn), IIC_VLD1u,
651 "vld1", Dt, "$Vd, $Rn!",
652 "$Rn.addr = $wb", []> {
653 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
655 let DecoderMethod = "DecodeVLDST1Instruction";
657 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
658 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
659 "vld1", Dt, "$Vd, $Rn, $Rm",
660 "$Rn.addr = $wb", []> {
662 let DecoderMethod = "DecodeVLDST1Instruction";
665 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
666 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
667 (ins addrmode6:$Rn), IIC_VLD1x2u,
668 "vld1", Dt, "$Vd, $Rn!",
669 "$Rn.addr = $wb", []> {
670 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
671 let Inst{5-4} = Rn{5-4};
672 let DecoderMethod = "DecodeVLDST1Instruction";
674 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
675 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
676 "vld1", Dt, "$Vd, $Rn, $Rm",
677 "$Rn.addr = $wb", []> {
678 let Inst{5-4} = Rn{5-4};
679 let DecoderMethod = "DecodeVLDST1Instruction";
683 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
684 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
685 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
686 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
687 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
688 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
689 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
690 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
692 // ...with 3 registers
693 class VLD1D3<bits<4> op7_4, string Dt>
694 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
695 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
696 "$Vd, $Rn", "", []> {
699 let DecoderMethod = "DecodeVLDST1Instruction";
701 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
702 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
703 (ins addrmode6:$Rn), IIC_VLD1x2u,
704 "vld1", Dt, "$Vd, $Rn!",
705 "$Rn.addr = $wb", []> {
706 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
708 let DecoderMethod = "DecodeVLDST1Instruction";
710 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
711 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
712 "vld1", Dt, "$Vd, $Rn, $Rm",
713 "$Rn.addr = $wb", []> {
715 let DecoderMethod = "DecodeVLDST1Instruction";
719 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
720 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
721 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
722 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
724 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
725 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
726 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
727 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
729 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
730 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
731 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
733 // ...with 4 registers
734 class VLD1D4<bits<4> op7_4, string Dt>
735 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
736 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
737 "$Vd, $Rn", "", []> {
739 let Inst{5-4} = Rn{5-4};
740 let DecoderMethod = "DecodeVLDST1Instruction";
742 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
743 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
744 (ins addrmode6:$Rn), IIC_VLD1x2u,
745 "vld1", Dt, "$Vd, $Rn!",
746 "$Rn.addr = $wb", []> {
747 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
748 let Inst{5-4} = Rn{5-4};
749 let DecoderMethod = "DecodeVLDST1Instruction";
751 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
752 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
753 "vld1", Dt, "$Vd, $Rn, $Rm",
754 "$Rn.addr = $wb", []> {
755 let Inst{5-4} = Rn{5-4};
756 let DecoderMethod = "DecodeVLDST1Instruction";
760 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
761 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
762 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
763 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
765 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
766 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
767 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
768 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
770 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
771 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
772 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
774 // VLD2 : Vector Load (multiple 2-element structures)
775 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
777 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
778 (ins addrmode6:$Rn), itin,
779 "vld2", Dt, "$Vd, $Rn", "", []> {
781 let Inst{5-4} = Rn{5-4};
782 let DecoderMethod = "DecodeVLDST2Instruction";
785 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
786 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
787 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
789 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
790 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
791 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
793 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
794 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
795 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
797 // ...with address register writeback:
798 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
799 RegisterOperand VdTy, InstrItinClass itin> {
800 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
801 (ins addrmode6:$Rn), itin,
802 "vld2", Dt, "$Vd, $Rn!",
803 "$Rn.addr = $wb", []> {
804 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
805 let Inst{5-4} = Rn{5-4};
806 let DecoderMethod = "DecodeVLDST2Instruction";
808 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
809 (ins addrmode6:$Rn, rGPR:$Rm), itin,
810 "vld2", Dt, "$Vd, $Rn, $Rm",
811 "$Rn.addr = $wb", []> {
812 let Inst{5-4} = Rn{5-4};
813 let DecoderMethod = "DecodeVLDST2Instruction";
817 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
818 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
819 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
821 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
822 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
823 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
825 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
826 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
827 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
828 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
829 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
830 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
832 // ...with double-spaced registers
833 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
834 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
835 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
836 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
837 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
838 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
840 // VLD3 : Vector Load (multiple 3-element structures)
841 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
842 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
843 (ins addrmode6:$Rn), IIC_VLD3,
844 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
847 let DecoderMethod = "DecodeVLDST3Instruction";
850 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
851 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
852 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
854 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
855 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
856 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
858 // ...with address register writeback:
859 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
860 : NLdSt<0, 0b10, op11_8, op7_4,
861 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
862 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
863 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
864 "$Rn.addr = $wb", []> {
866 let DecoderMethod = "DecodeVLDST3Instruction";
869 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
870 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
871 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
873 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
874 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
875 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
877 // ...with double-spaced registers:
878 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
879 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
880 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
881 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
882 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
883 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
885 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
886 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
887 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
889 // ...alternate versions to be allocated odd register numbers:
890 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
891 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
892 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
894 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
895 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
896 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
898 // VLD4 : Vector Load (multiple 4-element structures)
899 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
900 : NLdSt<0, 0b10, op11_8, op7_4,
901 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
902 (ins addrmode6:$Rn), IIC_VLD4,
903 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
905 let Inst{5-4} = Rn{5-4};
906 let DecoderMethod = "DecodeVLDST4Instruction";
909 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
910 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
911 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
913 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
914 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
915 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
917 // ...with address register writeback:
918 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
919 : NLdSt<0, 0b10, op11_8, op7_4,
920 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
921 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
922 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
923 "$Rn.addr = $wb", []> {
924 let Inst{5-4} = Rn{5-4};
925 let DecoderMethod = "DecodeVLDST4Instruction";
928 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
929 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
930 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
932 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
933 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
934 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
936 // ...with double-spaced registers:
937 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
938 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
939 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
940 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
941 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
942 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
944 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
945 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
946 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
948 // ...alternate versions to be allocated odd register numbers:
949 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
950 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
951 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
953 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
954 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
955 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
957 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
959 // Classes for VLD*LN pseudo-instructions with multi-register operands.
960 // These are expanded to real instructions after register allocation.
961 class VLDQLNPseudo<InstrItinClass itin>
962 : PseudoNLdSt<(outs QPR:$dst),
963 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
964 itin, "$src = $dst">;
965 class VLDQLNWBPseudo<InstrItinClass itin>
966 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
967 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
968 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
969 class VLDQQLNPseudo<InstrItinClass itin>
970 : PseudoNLdSt<(outs QQPR:$dst),
971 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
972 itin, "$src = $dst">;
973 class VLDQQLNWBPseudo<InstrItinClass itin>
974 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
975 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
976 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
977 class VLDQQQQLNPseudo<InstrItinClass itin>
978 : PseudoNLdSt<(outs QQQQPR:$dst),
979 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
980 itin, "$src = $dst">;
981 class VLDQQQQLNWBPseudo<InstrItinClass itin>
982 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
983 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
984 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
986 // VLD1LN : Vector Load (single element to one lane)
987 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
989 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
990 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
991 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
993 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
994 (i32 (LoadOp addrmode6:$Rn)),
997 let DecoderMethod = "DecodeVLD1LN";
999 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1001 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1002 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1003 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1005 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1006 (i32 (LoadOp addrmode6oneL32:$Rn)),
1009 let DecoderMethod = "DecodeVLD1LN";
1011 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1012 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1013 (i32 (LoadOp addrmode6:$addr)),
1017 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1018 let Inst{7-5} = lane{2-0};
1020 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1021 let Inst{7-6} = lane{1-0};
1022 let Inst{5-4} = Rn{5-4};
1024 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1025 let Inst{7} = lane{0};
1026 let Inst{5-4} = Rn{5-4};
1029 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1030 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1031 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1033 def : Pat<(vector_insert (v2f32 DPR:$src),
1034 (f32 (load addrmode6:$addr)), imm:$lane),
1035 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1036 def : Pat<(vector_insert (v4f32 QPR:$src),
1037 (f32 (load addrmode6:$addr)), imm:$lane),
1038 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1040 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1042 // ...with address register writeback:
1043 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1044 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1045 (ins addrmode6:$Rn, am6offset:$Rm,
1046 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1047 "\\{$Vd[$lane]\\}, $Rn$Rm",
1048 "$src = $Vd, $Rn.addr = $wb", []> {
1049 let DecoderMethod = "DecodeVLD1LN";
1052 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1053 let Inst{7-5} = lane{2-0};
1055 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1056 let Inst{7-6} = lane{1-0};
1057 let Inst{4} = Rn{4};
1059 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1060 let Inst{7} = lane{0};
1061 let Inst{5} = Rn{4};
1062 let Inst{4} = Rn{4};
1065 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1066 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1067 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1069 // VLD2LN : Vector Load (single 2-element structure to one lane)
1070 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1071 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1072 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1073 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1074 "$src1 = $Vd, $src2 = $dst2", []> {
1076 let Inst{4} = Rn{4};
1077 let DecoderMethod = "DecodeVLD2LN";
1080 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1081 let Inst{7-5} = lane{2-0};
1083 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1084 let Inst{7-6} = lane{1-0};
1086 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1087 let Inst{7} = lane{0};
1090 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1091 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1092 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1094 // ...with double-spaced registers:
1095 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1096 let Inst{7-6} = lane{1-0};
1098 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1099 let Inst{7} = lane{0};
1102 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1103 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1105 // ...with address register writeback:
1106 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1107 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1108 (ins addrmode6:$Rn, am6offset:$Rm,
1109 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1110 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1111 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1112 let Inst{4} = Rn{4};
1113 let DecoderMethod = "DecodeVLD2LN";
1116 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1117 let Inst{7-5} = lane{2-0};
1119 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1120 let Inst{7-6} = lane{1-0};
1122 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1123 let Inst{7} = lane{0};
1126 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1127 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1128 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1130 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1131 let Inst{7-6} = lane{1-0};
1133 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1134 let Inst{7} = lane{0};
1137 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1138 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1140 // VLD3LN : Vector Load (single 3-element structure to one lane)
1141 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1142 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1143 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1144 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1145 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1146 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1148 let DecoderMethod = "DecodeVLD3LN";
1151 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1152 let Inst{7-5} = lane{2-0};
1154 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1155 let Inst{7-6} = lane{1-0};
1157 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1158 let Inst{7} = lane{0};
1161 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1162 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1163 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1165 // ...with double-spaced registers:
1166 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1167 let Inst{7-6} = lane{1-0};
1169 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1170 let Inst{7} = lane{0};
1173 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1174 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1176 // ...with address register writeback:
1177 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1178 : NLdStLn<1, 0b10, op11_8, op7_4,
1179 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1180 (ins addrmode6:$Rn, am6offset:$Rm,
1181 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1182 IIC_VLD3lnu, "vld3", Dt,
1183 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1184 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1186 let DecoderMethod = "DecodeVLD3LN";
1189 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1190 let Inst{7-5} = lane{2-0};
1192 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1193 let Inst{7-6} = lane{1-0};
1195 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1196 let Inst{7} = lane{0};
1199 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1200 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1201 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1203 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1204 let Inst{7-6} = lane{1-0};
1206 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1207 let Inst{7} = lane{0};
1210 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1211 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1213 // VLD4LN : Vector Load (single 4-element structure to one lane)
1214 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1215 : NLdStLn<1, 0b10, op11_8, op7_4,
1216 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1217 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1218 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1219 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1220 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1222 let Inst{4} = Rn{4};
1223 let DecoderMethod = "DecodeVLD4LN";
1226 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1227 let Inst{7-5} = lane{2-0};
1229 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1230 let Inst{7-6} = lane{1-0};
1232 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1233 let Inst{7} = lane{0};
1234 let Inst{5} = Rn{5};
1237 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1238 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1239 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1241 // ...with double-spaced registers:
1242 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1243 let Inst{7-6} = lane{1-0};
1245 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1246 let Inst{7} = lane{0};
1247 let Inst{5} = Rn{5};
1250 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1251 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1253 // ...with address register writeback:
1254 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1255 : NLdStLn<1, 0b10, op11_8, op7_4,
1256 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1257 (ins addrmode6:$Rn, am6offset:$Rm,
1258 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1259 IIC_VLD4lnu, "vld4", Dt,
1260 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1261 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1263 let Inst{4} = Rn{4};
1264 let DecoderMethod = "DecodeVLD4LN" ;
1267 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1268 let Inst{7-5} = lane{2-0};
1270 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1271 let Inst{7-6} = lane{1-0};
1273 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1274 let Inst{7} = lane{0};
1275 let Inst{5} = Rn{5};
1278 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1279 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1280 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1282 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1283 let Inst{7-6} = lane{1-0};
1285 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1286 let Inst{7} = lane{0};
1287 let Inst{5} = Rn{5};
1290 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1291 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1293 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1295 // VLD1DUP : Vector Load (single element to all lanes)
1296 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1297 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1298 (ins addrmode6dup:$Rn),
1299 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1300 [(set VecListOneDAllLanes:$Vd,
1301 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1303 let Inst{4} = Rn{4};
1304 let DecoderMethod = "DecodeVLD1DupInstruction";
1306 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1307 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1308 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1310 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1311 (VLD1DUPd32 addrmode6:$addr)>;
1313 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1314 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1315 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1316 "vld1", Dt, "$Vd, $Rn", "",
1317 [(set VecListDPairAllLanes:$Vd,
1318 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1320 let Inst{4} = Rn{4};
1321 let DecoderMethod = "DecodeVLD1DupInstruction";
1324 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1325 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1326 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1328 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1329 (VLD1DUPq32 addrmode6:$addr)>;
1331 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1332 // ...with address register writeback:
1333 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1334 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1335 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1336 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1337 "vld1", Dt, "$Vd, $Rn!",
1338 "$Rn.addr = $wb", []> {
1339 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1340 let Inst{4} = Rn{4};
1341 let DecoderMethod = "DecodeVLD1DupInstruction";
1343 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1344 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1345 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1346 "vld1", Dt, "$Vd, $Rn, $Rm",
1347 "$Rn.addr = $wb", []> {
1348 let Inst{4} = Rn{4};
1349 let DecoderMethod = "DecodeVLD1DupInstruction";
1352 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1353 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1354 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1355 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1356 "vld1", Dt, "$Vd, $Rn!",
1357 "$Rn.addr = $wb", []> {
1358 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1359 let Inst{4} = Rn{4};
1360 let DecoderMethod = "DecodeVLD1DupInstruction";
1362 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1363 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1364 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1365 "vld1", Dt, "$Vd, $Rn, $Rm",
1366 "$Rn.addr = $wb", []> {
1367 let Inst{4} = Rn{4};
1368 let DecoderMethod = "DecodeVLD1DupInstruction";
1372 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1373 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1374 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1376 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1377 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1378 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1380 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1381 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1382 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1383 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1384 "vld2", Dt, "$Vd, $Rn", "", []> {
1386 let Inst{4} = Rn{4};
1387 let DecoderMethod = "DecodeVLD2DupInstruction";
1390 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1391 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1392 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1394 // ...with double-spaced registers
1395 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1396 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1397 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1399 // ...with address register writeback:
1400 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1401 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1402 (outs VdTy:$Vd, GPR:$wb),
1403 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1404 "vld2", Dt, "$Vd, $Rn!",
1405 "$Rn.addr = $wb", []> {
1406 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1407 let Inst{4} = Rn{4};
1408 let DecoderMethod = "DecodeVLD2DupInstruction";
1410 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1411 (outs VdTy:$Vd, GPR:$wb),
1412 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1413 "vld2", Dt, "$Vd, $Rn, $Rm",
1414 "$Rn.addr = $wb", []> {
1415 let Inst{4} = Rn{4};
1416 let DecoderMethod = "DecodeVLD2DupInstruction";
1420 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1421 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1422 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1424 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1425 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1426 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1428 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1429 class VLD3DUP<bits<4> op7_4, string Dt>
1430 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1431 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1432 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1435 let DecoderMethod = "DecodeVLD3DupInstruction";
1438 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1439 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1440 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1442 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1443 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1444 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1446 // ...with double-spaced registers (not used for codegen):
1447 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1448 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1449 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1451 // ...with address register writeback:
1452 class VLD3DUPWB<bits<4> op7_4, string Dt>
1453 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1454 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1455 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1456 "$Rn.addr = $wb", []> {
1458 let DecoderMethod = "DecodeVLD3DupInstruction";
1461 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1462 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1463 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1465 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1466 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1467 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1469 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1470 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1471 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1473 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1474 class VLD4DUP<bits<4> op7_4, string Dt>
1475 : NLdSt<1, 0b10, 0b1111, op7_4,
1476 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1477 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1478 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1480 let Inst{4} = Rn{4};
1481 let DecoderMethod = "DecodeVLD4DupInstruction";
1484 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1485 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1486 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1488 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1489 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1490 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1492 // ...with double-spaced registers (not used for codegen):
1493 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1494 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1495 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1497 // ...with address register writeback:
1498 class VLD4DUPWB<bits<4> op7_4, string Dt>
1499 : NLdSt<1, 0b10, 0b1111, op7_4,
1500 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1501 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1502 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1503 "$Rn.addr = $wb", []> {
1504 let Inst{4} = Rn{4};
1505 let DecoderMethod = "DecodeVLD4DupInstruction";
1508 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1509 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1510 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1512 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1513 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1514 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1516 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1517 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1518 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1520 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1522 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1524 // Classes for VST* pseudo-instructions with multi-register operands.
1525 // These are expanded to real instructions after register allocation.
1526 class VSTQPseudo<InstrItinClass itin>
1527 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1528 class VSTQWBPseudo<InstrItinClass itin>
1529 : PseudoNLdSt<(outs GPR:$wb),
1530 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1531 "$addr.addr = $wb">;
1532 class VSTQWBfixedPseudo<InstrItinClass itin>
1533 : PseudoNLdSt<(outs GPR:$wb),
1534 (ins addrmode6:$addr, QPR:$src), itin,
1535 "$addr.addr = $wb">;
1536 class VSTQWBregisterPseudo<InstrItinClass itin>
1537 : PseudoNLdSt<(outs GPR:$wb),
1538 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1539 "$addr.addr = $wb">;
1540 class VSTQQPseudo<InstrItinClass itin>
1541 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1542 class VSTQQWBPseudo<InstrItinClass itin>
1543 : PseudoNLdSt<(outs GPR:$wb),
1544 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1545 "$addr.addr = $wb">;
1546 class VSTQQWBfixedPseudo<InstrItinClass itin>
1547 : PseudoNLdSt<(outs GPR:$wb),
1548 (ins addrmode6:$addr, QQPR:$src), itin,
1549 "$addr.addr = $wb">;
1550 class VSTQQWBregisterPseudo<InstrItinClass itin>
1551 : PseudoNLdSt<(outs GPR:$wb),
1552 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1553 "$addr.addr = $wb">;
1555 class VSTQQQQPseudo<InstrItinClass itin>
1556 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1557 class VSTQQQQWBPseudo<InstrItinClass itin>
1558 : PseudoNLdSt<(outs GPR:$wb),
1559 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1560 "$addr.addr = $wb">;
1562 // VST1 : Vector Store (multiple single elements)
1563 class VST1D<bits<4> op7_4, string Dt>
1564 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1565 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1567 let Inst{4} = Rn{4};
1568 let DecoderMethod = "DecodeVLDST1Instruction";
1570 class VST1Q<bits<4> op7_4, string Dt>
1571 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1572 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1574 let Inst{5-4} = Rn{5-4};
1575 let DecoderMethod = "DecodeVLDST1Instruction";
1578 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1579 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1580 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1581 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1583 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1584 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1585 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1586 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1588 // ...with address register writeback:
1589 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1590 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1591 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1592 "vst1", Dt, "$Vd, $Rn!",
1593 "$Rn.addr = $wb", []> {
1594 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1595 let Inst{4} = Rn{4};
1596 let DecoderMethod = "DecodeVLDST1Instruction";
1598 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1599 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1601 "vst1", Dt, "$Vd, $Rn, $Rm",
1602 "$Rn.addr = $wb", []> {
1603 let Inst{4} = Rn{4};
1604 let DecoderMethod = "DecodeVLDST1Instruction";
1607 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1608 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1609 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1610 "vst1", Dt, "$Vd, $Rn!",
1611 "$Rn.addr = $wb", []> {
1612 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1613 let Inst{5-4} = Rn{5-4};
1614 let DecoderMethod = "DecodeVLDST1Instruction";
1616 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1617 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1619 "vst1", Dt, "$Vd, $Rn, $Rm",
1620 "$Rn.addr = $wb", []> {
1621 let Inst{5-4} = Rn{5-4};
1622 let DecoderMethod = "DecodeVLDST1Instruction";
1626 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1627 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1628 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1629 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1631 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1632 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1633 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1634 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1636 // ...with 3 registers
1637 class VST1D3<bits<4> op7_4, string Dt>
1638 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1639 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1640 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1642 let Inst{4} = Rn{4};
1643 let DecoderMethod = "DecodeVLDST1Instruction";
1645 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1646 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1647 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1648 "vst1", Dt, "$Vd, $Rn!",
1649 "$Rn.addr = $wb", []> {
1650 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1651 let Inst{5-4} = Rn{5-4};
1652 let DecoderMethod = "DecodeVLDST1Instruction";
1654 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1655 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1657 "vst1", Dt, "$Vd, $Rn, $Rm",
1658 "$Rn.addr = $wb", []> {
1659 let Inst{5-4} = Rn{5-4};
1660 let DecoderMethod = "DecodeVLDST1Instruction";
1664 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1665 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1666 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1667 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1669 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1670 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1671 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1672 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1674 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1675 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1676 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1678 // ...with 4 registers
1679 class VST1D4<bits<4> op7_4, string Dt>
1680 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1681 (ins addrmode6:$Rn, VecListFourD:$Vd),
1682 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1685 let Inst{5-4} = Rn{5-4};
1686 let DecoderMethod = "DecodeVLDST1Instruction";
1688 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1689 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1690 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1691 "vst1", Dt, "$Vd, $Rn!",
1692 "$Rn.addr = $wb", []> {
1693 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1694 let Inst{5-4} = Rn{5-4};
1695 let DecoderMethod = "DecodeVLDST1Instruction";
1697 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1698 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1700 "vst1", Dt, "$Vd, $Rn, $Rm",
1701 "$Rn.addr = $wb", []> {
1702 let Inst{5-4} = Rn{5-4};
1703 let DecoderMethod = "DecodeVLDST1Instruction";
1707 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1708 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1709 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1710 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1712 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1713 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1714 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1715 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1717 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1718 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1719 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1721 // VST2 : Vector Store (multiple 2-element structures)
1722 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1723 InstrItinClass itin>
1724 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1725 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1727 let Inst{5-4} = Rn{5-4};
1728 let DecoderMethod = "DecodeVLDST2Instruction";
1731 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1732 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1733 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1735 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1736 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1737 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1739 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1740 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1741 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1743 // ...with address register writeback:
1744 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1745 RegisterOperand VdTy> {
1746 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1747 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1748 "vst2", Dt, "$Vd, $Rn!",
1749 "$Rn.addr = $wb", []> {
1750 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1751 let Inst{5-4} = Rn{5-4};
1752 let DecoderMethod = "DecodeVLDST2Instruction";
1754 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1755 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1756 "vst2", Dt, "$Vd, $Rn, $Rm",
1757 "$Rn.addr = $wb", []> {
1758 let Inst{5-4} = Rn{5-4};
1759 let DecoderMethod = "DecodeVLDST2Instruction";
1762 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1763 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1764 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1765 "vst2", Dt, "$Vd, $Rn!",
1766 "$Rn.addr = $wb", []> {
1767 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1768 let Inst{5-4} = Rn{5-4};
1769 let DecoderMethod = "DecodeVLDST2Instruction";
1771 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1772 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1774 "vst2", Dt, "$Vd, $Rn, $Rm",
1775 "$Rn.addr = $wb", []> {
1776 let Inst{5-4} = Rn{5-4};
1777 let DecoderMethod = "DecodeVLDST2Instruction";
1781 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1782 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1783 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1785 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1786 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1787 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1789 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1790 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1791 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1792 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1793 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1794 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1796 // ...with double-spaced registers
1797 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1798 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1799 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1800 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1801 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1802 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1804 // VST3 : Vector Store (multiple 3-element structures)
1805 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1806 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1807 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1808 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1810 let Inst{4} = Rn{4};
1811 let DecoderMethod = "DecodeVLDST3Instruction";
1814 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1815 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1816 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1818 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1819 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1820 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1822 // ...with address register writeback:
1823 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1824 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1825 (ins addrmode6:$Rn, am6offset:$Rm,
1826 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1827 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1828 "$Rn.addr = $wb", []> {
1829 let Inst{4} = Rn{4};
1830 let DecoderMethod = "DecodeVLDST3Instruction";
1833 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1834 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1835 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1837 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1838 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1839 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1841 // ...with double-spaced registers:
1842 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1843 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1844 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1845 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1846 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1847 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1849 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1850 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1851 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1853 // ...alternate versions to be allocated odd register numbers:
1854 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1855 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1856 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1858 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1859 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1860 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1862 // VST4 : Vector Store (multiple 4-element structures)
1863 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1864 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1865 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1866 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1869 let Inst{5-4} = Rn{5-4};
1870 let DecoderMethod = "DecodeVLDST4Instruction";
1873 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1874 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1875 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1877 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1878 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1879 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1881 // ...with address register writeback:
1882 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1883 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1884 (ins addrmode6:$Rn, am6offset:$Rm,
1885 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1886 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1887 "$Rn.addr = $wb", []> {
1888 let Inst{5-4} = Rn{5-4};
1889 let DecoderMethod = "DecodeVLDST4Instruction";
1892 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1893 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1894 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1896 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1897 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1898 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1900 // ...with double-spaced registers:
1901 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1902 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1903 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1904 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1905 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1906 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1908 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1909 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1910 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1912 // ...alternate versions to be allocated odd register numbers:
1913 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1914 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1915 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1917 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1918 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1919 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1921 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1923 // Classes for VST*LN pseudo-instructions with multi-register operands.
1924 // These are expanded to real instructions after register allocation.
1925 class VSTQLNPseudo<InstrItinClass itin>
1926 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1928 class VSTQLNWBPseudo<InstrItinClass itin>
1929 : PseudoNLdSt<(outs GPR:$wb),
1930 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1931 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1932 class VSTQQLNPseudo<InstrItinClass itin>
1933 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1935 class VSTQQLNWBPseudo<InstrItinClass itin>
1936 : PseudoNLdSt<(outs GPR:$wb),
1937 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1938 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1939 class VSTQQQQLNPseudo<InstrItinClass itin>
1940 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1942 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1943 : PseudoNLdSt<(outs GPR:$wb),
1944 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1945 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1947 // VST1LN : Vector Store (single element from one lane)
1948 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1949 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
1950 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1951 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
1952 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1953 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
1955 let DecoderMethod = "DecodeVST1LN";
1957 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1958 : VSTQLNPseudo<IIC_VST1ln> {
1959 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1963 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1964 NEONvgetlaneu, addrmode6> {
1965 let Inst{7-5} = lane{2-0};
1967 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1968 NEONvgetlaneu, addrmode6> {
1969 let Inst{7-6} = lane{1-0};
1970 let Inst{4} = Rn{4};
1973 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
1975 let Inst{7} = lane{0};
1976 let Inst{5-4} = Rn{5-4};
1979 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1980 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1981 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1983 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1984 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1985 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1986 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1988 // ...with address register writeback:
1989 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1990 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
1991 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1992 (ins AdrMode:$Rn, am6offset:$Rm,
1993 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1994 "\\{$Vd[$lane]\\}, $Rn$Rm",
1996 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1997 AdrMode:$Rn, am6offset:$Rm))]> {
1998 let DecoderMethod = "DecodeVST1LN";
2000 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2001 : VSTQLNWBPseudo<IIC_VST1lnu> {
2002 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2003 addrmode6:$addr, am6offset:$offset))];
2006 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2007 NEONvgetlaneu, addrmode6> {
2008 let Inst{7-5} = lane{2-0};
2010 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2011 NEONvgetlaneu, addrmode6> {
2012 let Inst{7-6} = lane{1-0};
2013 let Inst{4} = Rn{4};
2015 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2016 extractelt, addrmode6oneL32> {
2017 let Inst{7} = lane{0};
2018 let Inst{5-4} = Rn{5-4};
2021 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2022 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2023 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2025 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2027 // VST2LN : Vector Store (single 2-element structure from one lane)
2028 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2029 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2030 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2031 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2034 let Inst{4} = Rn{4};
2035 let DecoderMethod = "DecodeVST2LN";
2038 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2039 let Inst{7-5} = lane{2-0};
2041 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2042 let Inst{7-6} = lane{1-0};
2044 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2045 let Inst{7} = lane{0};
2048 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2049 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2050 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2052 // ...with double-spaced registers:
2053 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2054 let Inst{7-6} = lane{1-0};
2055 let Inst{4} = Rn{4};
2057 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2058 let Inst{7} = lane{0};
2059 let Inst{4} = Rn{4};
2062 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2063 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2065 // ...with address register writeback:
2066 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2067 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2068 (ins addrmode6:$Rn, am6offset:$Rm,
2069 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2070 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2071 "$Rn.addr = $wb", []> {
2072 let Inst{4} = Rn{4};
2073 let DecoderMethod = "DecodeVST2LN";
2076 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2077 let Inst{7-5} = lane{2-0};
2079 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2080 let Inst{7-6} = lane{1-0};
2082 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2083 let Inst{7} = lane{0};
2086 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2087 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2088 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2090 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2091 let Inst{7-6} = lane{1-0};
2093 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2094 let Inst{7} = lane{0};
2097 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2098 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2100 // VST3LN : Vector Store (single 3-element structure from one lane)
2101 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2102 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2103 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2104 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2105 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2107 let DecoderMethod = "DecodeVST3LN";
2110 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2111 let Inst{7-5} = lane{2-0};
2113 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2114 let Inst{7-6} = lane{1-0};
2116 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2117 let Inst{7} = lane{0};
2120 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2121 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2122 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2124 // ...with double-spaced registers:
2125 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2126 let Inst{7-6} = lane{1-0};
2128 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2129 let Inst{7} = lane{0};
2132 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2133 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2135 // ...with address register writeback:
2136 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2137 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2138 (ins addrmode6:$Rn, am6offset:$Rm,
2139 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2140 IIC_VST3lnu, "vst3", Dt,
2141 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2142 "$Rn.addr = $wb", []> {
2143 let DecoderMethod = "DecodeVST3LN";
2146 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2147 let Inst{7-5} = lane{2-0};
2149 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2150 let Inst{7-6} = lane{1-0};
2152 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2153 let Inst{7} = lane{0};
2156 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2157 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2158 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2160 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2161 let Inst{7-6} = lane{1-0};
2163 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2164 let Inst{7} = lane{0};
2167 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2168 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2170 // VST4LN : Vector Store (single 4-element structure from one lane)
2171 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2172 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2173 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2174 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2175 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2178 let Inst{4} = Rn{4};
2179 let DecoderMethod = "DecodeVST4LN";
2182 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2183 let Inst{7-5} = lane{2-0};
2185 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2186 let Inst{7-6} = lane{1-0};
2188 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2189 let Inst{7} = lane{0};
2190 let Inst{5} = Rn{5};
2193 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2194 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2195 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2197 // ...with double-spaced registers:
2198 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2199 let Inst{7-6} = lane{1-0};
2201 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2202 let Inst{7} = lane{0};
2203 let Inst{5} = Rn{5};
2206 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2207 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2209 // ...with address register writeback:
2210 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2211 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2212 (ins addrmode6:$Rn, am6offset:$Rm,
2213 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2214 IIC_VST4lnu, "vst4", Dt,
2215 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2216 "$Rn.addr = $wb", []> {
2217 let Inst{4} = Rn{4};
2218 let DecoderMethod = "DecodeVST4LN";
2221 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2222 let Inst{7-5} = lane{2-0};
2224 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2225 let Inst{7-6} = lane{1-0};
2227 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2228 let Inst{7} = lane{0};
2229 let Inst{5} = Rn{5};
2232 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2233 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2234 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2236 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2237 let Inst{7-6} = lane{1-0};
2239 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2240 let Inst{7} = lane{0};
2241 let Inst{5} = Rn{5};
2244 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2245 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2247 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2249 // Use vld1/vst1 for unaligned f64 load / store
2250 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2251 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2252 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2253 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2254 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2255 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2256 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2257 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2258 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2259 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2260 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2261 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2263 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2264 // load / store if it's legal.
2265 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2266 (VLD1q64 addrmode6:$addr)>;
2267 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2268 (VST1q64 addrmode6:$addr, QPR:$value)>;
2269 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2270 (VLD1q32 addrmode6:$addr)>;
2271 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2272 (VST1q32 addrmode6:$addr, QPR:$value)>;
2273 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2274 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2275 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2276 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2277 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2278 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2279 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2280 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2282 //===----------------------------------------------------------------------===//
2283 // NEON pattern fragments
2284 //===----------------------------------------------------------------------===//
2286 // Extract D sub-registers of Q registers.
2287 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2288 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2289 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2291 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2292 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2293 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2295 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2296 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2297 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2299 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2300 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2301 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2304 // Extract S sub-registers of Q/D registers.
2305 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2306 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2307 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2310 // Translate lane numbers from Q registers to D subregs.
2311 def SubReg_i8_lane : SDNodeXForm<imm, [{
2312 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2314 def SubReg_i16_lane : SDNodeXForm<imm, [{
2315 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2317 def SubReg_i32_lane : SDNodeXForm<imm, [{
2318 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2321 //===----------------------------------------------------------------------===//
2322 // Instruction Classes
2323 //===----------------------------------------------------------------------===//
2325 // Basic 2-register operations: double- and quad-register.
2326 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2327 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2328 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2329 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2330 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2331 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2332 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2333 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2334 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2335 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2336 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2337 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2339 // Basic 2-register intrinsics, both double- and quad-register.
2340 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2341 bits<2> op17_16, bits<5> op11_7, bit op4,
2342 InstrItinClass itin, string OpcodeStr, string Dt,
2343 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2344 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2345 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2346 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2347 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2348 bits<2> op17_16, bits<5> op11_7, bit op4,
2349 InstrItinClass itin, string OpcodeStr, string Dt,
2350 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2351 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2352 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2353 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2355 // Same as above, but not predicated.
2356 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2357 InstrItinClass itin, string OpcodeStr, string Dt,
2358 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2359 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2360 itin, OpcodeStr, Dt, ResTy, OpTy,
2361 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2363 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2364 InstrItinClass itin, string OpcodeStr, string Dt,
2365 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2366 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2367 itin, OpcodeStr, Dt, ResTy, OpTy,
2368 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2370 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2371 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2372 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2373 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2374 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2375 itin, OpcodeStr, Dt, ResTy, OpTy,
2376 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2378 // Same as N2VQIntXnp but with Vd as a src register.
2379 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2380 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2381 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2382 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2383 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2384 itin, OpcodeStr, Dt, ResTy, OpTy,
2385 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2386 let Constraints = "$src = $Vd";
2389 // Narrow 2-register operations.
2390 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2391 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2392 InstrItinClass itin, string OpcodeStr, string Dt,
2393 ValueType TyD, ValueType TyQ, SDNode OpNode>
2394 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2395 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2396 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2398 // Narrow 2-register intrinsics.
2399 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2400 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2401 InstrItinClass itin, string OpcodeStr, string Dt,
2402 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2403 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2404 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2405 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2407 // Long 2-register operations (currently only used for VMOVL).
2408 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2409 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2410 InstrItinClass itin, string OpcodeStr, string Dt,
2411 ValueType TyQ, ValueType TyD, SDNode OpNode>
2412 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2413 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2414 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2416 // Long 2-register intrinsics.
2417 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2418 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2419 InstrItinClass itin, string OpcodeStr, string Dt,
2420 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2421 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2422 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2423 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2425 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2426 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2427 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2428 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2429 OpcodeStr, Dt, "$Vd, $Vm",
2430 "$src1 = $Vd, $src2 = $Vm", []>;
2431 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2432 InstrItinClass itin, string OpcodeStr, string Dt>
2433 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2434 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2435 "$src1 = $Vd, $src2 = $Vm", []>;
2437 // Basic 3-register operations: double- and quad-register.
2438 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2439 InstrItinClass itin, string OpcodeStr, string Dt,
2440 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2441 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2442 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2443 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2444 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2445 // All of these have a two-operand InstAlias.
2446 let TwoOperandAliasConstraint = "$Vn = $Vd";
2447 let isCommutable = Commutable;
2449 // Same as N3VD but no data type.
2450 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2451 InstrItinClass itin, string OpcodeStr,
2452 ValueType ResTy, ValueType OpTy,
2453 SDNode OpNode, bit Commutable>
2454 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2455 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2456 OpcodeStr, "$Vd, $Vn, $Vm", "",
2457 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2458 // All of these have a two-operand InstAlias.
2459 let TwoOperandAliasConstraint = "$Vn = $Vd";
2460 let isCommutable = Commutable;
2463 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2464 InstrItinClass itin, string OpcodeStr, string Dt,
2465 ValueType Ty, SDNode ShOp>
2466 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2467 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2468 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2470 (Ty (ShOp (Ty DPR:$Vn),
2471 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2472 // All of these have a two-operand InstAlias.
2473 let TwoOperandAliasConstraint = "$Vn = $Vd";
2474 let isCommutable = 0;
2476 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2477 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2478 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2479 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2480 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2482 (Ty (ShOp (Ty DPR:$Vn),
2483 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2484 // All of these have a two-operand InstAlias.
2485 let TwoOperandAliasConstraint = "$Vn = $Vd";
2486 let isCommutable = 0;
2489 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2490 InstrItinClass itin, string OpcodeStr, string Dt,
2491 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2492 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2493 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2494 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2495 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2496 // All of these have a two-operand InstAlias.
2497 let TwoOperandAliasConstraint = "$Vn = $Vd";
2498 let isCommutable = Commutable;
2500 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2501 InstrItinClass itin, string OpcodeStr,
2502 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2503 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2504 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2505 OpcodeStr, "$Vd, $Vn, $Vm", "",
2506 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2507 // All of these have a two-operand InstAlias.
2508 let TwoOperandAliasConstraint = "$Vn = $Vd";
2509 let isCommutable = Commutable;
2511 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2512 InstrItinClass itin, string OpcodeStr, string Dt,
2513 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2514 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2515 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2516 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2517 [(set (ResTy QPR:$Vd),
2518 (ResTy (ShOp (ResTy QPR:$Vn),
2519 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2521 // All of these have a two-operand InstAlias.
2522 let TwoOperandAliasConstraint = "$Vn = $Vd";
2523 let isCommutable = 0;
2525 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2526 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2527 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2528 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2529 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2530 [(set (ResTy QPR:$Vd),
2531 (ResTy (ShOp (ResTy QPR:$Vn),
2532 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2534 // All of these have a two-operand InstAlias.
2535 let TwoOperandAliasConstraint = "$Vn = $Vd";
2536 let isCommutable = 0;
2539 // Basic 3-register intrinsics, both double- and quad-register.
2540 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2541 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2542 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2543 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2544 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2545 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2546 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2547 // All of these have a two-operand InstAlias.
2548 let TwoOperandAliasConstraint = "$Vn = $Vd";
2549 let isCommutable = Commutable;
2552 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2553 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2554 string Dt, ValueType ResTy, ValueType OpTy,
2555 SDPatternOperator IntOp, bit Commutable>
2556 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2557 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2558 ResTy, OpTy, IntOp, Commutable,
2559 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2561 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2562 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2563 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2564 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2565 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2567 (Ty (IntOp (Ty DPR:$Vn),
2568 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2570 let isCommutable = 0;
2573 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2574 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2575 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2576 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2577 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2579 (Ty (IntOp (Ty DPR:$Vn),
2580 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2581 let isCommutable = 0;
2583 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2584 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2585 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2586 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2587 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2588 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2589 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2590 let TwoOperandAliasConstraint = "$Vm = $Vd";
2591 let isCommutable = 0;
2594 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2595 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2596 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2597 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2598 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2599 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2600 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2601 // All of these have a two-operand InstAlias.
2602 let TwoOperandAliasConstraint = "$Vn = $Vd";
2603 let isCommutable = Commutable;
2606 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2607 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2608 string Dt, ValueType ResTy, ValueType OpTy,
2609 SDPatternOperator IntOp, bit Commutable>
2610 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2611 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2612 ResTy, OpTy, IntOp, Commutable,
2613 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2615 // Same as N3VQIntnp but with Vd as a src register.
2616 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2617 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2618 string Dt, ValueType ResTy, ValueType OpTy,
2619 SDPatternOperator IntOp, bit Commutable>
2620 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2621 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2622 Dt, ResTy, OpTy, IntOp, Commutable,
2623 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2624 (OpTy QPR:$Vm))))]> {
2625 let Constraints = "$src = $Vd";
2628 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2629 string OpcodeStr, string Dt,
2630 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2631 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2632 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2633 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2634 [(set (ResTy QPR:$Vd),
2635 (ResTy (IntOp (ResTy QPR:$Vn),
2636 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2638 let isCommutable = 0;
2640 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2641 string OpcodeStr, string Dt,
2642 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2643 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2644 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2645 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2646 [(set (ResTy QPR:$Vd),
2647 (ResTy (IntOp (ResTy QPR:$Vn),
2648 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2650 let isCommutable = 0;
2652 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2653 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2654 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2655 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2656 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2657 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2658 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2659 let TwoOperandAliasConstraint = "$Vm = $Vd";
2660 let isCommutable = 0;
2663 // Multiply-Add/Sub operations: double- and quad-register.
2664 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2665 InstrItinClass itin, string OpcodeStr, string Dt,
2666 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2667 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2668 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2669 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2670 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2671 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2673 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2674 string OpcodeStr, string Dt,
2675 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2676 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2678 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2680 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2682 (Ty (ShOp (Ty DPR:$src1),
2684 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2686 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2687 string OpcodeStr, string Dt,
2688 ValueType Ty, SDNode MulOp, SDNode ShOp>
2689 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2691 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2693 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2695 (Ty (ShOp (Ty DPR:$src1),
2697 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2700 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2701 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2702 SDPatternOperator MulOp, SDPatternOperator OpNode>
2703 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2704 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2705 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2706 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2707 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2708 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2709 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2710 SDPatternOperator MulOp, SDPatternOperator ShOp>
2711 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2713 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2715 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2716 [(set (ResTy QPR:$Vd),
2717 (ResTy (ShOp (ResTy QPR:$src1),
2718 (ResTy (MulOp QPR:$Vn,
2719 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2721 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2722 string OpcodeStr, string Dt,
2723 ValueType ResTy, ValueType OpTy,
2724 SDNode MulOp, SDNode ShOp>
2725 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2727 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2729 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2730 [(set (ResTy QPR:$Vd),
2731 (ResTy (ShOp (ResTy QPR:$src1),
2732 (ResTy (MulOp QPR:$Vn,
2733 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2736 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2737 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2738 InstrItinClass itin, string OpcodeStr, string Dt,
2739 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2740 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2741 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2742 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2743 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2744 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2745 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2746 InstrItinClass itin, string OpcodeStr, string Dt,
2747 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2748 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2749 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2750 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2751 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2752 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2754 // Neon 3-argument intrinsics, both double- and quad-register.
2755 // The destination register is also used as the first source operand register.
2756 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2757 InstrItinClass itin, string OpcodeStr, string Dt,
2758 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2759 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2760 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2761 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2762 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2763 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2764 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2765 InstrItinClass itin, string OpcodeStr, string Dt,
2766 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2767 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2768 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2769 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2770 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2771 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2773 // Long Multiply-Add/Sub operations.
2774 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2775 InstrItinClass itin, string OpcodeStr, string Dt,
2776 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2777 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2778 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2779 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2780 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2781 (TyQ (MulOp (TyD DPR:$Vn),
2782 (TyD DPR:$Vm)))))]>;
2783 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2784 InstrItinClass itin, string OpcodeStr, string Dt,
2785 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2786 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2787 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2789 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2791 (OpNode (TyQ QPR:$src1),
2792 (TyQ (MulOp (TyD DPR:$Vn),
2793 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2795 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2796 InstrItinClass itin, string OpcodeStr, string Dt,
2797 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2798 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2799 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2801 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2803 (OpNode (TyQ QPR:$src1),
2804 (TyQ (MulOp (TyD DPR:$Vn),
2805 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2808 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2809 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2810 InstrItinClass itin, string OpcodeStr, string Dt,
2811 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2813 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2814 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2815 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2816 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2817 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2818 (TyD DPR:$Vm)))))))]>;
2820 // Neon Long 3-argument intrinsic. The destination register is
2821 // a quad-register and is also used as the first source operand register.
2822 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2823 InstrItinClass itin, string OpcodeStr, string Dt,
2824 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2825 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2826 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2827 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2829 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2830 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2831 string OpcodeStr, string Dt,
2832 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2833 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2835 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2837 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2838 [(set (ResTy QPR:$Vd),
2839 (ResTy (IntOp (ResTy QPR:$src1),
2841 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2843 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2844 InstrItinClass itin, string OpcodeStr, string Dt,
2845 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2846 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2848 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2850 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2851 [(set (ResTy QPR:$Vd),
2852 (ResTy (IntOp (ResTy QPR:$src1),
2854 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2857 // Narrowing 3-register intrinsics.
2858 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2859 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2860 SDPatternOperator IntOp, bit Commutable>
2861 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2862 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2863 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2864 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2865 let isCommutable = Commutable;
2868 // Long 3-register operations.
2869 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2870 InstrItinClass itin, string OpcodeStr, string Dt,
2871 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2872 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2873 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2874 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2875 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2876 let isCommutable = Commutable;
2879 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2880 InstrItinClass itin, string OpcodeStr, string Dt,
2881 ValueType TyQ, ValueType TyD, SDNode OpNode>
2882 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2883 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2884 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2886 (TyQ (OpNode (TyD DPR:$Vn),
2887 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2888 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2889 InstrItinClass itin, string OpcodeStr, string Dt,
2890 ValueType TyQ, ValueType TyD, SDNode OpNode>
2891 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2892 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2893 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2895 (TyQ (OpNode (TyD DPR:$Vn),
2896 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2898 // Long 3-register operations with explicitly extended operands.
2899 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2900 InstrItinClass itin, string OpcodeStr, string Dt,
2901 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2903 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2904 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2905 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2906 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2907 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2908 let isCommutable = Commutable;
2911 // Long 3-register intrinsics with explicit extend (VABDL).
2912 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2913 InstrItinClass itin, string OpcodeStr, string Dt,
2914 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2916 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2917 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2918 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2919 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2920 (TyD DPR:$Vm))))))]> {
2921 let isCommutable = Commutable;
2924 // Long 3-register intrinsics.
2925 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2926 InstrItinClass itin, string OpcodeStr, string Dt,
2927 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
2928 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2929 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2930 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2931 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2932 let isCommutable = Commutable;
2935 // Same as above, but not predicated.
2936 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2937 bit op4, InstrItinClass itin, string OpcodeStr,
2938 string Dt, ValueType ResTy, ValueType OpTy,
2939 SDPatternOperator IntOp, bit Commutable>
2940 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2941 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2942 ResTy, OpTy, IntOp, Commutable,
2943 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2945 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2946 string OpcodeStr, string Dt,
2947 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2948 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2949 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2950 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2951 [(set (ResTy QPR:$Vd),
2952 (ResTy (IntOp (OpTy DPR:$Vn),
2953 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2955 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2956 InstrItinClass itin, string OpcodeStr, string Dt,
2957 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2958 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2959 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2960 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2961 [(set (ResTy QPR:$Vd),
2962 (ResTy (IntOp (OpTy DPR:$Vn),
2963 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2966 // Wide 3-register operations.
2967 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2968 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2969 SDNode OpNode, SDNode ExtOp, bit Commutable>
2970 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2971 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2972 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2973 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2974 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2975 // All of these have a two-operand InstAlias.
2976 let TwoOperandAliasConstraint = "$Vn = $Vd";
2977 let isCommutable = Commutable;
2980 // Pairwise long 2-register intrinsics, both double- and quad-register.
2981 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2982 bits<2> op17_16, bits<5> op11_7, bit op4,
2983 string OpcodeStr, string Dt,
2984 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2985 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2986 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2987 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2988 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2989 bits<2> op17_16, bits<5> op11_7, bit op4,
2990 string OpcodeStr, string Dt,
2991 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2992 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2993 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2994 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2996 // Pairwise long 2-register accumulate intrinsics,
2997 // both double- and quad-register.
2998 // The destination register is also used as the first source operand register.
2999 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3000 bits<2> op17_16, bits<5> op11_7, bit op4,
3001 string OpcodeStr, string Dt,
3002 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3003 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3004 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3005 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3006 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3007 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3008 bits<2> op17_16, bits<5> op11_7, bit op4,
3009 string OpcodeStr, string Dt,
3010 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3011 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3012 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3013 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3014 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3016 // Shift by immediate,
3017 // both double- and quad-register.
3018 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3019 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3020 Format f, InstrItinClass itin, Operand ImmTy,
3021 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3022 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3023 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3024 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3025 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3026 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3027 Format f, InstrItinClass itin, Operand ImmTy,
3028 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3029 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3030 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3031 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3032 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3035 // Long shift by immediate.
3036 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3037 string OpcodeStr, string Dt,
3038 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3039 SDPatternOperator OpNode>
3040 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3041 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3042 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3043 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3045 // Narrow shift by immediate.
3046 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3047 InstrItinClass itin, string OpcodeStr, string Dt,
3048 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3049 SDPatternOperator OpNode>
3050 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3051 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3052 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3053 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3054 (i32 ImmTy:$SIMM))))]>;
3056 // Shift right by immediate and accumulate,
3057 // both double- and quad-register.
3058 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3059 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3060 Operand ImmTy, string OpcodeStr, string Dt,
3061 ValueType Ty, SDNode ShOp>
3062 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3063 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3064 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3065 [(set DPR:$Vd, (Ty (add DPR:$src1,
3066 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3067 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3068 Operand ImmTy, string OpcodeStr, string Dt,
3069 ValueType Ty, SDNode ShOp>
3070 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3071 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3072 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3073 [(set QPR:$Vd, (Ty (add QPR:$src1,
3074 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3077 // Shift by immediate and insert,
3078 // both double- and quad-register.
3079 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3080 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3081 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3082 ValueType Ty,SDNode ShOp>
3083 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3084 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3085 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3086 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3087 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3088 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3089 ValueType Ty,SDNode ShOp>
3090 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3091 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3092 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3093 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3096 // Convert, with fractional bits immediate,
3097 // both double- and quad-register.
3098 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3099 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3100 SDPatternOperator IntOp>
3101 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3102 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3103 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3104 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3105 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3106 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3107 SDPatternOperator IntOp>
3108 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3109 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3110 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3111 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3113 //===----------------------------------------------------------------------===//
3115 //===----------------------------------------------------------------------===//
3117 // Abbreviations used in multiclass suffixes:
3118 // Q = quarter int (8 bit) elements
3119 // H = half int (16 bit) elements
3120 // S = single int (32 bit) elements
3121 // D = double int (64 bit) elements
3123 // Neon 2-register vector operations and intrinsics.
3125 // Neon 2-register comparisons.
3126 // source operand element sizes of 8, 16 and 32 bits:
3127 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3128 bits<5> op11_7, bit op4, string opc, string Dt,
3129 string asm, SDNode OpNode> {
3130 // 64-bit vector types.
3131 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3132 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3133 opc, !strconcat(Dt, "8"), asm, "",
3134 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3135 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3136 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3137 opc, !strconcat(Dt, "16"), asm, "",
3138 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3139 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3140 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3141 opc, !strconcat(Dt, "32"), asm, "",
3142 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3143 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3144 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3145 opc, "f32", asm, "",
3146 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3147 let Inst{10} = 1; // overwrite F = 1
3150 // 128-bit vector types.
3151 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3152 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3153 opc, !strconcat(Dt, "8"), asm, "",
3154 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3155 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3156 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3157 opc, !strconcat(Dt, "16"), asm, "",
3158 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3159 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3160 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3161 opc, !strconcat(Dt, "32"), asm, "",
3162 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3163 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3164 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3165 opc, "f32", asm, "",
3166 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3167 let Inst{10} = 1; // overwrite F = 1
3172 // Neon 2-register vector intrinsics,
3173 // element sizes of 8, 16 and 32 bits:
3174 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3175 bits<5> op11_7, bit op4,
3176 InstrItinClass itinD, InstrItinClass itinQ,
3177 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3178 // 64-bit vector types.
3179 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3180 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3181 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3182 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3183 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3184 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3186 // 128-bit vector types.
3187 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3188 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3189 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3190 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3191 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3192 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3196 // Neon Narrowing 2-register vector operations,
3197 // source operand element sizes of 16, 32 and 64 bits:
3198 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3199 bits<5> op11_7, bit op6, bit op4,
3200 InstrItinClass itin, string OpcodeStr, string Dt,
3202 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3203 itin, OpcodeStr, !strconcat(Dt, "16"),
3204 v8i8, v8i16, OpNode>;
3205 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3206 itin, OpcodeStr, !strconcat(Dt, "32"),
3207 v4i16, v4i32, OpNode>;
3208 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3209 itin, OpcodeStr, !strconcat(Dt, "64"),
3210 v2i32, v2i64, OpNode>;
3213 // Neon Narrowing 2-register vector intrinsics,
3214 // source operand element sizes of 16, 32 and 64 bits:
3215 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3216 bits<5> op11_7, bit op6, bit op4,
3217 InstrItinClass itin, string OpcodeStr, string Dt,
3218 SDPatternOperator IntOp> {
3219 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3220 itin, OpcodeStr, !strconcat(Dt, "16"),
3221 v8i8, v8i16, IntOp>;
3222 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3223 itin, OpcodeStr, !strconcat(Dt, "32"),
3224 v4i16, v4i32, IntOp>;
3225 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3226 itin, OpcodeStr, !strconcat(Dt, "64"),
3227 v2i32, v2i64, IntOp>;
3231 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3232 // source operand element sizes of 16, 32 and 64 bits:
3233 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3234 string OpcodeStr, string Dt, SDNode OpNode> {
3235 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3236 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3237 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3238 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3239 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3240 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3244 // Neon 3-register vector operations.
3246 // First with only element sizes of 8, 16 and 32 bits:
3247 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3248 InstrItinClass itinD16, InstrItinClass itinD32,
3249 InstrItinClass itinQ16, InstrItinClass itinQ32,
3250 string OpcodeStr, string Dt,
3251 SDNode OpNode, bit Commutable = 0> {
3252 // 64-bit vector types.
3253 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3254 OpcodeStr, !strconcat(Dt, "8"),
3255 v8i8, v8i8, OpNode, Commutable>;
3256 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3257 OpcodeStr, !strconcat(Dt, "16"),
3258 v4i16, v4i16, OpNode, Commutable>;
3259 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3260 OpcodeStr, !strconcat(Dt, "32"),
3261 v2i32, v2i32, OpNode, Commutable>;
3263 // 128-bit vector types.
3264 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3265 OpcodeStr, !strconcat(Dt, "8"),
3266 v16i8, v16i8, OpNode, Commutable>;
3267 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3268 OpcodeStr, !strconcat(Dt, "16"),
3269 v8i16, v8i16, OpNode, Commutable>;
3270 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3271 OpcodeStr, !strconcat(Dt, "32"),
3272 v4i32, v4i32, OpNode, Commutable>;
3275 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3276 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3277 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3278 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3279 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3280 v4i32, v2i32, ShOp>;
3283 // ....then also with element size 64 bits:
3284 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3285 InstrItinClass itinD, InstrItinClass itinQ,
3286 string OpcodeStr, string Dt,
3287 SDNode OpNode, bit Commutable = 0>
3288 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3289 OpcodeStr, Dt, OpNode, Commutable> {
3290 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3291 OpcodeStr, !strconcat(Dt, "64"),
3292 v1i64, v1i64, OpNode, Commutable>;
3293 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3294 OpcodeStr, !strconcat(Dt, "64"),
3295 v2i64, v2i64, OpNode, Commutable>;
3299 // Neon 3-register vector intrinsics.
3301 // First with only element sizes of 16 and 32 bits:
3302 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3303 InstrItinClass itinD16, InstrItinClass itinD32,
3304 InstrItinClass itinQ16, InstrItinClass itinQ32,
3305 string OpcodeStr, string Dt,
3306 SDPatternOperator IntOp, bit Commutable = 0> {
3307 // 64-bit vector types.
3308 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3309 OpcodeStr, !strconcat(Dt, "16"),
3310 v4i16, v4i16, IntOp, Commutable>;
3311 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3312 OpcodeStr, !strconcat(Dt, "32"),
3313 v2i32, v2i32, IntOp, Commutable>;
3315 // 128-bit vector types.
3316 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3317 OpcodeStr, !strconcat(Dt, "16"),
3318 v8i16, v8i16, IntOp, Commutable>;
3319 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3320 OpcodeStr, !strconcat(Dt, "32"),
3321 v4i32, v4i32, IntOp, Commutable>;
3323 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3324 InstrItinClass itinD16, InstrItinClass itinD32,
3325 InstrItinClass itinQ16, InstrItinClass itinQ32,
3326 string OpcodeStr, string Dt,
3327 SDPatternOperator IntOp> {
3328 // 64-bit vector types.
3329 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3330 OpcodeStr, !strconcat(Dt, "16"),
3331 v4i16, v4i16, IntOp>;
3332 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3333 OpcodeStr, !strconcat(Dt, "32"),
3334 v2i32, v2i32, IntOp>;
3336 // 128-bit vector types.
3337 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3338 OpcodeStr, !strconcat(Dt, "16"),
3339 v8i16, v8i16, IntOp>;
3340 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3341 OpcodeStr, !strconcat(Dt, "32"),
3342 v4i32, v4i32, IntOp>;
3345 multiclass N3VIntSL_HS<bits<4> op11_8,
3346 InstrItinClass itinD16, InstrItinClass itinD32,
3347 InstrItinClass itinQ16, InstrItinClass itinQ32,
3348 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3349 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3350 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3351 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3352 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3353 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3354 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3355 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3356 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3359 // ....then also with element size of 8 bits:
3360 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3361 InstrItinClass itinD16, InstrItinClass itinD32,
3362 InstrItinClass itinQ16, InstrItinClass itinQ32,
3363 string OpcodeStr, string Dt,
3364 SDPatternOperator IntOp, bit Commutable = 0>
3365 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3366 OpcodeStr, Dt, IntOp, Commutable> {
3367 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3368 OpcodeStr, !strconcat(Dt, "8"),
3369 v8i8, v8i8, IntOp, Commutable>;
3370 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3371 OpcodeStr, !strconcat(Dt, "8"),
3372 v16i8, v16i8, IntOp, Commutable>;
3374 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3375 InstrItinClass itinD16, InstrItinClass itinD32,
3376 InstrItinClass itinQ16, InstrItinClass itinQ32,
3377 string OpcodeStr, string Dt,
3378 SDPatternOperator IntOp>
3379 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3380 OpcodeStr, Dt, IntOp> {
3381 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3382 OpcodeStr, !strconcat(Dt, "8"),
3384 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3385 OpcodeStr, !strconcat(Dt, "8"),
3386 v16i8, v16i8, IntOp>;
3390 // ....then also with element size of 64 bits:
3391 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3392 InstrItinClass itinD16, InstrItinClass itinD32,
3393 InstrItinClass itinQ16, InstrItinClass itinQ32,
3394 string OpcodeStr, string Dt,
3395 SDPatternOperator IntOp, bit Commutable = 0>
3396 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3397 OpcodeStr, Dt, IntOp, Commutable> {
3398 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3399 OpcodeStr, !strconcat(Dt, "64"),
3400 v1i64, v1i64, IntOp, Commutable>;
3401 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3402 OpcodeStr, !strconcat(Dt, "64"),
3403 v2i64, v2i64, IntOp, Commutable>;
3405 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3406 InstrItinClass itinD16, InstrItinClass itinD32,
3407 InstrItinClass itinQ16, InstrItinClass itinQ32,
3408 string OpcodeStr, string Dt,
3409 SDPatternOperator IntOp>
3410 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3411 OpcodeStr, Dt, IntOp> {
3412 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3413 OpcodeStr, !strconcat(Dt, "64"),
3414 v1i64, v1i64, IntOp>;
3415 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3416 OpcodeStr, !strconcat(Dt, "64"),
3417 v2i64, v2i64, IntOp>;
3420 // Neon Narrowing 3-register vector intrinsics,
3421 // source operand element sizes of 16, 32 and 64 bits:
3422 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3423 string OpcodeStr, string Dt,
3424 SDPatternOperator IntOp, bit Commutable = 0> {
3425 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3426 OpcodeStr, !strconcat(Dt, "16"),
3427 v8i8, v8i16, IntOp, Commutable>;
3428 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3429 OpcodeStr, !strconcat(Dt, "32"),
3430 v4i16, v4i32, IntOp, Commutable>;
3431 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3432 OpcodeStr, !strconcat(Dt, "64"),
3433 v2i32, v2i64, IntOp, Commutable>;
3437 // Neon Long 3-register vector operations.
3439 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3440 InstrItinClass itin16, InstrItinClass itin32,
3441 string OpcodeStr, string Dt,
3442 SDNode OpNode, bit Commutable = 0> {
3443 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3444 OpcodeStr, !strconcat(Dt, "8"),
3445 v8i16, v8i8, OpNode, Commutable>;
3446 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3447 OpcodeStr, !strconcat(Dt, "16"),
3448 v4i32, v4i16, OpNode, Commutable>;
3449 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3450 OpcodeStr, !strconcat(Dt, "32"),
3451 v2i64, v2i32, OpNode, Commutable>;
3454 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3455 InstrItinClass itin, string OpcodeStr, string Dt,
3457 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3458 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3459 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3460 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3463 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3464 InstrItinClass itin16, InstrItinClass itin32,
3465 string OpcodeStr, string Dt,
3466 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3467 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3468 OpcodeStr, !strconcat(Dt, "8"),
3469 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3470 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3471 OpcodeStr, !strconcat(Dt, "16"),
3472 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3473 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3474 OpcodeStr, !strconcat(Dt, "32"),
3475 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3478 // Neon Long 3-register vector intrinsics.
3480 // First with only element sizes of 16 and 32 bits:
3481 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3482 InstrItinClass itin16, InstrItinClass itin32,
3483 string OpcodeStr, string Dt,
3484 SDPatternOperator IntOp, bit Commutable = 0> {
3485 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3486 OpcodeStr, !strconcat(Dt, "16"),
3487 v4i32, v4i16, IntOp, Commutable>;
3488 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3489 OpcodeStr, !strconcat(Dt, "32"),
3490 v2i64, v2i32, IntOp, Commutable>;
3493 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3494 InstrItinClass itin, string OpcodeStr, string Dt,
3495 SDPatternOperator IntOp> {
3496 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3497 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3498 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3499 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3502 // ....then also with element size of 8 bits:
3503 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3504 InstrItinClass itin16, InstrItinClass itin32,
3505 string OpcodeStr, string Dt,
3506 SDPatternOperator IntOp, bit Commutable = 0>
3507 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3508 IntOp, Commutable> {
3509 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3510 OpcodeStr, !strconcat(Dt, "8"),
3511 v8i16, v8i8, IntOp, Commutable>;
3514 // ....with explicit extend (VABDL).
3515 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3516 InstrItinClass itin, string OpcodeStr, string Dt,
3517 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3518 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3519 OpcodeStr, !strconcat(Dt, "8"),
3520 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3521 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3522 OpcodeStr, !strconcat(Dt, "16"),
3523 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3524 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3525 OpcodeStr, !strconcat(Dt, "32"),
3526 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3530 // Neon Wide 3-register vector intrinsics,
3531 // source operand element sizes of 8, 16 and 32 bits:
3532 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3533 string OpcodeStr, string Dt,
3534 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3535 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3536 OpcodeStr, !strconcat(Dt, "8"),
3537 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3538 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3539 OpcodeStr, !strconcat(Dt, "16"),
3540 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3541 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3542 OpcodeStr, !strconcat(Dt, "32"),
3543 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3547 // Neon Multiply-Op vector operations,
3548 // element sizes of 8, 16 and 32 bits:
3549 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3550 InstrItinClass itinD16, InstrItinClass itinD32,
3551 InstrItinClass itinQ16, InstrItinClass itinQ32,
3552 string OpcodeStr, string Dt, SDNode OpNode> {
3553 // 64-bit vector types.
3554 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3555 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3556 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3557 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3558 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3559 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3561 // 128-bit vector types.
3562 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3563 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3564 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3565 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3566 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3567 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3570 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3571 InstrItinClass itinD16, InstrItinClass itinD32,
3572 InstrItinClass itinQ16, InstrItinClass itinQ32,
3573 string OpcodeStr, string Dt, SDNode ShOp> {
3574 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3575 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3576 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3577 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3578 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3579 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3581 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3582 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3586 // Neon Intrinsic-Op vector operations,
3587 // element sizes of 8, 16 and 32 bits:
3588 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3589 InstrItinClass itinD, InstrItinClass itinQ,
3590 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3592 // 64-bit vector types.
3593 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3594 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3595 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3596 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3597 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3598 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3600 // 128-bit vector types.
3601 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3602 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3603 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3604 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3605 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3606 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3609 // Neon 3-argument intrinsics,
3610 // element sizes of 8, 16 and 32 bits:
3611 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3612 InstrItinClass itinD, InstrItinClass itinQ,
3613 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3614 // 64-bit vector types.
3615 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3616 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3617 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3618 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3619 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3620 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3622 // 128-bit vector types.
3623 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3624 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3625 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3626 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3627 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3628 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3632 // Neon Long Multiply-Op vector operations,
3633 // element sizes of 8, 16 and 32 bits:
3634 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3635 InstrItinClass itin16, InstrItinClass itin32,
3636 string OpcodeStr, string Dt, SDNode MulOp,
3638 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3639 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3640 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3641 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3642 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3643 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3646 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3647 string Dt, SDNode MulOp, SDNode OpNode> {
3648 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3649 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3650 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3651 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3655 // Neon Long 3-argument intrinsics.
3657 // First with only element sizes of 16 and 32 bits:
3658 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3659 InstrItinClass itin16, InstrItinClass itin32,
3660 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3661 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3662 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3663 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3664 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3667 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3668 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3669 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3670 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3671 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3672 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3675 // ....then also with element size of 8 bits:
3676 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3677 InstrItinClass itin16, InstrItinClass itin32,
3678 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3679 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3680 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3681 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3684 // ....with explicit extend (VABAL).
3685 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3686 InstrItinClass itin, string OpcodeStr, string Dt,
3687 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3688 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3689 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3690 IntOp, ExtOp, OpNode>;
3691 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3692 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3693 IntOp, ExtOp, OpNode>;
3694 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3695 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3696 IntOp, ExtOp, OpNode>;
3700 // Neon Pairwise long 2-register intrinsics,
3701 // element sizes of 8, 16 and 32 bits:
3702 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3703 bits<5> op11_7, bit op4,
3704 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3705 // 64-bit vector types.
3706 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3707 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3708 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3709 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3710 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3711 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3713 // 128-bit vector types.
3714 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3715 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3716 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3717 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3718 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3719 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3723 // Neon Pairwise long 2-register accumulate intrinsics,
3724 // element sizes of 8, 16 and 32 bits:
3725 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3726 bits<5> op11_7, bit op4,
3727 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3728 // 64-bit vector types.
3729 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3730 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3731 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3732 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3733 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3734 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3736 // 128-bit vector types.
3737 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3738 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3739 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3740 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3741 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3742 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3746 // Neon 2-register vector shift by immediate,
3747 // with f of either N2RegVShLFrm or N2RegVShRFrm
3748 // element sizes of 8, 16, 32 and 64 bits:
3749 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3750 InstrItinClass itin, string OpcodeStr, string Dt,
3752 // 64-bit vector types.
3753 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3754 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3755 let Inst{21-19} = 0b001; // imm6 = 001xxx
3757 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3758 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3759 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3761 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3762 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3763 let Inst{21} = 0b1; // imm6 = 1xxxxx
3765 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3766 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3769 // 128-bit vector types.
3770 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3771 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3772 let Inst{21-19} = 0b001; // imm6 = 001xxx
3774 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3775 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3776 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3778 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3779 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3780 let Inst{21} = 0b1; // imm6 = 1xxxxx
3782 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3783 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3786 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3787 InstrItinClass itin, string OpcodeStr, string Dt,
3788 string baseOpc, SDNode OpNode> {
3789 // 64-bit vector types.
3790 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3791 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3792 let Inst{21-19} = 0b001; // imm6 = 001xxx
3794 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3795 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3796 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3798 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3799 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3800 let Inst{21} = 0b1; // imm6 = 1xxxxx
3802 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3803 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3806 // 128-bit vector types.
3807 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3808 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3809 let Inst{21-19} = 0b001; // imm6 = 001xxx
3811 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3812 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3813 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3815 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3816 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3817 let Inst{21} = 0b1; // imm6 = 1xxxxx
3819 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3820 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3824 // Neon Shift-Accumulate vector operations,
3825 // element sizes of 8, 16, 32 and 64 bits:
3826 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3827 string OpcodeStr, string Dt, SDNode ShOp> {
3828 // 64-bit vector types.
3829 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3830 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3831 let Inst{21-19} = 0b001; // imm6 = 001xxx
3833 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3834 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3835 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3837 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3838 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3839 let Inst{21} = 0b1; // imm6 = 1xxxxx
3841 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3842 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3845 // 128-bit vector types.
3846 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3847 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3848 let Inst{21-19} = 0b001; // imm6 = 001xxx
3850 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3851 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3852 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3854 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3855 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3856 let Inst{21} = 0b1; // imm6 = 1xxxxx
3858 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3859 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3863 // Neon Shift-Insert vector operations,
3864 // with f of either N2RegVShLFrm or N2RegVShRFrm
3865 // element sizes of 8, 16, 32 and 64 bits:
3866 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3868 // 64-bit vector types.
3869 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3870 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3871 let Inst{21-19} = 0b001; // imm6 = 001xxx
3873 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3874 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3875 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3877 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3878 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3879 let Inst{21} = 0b1; // imm6 = 1xxxxx
3881 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3882 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3885 // 128-bit vector types.
3886 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3887 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3888 let Inst{21-19} = 0b001; // imm6 = 001xxx
3890 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3891 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3892 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3894 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3895 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3896 let Inst{21} = 0b1; // imm6 = 1xxxxx
3898 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3899 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3902 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3904 // 64-bit vector types.
3905 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3906 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3907 let Inst{21-19} = 0b001; // imm6 = 001xxx
3909 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3910 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3911 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3913 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3914 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3915 let Inst{21} = 0b1; // imm6 = 1xxxxx
3917 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3918 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3921 // 128-bit vector types.
3922 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3923 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3924 let Inst{21-19} = 0b001; // imm6 = 001xxx
3926 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3927 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3928 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3930 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3931 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3932 let Inst{21} = 0b1; // imm6 = 1xxxxx
3934 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3935 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3939 // Neon Shift Long operations,
3940 // element sizes of 8, 16, 32 bits:
3941 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3942 bit op4, string OpcodeStr, string Dt,
3943 SDPatternOperator OpNode> {
3944 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3945 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3946 let Inst{21-19} = 0b001; // imm6 = 001xxx
3948 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3949 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3950 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3952 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3953 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3954 let Inst{21} = 0b1; // imm6 = 1xxxxx
3958 // Neon Shift Narrow operations,
3959 // element sizes of 16, 32, 64 bits:
3960 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3961 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3962 SDPatternOperator OpNode> {
3963 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3964 OpcodeStr, !strconcat(Dt, "16"),
3965 v8i8, v8i16, shr_imm8, OpNode> {
3966 let Inst{21-19} = 0b001; // imm6 = 001xxx
3968 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3969 OpcodeStr, !strconcat(Dt, "32"),
3970 v4i16, v4i32, shr_imm16, OpNode> {
3971 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3973 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3974 OpcodeStr, !strconcat(Dt, "64"),
3975 v2i32, v2i64, shr_imm32, OpNode> {
3976 let Inst{21} = 0b1; // imm6 = 1xxxxx
3980 //===----------------------------------------------------------------------===//
3981 // Instruction Definitions.
3982 //===----------------------------------------------------------------------===//
3984 // Vector Add Operations.
3986 // VADD : Vector Add (integer and floating-point)
3987 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3989 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3990 v2f32, v2f32, fadd, 1>;
3991 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3992 v4f32, v4f32, fadd, 1>;
3993 // VADDL : Vector Add Long (Q = D + D)
3994 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3995 "vaddl", "s", add, sext, 1>;
3996 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3997 "vaddl", "u", add, zext, 1>;
3998 // VADDW : Vector Add Wide (Q = Q + D)
3999 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4000 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4001 // VHADD : Vector Halving Add
4002 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4003 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4004 "vhadd", "s", int_arm_neon_vhadds, 1>;
4005 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4006 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4007 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4008 // VRHADD : Vector Rounding Halving Add
4009 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4010 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4011 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4012 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4013 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4014 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4015 // VQADD : Vector Saturating Add
4016 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4017 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4018 "vqadd", "s", int_arm_neon_vqadds, 1>;
4019 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4020 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4021 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4022 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4023 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4024 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4025 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4026 int_arm_neon_vraddhn, 1>;
4028 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4029 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4030 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4031 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4032 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4033 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4035 // Vector Multiply Operations.
4037 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4038 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4039 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4040 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4041 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4042 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4043 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4044 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4045 v2f32, v2f32, fmul, 1>;
4046 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4047 v4f32, v4f32, fmul, 1>;
4048 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4049 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4050 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4053 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4054 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4055 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4056 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4057 (DSubReg_i16_reg imm:$lane))),
4058 (SubReg_i16_lane imm:$lane)))>;
4059 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4060 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4061 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4062 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4063 (DSubReg_i32_reg imm:$lane))),
4064 (SubReg_i32_lane imm:$lane)))>;
4065 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4066 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4067 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4068 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4069 (DSubReg_i32_reg imm:$lane))),
4070 (SubReg_i32_lane imm:$lane)))>;
4073 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4075 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4077 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4079 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4083 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4084 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4085 IIC_VMULi16Q, IIC_VMULi32Q,
4086 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4087 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4088 IIC_VMULi16Q, IIC_VMULi32Q,
4089 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4090 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4091 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4093 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4094 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4095 (DSubReg_i16_reg imm:$lane))),
4096 (SubReg_i16_lane imm:$lane)))>;
4097 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4098 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4100 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4101 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4102 (DSubReg_i32_reg imm:$lane))),
4103 (SubReg_i32_lane imm:$lane)))>;
4105 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4106 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4107 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4108 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4109 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4110 IIC_VMULi16Q, IIC_VMULi32Q,
4111 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4112 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4113 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4115 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4116 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4117 (DSubReg_i16_reg imm:$lane))),
4118 (SubReg_i16_lane imm:$lane)))>;
4119 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4120 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4122 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4123 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4124 (DSubReg_i32_reg imm:$lane))),
4125 (SubReg_i32_lane imm:$lane)))>;
4127 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4128 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4129 DecoderNamespace = "NEONData" in {
4130 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4131 "vmull", "s", NEONvmulls, 1>;
4132 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4133 "vmull", "u", NEONvmullu, 1>;
4134 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4135 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4136 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4137 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4138 Requires<[HasV8, HasCrypto]>;
4140 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4141 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4143 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4144 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4145 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4146 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4147 "vqdmull", "s", int_arm_neon_vqdmull>;
4149 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4151 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4152 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4153 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4154 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4155 v2f32, fmul_su, fadd_mlx>,
4156 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4157 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4158 v4f32, fmul_su, fadd_mlx>,
4159 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4160 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4161 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4162 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4163 v2f32, fmul_su, fadd_mlx>,
4164 Requires<[HasNEON, UseFPVMLx]>;
4165 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4166 v4f32, v2f32, fmul_su, fadd_mlx>,
4167 Requires<[HasNEON, UseFPVMLx]>;
4169 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4170 (mul (v8i16 QPR:$src2),
4171 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4172 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4173 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4174 (DSubReg_i16_reg imm:$lane))),
4175 (SubReg_i16_lane imm:$lane)))>;
4177 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4178 (mul (v4i32 QPR:$src2),
4179 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4180 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4181 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4182 (DSubReg_i32_reg imm:$lane))),
4183 (SubReg_i32_lane imm:$lane)))>;
4185 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4186 (fmul_su (v4f32 QPR:$src2),
4187 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4188 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4190 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4191 (DSubReg_i32_reg imm:$lane))),
4192 (SubReg_i32_lane imm:$lane)))>,
4193 Requires<[HasNEON, UseFPVMLx]>;
4195 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4196 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4197 "vmlal", "s", NEONvmulls, add>;
4198 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4199 "vmlal", "u", NEONvmullu, add>;
4201 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4202 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4204 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4205 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4206 "vqdmlal", "s", null_frag>;
4207 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4209 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4210 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4211 (v4i16 DPR:$Vm))))),
4212 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4213 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4214 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4215 (v2i32 DPR:$Vm))))),
4216 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4217 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4218 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4219 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4221 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4222 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4223 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4224 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4226 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4228 // VMLS : Vector Multiply Subtract (integer and floating-point)
4229 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4230 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4231 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4232 v2f32, fmul_su, fsub_mlx>,
4233 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4234 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4235 v4f32, fmul_su, fsub_mlx>,
4236 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4237 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4238 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4239 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4240 v2f32, fmul_su, fsub_mlx>,
4241 Requires<[HasNEON, UseFPVMLx]>;
4242 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4243 v4f32, v2f32, fmul_su, fsub_mlx>,
4244 Requires<[HasNEON, UseFPVMLx]>;
4246 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4247 (mul (v8i16 QPR:$src2),
4248 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4249 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4250 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4251 (DSubReg_i16_reg imm:$lane))),
4252 (SubReg_i16_lane imm:$lane)))>;
4254 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4255 (mul (v4i32 QPR:$src2),
4256 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4257 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4258 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4259 (DSubReg_i32_reg imm:$lane))),
4260 (SubReg_i32_lane imm:$lane)))>;
4262 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4263 (fmul_su (v4f32 QPR:$src2),
4264 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4265 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4266 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4267 (DSubReg_i32_reg imm:$lane))),
4268 (SubReg_i32_lane imm:$lane)))>,
4269 Requires<[HasNEON, UseFPVMLx]>;
4271 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4272 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4273 "vmlsl", "s", NEONvmulls, sub>;
4274 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4275 "vmlsl", "u", NEONvmullu, sub>;
4277 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4278 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4280 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4281 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4282 "vqdmlsl", "s", null_frag>;
4283 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>;
4285 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4286 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4287 (v4i16 DPR:$Vm))))),
4288 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4289 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4290 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4291 (v2i32 DPR:$Vm))))),
4292 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4293 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4294 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4295 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4297 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4298 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4299 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4300 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4302 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4304 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4305 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4306 v2f32, fmul_su, fadd_mlx>,
4307 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4309 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4310 v4f32, fmul_su, fadd_mlx>,
4311 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4313 // Fused Vector Multiply Subtract (floating-point)
4314 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4315 v2f32, fmul_su, fsub_mlx>,
4316 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4317 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4318 v4f32, fmul_su, fsub_mlx>,
4319 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4321 // Match @llvm.fma.* intrinsics
4322 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4323 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4324 Requires<[HasVFP4]>;
4325 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4326 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4327 Requires<[HasVFP4]>;
4328 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4329 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4330 Requires<[HasVFP4]>;
4331 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4332 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4333 Requires<[HasVFP4]>;
4335 // Vector Subtract Operations.
4337 // VSUB : Vector Subtract (integer and floating-point)
4338 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4339 "vsub", "i", sub, 0>;
4340 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4341 v2f32, v2f32, fsub, 0>;
4342 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4343 v4f32, v4f32, fsub, 0>;
4344 // VSUBL : Vector Subtract Long (Q = D - D)
4345 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4346 "vsubl", "s", sub, sext, 0>;
4347 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4348 "vsubl", "u", sub, zext, 0>;
4349 // VSUBW : Vector Subtract Wide (Q = Q - D)
4350 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4351 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4352 // VHSUB : Vector Halving Subtract
4353 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4354 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4355 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4356 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4357 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4358 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4359 // VQSUB : Vector Saturing Subtract
4360 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4361 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4362 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4363 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4364 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4365 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4366 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4367 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4368 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4369 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4370 int_arm_neon_vrsubhn, 0>;
4372 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4373 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4374 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4375 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4376 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4377 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4379 // Vector Comparisons.
4381 // VCEQ : Vector Compare Equal
4382 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4383 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4384 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4386 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4389 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4390 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4391 "$Vd, $Vm, #0", NEONvceqz>;
4393 // VCGE : Vector Compare Greater Than or Equal
4394 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4395 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4396 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4397 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4398 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4400 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4403 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4404 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4405 "$Vd, $Vm, #0", NEONvcgez>;
4406 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4407 "$Vd, $Vm, #0", NEONvclez>;
4410 // VCGT : Vector Compare Greater Than
4411 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4412 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4413 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4414 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4415 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4417 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4420 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4421 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4422 "$Vd, $Vm, #0", NEONvcgtz>;
4423 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4424 "$Vd, $Vm, #0", NEONvcltz>;
4427 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4428 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4429 "f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
4430 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4431 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
4432 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4433 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4434 "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
4435 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4436 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
4437 // VTST : Vector Test Bits
4438 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4439 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4441 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4442 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4443 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4444 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4445 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4446 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4447 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4448 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4450 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4451 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4452 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4453 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4454 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4455 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4456 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4457 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4459 // Vector Bitwise Operations.
4461 def vnotd : PatFrag<(ops node:$in),
4462 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4463 def vnotq : PatFrag<(ops node:$in),
4464 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4467 // VAND : Vector Bitwise AND
4468 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4469 v2i32, v2i32, and, 1>;
4470 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4471 v4i32, v4i32, and, 1>;
4473 // VEOR : Vector Bitwise Exclusive OR
4474 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4475 v2i32, v2i32, xor, 1>;
4476 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4477 v4i32, v4i32, xor, 1>;
4479 // VORR : Vector Bitwise OR
4480 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4481 v2i32, v2i32, or, 1>;
4482 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4483 v4i32, v4i32, or, 1>;
4485 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4486 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4488 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4490 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4491 let Inst{9} = SIMM{9};
4494 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4495 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4497 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4499 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4500 let Inst{10-9} = SIMM{10-9};
4503 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4504 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4506 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4508 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4509 let Inst{9} = SIMM{9};
4512 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4513 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4515 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4517 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4518 let Inst{10-9} = SIMM{10-9};
4522 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4523 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4524 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4525 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4526 "vbic", "$Vd, $Vn, $Vm", "",
4527 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4528 (vnotd DPR:$Vm))))]>;
4529 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4530 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4531 "vbic", "$Vd, $Vn, $Vm", "",
4532 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4533 (vnotq QPR:$Vm))))]>;
4536 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4537 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4539 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4541 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4542 let Inst{9} = SIMM{9};
4545 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4546 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4548 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4550 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4551 let Inst{10-9} = SIMM{10-9};
4554 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4555 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4557 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4559 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4560 let Inst{9} = SIMM{9};
4563 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4564 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4566 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4568 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4569 let Inst{10-9} = SIMM{10-9};
4572 // VORN : Vector Bitwise OR NOT
4573 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4574 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4575 "vorn", "$Vd, $Vn, $Vm", "",
4576 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4577 (vnotd DPR:$Vm))))]>;
4578 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4579 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4580 "vorn", "$Vd, $Vn, $Vm", "",
4581 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4582 (vnotq QPR:$Vm))))]>;
4584 // VMVN : Vector Bitwise NOT (Immediate)
4586 let isReMaterializable = 1 in {
4588 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4589 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4590 "vmvn", "i16", "$Vd, $SIMM", "",
4591 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4592 let Inst{9} = SIMM{9};
4595 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4596 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4597 "vmvn", "i16", "$Vd, $SIMM", "",
4598 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4599 let Inst{9} = SIMM{9};
4602 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4603 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4604 "vmvn", "i32", "$Vd, $SIMM", "",
4605 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4606 let Inst{11-8} = SIMM{11-8};
4609 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4610 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4611 "vmvn", "i32", "$Vd, $SIMM", "",
4612 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4613 let Inst{11-8} = SIMM{11-8};
4617 // VMVN : Vector Bitwise NOT
4618 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4619 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4620 "vmvn", "$Vd, $Vm", "",
4621 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4622 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4623 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4624 "vmvn", "$Vd, $Vm", "",
4625 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4626 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4627 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4629 // VBSL : Vector Bitwise Select
4630 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4631 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4632 N3RegFrm, IIC_VCNTiD,
4633 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4635 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4636 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4637 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4638 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4639 Requires<[HasNEON]>;
4640 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4641 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4642 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4643 Requires<[HasNEON]>;
4644 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4645 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4646 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4647 Requires<[HasNEON]>;
4648 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4649 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4650 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4651 Requires<[HasNEON]>;
4652 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4653 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4654 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4655 Requires<[HasNEON]>;
4657 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4658 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4659 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4660 Requires<[HasNEON]>;
4662 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4663 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4664 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4665 Requires<[HasNEON]>;
4667 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4668 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4669 N3RegFrm, IIC_VCNTiQ,
4670 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4672 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4674 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4675 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4676 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4677 Requires<[HasNEON]>;
4678 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4679 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4680 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4681 Requires<[HasNEON]>;
4682 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4683 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4684 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4685 Requires<[HasNEON]>;
4686 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4687 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4688 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4689 Requires<[HasNEON]>;
4690 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4691 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4692 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4693 Requires<[HasNEON]>;
4695 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4696 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4697 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4698 Requires<[HasNEON]>;
4699 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4700 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4701 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4702 Requires<[HasNEON]>;
4704 // VBIF : Vector Bitwise Insert if False
4705 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4706 // FIXME: This instruction's encoding MAY NOT BE correct.
4707 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4708 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4709 N3RegFrm, IIC_VBINiD,
4710 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4712 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4713 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4714 N3RegFrm, IIC_VBINiQ,
4715 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4718 // VBIT : Vector Bitwise Insert if True
4719 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4720 // FIXME: This instruction's encoding MAY NOT BE correct.
4721 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4722 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4723 N3RegFrm, IIC_VBINiD,
4724 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4726 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4727 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4728 N3RegFrm, IIC_VBINiQ,
4729 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4732 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4733 // for equivalent operations with different register constraints; it just
4736 // Vector Absolute Differences.
4738 // VABD : Vector Absolute Difference
4739 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4740 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4741 "vabd", "s", int_arm_neon_vabds, 1>;
4742 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4743 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4744 "vabd", "u", int_arm_neon_vabdu, 1>;
4745 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4746 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4747 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4748 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4750 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4751 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4752 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4753 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4754 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4756 // VABA : Vector Absolute Difference and Accumulate
4757 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4758 "vaba", "s", int_arm_neon_vabds, add>;
4759 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4760 "vaba", "u", int_arm_neon_vabdu, add>;
4762 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4763 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4764 "vabal", "s", int_arm_neon_vabds, zext, add>;
4765 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4766 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4768 // Vector Maximum and Minimum.
4770 // VMAX : Vector Maximum
4771 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4772 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4773 "vmax", "s", int_arm_neon_vmaxs, 1>;
4774 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4775 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4776 "vmax", "u", int_arm_neon_vmaxu, 1>;
4777 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4779 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4780 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4782 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4785 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4786 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4787 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4788 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4789 Requires<[HasV8, HasNEON]>;
4790 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4791 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4792 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4793 Requires<[HasV8, HasNEON]>;
4796 // VMIN : Vector Minimum
4797 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4798 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4799 "vmin", "s", int_arm_neon_vmins, 1>;
4800 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4801 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4802 "vmin", "u", int_arm_neon_vminu, 1>;
4803 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4805 v2f32, v2f32, int_arm_neon_vmins, 1>;
4806 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4808 v4f32, v4f32, int_arm_neon_vmins, 1>;
4811 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4812 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4813 N3RegFrm, NoItinerary, "vminnm", "f32",
4814 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4815 Requires<[HasV8, HasNEON]>;
4816 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4817 N3RegFrm, NoItinerary, "vminnm", "f32",
4818 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4819 Requires<[HasV8, HasNEON]>;
4822 // Vector Pairwise Operations.
4824 // VPADD : Vector Pairwise Add
4825 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4827 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4828 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4830 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4831 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4833 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4834 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4835 IIC_VPBIND, "vpadd", "f32",
4836 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4838 // VPADDL : Vector Pairwise Add Long
4839 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4840 int_arm_neon_vpaddls>;
4841 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4842 int_arm_neon_vpaddlu>;
4844 // VPADAL : Vector Pairwise Add and Accumulate Long
4845 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4846 int_arm_neon_vpadals>;
4847 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4848 int_arm_neon_vpadalu>;
4850 // VPMAX : Vector Pairwise Maximum
4851 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4852 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4853 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4854 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4855 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4856 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4857 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4858 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4859 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4860 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4861 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4862 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4863 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4864 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4866 // VPMIN : Vector Pairwise Minimum
4867 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4868 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4869 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4870 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4871 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4872 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4873 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4874 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4875 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4876 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4877 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4878 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4879 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4880 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4882 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4884 // VRECPE : Vector Reciprocal Estimate
4885 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4886 IIC_VUNAD, "vrecpe", "u32",
4887 v2i32, v2i32, int_arm_neon_vrecpe>;
4888 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4889 IIC_VUNAQ, "vrecpe", "u32",
4890 v4i32, v4i32, int_arm_neon_vrecpe>;
4891 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4892 IIC_VUNAD, "vrecpe", "f32",
4893 v2f32, v2f32, int_arm_neon_vrecpe>;
4894 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4895 IIC_VUNAQ, "vrecpe", "f32",
4896 v4f32, v4f32, int_arm_neon_vrecpe>;
4898 // VRECPS : Vector Reciprocal Step
4899 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4900 IIC_VRECSD, "vrecps", "f32",
4901 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4902 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4903 IIC_VRECSQ, "vrecps", "f32",
4904 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4906 // VRSQRTE : Vector Reciprocal Square Root Estimate
4907 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4908 IIC_VUNAD, "vrsqrte", "u32",
4909 v2i32, v2i32, int_arm_neon_vrsqrte>;
4910 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4911 IIC_VUNAQ, "vrsqrte", "u32",
4912 v4i32, v4i32, int_arm_neon_vrsqrte>;
4913 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4914 IIC_VUNAD, "vrsqrte", "f32",
4915 v2f32, v2f32, int_arm_neon_vrsqrte>;
4916 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4917 IIC_VUNAQ, "vrsqrte", "f32",
4918 v4f32, v4f32, int_arm_neon_vrsqrte>;
4920 // VRSQRTS : Vector Reciprocal Square Root Step
4921 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4922 IIC_VRECSD, "vrsqrts", "f32",
4923 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4924 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4925 IIC_VRECSQ, "vrsqrts", "f32",
4926 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4930 // VSHL : Vector Shift
4931 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4932 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4933 "vshl", "s", int_arm_neon_vshifts>;
4934 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4935 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4936 "vshl", "u", int_arm_neon_vshiftu>;
4938 // VSHL : Vector Shift Left (Immediate)
4939 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4941 // VSHR : Vector Shift Right (Immediate)
4942 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4944 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4947 // VSHLL : Vector Shift Left Long
4948 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
4949 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
4950 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
4951 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
4953 // VSHLL : Vector Shift Left Long (with maximum shift count)
4954 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4955 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4956 ValueType OpTy, Operand ImmTy>
4957 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4958 ResTy, OpTy, ImmTy, null_frag> {
4959 let Inst{21-16} = op21_16;
4960 let DecoderMethod = "DecodeVSHLMaxInstruction";
4962 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4964 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4965 v4i32, v4i16, imm16>;
4966 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4967 v2i64, v2i32, imm32>;
4969 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
4970 (VSHLLi8 DPR:$Rn, 8)>;
4971 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
4972 (VSHLLi16 DPR:$Rn, 16)>;
4973 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
4974 (VSHLLi32 DPR:$Rn, 32)>;
4975 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
4976 (VSHLLi8 DPR:$Rn, 8)>;
4977 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
4978 (VSHLLi16 DPR:$Rn, 16)>;
4979 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
4980 (VSHLLi32 DPR:$Rn, 32)>;
4982 // VSHRN : Vector Shift Right and Narrow
4983 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4984 PatFrag<(ops node:$Rn, node:$amt),
4985 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
4987 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
4988 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
4989 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
4990 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
4991 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
4992 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
4994 // VRSHL : Vector Rounding Shift
4995 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4996 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4997 "vrshl", "s", int_arm_neon_vrshifts>;
4998 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4999 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5000 "vrshl", "u", int_arm_neon_vrshiftu>;
5001 // VRSHR : Vector Rounding Shift Right
5002 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
5004 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
5007 // VRSHRN : Vector Rounding Shift Right and Narrow
5008 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
5011 // VQSHL : Vector Saturating Shift
5012 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
5013 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5014 "vqshl", "s", int_arm_neon_vqshifts>;
5015 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
5016 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5017 "vqshl", "u", int_arm_neon_vqshiftu>;
5018 // VQSHL : Vector Saturating Shift Left (Immediate)
5019 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5020 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5022 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5023 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5025 // VQSHRN : Vector Saturating Shift Right and Narrow
5026 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5028 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5031 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5032 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5035 // VQRSHL : Vector Saturating Rounding Shift
5036 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5037 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5038 "vqrshl", "s", int_arm_neon_vqrshifts>;
5039 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5040 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5041 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5043 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5044 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5046 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5049 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5050 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5053 // VSRA : Vector Shift Right and Accumulate
5054 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5055 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5056 // VRSRA : Vector Rounding Shift Right and Accumulate
5057 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5058 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5060 // VSLI : Vector Shift Left and Insert
5061 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5063 // VSRI : Vector Shift Right and Insert
5064 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5066 // Vector Absolute and Saturating Absolute.
5068 // VABS : Vector Absolute Value
5069 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5070 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5072 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5074 v2f32, v2f32, fabs>;
5075 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5077 v4f32, v4f32, fabs>;
5079 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5080 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5081 (NEONvshrs DPR:$src, (i32 7))))))),
5082 (VABSv8i8 DPR:$src)>;
5083 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5084 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5085 (NEONvshrs DPR:$src, (i32 15))))))),
5086 (VABSv4i16 DPR:$src)>;
5087 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5088 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5089 (VABSv2i32 DPR:$src)>;
5090 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5091 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5092 (NEONvshrs QPR:$src, (i32 7))))))),
5093 (VABSv16i8 QPR:$src)>;
5094 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5095 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5096 (NEONvshrs QPR:$src, (i32 15))))))),
5097 (VABSv8i16 QPR:$src)>;
5098 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5099 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5100 (VABSv4i32 QPR:$src)>;
5102 // VQABS : Vector Saturating Absolute Value
5103 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5104 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5105 int_arm_neon_vqabs>;
5109 def vnegd : PatFrag<(ops node:$in),
5110 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5111 def vnegq : PatFrag<(ops node:$in),
5112 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5114 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5115 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5116 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5117 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5118 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5119 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5120 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5121 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5123 // VNEG : Vector Negate (integer)
5124 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5125 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5126 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5127 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5128 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5129 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5131 // VNEG : Vector Negate (floating-point)
5132 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5133 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5134 "vneg", "f32", "$Vd, $Vm", "",
5135 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5136 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5137 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5138 "vneg", "f32", "$Vd, $Vm", "",
5139 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5141 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5142 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5143 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5144 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5145 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5146 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5148 // VQNEG : Vector Saturating Negate
5149 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5150 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5151 int_arm_neon_vqneg>;
5153 // Vector Bit Counting Operations.
5155 // VCLS : Vector Count Leading Sign Bits
5156 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5157 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5159 // VCLZ : Vector Count Leading Zeros
5160 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5161 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5163 // VCNT : Vector Count One Bits
5164 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5165 IIC_VCNTiD, "vcnt", "8",
5167 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5168 IIC_VCNTiQ, "vcnt", "8",
5169 v16i8, v16i8, ctpop>;
5172 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5173 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5174 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5176 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5177 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5178 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5181 // Vector Move Operations.
5183 // VMOV : Vector Move (Register)
5184 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5185 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5186 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5187 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5189 // VMOV : Vector Move (Immediate)
5191 let isReMaterializable = 1 in {
5192 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5193 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5194 "vmov", "i8", "$Vd, $SIMM", "",
5195 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5196 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5197 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5198 "vmov", "i8", "$Vd, $SIMM", "",
5199 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5201 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5202 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5203 "vmov", "i16", "$Vd, $SIMM", "",
5204 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5205 let Inst{9} = SIMM{9};
5208 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5209 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5210 "vmov", "i16", "$Vd, $SIMM", "",
5211 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5212 let Inst{9} = SIMM{9};
5215 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5216 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5217 "vmov", "i32", "$Vd, $SIMM", "",
5218 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5219 let Inst{11-8} = SIMM{11-8};
5222 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5223 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5224 "vmov", "i32", "$Vd, $SIMM", "",
5225 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5226 let Inst{11-8} = SIMM{11-8};
5229 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5230 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5231 "vmov", "i64", "$Vd, $SIMM", "",
5232 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5233 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5234 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5235 "vmov", "i64", "$Vd, $SIMM", "",
5236 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5238 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5239 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5240 "vmov", "f32", "$Vd, $SIMM", "",
5241 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5242 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5243 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5244 "vmov", "f32", "$Vd, $SIMM", "",
5245 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5246 } // isReMaterializable
5249 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
5250 // require zero cycles to execute so they should be used wherever possible for
5251 // setting a register to zero.
5253 // Even without these pseudo-insts we would probably end up with the correct
5254 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
5255 // since they are sometimes rather expensive (in general).
5257 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
5258 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5259 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5260 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5262 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5263 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5264 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5268 // VMOV : Vector Get Lane (move scalar to ARM core register)
5270 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5271 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5272 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5273 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5275 let Inst{21} = lane{2};
5276 let Inst{6-5} = lane{1-0};
5278 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5279 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5280 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5281 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5283 let Inst{21} = lane{1};
5284 let Inst{6} = lane{0};
5286 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5287 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5288 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5289 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5291 let Inst{21} = lane{2};
5292 let Inst{6-5} = lane{1-0};
5294 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5295 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5296 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5297 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5299 let Inst{21} = lane{1};
5300 let Inst{6} = lane{0};
5302 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5303 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5304 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5305 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5307 Requires<[HasNEON, HasFastVGETLNi32]> {
5308 let Inst{21} = lane{0};
5310 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5311 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5312 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5313 (DSubReg_i8_reg imm:$lane))),
5314 (SubReg_i8_lane imm:$lane))>;
5315 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5316 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5317 (DSubReg_i16_reg imm:$lane))),
5318 (SubReg_i16_lane imm:$lane))>;
5319 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5320 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5321 (DSubReg_i8_reg imm:$lane))),
5322 (SubReg_i8_lane imm:$lane))>;
5323 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5324 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5325 (DSubReg_i16_reg imm:$lane))),
5326 (SubReg_i16_lane imm:$lane))>;
5327 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5328 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5329 (DSubReg_i32_reg imm:$lane))),
5330 (SubReg_i32_lane imm:$lane))>,
5331 Requires<[HasNEON, HasFastVGETLNi32]>;
5332 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5334 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5335 Requires<[HasNEON, HasSlowVGETLNi32]>;
5336 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5338 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5339 Requires<[HasNEON, HasSlowVGETLNi32]>;
5340 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5341 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5342 (SSubReg_f32_reg imm:$src2))>;
5343 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5344 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5345 (SSubReg_f32_reg imm:$src2))>;
5346 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5347 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5348 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5349 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5352 // VMOV : Vector Set Lane (move ARM core register to scalar)
5354 let Constraints = "$src1 = $V" in {
5355 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5356 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5357 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5358 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5359 GPR:$R, imm:$lane))]> {
5360 let Inst{21} = lane{2};
5361 let Inst{6-5} = lane{1-0};
5363 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5364 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5365 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5366 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5367 GPR:$R, imm:$lane))]> {
5368 let Inst{21} = lane{1};
5369 let Inst{6} = lane{0};
5371 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5372 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5373 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5374 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5375 GPR:$R, imm:$lane))]> {
5376 let Inst{21} = lane{0};
5379 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5380 (v16i8 (INSERT_SUBREG QPR:$src1,
5381 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5382 (DSubReg_i8_reg imm:$lane))),
5383 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5384 (DSubReg_i8_reg imm:$lane)))>;
5385 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5386 (v8i16 (INSERT_SUBREG QPR:$src1,
5387 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5388 (DSubReg_i16_reg imm:$lane))),
5389 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5390 (DSubReg_i16_reg imm:$lane)))>;
5391 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5392 (v4i32 (INSERT_SUBREG QPR:$src1,
5393 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5394 (DSubReg_i32_reg imm:$lane))),
5395 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5396 (DSubReg_i32_reg imm:$lane)))>;
5398 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5399 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5400 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5401 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5402 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5403 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5405 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5406 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5407 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5408 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5410 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5411 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5412 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5413 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5414 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5415 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5417 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5418 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5419 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5420 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5421 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5422 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5424 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5425 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5426 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5428 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5429 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5430 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5432 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5433 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5434 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5437 // VDUP : Vector Duplicate (from ARM core register to all elements)
5439 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5440 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5441 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5442 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5443 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5444 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5445 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5446 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5448 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5449 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5450 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5451 Requires<[HasNEON, HasFastVDUP32]>;
5452 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5453 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5454 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5456 // NEONvdup patterns for uarchs with fast VDUP.32.
5457 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5458 Requires<[HasNEON,HasFastVDUP32]>;
5459 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5461 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5462 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5463 Requires<[HasNEON,HasSlowVDUP32]>;
5464 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5465 Requires<[HasNEON,HasSlowVDUP32]>;
5467 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5469 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5470 ValueType Ty, Operand IdxTy>
5471 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5472 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5473 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5475 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5476 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5477 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5478 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5479 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5480 VectorIndex32:$lane)))]>;
5482 // Inst{19-16} is partially specified depending on the element size.
5484 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5486 let Inst{19-17} = lane{2-0};
5488 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5490 let Inst{19-18} = lane{1-0};
5492 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5494 let Inst{19} = lane{0};
5496 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5498 let Inst{19-17} = lane{2-0};
5500 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5502 let Inst{19-18} = lane{1-0};
5504 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5506 let Inst{19} = lane{0};
5509 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5510 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5512 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5513 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5515 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5516 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5517 (DSubReg_i8_reg imm:$lane))),
5518 (SubReg_i8_lane imm:$lane)))>;
5519 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5520 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5521 (DSubReg_i16_reg imm:$lane))),
5522 (SubReg_i16_lane imm:$lane)))>;
5523 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5524 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5525 (DSubReg_i32_reg imm:$lane))),
5526 (SubReg_i32_lane imm:$lane)))>;
5527 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5528 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5529 (DSubReg_i32_reg imm:$lane))),
5530 (SubReg_i32_lane imm:$lane)))>;
5532 def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
5533 (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5534 SPR:$src, ssub_0), (i32 0)))>;
5535 def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
5536 (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5537 SPR:$src, ssub_0), (i32 0)))>;
5539 // VMOVN : Vector Narrowing Move
5540 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5541 "vmovn", "i", trunc>;
5542 // VQMOVN : Vector Saturating Narrowing Move
5543 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5544 "vqmovn", "s", int_arm_neon_vqmovns>;
5545 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5546 "vqmovn", "u", int_arm_neon_vqmovnu>;
5547 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5548 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5549 // VMOVL : Vector Lengthening Move
5550 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5551 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5552 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5553 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5554 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5556 // Vector Conversions.
5558 // VCVT : Vector Convert Between Floating-Point and Integers
5559 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5560 v2i32, v2f32, fp_to_sint>;
5561 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5562 v2i32, v2f32, fp_to_uint>;
5563 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5564 v2f32, v2i32, sint_to_fp>;
5565 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5566 v2f32, v2i32, uint_to_fp>;
5568 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5569 v4i32, v4f32, fp_to_sint>;
5570 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5571 v4i32, v4f32, fp_to_uint>;
5572 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5573 v4f32, v4i32, sint_to_fp>;
5574 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5575 v4f32, v4i32, uint_to_fp>;
5578 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5579 SDPatternOperator IntU> {
5580 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5581 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5582 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5583 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5584 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5585 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5586 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5587 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5588 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5592 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5593 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5594 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5595 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5597 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5598 let DecoderMethod = "DecodeVCVTD" in {
5599 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5600 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5601 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5602 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5603 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5604 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5605 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5606 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5609 let DecoderMethod = "DecodeVCVTQ" in {
5610 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5611 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5612 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5613 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5614 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5615 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5616 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5617 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5620 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5621 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5622 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5623 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5624 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5625 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5626 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5627 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5629 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5630 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5631 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5632 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5633 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5634 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5635 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5636 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5639 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5640 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5641 IIC_VUNAQ, "vcvt", "f16.f32",
5642 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5643 Requires<[HasNEON, HasFP16]>;
5644 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5645 IIC_VUNAQ, "vcvt", "f32.f16",
5646 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5647 Requires<[HasNEON, HasFP16]>;
5651 // VREV64 : Vector Reverse elements within 64-bit doublewords
5653 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5654 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5655 (ins DPR:$Vm), IIC_VMOVD,
5656 OpcodeStr, Dt, "$Vd, $Vm", "",
5657 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5658 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5659 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5660 (ins QPR:$Vm), IIC_VMOVQ,
5661 OpcodeStr, Dt, "$Vd, $Vm", "",
5662 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5664 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5665 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5666 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5667 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5669 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5670 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5671 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5672 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5674 // VREV32 : Vector Reverse elements within 32-bit words
5676 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5677 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5678 (ins DPR:$Vm), IIC_VMOVD,
5679 OpcodeStr, Dt, "$Vd, $Vm", "",
5680 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5681 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5682 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5683 (ins QPR:$Vm), IIC_VMOVQ,
5684 OpcodeStr, Dt, "$Vd, $Vm", "",
5685 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5687 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5688 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5690 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5691 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5693 // VREV16 : Vector Reverse elements within 16-bit halfwords
5695 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5696 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5697 (ins DPR:$Vm), IIC_VMOVD,
5698 OpcodeStr, Dt, "$Vd, $Vm", "",
5699 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5700 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5701 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5702 (ins QPR:$Vm), IIC_VMOVQ,
5703 OpcodeStr, Dt, "$Vd, $Vm", "",
5704 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5706 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5707 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5709 // Other Vector Shuffles.
5711 // Aligned extractions: really just dropping registers
5713 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5714 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5715 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5717 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5719 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5721 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5723 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5725 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5728 // VEXT : Vector Extract
5731 // All of these have a two-operand InstAlias.
5732 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5733 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5734 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5735 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5736 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5737 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5738 (Ty DPR:$Vm), imm:$index)))]> {
5741 let Inst{10-8} = index{2-0};
5744 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5745 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5746 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5747 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5748 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5749 (Ty QPR:$Vm), imm:$index)))]> {
5751 let Inst{11-8} = index{3-0};
5755 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5756 let Inst{10-8} = index{2-0};
5758 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5759 let Inst{10-9} = index{1-0};
5762 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5763 let Inst{10} = index{0};
5764 let Inst{9-8} = 0b00;
5766 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5769 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5771 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5772 let Inst{11-8} = index{3-0};
5774 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5775 let Inst{11-9} = index{2-0};
5778 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5779 let Inst{11-10} = index{1-0};
5780 let Inst{9-8} = 0b00;
5782 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5783 let Inst{11} = index{0};
5784 let Inst{10-8} = 0b000;
5786 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5789 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5791 // VTRN : Vector Transpose
5793 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5794 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5795 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5797 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5798 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5799 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5801 // VUZP : Vector Unzip (Deinterleave)
5803 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5804 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5805 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5806 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5807 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5809 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5810 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5811 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5813 // VZIP : Vector Zip (Interleave)
5815 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5816 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5817 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5818 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5819 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5821 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5822 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5823 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5825 // Vector Table Lookup and Table Extension.
5827 // VTBL : Vector Table Lookup
5828 let DecoderMethod = "DecodeTBLInstruction" in {
5830 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5831 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5832 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5833 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5834 let hasExtraSrcRegAllocReq = 1 in {
5836 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5837 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5838 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5840 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5841 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5842 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5844 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5845 (ins VecListFourD:$Vn, DPR:$Vm),
5847 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5848 } // hasExtraSrcRegAllocReq = 1
5851 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5853 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5855 // VTBX : Vector Table Extension
5857 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5858 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5859 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5860 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5861 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5862 let hasExtraSrcRegAllocReq = 1 in {
5864 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5865 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5866 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5868 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5869 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5870 NVTBLFrm, IIC_VTBX3,
5871 "vtbx", "8", "$Vd, $Vn, $Vm",
5874 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5875 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5876 "vtbx", "8", "$Vd, $Vn, $Vm",
5878 } // hasExtraSrcRegAllocReq = 1
5881 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5882 IIC_VTBX3, "$orig = $dst", []>;
5884 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5885 IIC_VTBX4, "$orig = $dst", []>;
5886 } // DecoderMethod = "DecodeTBLInstruction"
5888 // VRINT : Vector Rounding
5889 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
5890 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5891 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
5892 !strconcat("vrint", op), "f32",
5893 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
5894 let Inst{9-7} = op9_7;
5896 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
5897 !strconcat("vrint", op), "f32",
5898 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
5899 let Inst{9-7} = op9_7;
5903 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
5904 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
5905 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
5906 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
5909 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
5910 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
5911 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
5912 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
5913 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
5914 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
5916 // Cryptography instructions
5917 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
5918 DecoderNamespace = "v8Crypto", hasSideEffects = 0 in {
5919 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
5920 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5921 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5922 Requires<[HasV8, HasCrypto]>;
5923 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
5924 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5925 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5926 Requires<[HasV8, HasCrypto]>;
5927 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5928 SDPatternOperator Int>
5929 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5930 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5931 Requires<[HasV8, HasCrypto]>;
5932 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5933 SDPatternOperator Int>
5934 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5935 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5936 Requires<[HasV8, HasCrypto]>;
5937 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
5938 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
5939 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
5940 Requires<[HasV8, HasCrypto]>;
5943 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
5944 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
5945 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
5946 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
5948 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
5949 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
5950 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
5951 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
5952 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
5953 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
5954 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
5955 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
5956 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
5957 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
5959 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
5960 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
5961 (SHA1H (SUBREG_TO_REG (i64 0),
5962 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
5966 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
5967 (SHA1C v4i32:$hash_abcd,
5968 (SUBREG_TO_REG (i64 0),
5969 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
5973 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
5974 (SHA1M v4i32:$hash_abcd,
5975 (SUBREG_TO_REG (i64 0),
5976 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
5980 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
5981 (SHA1P v4i32:$hash_abcd,
5982 (SUBREG_TO_REG (i64 0),
5983 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
5987 //===----------------------------------------------------------------------===//
5988 // NEON instructions for single-precision FP math
5989 //===----------------------------------------------------------------------===//
5991 class N2VSPat<SDNode OpNode, NeonI Inst>
5992 : NEONFPPat<(f32 (OpNode SPR:$a)),
5994 (v2f32 (COPY_TO_REGCLASS (Inst
5996 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5997 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5999 class N3VSPat<SDNode OpNode, NeonI Inst>
6000 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
6002 (v2f32 (COPY_TO_REGCLASS (Inst
6004 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6007 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6008 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6010 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
6011 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
6013 (v2f32 (COPY_TO_REGCLASS (Inst
6015 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6018 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6021 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6022 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6024 def : N3VSPat<fadd, VADDfd>;
6025 def : N3VSPat<fsub, VSUBfd>;
6026 def : N3VSPat<fmul, VMULfd>;
6027 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
6028 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6029 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
6030 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6031 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
6032 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6033 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
6034 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6035 def : N2VSPat<fabs, VABSfd>;
6036 def : N2VSPat<fneg, VNEGfd>;
6037 def : N3VSPat<NEONfmax, VMAXfd>;
6038 def : N3VSPat<NEONfmin, VMINfd>;
6039 def : N2VSPat<arm_ftosi, VCVTf2sd>;
6040 def : N2VSPat<arm_ftoui, VCVTf2ud>;
6041 def : N2VSPat<arm_sitof, VCVTs2fd>;
6042 def : N2VSPat<arm_uitof, VCVTu2fd>;
6044 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6045 def : Pat<(f32 (bitconvert GPR:$a)),
6046 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6047 Requires<[HasNEON, DontUseVMOVSR]>;
6049 //===----------------------------------------------------------------------===//
6050 // Non-Instruction Patterns
6051 //===----------------------------------------------------------------------===//
6054 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6055 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6056 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6057 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6058 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6059 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6060 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6061 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6062 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6063 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6064 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6065 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6066 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6067 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6068 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6069 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6070 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6071 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6072 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6073 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6074 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6075 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6076 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6077 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6078 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6079 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6080 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6081 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6082 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6083 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6085 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6086 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6087 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6088 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6089 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6090 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6091 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6092 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6093 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6094 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6095 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6096 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6097 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6098 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6099 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6100 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6101 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6102 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6103 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6104 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6105 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6106 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6107 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6108 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6109 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6110 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6111 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6112 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6113 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6114 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6116 // Fold extracting an element out of a v2i32 into a vfp register.
6117 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6118 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6120 // Vector lengthening move with load, matching extending loads.
6122 // extload, zextload and sextload for a standard lengthening load. Example:
6123 // Lengthen_Single<"8", "i16", "8"> =
6124 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6125 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6126 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6127 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6128 let AddedComplexity = 10 in {
6129 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6130 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6131 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6132 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6134 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6135 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6136 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6137 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6139 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6140 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6141 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6142 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6146 // extload, zextload and sextload for a lengthening load which only uses
6147 // half the lanes available. Example:
6148 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6149 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6150 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6151 // (f64 (IMPLICIT_DEF)), (i32 0))),
6153 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6154 string InsnLanes, string InsnTy> {
6155 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6156 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6157 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6158 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6160 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6161 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6162 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6163 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6165 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6166 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6167 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6168 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6172 // extload, zextload and sextload for a lengthening load followed by another
6173 // lengthening load, to quadruple the initial length.
6175 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6176 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6177 // (EXTRACT_SUBREG (VMOVLuv4i32
6178 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6179 // (f64 (IMPLICIT_DEF)),
6183 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6184 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6186 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6187 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6188 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6189 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6190 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6192 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6193 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6194 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6195 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6196 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6198 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6199 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6200 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6201 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6202 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6206 // extload, zextload and sextload for a lengthening load followed by another
6207 // lengthening load, to quadruple the initial length, but which ends up only
6208 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6210 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6211 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6212 // (EXTRACT_SUBREG (VMOVLuv4i32
6213 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6214 // (f64 (IMPLICIT_DEF)), (i32 0))),
6217 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6218 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6220 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6221 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6222 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6223 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6224 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6227 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6228 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6229 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6230 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6231 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6234 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6235 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6236 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6237 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6238 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6243 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6244 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6245 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6247 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6248 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6250 // Double lengthening - v4i8 -> v4i16 -> v4i32
6251 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6252 // v2i8 -> v2i16 -> v2i32
6253 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6254 // v2i16 -> v2i32 -> v2i64
6255 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6257 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6258 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6259 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6260 (VLD1LNd16 addrmode6:$addr,
6261 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6262 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6263 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6264 (VLD1LNd16 addrmode6:$addr,
6265 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6266 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6267 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6268 (VLD1LNd16 addrmode6:$addr,
6269 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6271 //===----------------------------------------------------------------------===//
6272 // Assembler aliases
6275 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6276 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6277 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6278 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6280 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6281 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6282 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6283 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6284 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6285 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6286 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6287 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6288 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6289 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6290 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6291 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6292 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6293 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6294 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6295 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6296 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6297 // ... two-operand aliases
6298 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6299 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6300 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6301 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6302 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6303 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6304 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6305 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6306 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6307 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6308 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6309 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6311 // VLD1 single-lane pseudo-instructions. These need special handling for
6312 // the lane index that an InstAlias can't handle, so we use these instead.
6313 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6314 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6315 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6316 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6317 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6318 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6320 def VLD1LNdWB_fixed_Asm_8 :
6321 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6322 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6323 def VLD1LNdWB_fixed_Asm_16 :
6324 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6325 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6326 def VLD1LNdWB_fixed_Asm_32 :
6327 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6328 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6329 def VLD1LNdWB_register_Asm_8 :
6330 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6331 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6332 rGPR:$Rm, pred:$p)>;
6333 def VLD1LNdWB_register_Asm_16 :
6334 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6335 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6336 rGPR:$Rm, pred:$p)>;
6337 def VLD1LNdWB_register_Asm_32 :
6338 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6339 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6340 rGPR:$Rm, pred:$p)>;
6343 // VST1 single-lane pseudo-instructions. These need special handling for
6344 // the lane index that an InstAlias can't handle, so we use these instead.
6345 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6346 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6347 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6348 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6349 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6350 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6352 def VST1LNdWB_fixed_Asm_8 :
6353 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6354 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6355 def VST1LNdWB_fixed_Asm_16 :
6356 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6357 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6358 def VST1LNdWB_fixed_Asm_32 :
6359 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6360 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6361 def VST1LNdWB_register_Asm_8 :
6362 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6363 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6364 rGPR:$Rm, pred:$p)>;
6365 def VST1LNdWB_register_Asm_16 :
6366 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6367 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6368 rGPR:$Rm, pred:$p)>;
6369 def VST1LNdWB_register_Asm_32 :
6370 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6371 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6372 rGPR:$Rm, pred:$p)>;
6374 // VLD2 single-lane pseudo-instructions. These need special handling for
6375 // the lane index that an InstAlias can't handle, so we use these instead.
6376 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6377 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6378 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6379 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6380 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6381 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6382 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6383 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6384 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6385 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6387 def VLD2LNdWB_fixed_Asm_8 :
6388 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6389 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6390 def VLD2LNdWB_fixed_Asm_16 :
6391 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6392 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6393 def VLD2LNdWB_fixed_Asm_32 :
6394 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6395 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6396 def VLD2LNqWB_fixed_Asm_16 :
6397 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6398 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6399 def VLD2LNqWB_fixed_Asm_32 :
6400 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6401 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6402 def VLD2LNdWB_register_Asm_8 :
6403 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6404 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6405 rGPR:$Rm, pred:$p)>;
6406 def VLD2LNdWB_register_Asm_16 :
6407 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6408 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6409 rGPR:$Rm, pred:$p)>;
6410 def VLD2LNdWB_register_Asm_32 :
6411 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6412 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6413 rGPR:$Rm, pred:$p)>;
6414 def VLD2LNqWB_register_Asm_16 :
6415 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6416 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6417 rGPR:$Rm, pred:$p)>;
6418 def VLD2LNqWB_register_Asm_32 :
6419 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6420 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6421 rGPR:$Rm, pred:$p)>;
6424 // VST2 single-lane pseudo-instructions. These need special handling for
6425 // the lane index that an InstAlias can't handle, so we use these instead.
6426 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6427 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6428 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6429 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6430 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6431 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6432 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6433 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6434 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6435 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6437 def VST2LNdWB_fixed_Asm_8 :
6438 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6439 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6440 def VST2LNdWB_fixed_Asm_16 :
6441 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6442 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6443 def VST2LNdWB_fixed_Asm_32 :
6444 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6445 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6446 def VST2LNqWB_fixed_Asm_16 :
6447 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6448 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6449 def VST2LNqWB_fixed_Asm_32 :
6450 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6451 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6452 def VST2LNdWB_register_Asm_8 :
6453 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6454 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6455 rGPR:$Rm, pred:$p)>;
6456 def VST2LNdWB_register_Asm_16 :
6457 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6458 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6459 rGPR:$Rm, pred:$p)>;
6460 def VST2LNdWB_register_Asm_32 :
6461 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6462 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6463 rGPR:$Rm, pred:$p)>;
6464 def VST2LNqWB_register_Asm_16 :
6465 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6466 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6467 rGPR:$Rm, pred:$p)>;
6468 def VST2LNqWB_register_Asm_32 :
6469 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6470 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6471 rGPR:$Rm, pred:$p)>;
6473 // VLD3 all-lanes pseudo-instructions. These need special handling for
6474 // the lane index that an InstAlias can't handle, so we use these instead.
6475 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6476 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6477 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6478 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6479 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6480 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6481 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6482 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6483 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6484 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6485 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6486 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6488 def VLD3DUPdWB_fixed_Asm_8 :
6489 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6490 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6491 def VLD3DUPdWB_fixed_Asm_16 :
6492 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6493 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6494 def VLD3DUPdWB_fixed_Asm_32 :
6495 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6496 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6497 def VLD3DUPqWB_fixed_Asm_8 :
6498 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6499 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6500 def VLD3DUPqWB_fixed_Asm_16 :
6501 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6502 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6503 def VLD3DUPqWB_fixed_Asm_32 :
6504 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6505 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6506 def VLD3DUPdWB_register_Asm_8 :
6507 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6508 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6509 rGPR:$Rm, pred:$p)>;
6510 def VLD3DUPdWB_register_Asm_16 :
6511 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6512 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6513 rGPR:$Rm, pred:$p)>;
6514 def VLD3DUPdWB_register_Asm_32 :
6515 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6516 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6517 rGPR:$Rm, pred:$p)>;
6518 def VLD3DUPqWB_register_Asm_8 :
6519 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6520 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6521 rGPR:$Rm, pred:$p)>;
6522 def VLD3DUPqWB_register_Asm_16 :
6523 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6524 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6525 rGPR:$Rm, pred:$p)>;
6526 def VLD3DUPqWB_register_Asm_32 :
6527 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6528 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6529 rGPR:$Rm, pred:$p)>;
6532 // VLD3 single-lane pseudo-instructions. These need special handling for
6533 // the lane index that an InstAlias can't handle, so we use these instead.
6534 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6535 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6536 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6537 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6538 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6539 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6540 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6541 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6542 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6543 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6545 def VLD3LNdWB_fixed_Asm_8 :
6546 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6547 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6548 def VLD3LNdWB_fixed_Asm_16 :
6549 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6550 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6551 def VLD3LNdWB_fixed_Asm_32 :
6552 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6553 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6554 def VLD3LNqWB_fixed_Asm_16 :
6555 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6556 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6557 def VLD3LNqWB_fixed_Asm_32 :
6558 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6559 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6560 def VLD3LNdWB_register_Asm_8 :
6561 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6562 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6563 rGPR:$Rm, pred:$p)>;
6564 def VLD3LNdWB_register_Asm_16 :
6565 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6566 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6567 rGPR:$Rm, pred:$p)>;
6568 def VLD3LNdWB_register_Asm_32 :
6569 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6570 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6571 rGPR:$Rm, pred:$p)>;
6572 def VLD3LNqWB_register_Asm_16 :
6573 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6574 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6575 rGPR:$Rm, pred:$p)>;
6576 def VLD3LNqWB_register_Asm_32 :
6577 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6578 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6579 rGPR:$Rm, pred:$p)>;
6581 // VLD3 multiple structure pseudo-instructions. These need special handling for
6582 // the vector operands that the normal instructions don't yet model.
6583 // FIXME: Remove these when the register classes and instructions are updated.
6584 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6585 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6586 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6587 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6588 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6589 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6590 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6591 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6592 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6593 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6594 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6595 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6597 def VLD3dWB_fixed_Asm_8 :
6598 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6599 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6600 def VLD3dWB_fixed_Asm_16 :
6601 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6602 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6603 def VLD3dWB_fixed_Asm_32 :
6604 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6605 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6606 def VLD3qWB_fixed_Asm_8 :
6607 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6608 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6609 def VLD3qWB_fixed_Asm_16 :
6610 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6611 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6612 def VLD3qWB_fixed_Asm_32 :
6613 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6614 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6615 def VLD3dWB_register_Asm_8 :
6616 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6617 (ins VecListThreeD:$list, addrmode6:$addr,
6618 rGPR:$Rm, pred:$p)>;
6619 def VLD3dWB_register_Asm_16 :
6620 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6621 (ins VecListThreeD:$list, addrmode6:$addr,
6622 rGPR:$Rm, pred:$p)>;
6623 def VLD3dWB_register_Asm_32 :
6624 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6625 (ins VecListThreeD:$list, addrmode6:$addr,
6626 rGPR:$Rm, pred:$p)>;
6627 def VLD3qWB_register_Asm_8 :
6628 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6629 (ins VecListThreeQ:$list, addrmode6:$addr,
6630 rGPR:$Rm, pred:$p)>;
6631 def VLD3qWB_register_Asm_16 :
6632 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6633 (ins VecListThreeQ:$list, addrmode6:$addr,
6634 rGPR:$Rm, pred:$p)>;
6635 def VLD3qWB_register_Asm_32 :
6636 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6637 (ins VecListThreeQ:$list, addrmode6:$addr,
6638 rGPR:$Rm, pred:$p)>;
6640 // VST3 single-lane pseudo-instructions. These need special handling for
6641 // the lane index that an InstAlias can't handle, so we use these instead.
6642 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6643 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6644 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6645 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6646 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6647 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6648 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6649 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6650 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6651 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6653 def VST3LNdWB_fixed_Asm_8 :
6654 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6655 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6656 def VST3LNdWB_fixed_Asm_16 :
6657 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6658 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6659 def VST3LNdWB_fixed_Asm_32 :
6660 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6661 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6662 def VST3LNqWB_fixed_Asm_16 :
6663 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6664 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6665 def VST3LNqWB_fixed_Asm_32 :
6666 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6667 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6668 def VST3LNdWB_register_Asm_8 :
6669 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6670 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6671 rGPR:$Rm, pred:$p)>;
6672 def VST3LNdWB_register_Asm_16 :
6673 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6674 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6675 rGPR:$Rm, pred:$p)>;
6676 def VST3LNdWB_register_Asm_32 :
6677 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6678 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6679 rGPR:$Rm, pred:$p)>;
6680 def VST3LNqWB_register_Asm_16 :
6681 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6682 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6683 rGPR:$Rm, pred:$p)>;
6684 def VST3LNqWB_register_Asm_32 :
6685 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6686 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6687 rGPR:$Rm, pred:$p)>;
6690 // VST3 multiple structure pseudo-instructions. These need special handling for
6691 // the vector operands that the normal instructions don't yet model.
6692 // FIXME: Remove these when the register classes and instructions are updated.
6693 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6694 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6695 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6696 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6697 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6698 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6699 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6700 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6701 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6702 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6703 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6704 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6706 def VST3dWB_fixed_Asm_8 :
6707 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6708 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6709 def VST3dWB_fixed_Asm_16 :
6710 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6711 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6712 def VST3dWB_fixed_Asm_32 :
6713 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6714 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6715 def VST3qWB_fixed_Asm_8 :
6716 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6717 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6718 def VST3qWB_fixed_Asm_16 :
6719 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6720 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6721 def VST3qWB_fixed_Asm_32 :
6722 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6723 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6724 def VST3dWB_register_Asm_8 :
6725 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6726 (ins VecListThreeD:$list, addrmode6:$addr,
6727 rGPR:$Rm, pred:$p)>;
6728 def VST3dWB_register_Asm_16 :
6729 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6730 (ins VecListThreeD:$list, addrmode6:$addr,
6731 rGPR:$Rm, pred:$p)>;
6732 def VST3dWB_register_Asm_32 :
6733 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6734 (ins VecListThreeD:$list, addrmode6:$addr,
6735 rGPR:$Rm, pred:$p)>;
6736 def VST3qWB_register_Asm_8 :
6737 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6738 (ins VecListThreeQ:$list, addrmode6:$addr,
6739 rGPR:$Rm, pred:$p)>;
6740 def VST3qWB_register_Asm_16 :
6741 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6742 (ins VecListThreeQ:$list, addrmode6:$addr,
6743 rGPR:$Rm, pred:$p)>;
6744 def VST3qWB_register_Asm_32 :
6745 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6746 (ins VecListThreeQ:$list, addrmode6:$addr,
6747 rGPR:$Rm, pred:$p)>;
6749 // VLD4 all-lanes pseudo-instructions. These need special handling for
6750 // the lane index that an InstAlias can't handle, so we use these instead.
6751 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6752 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6753 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6754 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6755 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6756 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6757 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6758 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6759 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6760 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6761 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6762 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6764 def VLD4DUPdWB_fixed_Asm_8 :
6765 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6766 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6767 def VLD4DUPdWB_fixed_Asm_16 :
6768 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6769 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6770 def VLD4DUPdWB_fixed_Asm_32 :
6771 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6772 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6773 def VLD4DUPqWB_fixed_Asm_8 :
6774 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6775 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6776 def VLD4DUPqWB_fixed_Asm_16 :
6777 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6778 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6779 def VLD4DUPqWB_fixed_Asm_32 :
6780 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6781 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6782 def VLD4DUPdWB_register_Asm_8 :
6783 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6784 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6785 rGPR:$Rm, pred:$p)>;
6786 def VLD4DUPdWB_register_Asm_16 :
6787 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6788 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6789 rGPR:$Rm, pred:$p)>;
6790 def VLD4DUPdWB_register_Asm_32 :
6791 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6792 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6793 rGPR:$Rm, pred:$p)>;
6794 def VLD4DUPqWB_register_Asm_8 :
6795 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6796 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6797 rGPR:$Rm, pred:$p)>;
6798 def VLD4DUPqWB_register_Asm_16 :
6799 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6800 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6801 rGPR:$Rm, pred:$p)>;
6802 def VLD4DUPqWB_register_Asm_32 :
6803 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6804 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6805 rGPR:$Rm, pred:$p)>;
6808 // VLD4 single-lane pseudo-instructions. These need special handling for
6809 // the lane index that an InstAlias can't handle, so we use these instead.
6810 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6811 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6812 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6813 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6814 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6815 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6816 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6817 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6818 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6819 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6821 def VLD4LNdWB_fixed_Asm_8 :
6822 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6823 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6824 def VLD4LNdWB_fixed_Asm_16 :
6825 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6826 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6827 def VLD4LNdWB_fixed_Asm_32 :
6828 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6829 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6830 def VLD4LNqWB_fixed_Asm_16 :
6831 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6832 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6833 def VLD4LNqWB_fixed_Asm_32 :
6834 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6835 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6836 def VLD4LNdWB_register_Asm_8 :
6837 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6838 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6839 rGPR:$Rm, pred:$p)>;
6840 def VLD4LNdWB_register_Asm_16 :
6841 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6842 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6843 rGPR:$Rm, pred:$p)>;
6844 def VLD4LNdWB_register_Asm_32 :
6845 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6846 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6847 rGPR:$Rm, pred:$p)>;
6848 def VLD4LNqWB_register_Asm_16 :
6849 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6850 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6851 rGPR:$Rm, pred:$p)>;
6852 def VLD4LNqWB_register_Asm_32 :
6853 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6854 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6855 rGPR:$Rm, pred:$p)>;
6859 // VLD4 multiple structure pseudo-instructions. These need special handling for
6860 // the vector operands that the normal instructions don't yet model.
6861 // FIXME: Remove these when the register classes and instructions are updated.
6862 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6863 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6864 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6865 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6866 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6867 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6868 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6869 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6870 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6871 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6872 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6873 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6875 def VLD4dWB_fixed_Asm_8 :
6876 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6877 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6878 def VLD4dWB_fixed_Asm_16 :
6879 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6880 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6881 def VLD4dWB_fixed_Asm_32 :
6882 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6883 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6884 def VLD4qWB_fixed_Asm_8 :
6885 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6886 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6887 def VLD4qWB_fixed_Asm_16 :
6888 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6889 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6890 def VLD4qWB_fixed_Asm_32 :
6891 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6892 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6893 def VLD4dWB_register_Asm_8 :
6894 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6895 (ins VecListFourD:$list, addrmode6:$addr,
6896 rGPR:$Rm, pred:$p)>;
6897 def VLD4dWB_register_Asm_16 :
6898 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6899 (ins VecListFourD:$list, addrmode6:$addr,
6900 rGPR:$Rm, pred:$p)>;
6901 def VLD4dWB_register_Asm_32 :
6902 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6903 (ins VecListFourD:$list, addrmode6:$addr,
6904 rGPR:$Rm, pred:$p)>;
6905 def VLD4qWB_register_Asm_8 :
6906 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6907 (ins VecListFourQ:$list, addrmode6:$addr,
6908 rGPR:$Rm, pred:$p)>;
6909 def VLD4qWB_register_Asm_16 :
6910 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6911 (ins VecListFourQ:$list, addrmode6:$addr,
6912 rGPR:$Rm, pred:$p)>;
6913 def VLD4qWB_register_Asm_32 :
6914 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6915 (ins VecListFourQ:$list, addrmode6:$addr,
6916 rGPR:$Rm, pred:$p)>;
6918 // VST4 single-lane pseudo-instructions. These need special handling for
6919 // the lane index that an InstAlias can't handle, so we use these instead.
6920 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6921 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6922 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6923 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6924 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6925 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6926 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6927 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6928 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6929 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6931 def VST4LNdWB_fixed_Asm_8 :
6932 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6933 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6934 def VST4LNdWB_fixed_Asm_16 :
6935 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6936 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6937 def VST4LNdWB_fixed_Asm_32 :
6938 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6939 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6940 def VST4LNqWB_fixed_Asm_16 :
6941 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6942 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6943 def VST4LNqWB_fixed_Asm_32 :
6944 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6945 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6946 def VST4LNdWB_register_Asm_8 :
6947 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6948 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6949 rGPR:$Rm, pred:$p)>;
6950 def VST4LNdWB_register_Asm_16 :
6951 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6952 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6953 rGPR:$Rm, pred:$p)>;
6954 def VST4LNdWB_register_Asm_32 :
6955 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6956 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6957 rGPR:$Rm, pred:$p)>;
6958 def VST4LNqWB_register_Asm_16 :
6959 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6960 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6961 rGPR:$Rm, pred:$p)>;
6962 def VST4LNqWB_register_Asm_32 :
6963 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6964 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6965 rGPR:$Rm, pred:$p)>;
6968 // VST4 multiple structure pseudo-instructions. These need special handling for
6969 // the vector operands that the normal instructions don't yet model.
6970 // FIXME: Remove these when the register classes and instructions are updated.
6971 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6972 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6973 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6974 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6975 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6976 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6977 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6978 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6979 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6980 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6981 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6982 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6984 def VST4dWB_fixed_Asm_8 :
6985 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6986 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6987 def VST4dWB_fixed_Asm_16 :
6988 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6989 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6990 def VST4dWB_fixed_Asm_32 :
6991 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6992 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6993 def VST4qWB_fixed_Asm_8 :
6994 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6995 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6996 def VST4qWB_fixed_Asm_16 :
6997 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6998 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6999 def VST4qWB_fixed_Asm_32 :
7000 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7001 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
7002 def VST4dWB_register_Asm_8 :
7003 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7004 (ins VecListFourD:$list, addrmode6:$addr,
7005 rGPR:$Rm, pred:$p)>;
7006 def VST4dWB_register_Asm_16 :
7007 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7008 (ins VecListFourD:$list, addrmode6:$addr,
7009 rGPR:$Rm, pred:$p)>;
7010 def VST4dWB_register_Asm_32 :
7011 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7012 (ins VecListFourD:$list, addrmode6:$addr,
7013 rGPR:$Rm, pred:$p)>;
7014 def VST4qWB_register_Asm_8 :
7015 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7016 (ins VecListFourQ:$list, addrmode6:$addr,
7017 rGPR:$Rm, pred:$p)>;
7018 def VST4qWB_register_Asm_16 :
7019 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7020 (ins VecListFourQ:$list, addrmode6:$addr,
7021 rGPR:$Rm, pred:$p)>;
7022 def VST4qWB_register_Asm_32 :
7023 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7024 (ins VecListFourQ:$list, addrmode6:$addr,
7025 rGPR:$Rm, pred:$p)>;
7027 // VMOV/VMVN takes an optional datatype suffix
7028 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7029 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
7030 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7031 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7033 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7034 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
7035 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7036 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7038 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7039 // D-register versions.
7040 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
7041 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7042 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
7043 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7044 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
7045 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7046 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
7047 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7048 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
7049 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7050 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
7051 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7052 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
7053 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7054 // Q-register versions.
7055 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
7056 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7057 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
7058 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7059 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
7060 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7061 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
7062 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7063 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
7064 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7065 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
7066 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7067 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
7068 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7070 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7071 // D-register versions.
7072 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7073 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7074 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7075 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7076 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7077 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7078 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7079 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7080 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7081 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7082 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7083 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7084 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7085 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7086 // Q-register versions.
7087 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7088 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7089 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7090 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7091 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7092 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7093 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7094 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7095 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7096 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7097 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7098 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7099 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7100 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7102 // VSWP allows, but does not require, a type suffix.
7103 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7104 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7105 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7106 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7108 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7109 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7110 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7111 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7112 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7113 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7114 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7115 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7116 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7117 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7118 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7119 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7120 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7122 // "vmov Rd, #-imm" can be handled via "vmvn".
7123 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7124 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7125 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7126 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7127 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7128 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7129 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7130 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7132 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7133 // these should restrict to just the Q register variants, but the register
7134 // classes are enough to match correctly regardless, so we keep it simple
7135 // and just use MnemonicAlias.
7136 def : NEONMnemonicAlias<"vbicq", "vbic">;
7137 def : NEONMnemonicAlias<"vandq", "vand">;
7138 def : NEONMnemonicAlias<"veorq", "veor">;
7139 def : NEONMnemonicAlias<"vorrq", "vorr">;
7141 def : NEONMnemonicAlias<"vmovq", "vmov">;
7142 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7143 // Explicit versions for floating point so that the FPImm variants get
7144 // handled early. The parser gets confused otherwise.
7145 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7146 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7148 def : NEONMnemonicAlias<"vaddq", "vadd">;
7149 def : NEONMnemonicAlias<"vsubq", "vsub">;
7151 def : NEONMnemonicAlias<"vminq", "vmin">;
7152 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7154 def : NEONMnemonicAlias<"vmulq", "vmul">;
7156 def : NEONMnemonicAlias<"vabsq", "vabs">;
7158 def : NEONMnemonicAlias<"vshlq", "vshl">;
7159 def : NEONMnemonicAlias<"vshrq", "vshr">;
7161 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7163 def : NEONMnemonicAlias<"vcleq", "vcle">;
7164 def : NEONMnemonicAlias<"vceqq", "vceq">;
7166 def : NEONMnemonicAlias<"vzipq", "vzip">;
7167 def : NEONMnemonicAlias<"vswpq", "vswp">;
7169 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7170 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7173 // Alias for loading floating point immediates that aren't representable
7174 // using the vmov.f32 encoding but the bitpattern is representable using
7175 // the .i32 encoding.
7176 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7177 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7178 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7179 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;