1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
43 def nImmSplatI64 : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmSplatI64AsmOperand;
48 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
49 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
50 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
51 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
52 return ((uint64_t)Imm) < 8;
54 let ParserMatchClass = VectorIndex8Operand;
55 let PrintMethod = "printVectorIndex";
56 let MIOperandInfo = (ops i32imm);
58 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
59 return ((uint64_t)Imm) < 4;
61 let ParserMatchClass = VectorIndex16Operand;
62 let PrintMethod = "printVectorIndex";
63 let MIOperandInfo = (ops i32imm);
65 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
66 return ((uint64_t)Imm) < 2;
68 let ParserMatchClass = VectorIndex32Operand;
69 let PrintMethod = "printVectorIndex";
70 let MIOperandInfo = (ops i32imm);
73 def VecListOneDAsmOperand : AsmOperandClass {
74 let Name = "VecListOneD";
75 let ParserMethod = "parseVectorList";
77 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
78 let ParserMatchClass = VecListOneDAsmOperand;
80 // Register list of two sequential D registers.
81 def VecListTwoDAsmOperand : AsmOperandClass {
82 let Name = "VecListTwoD";
83 let ParserMethod = "parseVectorList";
85 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
86 let ParserMatchClass = VecListTwoDAsmOperand;
88 // Register list of three sequential D registers.
89 def VecListThreeDAsmOperand : AsmOperandClass {
90 let Name = "VecListThreeD";
91 let ParserMethod = "parseVectorList";
93 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
94 let ParserMatchClass = VecListThreeDAsmOperand;
96 // Register list of four sequential D registers.
97 def VecListFourDAsmOperand : AsmOperandClass {
98 let Name = "VecListFourD";
99 let ParserMethod = "parseVectorList";
101 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
102 let ParserMatchClass = VecListFourDAsmOperand;
104 // Register list of two D registers spaced by 2 (two sequential Q registers).
105 def VecListTwoQAsmOperand : AsmOperandClass {
106 let Name = "VecListTwoQ";
107 let ParserMethod = "parseVectorList";
109 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
110 let ParserMatchClass = VecListTwoQAsmOperand;
113 //===----------------------------------------------------------------------===//
114 // NEON-specific DAG Nodes.
115 //===----------------------------------------------------------------------===//
117 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
118 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
120 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
121 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
122 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
123 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
124 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
125 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
126 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
127 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
128 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
129 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
130 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
132 // Types for vector shift by immediates. The "SHX" version is for long and
133 // narrow operations where the source and destination vectors have different
134 // types. The "SHINS" version is for shift and insert operations.
135 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
137 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
139 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
140 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
142 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
143 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
144 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
145 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
146 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
147 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
148 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
150 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
151 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
152 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
154 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
155 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
156 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
157 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
158 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
159 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
161 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
162 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
163 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
165 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
166 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
168 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
170 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
171 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
173 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
174 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
175 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
177 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
179 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
180 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
182 def NEONvbsl : SDNode<"ARMISD::VBSL",
183 SDTypeProfile<1, 3, [SDTCisVec<0>,
186 SDTCisSameAs<0, 3>]>>;
188 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
190 // VDUPLANE can produce a quad-register result from a double-register source,
191 // so the result is not constrained to match the source.
192 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
193 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
196 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
197 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
198 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
200 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
201 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
202 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
203 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
205 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
207 SDTCisSameAs<0, 3>]>;
208 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
209 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
210 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
212 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
213 SDTCisSameAs<1, 2>]>;
214 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
215 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
217 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
218 SDTCisSameAs<0, 2>]>;
219 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
220 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
222 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
223 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
224 unsigned EltBits = 0;
225 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
226 return (EltBits == 32 && EltVal == 0);
229 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
230 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
231 unsigned EltBits = 0;
232 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
233 return (EltBits == 8 && EltVal == 0xff);
236 //===----------------------------------------------------------------------===//
237 // NEON load / store instructions
238 //===----------------------------------------------------------------------===//
240 // Use VLDM to load a Q register as a D register pair.
241 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
243 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
245 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
247 // Use VSTM to store a Q register as a D register pair.
248 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
250 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
252 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
254 // Classes for VLD* pseudo-instructions with multi-register operands.
255 // These are expanded to real instructions after register allocation.
256 class VLDQPseudo<InstrItinClass itin>
257 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
258 class VLDQWBPseudo<InstrItinClass itin>
259 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
260 (ins addrmode6:$addr, am6offset:$offset), itin,
262 class VLDQWBfixedPseudo<InstrItinClass itin>
263 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
264 (ins addrmode6:$addr), itin,
266 class VLDQWBregisterPseudo<InstrItinClass itin>
267 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
268 (ins addrmode6:$addr, rGPR:$offset), itin,
270 class VLDQQPseudo<InstrItinClass itin>
271 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
272 class VLDQQWBPseudo<InstrItinClass itin>
273 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
274 (ins addrmode6:$addr, am6offset:$offset), itin,
276 class VLDQQQQPseudo<InstrItinClass itin>
277 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
279 class VLDQQQQWBPseudo<InstrItinClass itin>
280 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
281 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
282 "$addr.addr = $wb, $src = $dst">;
284 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
286 // VLD1 : Vector Load (multiple single elements)
287 class VLD1D<bits<4> op7_4, string Dt>
288 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
289 (ins addrmode6:$Rn), IIC_VLD1,
290 "vld1", Dt, "$Vd, $Rn", "", []> {
293 let DecoderMethod = "DecodeVLDInstruction";
295 class VLD1Q<bits<4> op7_4, string Dt>
296 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
297 (ins addrmode6:$Rn), IIC_VLD1x2,
298 "vld1", Dt, "$Vd, $Rn", "", []> {
300 let Inst{5-4} = Rn{5-4};
301 let DecoderMethod = "DecodeVLDInstruction";
304 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
305 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
306 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
307 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
309 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
310 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
311 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
312 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
314 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
315 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
316 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
317 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
319 // ...with address register writeback:
320 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
321 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
322 (ins addrmode6:$Rn), IIC_VLD1u,
323 "vld1", Dt, "$Vd, $Rn!",
324 "$Rn.addr = $wb", []> {
325 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
327 let DecoderMethod = "DecodeVLDInstruction";
328 let AsmMatchConverter = "cvtVLDwbFixed";
330 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
331 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
332 "vld1", Dt, "$Vd, $Rn, $Rm",
333 "$Rn.addr = $wb", []> {
335 let DecoderMethod = "DecodeVLDInstruction";
336 let AsmMatchConverter = "cvtVLDwbRegister";
339 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
340 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
341 (ins addrmode6:$Rn), IIC_VLD1x2u,
342 "vld1", Dt, "$Vd, $Rn!",
343 "$Rn.addr = $wb", []> {
344 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
345 let Inst{5-4} = Rn{5-4};
346 let DecoderMethod = "DecodeVLDInstruction";
347 let AsmMatchConverter = "cvtVLDwbFixed";
349 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
350 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
351 "vld1", Dt, "$Vd, $Rn, $Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
354 let DecoderMethod = "DecodeVLDInstruction";
355 let AsmMatchConverter = "cvtVLDwbRegister";
359 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
360 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
361 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
362 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
363 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
364 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
365 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
366 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
368 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
369 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
370 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
371 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
372 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
373 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
374 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
375 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
377 // ...with 3 registers
378 class VLD1D3<bits<4> op7_4, string Dt>
379 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
380 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
381 "$Vd, $Rn", "", []> {
384 let DecoderMethod = "DecodeVLDInstruction";
386 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
387 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
388 (ins addrmode6:$Rn), IIC_VLD1x2u,
389 "vld1", Dt, "$Vd, $Rn!",
390 "$Rn.addr = $wb", []> {
391 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
393 let DecoderMethod = "DecodeVLDInstruction";
394 let AsmMatchConverter = "cvtVLDwbFixed";
396 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
397 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
398 "vld1", Dt, "$Vd, $Rn, $Rm",
399 "$Rn.addr = $wb", []> {
401 let DecoderMethod = "DecodeVLDInstruction";
402 let AsmMatchConverter = "cvtVLDwbRegister";
406 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
407 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
408 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
409 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
411 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
412 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
413 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
414 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
416 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
418 // ...with 4 registers
419 class VLD1D4<bits<4> op7_4, string Dt>
420 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
421 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
422 "$Vd, $Rn", "", []> {
424 let Inst{5-4} = Rn{5-4};
425 let DecoderMethod = "DecodeVLDInstruction";
427 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
428 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
429 (ins addrmode6:$Rn), IIC_VLD1x2u,
430 "vld1", Dt, "$Vd, $Rn!",
431 "$Rn.addr = $wb", []> {
432 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
433 let Inst{5-4} = Rn{5-4};
434 let DecoderMethod = "DecodeVLDInstruction";
435 let AsmMatchConverter = "cvtVLDwbFixed";
437 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
438 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
439 "vld1", Dt, "$Vd, $Rn, $Rm",
440 "$Rn.addr = $wb", []> {
441 let Inst{5-4} = Rn{5-4};
442 let DecoderMethod = "DecodeVLDInstruction";
443 let AsmMatchConverter = "cvtVLDwbRegister";
447 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
448 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
449 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
450 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
452 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
453 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
454 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
455 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
457 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
459 // VLD2 : Vector Load (multiple 2-element structures)
460 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
461 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
462 (ins addrmode6:$Rn), IIC_VLD2,
463 "vld2", Dt, "$Vd, $Rn", "", []> {
465 let Inst{5-4} = Rn{5-4};
466 let DecoderMethod = "DecodeVLDInstruction";
468 class VLD2Q<bits<4> op7_4, string Dt, RegisterOperand VdTy>
469 : NLdSt<0, 0b10, 0b0011, op7_4,
471 (ins addrmode6:$Rn), IIC_VLD2x2,
472 "vld2", Dt, "$Vd, $Rn", "", []> {
474 let Inst{5-4} = Rn{5-4};
475 let DecoderMethod = "DecodeVLDInstruction";
478 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
479 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
480 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
482 def VLD2q8 : VLD2Q<{0,0,?,?}, "8", VecListFourD>;
483 def VLD2q16 : VLD2Q<{0,1,?,?}, "16", VecListFourD>;
484 def VLD2q32 : VLD2Q<{1,0,?,?}, "32", VecListFourD>;
486 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
487 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
488 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
490 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
491 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
492 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
494 // ...with address register writeback:
495 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
496 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
497 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
498 "vld2", Dt, "$Vd, $Rn$Rm",
499 "$Rn.addr = $wb", []> {
500 let Inst{5-4} = Rn{5-4};
501 let DecoderMethod = "DecodeVLDInstruction";
503 class VLD2QWB<bits<4> op7_4, string Dt, RegisterOperand VdTy>
504 : NLdSt<0, 0b10, 0b0011, op7_4,
505 (outs VdTy:$Vd, GPR:$wb),
506 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
507 "vld2", Dt, "$Vd, $Rn$Rm",
508 "$Rn.addr = $wb", []> {
509 let Inst{5-4} = Rn{5-4};
510 let DecoderMethod = "DecodeVLDInstruction";
513 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
514 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
515 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
517 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8", VecListFourD>;
518 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16", VecListFourD>;
519 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32", VecListFourD>;
521 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
522 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
523 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
525 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
526 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
527 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
529 // ...with double-spaced registers
530 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
531 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
532 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
533 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
534 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
535 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
537 // VLD3 : Vector Load (multiple 3-element structures)
538 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
539 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
540 (ins addrmode6:$Rn), IIC_VLD3,
541 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
544 let DecoderMethod = "DecodeVLDInstruction";
547 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
548 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
549 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
551 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
552 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
553 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
555 // ...with address register writeback:
556 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b10, op11_8, op7_4,
558 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
559 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
560 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
561 "$Rn.addr = $wb", []> {
563 let DecoderMethod = "DecodeVLDInstruction";
566 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
567 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
568 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
570 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
571 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
572 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
574 // ...with double-spaced registers:
575 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
576 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
577 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
578 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
579 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
580 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
582 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
583 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
584 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
586 // ...alternate versions to be allocated odd register numbers:
587 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
588 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
589 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
591 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
592 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
593 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
595 // VLD4 : Vector Load (multiple 4-element structures)
596 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
597 : NLdSt<0, 0b10, op11_8, op7_4,
598 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
599 (ins addrmode6:$Rn), IIC_VLD4,
600 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
602 let Inst{5-4} = Rn{5-4};
603 let DecoderMethod = "DecodeVLDInstruction";
606 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
607 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
608 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
610 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
611 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
612 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
614 // ...with address register writeback:
615 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
616 : NLdSt<0, 0b10, op11_8, op7_4,
617 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
618 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
619 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
620 "$Rn.addr = $wb", []> {
621 let Inst{5-4} = Rn{5-4};
622 let DecoderMethod = "DecodeVLDInstruction";
625 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
626 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
627 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
629 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
630 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
631 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
633 // ...with double-spaced registers:
634 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
635 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
636 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
637 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
638 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
639 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
641 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
642 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
643 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
645 // ...alternate versions to be allocated odd register numbers:
646 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
647 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
648 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
650 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
651 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
652 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
654 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
656 // Classes for VLD*LN pseudo-instructions with multi-register operands.
657 // These are expanded to real instructions after register allocation.
658 class VLDQLNPseudo<InstrItinClass itin>
659 : PseudoNLdSt<(outs QPR:$dst),
660 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
661 itin, "$src = $dst">;
662 class VLDQLNWBPseudo<InstrItinClass itin>
663 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
664 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
665 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
666 class VLDQQLNPseudo<InstrItinClass itin>
667 : PseudoNLdSt<(outs QQPR:$dst),
668 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
669 itin, "$src = $dst">;
670 class VLDQQLNWBPseudo<InstrItinClass itin>
671 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
672 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
673 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
674 class VLDQQQQLNPseudo<InstrItinClass itin>
675 : PseudoNLdSt<(outs QQQQPR:$dst),
676 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
677 itin, "$src = $dst">;
678 class VLDQQQQLNWBPseudo<InstrItinClass itin>
679 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
680 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
681 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
683 // VLD1LN : Vector Load (single element to one lane)
684 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
686 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
687 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
688 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
690 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
691 (i32 (LoadOp addrmode6:$Rn)),
694 let DecoderMethod = "DecodeVLD1LN";
696 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
698 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
699 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
700 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
702 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
703 (i32 (LoadOp addrmode6oneL32:$Rn)),
706 let DecoderMethod = "DecodeVLD1LN";
708 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
709 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
710 (i32 (LoadOp addrmode6:$addr)),
714 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
715 let Inst{7-5} = lane{2-0};
717 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
718 let Inst{7-6} = lane{1-0};
721 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
722 let Inst{7} = lane{0};
727 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
728 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
729 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
731 def : Pat<(vector_insert (v2f32 DPR:$src),
732 (f32 (load addrmode6:$addr)), imm:$lane),
733 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
734 def : Pat<(vector_insert (v4f32 QPR:$src),
735 (f32 (load addrmode6:$addr)), imm:$lane),
736 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
738 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
740 // ...with address register writeback:
741 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
742 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
743 (ins addrmode6:$Rn, am6offset:$Rm,
744 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
745 "\\{$Vd[$lane]\\}, $Rn$Rm",
746 "$src = $Vd, $Rn.addr = $wb", []> {
747 let DecoderMethod = "DecodeVLD1LN";
750 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
751 let Inst{7-5} = lane{2-0};
753 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
754 let Inst{7-6} = lane{1-0};
757 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
758 let Inst{7} = lane{0};
763 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
764 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
765 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
767 // VLD2LN : Vector Load (single 2-element structure to one lane)
768 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
769 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
770 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
771 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
772 "$src1 = $Vd, $src2 = $dst2", []> {
775 let DecoderMethod = "DecodeVLD2LN";
778 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
779 let Inst{7-5} = lane{2-0};
781 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
782 let Inst{7-6} = lane{1-0};
784 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
785 let Inst{7} = lane{0};
788 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
789 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
790 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
792 // ...with double-spaced registers:
793 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
794 let Inst{7-6} = lane{1-0};
796 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
797 let Inst{7} = lane{0};
800 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
801 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
803 // ...with address register writeback:
804 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
805 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
806 (ins addrmode6:$Rn, am6offset:$Rm,
807 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
808 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
809 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
811 let DecoderMethod = "DecodeVLD2LN";
814 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
815 let Inst{7-5} = lane{2-0};
817 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
818 let Inst{7-6} = lane{1-0};
820 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
821 let Inst{7} = lane{0};
824 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
825 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
826 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
828 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
829 let Inst{7-6} = lane{1-0};
831 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
832 let Inst{7} = lane{0};
835 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
836 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
838 // VLD3LN : Vector Load (single 3-element structure to one lane)
839 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
840 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
841 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
842 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
843 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
844 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
846 let DecoderMethod = "DecodeVLD3LN";
849 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
850 let Inst{7-5} = lane{2-0};
852 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
853 let Inst{7-6} = lane{1-0};
855 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
856 let Inst{7} = lane{0};
859 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
860 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
861 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
863 // ...with double-spaced registers:
864 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
865 let Inst{7-6} = lane{1-0};
867 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
868 let Inst{7} = lane{0};
871 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
872 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
874 // ...with address register writeback:
875 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
876 : NLdStLn<1, 0b10, op11_8, op7_4,
877 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
878 (ins addrmode6:$Rn, am6offset:$Rm,
879 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
880 IIC_VLD3lnu, "vld3", Dt,
881 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
882 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
884 let DecoderMethod = "DecodeVLD3LN";
887 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
888 let Inst{7-5} = lane{2-0};
890 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
891 let Inst{7-6} = lane{1-0};
893 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
894 let Inst{7} = lane{0};
897 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
898 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
899 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
901 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
902 let Inst{7-6} = lane{1-0};
904 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
905 let Inst{7} = lane{0};
908 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
909 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
911 // VLD4LN : Vector Load (single 4-element structure to one lane)
912 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
913 : NLdStLn<1, 0b10, op11_8, op7_4,
914 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
915 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
916 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
917 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
918 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
921 let DecoderMethod = "DecodeVLD4LN";
924 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
925 let Inst{7-5} = lane{2-0};
927 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
928 let Inst{7-6} = lane{1-0};
930 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
931 let Inst{7} = lane{0};
935 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
936 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
937 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
939 // ...with double-spaced registers:
940 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
941 let Inst{7-6} = lane{1-0};
943 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
944 let Inst{7} = lane{0};
948 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
949 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
951 // ...with address register writeback:
952 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
953 : NLdStLn<1, 0b10, op11_8, op7_4,
954 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
955 (ins addrmode6:$Rn, am6offset:$Rm,
956 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
957 IIC_VLD4lnu, "vld4", Dt,
958 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
959 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
962 let DecoderMethod = "DecodeVLD4LN" ;
965 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
966 let Inst{7-5} = lane{2-0};
968 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
969 let Inst{7-6} = lane{1-0};
971 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
972 let Inst{7} = lane{0};
976 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
977 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
978 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
980 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
981 let Inst{7-6} = lane{1-0};
983 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
984 let Inst{7} = lane{0};
988 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
989 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
991 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
993 // VLD1DUP : Vector Load (single element to all lanes)
994 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
995 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
996 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
997 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1000 let DecoderMethod = "DecodeVLD1DupInstruction";
1002 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1003 let Pattern = [(set QPR:$dst,
1004 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1007 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1008 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1009 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1011 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1012 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1013 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1015 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1016 (VLD1DUPd32 addrmode6:$addr)>;
1017 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1018 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1020 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1022 class VLD1QDUP<bits<4> op7_4, string Dt>
1023 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
1024 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1025 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1027 let Inst{4} = Rn{4};
1028 let DecoderMethod = "DecodeVLD1DupInstruction";
1031 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1032 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1033 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1035 // ...with address register writeback:
1036 class VLD1DUPWB<bits<4> op7_4, string Dt>
1037 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
1038 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1039 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1040 let Inst{4} = Rn{4};
1041 let DecoderMethod = "DecodeVLD1DupInstruction";
1043 class VLD1QDUPWB<bits<4> op7_4, string Dt>
1044 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1045 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
1046 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1047 let Inst{4} = Rn{4};
1048 let DecoderMethod = "DecodeVLD1DupInstruction";
1051 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
1052 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
1053 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
1055 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
1056 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
1057 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
1059 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1060 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1061 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
1063 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1064 class VLD2DUP<bits<4> op7_4, string Dt>
1065 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
1066 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1067 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1069 let Inst{4} = Rn{4};
1070 let DecoderMethod = "DecodeVLD2DupInstruction";
1073 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
1074 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
1075 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
1077 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1078 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1079 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1081 // ...with double-spaced registers (not used for codegen):
1082 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
1083 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
1084 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1086 // ...with address register writeback:
1087 class VLD2DUPWB<bits<4> op7_4, string Dt>
1088 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1089 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1090 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1091 let Inst{4} = Rn{4};
1092 let DecoderMethod = "DecodeVLD2DupInstruction";
1095 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1096 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1097 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1099 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1100 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1101 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1103 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1104 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1105 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1107 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1108 class VLD3DUP<bits<4> op7_4, string Dt>
1109 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1110 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1111 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1114 let DecoderMethod = "DecodeVLD3DupInstruction";
1117 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1118 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1119 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1121 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1122 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1123 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1125 // ...with double-spaced registers (not used for codegen):
1126 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1127 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1128 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1130 // ...with address register writeback:
1131 class VLD3DUPWB<bits<4> op7_4, string Dt>
1132 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1133 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1134 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1135 "$Rn.addr = $wb", []> {
1137 let DecoderMethod = "DecodeVLD3DupInstruction";
1140 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1141 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1142 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1144 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1145 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1146 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1148 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1149 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1150 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1152 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1153 class VLD4DUP<bits<4> op7_4, string Dt>
1154 : NLdSt<1, 0b10, 0b1111, op7_4,
1155 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1156 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1157 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1159 let Inst{4} = Rn{4};
1160 let DecoderMethod = "DecodeVLD4DupInstruction";
1163 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1164 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1165 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1167 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1168 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1169 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1171 // ...with double-spaced registers (not used for codegen):
1172 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1173 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1174 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1176 // ...with address register writeback:
1177 class VLD4DUPWB<bits<4> op7_4, string Dt>
1178 : NLdSt<1, 0b10, 0b1111, op7_4,
1179 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1180 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1181 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1182 "$Rn.addr = $wb", []> {
1183 let Inst{4} = Rn{4};
1184 let DecoderMethod = "DecodeVLD4DupInstruction";
1187 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1188 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1189 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1191 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1192 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1193 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1195 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1196 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1197 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1199 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1201 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1203 // Classes for VST* pseudo-instructions with multi-register operands.
1204 // These are expanded to real instructions after register allocation.
1205 class VSTQPseudo<InstrItinClass itin>
1206 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1207 class VSTQWBPseudo<InstrItinClass itin>
1208 : PseudoNLdSt<(outs GPR:$wb),
1209 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1210 "$addr.addr = $wb">;
1211 class VSTQWBfixedPseudo<InstrItinClass itin>
1212 : PseudoNLdSt<(outs GPR:$wb),
1213 (ins addrmode6:$addr, QPR:$src), itin,
1214 "$addr.addr = $wb">;
1215 class VSTQWBregisterPseudo<InstrItinClass itin>
1216 : PseudoNLdSt<(outs GPR:$wb),
1217 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1218 "$addr.addr = $wb">;
1219 class VSTQQPseudo<InstrItinClass itin>
1220 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1221 class VSTQQWBPseudo<InstrItinClass itin>
1222 : PseudoNLdSt<(outs GPR:$wb),
1223 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1224 "$addr.addr = $wb">;
1225 class VSTQQQQPseudo<InstrItinClass itin>
1226 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1227 class VSTQQQQWBPseudo<InstrItinClass itin>
1228 : PseudoNLdSt<(outs GPR:$wb),
1229 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1230 "$addr.addr = $wb">;
1232 // VST1 : Vector Store (multiple single elements)
1233 class VST1D<bits<4> op7_4, string Dt>
1234 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1235 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1237 let Inst{4} = Rn{4};
1238 let DecoderMethod = "DecodeVSTInstruction";
1240 class VST1Q<bits<4> op7_4, string Dt>
1241 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1242 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1244 let Inst{5-4} = Rn{5-4};
1245 let DecoderMethod = "DecodeVSTInstruction";
1248 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1249 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1250 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1251 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1253 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1254 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1255 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1256 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1258 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1259 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1260 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1261 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1263 // ...with address register writeback:
1264 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1265 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1266 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1267 "vst1", Dt, "$Vd, $Rn!",
1268 "$Rn.addr = $wb", []> {
1269 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1270 let Inst{4} = Rn{4};
1271 let DecoderMethod = "DecodeVSTInstruction";
1272 let AsmMatchConverter = "cvtVSTwbFixed";
1274 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1275 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1277 "vst1", Dt, "$Vd, $Rn, $Rm",
1278 "$Rn.addr = $wb", []> {
1279 let Inst{4} = Rn{4};
1280 let DecoderMethod = "DecodeVSTInstruction";
1281 let AsmMatchConverter = "cvtVSTwbRegister";
1284 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1285 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1286 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1287 "vst1", Dt, "$Vd, $Rn!",
1288 "$Rn.addr = $wb", []> {
1289 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1290 let Inst{5-4} = Rn{5-4};
1291 let DecoderMethod = "DecodeVSTInstruction";
1292 let AsmMatchConverter = "cvtVSTwbFixed";
1294 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1295 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1297 "vst1", Dt, "$Vd, $Rn, $Rm",
1298 "$Rn.addr = $wb", []> {
1299 let Inst{5-4} = Rn{5-4};
1300 let DecoderMethod = "DecodeVSTInstruction";
1301 let AsmMatchConverter = "cvtVSTwbRegister";
1305 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1306 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1307 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1308 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1310 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1311 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1312 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1313 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1315 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1316 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1317 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1318 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1319 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1320 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1321 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1322 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1324 // ...with 3 registers
1325 class VST1D3<bits<4> op7_4, string Dt>
1326 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1327 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1328 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1330 let Inst{4} = Rn{4};
1331 let DecoderMethod = "DecodeVSTInstruction";
1333 class VST1D3WB<bits<4> op7_4, string Dt>
1334 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1335 (ins addrmode6:$Rn, am6offset:$Rm,
1336 DPR:$Vd, DPR:$src2, DPR:$src3),
1337 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1338 "$Rn.addr = $wb", []> {
1339 let Inst{4} = Rn{4};
1340 let DecoderMethod = "DecodeVSTInstruction";
1343 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1344 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1345 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1346 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1348 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1349 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1350 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1351 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1353 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1354 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1356 // ...with 4 registers
1357 class VST1D4<bits<4> op7_4, string Dt>
1358 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1359 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1360 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1363 let Inst{5-4} = Rn{5-4};
1364 let DecoderMethod = "DecodeVSTInstruction";
1366 class VST1D4WB<bits<4> op7_4, string Dt>
1367 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1368 (ins addrmode6:$Rn, am6offset:$Rm,
1369 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1370 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1371 "$Rn.addr = $wb", []> {
1372 let Inst{5-4} = Rn{5-4};
1373 let DecoderMethod = "DecodeVSTInstruction";
1376 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1377 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1378 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1379 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1381 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1382 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1383 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1384 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1386 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1387 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1389 // VST2 : Vector Store (multiple 2-element structures)
1390 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1391 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1392 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1393 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1395 let Inst{5-4} = Rn{5-4};
1396 let DecoderMethod = "DecodeVSTInstruction";
1398 class VST2Q<bits<4> op7_4, string Dt>
1399 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1400 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1401 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1404 let Inst{5-4} = Rn{5-4};
1405 let DecoderMethod = "DecodeVSTInstruction";
1408 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1409 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1410 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1412 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1413 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1414 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1416 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1417 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1418 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1420 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1421 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1422 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1424 // ...with address register writeback:
1425 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1426 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1427 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1428 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1429 "$Rn.addr = $wb", []> {
1430 let Inst{5-4} = Rn{5-4};
1431 let DecoderMethod = "DecodeVSTInstruction";
1433 class VST2QWB<bits<4> op7_4, string Dt>
1434 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1435 (ins addrmode6:$Rn, am6offset:$Rm,
1436 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1437 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1438 "$Rn.addr = $wb", []> {
1439 let Inst{5-4} = Rn{5-4};
1440 let DecoderMethod = "DecodeVSTInstruction";
1443 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1444 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1445 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1447 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1448 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1449 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1451 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1452 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1453 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1455 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1456 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1457 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1459 // ...with double-spaced registers
1460 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1461 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1462 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1463 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1464 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1465 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1467 // VST3 : Vector Store (multiple 3-element structures)
1468 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1469 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1470 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1471 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1473 let Inst{4} = Rn{4};
1474 let DecoderMethod = "DecodeVSTInstruction";
1477 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1478 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1479 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1481 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1482 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1483 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1485 // ...with address register writeback:
1486 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1487 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1488 (ins addrmode6:$Rn, am6offset:$Rm,
1489 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1490 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1491 "$Rn.addr = $wb", []> {
1492 let Inst{4} = Rn{4};
1493 let DecoderMethod = "DecodeVSTInstruction";
1496 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1497 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1498 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1500 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1501 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1502 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1504 // ...with double-spaced registers:
1505 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1506 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1507 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1508 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1509 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1510 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1512 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1513 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1514 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1516 // ...alternate versions to be allocated odd register numbers:
1517 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1518 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1519 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1521 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1522 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1523 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1525 // VST4 : Vector Store (multiple 4-element structures)
1526 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1527 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1528 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1529 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1532 let Inst{5-4} = Rn{5-4};
1533 let DecoderMethod = "DecodeVSTInstruction";
1536 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1537 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1538 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1540 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1541 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1542 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1544 // ...with address register writeback:
1545 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1546 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1547 (ins addrmode6:$Rn, am6offset:$Rm,
1548 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1549 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1550 "$Rn.addr = $wb", []> {
1551 let Inst{5-4} = Rn{5-4};
1552 let DecoderMethod = "DecodeVSTInstruction";
1555 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1556 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1557 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1559 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1560 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1561 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1563 // ...with double-spaced registers:
1564 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1565 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1566 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1567 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1568 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1569 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1571 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1572 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1573 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1575 // ...alternate versions to be allocated odd register numbers:
1576 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1577 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1578 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1580 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1581 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1582 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1584 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1586 // Classes for VST*LN pseudo-instructions with multi-register operands.
1587 // These are expanded to real instructions after register allocation.
1588 class VSTQLNPseudo<InstrItinClass itin>
1589 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1591 class VSTQLNWBPseudo<InstrItinClass itin>
1592 : PseudoNLdSt<(outs GPR:$wb),
1593 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1594 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1595 class VSTQQLNPseudo<InstrItinClass itin>
1596 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1598 class VSTQQLNWBPseudo<InstrItinClass itin>
1599 : PseudoNLdSt<(outs GPR:$wb),
1600 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1601 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1602 class VSTQQQQLNPseudo<InstrItinClass itin>
1603 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1605 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1606 : PseudoNLdSt<(outs GPR:$wb),
1607 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1608 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1610 // VST1LN : Vector Store (single element from one lane)
1611 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1612 PatFrag StoreOp, SDNode ExtractOp>
1613 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1614 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1615 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1616 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1618 let DecoderMethod = "DecodeVST1LN";
1620 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1621 PatFrag StoreOp, SDNode ExtractOp>
1622 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1623 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1624 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1625 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1627 let DecoderMethod = "DecodeVST1LN";
1629 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1630 : VSTQLNPseudo<IIC_VST1ln> {
1631 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1635 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1637 let Inst{7-5} = lane{2-0};
1639 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1641 let Inst{7-6} = lane{1-0};
1642 let Inst{4} = Rn{5};
1645 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1646 let Inst{7} = lane{0};
1647 let Inst{5-4} = Rn{5-4};
1650 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1651 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1652 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1654 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1655 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1656 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1657 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1659 // ...with address register writeback:
1660 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1661 PatFrag StoreOp, SDNode ExtractOp>
1662 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1663 (ins addrmode6:$Rn, am6offset:$Rm,
1664 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1665 "\\{$Vd[$lane]\\}, $Rn$Rm",
1667 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1668 addrmode6:$Rn, am6offset:$Rm))]> {
1669 let DecoderMethod = "DecodeVST1LN";
1671 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1672 : VSTQLNWBPseudo<IIC_VST1lnu> {
1673 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1674 addrmode6:$addr, am6offset:$offset))];
1677 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1679 let Inst{7-5} = lane{2-0};
1681 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1683 let Inst{7-6} = lane{1-0};
1684 let Inst{4} = Rn{5};
1686 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1688 let Inst{7} = lane{0};
1689 let Inst{5-4} = Rn{5-4};
1692 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1693 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1694 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1696 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1698 // VST2LN : Vector Store (single 2-element structure from one lane)
1699 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1700 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1701 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1702 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1705 let Inst{4} = Rn{4};
1706 let DecoderMethod = "DecodeVST2LN";
1709 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1710 let Inst{7-5} = lane{2-0};
1712 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1713 let Inst{7-6} = lane{1-0};
1715 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1716 let Inst{7} = lane{0};
1719 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1720 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1721 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1723 // ...with double-spaced registers:
1724 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1725 let Inst{7-6} = lane{1-0};
1726 let Inst{4} = Rn{4};
1728 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1729 let Inst{7} = lane{0};
1730 let Inst{4} = Rn{4};
1733 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1734 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1736 // ...with address register writeback:
1737 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1738 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1739 (ins addrmode6:$addr, am6offset:$offset,
1740 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1741 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1742 "$addr.addr = $wb", []> {
1743 let Inst{4} = Rn{4};
1744 let DecoderMethod = "DecodeVST2LN";
1747 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1748 let Inst{7-5} = lane{2-0};
1750 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1751 let Inst{7-6} = lane{1-0};
1753 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1754 let Inst{7} = lane{0};
1757 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1758 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1759 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1761 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1762 let Inst{7-6} = lane{1-0};
1764 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1765 let Inst{7} = lane{0};
1768 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1769 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1771 // VST3LN : Vector Store (single 3-element structure from one lane)
1772 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1773 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1774 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1775 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1776 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1778 let DecoderMethod = "DecodeVST3LN";
1781 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1782 let Inst{7-5} = lane{2-0};
1784 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1785 let Inst{7-6} = lane{1-0};
1787 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1788 let Inst{7} = lane{0};
1791 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1792 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1793 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1795 // ...with double-spaced registers:
1796 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1797 let Inst{7-6} = lane{1-0};
1799 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1800 let Inst{7} = lane{0};
1803 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1804 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1806 // ...with address register writeback:
1807 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1808 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1809 (ins addrmode6:$Rn, am6offset:$Rm,
1810 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1811 IIC_VST3lnu, "vst3", Dt,
1812 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1813 "$Rn.addr = $wb", []> {
1814 let DecoderMethod = "DecodeVST3LN";
1817 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1818 let Inst{7-5} = lane{2-0};
1820 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1821 let Inst{7-6} = lane{1-0};
1823 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1824 let Inst{7} = lane{0};
1827 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1828 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1829 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1831 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1832 let Inst{7-6} = lane{1-0};
1834 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1835 let Inst{7} = lane{0};
1838 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1839 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1841 // VST4LN : Vector Store (single 4-element structure from one lane)
1842 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1843 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1844 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1845 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1846 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1849 let Inst{4} = Rn{4};
1850 let DecoderMethod = "DecodeVST4LN";
1853 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1854 let Inst{7-5} = lane{2-0};
1856 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1857 let Inst{7-6} = lane{1-0};
1859 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1860 let Inst{7} = lane{0};
1861 let Inst{5} = Rn{5};
1864 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1865 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1866 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1868 // ...with double-spaced registers:
1869 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1870 let Inst{7-6} = lane{1-0};
1872 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1873 let Inst{7} = lane{0};
1874 let Inst{5} = Rn{5};
1877 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1878 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1880 // ...with address register writeback:
1881 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1882 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1883 (ins addrmode6:$Rn, am6offset:$Rm,
1884 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1885 IIC_VST4lnu, "vst4", Dt,
1886 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1887 "$Rn.addr = $wb", []> {
1888 let Inst{4} = Rn{4};
1889 let DecoderMethod = "DecodeVST4LN";
1892 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1893 let Inst{7-5} = lane{2-0};
1895 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1896 let Inst{7-6} = lane{1-0};
1898 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1899 let Inst{7} = lane{0};
1900 let Inst{5} = Rn{5};
1903 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1904 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1905 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1907 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1908 let Inst{7-6} = lane{1-0};
1910 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1911 let Inst{7} = lane{0};
1912 let Inst{5} = Rn{5};
1915 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1916 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1918 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1921 //===----------------------------------------------------------------------===//
1922 // NEON pattern fragments
1923 //===----------------------------------------------------------------------===//
1925 // Extract D sub-registers of Q registers.
1926 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1927 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1928 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1930 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1931 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1932 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1934 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1935 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1936 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1938 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1939 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1940 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1943 // Extract S sub-registers of Q/D registers.
1944 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1945 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1946 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1949 // Translate lane numbers from Q registers to D subregs.
1950 def SubReg_i8_lane : SDNodeXForm<imm, [{
1951 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1953 def SubReg_i16_lane : SDNodeXForm<imm, [{
1954 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1956 def SubReg_i32_lane : SDNodeXForm<imm, [{
1957 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1960 //===----------------------------------------------------------------------===//
1961 // Instruction Classes
1962 //===----------------------------------------------------------------------===//
1964 // Basic 2-register operations: double- and quad-register.
1965 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1966 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1967 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1968 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1969 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1970 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1971 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1972 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1973 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1974 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1975 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1976 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1978 // Basic 2-register intrinsics, both double- and quad-register.
1979 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1980 bits<2> op17_16, bits<5> op11_7, bit op4,
1981 InstrItinClass itin, string OpcodeStr, string Dt,
1982 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1983 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1984 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1985 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1986 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1987 bits<2> op17_16, bits<5> op11_7, bit op4,
1988 InstrItinClass itin, string OpcodeStr, string Dt,
1989 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1990 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1991 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1992 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1994 // Narrow 2-register operations.
1995 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1996 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1997 InstrItinClass itin, string OpcodeStr, string Dt,
1998 ValueType TyD, ValueType TyQ, SDNode OpNode>
1999 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2000 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2001 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2003 // Narrow 2-register intrinsics.
2004 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2005 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2006 InstrItinClass itin, string OpcodeStr, string Dt,
2007 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2008 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2009 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2010 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2012 // Long 2-register operations (currently only used for VMOVL).
2013 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2014 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2015 InstrItinClass itin, string OpcodeStr, string Dt,
2016 ValueType TyQ, ValueType TyD, SDNode OpNode>
2017 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2018 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2019 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2021 // Long 2-register intrinsics.
2022 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2023 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2024 InstrItinClass itin, string OpcodeStr, string Dt,
2025 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2026 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2027 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2028 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2030 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2031 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2032 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2033 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2034 OpcodeStr, Dt, "$Vd, $Vm",
2035 "$src1 = $Vd, $src2 = $Vm", []>;
2036 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2037 InstrItinClass itin, string OpcodeStr, string Dt>
2038 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2039 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2040 "$src1 = $Vd, $src2 = $Vm", []>;
2042 // Basic 3-register operations: double- and quad-register.
2043 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2044 InstrItinClass itin, string OpcodeStr, string Dt,
2045 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2046 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2047 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2048 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2049 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2050 let isCommutable = Commutable;
2052 // Same as N3VD but no data type.
2053 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2054 InstrItinClass itin, string OpcodeStr,
2055 ValueType ResTy, ValueType OpTy,
2056 SDNode OpNode, bit Commutable>
2057 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2058 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2059 OpcodeStr, "$Vd, $Vn, $Vm", "",
2060 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2061 let isCommutable = Commutable;
2064 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2065 InstrItinClass itin, string OpcodeStr, string Dt,
2066 ValueType Ty, SDNode ShOp>
2067 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2068 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2069 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2071 (Ty (ShOp (Ty DPR:$Vn),
2072 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2073 let isCommutable = 0;
2075 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2076 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2077 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2078 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2079 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2081 (Ty (ShOp (Ty DPR:$Vn),
2082 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2083 let isCommutable = 0;
2086 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2087 InstrItinClass itin, string OpcodeStr, string Dt,
2088 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2089 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2090 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2091 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2092 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2093 let isCommutable = Commutable;
2095 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2096 InstrItinClass itin, string OpcodeStr,
2097 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2098 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2099 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2100 OpcodeStr, "$Vd, $Vn, $Vm", "",
2101 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2102 let isCommutable = Commutable;
2104 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2105 InstrItinClass itin, string OpcodeStr, string Dt,
2106 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2107 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2108 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2109 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2110 [(set (ResTy QPR:$Vd),
2111 (ResTy (ShOp (ResTy QPR:$Vn),
2112 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2114 let isCommutable = 0;
2116 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2117 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2118 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2119 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2120 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2121 [(set (ResTy QPR:$Vd),
2122 (ResTy (ShOp (ResTy QPR:$Vn),
2123 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2125 let isCommutable = 0;
2128 // Basic 3-register intrinsics, both double- and quad-register.
2129 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2130 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2131 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2132 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2133 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2134 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2135 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2136 let isCommutable = Commutable;
2138 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2139 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2140 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2141 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2142 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2144 (Ty (IntOp (Ty DPR:$Vn),
2145 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2147 let isCommutable = 0;
2149 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2150 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2151 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2152 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2153 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2155 (Ty (IntOp (Ty DPR:$Vn),
2156 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2157 let isCommutable = 0;
2159 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2160 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2161 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2162 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2163 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2164 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2165 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2166 let isCommutable = 0;
2169 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2170 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2171 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2172 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2173 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2174 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2175 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2176 let isCommutable = Commutable;
2178 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2179 string OpcodeStr, string Dt,
2180 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2181 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2182 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2183 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2184 [(set (ResTy QPR:$Vd),
2185 (ResTy (IntOp (ResTy QPR:$Vn),
2186 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2188 let isCommutable = 0;
2190 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2191 string OpcodeStr, string Dt,
2192 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2193 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2194 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2195 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2196 [(set (ResTy QPR:$Vd),
2197 (ResTy (IntOp (ResTy QPR:$Vn),
2198 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2200 let isCommutable = 0;
2202 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2203 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2204 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2205 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2206 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2207 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2208 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2209 let isCommutable = 0;
2212 // Multiply-Add/Sub operations: double- and quad-register.
2213 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2214 InstrItinClass itin, string OpcodeStr, string Dt,
2215 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2216 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2217 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2218 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2219 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2220 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2222 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2223 string OpcodeStr, string Dt,
2224 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2225 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2227 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2229 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2231 (Ty (ShOp (Ty DPR:$src1),
2233 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2235 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2236 string OpcodeStr, string Dt,
2237 ValueType Ty, SDNode MulOp, SDNode ShOp>
2238 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2240 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2242 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2244 (Ty (ShOp (Ty DPR:$src1),
2246 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2249 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2250 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2251 SDPatternOperator MulOp, SDPatternOperator OpNode>
2252 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2253 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2254 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2255 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2256 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2257 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2258 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2259 SDPatternOperator MulOp, SDPatternOperator ShOp>
2260 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2262 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2264 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2265 [(set (ResTy QPR:$Vd),
2266 (ResTy (ShOp (ResTy QPR:$src1),
2267 (ResTy (MulOp QPR:$Vn,
2268 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2270 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2271 string OpcodeStr, string Dt,
2272 ValueType ResTy, ValueType OpTy,
2273 SDNode MulOp, SDNode ShOp>
2274 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2276 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2278 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2279 [(set (ResTy QPR:$Vd),
2280 (ResTy (ShOp (ResTy QPR:$src1),
2281 (ResTy (MulOp QPR:$Vn,
2282 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2285 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2286 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2287 InstrItinClass itin, string OpcodeStr, string Dt,
2288 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2289 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2290 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2291 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2292 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2293 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2294 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2295 InstrItinClass itin, string OpcodeStr, string Dt,
2296 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2297 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2298 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2299 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2300 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2301 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2303 // Neon 3-argument intrinsics, both double- and quad-register.
2304 // The destination register is also used as the first source operand register.
2305 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2306 InstrItinClass itin, string OpcodeStr, string Dt,
2307 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2308 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2309 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2310 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2311 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2312 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2313 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2314 InstrItinClass itin, string OpcodeStr, string Dt,
2315 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2316 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2317 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2318 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2319 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2320 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2322 // Long Multiply-Add/Sub operations.
2323 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2324 InstrItinClass itin, string OpcodeStr, string Dt,
2325 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2326 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2327 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2328 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2329 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2330 (TyQ (MulOp (TyD DPR:$Vn),
2331 (TyD DPR:$Vm)))))]>;
2332 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2333 InstrItinClass itin, string OpcodeStr, string Dt,
2334 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2335 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2336 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2338 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2340 (OpNode (TyQ QPR:$src1),
2341 (TyQ (MulOp (TyD DPR:$Vn),
2342 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2344 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
2346 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2347 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2348 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2350 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2352 (OpNode (TyQ QPR:$src1),
2353 (TyQ (MulOp (TyD DPR:$Vn),
2354 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2357 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2358 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2359 InstrItinClass itin, string OpcodeStr, string Dt,
2360 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2362 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2363 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2364 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2365 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2366 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2367 (TyD DPR:$Vm)))))))]>;
2369 // Neon Long 3-argument intrinsic. The destination register is
2370 // a quad-register and is also used as the first source operand register.
2371 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2372 InstrItinClass itin, string OpcodeStr, string Dt,
2373 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2374 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2375 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2376 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2378 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2379 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2380 string OpcodeStr, string Dt,
2381 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2382 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2384 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2386 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2387 [(set (ResTy QPR:$Vd),
2388 (ResTy (IntOp (ResTy QPR:$src1),
2390 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2392 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2393 InstrItinClass itin, string OpcodeStr, string Dt,
2394 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2395 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2397 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2399 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2400 [(set (ResTy QPR:$Vd),
2401 (ResTy (IntOp (ResTy QPR:$src1),
2403 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2406 // Narrowing 3-register intrinsics.
2407 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2408 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2409 Intrinsic IntOp, bit Commutable>
2410 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2411 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2412 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2413 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2414 let isCommutable = Commutable;
2417 // Long 3-register operations.
2418 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2419 InstrItinClass itin, string OpcodeStr, string Dt,
2420 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2421 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2422 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2423 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2424 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2425 let isCommutable = Commutable;
2427 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2428 InstrItinClass itin, string OpcodeStr, string Dt,
2429 ValueType TyQ, ValueType TyD, SDNode OpNode>
2430 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2431 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2432 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2434 (TyQ (OpNode (TyD DPR:$Vn),
2435 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2436 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2437 InstrItinClass itin, string OpcodeStr, string Dt,
2438 ValueType TyQ, ValueType TyD, SDNode OpNode>
2439 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2440 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2441 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2443 (TyQ (OpNode (TyD DPR:$Vn),
2444 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2446 // Long 3-register operations with explicitly extended operands.
2447 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2448 InstrItinClass itin, string OpcodeStr, string Dt,
2449 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2451 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2452 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2453 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2454 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2455 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2456 let isCommutable = Commutable;
2459 // Long 3-register intrinsics with explicit extend (VABDL).
2460 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2461 InstrItinClass itin, string OpcodeStr, string Dt,
2462 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2464 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2465 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2466 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2467 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2468 (TyD DPR:$Vm))))))]> {
2469 let isCommutable = Commutable;
2472 // Long 3-register intrinsics.
2473 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2474 InstrItinClass itin, string OpcodeStr, string Dt,
2475 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2476 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2477 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2478 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2479 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2480 let isCommutable = Commutable;
2482 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2483 string OpcodeStr, string Dt,
2484 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2485 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2486 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2487 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2488 [(set (ResTy QPR:$Vd),
2489 (ResTy (IntOp (OpTy DPR:$Vn),
2490 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2492 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2493 InstrItinClass itin, string OpcodeStr, string Dt,
2494 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2495 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2496 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2497 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2498 [(set (ResTy QPR:$Vd),
2499 (ResTy (IntOp (OpTy DPR:$Vn),
2500 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2503 // Wide 3-register operations.
2504 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2505 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2506 SDNode OpNode, SDNode ExtOp, bit Commutable>
2507 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2508 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2509 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2510 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2511 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2512 let isCommutable = Commutable;
2515 // Pairwise long 2-register intrinsics, both double- and quad-register.
2516 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2517 bits<2> op17_16, bits<5> op11_7, bit op4,
2518 string OpcodeStr, string Dt,
2519 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2520 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2521 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2522 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2523 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2524 bits<2> op17_16, bits<5> op11_7, bit op4,
2525 string OpcodeStr, string Dt,
2526 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2527 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2528 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2529 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2531 // Pairwise long 2-register accumulate intrinsics,
2532 // both double- and quad-register.
2533 // The destination register is also used as the first source operand register.
2534 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2535 bits<2> op17_16, bits<5> op11_7, bit op4,
2536 string OpcodeStr, string Dt,
2537 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2538 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2539 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2540 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2541 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2542 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2543 bits<2> op17_16, bits<5> op11_7, bit op4,
2544 string OpcodeStr, string Dt,
2545 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2546 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2547 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2548 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2549 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2551 // Shift by immediate,
2552 // both double- and quad-register.
2553 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2554 Format f, InstrItinClass itin, Operand ImmTy,
2555 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2556 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2557 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2558 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2559 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2560 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2561 Format f, InstrItinClass itin, Operand ImmTy,
2562 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2563 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2564 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2565 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2566 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2568 // Long shift by immediate.
2569 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2570 string OpcodeStr, string Dt,
2571 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2572 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2573 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2574 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2575 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2576 (i32 imm:$SIMM))))]>;
2578 // Narrow shift by immediate.
2579 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2580 InstrItinClass itin, string OpcodeStr, string Dt,
2581 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2582 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2583 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2584 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2585 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2586 (i32 imm:$SIMM))))]>;
2588 // Shift right by immediate and accumulate,
2589 // both double- and quad-register.
2590 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2591 Operand ImmTy, string OpcodeStr, string Dt,
2592 ValueType Ty, SDNode ShOp>
2593 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2594 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2595 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2596 [(set DPR:$Vd, (Ty (add DPR:$src1,
2597 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2598 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2599 Operand ImmTy, string OpcodeStr, string Dt,
2600 ValueType Ty, SDNode ShOp>
2601 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2602 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2603 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2604 [(set QPR:$Vd, (Ty (add QPR:$src1,
2605 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2607 // Shift by immediate and insert,
2608 // both double- and quad-register.
2609 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2610 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2611 ValueType Ty,SDNode ShOp>
2612 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2613 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2614 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2615 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2616 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2617 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2618 ValueType Ty,SDNode ShOp>
2619 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2620 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2621 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2622 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2624 // Convert, with fractional bits immediate,
2625 // both double- and quad-register.
2626 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2627 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2629 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2630 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2631 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2632 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2633 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2634 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2636 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2637 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2638 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2639 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2641 //===----------------------------------------------------------------------===//
2643 //===----------------------------------------------------------------------===//
2645 // Abbreviations used in multiclass suffixes:
2646 // Q = quarter int (8 bit) elements
2647 // H = half int (16 bit) elements
2648 // S = single int (32 bit) elements
2649 // D = double int (64 bit) elements
2651 // Neon 2-register vector operations and intrinsics.
2653 // Neon 2-register comparisons.
2654 // source operand element sizes of 8, 16 and 32 bits:
2655 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2656 bits<5> op11_7, bit op4, string opc, string Dt,
2657 string asm, SDNode OpNode> {
2658 // 64-bit vector types.
2659 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2660 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2661 opc, !strconcat(Dt, "8"), asm, "",
2662 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2663 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2664 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2665 opc, !strconcat(Dt, "16"), asm, "",
2666 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2667 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2668 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2669 opc, !strconcat(Dt, "32"), asm, "",
2670 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2671 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2672 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2673 opc, "f32", asm, "",
2674 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2675 let Inst{10} = 1; // overwrite F = 1
2678 // 128-bit vector types.
2679 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2680 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2681 opc, !strconcat(Dt, "8"), asm, "",
2682 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2683 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2684 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2685 opc, !strconcat(Dt, "16"), asm, "",
2686 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2687 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2688 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2689 opc, !strconcat(Dt, "32"), asm, "",
2690 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2691 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2692 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2693 opc, "f32", asm, "",
2694 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2695 let Inst{10} = 1; // overwrite F = 1
2700 // Neon 2-register vector intrinsics,
2701 // element sizes of 8, 16 and 32 bits:
2702 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2703 bits<5> op11_7, bit op4,
2704 InstrItinClass itinD, InstrItinClass itinQ,
2705 string OpcodeStr, string Dt, Intrinsic IntOp> {
2706 // 64-bit vector types.
2707 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2708 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2709 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2710 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2711 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2712 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2714 // 128-bit vector types.
2715 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2716 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2717 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2718 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2719 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2720 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2724 // Neon Narrowing 2-register vector operations,
2725 // source operand element sizes of 16, 32 and 64 bits:
2726 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2727 bits<5> op11_7, bit op6, bit op4,
2728 InstrItinClass itin, string OpcodeStr, string Dt,
2730 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2731 itin, OpcodeStr, !strconcat(Dt, "16"),
2732 v8i8, v8i16, OpNode>;
2733 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2734 itin, OpcodeStr, !strconcat(Dt, "32"),
2735 v4i16, v4i32, OpNode>;
2736 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2737 itin, OpcodeStr, !strconcat(Dt, "64"),
2738 v2i32, v2i64, OpNode>;
2741 // Neon Narrowing 2-register vector intrinsics,
2742 // source operand element sizes of 16, 32 and 64 bits:
2743 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2744 bits<5> op11_7, bit op6, bit op4,
2745 InstrItinClass itin, string OpcodeStr, string Dt,
2747 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2748 itin, OpcodeStr, !strconcat(Dt, "16"),
2749 v8i8, v8i16, IntOp>;
2750 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2751 itin, OpcodeStr, !strconcat(Dt, "32"),
2752 v4i16, v4i32, IntOp>;
2753 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2754 itin, OpcodeStr, !strconcat(Dt, "64"),
2755 v2i32, v2i64, IntOp>;
2759 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2760 // source operand element sizes of 16, 32 and 64 bits:
2761 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2762 string OpcodeStr, string Dt, SDNode OpNode> {
2763 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2764 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2765 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2766 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2767 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2768 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2772 // Neon 3-register vector operations.
2774 // First with only element sizes of 8, 16 and 32 bits:
2775 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2776 InstrItinClass itinD16, InstrItinClass itinD32,
2777 InstrItinClass itinQ16, InstrItinClass itinQ32,
2778 string OpcodeStr, string Dt,
2779 SDNode OpNode, bit Commutable = 0> {
2780 // 64-bit vector types.
2781 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2782 OpcodeStr, !strconcat(Dt, "8"),
2783 v8i8, v8i8, OpNode, Commutable>;
2784 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2785 OpcodeStr, !strconcat(Dt, "16"),
2786 v4i16, v4i16, OpNode, Commutable>;
2787 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2788 OpcodeStr, !strconcat(Dt, "32"),
2789 v2i32, v2i32, OpNode, Commutable>;
2791 // 128-bit vector types.
2792 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2793 OpcodeStr, !strconcat(Dt, "8"),
2794 v16i8, v16i8, OpNode, Commutable>;
2795 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2796 OpcodeStr, !strconcat(Dt, "16"),
2797 v8i16, v8i16, OpNode, Commutable>;
2798 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2799 OpcodeStr, !strconcat(Dt, "32"),
2800 v4i32, v4i32, OpNode, Commutable>;
2803 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2804 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2806 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2808 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2809 v8i16, v4i16, ShOp>;
2810 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2811 v4i32, v2i32, ShOp>;
2814 // ....then also with element size 64 bits:
2815 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2816 InstrItinClass itinD, InstrItinClass itinQ,
2817 string OpcodeStr, string Dt,
2818 SDNode OpNode, bit Commutable = 0>
2819 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2820 OpcodeStr, Dt, OpNode, Commutable> {
2821 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2822 OpcodeStr, !strconcat(Dt, "64"),
2823 v1i64, v1i64, OpNode, Commutable>;
2824 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2825 OpcodeStr, !strconcat(Dt, "64"),
2826 v2i64, v2i64, OpNode, Commutable>;
2830 // Neon 3-register vector intrinsics.
2832 // First with only element sizes of 16 and 32 bits:
2833 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2834 InstrItinClass itinD16, InstrItinClass itinD32,
2835 InstrItinClass itinQ16, InstrItinClass itinQ32,
2836 string OpcodeStr, string Dt,
2837 Intrinsic IntOp, bit Commutable = 0> {
2838 // 64-bit vector types.
2839 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2840 OpcodeStr, !strconcat(Dt, "16"),
2841 v4i16, v4i16, IntOp, Commutable>;
2842 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2843 OpcodeStr, !strconcat(Dt, "32"),
2844 v2i32, v2i32, IntOp, Commutable>;
2846 // 128-bit vector types.
2847 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2848 OpcodeStr, !strconcat(Dt, "16"),
2849 v8i16, v8i16, IntOp, Commutable>;
2850 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2851 OpcodeStr, !strconcat(Dt, "32"),
2852 v4i32, v4i32, IntOp, Commutable>;
2854 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2855 InstrItinClass itinD16, InstrItinClass itinD32,
2856 InstrItinClass itinQ16, InstrItinClass itinQ32,
2857 string OpcodeStr, string Dt,
2859 // 64-bit vector types.
2860 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2861 OpcodeStr, !strconcat(Dt, "16"),
2862 v4i16, v4i16, IntOp>;
2863 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2864 OpcodeStr, !strconcat(Dt, "32"),
2865 v2i32, v2i32, IntOp>;
2867 // 128-bit vector types.
2868 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2869 OpcodeStr, !strconcat(Dt, "16"),
2870 v8i16, v8i16, IntOp>;
2871 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2872 OpcodeStr, !strconcat(Dt, "32"),
2873 v4i32, v4i32, IntOp>;
2876 multiclass N3VIntSL_HS<bits<4> op11_8,
2877 InstrItinClass itinD16, InstrItinClass itinD32,
2878 InstrItinClass itinQ16, InstrItinClass itinQ32,
2879 string OpcodeStr, string Dt, Intrinsic IntOp> {
2880 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2881 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2882 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2883 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2884 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2885 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2886 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2887 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2890 // ....then also with element size of 8 bits:
2891 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2892 InstrItinClass itinD16, InstrItinClass itinD32,
2893 InstrItinClass itinQ16, InstrItinClass itinQ32,
2894 string OpcodeStr, string Dt,
2895 Intrinsic IntOp, bit Commutable = 0>
2896 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2897 OpcodeStr, Dt, IntOp, Commutable> {
2898 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2899 OpcodeStr, !strconcat(Dt, "8"),
2900 v8i8, v8i8, IntOp, Commutable>;
2901 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2902 OpcodeStr, !strconcat(Dt, "8"),
2903 v16i8, v16i8, IntOp, Commutable>;
2905 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2906 InstrItinClass itinD16, InstrItinClass itinD32,
2907 InstrItinClass itinQ16, InstrItinClass itinQ32,
2908 string OpcodeStr, string Dt,
2910 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2911 OpcodeStr, Dt, IntOp> {
2912 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2913 OpcodeStr, !strconcat(Dt, "8"),
2915 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2916 OpcodeStr, !strconcat(Dt, "8"),
2917 v16i8, v16i8, IntOp>;
2921 // ....then also with element size of 64 bits:
2922 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2923 InstrItinClass itinD16, InstrItinClass itinD32,
2924 InstrItinClass itinQ16, InstrItinClass itinQ32,
2925 string OpcodeStr, string Dt,
2926 Intrinsic IntOp, bit Commutable = 0>
2927 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2928 OpcodeStr, Dt, IntOp, Commutable> {
2929 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2930 OpcodeStr, !strconcat(Dt, "64"),
2931 v1i64, v1i64, IntOp, Commutable>;
2932 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2933 OpcodeStr, !strconcat(Dt, "64"),
2934 v2i64, v2i64, IntOp, Commutable>;
2936 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2937 InstrItinClass itinD16, InstrItinClass itinD32,
2938 InstrItinClass itinQ16, InstrItinClass itinQ32,
2939 string OpcodeStr, string Dt,
2941 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2942 OpcodeStr, Dt, IntOp> {
2943 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2944 OpcodeStr, !strconcat(Dt, "64"),
2945 v1i64, v1i64, IntOp>;
2946 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2947 OpcodeStr, !strconcat(Dt, "64"),
2948 v2i64, v2i64, IntOp>;
2951 // Neon Narrowing 3-register vector intrinsics,
2952 // source operand element sizes of 16, 32 and 64 bits:
2953 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2954 string OpcodeStr, string Dt,
2955 Intrinsic IntOp, bit Commutable = 0> {
2956 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2957 OpcodeStr, !strconcat(Dt, "16"),
2958 v8i8, v8i16, IntOp, Commutable>;
2959 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2960 OpcodeStr, !strconcat(Dt, "32"),
2961 v4i16, v4i32, IntOp, Commutable>;
2962 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2963 OpcodeStr, !strconcat(Dt, "64"),
2964 v2i32, v2i64, IntOp, Commutable>;
2968 // Neon Long 3-register vector operations.
2970 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2971 InstrItinClass itin16, InstrItinClass itin32,
2972 string OpcodeStr, string Dt,
2973 SDNode OpNode, bit Commutable = 0> {
2974 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2975 OpcodeStr, !strconcat(Dt, "8"),
2976 v8i16, v8i8, OpNode, Commutable>;
2977 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2978 OpcodeStr, !strconcat(Dt, "16"),
2979 v4i32, v4i16, OpNode, Commutable>;
2980 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2981 OpcodeStr, !strconcat(Dt, "32"),
2982 v2i64, v2i32, OpNode, Commutable>;
2985 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2986 InstrItinClass itin, string OpcodeStr, string Dt,
2988 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2989 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2990 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2991 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2994 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2995 InstrItinClass itin16, InstrItinClass itin32,
2996 string OpcodeStr, string Dt,
2997 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2998 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2999 OpcodeStr, !strconcat(Dt, "8"),
3000 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3001 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3002 OpcodeStr, !strconcat(Dt, "16"),
3003 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3004 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3005 OpcodeStr, !strconcat(Dt, "32"),
3006 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3009 // Neon Long 3-register vector intrinsics.
3011 // First with only element sizes of 16 and 32 bits:
3012 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3013 InstrItinClass itin16, InstrItinClass itin32,
3014 string OpcodeStr, string Dt,
3015 Intrinsic IntOp, bit Commutable = 0> {
3016 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3017 OpcodeStr, !strconcat(Dt, "16"),
3018 v4i32, v4i16, IntOp, Commutable>;
3019 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3020 OpcodeStr, !strconcat(Dt, "32"),
3021 v2i64, v2i32, IntOp, Commutable>;
3024 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3025 InstrItinClass itin, string OpcodeStr, string Dt,
3027 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3028 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3029 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3030 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3033 // ....then also with element size of 8 bits:
3034 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3035 InstrItinClass itin16, InstrItinClass itin32,
3036 string OpcodeStr, string Dt,
3037 Intrinsic IntOp, bit Commutable = 0>
3038 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3039 IntOp, Commutable> {
3040 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3041 OpcodeStr, !strconcat(Dt, "8"),
3042 v8i16, v8i8, IntOp, Commutable>;
3045 // ....with explicit extend (VABDL).
3046 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3047 InstrItinClass itin, string OpcodeStr, string Dt,
3048 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3049 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3050 OpcodeStr, !strconcat(Dt, "8"),
3051 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3052 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3053 OpcodeStr, !strconcat(Dt, "16"),
3054 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3055 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3056 OpcodeStr, !strconcat(Dt, "32"),
3057 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3061 // Neon Wide 3-register vector intrinsics,
3062 // source operand element sizes of 8, 16 and 32 bits:
3063 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3064 string OpcodeStr, string Dt,
3065 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3066 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3067 OpcodeStr, !strconcat(Dt, "8"),
3068 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3069 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3070 OpcodeStr, !strconcat(Dt, "16"),
3071 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3072 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3073 OpcodeStr, !strconcat(Dt, "32"),
3074 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3078 // Neon Multiply-Op vector operations,
3079 // element sizes of 8, 16 and 32 bits:
3080 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3081 InstrItinClass itinD16, InstrItinClass itinD32,
3082 InstrItinClass itinQ16, InstrItinClass itinQ32,
3083 string OpcodeStr, string Dt, SDNode OpNode> {
3084 // 64-bit vector types.
3085 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3086 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3087 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3088 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3089 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3090 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3092 // 128-bit vector types.
3093 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3094 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3095 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3096 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3097 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3098 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3101 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3102 InstrItinClass itinD16, InstrItinClass itinD32,
3103 InstrItinClass itinQ16, InstrItinClass itinQ32,
3104 string OpcodeStr, string Dt, SDNode ShOp> {
3105 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3106 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3107 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3108 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3109 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3110 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3112 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3113 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3117 // Neon Intrinsic-Op vector operations,
3118 // element sizes of 8, 16 and 32 bits:
3119 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3120 InstrItinClass itinD, InstrItinClass itinQ,
3121 string OpcodeStr, string Dt, Intrinsic IntOp,
3123 // 64-bit vector types.
3124 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3125 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3126 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3127 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3128 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3129 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3131 // 128-bit vector types.
3132 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3133 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3134 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3135 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3136 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3137 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3140 // Neon 3-argument intrinsics,
3141 // element sizes of 8, 16 and 32 bits:
3142 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3143 InstrItinClass itinD, InstrItinClass itinQ,
3144 string OpcodeStr, string Dt, Intrinsic IntOp> {
3145 // 64-bit vector types.
3146 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3147 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3148 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3149 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3150 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3151 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3153 // 128-bit vector types.
3154 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3155 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3156 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3157 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3158 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3159 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3163 // Neon Long Multiply-Op vector operations,
3164 // element sizes of 8, 16 and 32 bits:
3165 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3166 InstrItinClass itin16, InstrItinClass itin32,
3167 string OpcodeStr, string Dt, SDNode MulOp,
3169 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3170 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3171 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3172 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3173 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3174 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3177 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3178 string Dt, SDNode MulOp, SDNode OpNode> {
3179 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3180 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3181 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3182 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3186 // Neon Long 3-argument intrinsics.
3188 // First with only element sizes of 16 and 32 bits:
3189 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3190 InstrItinClass itin16, InstrItinClass itin32,
3191 string OpcodeStr, string Dt, Intrinsic IntOp> {
3192 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3193 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3194 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3195 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3198 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3199 string OpcodeStr, string Dt, Intrinsic IntOp> {
3200 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3201 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3202 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3203 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3206 // ....then also with element size of 8 bits:
3207 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3208 InstrItinClass itin16, InstrItinClass itin32,
3209 string OpcodeStr, string Dt, Intrinsic IntOp>
3210 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3211 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3212 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3215 // ....with explicit extend (VABAL).
3216 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3217 InstrItinClass itin, string OpcodeStr, string Dt,
3218 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3219 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3220 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3221 IntOp, ExtOp, OpNode>;
3222 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3223 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3224 IntOp, ExtOp, OpNode>;
3225 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3226 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3227 IntOp, ExtOp, OpNode>;
3231 // Neon Pairwise long 2-register intrinsics,
3232 // element sizes of 8, 16 and 32 bits:
3233 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3234 bits<5> op11_7, bit op4,
3235 string OpcodeStr, string Dt, Intrinsic IntOp> {
3236 // 64-bit vector types.
3237 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3238 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3239 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3240 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3241 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3242 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3244 // 128-bit vector types.
3245 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3246 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3247 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3248 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3249 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3250 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3254 // Neon Pairwise long 2-register accumulate intrinsics,
3255 // element sizes of 8, 16 and 32 bits:
3256 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3257 bits<5> op11_7, bit op4,
3258 string OpcodeStr, string Dt, Intrinsic IntOp> {
3259 // 64-bit vector types.
3260 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3261 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3262 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3263 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3264 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3265 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3267 // 128-bit vector types.
3268 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3269 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3270 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3271 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3272 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3273 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3277 // Neon 2-register vector shift by immediate,
3278 // with f of either N2RegVShLFrm or N2RegVShRFrm
3279 // element sizes of 8, 16, 32 and 64 bits:
3280 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3281 InstrItinClass itin, string OpcodeStr, string Dt,
3283 // 64-bit vector types.
3284 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3285 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3286 let Inst{21-19} = 0b001; // imm6 = 001xxx
3288 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3289 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3290 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3292 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3293 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3294 let Inst{21} = 0b1; // imm6 = 1xxxxx
3296 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3297 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3300 // 128-bit vector types.
3301 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3302 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3303 let Inst{21-19} = 0b001; // imm6 = 001xxx
3305 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3306 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3307 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3309 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3310 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3311 let Inst{21} = 0b1; // imm6 = 1xxxxx
3313 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3314 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3317 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3318 InstrItinClass itin, string OpcodeStr, string Dt,
3320 // 64-bit vector types.
3321 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3322 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3323 let Inst{21-19} = 0b001; // imm6 = 001xxx
3325 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3326 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3327 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3329 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3330 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3331 let Inst{21} = 0b1; // imm6 = 1xxxxx
3333 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3334 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3337 // 128-bit vector types.
3338 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3339 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3340 let Inst{21-19} = 0b001; // imm6 = 001xxx
3342 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3343 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3344 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3346 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3347 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3348 let Inst{21} = 0b1; // imm6 = 1xxxxx
3350 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3351 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3355 // Neon Shift-Accumulate vector operations,
3356 // element sizes of 8, 16, 32 and 64 bits:
3357 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3358 string OpcodeStr, string Dt, SDNode ShOp> {
3359 // 64-bit vector types.
3360 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3361 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3362 let Inst{21-19} = 0b001; // imm6 = 001xxx
3364 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3365 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3366 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3368 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3369 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3370 let Inst{21} = 0b1; // imm6 = 1xxxxx
3372 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3373 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3376 // 128-bit vector types.
3377 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3378 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3379 let Inst{21-19} = 0b001; // imm6 = 001xxx
3381 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3382 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3383 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3385 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3386 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3387 let Inst{21} = 0b1; // imm6 = 1xxxxx
3389 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3390 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3394 // Neon Shift-Insert vector operations,
3395 // with f of either N2RegVShLFrm or N2RegVShRFrm
3396 // element sizes of 8, 16, 32 and 64 bits:
3397 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3399 // 64-bit vector types.
3400 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3401 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3402 let Inst{21-19} = 0b001; // imm6 = 001xxx
3404 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3405 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3406 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3408 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3409 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3410 let Inst{21} = 0b1; // imm6 = 1xxxxx
3412 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3413 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3416 // 128-bit vector types.
3417 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3418 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3419 let Inst{21-19} = 0b001; // imm6 = 001xxx
3421 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3422 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3423 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3425 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3426 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3427 let Inst{21} = 0b1; // imm6 = 1xxxxx
3429 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3430 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3433 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3435 // 64-bit vector types.
3436 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3437 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3438 let Inst{21-19} = 0b001; // imm6 = 001xxx
3440 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3441 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3442 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3444 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3445 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3446 let Inst{21} = 0b1; // imm6 = 1xxxxx
3448 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3449 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3452 // 128-bit vector types.
3453 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3454 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3455 let Inst{21-19} = 0b001; // imm6 = 001xxx
3457 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3458 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3459 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3461 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3462 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3463 let Inst{21} = 0b1; // imm6 = 1xxxxx
3465 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3466 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3470 // Neon Shift Long operations,
3471 // element sizes of 8, 16, 32 bits:
3472 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3473 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3474 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3475 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3476 let Inst{21-19} = 0b001; // imm6 = 001xxx
3478 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3479 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3480 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3482 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3483 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3484 let Inst{21} = 0b1; // imm6 = 1xxxxx
3488 // Neon Shift Narrow operations,
3489 // element sizes of 16, 32, 64 bits:
3490 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3491 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3493 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3494 OpcodeStr, !strconcat(Dt, "16"),
3495 v8i8, v8i16, shr_imm8, OpNode> {
3496 let Inst{21-19} = 0b001; // imm6 = 001xxx
3498 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3499 OpcodeStr, !strconcat(Dt, "32"),
3500 v4i16, v4i32, shr_imm16, OpNode> {
3501 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3503 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3504 OpcodeStr, !strconcat(Dt, "64"),
3505 v2i32, v2i64, shr_imm32, OpNode> {
3506 let Inst{21} = 0b1; // imm6 = 1xxxxx
3510 //===----------------------------------------------------------------------===//
3511 // Instruction Definitions.
3512 //===----------------------------------------------------------------------===//
3514 // Vector Add Operations.
3516 // VADD : Vector Add (integer and floating-point)
3517 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3519 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3520 v2f32, v2f32, fadd, 1>;
3521 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3522 v4f32, v4f32, fadd, 1>;
3523 // VADDL : Vector Add Long (Q = D + D)
3524 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3525 "vaddl", "s", add, sext, 1>;
3526 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3527 "vaddl", "u", add, zext, 1>;
3528 // VADDW : Vector Add Wide (Q = Q + D)
3529 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3530 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3531 // VHADD : Vector Halving Add
3532 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3533 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3534 "vhadd", "s", int_arm_neon_vhadds, 1>;
3535 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3536 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3537 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3538 // VRHADD : Vector Rounding Halving Add
3539 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3540 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3541 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3542 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3543 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3544 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3545 // VQADD : Vector Saturating Add
3546 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3547 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3548 "vqadd", "s", int_arm_neon_vqadds, 1>;
3549 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3550 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3551 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3552 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3553 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3554 int_arm_neon_vaddhn, 1>;
3555 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3556 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3557 int_arm_neon_vraddhn, 1>;
3559 // Vector Multiply Operations.
3561 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3562 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3563 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3564 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3565 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3566 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3567 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3568 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3569 v2f32, v2f32, fmul, 1>;
3570 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3571 v4f32, v4f32, fmul, 1>;
3572 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3573 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3574 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3577 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3578 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3579 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3580 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3581 (DSubReg_i16_reg imm:$lane))),
3582 (SubReg_i16_lane imm:$lane)))>;
3583 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3584 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3585 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3586 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3587 (DSubReg_i32_reg imm:$lane))),
3588 (SubReg_i32_lane imm:$lane)))>;
3589 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3590 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3591 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3592 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3593 (DSubReg_i32_reg imm:$lane))),
3594 (SubReg_i32_lane imm:$lane)))>;
3596 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3597 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3598 IIC_VMULi16Q, IIC_VMULi32Q,
3599 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3600 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3601 IIC_VMULi16Q, IIC_VMULi32Q,
3602 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3603 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3604 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3606 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3607 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3608 (DSubReg_i16_reg imm:$lane))),
3609 (SubReg_i16_lane imm:$lane)))>;
3610 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3611 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3613 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3614 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3615 (DSubReg_i32_reg imm:$lane))),
3616 (SubReg_i32_lane imm:$lane)))>;
3618 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3619 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3620 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3621 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3622 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3623 IIC_VMULi16Q, IIC_VMULi32Q,
3624 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3625 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3626 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3628 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3629 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3630 (DSubReg_i16_reg imm:$lane))),
3631 (SubReg_i16_lane imm:$lane)))>;
3632 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3633 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3635 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3636 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3637 (DSubReg_i32_reg imm:$lane))),
3638 (SubReg_i32_lane imm:$lane)))>;
3640 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3641 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3642 "vmull", "s", NEONvmulls, 1>;
3643 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3644 "vmull", "u", NEONvmullu, 1>;
3645 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3646 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3647 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3648 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3650 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3651 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3652 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3653 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3654 "vqdmull", "s", int_arm_neon_vqdmull>;
3656 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3658 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3659 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3660 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3661 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3662 v2f32, fmul_su, fadd_mlx>,
3663 Requires<[HasNEON, UseFPVMLx]>;
3664 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3665 v4f32, fmul_su, fadd_mlx>,
3666 Requires<[HasNEON, UseFPVMLx]>;
3667 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3668 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3669 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3670 v2f32, fmul_su, fadd_mlx>,
3671 Requires<[HasNEON, UseFPVMLx]>;
3672 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3673 v4f32, v2f32, fmul_su, fadd_mlx>,
3674 Requires<[HasNEON, UseFPVMLx]>;
3676 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3677 (mul (v8i16 QPR:$src2),
3678 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3679 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3680 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3681 (DSubReg_i16_reg imm:$lane))),
3682 (SubReg_i16_lane imm:$lane)))>;
3684 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3685 (mul (v4i32 QPR:$src2),
3686 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3687 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3688 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3689 (DSubReg_i32_reg imm:$lane))),
3690 (SubReg_i32_lane imm:$lane)))>;
3692 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3693 (fmul_su (v4f32 QPR:$src2),
3694 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3695 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3697 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3698 (DSubReg_i32_reg imm:$lane))),
3699 (SubReg_i32_lane imm:$lane)))>,
3700 Requires<[HasNEON, UseFPVMLx]>;
3702 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3703 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3704 "vmlal", "s", NEONvmulls, add>;
3705 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3706 "vmlal", "u", NEONvmullu, add>;
3708 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3709 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3711 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3712 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3713 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3714 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3716 // VMLS : Vector Multiply Subtract (integer and floating-point)
3717 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3718 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3719 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3720 v2f32, fmul_su, fsub_mlx>,
3721 Requires<[HasNEON, UseFPVMLx]>;
3722 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3723 v4f32, fmul_su, fsub_mlx>,
3724 Requires<[HasNEON, UseFPVMLx]>;
3725 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3726 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3727 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3728 v2f32, fmul_su, fsub_mlx>,
3729 Requires<[HasNEON, UseFPVMLx]>;
3730 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3731 v4f32, v2f32, fmul_su, fsub_mlx>,
3732 Requires<[HasNEON, UseFPVMLx]>;
3734 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3735 (mul (v8i16 QPR:$src2),
3736 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3737 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3738 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3739 (DSubReg_i16_reg imm:$lane))),
3740 (SubReg_i16_lane imm:$lane)))>;
3742 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3743 (mul (v4i32 QPR:$src2),
3744 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3745 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3746 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3747 (DSubReg_i32_reg imm:$lane))),
3748 (SubReg_i32_lane imm:$lane)))>;
3750 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3751 (fmul_su (v4f32 QPR:$src2),
3752 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3753 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3754 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3755 (DSubReg_i32_reg imm:$lane))),
3756 (SubReg_i32_lane imm:$lane)))>,
3757 Requires<[HasNEON, UseFPVMLx]>;
3759 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3760 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3761 "vmlsl", "s", NEONvmulls, sub>;
3762 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3763 "vmlsl", "u", NEONvmullu, sub>;
3765 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3766 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3768 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3769 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3770 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3771 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3773 // Vector Subtract Operations.
3775 // VSUB : Vector Subtract (integer and floating-point)
3776 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3777 "vsub", "i", sub, 0>;
3778 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3779 v2f32, v2f32, fsub, 0>;
3780 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3781 v4f32, v4f32, fsub, 0>;
3782 // VSUBL : Vector Subtract Long (Q = D - D)
3783 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3784 "vsubl", "s", sub, sext, 0>;
3785 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3786 "vsubl", "u", sub, zext, 0>;
3787 // VSUBW : Vector Subtract Wide (Q = Q - D)
3788 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3789 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3790 // VHSUB : Vector Halving Subtract
3791 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3792 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3793 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3794 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3795 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3796 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3797 // VQSUB : Vector Saturing Subtract
3798 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3799 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3800 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3801 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3802 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3803 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3804 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3805 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3806 int_arm_neon_vsubhn, 0>;
3807 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3808 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3809 int_arm_neon_vrsubhn, 0>;
3811 // Vector Comparisons.
3813 // VCEQ : Vector Compare Equal
3814 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3815 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3816 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3818 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3821 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3822 "$Vd, $Vm, #0", NEONvceqz>;
3824 // VCGE : Vector Compare Greater Than or Equal
3825 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3826 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3827 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3828 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3829 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3831 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3834 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3835 "$Vd, $Vm, #0", NEONvcgez>;
3836 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3837 "$Vd, $Vm, #0", NEONvclez>;
3839 // VCGT : Vector Compare Greater Than
3840 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3841 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3842 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3843 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3844 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3846 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3849 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3850 "$Vd, $Vm, #0", NEONvcgtz>;
3851 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3852 "$Vd, $Vm, #0", NEONvcltz>;
3854 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3855 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3856 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3857 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3858 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3859 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3860 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3861 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3862 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3863 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3864 // VTST : Vector Test Bits
3865 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3866 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3868 // Vector Bitwise Operations.
3870 def vnotd : PatFrag<(ops node:$in),
3871 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3872 def vnotq : PatFrag<(ops node:$in),
3873 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3876 // VAND : Vector Bitwise AND
3877 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3878 v2i32, v2i32, and, 1>;
3879 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3880 v4i32, v4i32, and, 1>;
3882 // VEOR : Vector Bitwise Exclusive OR
3883 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3884 v2i32, v2i32, xor, 1>;
3885 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3886 v4i32, v4i32, xor, 1>;
3888 // VORR : Vector Bitwise OR
3889 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3890 v2i32, v2i32, or, 1>;
3891 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3892 v4i32, v4i32, or, 1>;
3894 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3895 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3897 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3899 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3900 let Inst{9} = SIMM{9};
3903 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3904 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3906 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3908 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3909 let Inst{10-9} = SIMM{10-9};
3912 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3913 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3915 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3917 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3918 let Inst{9} = SIMM{9};
3921 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3922 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3924 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3926 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3927 let Inst{10-9} = SIMM{10-9};
3931 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3932 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3933 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3934 "vbic", "$Vd, $Vn, $Vm", "",
3935 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3936 (vnotd DPR:$Vm))))]>;
3937 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3938 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3939 "vbic", "$Vd, $Vn, $Vm", "",
3940 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3941 (vnotq QPR:$Vm))))]>;
3943 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3944 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3946 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3948 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3949 let Inst{9} = SIMM{9};
3952 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3953 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3955 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3957 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3958 let Inst{10-9} = SIMM{10-9};
3961 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3962 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3964 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3966 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3967 let Inst{9} = SIMM{9};
3970 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3971 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3973 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3975 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3976 let Inst{10-9} = SIMM{10-9};
3979 // VORN : Vector Bitwise OR NOT
3980 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3981 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3982 "vorn", "$Vd, $Vn, $Vm", "",
3983 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3984 (vnotd DPR:$Vm))))]>;
3985 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3986 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3987 "vorn", "$Vd, $Vn, $Vm", "",
3988 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3989 (vnotq QPR:$Vm))))]>;
3991 // VMVN : Vector Bitwise NOT (Immediate)
3993 let isReMaterializable = 1 in {
3995 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3996 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3997 "vmvn", "i16", "$Vd, $SIMM", "",
3998 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3999 let Inst{9} = SIMM{9};
4002 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4003 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4004 "vmvn", "i16", "$Vd, $SIMM", "",
4005 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4006 let Inst{9} = SIMM{9};
4009 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4010 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4011 "vmvn", "i32", "$Vd, $SIMM", "",
4012 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4013 let Inst{11-8} = SIMM{11-8};
4016 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4017 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4018 "vmvn", "i32", "$Vd, $SIMM", "",
4019 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4020 let Inst{11-8} = SIMM{11-8};
4024 // VMVN : Vector Bitwise NOT
4025 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4026 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4027 "vmvn", "$Vd, $Vm", "",
4028 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4029 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4030 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4031 "vmvn", "$Vd, $Vm", "",
4032 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4033 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4034 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4036 // VBSL : Vector Bitwise Select
4037 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4038 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4039 N3RegFrm, IIC_VCNTiD,
4040 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4042 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4044 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4045 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4046 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4048 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4049 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4050 N3RegFrm, IIC_VCNTiQ,
4051 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4053 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4055 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4056 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4057 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4059 // VBIF : Vector Bitwise Insert if False
4060 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4061 // FIXME: This instruction's encoding MAY NOT BE correct.
4062 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4063 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4064 N3RegFrm, IIC_VBINiD,
4065 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4067 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4068 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4069 N3RegFrm, IIC_VBINiQ,
4070 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4073 // VBIT : Vector Bitwise Insert if True
4074 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4075 // FIXME: This instruction's encoding MAY NOT BE correct.
4076 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4077 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4078 N3RegFrm, IIC_VBINiD,
4079 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4081 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4082 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4083 N3RegFrm, IIC_VBINiQ,
4084 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4087 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4088 // for equivalent operations with different register constraints; it just
4091 // Vector Absolute Differences.
4093 // VABD : Vector Absolute Difference
4094 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4095 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4096 "vabd", "s", int_arm_neon_vabds, 1>;
4097 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4098 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4099 "vabd", "u", int_arm_neon_vabdu, 1>;
4100 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4101 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4102 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4103 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4105 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4106 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4107 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4108 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4109 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4111 // VABA : Vector Absolute Difference and Accumulate
4112 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4113 "vaba", "s", int_arm_neon_vabds, add>;
4114 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4115 "vaba", "u", int_arm_neon_vabdu, add>;
4117 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4118 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4119 "vabal", "s", int_arm_neon_vabds, zext, add>;
4120 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4121 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4123 // Vector Maximum and Minimum.
4125 // VMAX : Vector Maximum
4126 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4127 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4128 "vmax", "s", int_arm_neon_vmaxs, 1>;
4129 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4130 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4131 "vmax", "u", int_arm_neon_vmaxu, 1>;
4132 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4134 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4135 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4137 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4139 // VMIN : Vector Minimum
4140 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4141 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4142 "vmin", "s", int_arm_neon_vmins, 1>;
4143 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4144 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4145 "vmin", "u", int_arm_neon_vminu, 1>;
4146 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4148 v2f32, v2f32, int_arm_neon_vmins, 1>;
4149 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4151 v4f32, v4f32, int_arm_neon_vmins, 1>;
4153 // Vector Pairwise Operations.
4155 // VPADD : Vector Pairwise Add
4156 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4158 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4159 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4161 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4162 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4164 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4165 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4166 IIC_VPBIND, "vpadd", "f32",
4167 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4169 // VPADDL : Vector Pairwise Add Long
4170 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4171 int_arm_neon_vpaddls>;
4172 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4173 int_arm_neon_vpaddlu>;
4175 // VPADAL : Vector Pairwise Add and Accumulate Long
4176 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4177 int_arm_neon_vpadals>;
4178 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4179 int_arm_neon_vpadalu>;
4181 // VPMAX : Vector Pairwise Maximum
4182 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4183 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4184 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4185 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4186 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4187 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4188 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4189 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4190 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4191 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4192 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4193 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4194 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4195 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4197 // VPMIN : Vector Pairwise Minimum
4198 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4199 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4200 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4201 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4202 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4203 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4204 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4205 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4206 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4207 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4208 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4209 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4210 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4211 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4213 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4215 // VRECPE : Vector Reciprocal Estimate
4216 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4217 IIC_VUNAD, "vrecpe", "u32",
4218 v2i32, v2i32, int_arm_neon_vrecpe>;
4219 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4220 IIC_VUNAQ, "vrecpe", "u32",
4221 v4i32, v4i32, int_arm_neon_vrecpe>;
4222 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4223 IIC_VUNAD, "vrecpe", "f32",
4224 v2f32, v2f32, int_arm_neon_vrecpe>;
4225 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4226 IIC_VUNAQ, "vrecpe", "f32",
4227 v4f32, v4f32, int_arm_neon_vrecpe>;
4229 // VRECPS : Vector Reciprocal Step
4230 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4231 IIC_VRECSD, "vrecps", "f32",
4232 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4233 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4234 IIC_VRECSQ, "vrecps", "f32",
4235 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4237 // VRSQRTE : Vector Reciprocal Square Root Estimate
4238 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4239 IIC_VUNAD, "vrsqrte", "u32",
4240 v2i32, v2i32, int_arm_neon_vrsqrte>;
4241 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4242 IIC_VUNAQ, "vrsqrte", "u32",
4243 v4i32, v4i32, int_arm_neon_vrsqrte>;
4244 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4245 IIC_VUNAD, "vrsqrte", "f32",
4246 v2f32, v2f32, int_arm_neon_vrsqrte>;
4247 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4248 IIC_VUNAQ, "vrsqrte", "f32",
4249 v4f32, v4f32, int_arm_neon_vrsqrte>;
4251 // VRSQRTS : Vector Reciprocal Square Root Step
4252 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4253 IIC_VRECSD, "vrsqrts", "f32",
4254 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4255 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4256 IIC_VRECSQ, "vrsqrts", "f32",
4257 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4261 // VSHL : Vector Shift
4262 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4263 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4264 "vshl", "s", int_arm_neon_vshifts>;
4265 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4266 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4267 "vshl", "u", int_arm_neon_vshiftu>;
4269 // VSHL : Vector Shift Left (Immediate)
4270 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4272 // VSHR : Vector Shift Right (Immediate)
4273 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4274 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4276 // VSHLL : Vector Shift Left Long
4277 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4278 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4280 // VSHLL : Vector Shift Left Long (with maximum shift count)
4281 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4282 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4283 ValueType OpTy, SDNode OpNode>
4284 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4285 ResTy, OpTy, OpNode> {
4286 let Inst{21-16} = op21_16;
4287 let DecoderMethod = "DecodeVSHLMaxInstruction";
4289 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4290 v8i16, v8i8, NEONvshlli>;
4291 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4292 v4i32, v4i16, NEONvshlli>;
4293 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4294 v2i64, v2i32, NEONvshlli>;
4296 // VSHRN : Vector Shift Right and Narrow
4297 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4300 // VRSHL : Vector Rounding Shift
4301 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4302 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4303 "vrshl", "s", int_arm_neon_vrshifts>;
4304 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4305 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4306 "vrshl", "u", int_arm_neon_vrshiftu>;
4307 // VRSHR : Vector Rounding Shift Right
4308 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4309 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4311 // VRSHRN : Vector Rounding Shift Right and Narrow
4312 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4315 // VQSHL : Vector Saturating Shift
4316 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4317 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4318 "vqshl", "s", int_arm_neon_vqshifts>;
4319 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4320 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4321 "vqshl", "u", int_arm_neon_vqshiftu>;
4322 // VQSHL : Vector Saturating Shift Left (Immediate)
4323 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4324 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4326 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4327 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4329 // VQSHRN : Vector Saturating Shift Right and Narrow
4330 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4332 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4335 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4336 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4339 // VQRSHL : Vector Saturating Rounding Shift
4340 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4341 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4342 "vqrshl", "s", int_arm_neon_vqrshifts>;
4343 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4344 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4345 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4347 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4348 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4350 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4353 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4354 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4357 // VSRA : Vector Shift Right and Accumulate
4358 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4359 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4360 // VRSRA : Vector Rounding Shift Right and Accumulate
4361 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4362 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4364 // VSLI : Vector Shift Left and Insert
4365 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4367 // VSRI : Vector Shift Right and Insert
4368 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4370 // Vector Absolute and Saturating Absolute.
4372 // VABS : Vector Absolute Value
4373 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4374 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4376 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4377 IIC_VUNAD, "vabs", "f32",
4378 v2f32, v2f32, int_arm_neon_vabs>;
4379 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4380 IIC_VUNAQ, "vabs", "f32",
4381 v4f32, v4f32, int_arm_neon_vabs>;
4383 // VQABS : Vector Saturating Absolute Value
4384 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4385 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4386 int_arm_neon_vqabs>;
4390 def vnegd : PatFrag<(ops node:$in),
4391 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4392 def vnegq : PatFrag<(ops node:$in),
4393 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4395 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4396 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4397 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4398 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4399 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4400 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4401 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4402 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4404 // VNEG : Vector Negate (integer)
4405 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4406 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4407 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4408 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4409 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4410 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4412 // VNEG : Vector Negate (floating-point)
4413 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4414 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4415 "vneg", "f32", "$Vd, $Vm", "",
4416 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4417 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4418 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4419 "vneg", "f32", "$Vd, $Vm", "",
4420 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4422 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4423 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4424 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4425 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4426 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4427 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4429 // VQNEG : Vector Saturating Negate
4430 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4431 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4432 int_arm_neon_vqneg>;
4434 // Vector Bit Counting Operations.
4436 // VCLS : Vector Count Leading Sign Bits
4437 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4438 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4440 // VCLZ : Vector Count Leading Zeros
4441 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4442 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4444 // VCNT : Vector Count One Bits
4445 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4446 IIC_VCNTiD, "vcnt", "8",
4447 v8i8, v8i8, int_arm_neon_vcnt>;
4448 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4449 IIC_VCNTiQ, "vcnt", "8",
4450 v16i8, v16i8, int_arm_neon_vcnt>;
4453 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4454 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4455 "vswp", "$Vd, $Vm", "", []>;
4456 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4457 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4458 "vswp", "$Vd, $Vm", "", []>;
4460 // Vector Move Operations.
4462 // VMOV : Vector Move (Register)
4463 def : InstAlias<"vmov${p} $Vd, $Vm",
4464 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4465 def : InstAlias<"vmov${p} $Vd, $Vm",
4466 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4468 // VMOV : Vector Move (Immediate)
4470 let isReMaterializable = 1 in {
4471 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4472 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4473 "vmov", "i8", "$Vd, $SIMM", "",
4474 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4475 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4476 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4477 "vmov", "i8", "$Vd, $SIMM", "",
4478 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4480 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4481 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4482 "vmov", "i16", "$Vd, $SIMM", "",
4483 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4484 let Inst{9} = SIMM{9};
4487 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4488 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4489 "vmov", "i16", "$Vd, $SIMM", "",
4490 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4491 let Inst{9} = SIMM{9};
4494 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4495 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4496 "vmov", "i32", "$Vd, $SIMM", "",
4497 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4498 let Inst{11-8} = SIMM{11-8};
4501 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4502 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4503 "vmov", "i32", "$Vd, $SIMM", "",
4504 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4505 let Inst{11-8} = SIMM{11-8};
4508 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4509 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4510 "vmov", "i64", "$Vd, $SIMM", "",
4511 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4512 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4513 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4514 "vmov", "i64", "$Vd, $SIMM", "",
4515 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4516 } // isReMaterializable
4518 // VMOV : Vector Get Lane (move scalar to ARM core register)
4520 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4521 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4522 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4523 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4525 let Inst{21} = lane{2};
4526 let Inst{6-5} = lane{1-0};
4528 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4529 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4530 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4531 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4533 let Inst{21} = lane{1};
4534 let Inst{6} = lane{0};
4536 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4537 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4538 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4539 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4541 let Inst{21} = lane{2};
4542 let Inst{6-5} = lane{1-0};
4544 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4545 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4546 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4547 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4549 let Inst{21} = lane{1};
4550 let Inst{6} = lane{0};
4552 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4553 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4554 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4555 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4557 let Inst{21} = lane{0};
4559 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4560 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4561 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4562 (DSubReg_i8_reg imm:$lane))),
4563 (SubReg_i8_lane imm:$lane))>;
4564 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4565 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4566 (DSubReg_i16_reg imm:$lane))),
4567 (SubReg_i16_lane imm:$lane))>;
4568 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4569 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4570 (DSubReg_i8_reg imm:$lane))),
4571 (SubReg_i8_lane imm:$lane))>;
4572 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4573 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4574 (DSubReg_i16_reg imm:$lane))),
4575 (SubReg_i16_lane imm:$lane))>;
4576 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4577 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4578 (DSubReg_i32_reg imm:$lane))),
4579 (SubReg_i32_lane imm:$lane))>;
4580 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4581 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4582 (SSubReg_f32_reg imm:$src2))>;
4583 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4584 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4585 (SSubReg_f32_reg imm:$src2))>;
4586 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4587 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4588 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4589 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4592 // VMOV : Vector Set Lane (move ARM core register to scalar)
4594 let Constraints = "$src1 = $V" in {
4595 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4596 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4597 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4598 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4599 GPR:$R, imm:$lane))]> {
4600 let Inst{21} = lane{2};
4601 let Inst{6-5} = lane{1-0};
4603 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4604 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4605 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4606 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4607 GPR:$R, imm:$lane))]> {
4608 let Inst{21} = lane{1};
4609 let Inst{6} = lane{0};
4611 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4612 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4613 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4614 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4615 GPR:$R, imm:$lane))]> {
4616 let Inst{21} = lane{0};
4619 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4620 (v16i8 (INSERT_SUBREG QPR:$src1,
4621 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4622 (DSubReg_i8_reg imm:$lane))),
4623 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4624 (DSubReg_i8_reg imm:$lane)))>;
4625 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4626 (v8i16 (INSERT_SUBREG QPR:$src1,
4627 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4628 (DSubReg_i16_reg imm:$lane))),
4629 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4630 (DSubReg_i16_reg imm:$lane)))>;
4631 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4632 (v4i32 (INSERT_SUBREG QPR:$src1,
4633 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4634 (DSubReg_i32_reg imm:$lane))),
4635 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4636 (DSubReg_i32_reg imm:$lane)))>;
4638 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4639 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4640 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4641 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4642 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4643 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4645 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4646 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4647 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4648 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4650 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4651 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4652 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4653 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4654 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4655 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4657 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4658 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4659 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4660 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4661 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4662 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4664 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4665 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4666 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4668 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4669 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4670 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4672 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4673 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4674 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4677 // VDUP : Vector Duplicate (from ARM core register to all elements)
4679 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4680 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4681 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4682 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4683 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4684 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4685 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4686 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4688 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4689 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4690 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4691 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4692 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4693 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4695 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4696 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4698 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4700 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4701 ValueType Ty, Operand IdxTy>
4702 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4703 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4704 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4706 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4707 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4708 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4709 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4710 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4711 VectorIndex32:$lane)))]>;
4713 // Inst{19-16} is partially specified depending on the element size.
4715 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4717 let Inst{19-17} = lane{2-0};
4719 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4721 let Inst{19-18} = lane{1-0};
4723 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4725 let Inst{19} = lane{0};
4727 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4729 let Inst{19-17} = lane{2-0};
4731 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4733 let Inst{19-18} = lane{1-0};
4735 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4737 let Inst{19} = lane{0};
4740 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4741 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4743 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4744 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4746 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4747 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4748 (DSubReg_i8_reg imm:$lane))),
4749 (SubReg_i8_lane imm:$lane)))>;
4750 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4751 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4752 (DSubReg_i16_reg imm:$lane))),
4753 (SubReg_i16_lane imm:$lane)))>;
4754 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4755 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4756 (DSubReg_i32_reg imm:$lane))),
4757 (SubReg_i32_lane imm:$lane)))>;
4758 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4759 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4760 (DSubReg_i32_reg imm:$lane))),
4761 (SubReg_i32_lane imm:$lane)))>;
4763 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4764 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4765 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4766 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4768 // VMOVN : Vector Narrowing Move
4769 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4770 "vmovn", "i", trunc>;
4771 // VQMOVN : Vector Saturating Narrowing Move
4772 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4773 "vqmovn", "s", int_arm_neon_vqmovns>;
4774 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4775 "vqmovn", "u", int_arm_neon_vqmovnu>;
4776 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4777 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4778 // VMOVL : Vector Lengthening Move
4779 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4780 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4782 // Vector Conversions.
4784 // VCVT : Vector Convert Between Floating-Point and Integers
4785 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4786 v2i32, v2f32, fp_to_sint>;
4787 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4788 v2i32, v2f32, fp_to_uint>;
4789 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4790 v2f32, v2i32, sint_to_fp>;
4791 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4792 v2f32, v2i32, uint_to_fp>;
4794 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4795 v4i32, v4f32, fp_to_sint>;
4796 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4797 v4i32, v4f32, fp_to_uint>;
4798 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4799 v4f32, v4i32, sint_to_fp>;
4800 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4801 v4f32, v4i32, uint_to_fp>;
4803 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4804 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4805 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4806 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4807 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4808 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4809 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4810 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4811 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4813 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4814 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4815 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4816 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4817 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4818 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4819 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4820 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4822 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4823 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4824 IIC_VUNAQ, "vcvt", "f16.f32",
4825 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4826 Requires<[HasNEON, HasFP16]>;
4827 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4828 IIC_VUNAQ, "vcvt", "f32.f16",
4829 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4830 Requires<[HasNEON, HasFP16]>;
4834 // VREV64 : Vector Reverse elements within 64-bit doublewords
4836 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4837 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4838 (ins DPR:$Vm), IIC_VMOVD,
4839 OpcodeStr, Dt, "$Vd, $Vm", "",
4840 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4841 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4842 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4843 (ins QPR:$Vm), IIC_VMOVQ,
4844 OpcodeStr, Dt, "$Vd, $Vm", "",
4845 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4847 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4848 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4849 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4850 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4852 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4853 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4854 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4855 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4857 // VREV32 : Vector Reverse elements within 32-bit words
4859 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4860 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4861 (ins DPR:$Vm), IIC_VMOVD,
4862 OpcodeStr, Dt, "$Vd, $Vm", "",
4863 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4864 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4865 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4866 (ins QPR:$Vm), IIC_VMOVQ,
4867 OpcodeStr, Dt, "$Vd, $Vm", "",
4868 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4870 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4871 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4873 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4874 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4876 // VREV16 : Vector Reverse elements within 16-bit halfwords
4878 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4879 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4880 (ins DPR:$Vm), IIC_VMOVD,
4881 OpcodeStr, Dt, "$Vd, $Vm", "",
4882 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4883 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4884 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4885 (ins QPR:$Vm), IIC_VMOVQ,
4886 OpcodeStr, Dt, "$Vd, $Vm", "",
4887 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4889 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4890 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4892 // Other Vector Shuffles.
4894 // Aligned extractions: really just dropping registers
4896 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4897 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4898 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4900 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4902 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4904 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4906 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4908 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4911 // VEXT : Vector Extract
4913 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4914 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4915 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4916 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4917 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4918 (Ty DPR:$Vm), imm:$index)))]> {
4920 let Inst{11-8} = index{3-0};
4923 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4924 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4925 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4926 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4927 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4928 (Ty QPR:$Vm), imm:$index)))]> {
4930 let Inst{11-8} = index{3-0};
4933 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4934 let Inst{11-8} = index{3-0};
4936 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4937 let Inst{11-9} = index{2-0};
4940 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4941 let Inst{11-10} = index{1-0};
4942 let Inst{9-8} = 0b00;
4944 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4947 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4949 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4950 let Inst{11-8} = index{3-0};
4952 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4953 let Inst{11-9} = index{2-0};
4956 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4957 let Inst{11-10} = index{1-0};
4958 let Inst{9-8} = 0b00;
4960 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4963 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4965 // VTRN : Vector Transpose
4967 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4968 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4969 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4971 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4972 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4973 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4975 // VUZP : Vector Unzip (Deinterleave)
4977 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4978 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4979 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4981 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4982 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4983 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4985 // VZIP : Vector Zip (Interleave)
4987 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4988 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4989 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4991 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4992 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4993 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4995 // Vector Table Lookup and Table Extension.
4997 // VTBL : Vector Table Lookup
4998 let DecoderMethod = "DecodeTBLInstruction" in {
5000 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5001 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5002 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5003 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5004 let hasExtraSrcRegAllocReq = 1 in {
5006 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5007 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5008 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
5010 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5011 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5012 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
5014 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5015 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
5017 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
5018 } // hasExtraSrcRegAllocReq = 1
5021 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5023 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5025 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5027 // VTBX : Vector Table Extension
5029 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5030 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5031 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5032 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5033 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5034 let hasExtraSrcRegAllocReq = 1 in {
5036 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5037 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5038 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
5040 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5041 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
5042 NVTBLFrm, IIC_VTBX3,
5043 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
5046 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
5047 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5048 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
5050 } // hasExtraSrcRegAllocReq = 1
5053 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5054 IIC_VTBX2, "$orig = $dst", []>;
5056 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5057 IIC_VTBX3, "$orig = $dst", []>;
5059 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5060 IIC_VTBX4, "$orig = $dst", []>;
5061 } // DecoderMethod = "DecodeTBLInstruction"
5063 //===----------------------------------------------------------------------===//
5064 // NEON instructions for single-precision FP math
5065 //===----------------------------------------------------------------------===//
5067 class N2VSPat<SDNode OpNode, NeonI Inst>
5068 : NEONFPPat<(f32 (OpNode SPR:$a)),
5070 (v2f32 (COPY_TO_REGCLASS (Inst
5072 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5073 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5075 class N3VSPat<SDNode OpNode, NeonI Inst>
5076 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5078 (v2f32 (COPY_TO_REGCLASS (Inst
5080 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5083 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5084 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5086 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5087 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5089 (v2f32 (COPY_TO_REGCLASS (Inst
5091 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5094 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5097 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5098 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5100 def : N3VSPat<fadd, VADDfd>;
5101 def : N3VSPat<fsub, VSUBfd>;
5102 def : N3VSPat<fmul, VMULfd>;
5103 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5104 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5105 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5106 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5107 def : N2VSPat<fabs, VABSfd>;
5108 def : N2VSPat<fneg, VNEGfd>;
5109 def : N3VSPat<NEONfmax, VMAXfd>;
5110 def : N3VSPat<NEONfmin, VMINfd>;
5111 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5112 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5113 def : N2VSPat<arm_sitof, VCVTs2fd>;
5114 def : N2VSPat<arm_uitof, VCVTu2fd>;
5116 //===----------------------------------------------------------------------===//
5117 // Non-Instruction Patterns
5118 //===----------------------------------------------------------------------===//
5121 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5122 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5123 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5124 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5125 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5126 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5127 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5128 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5129 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5130 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5131 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5132 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5133 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5134 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5135 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5136 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5137 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5138 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5139 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5140 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5141 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5142 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5143 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5144 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5145 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5146 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5147 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5148 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5149 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5150 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5152 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5153 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5154 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5155 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5156 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5157 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5158 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5159 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5160 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5161 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5162 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5163 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5164 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5165 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5166 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5167 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5168 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5169 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5170 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5171 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5172 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5173 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5174 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5175 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5176 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5177 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5178 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5179 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5180 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5181 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5184 //===----------------------------------------------------------------------===//
5185 // Assembler aliases
5188 // VAND/VEOR/VORR accept but do not require a type suffix.
5189 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5190 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5191 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5192 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5193 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5194 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5195 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5196 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5197 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5198 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5199 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5200 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5202 // VLD1 requires a size suffix, but also accepts type specific variants.
5203 // Load one D register.
5204 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5205 (VLD1d8 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
5206 defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5207 (VLD1d16 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
5208 defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5209 (VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
5210 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5211 (VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
5213 // Load two D registers.
5214 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5215 (VLD1q8 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
5216 defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5217 (VLD1q16 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
5218 defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5219 (VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
5220 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5221 (VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
5223 // Load three D registers.
5224 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5225 (VLD1d8T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
5226 defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5227 (VLD1d16T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
5228 defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5229 (VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
5230 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5231 (VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
5233 // Load four D registers.
5234 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5235 (VLD1d8Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
5236 defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5237 (VLD1d16Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
5238 defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5239 (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
5240 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
5241 (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
5243 // VST1 requires a size suffix, but also accepts type specific variants.
5244 // Load one D register.
5245 defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5246 (VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
5247 defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5248 (VST1d16 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
5249 defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5250 (VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
5251 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5252 (VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
5254 // Load two D registers.
5255 defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5256 (VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
5257 defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5258 (VST1q16 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
5259 defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5260 (VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
5261 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5262 (VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
5264 // FIXME: The three and four register VST1 instructions haven't been moved
5265 // to the VecList* encoding yet, so we can't do assembly parsing support
5266 // for them. Uncomment these when that happens.
5267 // Load three D registers.
5268 //defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5269 // (VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
5270 //defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5271 // (VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
5272 //defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5273 // (VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
5274 //defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5275 // (VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
5277 // Load four D registers.
5278 //defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5279 // (VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
5280 //defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5281 // (VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
5282 //defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5283 // (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
5284 //defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
5285 // (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;