1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
98 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
99 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
101 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
102 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
103 unsigned EltBits = 0;
104 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
105 return (EltBits == 32 && EltVal == 0);
108 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
109 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
110 unsigned EltBits = 0;
111 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
112 return (EltBits == 8 && EltVal == 0xff);
115 //===----------------------------------------------------------------------===//
116 // NEON operand definitions
117 //===----------------------------------------------------------------------===//
119 def nModImm : Operand<i32> {
120 let PrintMethod = "printNEONModImmOperand";
123 //===----------------------------------------------------------------------===//
124 // NEON load / store instructions
125 //===----------------------------------------------------------------------===//
127 // Use vldmia to load a Q register as a D register pair.
128 // This is equivalent to VLDMD except that it has a Q register operand
129 // instead of a pair of D registers.
131 : AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
132 IndexModeNone, IIC_fpLoadm,
133 "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
134 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
136 let mayLoad = 1, neverHasSideEffects = 1 in {
137 // Use vld1 to load a Q register as a D register pair.
138 // This alternative to VLDMQ allows an alignment to be specified.
139 // This is equivalent to VLD1q64 except that it has a Q register operand.
141 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
142 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
143 } // mayLoad = 1, neverHasSideEffects = 1
145 // Use vstmia to store a Q register as a D register pair.
146 // This is equivalent to VSTMD except that it has a Q register operand
147 // instead of a pair of D registers.
149 : AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
150 IndexModeNone, IIC_fpStorem,
151 "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
152 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
154 let mayStore = 1, neverHasSideEffects = 1 in {
155 // Use vst1 to store a Q register as a D register pair.
156 // This alternative to VSTMQ allows an alignment to be specified.
157 // This is equivalent to VST1q64 except that it has a Q register operand.
159 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
160 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
161 } // mayStore = 1, neverHasSideEffects = 1
163 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
165 // VLD1 : Vector Load (multiple single elements)
166 class VLD1D<bits<4> op7_4, string Dt>
167 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
168 (ins addrmode6:$addr), IIC_VLD1,
169 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
170 class VLD1Q<bits<4> op7_4, string Dt>
171 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
172 (ins addrmode6:$addr), IIC_VLD1,
173 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
175 def VLD1d8 : VLD1D<0b0000, "8">;
176 def VLD1d16 : VLD1D<0b0100, "16">;
177 def VLD1d32 : VLD1D<0b1000, "32">;
178 def VLD1d64 : VLD1D<0b1100, "64">;
180 def VLD1q8 : VLD1Q<0b0000, "8">;
181 def VLD1q16 : VLD1Q<0b0100, "16">;
182 def VLD1q32 : VLD1Q<0b1000, "32">;
183 def VLD1q64 : VLD1Q<0b1100, "64">;
185 // ...with address register writeback:
186 class VLD1DWB<bits<4> op7_4, string Dt>
187 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
188 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
189 "vld1", Dt, "\\{$dst\\}, $addr$offset",
190 "$addr.addr = $wb", []>;
191 class VLD1QWB<bits<4> op7_4, string Dt>
192 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
193 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
194 "vld1", Dt, "${dst:dregpair}, $addr$offset",
195 "$addr.addr = $wb", []>;
197 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
198 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
199 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
200 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
202 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
203 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
204 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
205 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
207 // ...with 3 registers (some of these are only for the disassembler):
208 class VLD1D3<bits<4> op7_4, string Dt>
209 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
210 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
211 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
212 class VLD1D3WB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
214 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
215 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
217 def VLD1d8T : VLD1D3<0b0000, "8">;
218 def VLD1d16T : VLD1D3<0b0100, "16">;
219 def VLD1d32T : VLD1D3<0b1000, "32">;
220 def VLD1d64T : VLD1D3<0b1100, "64">;
222 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
223 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
224 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
225 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
227 // ...with 4 registers (some of these are only for the disassembler):
228 class VLD1D4<bits<4> op7_4, string Dt>
229 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
230 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
231 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
232 class VLD1D4WB<bits<4> op7_4, string Dt>
233 : NLdSt<0,0b10,0b0010,op7_4,
234 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
235 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
236 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
239 def VLD1d8Q : VLD1D4<0b0000, "8">;
240 def VLD1d16Q : VLD1D4<0b0100, "16">;
241 def VLD1d32Q : VLD1D4<0b1000, "32">;
242 def VLD1d64Q : VLD1D4<0b1100, "64">;
244 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
245 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
246 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
247 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
249 // VLD2 : Vector Load (multiple 2-element structures)
250 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
251 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
252 (ins addrmode6:$addr), IIC_VLD2,
253 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
254 class VLD2Q<bits<4> op7_4, string Dt>
255 : NLdSt<0, 0b10, 0b0011, op7_4,
256 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
257 (ins addrmode6:$addr), IIC_VLD2,
258 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
260 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
261 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
262 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
264 def VLD2q8 : VLD2Q<0b0000, "8">;
265 def VLD2q16 : VLD2Q<0b0100, "16">;
266 def VLD2q32 : VLD2Q<0b1000, "32">;
268 // ...with address register writeback:
269 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
270 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
271 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
272 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
273 "$addr.addr = $wb", []>;
274 class VLD2QWB<bits<4> op7_4, string Dt>
275 : NLdSt<0, 0b10, 0b0011, op7_4,
276 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
277 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
278 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
279 "$addr.addr = $wb", []>;
281 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
282 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
283 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
285 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
286 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
287 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
289 // ...with double-spaced registers (for disassembly only):
290 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
291 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
292 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
293 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
294 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
295 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
297 // VLD3 : Vector Load (multiple 3-element structures)
298 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
299 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
300 (ins addrmode6:$addr), IIC_VLD3,
301 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
303 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
304 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
305 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
307 // ...with address register writeback:
308 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
309 : NLdSt<0, 0b10, op11_8, op7_4,
310 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
311 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
312 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
313 "$addr.addr = $wb", []>;
315 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
316 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
317 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
319 // ...with double-spaced registers (non-updating versions for disassembly only):
320 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
321 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
322 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
323 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
324 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
325 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
327 // ...alternate versions to be allocated odd register numbers:
328 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
329 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
330 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
332 // VLD4 : Vector Load (multiple 4-element structures)
333 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
334 : NLdSt<0, 0b10, op11_8, op7_4,
335 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
336 (ins addrmode6:$addr), IIC_VLD4,
337 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
339 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
340 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
341 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
343 // ...with address register writeback:
344 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
345 : NLdSt<0, 0b10, op11_8, op7_4,
346 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
347 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
348 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
349 "$addr.addr = $wb", []>;
351 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
352 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
353 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
355 // ...with double-spaced registers (non-updating versions for disassembly only):
356 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
357 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
358 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
359 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
360 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
361 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
363 // ...alternate versions to be allocated odd register numbers:
364 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
365 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
366 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
368 // VLD1LN : Vector Load (single element to one lane)
369 // FIXME: Not yet implemented.
371 // VLD2LN : Vector Load (single 2-element structure to one lane)
372 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
373 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
374 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
375 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
376 "$src1 = $dst1, $src2 = $dst2", []>;
378 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
379 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
380 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
382 // ...with double-spaced registers:
383 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
384 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
386 // ...alternate versions to be allocated odd register numbers:
387 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
388 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
390 // ...with address register writeback:
391 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
392 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
393 (ins addrmode6:$addr, am6offset:$offset,
394 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
395 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
396 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
398 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
399 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
400 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
402 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
403 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
405 // VLD3LN : Vector Load (single 3-element structure to one lane)
406 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
407 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
408 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
409 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
410 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
411 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
413 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
414 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
415 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
417 // ...with double-spaced registers:
418 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
419 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
421 // ...alternate versions to be allocated odd register numbers:
422 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
423 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
425 // ...with address register writeback:
426 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
427 : NLdSt<1, 0b10, op11_8, op7_4,
428 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
429 (ins addrmode6:$addr, am6offset:$offset,
430 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
431 IIC_VLD3, "vld3", Dt,
432 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
433 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
436 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
437 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
438 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
440 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
441 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
443 // VLD4LN : Vector Load (single 4-element structure to one lane)
444 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
445 : NLdSt<1, 0b10, op11_8, op7_4,
446 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
447 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
448 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
449 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
450 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
452 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
453 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
454 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
456 // ...with double-spaced registers:
457 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
458 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
460 // ...alternate versions to be allocated odd register numbers:
461 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
462 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
464 // ...with address register writeback:
465 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
466 : NLdSt<1, 0b10, op11_8, op7_4,
467 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
468 (ins addrmode6:$addr, am6offset:$offset,
469 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
470 IIC_VLD4, "vld4", Dt,
471 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
472 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
475 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
476 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
477 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
479 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
480 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
482 // VLD1DUP : Vector Load (single element to all lanes)
483 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
484 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
485 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
486 // FIXME: Not yet implemented.
487 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
489 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
491 // Classes for VST* pseudo-instructions with multi-register operands.
492 // These are expanded to real instructions after register allocation.
494 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, "">;
496 : PseudoNLdSt<(outs GPR:$wb),
497 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
500 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
502 : PseudoNLdSt<(outs GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST,
505 class VSTQQQQWBPseudo
506 : PseudoNLdSt<(outs GPR:$wb),
507 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
510 // VST1 : Vector Store (multiple single elements)
511 class VST1D<bits<4> op7_4, string Dt>
512 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
513 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
514 class VST1Q<bits<4> op7_4, string Dt>
515 : NLdSt<0,0b00,0b1010,op7_4, (outs),
516 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
517 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
519 def VST1d8 : VST1D<0b0000, "8">;
520 def VST1d16 : VST1D<0b0100, "16">;
521 def VST1d32 : VST1D<0b1000, "32">;
522 def VST1d64 : VST1D<0b1100, "64">;
524 def VST1q8 : VST1Q<0b0000, "8">;
525 def VST1q16 : VST1Q<0b0100, "16">;
526 def VST1q32 : VST1Q<0b1000, "32">;
527 def VST1q64 : VST1Q<0b1100, "64">;
529 def VST1q8Pseudo : VSTQPseudo;
530 def VST1q16Pseudo : VSTQPseudo;
531 def VST1q32Pseudo : VSTQPseudo;
532 def VST1q64Pseudo : VSTQPseudo;
534 // ...with address register writeback:
535 class VST1DWB<bits<4> op7_4, string Dt>
536 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
537 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
538 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
539 class VST1QWB<bits<4> op7_4, string Dt>
540 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
541 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
542 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
544 def VST1d8_UPD : VST1DWB<0b0000, "8">;
545 def VST1d16_UPD : VST1DWB<0b0100, "16">;
546 def VST1d32_UPD : VST1DWB<0b1000, "32">;
547 def VST1d64_UPD : VST1DWB<0b1100, "64">;
549 def VST1q8_UPD : VST1QWB<0b0000, "8">;
550 def VST1q16_UPD : VST1QWB<0b0100, "16">;
551 def VST1q32_UPD : VST1QWB<0b1000, "32">;
552 def VST1q64_UPD : VST1QWB<0b1100, "64">;
554 def VST1q8Pseudo_UPD : VSTQWBPseudo;
555 def VST1q16Pseudo_UPD : VSTQWBPseudo;
556 def VST1q32Pseudo_UPD : VSTQWBPseudo;
557 def VST1q64Pseudo_UPD : VSTQWBPseudo;
559 // ...with 3 registers (some of these are only for the disassembler):
560 class VST1D3<bits<4> op7_4, string Dt>
561 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
562 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
563 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
564 class VST1D3WB<bits<4> op7_4, string Dt>
565 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
566 (ins addrmode6:$addr, am6offset:$offset,
567 DPR:$src1, DPR:$src2, DPR:$src3),
568 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
569 "$addr.addr = $wb", []>;
571 def VST1d8T : VST1D3<0b0000, "8">;
572 def VST1d16T : VST1D3<0b0100, "16">;
573 def VST1d32T : VST1D3<0b1000, "32">;
574 def VST1d64T : VST1D3<0b1100, "64">;
576 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
577 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
578 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
579 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
581 def VST1d64TPseudo : VSTQQPseudo;
582 def VST1d64TPseudo_UPD : VSTQQWBPseudo;
584 // ...with 4 registers (some of these are only for the disassembler):
585 class VST1D4<bits<4> op7_4, string Dt>
586 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
587 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
588 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
590 class VST1D4WB<bits<4> op7_4, string Dt>
591 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
592 (ins addrmode6:$addr, am6offset:$offset,
593 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
594 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
595 "$addr.addr = $wb", []>;
597 def VST1d8Q : VST1D4<0b0000, "8">;
598 def VST1d16Q : VST1D4<0b0100, "16">;
599 def VST1d32Q : VST1D4<0b1000, "32">;
600 def VST1d64Q : VST1D4<0b1100, "64">;
602 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
603 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
604 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
605 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
607 def VST1d64QPseudo : VSTQQPseudo;
608 def VST1d64QPseudo_UPD : VSTQQWBPseudo;
610 // VST2 : Vector Store (multiple 2-element structures)
611 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
612 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
613 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
614 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
615 class VST2Q<bits<4> op7_4, string Dt>
616 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
617 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
618 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
621 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
622 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
623 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
625 def VST2q8 : VST2Q<0b0000, "8">;
626 def VST2q16 : VST2Q<0b0100, "16">;
627 def VST2q32 : VST2Q<0b1000, "32">;
629 def VST2d8Pseudo : VSTQPseudo;
630 def VST2d16Pseudo : VSTQPseudo;
631 def VST2d32Pseudo : VSTQPseudo;
633 def VST2q8Pseudo : VSTQQPseudo;
634 def VST2q16Pseudo : VSTQQPseudo;
635 def VST2q32Pseudo : VSTQQPseudo;
637 // ...with address register writeback:
638 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
639 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
640 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
641 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
642 "$addr.addr = $wb", []>;
643 class VST2QWB<bits<4> op7_4, string Dt>
644 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
645 (ins addrmode6:$addr, am6offset:$offset,
646 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
647 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
648 "$addr.addr = $wb", []>;
650 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
651 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
652 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
654 def VST2q8_UPD : VST2QWB<0b0000, "8">;
655 def VST2q16_UPD : VST2QWB<0b0100, "16">;
656 def VST2q32_UPD : VST2QWB<0b1000, "32">;
658 def VST2d8Pseudo_UPD : VSTQWBPseudo;
659 def VST2d16Pseudo_UPD : VSTQWBPseudo;
660 def VST2d32Pseudo_UPD : VSTQWBPseudo;
662 def VST2q8Pseudo_UPD : VSTQQWBPseudo;
663 def VST2q16Pseudo_UPD : VSTQQWBPseudo;
664 def VST2q32Pseudo_UPD : VSTQQWBPseudo;
666 // ...with double-spaced registers (for disassembly only):
667 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
668 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
669 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
670 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
671 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
672 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
674 // VST3 : Vector Store (multiple 3-element structures)
675 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
676 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
677 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
678 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
680 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
681 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
682 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
684 def VST3d8Pseudo : VSTQQPseudo;
685 def VST3d16Pseudo : VSTQQPseudo;
686 def VST3d32Pseudo : VSTQQPseudo;
688 // ...with address register writeback:
689 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
690 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
691 (ins addrmode6:$addr, am6offset:$offset,
692 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
693 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
694 "$addr.addr = $wb", []>;
696 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
697 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
698 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
700 def VST3d8Pseudo_UPD : VSTQQWBPseudo;
701 def VST3d16Pseudo_UPD : VSTQQWBPseudo;
702 def VST3d32Pseudo_UPD : VSTQQWBPseudo;
704 // ...with double-spaced registers (non-updating versions for disassembly only):
705 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
706 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
707 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
708 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
709 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
710 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
712 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo;
713 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo;
714 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo;
716 // ...alternate versions to be allocated odd register numbers:
717 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo;
718 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo;
719 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo;
721 // VST4 : Vector Store (multiple 4-element structures)
722 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
723 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
724 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
725 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
728 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
729 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
730 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
732 def VST4d8Pseudo : VSTQQPseudo;
733 def VST4d16Pseudo : VSTQQPseudo;
734 def VST4d32Pseudo : VSTQQPseudo;
736 // ...with address register writeback:
737 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
738 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
739 (ins addrmode6:$addr, am6offset:$offset,
740 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
741 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
742 "$addr.addr = $wb", []>;
744 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
745 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
746 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
748 def VST4d8Pseudo_UPD : VSTQQWBPseudo;
749 def VST4d16Pseudo_UPD : VSTQQWBPseudo;
750 def VST4d32Pseudo_UPD : VSTQQWBPseudo;
752 // ...with double-spaced registers (non-updating versions for disassembly only):
753 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
754 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
755 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
756 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
757 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
758 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
760 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo;
761 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo;
762 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo;
764 // ...alternate versions to be allocated odd register numbers:
765 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo;
766 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo;
767 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo;
769 // VST1LN : Vector Store (single element from one lane)
770 // FIXME: Not yet implemented.
772 // VST2LN : Vector Store (single 2-element structure from one lane)
773 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
774 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
775 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
776 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
779 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
780 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
781 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
783 // ...with double-spaced registers:
784 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
785 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
787 // ...alternate versions to be allocated odd register numbers:
788 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
789 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
791 // ...with address register writeback:
792 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
793 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
794 (ins addrmode6:$addr, am6offset:$offset,
795 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
796 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
797 "$addr.addr = $wb", []>;
799 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
800 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
801 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
803 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
804 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
806 // VST3LN : Vector Store (single 3-element structure from one lane)
807 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
808 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
809 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
810 nohash_imm:$lane), IIC_VST, "vst3", Dt,
811 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
813 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
814 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
815 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
817 // ...with double-spaced registers:
818 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
819 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
821 // ...alternate versions to be allocated odd register numbers:
822 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
823 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
825 // ...with address register writeback:
826 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
827 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
828 (ins addrmode6:$addr, am6offset:$offset,
829 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
831 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
832 "$addr.addr = $wb", []>;
834 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
835 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
836 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
838 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
839 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
841 // VST4LN : Vector Store (single 4-element structure from one lane)
842 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
843 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
844 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
845 nohash_imm:$lane), IIC_VST, "vst4", Dt,
846 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
849 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
850 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
851 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
853 // ...with double-spaced registers:
854 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
855 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
857 // ...alternate versions to be allocated odd register numbers:
858 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
859 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
861 // ...with address register writeback:
862 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
863 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
864 (ins addrmode6:$addr, am6offset:$offset,
865 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
867 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
868 "$addr.addr = $wb", []>;
870 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
871 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
872 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
874 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
875 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
877 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
880 //===----------------------------------------------------------------------===//
881 // NEON pattern fragments
882 //===----------------------------------------------------------------------===//
884 // Extract D sub-registers of Q registers.
885 def DSubReg_i8_reg : SDNodeXForm<imm, [{
886 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
887 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
889 def DSubReg_i16_reg : SDNodeXForm<imm, [{
890 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
891 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
893 def DSubReg_i32_reg : SDNodeXForm<imm, [{
894 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
895 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
897 def DSubReg_f64_reg : SDNodeXForm<imm, [{
898 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
899 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
902 // Extract S sub-registers of Q/D registers.
903 def SSubReg_f32_reg : SDNodeXForm<imm, [{
904 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
905 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
908 // Translate lane numbers from Q registers to D subregs.
909 def SubReg_i8_lane : SDNodeXForm<imm, [{
910 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
912 def SubReg_i16_lane : SDNodeXForm<imm, [{
913 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
915 def SubReg_i32_lane : SDNodeXForm<imm, [{
916 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
919 //===----------------------------------------------------------------------===//
920 // Instruction Classes
921 //===----------------------------------------------------------------------===//
923 // Basic 2-register operations: single-, double- and quad-register.
924 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
925 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
926 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
927 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
928 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
929 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
930 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
931 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
932 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
933 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
934 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
935 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
936 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
937 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
938 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
939 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
940 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
941 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
943 // Basic 2-register intrinsics, both double- and quad-register.
944 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
945 bits<2> op17_16, bits<5> op11_7, bit op4,
946 InstrItinClass itin, string OpcodeStr, string Dt,
947 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
948 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
949 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
950 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
951 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
952 bits<2> op17_16, bits<5> op11_7, bit op4,
953 InstrItinClass itin, string OpcodeStr, string Dt,
954 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
955 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
956 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
957 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
959 // Narrow 2-register operations.
960 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
961 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
962 InstrItinClass itin, string OpcodeStr, string Dt,
963 ValueType TyD, ValueType TyQ, SDNode OpNode>
964 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
965 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
966 [(set DPR:$dst, (TyD (OpNode (TyQ QPR:$src))))]>;
968 // Narrow 2-register intrinsics.
969 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
970 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
971 InstrItinClass itin, string OpcodeStr, string Dt,
972 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
973 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
974 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
975 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
977 // Long 2-register operations (currently only used for VMOVL).
978 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
979 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
980 InstrItinClass itin, string OpcodeStr, string Dt,
981 ValueType TyQ, ValueType TyD, SDNode OpNode>
982 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
983 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
984 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
986 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
987 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
988 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
989 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
990 OpcodeStr, Dt, "$dst1, $dst2",
991 "$src1 = $dst1, $src2 = $dst2", []>;
992 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
993 InstrItinClass itin, string OpcodeStr, string Dt>
994 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
995 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
996 "$src1 = $dst1, $src2 = $dst2", []>;
998 // Basic 3-register operations: single-, double- and quad-register.
999 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1000 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1001 SDNode OpNode, bit Commutable>
1002 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1003 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
1004 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
1005 let isCommutable = Commutable;
1008 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1009 InstrItinClass itin, string OpcodeStr, string Dt,
1010 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1011 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1012 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1013 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1014 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1015 let isCommutable = Commutable;
1017 // Same as N3VD but no data type.
1018 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1019 InstrItinClass itin, string OpcodeStr,
1020 ValueType ResTy, ValueType OpTy,
1021 SDNode OpNode, bit Commutable>
1022 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1023 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1024 OpcodeStr, "$dst, $src1, $src2", "",
1025 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
1026 let isCommutable = Commutable;
1029 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1030 InstrItinClass itin, string OpcodeStr, string Dt,
1031 ValueType Ty, SDNode ShOp>
1032 : N3V<0, 1, op21_20, op11_8, 1, 0,
1033 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1034 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1035 [(set (Ty DPR:$dst),
1036 (Ty (ShOp (Ty DPR:$src1),
1037 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
1038 let isCommutable = 0;
1040 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1041 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1042 : N3V<0, 1, op21_20, op11_8, 1, 0,
1043 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1044 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1045 [(set (Ty DPR:$dst),
1046 (Ty (ShOp (Ty DPR:$src1),
1047 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1048 let isCommutable = 0;
1051 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1052 InstrItinClass itin, string OpcodeStr, string Dt,
1053 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1054 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1055 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1056 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1057 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1058 let isCommutable = Commutable;
1060 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1061 InstrItinClass itin, string OpcodeStr,
1062 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1063 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1064 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1065 OpcodeStr, "$dst, $src1, $src2", "",
1066 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1067 let isCommutable = Commutable;
1069 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1070 InstrItinClass itin, string OpcodeStr, string Dt,
1071 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1072 : N3V<1, 1, op21_20, op11_8, 1, 0,
1073 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1074 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1075 [(set (ResTy QPR:$dst),
1076 (ResTy (ShOp (ResTy QPR:$src1),
1077 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1079 let isCommutable = 0;
1081 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1082 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1083 : N3V<1, 1, op21_20, op11_8, 1, 0,
1084 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1085 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1086 [(set (ResTy QPR:$dst),
1087 (ResTy (ShOp (ResTy QPR:$src1),
1088 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1090 let isCommutable = 0;
1093 // Basic 3-register intrinsics, both double- and quad-register.
1094 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1095 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1096 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1097 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1098 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1099 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1100 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1101 let isCommutable = Commutable;
1103 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1104 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1105 : N3V<0, 1, op21_20, op11_8, 1, 0,
1106 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1107 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1108 [(set (Ty DPR:$dst),
1109 (Ty (IntOp (Ty DPR:$src1),
1110 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1112 let isCommutable = 0;
1114 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1115 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1116 : N3V<0, 1, op21_20, op11_8, 1, 0,
1117 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1118 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1119 [(set (Ty DPR:$dst),
1120 (Ty (IntOp (Ty DPR:$src1),
1121 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1122 let isCommutable = 0;
1125 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1126 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1127 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1128 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1129 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1130 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1131 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1132 let isCommutable = Commutable;
1134 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1135 string OpcodeStr, string Dt,
1136 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1137 : N3V<1, 1, op21_20, op11_8, 1, 0,
1138 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1139 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1140 [(set (ResTy QPR:$dst),
1141 (ResTy (IntOp (ResTy QPR:$src1),
1142 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1144 let isCommutable = 0;
1146 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1147 string OpcodeStr, string Dt,
1148 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1149 : N3V<1, 1, op21_20, op11_8, 1, 0,
1150 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1151 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1152 [(set (ResTy QPR:$dst),
1153 (ResTy (IntOp (ResTy QPR:$src1),
1154 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1156 let isCommutable = 0;
1159 // Multiply-Add/Sub operations: single-, double- and quad-register.
1160 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1161 InstrItinClass itin, string OpcodeStr, string Dt,
1162 ValueType Ty, SDNode MulOp, SDNode OpNode>
1163 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1164 (outs DPR_VFP2:$dst),
1165 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1166 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1168 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1169 InstrItinClass itin, string OpcodeStr, string Dt,
1170 ValueType Ty, SDNode MulOp, SDNode OpNode>
1171 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1172 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1173 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1174 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1175 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1176 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1177 string OpcodeStr, string Dt,
1178 ValueType Ty, SDNode MulOp, SDNode ShOp>
1179 : N3V<0, 1, op21_20, op11_8, 1, 0,
1181 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1183 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1184 [(set (Ty DPR:$dst),
1185 (Ty (ShOp (Ty DPR:$src1),
1186 (Ty (MulOp DPR:$src2,
1187 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1189 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1190 string OpcodeStr, string Dt,
1191 ValueType Ty, SDNode MulOp, SDNode ShOp>
1192 : N3V<0, 1, op21_20, op11_8, 1, 0,
1194 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1196 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1197 [(set (Ty DPR:$dst),
1198 (Ty (ShOp (Ty DPR:$src1),
1199 (Ty (MulOp DPR:$src2,
1200 (Ty (NEONvduplane (Ty DPR_8:$src3),
1203 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1204 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1205 SDNode MulOp, SDNode OpNode>
1206 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1207 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1208 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1209 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1210 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1211 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1212 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1213 SDNode MulOp, SDNode ShOp>
1214 : N3V<1, 1, op21_20, op11_8, 1, 0,
1216 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1218 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1219 [(set (ResTy QPR:$dst),
1220 (ResTy (ShOp (ResTy QPR:$src1),
1221 (ResTy (MulOp QPR:$src2,
1222 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1224 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1225 string OpcodeStr, string Dt,
1226 ValueType ResTy, ValueType OpTy,
1227 SDNode MulOp, SDNode ShOp>
1228 : N3V<1, 1, op21_20, op11_8, 1, 0,
1230 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1232 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1233 [(set (ResTy QPR:$dst),
1234 (ResTy (ShOp (ResTy QPR:$src1),
1235 (ResTy (MulOp QPR:$src2,
1236 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1239 // Neon 3-argument intrinsics, both double- and quad-register.
1240 // The destination register is also used as the first source operand register.
1241 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1242 InstrItinClass itin, string OpcodeStr, string Dt,
1243 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1244 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1245 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1246 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1247 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1248 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1249 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1250 InstrItinClass itin, string OpcodeStr, string Dt,
1251 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1252 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1253 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1254 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1255 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1256 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1258 // Neon Long 3-argument intrinsic. The destination register is
1259 // a quad-register and is also used as the first source operand register.
1260 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1261 InstrItinClass itin, string OpcodeStr, string Dt,
1262 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1263 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1264 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1265 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1267 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1268 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1269 string OpcodeStr, string Dt,
1270 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1271 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1273 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1275 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1276 [(set (ResTy QPR:$dst),
1277 (ResTy (IntOp (ResTy QPR:$src1),
1279 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1281 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1282 InstrItinClass itin, string OpcodeStr, string Dt,
1283 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1284 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1286 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1288 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1289 [(set (ResTy QPR:$dst),
1290 (ResTy (IntOp (ResTy QPR:$src1),
1292 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1295 // Narrowing 3-register intrinsics.
1296 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1297 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1298 Intrinsic IntOp, bit Commutable>
1299 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1300 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1301 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1302 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1303 let isCommutable = Commutable;
1306 // Long 3-register operations.
1307 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1308 InstrItinClass itin, string OpcodeStr, string Dt,
1309 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
1311 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1312 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1313 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1314 [(set QPR:$dst, (OpNode (TyQ (ExtOp (TyD DPR:$src1))),
1315 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1316 let isCommutable = Commutable;
1319 // Long 3-register intrinsics.
1320 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1321 InstrItinClass itin, string OpcodeStr, string Dt,
1322 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1323 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1324 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1325 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1326 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1327 let isCommutable = Commutable;
1329 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1330 string OpcodeStr, string Dt,
1331 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1332 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1333 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1334 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1335 [(set (ResTy QPR:$dst),
1336 (ResTy (IntOp (OpTy DPR:$src1),
1337 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1339 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1340 InstrItinClass itin, string OpcodeStr, string Dt,
1341 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1342 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1343 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1344 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1345 [(set (ResTy QPR:$dst),
1346 (ResTy (IntOp (OpTy DPR:$src1),
1347 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1350 // Wide 3-register operations.
1351 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1352 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1353 SDNode OpNode, SDNode ExtOp, bit Commutable>
1354 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1355 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1356 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1357 [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
1358 (TyQ (ExtOp (TyD DPR:$src2)))))]> {
1359 let isCommutable = Commutable;
1362 // Pairwise long 2-register intrinsics, both double- and quad-register.
1363 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1364 bits<2> op17_16, bits<5> op11_7, bit op4,
1365 string OpcodeStr, string Dt,
1366 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1367 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1368 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1369 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1370 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1371 bits<2> op17_16, bits<5> op11_7, bit op4,
1372 string OpcodeStr, string Dt,
1373 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1374 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1375 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1376 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1378 // Pairwise long 2-register accumulate intrinsics,
1379 // both double- and quad-register.
1380 // The destination register is also used as the first source operand register.
1381 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1382 bits<2> op17_16, bits<5> op11_7, bit op4,
1383 string OpcodeStr, string Dt,
1384 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1385 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1386 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1387 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1388 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1389 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1390 bits<2> op17_16, bits<5> op11_7, bit op4,
1391 string OpcodeStr, string Dt,
1392 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1394 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1395 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1396 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1398 // Shift by immediate,
1399 // both double- and quad-register.
1400 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1401 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1402 ValueType Ty, SDNode OpNode>
1403 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1404 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1405 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1406 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1407 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1408 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1409 ValueType Ty, SDNode OpNode>
1410 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1411 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1412 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1413 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1415 // Long shift by immediate.
1416 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1417 string OpcodeStr, string Dt,
1418 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1419 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1420 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1421 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1422 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1423 (i32 imm:$SIMM))))]>;
1425 // Narrow shift by immediate.
1426 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1427 InstrItinClass itin, string OpcodeStr, string Dt,
1428 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1429 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1430 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1431 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1432 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1433 (i32 imm:$SIMM))))]>;
1435 // Shift right by immediate and accumulate,
1436 // both double- and quad-register.
1437 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1438 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1439 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1440 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1441 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1442 [(set DPR:$dst, (Ty (add DPR:$src1,
1443 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1444 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1445 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1446 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1447 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1448 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1449 [(set QPR:$dst, (Ty (add QPR:$src1,
1450 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1452 // Shift by immediate and insert,
1453 // both double- and quad-register.
1454 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1455 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1456 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1457 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1458 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1459 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1460 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1461 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1462 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1463 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1464 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1465 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1467 // Convert, with fractional bits immediate,
1468 // both double- and quad-register.
1469 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1470 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1472 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1473 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1474 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1475 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1476 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1477 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1479 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1480 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1481 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1482 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1484 //===----------------------------------------------------------------------===//
1486 //===----------------------------------------------------------------------===//
1488 // Abbreviations used in multiclass suffixes:
1489 // Q = quarter int (8 bit) elements
1490 // H = half int (16 bit) elements
1491 // S = single int (32 bit) elements
1492 // D = double int (64 bit) elements
1494 // Neon 2-register vector operations -- for disassembly only.
1496 // First with only element sizes of 8, 16 and 32 bits:
1497 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1498 bits<5> op11_7, bit op4, string opc, string Dt,
1500 // 64-bit vector types.
1501 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1502 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1503 opc, !strconcat(Dt, "8"), asm, "", []>;
1504 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1505 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1506 opc, !strconcat(Dt, "16"), asm, "", []>;
1507 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1508 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1509 opc, !strconcat(Dt, "32"), asm, "", []>;
1510 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1511 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1512 opc, "f32", asm, "", []> {
1513 let Inst{10} = 1; // overwrite F = 1
1516 // 128-bit vector types.
1517 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1518 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1519 opc, !strconcat(Dt, "8"), asm, "", []>;
1520 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1521 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1522 opc, !strconcat(Dt, "16"), asm, "", []>;
1523 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1524 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1525 opc, !strconcat(Dt, "32"), asm, "", []>;
1526 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1527 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1528 opc, "f32", asm, "", []> {
1529 let Inst{10} = 1; // overwrite F = 1
1533 // Neon 3-register vector operations.
1535 // First with only element sizes of 8, 16 and 32 bits:
1536 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1537 InstrItinClass itinD16, InstrItinClass itinD32,
1538 InstrItinClass itinQ16, InstrItinClass itinQ32,
1539 string OpcodeStr, string Dt,
1540 SDNode OpNode, bit Commutable = 0> {
1541 // 64-bit vector types.
1542 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1543 OpcodeStr, !strconcat(Dt, "8"),
1544 v8i8, v8i8, OpNode, Commutable>;
1545 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1546 OpcodeStr, !strconcat(Dt, "16"),
1547 v4i16, v4i16, OpNode, Commutable>;
1548 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1549 OpcodeStr, !strconcat(Dt, "32"),
1550 v2i32, v2i32, OpNode, Commutable>;
1552 // 128-bit vector types.
1553 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1554 OpcodeStr, !strconcat(Dt, "8"),
1555 v16i8, v16i8, OpNode, Commutable>;
1556 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1557 OpcodeStr, !strconcat(Dt, "16"),
1558 v8i16, v8i16, OpNode, Commutable>;
1559 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1560 OpcodeStr, !strconcat(Dt, "32"),
1561 v4i32, v4i32, OpNode, Commutable>;
1564 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1565 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1567 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1569 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1570 v8i16, v4i16, ShOp>;
1571 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1572 v4i32, v2i32, ShOp>;
1575 // ....then also with element size 64 bits:
1576 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1577 InstrItinClass itinD, InstrItinClass itinQ,
1578 string OpcodeStr, string Dt,
1579 SDNode OpNode, bit Commutable = 0>
1580 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1581 OpcodeStr, Dt, OpNode, Commutable> {
1582 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1583 OpcodeStr, !strconcat(Dt, "64"),
1584 v1i64, v1i64, OpNode, Commutable>;
1585 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1586 OpcodeStr, !strconcat(Dt, "64"),
1587 v2i64, v2i64, OpNode, Commutable>;
1591 // Neon Narrowing 2-register vector operations,
1592 // source operand element sizes of 16, 32 and 64 bits:
1593 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1594 bits<5> op11_7, bit op6, bit op4,
1595 InstrItinClass itin, string OpcodeStr, string Dt,
1597 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1598 itin, OpcodeStr, !strconcat(Dt, "16"),
1599 v8i8, v8i16, OpNode>;
1600 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1601 itin, OpcodeStr, !strconcat(Dt, "32"),
1602 v4i16, v4i32, OpNode>;
1603 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1604 itin, OpcodeStr, !strconcat(Dt, "64"),
1605 v2i32, v2i64, OpNode>;
1608 // Neon Narrowing 2-register vector intrinsics,
1609 // source operand element sizes of 16, 32 and 64 bits:
1610 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1611 bits<5> op11_7, bit op6, bit op4,
1612 InstrItinClass itin, string OpcodeStr, string Dt,
1614 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1615 itin, OpcodeStr, !strconcat(Dt, "16"),
1616 v8i8, v8i16, IntOp>;
1617 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1618 itin, OpcodeStr, !strconcat(Dt, "32"),
1619 v4i16, v4i32, IntOp>;
1620 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1621 itin, OpcodeStr, !strconcat(Dt, "64"),
1622 v2i32, v2i64, IntOp>;
1626 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1627 // source operand element sizes of 16, 32 and 64 bits:
1628 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1629 string OpcodeStr, string Dt, SDNode OpNode> {
1630 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1631 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
1632 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1633 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1634 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1635 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1639 // Neon 3-register vector intrinsics.
1641 // First with only element sizes of 16 and 32 bits:
1642 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1643 InstrItinClass itinD16, InstrItinClass itinD32,
1644 InstrItinClass itinQ16, InstrItinClass itinQ32,
1645 string OpcodeStr, string Dt,
1646 Intrinsic IntOp, bit Commutable = 0> {
1647 // 64-bit vector types.
1648 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1649 OpcodeStr, !strconcat(Dt, "16"),
1650 v4i16, v4i16, IntOp, Commutable>;
1651 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1652 OpcodeStr, !strconcat(Dt, "32"),
1653 v2i32, v2i32, IntOp, Commutable>;
1655 // 128-bit vector types.
1656 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1657 OpcodeStr, !strconcat(Dt, "16"),
1658 v8i16, v8i16, IntOp, Commutable>;
1659 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1660 OpcodeStr, !strconcat(Dt, "32"),
1661 v4i32, v4i32, IntOp, Commutable>;
1664 multiclass N3VIntSL_HS<bits<4> op11_8,
1665 InstrItinClass itinD16, InstrItinClass itinD32,
1666 InstrItinClass itinQ16, InstrItinClass itinQ32,
1667 string OpcodeStr, string Dt, Intrinsic IntOp> {
1668 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1669 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1670 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1671 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1672 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1673 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1674 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1675 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1678 // ....then also with element size of 8 bits:
1679 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1680 InstrItinClass itinD16, InstrItinClass itinD32,
1681 InstrItinClass itinQ16, InstrItinClass itinQ32,
1682 string OpcodeStr, string Dt,
1683 Intrinsic IntOp, bit Commutable = 0>
1684 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1685 OpcodeStr, Dt, IntOp, Commutable> {
1686 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1687 OpcodeStr, !strconcat(Dt, "8"),
1688 v8i8, v8i8, IntOp, Commutable>;
1689 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1690 OpcodeStr, !strconcat(Dt, "8"),
1691 v16i8, v16i8, IntOp, Commutable>;
1694 // ....then also with element size of 64 bits:
1695 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1696 InstrItinClass itinD16, InstrItinClass itinD32,
1697 InstrItinClass itinQ16, InstrItinClass itinQ32,
1698 string OpcodeStr, string Dt,
1699 Intrinsic IntOp, bit Commutable = 0>
1700 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1701 OpcodeStr, Dt, IntOp, Commutable> {
1702 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1703 OpcodeStr, !strconcat(Dt, "64"),
1704 v1i64, v1i64, IntOp, Commutable>;
1705 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1706 OpcodeStr, !strconcat(Dt, "64"),
1707 v2i64, v2i64, IntOp, Commutable>;
1710 // Neon Narrowing 3-register vector intrinsics,
1711 // source operand element sizes of 16, 32 and 64 bits:
1712 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1713 string OpcodeStr, string Dt,
1714 Intrinsic IntOp, bit Commutable = 0> {
1715 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1716 OpcodeStr, !strconcat(Dt, "16"),
1717 v8i8, v8i16, IntOp, Commutable>;
1718 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1719 OpcodeStr, !strconcat(Dt, "32"),
1720 v4i16, v4i32, IntOp, Commutable>;
1721 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1722 OpcodeStr, !strconcat(Dt, "64"),
1723 v2i32, v2i64, IntOp, Commutable>;
1727 // Neon Long 3-register vector operations.
1729 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1730 InstrItinClass itin16, InstrItinClass itin32,
1731 string OpcodeStr, string Dt,
1732 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
1733 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
1734 OpcodeStr, !strconcat(Dt, "16"),
1735 v4i32, v4i16, OpNode, ExtOp, Commutable>;
1736 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
1737 OpcodeStr, !strconcat(Dt, "32"),
1738 v2i64, v2i32, OpNode, ExtOp, Commutable>;
1739 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
1740 OpcodeStr, !strconcat(Dt, "8"),
1741 v8i16, v8i8, OpNode, ExtOp, Commutable>;
1744 // Neon Long 3-register vector intrinsics.
1746 // First with only element sizes of 16 and 32 bits:
1747 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1748 InstrItinClass itin16, InstrItinClass itin32,
1749 string OpcodeStr, string Dt,
1750 Intrinsic IntOp, bit Commutable = 0> {
1751 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
1752 OpcodeStr, !strconcat(Dt, "16"),
1753 v4i32, v4i16, IntOp, Commutable>;
1754 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
1755 OpcodeStr, !strconcat(Dt, "32"),
1756 v2i64, v2i32, IntOp, Commutable>;
1759 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1760 InstrItinClass itin, string OpcodeStr, string Dt,
1762 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1763 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1764 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1765 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1768 // ....then also with element size of 8 bits:
1769 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1770 InstrItinClass itin16, InstrItinClass itin32,
1771 string OpcodeStr, string Dt,
1772 Intrinsic IntOp, bit Commutable = 0>
1773 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
1774 IntOp, Commutable> {
1775 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
1776 OpcodeStr, !strconcat(Dt, "8"),
1777 v8i16, v8i8, IntOp, Commutable>;
1781 // Neon Wide 3-register vector intrinsics,
1782 // source operand element sizes of 8, 16 and 32 bits:
1783 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1784 string OpcodeStr, string Dt,
1785 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
1786 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
1787 OpcodeStr, !strconcat(Dt, "8"),
1788 v8i16, v8i8, OpNode, ExtOp, Commutable>;
1789 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
1790 OpcodeStr, !strconcat(Dt, "16"),
1791 v4i32, v4i16, OpNode, ExtOp, Commutable>;
1792 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
1793 OpcodeStr, !strconcat(Dt, "32"),
1794 v2i64, v2i32, OpNode, ExtOp, Commutable>;
1798 // Neon Multiply-Op vector operations,
1799 // element sizes of 8, 16 and 32 bits:
1800 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1801 InstrItinClass itinD16, InstrItinClass itinD32,
1802 InstrItinClass itinQ16, InstrItinClass itinQ32,
1803 string OpcodeStr, string Dt, SDNode OpNode> {
1804 // 64-bit vector types.
1805 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1806 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1807 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1808 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1809 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1810 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1812 // 128-bit vector types.
1813 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1814 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1815 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1816 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1817 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1818 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1821 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1822 InstrItinClass itinD16, InstrItinClass itinD32,
1823 InstrItinClass itinQ16, InstrItinClass itinQ32,
1824 string OpcodeStr, string Dt, SDNode ShOp> {
1825 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1826 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1827 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1828 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1829 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1830 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1832 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1833 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1837 // Neon 3-argument intrinsics,
1838 // element sizes of 8, 16 and 32 bits:
1839 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1840 InstrItinClass itinD, InstrItinClass itinQ,
1841 string OpcodeStr, string Dt, Intrinsic IntOp> {
1842 // 64-bit vector types.
1843 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
1844 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1845 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
1846 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1847 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
1848 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1850 // 128-bit vector types.
1851 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
1852 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1853 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
1854 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1855 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
1856 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1860 // Neon Long 3-argument intrinsics.
1862 // First with only element sizes of 16 and 32 bits:
1863 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1864 InstrItinClass itin16, InstrItinClass itin32,
1865 string OpcodeStr, string Dt, Intrinsic IntOp> {
1866 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
1867 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1868 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
1869 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1872 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1873 string OpcodeStr, string Dt, Intrinsic IntOp> {
1874 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1875 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1876 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1877 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1880 // ....then also with element size of 8 bits:
1881 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1882 InstrItinClass itin16, InstrItinClass itin32,
1883 string OpcodeStr, string Dt, Intrinsic IntOp>
1884 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
1885 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
1886 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1890 // Neon 2-register vector intrinsics,
1891 // element sizes of 8, 16 and 32 bits:
1892 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1893 bits<5> op11_7, bit op4,
1894 InstrItinClass itinD, InstrItinClass itinQ,
1895 string OpcodeStr, string Dt, Intrinsic IntOp> {
1896 // 64-bit vector types.
1897 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1898 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1899 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1900 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1901 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1902 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1904 // 128-bit vector types.
1905 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1906 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1907 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1908 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1909 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1910 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1914 // Neon Pairwise long 2-register intrinsics,
1915 // element sizes of 8, 16 and 32 bits:
1916 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1917 bits<5> op11_7, bit op4,
1918 string OpcodeStr, string Dt, Intrinsic IntOp> {
1919 // 64-bit vector types.
1920 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1921 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1922 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1923 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1924 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1925 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1927 // 128-bit vector types.
1928 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1929 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1930 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1931 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1932 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1933 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1937 // Neon Pairwise long 2-register accumulate intrinsics,
1938 // element sizes of 8, 16 and 32 bits:
1939 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1940 bits<5> op11_7, bit op4,
1941 string OpcodeStr, string Dt, Intrinsic IntOp> {
1942 // 64-bit vector types.
1943 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1944 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1945 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1946 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1947 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1948 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1950 // 128-bit vector types.
1951 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1952 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1953 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1954 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1955 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1956 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1960 // Neon 2-register vector shift by immediate,
1961 // with f of either N2RegVShLFrm or N2RegVShRFrm
1962 // element sizes of 8, 16, 32 and 64 bits:
1963 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1964 InstrItinClass itin, string OpcodeStr, string Dt,
1965 SDNode OpNode, Format f> {
1966 // 64-bit vector types.
1967 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1968 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1969 let Inst{21-19} = 0b001; // imm6 = 001xxx
1971 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1972 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1973 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1975 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1976 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1977 let Inst{21} = 0b1; // imm6 = 1xxxxx
1979 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
1980 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1983 // 128-bit vector types.
1984 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1985 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1986 let Inst{21-19} = 0b001; // imm6 = 001xxx
1988 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1989 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1990 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1992 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1993 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1994 let Inst{21} = 0b1; // imm6 = 1xxxxx
1996 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
1997 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
2001 // Neon Shift-Accumulate vector operations,
2002 // element sizes of 8, 16, 32 and 64 bits:
2003 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2004 string OpcodeStr, string Dt, SDNode ShOp> {
2005 // 64-bit vector types.
2006 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2007 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
2008 let Inst{21-19} = 0b001; // imm6 = 001xxx
2010 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2011 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
2012 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2014 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
2015 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
2016 let Inst{21} = 0b1; // imm6 = 1xxxxx
2018 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
2019 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
2022 // 128-bit vector types.
2023 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2024 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
2025 let Inst{21-19} = 0b001; // imm6 = 001xxx
2027 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2028 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
2029 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2031 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
2032 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
2033 let Inst{21} = 0b1; // imm6 = 1xxxxx
2035 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
2036 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
2041 // Neon Shift-Insert vector operations,
2042 // with f of either N2RegVShLFrm or N2RegVShRFrm
2043 // element sizes of 8, 16, 32 and 64 bits:
2044 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2045 string OpcodeStr, SDNode ShOp,
2047 // 64-bit vector types.
2048 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
2049 f, OpcodeStr, "8", v8i8, ShOp> {
2050 let Inst{21-19} = 0b001; // imm6 = 001xxx
2052 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
2053 f, OpcodeStr, "16", v4i16, ShOp> {
2054 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2056 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
2057 f, OpcodeStr, "32", v2i32, ShOp> {
2058 let Inst{21} = 0b1; // imm6 = 1xxxxx
2060 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
2061 f, OpcodeStr, "64", v1i64, ShOp>;
2064 // 128-bit vector types.
2065 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
2066 f, OpcodeStr, "8", v16i8, ShOp> {
2067 let Inst{21-19} = 0b001; // imm6 = 001xxx
2069 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
2070 f, OpcodeStr, "16", v8i16, ShOp> {
2071 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2073 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
2074 f, OpcodeStr, "32", v4i32, ShOp> {
2075 let Inst{21} = 0b1; // imm6 = 1xxxxx
2077 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
2078 f, OpcodeStr, "64", v2i64, ShOp>;
2082 // Neon Shift Long operations,
2083 // element sizes of 8, 16, 32 bits:
2084 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2085 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
2086 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2087 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
2088 let Inst{21-19} = 0b001; // imm6 = 001xxx
2090 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2091 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2092 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2094 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2095 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2096 let Inst{21} = 0b1; // imm6 = 1xxxxx
2100 // Neon Shift Narrow operations,
2101 // element sizes of 16, 32, 64 bits:
2102 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2103 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2105 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2106 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2107 let Inst{21-19} = 0b001; // imm6 = 001xxx
2109 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2110 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2111 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2113 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2114 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2115 let Inst{21} = 0b1; // imm6 = 1xxxxx
2119 //===----------------------------------------------------------------------===//
2120 // Instruction Definitions.
2121 //===----------------------------------------------------------------------===//
2123 // Vector Add Operations.
2125 // VADD : Vector Add (integer and floating-point)
2126 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2128 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2129 v2f32, v2f32, fadd, 1>;
2130 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2131 v4f32, v4f32, fadd, 1>;
2132 // VADDL : Vector Add Long (Q = D + D)
2133 defm VADDLs : N3VL_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2134 "vaddl", "s", add, sext, 1>;
2135 defm VADDLu : N3VL_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2136 "vaddl", "u", add, zext, 1>;
2137 // VADDW : Vector Add Wide (Q = Q + D)
2138 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
2139 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
2140 // VHADD : Vector Halving Add
2141 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2142 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2143 "vhadd", "s", int_arm_neon_vhadds, 1>;
2144 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2145 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2146 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2147 // VRHADD : Vector Rounding Halving Add
2148 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2149 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2150 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2151 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2152 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2153 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2154 // VQADD : Vector Saturating Add
2155 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2156 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2157 "vqadd", "s", int_arm_neon_vqadds, 1>;
2158 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2159 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2160 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2161 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2162 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2163 int_arm_neon_vaddhn, 1>;
2164 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2165 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2166 int_arm_neon_vraddhn, 1>;
2168 // Vector Multiply Operations.
2170 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2171 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2172 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2173 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2174 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2175 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2176 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2177 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2178 v2f32, v2f32, fmul, 1>;
2179 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2180 v4f32, v4f32, fmul, 1>;
2181 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2182 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2183 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2186 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2187 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2188 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2189 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2190 (DSubReg_i16_reg imm:$lane))),
2191 (SubReg_i16_lane imm:$lane)))>;
2192 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2193 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2194 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2195 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2196 (DSubReg_i32_reg imm:$lane))),
2197 (SubReg_i32_lane imm:$lane)))>;
2198 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2199 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2200 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2201 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2202 (DSubReg_i32_reg imm:$lane))),
2203 (SubReg_i32_lane imm:$lane)))>;
2205 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2206 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2207 IIC_VMULi16Q, IIC_VMULi32Q,
2208 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2209 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2210 IIC_VMULi16Q, IIC_VMULi32Q,
2211 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2212 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2213 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2215 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2216 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2217 (DSubReg_i16_reg imm:$lane))),
2218 (SubReg_i16_lane imm:$lane)))>;
2219 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2220 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2222 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2223 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2224 (DSubReg_i32_reg imm:$lane))),
2225 (SubReg_i32_lane imm:$lane)))>;
2227 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2228 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2229 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2230 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2231 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2232 IIC_VMULi16Q, IIC_VMULi32Q,
2233 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2234 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2235 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2237 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2238 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2239 (DSubReg_i16_reg imm:$lane))),
2240 (SubReg_i16_lane imm:$lane)))>;
2241 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2242 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2244 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2245 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2246 (DSubReg_i32_reg imm:$lane))),
2247 (SubReg_i32_lane imm:$lane)))>;
2249 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2250 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2251 "vmull", "s", int_arm_neon_vmulls, 1>;
2252 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2253 "vmull", "u", int_arm_neon_vmullu, 1>;
2254 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2255 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2256 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2257 int_arm_neon_vmulls>;
2258 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2259 int_arm_neon_vmullu>;
2261 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2262 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2263 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2264 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2265 "vqdmull", "s", int_arm_neon_vqdmull>;
2267 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2269 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2270 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2271 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2272 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2274 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2276 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2277 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2278 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2280 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2281 v4f32, v2f32, fmul, fadd>;
2283 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2284 (mul (v8i16 QPR:$src2),
2285 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2286 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2287 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2288 (DSubReg_i16_reg imm:$lane))),
2289 (SubReg_i16_lane imm:$lane)))>;
2291 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2292 (mul (v4i32 QPR:$src2),
2293 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2294 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2295 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2296 (DSubReg_i32_reg imm:$lane))),
2297 (SubReg_i32_lane imm:$lane)))>;
2299 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2300 (fmul (v4f32 QPR:$src2),
2301 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2302 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2304 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2305 (DSubReg_i32_reg imm:$lane))),
2306 (SubReg_i32_lane imm:$lane)))>;
2308 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2309 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2310 "vmlal", "s", int_arm_neon_vmlals>;
2311 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2312 "vmlal", "u", int_arm_neon_vmlalu>;
2314 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2315 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2317 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2318 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2319 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2320 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2322 // VMLS : Vector Multiply Subtract (integer and floating-point)
2323 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2324 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2325 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2327 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2329 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2330 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2331 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2333 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2334 v4f32, v2f32, fmul, fsub>;
2336 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2337 (mul (v8i16 QPR:$src2),
2338 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2339 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2340 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2341 (DSubReg_i16_reg imm:$lane))),
2342 (SubReg_i16_lane imm:$lane)))>;
2344 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2345 (mul (v4i32 QPR:$src2),
2346 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2347 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2348 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2349 (DSubReg_i32_reg imm:$lane))),
2350 (SubReg_i32_lane imm:$lane)))>;
2352 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2353 (fmul (v4f32 QPR:$src2),
2354 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2355 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2356 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2357 (DSubReg_i32_reg imm:$lane))),
2358 (SubReg_i32_lane imm:$lane)))>;
2360 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2361 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2362 "vmlsl", "s", int_arm_neon_vmlsls>;
2363 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2364 "vmlsl", "u", int_arm_neon_vmlslu>;
2366 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2367 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2369 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2370 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2371 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2372 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2374 // Vector Subtract Operations.
2376 // VSUB : Vector Subtract (integer and floating-point)
2377 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2378 "vsub", "i", sub, 0>;
2379 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2380 v2f32, v2f32, fsub, 0>;
2381 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2382 v4f32, v4f32, fsub, 0>;
2383 // VSUBL : Vector Subtract Long (Q = D - D)
2384 defm VSUBLs : N3VL_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2385 "vsubl", "s", sub, sext, 0>;
2386 defm VSUBLu : N3VL_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2387 "vsubl", "u", sub, zext, 0>;
2388 // VSUBW : Vector Subtract Wide (Q = Q - D)
2389 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
2390 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
2391 // VHSUB : Vector Halving Subtract
2392 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2393 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2394 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2395 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2396 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2397 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2398 // VQSUB : Vector Saturing Subtract
2399 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2400 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2401 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2402 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2403 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2404 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2405 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2406 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2407 int_arm_neon_vsubhn, 0>;
2408 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2409 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2410 int_arm_neon_vrsubhn, 0>;
2412 // Vector Comparisons.
2414 // VCEQ : Vector Compare Equal
2415 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2416 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2417 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2419 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2421 // For disassembly only.
2422 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2425 // VCGE : Vector Compare Greater Than or Equal
2426 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2427 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2428 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2429 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2430 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2432 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2434 // For disassembly only.
2435 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2437 // For disassembly only.
2438 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2441 // VCGT : Vector Compare Greater Than
2442 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2443 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2444 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2445 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2446 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2448 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2450 // For disassembly only.
2451 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2453 // For disassembly only.
2454 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2457 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2458 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2459 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2460 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2461 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2462 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2463 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2464 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2465 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2466 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2467 // VTST : Vector Test Bits
2468 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2469 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2471 // Vector Bitwise Operations.
2473 def vnotd : PatFrag<(ops node:$in),
2474 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2475 def vnotq : PatFrag<(ops node:$in),
2476 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2479 // VAND : Vector Bitwise AND
2480 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2481 v2i32, v2i32, and, 1>;
2482 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2483 v4i32, v4i32, and, 1>;
2485 // VEOR : Vector Bitwise Exclusive OR
2486 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2487 v2i32, v2i32, xor, 1>;
2488 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2489 v4i32, v4i32, xor, 1>;
2491 // VORR : Vector Bitwise OR
2492 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2493 v2i32, v2i32, or, 1>;
2494 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2495 v4i32, v4i32, or, 1>;
2497 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2498 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2499 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2500 "vbic", "$dst, $src1, $src2", "",
2501 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2502 (vnotd DPR:$src2))))]>;
2503 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2504 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2505 "vbic", "$dst, $src1, $src2", "",
2506 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2507 (vnotq QPR:$src2))))]>;
2509 // VORN : Vector Bitwise OR NOT
2510 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2511 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2512 "vorn", "$dst, $src1, $src2", "",
2513 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2514 (vnotd DPR:$src2))))]>;
2515 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2516 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2517 "vorn", "$dst, $src1, $src2", "",
2518 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2519 (vnotq QPR:$src2))))]>;
2521 // VMVN : Vector Bitwise NOT (Immediate)
2523 let isReMaterializable = 1 in {
2524 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2525 (ins nModImm:$SIMM), IIC_VMOVImm,
2526 "vmvn", "i16", "$dst, $SIMM", "",
2527 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2528 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2529 (ins nModImm:$SIMM), IIC_VMOVImm,
2530 "vmvn", "i16", "$dst, $SIMM", "",
2531 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2533 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2534 (ins nModImm:$SIMM), IIC_VMOVImm,
2535 "vmvn", "i32", "$dst, $SIMM", "",
2536 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2537 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2538 (ins nModImm:$SIMM), IIC_VMOVImm,
2539 "vmvn", "i32", "$dst, $SIMM", "",
2540 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2543 // VMVN : Vector Bitwise NOT
2544 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2545 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2546 "vmvn", "$dst, $src", "",
2547 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2548 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2549 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2550 "vmvn", "$dst, $src", "",
2551 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2552 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2553 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2555 // VBSL : Vector Bitwise Select
2556 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2557 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2558 N3RegFrm, IIC_VCNTiD,
2559 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2561 (v2i32 (or (and DPR:$src2, DPR:$src1),
2562 (and DPR:$src3, (vnotd DPR:$src1)))))]>;
2563 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2564 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2565 N3RegFrm, IIC_VCNTiQ,
2566 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2568 (v4i32 (or (and QPR:$src2, QPR:$src1),
2569 (and QPR:$src3, (vnotq QPR:$src1)))))]>;
2571 // VBIF : Vector Bitwise Insert if False
2572 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2573 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2574 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2575 N3RegFrm, IIC_VBINiD,
2576 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2577 [/* For disassembly only; pattern left blank */]>;
2578 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2579 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2580 N3RegFrm, IIC_VBINiQ,
2581 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2582 [/* For disassembly only; pattern left blank */]>;
2584 // VBIT : Vector Bitwise Insert if True
2585 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2586 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2587 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2588 N3RegFrm, IIC_VBINiD,
2589 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2590 [/* For disassembly only; pattern left blank */]>;
2591 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2592 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2593 N3RegFrm, IIC_VBINiQ,
2594 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2595 [/* For disassembly only; pattern left blank */]>;
2597 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2598 // for equivalent operations with different register constraints; it just
2601 // Vector Absolute Differences.
2603 // VABD : Vector Absolute Difference
2604 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2605 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2606 "vabd", "s", int_arm_neon_vabds, 0>;
2607 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2608 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2609 "vabd", "u", int_arm_neon_vabdu, 0>;
2610 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2611 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2612 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2613 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2615 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2616 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2617 "vabdl", "s", int_arm_neon_vabdls, 0>;
2618 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2619 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2621 // VABA : Vector Absolute Difference and Accumulate
2622 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2623 "vaba", "s", int_arm_neon_vabas>;
2624 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2625 "vaba", "u", int_arm_neon_vabau>;
2627 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2628 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2629 "vabal", "s", int_arm_neon_vabals>;
2630 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2631 "vabal", "u", int_arm_neon_vabalu>;
2633 // Vector Maximum and Minimum.
2635 // VMAX : Vector Maximum
2636 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2637 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2638 "vmax", "s", int_arm_neon_vmaxs, 1>;
2639 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2640 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2641 "vmax", "u", int_arm_neon_vmaxu, 1>;
2642 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2644 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2645 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2647 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2649 // VMIN : Vector Minimum
2650 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2651 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2652 "vmin", "s", int_arm_neon_vmins, 1>;
2653 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2654 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2655 "vmin", "u", int_arm_neon_vminu, 1>;
2656 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2658 v2f32, v2f32, int_arm_neon_vmins, 1>;
2659 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2661 v4f32, v4f32, int_arm_neon_vmins, 1>;
2663 // Vector Pairwise Operations.
2665 // VPADD : Vector Pairwise Add
2666 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2668 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2669 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2671 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2672 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2674 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2675 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2676 IIC_VBIND, "vpadd", "f32",
2677 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2679 // VPADDL : Vector Pairwise Add Long
2680 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2681 int_arm_neon_vpaddls>;
2682 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2683 int_arm_neon_vpaddlu>;
2685 // VPADAL : Vector Pairwise Add and Accumulate Long
2686 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2687 int_arm_neon_vpadals>;
2688 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2689 int_arm_neon_vpadalu>;
2691 // VPMAX : Vector Pairwise Maximum
2692 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2693 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2694 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2695 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2696 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2697 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2698 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2699 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2700 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2701 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2702 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2703 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2704 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2705 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2707 // VPMIN : Vector Pairwise Minimum
2708 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2709 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2710 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2711 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2712 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2713 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2714 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2715 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
2716 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2717 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
2718 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2719 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
2720 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
2721 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
2723 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2725 // VRECPE : Vector Reciprocal Estimate
2726 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2727 IIC_VUNAD, "vrecpe", "u32",
2728 v2i32, v2i32, int_arm_neon_vrecpe>;
2729 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2730 IIC_VUNAQ, "vrecpe", "u32",
2731 v4i32, v4i32, int_arm_neon_vrecpe>;
2732 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2733 IIC_VUNAD, "vrecpe", "f32",
2734 v2f32, v2f32, int_arm_neon_vrecpe>;
2735 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2736 IIC_VUNAQ, "vrecpe", "f32",
2737 v4f32, v4f32, int_arm_neon_vrecpe>;
2739 // VRECPS : Vector Reciprocal Step
2740 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2741 IIC_VRECSD, "vrecps", "f32",
2742 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2743 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2744 IIC_VRECSQ, "vrecps", "f32",
2745 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2747 // VRSQRTE : Vector Reciprocal Square Root Estimate
2748 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2749 IIC_VUNAD, "vrsqrte", "u32",
2750 v2i32, v2i32, int_arm_neon_vrsqrte>;
2751 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2752 IIC_VUNAQ, "vrsqrte", "u32",
2753 v4i32, v4i32, int_arm_neon_vrsqrte>;
2754 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2755 IIC_VUNAD, "vrsqrte", "f32",
2756 v2f32, v2f32, int_arm_neon_vrsqrte>;
2757 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2758 IIC_VUNAQ, "vrsqrte", "f32",
2759 v4f32, v4f32, int_arm_neon_vrsqrte>;
2761 // VRSQRTS : Vector Reciprocal Square Root Step
2762 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2763 IIC_VRECSD, "vrsqrts", "f32",
2764 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2765 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2766 IIC_VRECSQ, "vrsqrts", "f32",
2767 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2771 // VSHL : Vector Shift
2772 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
2773 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2774 "vshl", "s", int_arm_neon_vshifts, 0>;
2775 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
2776 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2777 "vshl", "u", int_arm_neon_vshiftu, 0>;
2778 // VSHL : Vector Shift Left (Immediate)
2779 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
2781 // VSHR : Vector Shift Right (Immediate)
2782 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
2784 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
2787 // VSHLL : Vector Shift Left Long
2788 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2789 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2791 // VSHLL : Vector Shift Left Long (with maximum shift count)
2792 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2793 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2794 ValueType OpTy, SDNode OpNode>
2795 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2796 ResTy, OpTy, OpNode> {
2797 let Inst{21-16} = op21_16;
2799 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2800 v8i16, v8i8, NEONvshlli>;
2801 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2802 v4i32, v4i16, NEONvshlli>;
2803 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2804 v2i64, v2i32, NEONvshlli>;
2806 // VSHRN : Vector Shift Right and Narrow
2807 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2810 // VRSHL : Vector Rounding Shift
2811 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
2812 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2813 "vrshl", "s", int_arm_neon_vrshifts, 0>;
2814 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
2815 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2816 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2817 // VRSHR : Vector Rounding Shift Right
2818 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
2820 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
2823 // VRSHRN : Vector Rounding Shift Right and Narrow
2824 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2827 // VQSHL : Vector Saturating Shift
2828 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
2829 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2830 "vqshl", "s", int_arm_neon_vqshifts, 0>;
2831 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
2832 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2833 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2834 // VQSHL : Vector Saturating Shift Left (Immediate)
2835 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
2837 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
2839 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2840 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
2843 // VQSHRN : Vector Saturating Shift Right and Narrow
2844 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2846 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2849 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2850 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2853 // VQRSHL : Vector Saturating Rounding Shift
2854 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
2855 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2856 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
2857 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
2858 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2859 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
2861 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2862 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2864 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2867 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2868 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2871 // VSRA : Vector Shift Right and Accumulate
2872 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2873 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2874 // VRSRA : Vector Rounding Shift Right and Accumulate
2875 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2876 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2878 // VSLI : Vector Shift Left and Insert
2879 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
2880 // VSRI : Vector Shift Right and Insert
2881 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
2883 // Vector Absolute and Saturating Absolute.
2885 // VABS : Vector Absolute Value
2886 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2887 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2889 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2890 IIC_VUNAD, "vabs", "f32",
2891 v2f32, v2f32, int_arm_neon_vabs>;
2892 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2893 IIC_VUNAQ, "vabs", "f32",
2894 v4f32, v4f32, int_arm_neon_vabs>;
2896 // VQABS : Vector Saturating Absolute Value
2897 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2898 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2899 int_arm_neon_vqabs>;
2903 def vnegd : PatFrag<(ops node:$in),
2904 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
2905 def vnegq : PatFrag<(ops node:$in),
2906 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
2908 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2909 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2910 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2911 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
2912 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2913 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2914 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2915 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
2917 // VNEG : Vector Negate (integer)
2918 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2919 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2920 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2921 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2922 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2923 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2925 // VNEG : Vector Negate (floating-point)
2926 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2927 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2928 "vneg", "f32", "$dst, $src", "",
2929 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2930 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2931 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2932 "vneg", "f32", "$dst, $src", "",
2933 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2935 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
2936 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
2937 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
2938 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
2939 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
2940 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
2942 // VQNEG : Vector Saturating Negate
2943 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2944 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2945 int_arm_neon_vqneg>;
2947 // Vector Bit Counting Operations.
2949 // VCLS : Vector Count Leading Sign Bits
2950 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2951 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2953 // VCLZ : Vector Count Leading Zeros
2954 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2955 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2957 // VCNT : Vector Count One Bits
2958 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2959 IIC_VCNTiD, "vcnt", "8",
2960 v8i8, v8i8, int_arm_neon_vcnt>;
2961 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2962 IIC_VCNTiQ, "vcnt", "8",
2963 v16i8, v16i8, int_arm_neon_vcnt>;
2965 // Vector Swap -- for disassembly only.
2966 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2967 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2968 "vswp", "$dst, $src", "", []>;
2969 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2970 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2971 "vswp", "$dst, $src", "", []>;
2973 // Vector Move Operations.
2975 // VMOV : Vector Move (Register)
2977 let neverHasSideEffects = 1 in {
2978 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2979 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2980 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2981 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2983 // Pseudo vector move instructions for QQ and QQQQ registers. This should
2984 // be expanded after register allocation is completed.
2985 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
2986 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2988 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
2989 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2990 } // neverHasSideEffects
2992 // VMOV : Vector Move (Immediate)
2994 let isReMaterializable = 1 in {
2995 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2996 (ins nModImm:$SIMM), IIC_VMOVImm,
2997 "vmov", "i8", "$dst, $SIMM", "",
2998 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
2999 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
3000 (ins nModImm:$SIMM), IIC_VMOVImm,
3001 "vmov", "i8", "$dst, $SIMM", "",
3002 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
3004 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
3005 (ins nModImm:$SIMM), IIC_VMOVImm,
3006 "vmov", "i16", "$dst, $SIMM", "",
3007 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
3008 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
3009 (ins nModImm:$SIMM), IIC_VMOVImm,
3010 "vmov", "i16", "$dst, $SIMM", "",
3011 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
3013 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
3014 (ins nModImm:$SIMM), IIC_VMOVImm,
3015 "vmov", "i32", "$dst, $SIMM", "",
3016 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
3017 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
3018 (ins nModImm:$SIMM), IIC_VMOVImm,
3019 "vmov", "i32", "$dst, $SIMM", "",
3020 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
3022 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
3023 (ins nModImm:$SIMM), IIC_VMOVImm,
3024 "vmov", "i64", "$dst, $SIMM", "",
3025 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
3026 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
3027 (ins nModImm:$SIMM), IIC_VMOVImm,
3028 "vmov", "i64", "$dst, $SIMM", "",
3029 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
3030 } // isReMaterializable
3032 // VMOV : Vector Get Lane (move scalar to ARM core register)
3034 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
3035 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3036 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
3037 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
3039 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
3040 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3041 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
3042 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
3044 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
3045 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3046 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
3047 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
3049 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
3050 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3051 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
3052 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
3054 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
3055 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3056 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
3057 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
3059 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
3060 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
3061 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3062 (DSubReg_i8_reg imm:$lane))),
3063 (SubReg_i8_lane imm:$lane))>;
3064 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
3065 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3066 (DSubReg_i16_reg imm:$lane))),
3067 (SubReg_i16_lane imm:$lane))>;
3068 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
3069 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
3070 (DSubReg_i8_reg imm:$lane))),
3071 (SubReg_i8_lane imm:$lane))>;
3072 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
3073 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
3074 (DSubReg_i16_reg imm:$lane))),
3075 (SubReg_i16_lane imm:$lane))>;
3076 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
3077 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
3078 (DSubReg_i32_reg imm:$lane))),
3079 (SubReg_i32_lane imm:$lane))>;
3080 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
3081 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
3082 (SSubReg_f32_reg imm:$src2))>;
3083 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
3084 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
3085 (SSubReg_f32_reg imm:$src2))>;
3086 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
3087 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3088 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
3089 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3092 // VMOV : Vector Set Lane (move ARM core register to scalar)
3094 let Constraints = "$src1 = $dst" in {
3095 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
3096 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3097 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
3098 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
3099 GPR:$src2, imm:$lane))]>;
3100 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
3101 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3102 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
3103 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
3104 GPR:$src2, imm:$lane))]>;
3105 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
3106 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3107 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
3108 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
3109 GPR:$src2, imm:$lane))]>;
3111 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3112 (v16i8 (INSERT_SUBREG QPR:$src1,
3113 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3114 (DSubReg_i8_reg imm:$lane))),
3115 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3116 (DSubReg_i8_reg imm:$lane)))>;
3117 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3118 (v8i16 (INSERT_SUBREG QPR:$src1,
3119 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3120 (DSubReg_i16_reg imm:$lane))),
3121 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3122 (DSubReg_i16_reg imm:$lane)))>;
3123 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3124 (v4i32 (INSERT_SUBREG QPR:$src1,
3125 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3126 (DSubReg_i32_reg imm:$lane))),
3127 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3128 (DSubReg_i32_reg imm:$lane)))>;
3130 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3131 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3132 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3133 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3134 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3135 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3137 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3138 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3139 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3140 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3142 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3143 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3144 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3145 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3146 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3147 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3149 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3150 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3151 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3152 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3153 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3154 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3156 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3157 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3158 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3160 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3161 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3162 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3164 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3165 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3166 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3169 // VDUP : Vector Duplicate (from ARM core register to all elements)
3171 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3172 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3173 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3174 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3175 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3176 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3177 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3178 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3180 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3181 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3182 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3183 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3184 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3185 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3187 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3188 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3189 [(set DPR:$dst, (v2f32 (NEONvdup
3190 (f32 (bitconvert GPR:$src)))))]>;
3191 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3192 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3193 [(set QPR:$dst, (v4f32 (NEONvdup
3194 (f32 (bitconvert GPR:$src)))))]>;
3196 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3198 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3200 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3201 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3202 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3204 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3205 ValueType ResTy, ValueType OpTy>
3206 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3207 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3208 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3211 // Inst{19-16} is partially specified depending on the element size.
3213 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3214 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3215 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3216 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3217 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3218 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3219 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3220 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3222 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3223 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3224 (DSubReg_i8_reg imm:$lane))),
3225 (SubReg_i8_lane imm:$lane)))>;
3226 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3227 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3228 (DSubReg_i16_reg imm:$lane))),
3229 (SubReg_i16_lane imm:$lane)))>;
3230 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3231 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3232 (DSubReg_i32_reg imm:$lane))),
3233 (SubReg_i32_lane imm:$lane)))>;
3234 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3235 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3236 (DSubReg_i32_reg imm:$lane))),
3237 (SubReg_i32_lane imm:$lane)))>;
3239 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3240 (outs DPR:$dst), (ins SPR:$src),
3241 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3242 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3244 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3245 (outs QPR:$dst), (ins SPR:$src),
3246 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3247 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3249 // VMOVN : Vector Narrowing Move
3250 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3251 "vmovn", "i", trunc>;
3252 // VQMOVN : Vector Saturating Narrowing Move
3253 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3254 "vqmovn", "s", int_arm_neon_vqmovns>;
3255 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3256 "vqmovn", "u", int_arm_neon_vqmovnu>;
3257 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3258 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3259 // VMOVL : Vector Lengthening Move
3260 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3261 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3263 // Vector Conversions.
3265 // VCVT : Vector Convert Between Floating-Point and Integers
3266 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3267 v2i32, v2f32, fp_to_sint>;
3268 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3269 v2i32, v2f32, fp_to_uint>;
3270 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3271 v2f32, v2i32, sint_to_fp>;
3272 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3273 v2f32, v2i32, uint_to_fp>;
3275 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3276 v4i32, v4f32, fp_to_sint>;
3277 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3278 v4i32, v4f32, fp_to_uint>;
3279 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3280 v4f32, v4i32, sint_to_fp>;
3281 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3282 v4f32, v4i32, uint_to_fp>;
3284 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3285 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3286 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3287 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3288 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3289 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3290 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3291 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3292 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3294 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3295 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3296 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3297 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3298 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3299 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3300 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3301 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3305 // VREV64 : Vector Reverse elements within 64-bit doublewords
3307 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3308 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3309 (ins DPR:$src), IIC_VMOVD,
3310 OpcodeStr, Dt, "$dst, $src", "",
3311 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3312 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3313 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3314 (ins QPR:$src), IIC_VMOVD,
3315 OpcodeStr, Dt, "$dst, $src", "",
3316 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3318 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3319 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3320 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3321 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3323 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3324 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3325 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3326 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3328 // VREV32 : Vector Reverse elements within 32-bit words
3330 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3331 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3332 (ins DPR:$src), IIC_VMOVD,
3333 OpcodeStr, Dt, "$dst, $src", "",
3334 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3335 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3336 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3337 (ins QPR:$src), IIC_VMOVD,
3338 OpcodeStr, Dt, "$dst, $src", "",
3339 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3341 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3342 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3344 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3345 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3347 // VREV16 : Vector Reverse elements within 16-bit halfwords
3349 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3350 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3351 (ins DPR:$src), IIC_VMOVD,
3352 OpcodeStr, Dt, "$dst, $src", "",
3353 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3354 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3355 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3356 (ins QPR:$src), IIC_VMOVD,
3357 OpcodeStr, Dt, "$dst, $src", "",
3358 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3360 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3361 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3363 // Other Vector Shuffles.
3365 // VEXT : Vector Extract
3367 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3368 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3369 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3370 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3371 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3372 (Ty DPR:$rhs), imm:$index)))]>;
3374 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3375 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3376 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3377 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3378 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3379 (Ty QPR:$rhs), imm:$index)))]>;
3381 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3382 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3383 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3384 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3386 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3387 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3388 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3389 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3391 // VTRN : Vector Transpose
3393 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3394 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3395 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3397 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3398 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3399 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3401 // VUZP : Vector Unzip (Deinterleave)
3403 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3404 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3405 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3407 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3408 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3409 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3411 // VZIP : Vector Zip (Interleave)
3413 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3414 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3415 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3417 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3418 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3419 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3421 // Vector Table Lookup and Table Extension.
3423 // VTBL : Vector Table Lookup
3425 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3426 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3427 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3428 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3429 let hasExtraSrcRegAllocReq = 1 in {
3431 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3432 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3433 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3435 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3436 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3437 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3439 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3440 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3442 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3443 } // hasExtraSrcRegAllocReq = 1
3445 // VTBX : Vector Table Extension
3447 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3448 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3449 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3450 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3451 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3452 let hasExtraSrcRegAllocReq = 1 in {
3454 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3455 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3456 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3458 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3459 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3460 NVTBLFrm, IIC_VTBX3,
3461 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3462 "$orig = $dst", []>;
3464 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3465 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3466 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3467 "$orig = $dst", []>;
3468 } // hasExtraSrcRegAllocReq = 1
3470 //===----------------------------------------------------------------------===//
3471 // NEON instructions for single-precision FP math
3472 //===----------------------------------------------------------------------===//
3474 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3475 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3476 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3480 class N3VSPat<SDNode OpNode, NeonI Inst>
3481 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3482 (EXTRACT_SUBREG (v2f32
3483 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3485 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3489 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3490 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3491 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3493 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3495 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3499 // These need separate instructions because they must use DPR_VFP2 register
3500 // class which have SPR sub-registers.
3502 // Vector Add Operations used for single-precision FP
3503 let neverHasSideEffects = 1 in
3504 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3505 def : N3VSPat<fadd, VADDfd_sfp>;
3507 // Vector Sub Operations used for single-precision FP
3508 let neverHasSideEffects = 1 in
3509 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3510 def : N3VSPat<fsub, VSUBfd_sfp>;
3512 // Vector Multiply Operations used for single-precision FP
3513 let neverHasSideEffects = 1 in
3514 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3515 def : N3VSPat<fmul, VMULfd_sfp>;
3517 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3518 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3519 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3521 //let neverHasSideEffects = 1 in
3522 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3523 // v2f32, fmul, fadd>;
3524 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3526 //let neverHasSideEffects = 1 in
3527 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3528 // v2f32, fmul, fsub>;
3529 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3531 // Vector Absolute used for single-precision FP
3532 let neverHasSideEffects = 1 in
3533 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3534 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3535 "vabs", "f32", "$dst, $src", "", []>;
3536 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3538 // Vector Negate used for single-precision FP
3539 let neverHasSideEffects = 1 in
3540 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3541 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3542 "vneg", "f32", "$dst, $src", "", []>;
3543 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3545 // Vector Maximum used for single-precision FP
3546 let neverHasSideEffects = 1 in
3547 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3548 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3549 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3550 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3552 // Vector Minimum used for single-precision FP
3553 let neverHasSideEffects = 1 in
3554 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3555 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3556 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3557 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3559 // Vector Convert between single-precision FP and integer
3560 let neverHasSideEffects = 1 in
3561 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3562 v2i32, v2f32, fp_to_sint>;
3563 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3565 let neverHasSideEffects = 1 in
3566 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3567 v2i32, v2f32, fp_to_uint>;
3568 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3570 let neverHasSideEffects = 1 in
3571 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3572 v2f32, v2i32, sint_to_fp>;
3573 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3575 let neverHasSideEffects = 1 in
3576 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3577 v2f32, v2i32, uint_to_fp>;
3578 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3580 //===----------------------------------------------------------------------===//
3581 // Non-Instruction Patterns
3582 //===----------------------------------------------------------------------===//
3585 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3586 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3587 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3588 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3589 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3590 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3591 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3592 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3593 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3594 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3595 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3596 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3597 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3598 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3599 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3600 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3601 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3602 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3603 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3604 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3605 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3606 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3607 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3608 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3609 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3610 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3611 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3612 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3613 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3614 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3616 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3617 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3618 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3619 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3620 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3621 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3622 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3623 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3624 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3625 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3626 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3627 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3628 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3629 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3630 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3631 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3632 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3633 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3634 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3635 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3636 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3637 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3638 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3639 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3640 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3641 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3642 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3643 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3644 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3645 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;