1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
69 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
70 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
72 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
74 // VDUPLANE can produce a quad-register result from a double-register source,
75 // so the result is not constrained to match the source.
76 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
80 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
82 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
84 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
85 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
86 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
87 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
89 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
93 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
94 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
96 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
98 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
99 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
101 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
102 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
103 unsigned EltBits = 0;
104 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
105 return (EltBits == 32 && EltVal == 0);
108 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
109 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
110 unsigned EltBits = 0;
111 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
112 return (EltBits == 8 && EltVal == 0xff);
115 //===----------------------------------------------------------------------===//
116 // NEON operand definitions
117 //===----------------------------------------------------------------------===//
119 def nModImm : Operand<i32> {
120 let PrintMethod = "printNEONModImmOperand";
123 //===----------------------------------------------------------------------===//
124 // NEON load / store instructions
125 //===----------------------------------------------------------------------===//
127 let mayLoad = 1, neverHasSideEffects = 1 in {
128 // Use vldmia to load a Q register as a D register pair.
129 // This is equivalent to VLDMD except that it has a Q register operand
130 // instead of a pair of D registers.
132 : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
133 IndexModeNone, IIC_fpLoadm,
134 "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
136 // Use vld1 to load a Q register as a D register pair.
137 // This alternative to VLDMQ allows an alignment to be specified.
138 // This is equivalent to VLD1q64 except that it has a Q register operand.
140 : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
141 IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
142 } // mayLoad = 1, neverHasSideEffects = 1
144 let mayStore = 1, neverHasSideEffects = 1 in {
145 // Use vstmia to store a Q register as a D register pair.
146 // This is equivalent to VSTMD except that it has a Q register operand
147 // instead of a pair of D registers.
149 : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
150 IndexModeNone, IIC_fpStorem,
151 "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
153 // Use vst1 to store a Q register as a D register pair.
154 // This alternative to VSTMQ allows an alignment to be specified.
155 // This is equivalent to VST1q64 except that it has a Q register operand.
157 : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
158 IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
159 } // mayStore = 1, neverHasSideEffects = 1
161 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
163 // VLD1 : Vector Load (multiple single elements)
164 class VLD1D<bits<4> op7_4, string Dt>
165 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst),
166 (ins addrmode6:$addr), IIC_VLD1,
167 "vld1", Dt, "\\{$dst\\}, $addr", "", []>;
168 class VLD1Q<bits<4> op7_4, string Dt>
169 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
170 (ins addrmode6:$addr), IIC_VLD1,
171 "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
173 def VLD1d8 : VLD1D<0b0000, "8">;
174 def VLD1d16 : VLD1D<0b0100, "16">;
175 def VLD1d32 : VLD1D<0b1000, "32">;
176 def VLD1d64 : VLD1D<0b1100, "64">;
178 def VLD1q8 : VLD1Q<0b0000, "8">;
179 def VLD1q16 : VLD1Q<0b0100, "16">;
180 def VLD1q32 : VLD1Q<0b1000, "32">;
181 def VLD1q64 : VLD1Q<0b1100, "64">;
183 // ...with address register writeback:
184 class VLD1DWB<bits<4> op7_4, string Dt>
185 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
186 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
187 "vld1", Dt, "\\{$dst\\}, $addr$offset",
188 "$addr.addr = $wb", []>;
189 class VLD1QWB<bits<4> op7_4, string Dt>
190 : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
191 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
192 "vld1", Dt, "${dst:dregpair}, $addr$offset",
193 "$addr.addr = $wb", []>;
195 def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
196 def VLD1d16_UPD : VLD1DWB<0b0100, "16">;
197 def VLD1d32_UPD : VLD1DWB<0b1000, "32">;
198 def VLD1d64_UPD : VLD1DWB<0b1100, "64">;
200 def VLD1q8_UPD : VLD1QWB<0b0000, "8">;
201 def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
202 def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
203 def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
205 // ...with 3 registers (some of these are only for the disassembler):
206 class VLD1D3<bits<4> op7_4, string Dt>
207 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
208 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
209 "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
210 class VLD1D3WB<bits<4> op7_4, string Dt>
211 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
212 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
213 "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
215 def VLD1d8T : VLD1D3<0b0000, "8">;
216 def VLD1d16T : VLD1D3<0b0100, "16">;
217 def VLD1d32T : VLD1D3<0b1000, "32">;
218 def VLD1d64T : VLD1D3<0b1100, "64">;
220 def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
221 def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
222 def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
223 def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
225 // ...with 4 registers (some of these are only for the disassembler):
226 class VLD1D4<bits<4> op7_4, string Dt>
227 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
228 (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
229 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
230 class VLD1D4WB<bits<4> op7_4, string Dt>
231 : NLdSt<0,0b10,0b0010,op7_4,
232 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
233 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
234 "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
237 def VLD1d8Q : VLD1D4<0b0000, "8">;
238 def VLD1d16Q : VLD1D4<0b0100, "16">;
239 def VLD1d32Q : VLD1D4<0b1000, "32">;
240 def VLD1d64Q : VLD1D4<0b1100, "64">;
242 def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
243 def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
244 def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
245 def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
247 // VLD2 : Vector Load (multiple 2-element structures)
248 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
249 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
250 (ins addrmode6:$addr), IIC_VLD2,
251 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
252 class VLD2Q<bits<4> op7_4, string Dt>
253 : NLdSt<0, 0b10, 0b0011, op7_4,
254 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
255 (ins addrmode6:$addr), IIC_VLD2,
256 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
258 def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
259 def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
260 def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
262 def VLD2q8 : VLD2Q<0b0000, "8">;
263 def VLD2q16 : VLD2Q<0b0100, "16">;
264 def VLD2q32 : VLD2Q<0b1000, "32">;
266 // ...with address register writeback:
267 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
268 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
269 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
270 "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
271 "$addr.addr = $wb", []>;
272 class VLD2QWB<bits<4> op7_4, string Dt>
273 : NLdSt<0, 0b10, 0b0011, op7_4,
274 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
275 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
276 "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
277 "$addr.addr = $wb", []>;
279 def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
280 def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
281 def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
283 def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
284 def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
285 def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
287 // ...with double-spaced registers (for disassembly only):
288 def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
289 def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
290 def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
291 def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
292 def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
293 def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
295 // VLD3 : Vector Load (multiple 3-element structures)
296 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
297 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
298 (ins addrmode6:$addr), IIC_VLD3,
299 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
301 def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
302 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
303 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
305 // ...with address register writeback:
306 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
307 : NLdSt<0, 0b10, op11_8, op7_4,
308 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
309 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
310 "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
311 "$addr.addr = $wb", []>;
313 def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
314 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
315 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
317 // ...with double-spaced registers (non-updating versions for disassembly only):
318 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
319 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
320 def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
321 def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
322 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
323 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
325 // ...alternate versions to be allocated odd register numbers:
326 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
327 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
328 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
330 // VLD4 : Vector Load (multiple 4-element structures)
331 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
332 : NLdSt<0, 0b10, op11_8, op7_4,
333 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
334 (ins addrmode6:$addr), IIC_VLD4,
335 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
337 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
338 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
339 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
341 // ...with address register writeback:
342 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
343 : NLdSt<0, 0b10, op11_8, op7_4,
344 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
345 (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
346 "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
347 "$addr.addr = $wb", []>;
349 def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
350 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
351 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
353 // ...with double-spaced registers (non-updating versions for disassembly only):
354 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
355 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
356 def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
357 def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
358 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
359 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
361 // ...alternate versions to be allocated odd register numbers:
362 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
363 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
364 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
366 // VLD1LN : Vector Load (single element to one lane)
367 // FIXME: Not yet implemented.
369 // VLD2LN : Vector Load (single 2-element structure to one lane)
370 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
371 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
372 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
373 IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
374 "$src1 = $dst1, $src2 = $dst2", []>;
376 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
377 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
378 def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
380 // ...with double-spaced registers:
381 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
382 def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
384 // ...alternate versions to be allocated odd register numbers:
385 def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">;
386 def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">;
388 // ...with address register writeback:
389 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
390 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
391 (ins addrmode6:$addr, am6offset:$offset,
392 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
393 "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
394 "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
396 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
397 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
398 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
400 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
401 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
403 // VLD3LN : Vector Load (single 3-element structure to one lane)
404 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
405 : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
406 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
407 nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
408 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
409 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
411 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">;
412 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
413 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
415 // ...with double-spaced registers:
416 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
417 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
419 // ...alternate versions to be allocated odd register numbers:
420 def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">;
421 def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">;
423 // ...with address register writeback:
424 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
425 : NLdSt<1, 0b10, op11_8, op7_4,
426 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
427 (ins addrmode6:$addr, am6offset:$offset,
428 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
429 IIC_VLD3, "vld3", Dt,
430 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
431 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
434 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">;
435 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
436 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
438 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
439 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
441 // VLD4LN : Vector Load (single 4-element structure to one lane)
442 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
443 : NLdSt<1, 0b10, op11_8, op7_4,
444 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
445 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
446 nohash_imm:$lane), IIC_VLD4, "vld4", Dt,
447 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr",
448 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
450 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">;
451 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">;
452 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">;
454 // ...with double-spaced registers:
455 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">;
456 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">;
458 // ...alternate versions to be allocated odd register numbers:
459 def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">;
460 def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">;
462 // ...with address register writeback:
463 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
464 : NLdSt<1, 0b10, op11_8, op7_4,
465 (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
466 (ins addrmode6:$addr, am6offset:$offset,
467 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
468 IIC_VLD4, "vld4", Dt,
469 "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset",
470 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb",
473 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">;
474 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">;
475 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">;
477 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">;
478 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
480 // VLD1DUP : Vector Load (single element to all lanes)
481 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
482 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
483 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
484 // FIXME: Not yet implemented.
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
489 // Classes for VST* pseudo-instructions with multi-register operands.
490 // These are expanded to real instructions after register allocation.
492 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
494 : PseudoNLdSt<(outs GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST,
497 class VSTQQQQWBPseudo
498 : PseudoNLdSt<(outs GPR:$wb),
499 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
502 // VST1 : Vector Store (multiple single elements)
503 class VST1D<bits<4> op7_4, string Dt>
504 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
505 "vst1", Dt, "\\{$src\\}, $addr", "", []>;
506 class VST1Q<bits<4> op7_4, string Dt>
507 : NLdSt<0,0b00,0b1010,op7_4, (outs),
508 (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
509 "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
511 def VST1d8 : VST1D<0b0000, "8">;
512 def VST1d16 : VST1D<0b0100, "16">;
513 def VST1d32 : VST1D<0b1000, "32">;
514 def VST1d64 : VST1D<0b1100, "64">;
516 def VST1q8 : VST1Q<0b0000, "8">;
517 def VST1q16 : VST1Q<0b0100, "16">;
518 def VST1q32 : VST1Q<0b1000, "32">;
519 def VST1q64 : VST1Q<0b1100, "64">;
521 // ...with address register writeback:
522 class VST1DWB<bits<4> op7_4, string Dt>
523 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
524 (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST,
525 "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
526 class VST1QWB<bits<4> op7_4, string Dt>
527 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
528 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
529 "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
531 def VST1d8_UPD : VST1DWB<0b0000, "8">;
532 def VST1d16_UPD : VST1DWB<0b0100, "16">;
533 def VST1d32_UPD : VST1DWB<0b1000, "32">;
534 def VST1d64_UPD : VST1DWB<0b1100, "64">;
536 def VST1q8_UPD : VST1QWB<0b0000, "8">;
537 def VST1q16_UPD : VST1QWB<0b0100, "16">;
538 def VST1q32_UPD : VST1QWB<0b1000, "32">;
539 def VST1q64_UPD : VST1QWB<0b1100, "64">;
541 // ...with 3 registers (some of these are only for the disassembler):
542 class VST1D3<bits<4> op7_4, string Dt>
543 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
544 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
545 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
546 class VST1D3WB<bits<4> op7_4, string Dt>
547 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
548 (ins addrmode6:$addr, am6offset:$offset,
549 DPR:$src1, DPR:$src2, DPR:$src3),
550 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
551 "$addr.addr = $wb", []>;
553 def VST1d8T : VST1D3<0b0000, "8">;
554 def VST1d16T : VST1D3<0b0100, "16">;
555 def VST1d32T : VST1D3<0b1000, "32">;
556 def VST1d64T : VST1D3<0b1100, "64">;
558 def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
559 def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
560 def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
561 def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
563 def VST1d64TPseudo : VSTQQPseudo;
564 def VST1d64TPseudo_UPD : VSTQQWBPseudo;
566 // ...with 4 registers (some of these are only for the disassembler):
567 class VST1D4<bits<4> op7_4, string Dt>
568 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
569 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
570 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
572 class VST1D4WB<bits<4> op7_4, string Dt>
573 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
574 (ins addrmode6:$addr, am6offset:$offset,
575 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
576 IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
577 "$addr.addr = $wb", []>;
579 def VST1d8Q : VST1D4<0b0000, "8">;
580 def VST1d16Q : VST1D4<0b0100, "16">;
581 def VST1d32Q : VST1D4<0b1000, "32">;
582 def VST1d64Q : VST1D4<0b1100, "64">;
584 def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
585 def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
586 def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
587 def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
589 def VST1d64QPseudo : VSTQQPseudo;
590 def VST1d64QPseudo_UPD : VSTQQWBPseudo;
592 // VST2 : Vector Store (multiple 2-element structures)
593 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
594 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
595 (ins addrmode6:$addr, DPR:$src1, DPR:$src2),
596 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
597 class VST2Q<bits<4> op7_4, string Dt>
598 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
599 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
600 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
603 def VST2d8 : VST2D<0b1000, 0b0000, "8">;
604 def VST2d16 : VST2D<0b1000, 0b0100, "16">;
605 def VST2d32 : VST2D<0b1000, 0b1000, "32">;
607 def VST2q8 : VST2Q<0b0000, "8">;
608 def VST2q16 : VST2Q<0b0100, "16">;
609 def VST2q32 : VST2Q<0b1000, "32">;
611 // ...with address register writeback:
612 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
613 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
614 (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
615 IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
616 "$addr.addr = $wb", []>;
617 class VST2QWB<bits<4> op7_4, string Dt>
618 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
619 (ins addrmode6:$addr, am6offset:$offset,
620 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
621 IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
622 "$addr.addr = $wb", []>;
624 def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
625 def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
626 def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
628 def VST2q8_UPD : VST2QWB<0b0000, "8">;
629 def VST2q16_UPD : VST2QWB<0b0100, "16">;
630 def VST2q32_UPD : VST2QWB<0b1000, "32">;
632 // ...with double-spaced registers (for disassembly only):
633 def VST2b8 : VST2D<0b1001, 0b0000, "8">;
634 def VST2b16 : VST2D<0b1001, 0b0100, "16">;
635 def VST2b32 : VST2D<0b1001, 0b1000, "32">;
636 def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
637 def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
638 def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
640 // VST3 : Vector Store (multiple 3-element structures)
641 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
642 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
643 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
644 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
646 def VST3d8 : VST3D<0b0100, 0b0000, "8">;
647 def VST3d16 : VST3D<0b0100, 0b0100, "16">;
648 def VST3d32 : VST3D<0b0100, 0b1000, "32">;
650 def VST3d8Pseudo : VSTQQPseudo;
651 def VST3d16Pseudo : VSTQQPseudo;
652 def VST3d32Pseudo : VSTQQPseudo;
654 // ...with address register writeback:
655 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
656 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
657 (ins addrmode6:$addr, am6offset:$offset,
658 DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
659 "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
660 "$addr.addr = $wb", []>;
662 def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
663 def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
664 def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
666 def VST3d8Pseudo_UPD : VSTQQWBPseudo;
667 def VST3d16Pseudo_UPD : VSTQQWBPseudo;
668 def VST3d32Pseudo_UPD : VSTQQWBPseudo;
670 // ...with double-spaced registers (non-updating versions for disassembly only):
671 def VST3q8 : VST3D<0b0101, 0b0000, "8">;
672 def VST3q16 : VST3D<0b0101, 0b0100, "16">;
673 def VST3q32 : VST3D<0b0101, 0b1000, "32">;
674 def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
675 def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
676 def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
678 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo;
679 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo;
680 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo;
682 // ...alternate versions to be allocated odd register numbers:
683 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo;
684 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo;
685 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo;
687 // VST4 : Vector Store (multiple 4-element structures)
688 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
689 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
690 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
691 IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
694 def VST4d8 : VST4D<0b0000, 0b0000, "8">;
695 def VST4d16 : VST4D<0b0000, 0b0100, "16">;
696 def VST4d32 : VST4D<0b0000, 0b1000, "32">;
698 def VST4d8Pseudo : VSTQQPseudo;
699 def VST4d16Pseudo : VSTQQPseudo;
700 def VST4d32Pseudo : VSTQQPseudo;
702 // ...with address register writeback:
703 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
704 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
705 (ins addrmode6:$addr, am6offset:$offset,
706 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
707 "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
708 "$addr.addr = $wb", []>;
710 def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
711 def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
712 def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
714 def VST4d8Pseudo_UPD : VSTQQWBPseudo;
715 def VST4d16Pseudo_UPD : VSTQQWBPseudo;
716 def VST4d32Pseudo_UPD : VSTQQWBPseudo;
718 // ...with double-spaced registers (non-updating versions for disassembly only):
719 def VST4q8 : VST4D<0b0001, 0b0000, "8">;
720 def VST4q16 : VST4D<0b0001, 0b0100, "16">;
721 def VST4q32 : VST4D<0b0001, 0b1000, "32">;
722 def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
723 def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
724 def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
726 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo;
727 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo;
728 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo;
730 // ...alternate versions to be allocated odd register numbers:
731 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo;
732 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo;
733 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo;
735 // VST1LN : Vector Store (single element from one lane)
736 // FIXME: Not yet implemented.
738 // VST2LN : Vector Store (single 2-element structure from one lane)
739 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
740 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
741 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
742 IIC_VST, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr",
745 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">;
746 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">;
747 def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">;
749 // ...with double-spaced registers:
750 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">;
751 def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">;
753 // ...alternate versions to be allocated odd register numbers:
754 def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">;
755 def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">;
757 // ...with address register writeback:
758 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
759 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
760 (ins addrmode6:$addr, am6offset:$offset,
761 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST, "vst2", Dt,
762 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
763 "$addr.addr = $wb", []>;
765 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">;
766 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">;
767 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">;
769 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">;
770 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">;
772 // VST3LN : Vector Store (single 3-element structure from one lane)
773 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
774 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
775 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
776 nohash_imm:$lane), IIC_VST, "vst3", Dt,
777 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>;
779 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">;
780 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">;
781 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">;
783 // ...with double-spaced registers:
784 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">;
785 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">;
787 // ...alternate versions to be allocated odd register numbers:
788 def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">;
789 def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">;
791 // ...with address register writeback:
792 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
793 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
794 (ins addrmode6:$addr, am6offset:$offset,
795 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
797 "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset",
798 "$addr.addr = $wb", []>;
800 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">;
801 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">;
802 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">;
804 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">;
805 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">;
807 // VST4LN : Vector Store (single 4-element structure from one lane)
808 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
809 : NLdSt<1, 0b00, op11_8, op7_4, (outs),
810 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
811 nohash_imm:$lane), IIC_VST, "vst4", Dt,
812 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr",
815 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">;
816 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">;
817 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">;
819 // ...with double-spaced registers:
820 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">;
821 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">;
823 // ...alternate versions to be allocated odd register numbers:
824 def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">;
825 def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">;
827 // ...with address register writeback:
828 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
829 : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
830 (ins addrmode6:$addr, am6offset:$offset,
831 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
833 "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset",
834 "$addr.addr = $wb", []>;
836 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">;
837 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">;
838 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">;
840 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">;
841 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">;
843 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
846 //===----------------------------------------------------------------------===//
847 // NEON pattern fragments
848 //===----------------------------------------------------------------------===//
850 // Extract D sub-registers of Q registers.
851 def DSubReg_i8_reg : SDNodeXForm<imm, [{
852 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
853 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
855 def DSubReg_i16_reg : SDNodeXForm<imm, [{
856 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
857 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
859 def DSubReg_i32_reg : SDNodeXForm<imm, [{
860 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
861 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
863 def DSubReg_f64_reg : SDNodeXForm<imm, [{
864 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
865 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
868 // Extract S sub-registers of Q/D registers.
869 def SSubReg_f32_reg : SDNodeXForm<imm, [{
870 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
871 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
874 // Translate lane numbers from Q registers to D subregs.
875 def SubReg_i8_lane : SDNodeXForm<imm, [{
876 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
878 def SubReg_i16_lane : SDNodeXForm<imm, [{
879 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
881 def SubReg_i32_lane : SDNodeXForm<imm, [{
882 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
885 //===----------------------------------------------------------------------===//
886 // Instruction Classes
887 //===----------------------------------------------------------------------===//
889 // Basic 2-register operations: single-, double- and quad-register.
890 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
891 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
892 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
893 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
894 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
895 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src", "", []>;
896 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
897 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
898 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
899 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
900 (ins DPR:$src), IIC_VUNAD, OpcodeStr, Dt,"$dst, $src", "",
901 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
902 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
903 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
904 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
905 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
906 (ins QPR:$src), IIC_VUNAQ, OpcodeStr, Dt,"$dst, $src", "",
907 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
909 // Basic 2-register intrinsics, both double- and quad-register.
910 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
911 bits<2> op17_16, bits<5> op11_7, bit op4,
912 InstrItinClass itin, string OpcodeStr, string Dt,
913 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
914 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
915 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
916 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
917 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
918 bits<2> op17_16, bits<5> op11_7, bit op4,
919 InstrItinClass itin, string OpcodeStr, string Dt,
920 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
921 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
922 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
923 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
925 // Narrow 2-register intrinsics.
926 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
927 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
928 InstrItinClass itin, string OpcodeStr, string Dt,
929 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
930 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
931 (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
932 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
934 // Long 2-register operations (currently only used for VMOVL).
935 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
936 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
937 InstrItinClass itin, string OpcodeStr, string Dt,
938 ValueType TyQ, ValueType TyD, SDNode OpNode>
939 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$dst),
940 (ins DPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "",
941 [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src))))]>;
943 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
944 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
945 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
946 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
947 OpcodeStr, Dt, "$dst1, $dst2",
948 "$src1 = $dst1, $src2 = $dst2", []>;
949 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
950 InstrItinClass itin, string OpcodeStr, string Dt>
951 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
952 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$dst1, $dst2",
953 "$src1 = $dst1, $src2 = $dst2", []>;
955 // Basic 3-register operations: single-, double- and quad-register.
956 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
957 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
958 SDNode OpNode, bit Commutable>
959 : N3V<op24, op23, op21_20, op11_8, 0, op4,
960 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm,
961 IIC_VBIND, OpcodeStr, Dt, "$dst, $src1, $src2", "", []> {
962 let isCommutable = Commutable;
965 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
966 InstrItinClass itin, string OpcodeStr, string Dt,
967 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
968 : N3V<op24, op23, op21_20, op11_8, 0, op4,
969 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
970 OpcodeStr, Dt, "$dst, $src1, $src2", "",
971 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
972 let isCommutable = Commutable;
974 // Same as N3VD but no data type.
975 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
976 InstrItinClass itin, string OpcodeStr,
977 ValueType ResTy, ValueType OpTy,
978 SDNode OpNode, bit Commutable>
979 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
980 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
981 OpcodeStr, "$dst, $src1, $src2", "",
982 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]>{
983 let isCommutable = Commutable;
986 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
987 InstrItinClass itin, string OpcodeStr, string Dt,
988 ValueType Ty, SDNode ShOp>
989 : N3V<0, 1, op21_20, op11_8, 1, 0,
990 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
991 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
993 (Ty (ShOp (Ty DPR:$src1),
994 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),imm:$lane)))))]> {
995 let isCommutable = 0;
997 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
998 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
999 : N3V<0, 1, op21_20, op11_8, 1, 0,
1000 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1001 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1002 [(set (Ty DPR:$dst),
1003 (Ty (ShOp (Ty DPR:$src1),
1004 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1005 let isCommutable = 0;
1008 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1009 InstrItinClass itin, string OpcodeStr, string Dt,
1010 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1011 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1012 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1013 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1014 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1015 let isCommutable = Commutable;
1017 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1018 InstrItinClass itin, string OpcodeStr,
1019 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1020 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1021 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, itin,
1022 OpcodeStr, "$dst, $src1, $src2", "",
1023 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]>{
1024 let isCommutable = Commutable;
1026 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1027 InstrItinClass itin, string OpcodeStr, string Dt,
1028 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1029 : N3V<1, 1, op21_20, op11_8, 1, 0,
1030 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1031 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1032 [(set (ResTy QPR:$dst),
1033 (ResTy (ShOp (ResTy QPR:$src1),
1034 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1036 let isCommutable = 0;
1038 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1039 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1040 : N3V<1, 1, op21_20, op11_8, 1, 0,
1041 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1042 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$dst, $src1, $src2[$lane]","",
1043 [(set (ResTy QPR:$dst),
1044 (ResTy (ShOp (ResTy QPR:$src1),
1045 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1047 let isCommutable = 0;
1050 // Basic 3-register intrinsics, both double- and quad-register.
1051 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1052 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1053 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1054 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1055 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), f, itin,
1056 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1057 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
1058 let isCommutable = Commutable;
1060 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1061 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1062 : N3V<0, 1, op21_20, op11_8, 1, 0,
1063 (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1064 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1065 [(set (Ty DPR:$dst),
1066 (Ty (IntOp (Ty DPR:$src1),
1067 (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
1069 let isCommutable = 0;
1071 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1072 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1073 : N3V<0, 1, op21_20, op11_8, 1, 0,
1074 (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1075 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1076 [(set (Ty DPR:$dst),
1077 (Ty (IntOp (Ty DPR:$src1),
1078 (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
1079 let isCommutable = 0;
1082 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1083 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1084 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1085 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1086 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), f, itin,
1087 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1088 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
1089 let isCommutable = Commutable;
1091 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1092 string OpcodeStr, string Dt,
1093 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1094 : N3V<1, 1, op21_20, op11_8, 1, 0,
1095 (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1096 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1097 [(set (ResTy QPR:$dst),
1098 (ResTy (IntOp (ResTy QPR:$src1),
1099 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1101 let isCommutable = 0;
1103 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1104 string OpcodeStr, string Dt,
1105 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1106 : N3V<1, 1, op21_20, op11_8, 1, 0,
1107 (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1108 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1109 [(set (ResTy QPR:$dst),
1110 (ResTy (IntOp (ResTy QPR:$src1),
1111 (ResTy (NEONvduplane (OpTy DPR_8:$src2),
1113 let isCommutable = 0;
1116 // Multiply-Add/Sub operations: single-, double- and quad-register.
1117 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1118 InstrItinClass itin, string OpcodeStr, string Dt,
1119 ValueType Ty, SDNode MulOp, SDNode OpNode>
1120 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1121 (outs DPR_VFP2:$dst),
1122 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), N3RegFrm, itin,
1123 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", []>;
1125 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1126 InstrItinClass itin, string OpcodeStr, string Dt,
1127 ValueType Ty, SDNode MulOp, SDNode OpNode>
1128 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1129 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1130 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1131 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
1132 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
1133 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1134 string OpcodeStr, string Dt,
1135 ValueType Ty, SDNode MulOp, SDNode ShOp>
1136 : N3V<0, 1, op21_20, op11_8, 1, 0,
1138 (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1140 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1141 [(set (Ty DPR:$dst),
1142 (Ty (ShOp (Ty DPR:$src1),
1143 (Ty (MulOp DPR:$src2,
1144 (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
1146 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1147 string OpcodeStr, string Dt,
1148 ValueType Ty, SDNode MulOp, SDNode ShOp>
1149 : N3V<0, 1, op21_20, op11_8, 1, 0,
1151 (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1153 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1154 [(set (Ty DPR:$dst),
1155 (Ty (ShOp (Ty DPR:$src1),
1156 (Ty (MulOp DPR:$src2,
1157 (Ty (NEONvduplane (Ty DPR_8:$src3),
1160 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1161 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1162 SDNode MulOp, SDNode OpNode>
1163 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1164 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1165 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1166 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
1167 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
1168 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1169 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1170 SDNode MulOp, SDNode ShOp>
1171 : N3V<1, 1, op21_20, op11_8, 1, 0,
1173 (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1175 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1176 [(set (ResTy QPR:$dst),
1177 (ResTy (ShOp (ResTy QPR:$src1),
1178 (ResTy (MulOp QPR:$src2,
1179 (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1181 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1182 string OpcodeStr, string Dt,
1183 ValueType ResTy, ValueType OpTy,
1184 SDNode MulOp, SDNode ShOp>
1185 : N3V<1, 1, op21_20, op11_8, 1, 0,
1187 (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1189 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1190 [(set (ResTy QPR:$dst),
1191 (ResTy (ShOp (ResTy QPR:$src1),
1192 (ResTy (MulOp QPR:$src2,
1193 (ResTy (NEONvduplane (OpTy DPR_8:$src3),
1196 // Neon 3-argument intrinsics, both double- and quad-register.
1197 // The destination register is also used as the first source operand register.
1198 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1199 InstrItinClass itin, string OpcodeStr, string Dt,
1200 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1201 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1202 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1203 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1204 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
1205 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
1206 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1207 InstrItinClass itin, string OpcodeStr, string Dt,
1208 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1209 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1210 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
1211 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1212 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
1213 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
1215 // Neon Long 3-argument intrinsic. The destination register is
1216 // a quad-register and is also used as the first source operand register.
1217 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1218 InstrItinClass itin, string OpcodeStr, string Dt,
1219 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1220 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1221 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
1222 OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
1224 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
1225 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1226 string OpcodeStr, string Dt,
1227 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1228 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1230 (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane),
1232 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1233 [(set (ResTy QPR:$dst),
1234 (ResTy (IntOp (ResTy QPR:$src1),
1236 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
1238 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1239 InstrItinClass itin, string OpcodeStr, string Dt,
1240 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1241 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1243 (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
1245 OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
1246 [(set (ResTy QPR:$dst),
1247 (ResTy (IntOp (ResTy QPR:$src1),
1249 (OpTy (NEONvduplane (OpTy DPR_8:$src3),
1252 // Narrowing 3-register intrinsics.
1253 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1254 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
1255 Intrinsic IntOp, bit Commutable>
1256 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1257 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINi4D,
1258 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1259 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
1260 let isCommutable = Commutable;
1263 // Long 3-register intrinsics.
1264 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1265 InstrItinClass itin, string OpcodeStr, string Dt,
1266 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
1267 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1268 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
1269 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1270 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
1271 let isCommutable = Commutable;
1273 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1274 string OpcodeStr, string Dt,
1275 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1276 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1277 (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
1278 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1279 [(set (ResTy QPR:$dst),
1280 (ResTy (IntOp (OpTy DPR:$src1),
1281 (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
1283 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
1284 InstrItinClass itin, string OpcodeStr, string Dt,
1285 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1286 : N3V<op24, 1, op21_20, op11_8, 1, 0,
1287 (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
1288 NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "",
1289 [(set (ResTy QPR:$dst),
1290 (ResTy (IntOp (OpTy DPR:$src1),
1291 (OpTy (NEONvduplane (OpTy DPR_8:$src2),
1294 // Wide 3-register intrinsics.
1295 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1296 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
1297 Intrinsic IntOp, bit Commutable>
1298 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1299 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
1300 OpcodeStr, Dt, "$dst, $src1, $src2", "",
1301 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
1302 let isCommutable = Commutable;
1305 // Pairwise long 2-register intrinsics, both double- and quad-register.
1306 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1307 bits<2> op17_16, bits<5> op11_7, bit op4,
1308 string OpcodeStr, string Dt,
1309 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1310 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
1311 (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1312 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
1313 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1314 bits<2> op17_16, bits<5> op11_7, bit op4,
1315 string OpcodeStr, string Dt,
1316 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1317 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
1318 (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
1319 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
1321 // Pairwise long 2-register accumulate intrinsics,
1322 // both double- and quad-register.
1323 // The destination register is also used as the first source operand register.
1324 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1325 bits<2> op17_16, bits<5> op11_7, bit op4,
1326 string OpcodeStr, string Dt,
1327 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1328 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
1329 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
1330 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1331 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
1332 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1333 bits<2> op17_16, bits<5> op11_7, bit op4,
1334 string OpcodeStr, string Dt,
1335 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1336 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
1337 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
1338 OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
1339 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
1341 // Shift by immediate,
1342 // both double- and quad-register.
1343 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1344 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1345 ValueType Ty, SDNode OpNode>
1346 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1347 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
1348 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1349 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
1350 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1351 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1352 ValueType Ty, SDNode OpNode>
1353 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1354 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
1355 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1356 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
1358 // Long shift by immediate.
1359 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1360 string OpcodeStr, string Dt,
1361 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1362 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1363 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
1364 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1365 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
1366 (i32 imm:$SIMM))))]>;
1368 // Narrow shift by immediate.
1369 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1370 InstrItinClass itin, string OpcodeStr, string Dt,
1371 ValueType ResTy, ValueType OpTy, SDNode OpNode>
1372 : N2VImm<op24, op23, op11_8, op7, op6, op4,
1373 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
1374 OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1375 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
1376 (i32 imm:$SIMM))))]>;
1378 // Shift right by immediate and accumulate,
1379 // both double- and quad-register.
1380 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1381 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1382 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1383 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1384 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1385 [(set DPR:$dst, (Ty (add DPR:$src1,
1386 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
1387 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1388 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1389 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1390 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
1391 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1392 [(set QPR:$dst, (Ty (add QPR:$src1,
1393 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
1395 // Shift by immediate and insert,
1396 // both double- and quad-register.
1397 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1398 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1399 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
1400 (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
1401 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1402 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
1403 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1404 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
1405 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
1406 (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
1407 OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
1408 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
1410 // Convert, with fractional bits immediate,
1411 // both double- and quad-register.
1412 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1413 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1415 : N2VImm<op24, op23, op11_8, op7, 0, op4,
1416 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
1417 IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1418 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
1419 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
1420 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1422 : N2VImm<op24, op23, op11_8, op7, 1, op4,
1423 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
1424 IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
1425 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
1427 //===----------------------------------------------------------------------===//
1429 //===----------------------------------------------------------------------===//
1431 // Abbreviations used in multiclass suffixes:
1432 // Q = quarter int (8 bit) elements
1433 // H = half int (16 bit) elements
1434 // S = single int (32 bit) elements
1435 // D = double int (64 bit) elements
1437 // Neon 2-register vector operations -- for disassembly only.
1439 // First with only element sizes of 8, 16 and 32 bits:
1440 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1441 bits<5> op11_7, bit op4, string opc, string Dt,
1443 // 64-bit vector types.
1444 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
1445 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1446 opc, !strconcat(Dt, "8"), asm, "", []>;
1447 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
1448 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1449 opc, !strconcat(Dt, "16"), asm, "", []>;
1450 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1451 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1452 opc, !strconcat(Dt, "32"), asm, "", []>;
1453 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
1454 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1455 opc, "f32", asm, "", []> {
1456 let Inst{10} = 1; // overwrite F = 1
1459 // 128-bit vector types.
1460 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
1461 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1462 opc, !strconcat(Dt, "8"), asm, "", []>;
1463 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
1464 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1465 opc, !strconcat(Dt, "16"), asm, "", []>;
1466 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1467 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1468 opc, !strconcat(Dt, "32"), asm, "", []>;
1469 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
1470 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1471 opc, "f32", asm, "", []> {
1472 let Inst{10} = 1; // overwrite F = 1
1476 // Neon 3-register vector operations.
1478 // First with only element sizes of 8, 16 and 32 bits:
1479 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1480 InstrItinClass itinD16, InstrItinClass itinD32,
1481 InstrItinClass itinQ16, InstrItinClass itinQ32,
1482 string OpcodeStr, string Dt,
1483 SDNode OpNode, bit Commutable = 0> {
1484 // 64-bit vector types.
1485 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
1486 OpcodeStr, !strconcat(Dt, "8"),
1487 v8i8, v8i8, OpNode, Commutable>;
1488 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
1489 OpcodeStr, !strconcat(Dt, "16"),
1490 v4i16, v4i16, OpNode, Commutable>;
1491 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
1492 OpcodeStr, !strconcat(Dt, "32"),
1493 v2i32, v2i32, OpNode, Commutable>;
1495 // 128-bit vector types.
1496 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
1497 OpcodeStr, !strconcat(Dt, "8"),
1498 v16i8, v16i8, OpNode, Commutable>;
1499 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
1500 OpcodeStr, !strconcat(Dt, "16"),
1501 v8i16, v8i16, OpNode, Commutable>;
1502 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
1503 OpcodeStr, !strconcat(Dt, "32"),
1504 v4i32, v4i32, OpNode, Commutable>;
1507 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
1508 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1510 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
1512 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
1513 v8i16, v4i16, ShOp>;
1514 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
1515 v4i32, v2i32, ShOp>;
1518 // ....then also with element size 64 bits:
1519 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1520 InstrItinClass itinD, InstrItinClass itinQ,
1521 string OpcodeStr, string Dt,
1522 SDNode OpNode, bit Commutable = 0>
1523 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
1524 OpcodeStr, Dt, OpNode, Commutable> {
1525 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
1526 OpcodeStr, !strconcat(Dt, "64"),
1527 v1i64, v1i64, OpNode, Commutable>;
1528 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
1529 OpcodeStr, !strconcat(Dt, "64"),
1530 v2i64, v2i64, OpNode, Commutable>;
1534 // Neon Narrowing 2-register vector intrinsics,
1535 // source operand element sizes of 16, 32 and 64 bits:
1536 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1537 bits<5> op11_7, bit op6, bit op4,
1538 InstrItinClass itin, string OpcodeStr, string Dt,
1540 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
1541 itin, OpcodeStr, !strconcat(Dt, "16"),
1542 v8i8, v8i16, IntOp>;
1543 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
1544 itin, OpcodeStr, !strconcat(Dt, "32"),
1545 v4i16, v4i32, IntOp>;
1546 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
1547 itin, OpcodeStr, !strconcat(Dt, "64"),
1548 v2i32, v2i64, IntOp>;
1552 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
1553 // source operand element sizes of 16, 32 and 64 bits:
1554 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
1555 string OpcodeStr, string Dt, SDNode OpNode> {
1556 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1557 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
1558 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1559 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
1560 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
1561 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
1565 // Neon 3-register vector intrinsics.
1567 // First with only element sizes of 16 and 32 bits:
1568 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1569 InstrItinClass itinD16, InstrItinClass itinD32,
1570 InstrItinClass itinQ16, InstrItinClass itinQ32,
1571 string OpcodeStr, string Dt,
1572 Intrinsic IntOp, bit Commutable = 0> {
1573 // 64-bit vector types.
1574 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
1575 OpcodeStr, !strconcat(Dt, "16"),
1576 v4i16, v4i16, IntOp, Commutable>;
1577 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
1578 OpcodeStr, !strconcat(Dt, "32"),
1579 v2i32, v2i32, IntOp, Commutable>;
1581 // 128-bit vector types.
1582 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
1583 OpcodeStr, !strconcat(Dt, "16"),
1584 v8i16, v8i16, IntOp, Commutable>;
1585 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
1586 OpcodeStr, !strconcat(Dt, "32"),
1587 v4i32, v4i32, IntOp, Commutable>;
1590 multiclass N3VIntSL_HS<bits<4> op11_8,
1591 InstrItinClass itinD16, InstrItinClass itinD32,
1592 InstrItinClass itinQ16, InstrItinClass itinQ32,
1593 string OpcodeStr, string Dt, Intrinsic IntOp> {
1594 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
1595 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
1596 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
1597 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
1598 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
1599 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
1600 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
1601 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
1604 // ....then also with element size of 8 bits:
1605 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1606 InstrItinClass itinD16, InstrItinClass itinD32,
1607 InstrItinClass itinQ16, InstrItinClass itinQ32,
1608 string OpcodeStr, string Dt,
1609 Intrinsic IntOp, bit Commutable = 0>
1610 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1611 OpcodeStr, Dt, IntOp, Commutable> {
1612 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
1613 OpcodeStr, !strconcat(Dt, "8"),
1614 v8i8, v8i8, IntOp, Commutable>;
1615 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
1616 OpcodeStr, !strconcat(Dt, "8"),
1617 v16i8, v16i8, IntOp, Commutable>;
1620 // ....then also with element size of 64 bits:
1621 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
1622 InstrItinClass itinD16, InstrItinClass itinD32,
1623 InstrItinClass itinQ16, InstrItinClass itinQ32,
1624 string OpcodeStr, string Dt,
1625 Intrinsic IntOp, bit Commutable = 0>
1626 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
1627 OpcodeStr, Dt, IntOp, Commutable> {
1628 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
1629 OpcodeStr, !strconcat(Dt, "64"),
1630 v1i64, v1i64, IntOp, Commutable>;
1631 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
1632 OpcodeStr, !strconcat(Dt, "64"),
1633 v2i64, v2i64, IntOp, Commutable>;
1636 // Neon Narrowing 3-register vector intrinsics,
1637 // source operand element sizes of 16, 32 and 64 bits:
1638 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1639 string OpcodeStr, string Dt,
1640 Intrinsic IntOp, bit Commutable = 0> {
1641 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
1642 OpcodeStr, !strconcat(Dt, "16"),
1643 v8i8, v8i16, IntOp, Commutable>;
1644 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
1645 OpcodeStr, !strconcat(Dt, "32"),
1646 v4i16, v4i32, IntOp, Commutable>;
1647 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
1648 OpcodeStr, !strconcat(Dt, "64"),
1649 v2i32, v2i64, IntOp, Commutable>;
1653 // Neon Long 3-register vector intrinsics.
1655 // First with only element sizes of 16 and 32 bits:
1656 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1657 InstrItinClass itin16, InstrItinClass itin32,
1658 string OpcodeStr, string Dt,
1659 Intrinsic IntOp, bit Commutable = 0> {
1660 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
1661 OpcodeStr, !strconcat(Dt, "16"),
1662 v4i32, v4i16, IntOp, Commutable>;
1663 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
1664 OpcodeStr, !strconcat(Dt, "32"),
1665 v2i64, v2i32, IntOp, Commutable>;
1668 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
1669 InstrItinClass itin, string OpcodeStr, string Dt,
1671 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
1672 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1673 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
1674 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1677 // ....then also with element size of 8 bits:
1678 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1679 InstrItinClass itin16, InstrItinClass itin32,
1680 string OpcodeStr, string Dt,
1681 Intrinsic IntOp, bit Commutable = 0>
1682 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
1683 IntOp, Commutable> {
1684 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
1685 OpcodeStr, !strconcat(Dt, "8"),
1686 v8i16, v8i8, IntOp, Commutable>;
1690 // Neon Wide 3-register vector intrinsics,
1691 // source operand element sizes of 8, 16 and 32 bits:
1692 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1693 string OpcodeStr, string Dt,
1694 Intrinsic IntOp, bit Commutable = 0> {
1695 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
1696 OpcodeStr, !strconcat(Dt, "8"),
1697 v8i16, v8i8, IntOp, Commutable>;
1698 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
1699 OpcodeStr, !strconcat(Dt, "16"),
1700 v4i32, v4i16, IntOp, Commutable>;
1701 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
1702 OpcodeStr, !strconcat(Dt, "32"),
1703 v2i64, v2i32, IntOp, Commutable>;
1707 // Neon Multiply-Op vector operations,
1708 // element sizes of 8, 16 and 32 bits:
1709 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1710 InstrItinClass itinD16, InstrItinClass itinD32,
1711 InstrItinClass itinQ16, InstrItinClass itinQ32,
1712 string OpcodeStr, string Dt, SDNode OpNode> {
1713 // 64-bit vector types.
1714 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
1715 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
1716 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
1717 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
1718 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
1719 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
1721 // 128-bit vector types.
1722 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
1723 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
1724 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
1725 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
1726 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
1727 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
1730 multiclass N3VMulOpSL_HS<bits<4> op11_8,
1731 InstrItinClass itinD16, InstrItinClass itinD32,
1732 InstrItinClass itinQ16, InstrItinClass itinQ32,
1733 string OpcodeStr, string Dt, SDNode ShOp> {
1734 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
1735 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
1736 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
1737 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
1738 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
1739 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
1741 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
1742 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
1746 // Neon 3-argument intrinsics,
1747 // element sizes of 8, 16 and 32 bits:
1748 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1749 InstrItinClass itinD, InstrItinClass itinQ,
1750 string OpcodeStr, string Dt, Intrinsic IntOp> {
1751 // 64-bit vector types.
1752 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
1753 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1754 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
1755 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
1756 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
1757 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
1759 // 128-bit vector types.
1760 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
1761 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
1762 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
1763 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
1764 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
1765 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
1769 // Neon Long 3-argument intrinsics.
1771 // First with only element sizes of 16 and 32 bits:
1772 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
1773 InstrItinClass itin16, InstrItinClass itin32,
1774 string OpcodeStr, string Dt, Intrinsic IntOp> {
1775 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
1776 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
1777 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
1778 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1781 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
1782 string OpcodeStr, string Dt, Intrinsic IntOp> {
1783 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
1784 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
1785 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
1786 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
1789 // ....then also with element size of 8 bits:
1790 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
1791 InstrItinClass itin16, InstrItinClass itin32,
1792 string OpcodeStr, string Dt, Intrinsic IntOp>
1793 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
1794 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
1795 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
1799 // Neon 2-register vector intrinsics,
1800 // element sizes of 8, 16 and 32 bits:
1801 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1802 bits<5> op11_7, bit op4,
1803 InstrItinClass itinD, InstrItinClass itinQ,
1804 string OpcodeStr, string Dt, Intrinsic IntOp> {
1805 // 64-bit vector types.
1806 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1807 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
1808 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1809 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
1810 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1811 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
1813 // 128-bit vector types.
1814 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1815 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
1816 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1817 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
1818 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1819 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
1823 // Neon Pairwise long 2-register intrinsics,
1824 // element sizes of 8, 16 and 32 bits:
1825 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1826 bits<5> op11_7, bit op4,
1827 string OpcodeStr, string Dt, Intrinsic IntOp> {
1828 // 64-bit vector types.
1829 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1830 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1831 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1832 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1833 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1834 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1836 // 128-bit vector types.
1837 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1838 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1839 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1840 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1841 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1842 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1846 // Neon Pairwise long 2-register accumulate intrinsics,
1847 // element sizes of 8, 16 and 32 bits:
1848 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1849 bits<5> op11_7, bit op4,
1850 string OpcodeStr, string Dt, Intrinsic IntOp> {
1851 // 64-bit vector types.
1852 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1853 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
1854 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1855 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
1856 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1857 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
1859 // 128-bit vector types.
1860 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1861 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
1862 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1863 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
1864 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1865 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
1869 // Neon 2-register vector shift by immediate,
1870 // with f of either N2RegVShLFrm or N2RegVShRFrm
1871 // element sizes of 8, 16, 32 and 64 bits:
1872 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1873 InstrItinClass itin, string OpcodeStr, string Dt,
1874 SDNode OpNode, Format f> {
1875 // 64-bit vector types.
1876 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1877 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
1878 let Inst{21-19} = 0b001; // imm6 = 001xxx
1880 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1881 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
1882 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1884 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
1885 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
1886 let Inst{21} = 0b1; // imm6 = 1xxxxx
1888 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
1889 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
1892 // 128-bit vector types.
1893 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1894 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
1895 let Inst{21-19} = 0b001; // imm6 = 001xxx
1897 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1898 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
1899 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1901 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
1902 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
1903 let Inst{21} = 0b1; // imm6 = 1xxxxx
1905 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
1906 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
1910 // Neon Shift-Accumulate vector operations,
1911 // element sizes of 8, 16, 32 and 64 bits:
1912 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1913 string OpcodeStr, string Dt, SDNode ShOp> {
1914 // 64-bit vector types.
1915 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1916 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
1917 let Inst{21-19} = 0b001; // imm6 = 001xxx
1919 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1920 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
1921 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1923 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
1924 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
1925 let Inst{21} = 0b1; // imm6 = 1xxxxx
1927 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
1928 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
1931 // 128-bit vector types.
1932 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1933 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
1934 let Inst{21-19} = 0b001; // imm6 = 001xxx
1936 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1937 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
1938 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1940 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
1941 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
1942 let Inst{21} = 0b1; // imm6 = 1xxxxx
1944 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
1945 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
1950 // Neon Shift-Insert vector operations,
1951 // with f of either N2RegVShLFrm or N2RegVShRFrm
1952 // element sizes of 8, 16, 32 and 64 bits:
1953 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1954 string OpcodeStr, SDNode ShOp,
1956 // 64-bit vector types.
1957 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
1958 f, OpcodeStr, "8", v8i8, ShOp> {
1959 let Inst{21-19} = 0b001; // imm6 = 001xxx
1961 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
1962 f, OpcodeStr, "16", v4i16, ShOp> {
1963 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1965 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
1966 f, OpcodeStr, "32", v2i32, ShOp> {
1967 let Inst{21} = 0b1; // imm6 = 1xxxxx
1969 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
1970 f, OpcodeStr, "64", v1i64, ShOp>;
1973 // 128-bit vector types.
1974 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
1975 f, OpcodeStr, "8", v16i8, ShOp> {
1976 let Inst{21-19} = 0b001; // imm6 = 001xxx
1978 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
1979 f, OpcodeStr, "16", v8i16, ShOp> {
1980 let Inst{21-20} = 0b01; // imm6 = 01xxxx
1982 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
1983 f, OpcodeStr, "32", v4i32, ShOp> {
1984 let Inst{21} = 0b1; // imm6 = 1xxxxx
1986 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
1987 f, OpcodeStr, "64", v2i64, ShOp>;
1991 // Neon Shift Long operations,
1992 // element sizes of 8, 16, 32 bits:
1993 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
1994 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
1995 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
1996 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
1997 let Inst{21-19} = 0b001; // imm6 = 001xxx
1999 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2000 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
2001 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2003 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
2004 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
2005 let Inst{21} = 0b1; // imm6 = 1xxxxx
2009 // Neon Shift Narrow operations,
2010 // element sizes of 16, 32, 64 bits:
2011 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
2012 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
2014 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2015 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
2016 let Inst{21-19} = 0b001; // imm6 = 001xxx
2018 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2019 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
2020 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2022 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
2023 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
2024 let Inst{21} = 0b1; // imm6 = 1xxxxx
2028 //===----------------------------------------------------------------------===//
2029 // Instruction Definitions.
2030 //===----------------------------------------------------------------------===//
2032 // Vector Add Operations.
2034 // VADD : Vector Add (integer and floating-point)
2035 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
2037 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
2038 v2f32, v2f32, fadd, 1>;
2039 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
2040 v4f32, v4f32, fadd, 1>;
2041 // VADDL : Vector Add Long (Q = D + D)
2042 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2043 "vaddl", "s", int_arm_neon_vaddls, 1>;
2044 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
2045 "vaddl", "u", int_arm_neon_vaddlu, 1>;
2046 // VADDW : Vector Add Wide (Q = Q + D)
2047 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
2048 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
2049 // VHADD : Vector Halving Add
2050 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
2051 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2052 "vhadd", "s", int_arm_neon_vhadds, 1>;
2053 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
2054 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2055 "vhadd", "u", int_arm_neon_vhaddu, 1>;
2056 // VRHADD : Vector Rounding Halving Add
2057 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
2058 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2059 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
2060 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
2061 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2062 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
2063 // VQADD : Vector Saturating Add
2064 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
2065 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2066 "vqadd", "s", int_arm_neon_vqadds, 1>;
2067 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
2068 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
2069 "vqadd", "u", int_arm_neon_vqaddu, 1>;
2070 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
2071 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
2072 int_arm_neon_vaddhn, 1>;
2073 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
2074 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
2075 int_arm_neon_vraddhn, 1>;
2077 // Vector Multiply Operations.
2079 // VMUL : Vector Multiply (integer, polynomial and floating-point)
2080 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
2081 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
2082 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
2083 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
2084 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
2085 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
2086 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul", "f32",
2087 v2f32, v2f32, fmul, 1>;
2088 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul", "f32",
2089 v4f32, v4f32, fmul, 1>;
2090 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
2091 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
2092 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
2095 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
2096 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
2097 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
2098 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2099 (DSubReg_i16_reg imm:$lane))),
2100 (SubReg_i16_lane imm:$lane)))>;
2101 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
2102 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
2103 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
2104 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2105 (DSubReg_i32_reg imm:$lane))),
2106 (SubReg_i32_lane imm:$lane)))>;
2107 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
2108 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
2109 (v4f32 (VMULslfq (v4f32 QPR:$src1),
2110 (v2f32 (EXTRACT_SUBREG QPR:$src2,
2111 (DSubReg_i32_reg imm:$lane))),
2112 (SubReg_i32_lane imm:$lane)))>;
2114 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
2115 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
2116 IIC_VMULi16Q, IIC_VMULi32Q,
2117 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
2118 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
2119 IIC_VMULi16Q, IIC_VMULi32Q,
2120 "vqdmulh", "s", int_arm_neon_vqdmulh>;
2121 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
2122 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2124 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
2125 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2126 (DSubReg_i16_reg imm:$lane))),
2127 (SubReg_i16_lane imm:$lane)))>;
2128 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
2129 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2131 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
2132 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2133 (DSubReg_i32_reg imm:$lane))),
2134 (SubReg_i32_lane imm:$lane)))>;
2136 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
2137 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
2138 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
2139 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
2140 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
2141 IIC_VMULi16Q, IIC_VMULi32Q,
2142 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
2143 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
2144 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
2146 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
2147 (v4i16 (EXTRACT_SUBREG QPR:$src2,
2148 (DSubReg_i16_reg imm:$lane))),
2149 (SubReg_i16_lane imm:$lane)))>;
2150 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
2151 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
2153 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
2154 (v2i32 (EXTRACT_SUBREG QPR:$src2,
2155 (DSubReg_i32_reg imm:$lane))),
2156 (SubReg_i32_lane imm:$lane)))>;
2158 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
2159 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2160 "vmull", "s", int_arm_neon_vmulls, 1>;
2161 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
2162 "vmull", "u", int_arm_neon_vmullu, 1>;
2163 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
2164 v8i16, v8i8, int_arm_neon_vmullp, 1>;
2165 defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s",
2166 int_arm_neon_vmulls>;
2167 defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u",
2168 int_arm_neon_vmullu>;
2170 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
2171 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
2172 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
2173 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
2174 "vqdmull", "s", int_arm_neon_vqdmull>;
2176 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
2178 // VMLA : Vector Multiply Accumulate (integer and floating-point)
2179 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2180 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2181 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
2183 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
2185 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
2186 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
2187 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
2189 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
2190 v4f32, v2f32, fmul, fadd>;
2192 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
2193 (mul (v8i16 QPR:$src2),
2194 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2195 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2196 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2197 (DSubReg_i16_reg imm:$lane))),
2198 (SubReg_i16_lane imm:$lane)))>;
2200 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
2201 (mul (v4i32 QPR:$src2),
2202 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2203 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2204 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2205 (DSubReg_i32_reg imm:$lane))),
2206 (SubReg_i32_lane imm:$lane)))>;
2208 def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
2209 (fmul (v4f32 QPR:$src2),
2210 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2211 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
2213 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2214 (DSubReg_i32_reg imm:$lane))),
2215 (SubReg_i32_lane imm:$lane)))>;
2217 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
2218 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2219 "vmlal", "s", int_arm_neon_vmlals>;
2220 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
2221 "vmlal", "u", int_arm_neon_vmlalu>;
2223 defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>;
2224 defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>;
2226 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
2227 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2228 "vqdmlal", "s", int_arm_neon_vqdmlal>;
2229 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
2231 // VMLS : Vector Multiply Subtract (integer and floating-point)
2232 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
2233 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2234 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
2236 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
2238 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
2239 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
2240 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
2242 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
2243 v4f32, v2f32, fmul, fsub>;
2245 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
2246 (mul (v8i16 QPR:$src2),
2247 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
2248 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
2249 (v4i16 (EXTRACT_SUBREG QPR:$src3,
2250 (DSubReg_i16_reg imm:$lane))),
2251 (SubReg_i16_lane imm:$lane)))>;
2253 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
2254 (mul (v4i32 QPR:$src2),
2255 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
2256 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
2257 (v2i32 (EXTRACT_SUBREG QPR:$src3,
2258 (DSubReg_i32_reg imm:$lane))),
2259 (SubReg_i32_lane imm:$lane)))>;
2261 def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
2262 (fmul (v4f32 QPR:$src2),
2263 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
2264 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
2265 (v2f32 (EXTRACT_SUBREG QPR:$src3,
2266 (DSubReg_i32_reg imm:$lane))),
2267 (SubReg_i32_lane imm:$lane)))>;
2269 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
2270 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2271 "vmlsl", "s", int_arm_neon_vmlsls>;
2272 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
2273 "vmlsl", "u", int_arm_neon_vmlslu>;
2275 defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>;
2276 defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>;
2278 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
2279 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
2280 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2281 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
2283 // Vector Subtract Operations.
2285 // VSUB : Vector Subtract (integer and floating-point)
2286 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
2287 "vsub", "i", sub, 0>;
2288 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
2289 v2f32, v2f32, fsub, 0>;
2290 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
2291 v4f32, v4f32, fsub, 0>;
2292 // VSUBL : Vector Subtract Long (Q = D - D)
2293 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2294 "vsubl", "s", int_arm_neon_vsubls, 1>;
2295 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
2296 "vsubl", "u", int_arm_neon_vsublu, 1>;
2297 // VSUBW : Vector Subtract Wide (Q = Q - D)
2298 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
2299 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
2300 // VHSUB : Vector Halving Subtract
2301 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
2302 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2303 "vhsub", "s", int_arm_neon_vhsubs, 0>;
2304 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
2305 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2306 "vhsub", "u", int_arm_neon_vhsubu, 0>;
2307 // VQSUB : Vector Saturing Subtract
2308 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
2309 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2310 "vqsub", "s", int_arm_neon_vqsubs, 0>;
2311 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
2312 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2313 "vqsub", "u", int_arm_neon_vqsubu, 0>;
2314 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
2315 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
2316 int_arm_neon_vsubhn, 0>;
2317 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
2318 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
2319 int_arm_neon_vrsubhn, 0>;
2321 // Vector Comparisons.
2323 // VCEQ : Vector Compare Equal
2324 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2325 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
2326 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
2328 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
2330 // For disassembly only.
2331 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
2334 // VCGE : Vector Compare Greater Than or Equal
2335 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2336 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
2337 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2338 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
2339 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
2341 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
2343 // For disassembly only.
2344 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
2346 // For disassembly only.
2347 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
2350 // VCGT : Vector Compare Greater Than
2351 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2352 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
2353 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
2354 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
2355 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
2357 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
2359 // For disassembly only.
2360 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
2362 // For disassembly only.
2363 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
2366 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
2367 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
2368 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
2369 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
2370 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
2371 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
2372 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
2373 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
2374 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
2375 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
2376 // VTST : Vector Test Bits
2377 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
2378 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
2380 // Vector Bitwise Operations.
2382 def vnotd : PatFrag<(ops node:$in),
2383 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
2384 def vnotq : PatFrag<(ops node:$in),
2385 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
2388 // VAND : Vector Bitwise AND
2389 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
2390 v2i32, v2i32, and, 1>;
2391 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
2392 v4i32, v4i32, and, 1>;
2394 // VEOR : Vector Bitwise Exclusive OR
2395 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
2396 v2i32, v2i32, xor, 1>;
2397 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
2398 v4i32, v4i32, xor, 1>;
2400 // VORR : Vector Bitwise OR
2401 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
2402 v2i32, v2i32, or, 1>;
2403 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
2404 v4i32, v4i32, or, 1>;
2406 // VBIC : Vector Bitwise Bit Clear (AND NOT)
2407 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2408 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2409 "vbic", "$dst, $src1, $src2", "",
2410 [(set DPR:$dst, (v2i32 (and DPR:$src1,
2411 (vnotd DPR:$src2))))]>;
2412 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2413 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2414 "vbic", "$dst, $src1, $src2", "",
2415 [(set QPR:$dst, (v4i32 (and QPR:$src1,
2416 (vnotq QPR:$src2))))]>;
2418 // VORN : Vector Bitwise OR NOT
2419 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
2420 (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
2421 "vorn", "$dst, $src1, $src2", "",
2422 [(set DPR:$dst, (v2i32 (or DPR:$src1,
2423 (vnotd DPR:$src2))))]>;
2424 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
2425 (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ,
2426 "vorn", "$dst, $src1, $src2", "",
2427 [(set QPR:$dst, (v4i32 (or QPR:$src1,
2428 (vnotq QPR:$src2))))]>;
2430 // VMVN : Vector Bitwise NOT (Immediate)
2432 let isReMaterializable = 1 in {
2433 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
2434 (ins nModImm:$SIMM), IIC_VMOVImm,
2435 "vmvn", "i16", "$dst, $SIMM", "",
2436 [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
2437 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
2438 (ins nModImm:$SIMM), IIC_VMOVImm,
2439 "vmvn", "i16", "$dst, $SIMM", "",
2440 [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
2442 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
2443 (ins nModImm:$SIMM), IIC_VMOVImm,
2444 "vmvn", "i32", "$dst, $SIMM", "",
2445 [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
2446 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
2447 (ins nModImm:$SIMM), IIC_VMOVImm,
2448 "vmvn", "i32", "$dst, $SIMM", "",
2449 [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
2452 // VMVN : Vector Bitwise NOT
2453 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
2454 (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
2455 "vmvn", "$dst, $src", "",
2456 [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>;
2457 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
2458 (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD,
2459 "vmvn", "$dst, $src", "",
2460 [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>;
2461 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
2462 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
2464 // VBSL : Vector Bitwise Select
2465 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
2466 (ins DPR:$src1, DPR:$src2, DPR:$src3),
2467 N3RegFrm, IIC_VCNTiD,
2468 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2470 (v2i32 (or (and DPR:$src2, DPR:$src1),
2471 (and DPR:$src3, (vnotd DPR:$src1)))))]>;
2472 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
2473 (ins QPR:$src1, QPR:$src2, QPR:$src3),
2474 N3RegFrm, IIC_VCNTiQ,
2475 "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
2477 (v4i32 (or (and QPR:$src2, QPR:$src1),
2478 (and QPR:$src3, (vnotq QPR:$src1)))))]>;
2480 // VBIF : Vector Bitwise Insert if False
2481 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
2482 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
2483 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2484 N3RegFrm, IIC_VBINiD,
2485 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2486 [/* For disassembly only; pattern left blank */]>;
2487 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
2488 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2489 N3RegFrm, IIC_VBINiQ,
2490 "vbif", "$dst, $src2, $src3", "$src1 = $dst",
2491 [/* For disassembly only; pattern left blank */]>;
2493 // VBIT : Vector Bitwise Insert if True
2494 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
2495 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
2496 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
2497 N3RegFrm, IIC_VBINiD,
2498 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2499 [/* For disassembly only; pattern left blank */]>;
2500 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
2501 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
2502 N3RegFrm, IIC_VBINiQ,
2503 "vbit", "$dst, $src2, $src3", "$src1 = $dst",
2504 [/* For disassembly only; pattern left blank */]>;
2506 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
2507 // for equivalent operations with different register constraints; it just
2510 // Vector Absolute Differences.
2512 // VABD : Vector Absolute Difference
2513 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
2514 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2515 "vabd", "s", int_arm_neon_vabds, 0>;
2516 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
2517 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2518 "vabd", "u", int_arm_neon_vabdu, 0>;
2519 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
2520 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
2521 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
2522 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
2524 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
2525 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2526 "vabdl", "s", int_arm_neon_vabdls, 0>;
2527 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
2528 "vabdl", "u", int_arm_neon_vabdlu, 0>;
2530 // VABA : Vector Absolute Difference and Accumulate
2531 defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2532 "vaba", "s", int_arm_neon_vabas>;
2533 defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
2534 "vaba", "u", int_arm_neon_vabau>;
2536 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
2537 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2538 "vabal", "s", int_arm_neon_vabals>;
2539 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD,
2540 "vabal", "u", int_arm_neon_vabalu>;
2542 // Vector Maximum and Minimum.
2544 // VMAX : Vector Maximum
2545 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
2546 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2547 "vmax", "s", int_arm_neon_vmaxs, 1>;
2548 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
2549 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2550 "vmax", "u", int_arm_neon_vmaxu, 1>;
2551 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
2553 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
2554 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2556 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
2558 // VMIN : Vector Minimum
2559 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
2560 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2561 "vmin", "s", int_arm_neon_vmins, 1>;
2562 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
2563 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
2564 "vmin", "u", int_arm_neon_vminu, 1>;
2565 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
2567 v2f32, v2f32, int_arm_neon_vmins, 1>;
2568 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
2570 v4f32, v4f32, int_arm_neon_vmins, 1>;
2572 // Vector Pairwise Operations.
2574 // VPADD : Vector Pairwise Add
2575 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2577 v8i8, v8i8, int_arm_neon_vpadd, 0>;
2578 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2580 v4i16, v4i16, int_arm_neon_vpadd, 0>;
2581 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
2583 v2i32, v2i32, int_arm_neon_vpadd, 0>;
2584 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
2585 IIC_VBIND, "vpadd", "f32",
2586 v2f32, v2f32, int_arm_neon_vpadd, 0>;
2588 // VPADDL : Vector Pairwise Add Long
2589 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
2590 int_arm_neon_vpaddls>;
2591 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
2592 int_arm_neon_vpaddlu>;
2594 // VPADAL : Vector Pairwise Add and Accumulate Long
2595 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
2596 int_arm_neon_vpadals>;
2597 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
2598 int_arm_neon_vpadalu>;
2600 // VPMAX : Vector Pairwise Maximum
2601 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2602 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
2603 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2604 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
2605 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2606 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
2607 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2608 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
2609 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2610 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
2611 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2612 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
2613 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
2614 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
2616 // VPMIN : Vector Pairwise Minimum
2617 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2618 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
2619 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2620 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
2621 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2622 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
2623 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2624 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
2625 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2626 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
2627 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
2628 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
2629 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VSUBi4D, "vpmin",
2630 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
2632 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
2634 // VRECPE : Vector Reciprocal Estimate
2635 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2636 IIC_VUNAD, "vrecpe", "u32",
2637 v2i32, v2i32, int_arm_neon_vrecpe>;
2638 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
2639 IIC_VUNAQ, "vrecpe", "u32",
2640 v4i32, v4i32, int_arm_neon_vrecpe>;
2641 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2642 IIC_VUNAD, "vrecpe", "f32",
2643 v2f32, v2f32, int_arm_neon_vrecpe>;
2644 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
2645 IIC_VUNAQ, "vrecpe", "f32",
2646 v4f32, v4f32, int_arm_neon_vrecpe>;
2648 // VRECPS : Vector Reciprocal Step
2649 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2650 IIC_VRECSD, "vrecps", "f32",
2651 v2f32, v2f32, int_arm_neon_vrecps, 1>;
2652 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
2653 IIC_VRECSQ, "vrecps", "f32",
2654 v4f32, v4f32, int_arm_neon_vrecps, 1>;
2656 // VRSQRTE : Vector Reciprocal Square Root Estimate
2657 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2658 IIC_VUNAD, "vrsqrte", "u32",
2659 v2i32, v2i32, int_arm_neon_vrsqrte>;
2660 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
2661 IIC_VUNAQ, "vrsqrte", "u32",
2662 v4i32, v4i32, int_arm_neon_vrsqrte>;
2663 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2664 IIC_VUNAD, "vrsqrte", "f32",
2665 v2f32, v2f32, int_arm_neon_vrsqrte>;
2666 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
2667 IIC_VUNAQ, "vrsqrte", "f32",
2668 v4f32, v4f32, int_arm_neon_vrsqrte>;
2670 // VRSQRTS : Vector Reciprocal Square Root Step
2671 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2672 IIC_VRECSD, "vrsqrts", "f32",
2673 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
2674 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
2675 IIC_VRECSQ, "vrsqrts", "f32",
2676 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
2680 // VSHL : Vector Shift
2681 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
2682 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2683 "vshl", "s", int_arm_neon_vshifts, 0>;
2684 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
2685 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
2686 "vshl", "u", int_arm_neon_vshiftu, 0>;
2687 // VSHL : Vector Shift Left (Immediate)
2688 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
2690 // VSHR : Vector Shift Right (Immediate)
2691 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
2693 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
2696 // VSHLL : Vector Shift Left Long
2697 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
2698 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
2700 // VSHLL : Vector Shift Left Long (with maximum shift count)
2701 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
2702 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
2703 ValueType OpTy, SDNode OpNode>
2704 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
2705 ResTy, OpTy, OpNode> {
2706 let Inst{21-16} = op21_16;
2708 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
2709 v8i16, v8i8, NEONvshlli>;
2710 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
2711 v4i32, v4i16, NEONvshlli>;
2712 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
2713 v2i64, v2i32, NEONvshlli>;
2715 // VSHRN : Vector Shift Right and Narrow
2716 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
2719 // VRSHL : Vector Rounding Shift
2720 defm VRSHLs : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
2721 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2722 "vrshl", "s", int_arm_neon_vrshifts, 0>;
2723 defm VRSHLu : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
2724 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2725 "vrshl", "u", int_arm_neon_vrshiftu, 0>;
2726 // VRSHR : Vector Rounding Shift Right
2727 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
2729 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
2732 // VRSHRN : Vector Rounding Shift Right and Narrow
2733 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
2736 // VQSHL : Vector Saturating Shift
2737 defm VQSHLs : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
2738 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2739 "vqshl", "s", int_arm_neon_vqshifts, 0>;
2740 defm VQSHLu : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
2741 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2742 "vqshl", "u", int_arm_neon_vqshiftu, 0>;
2743 // VQSHL : Vector Saturating Shift Left (Immediate)
2744 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
2746 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
2748 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
2749 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
2752 // VQSHRN : Vector Saturating Shift Right and Narrow
2753 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
2755 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
2758 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
2759 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
2762 // VQRSHL : Vector Saturating Rounding Shift
2763 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
2764 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2765 "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
2766 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
2767 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
2768 "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
2770 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
2771 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
2773 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
2776 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
2777 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
2780 // VSRA : Vector Shift Right and Accumulate
2781 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
2782 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
2783 // VRSRA : Vector Rounding Shift Right and Accumulate
2784 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
2785 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
2787 // VSLI : Vector Shift Left and Insert
2788 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
2789 // VSRI : Vector Shift Right and Insert
2790 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
2792 // Vector Absolute and Saturating Absolute.
2794 // VABS : Vector Absolute Value
2795 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
2796 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
2798 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2799 IIC_VUNAD, "vabs", "f32",
2800 v2f32, v2f32, int_arm_neon_vabs>;
2801 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
2802 IIC_VUNAQ, "vabs", "f32",
2803 v4f32, v4f32, int_arm_neon_vabs>;
2805 // VQABS : Vector Saturating Absolute Value
2806 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
2807 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
2808 int_arm_neon_vqabs>;
2812 def vnegd : PatFrag<(ops node:$in),
2813 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
2814 def vnegq : PatFrag<(ops node:$in),
2815 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
2817 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2818 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
2819 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2820 [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>;
2821 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
2822 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
2823 IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "",
2824 [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>;
2826 // VNEG : Vector Negate (integer)
2827 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
2828 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
2829 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
2830 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
2831 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
2832 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
2834 // VNEG : Vector Negate (floating-point)
2835 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2836 (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
2837 "vneg", "f32", "$dst, $src", "",
2838 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
2839 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
2840 (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
2841 "vneg", "f32", "$dst, $src", "",
2842 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
2844 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
2845 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
2846 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
2847 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
2848 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
2849 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
2851 // VQNEG : Vector Saturating Negate
2852 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
2853 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
2854 int_arm_neon_vqneg>;
2856 // Vector Bit Counting Operations.
2858 // VCLS : Vector Count Leading Sign Bits
2859 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
2860 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
2862 // VCLZ : Vector Count Leading Zeros
2863 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
2864 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
2866 // VCNT : Vector Count One Bits
2867 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2868 IIC_VCNTiD, "vcnt", "8",
2869 v8i8, v8i8, int_arm_neon_vcnt>;
2870 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
2871 IIC_VCNTiQ, "vcnt", "8",
2872 v16i8, v16i8, int_arm_neon_vcnt>;
2874 // Vector Swap -- for disassembly only.
2875 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
2876 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
2877 "vswp", "$dst, $src", "", []>;
2878 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
2879 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
2880 "vswp", "$dst, $src", "", []>;
2882 // Vector Move Operations.
2884 // VMOV : Vector Move (Register)
2886 let neverHasSideEffects = 1 in {
2887 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
2888 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2889 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
2890 N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
2892 // Pseudo vector move instructions for QQ and QQQQ registers. This should
2893 // be expanded after register allocation is completed.
2894 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
2895 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2897 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
2898 NoItinerary, "${:comment} vmov\t$dst, $src", []>;
2899 } // neverHasSideEffects
2901 // VMOV : Vector Move (Immediate)
2903 let isReMaterializable = 1 in {
2904 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
2905 (ins nModImm:$SIMM), IIC_VMOVImm,
2906 "vmov", "i8", "$dst, $SIMM", "",
2907 [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
2908 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
2909 (ins nModImm:$SIMM), IIC_VMOVImm,
2910 "vmov", "i8", "$dst, $SIMM", "",
2911 [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
2913 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
2914 (ins nModImm:$SIMM), IIC_VMOVImm,
2915 "vmov", "i16", "$dst, $SIMM", "",
2916 [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
2917 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
2918 (ins nModImm:$SIMM), IIC_VMOVImm,
2919 "vmov", "i16", "$dst, $SIMM", "",
2920 [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
2922 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
2923 (ins nModImm:$SIMM), IIC_VMOVImm,
2924 "vmov", "i32", "$dst, $SIMM", "",
2925 [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
2926 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
2927 (ins nModImm:$SIMM), IIC_VMOVImm,
2928 "vmov", "i32", "$dst, $SIMM", "",
2929 [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
2931 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
2932 (ins nModImm:$SIMM), IIC_VMOVImm,
2933 "vmov", "i64", "$dst, $SIMM", "",
2934 [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
2935 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
2936 (ins nModImm:$SIMM), IIC_VMOVImm,
2937 "vmov", "i64", "$dst, $SIMM", "",
2938 [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
2939 } // isReMaterializable
2941 // VMOV : Vector Get Lane (move scalar to ARM core register)
2943 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
2944 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2945 IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
2946 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
2948 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
2949 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2950 IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
2951 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
2953 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
2954 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2955 IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
2956 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
2958 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
2959 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2960 IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
2961 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
2963 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
2964 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
2965 IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
2966 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
2968 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
2969 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
2970 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2971 (DSubReg_i8_reg imm:$lane))),
2972 (SubReg_i8_lane imm:$lane))>;
2973 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
2974 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2975 (DSubReg_i16_reg imm:$lane))),
2976 (SubReg_i16_lane imm:$lane))>;
2977 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
2978 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
2979 (DSubReg_i8_reg imm:$lane))),
2980 (SubReg_i8_lane imm:$lane))>;
2981 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
2982 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
2983 (DSubReg_i16_reg imm:$lane))),
2984 (SubReg_i16_lane imm:$lane))>;
2985 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
2986 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
2987 (DSubReg_i32_reg imm:$lane))),
2988 (SubReg_i32_lane imm:$lane))>;
2989 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
2990 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
2991 (SSubReg_f32_reg imm:$src2))>;
2992 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
2993 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
2994 (SSubReg_f32_reg imm:$src2))>;
2995 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
2996 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
2997 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
2998 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
3001 // VMOV : Vector Set Lane (move ARM core register to scalar)
3003 let Constraints = "$src1 = $dst" in {
3004 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
3005 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3006 IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
3007 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
3008 GPR:$src2, imm:$lane))]>;
3009 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
3010 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3011 IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
3012 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
3013 GPR:$src2, imm:$lane))]>;
3014 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
3015 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
3016 IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
3017 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
3018 GPR:$src2, imm:$lane))]>;
3020 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
3021 (v16i8 (INSERT_SUBREG QPR:$src1,
3022 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
3023 (DSubReg_i8_reg imm:$lane))),
3024 GPR:$src2, (SubReg_i8_lane imm:$lane))),
3025 (DSubReg_i8_reg imm:$lane)))>;
3026 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
3027 (v8i16 (INSERT_SUBREG QPR:$src1,
3028 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
3029 (DSubReg_i16_reg imm:$lane))),
3030 GPR:$src2, (SubReg_i16_lane imm:$lane))),
3031 (DSubReg_i16_reg imm:$lane)))>;
3032 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
3033 (v4i32 (INSERT_SUBREG QPR:$src1,
3034 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
3035 (DSubReg_i32_reg imm:$lane))),
3036 GPR:$src2, (SubReg_i32_lane imm:$lane))),
3037 (DSubReg_i32_reg imm:$lane)))>;
3039 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
3040 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
3041 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3042 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
3043 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
3044 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
3046 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3047 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3048 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
3049 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
3051 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
3052 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3053 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
3054 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
3055 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
3056 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
3058 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
3059 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3060 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
3061 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3062 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
3063 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
3065 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
3066 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3067 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3069 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
3070 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3071 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3073 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
3074 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3075 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
3078 // VDUP : Vector Duplicate (from ARM core register to all elements)
3080 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3081 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
3082 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3083 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3084 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
3085 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
3086 IIC_VMOVIS, "vdup", Dt, "$dst, $src",
3087 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
3089 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
3090 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
3091 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
3092 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
3093 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
3094 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
3096 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
3097 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3098 [(set DPR:$dst, (v2f32 (NEONvdup
3099 (f32 (bitconvert GPR:$src)))))]>;
3100 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
3101 IIC_VMOVIS, "vdup", "32", "$dst, $src",
3102 [(set QPR:$dst, (v4f32 (NEONvdup
3103 (f32 (bitconvert GPR:$src)))))]>;
3105 // VDUP : Vector Duplicate Lane (from scalar to all elements)
3107 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
3109 : NVDupLane<op19_16, 0, (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3110 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3111 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
3113 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
3114 ValueType ResTy, ValueType OpTy>
3115 : NVDupLane<op19_16, 1, (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane),
3116 IIC_VMOVD, OpcodeStr, Dt, "$dst, $src[$lane]",
3117 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src),
3120 // Inst{19-16} is partially specified depending on the element size.
3122 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
3123 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
3124 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
3125 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
3126 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
3127 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
3128 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
3129 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
3131 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
3132 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
3133 (DSubReg_i8_reg imm:$lane))),
3134 (SubReg_i8_lane imm:$lane)))>;
3135 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
3136 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
3137 (DSubReg_i16_reg imm:$lane))),
3138 (SubReg_i16_lane imm:$lane)))>;
3139 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
3140 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
3141 (DSubReg_i32_reg imm:$lane))),
3142 (SubReg_i32_lane imm:$lane)))>;
3143 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
3144 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
3145 (DSubReg_i32_reg imm:$lane))),
3146 (SubReg_i32_lane imm:$lane)))>;
3148 def VDUPfdf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 0, 0,
3149 (outs DPR:$dst), (ins SPR:$src),
3150 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3151 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
3153 def VDUPfqf : N2V<0b11, 0b11, {?,1}, {0,0}, 0b11000, 1, 0,
3154 (outs QPR:$dst), (ins SPR:$src),
3155 IIC_VMOVD, "vdup", "32", "$dst, ${src:lane}", "",
3156 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
3158 // VMOVN : Vector Narrowing Move
3159 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD,
3160 "vmovn", "i", int_arm_neon_vmovn>;
3161 // VQMOVN : Vector Saturating Narrowing Move
3162 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
3163 "vqmovn", "s", int_arm_neon_vqmovns>;
3164 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
3165 "vqmovn", "u", int_arm_neon_vqmovnu>;
3166 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
3167 "vqmovun", "s", int_arm_neon_vqmovnsu>;
3168 // VMOVL : Vector Lengthening Move
3169 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
3170 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
3172 // Vector Conversions.
3174 // VCVT : Vector Convert Between Floating-Point and Integers
3175 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3176 v2i32, v2f32, fp_to_sint>;
3177 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3178 v2i32, v2f32, fp_to_uint>;
3179 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3180 v2f32, v2i32, sint_to_fp>;
3181 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3182 v2f32, v2i32, uint_to_fp>;
3184 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3185 v4i32, v4f32, fp_to_sint>;
3186 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3187 v4i32, v4f32, fp_to_uint>;
3188 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3189 v4f32, v4i32, sint_to_fp>;
3190 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3191 v4f32, v4i32, uint_to_fp>;
3193 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
3194 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3195 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
3196 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3197 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
3198 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3199 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
3200 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3201 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
3203 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
3204 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
3205 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
3206 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
3207 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
3208 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
3209 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
3210 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
3214 // VREV64 : Vector Reverse elements within 64-bit doublewords
3216 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3217 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
3218 (ins DPR:$src), IIC_VMOVD,
3219 OpcodeStr, Dt, "$dst, $src", "",
3220 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
3221 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3222 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
3223 (ins QPR:$src), IIC_VMOVD,
3224 OpcodeStr, Dt, "$dst, $src", "",
3225 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
3227 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
3228 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
3229 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
3230 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
3232 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
3233 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
3234 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
3235 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
3237 // VREV32 : Vector Reverse elements within 32-bit words
3239 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3240 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
3241 (ins DPR:$src), IIC_VMOVD,
3242 OpcodeStr, Dt, "$dst, $src", "",
3243 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
3244 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3245 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
3246 (ins QPR:$src), IIC_VMOVD,
3247 OpcodeStr, Dt, "$dst, $src", "",
3248 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
3250 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
3251 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
3253 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
3254 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
3256 // VREV16 : Vector Reverse elements within 16-bit halfwords
3258 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3259 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
3260 (ins DPR:$src), IIC_VMOVD,
3261 OpcodeStr, Dt, "$dst, $src", "",
3262 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
3263 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
3264 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
3265 (ins QPR:$src), IIC_VMOVD,
3266 OpcodeStr, Dt, "$dst, $src", "",
3267 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
3269 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
3270 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
3272 // Other Vector Shuffles.
3274 // VEXT : Vector Extract
3276 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
3277 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
3278 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
3279 IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3280 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
3281 (Ty DPR:$rhs), imm:$index)))]>;
3283 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
3284 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
3285 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
3286 IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
3287 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
3288 (Ty QPR:$rhs), imm:$index)))]>;
3290 def VEXTd8 : VEXTd<"vext", "8", v8i8>;
3291 def VEXTd16 : VEXTd<"vext", "16", v4i16>;
3292 def VEXTd32 : VEXTd<"vext", "32", v2i32>;
3293 def VEXTdf : VEXTd<"vext", "32", v2f32>;
3295 def VEXTq8 : VEXTq<"vext", "8", v16i8>;
3296 def VEXTq16 : VEXTq<"vext", "16", v8i16>;
3297 def VEXTq32 : VEXTq<"vext", "32", v4i32>;
3298 def VEXTqf : VEXTq<"vext", "32", v4f32>;
3300 // VTRN : Vector Transpose
3302 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
3303 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
3304 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
3306 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
3307 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
3308 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
3310 // VUZP : Vector Unzip (Deinterleave)
3312 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
3313 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
3314 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
3316 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
3317 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
3318 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
3320 // VZIP : Vector Zip (Interleave)
3322 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
3323 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
3324 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
3326 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
3327 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
3328 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
3330 // Vector Table Lookup and Table Extension.
3332 // VTBL : Vector Table Lookup
3334 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
3335 (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
3336 "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
3337 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
3338 let hasExtraSrcRegAllocReq = 1 in {
3340 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
3341 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
3342 "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
3344 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
3345 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
3346 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
3348 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
3349 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
3351 "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
3352 } // hasExtraSrcRegAllocReq = 1
3354 // VTBX : Vector Table Extension
3356 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
3357 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
3358 "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
3359 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
3360 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
3361 let hasExtraSrcRegAllocReq = 1 in {
3363 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
3364 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
3365 "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
3367 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
3368 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
3369 NVTBLFrm, IIC_VTBX3,
3370 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
3371 "$orig = $dst", []>;
3373 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
3374 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
3375 "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
3376 "$orig = $dst", []>;
3377 } // hasExtraSrcRegAllocReq = 1
3379 //===----------------------------------------------------------------------===//
3380 // NEON instructions for single-precision FP math
3381 //===----------------------------------------------------------------------===//
3383 class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
3384 : NEONFPPat<(ResTy (OpNode SPR:$a)),
3385 (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
3389 class N3VSPat<SDNode OpNode, NeonI Inst>
3390 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
3391 (EXTRACT_SUBREG (v2f32
3392 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3394 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3398 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
3399 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
3400 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3402 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3404 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
3408 // These need separate instructions because they must use DPR_VFP2 register
3409 // class which have SPR sub-registers.
3411 // Vector Add Operations used for single-precision FP
3412 let neverHasSideEffects = 1 in
3413 def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
3414 def : N3VSPat<fadd, VADDfd_sfp>;
3416 // Vector Sub Operations used for single-precision FP
3417 let neverHasSideEffects = 1 in
3418 def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
3419 def : N3VSPat<fsub, VSUBfd_sfp>;
3421 // Vector Multiply Operations used for single-precision FP
3422 let neverHasSideEffects = 1 in
3423 def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
3424 def : N3VSPat<fmul, VMULfd_sfp>;
3426 // Vector Multiply-Accumulate/Subtract used for single-precision FP
3427 // vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
3428 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
3430 //let neverHasSideEffects = 1 in
3431 //def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
3432 // v2f32, fmul, fadd>;
3433 //def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>;
3435 //let neverHasSideEffects = 1 in
3436 //def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
3437 // v2f32, fmul, fsub>;
3438 //def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>;
3440 // Vector Absolute used for single-precision FP
3441 let neverHasSideEffects = 1 in
3442 def VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
3443 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3444 "vabs", "f32", "$dst, $src", "", []>;
3445 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
3447 // Vector Negate used for single-precision FP
3448 let neverHasSideEffects = 1 in
3449 def VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
3450 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
3451 "vneg", "f32", "$dst, $src", "", []>;
3452 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
3454 // Vector Maximum used for single-precision FP
3455 let neverHasSideEffects = 1 in
3456 def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3457 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3458 "vmax", "f32", "$dst, $src1, $src2", "", []>;
3459 def : N3VSPat<NEONfmax, VMAXfd_sfp>;
3461 // Vector Minimum used for single-precision FP
3462 let neverHasSideEffects = 1 in
3463 def VMINfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$dst),
3464 (ins DPR_VFP2:$src1, DPR_VFP2:$src2), N3RegFrm, IIC_VBIND,
3465 "vmin", "f32", "$dst, $src1, $src2", "", []>;
3466 def : N3VSPat<NEONfmin, VMINfd_sfp>;
3468 // Vector Convert between single-precision FP and integer
3469 let neverHasSideEffects = 1 in
3470 def VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
3471 v2i32, v2f32, fp_to_sint>;
3472 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
3474 let neverHasSideEffects = 1 in
3475 def VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
3476 v2i32, v2f32, fp_to_uint>;
3477 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
3479 let neverHasSideEffects = 1 in
3480 def VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
3481 v2f32, v2i32, sint_to_fp>;
3482 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
3484 let neverHasSideEffects = 1 in
3485 def VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
3486 v2f32, v2i32, uint_to_fp>;
3487 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
3489 //===----------------------------------------------------------------------===//
3490 // Non-Instruction Patterns
3491 //===----------------------------------------------------------------------===//
3494 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
3495 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
3496 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
3497 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
3498 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
3499 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
3500 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
3501 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
3502 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
3503 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
3504 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
3505 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
3506 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
3507 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
3508 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
3509 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
3510 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
3511 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
3512 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
3513 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
3514 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
3515 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
3516 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
3517 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
3518 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
3519 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
3520 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
3521 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
3522 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
3523 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
3525 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
3526 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
3527 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
3528 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
3529 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
3530 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
3531 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
3532 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
3533 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
3534 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
3535 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
3536 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
3537 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
3538 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
3539 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
3540 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
3541 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
3542 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
3543 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
3544 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
3545 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
3546 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
3547 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
3548 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
3549 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
3550 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
3551 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
3552 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
3553 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
3554 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;