1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def memri : Operand<iPTR> {
17 let PrintMethod = "printMemRegImm";
18 let NumMIOperands = 2;
19 let MIOperandInfo = (ops i32imm, ptr_rc);
22 // Define ARM specific addressing mode.
23 //register plus/minus 12 bit offset
24 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
25 //register plus scaled register
26 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
33 let Namespace = "ARM";
35 dag OperandList = ops;
36 let AsmString = asmstr;
37 let Pattern = pattern;
40 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
41 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
42 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
44 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
45 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
46 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
47 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
48 [SDNPHasChain, SDNPOptInFlag]>;
50 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
51 "!ADJCALLSTACKUP $amt",
52 [(callseq_end imm:$amt)]>;
54 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
55 "!ADJCALLSTACKDOWN $amt",
56 [(callseq_start imm:$amt)]>;
59 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
62 let Defs = [R0, R1, R2, R3] in {
63 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
66 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
68 [(set IntRegs:$dst, (load iaddr:$addr))]>;
70 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
72 [(store IntRegs:$src, IntRegs:$addr)]>;
74 def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
75 "mov $dst, $src", []>;
77 def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
78 "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
80 def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
82 [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
84 def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
86 [(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;