1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
88 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
89 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
90 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
92 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
93 [SDNPHasChain, SDNPOutGlue]>;
94 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
99 SDNPMayStore, SDNPMayLoad]>;
101 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
107 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
108 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
112 [SDNPHasChain, SDNPOptInGlue]>;
114 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
117 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
118 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
120 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
122 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
125 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
128 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
131 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
132 [SDNPOutGlue, SDNPCommutative]>;
134 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
136 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
137 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
138 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
140 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
142 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
143 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
144 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
146 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
147 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
148 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
149 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
150 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
152 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
154 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
156 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
157 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
159 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
161 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
162 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
165 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
167 //===----------------------------------------------------------------------===//
168 // ARM Instruction Predicate Definitions.
170 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
171 AssemblerPredicate<"HasV4TOps", "armv4t">;
172 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
173 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
174 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
175 AssemblerPredicate<"HasV5TEOps", "armv5te">;
176 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
177 AssemblerPredicate<"HasV6Ops", "armv6">;
178 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
179 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
180 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
181 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
182 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
183 AssemblerPredicate<"HasV7Ops", "armv7">;
184 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
185 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
186 AssemblerPredicate<"FeatureVFP2", "VFP2">;
187 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
188 AssemblerPredicate<"FeatureVFP3", "VFP3">;
189 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
190 AssemblerPredicate<"FeatureVFP4", "VFP4">;
191 def HasNEON : Predicate<"Subtarget->hasNEON()">,
192 AssemblerPredicate<"FeatureNEON", "NEON">;
193 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
194 AssemblerPredicate<"FeatureFP16","half-float">;
195 def HasDivide : Predicate<"Subtarget->hasDivide()">,
196 AssemblerPredicate<"FeatureHWDiv", "divide">;
197 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
198 AssemblerPredicate<"FeatureT2XtPk",
200 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
201 AssemblerPredicate<"FeatureDSPThumb2",
203 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
204 AssemblerPredicate<"FeatureDB",
206 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
207 AssemblerPredicate<"FeatureMP",
209 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
210 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
211 def IsThumb : Predicate<"Subtarget->isThumb()">,
212 AssemblerPredicate<"ModeThumb", "thumb">;
213 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
214 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
215 AssemblerPredicate<"ModeThumb,FeatureThumb2",
217 def IsMClass : Predicate<"Subtarget->isMClass()">,
218 AssemblerPredicate<"FeatureMClass", "armv7m">;
219 def IsARClass : Predicate<"!Subtarget->isMClass()">,
220 AssemblerPredicate<"!FeatureMClass",
222 def IsARM : Predicate<"!Subtarget->isThumb()">,
223 AssemblerPredicate<"!ModeThumb", "arm-mode">;
224 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
225 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
226 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
228 // FIXME: Eventually this will be just "hasV6T2Ops".
229 def UseMovt : Predicate<"Subtarget->useMovt()">;
230 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
231 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
233 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
234 // But only select them if more precision in FP computation is allowed.
235 // Do not use them for Darwin platforms.
236 def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision && "
237 "!Subtarget->isTargetDarwin()">;
238 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
239 "Subtarget->isTargetDarwin()">;
241 //===----------------------------------------------------------------------===//
242 // ARM Flag Definitions.
244 class RegConstraint<string C> {
245 string Constraints = C;
248 //===----------------------------------------------------------------------===//
249 // ARM specific transformation functions and pattern fragments.
252 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
253 // so_imm_neg def below.
254 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
255 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
258 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
259 // so_imm_not def below.
260 def so_imm_not_XFORM : SDNodeXForm<imm, [{
261 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
264 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
265 def imm16_31 : ImmLeaf<i32, [{
266 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
269 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
270 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
271 int64_t Value = -(int)N->getZExtValue();
272 return Value && ARM_AM::getSOImmVal(Value) != -1;
273 }], so_imm_neg_XFORM> {
274 let ParserMatchClass = so_imm_neg_asmoperand;
277 // Note: this pattern doesn't require an encoder method and such, as it's
278 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
279 // is handled by the destination instructions, which use so_imm.
280 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
281 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
282 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
283 }], so_imm_not_XFORM> {
284 let ParserMatchClass = so_imm_not_asmoperand;
287 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
288 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
289 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
292 /// Split a 32-bit immediate into two 16 bit parts.
293 def hi16 : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
297 def lo16AllZero : PatLeaf<(i32 imm), [{
298 // Returns true if all low 16-bits are 0.
299 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
302 class BinOpWithFlagFrag<dag res> :
303 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
304 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
305 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
307 // An 'and' node with a single use.
308 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
309 return N->hasOneUse();
312 // An 'xor' node with a single use.
313 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
314 return N->hasOneUse();
317 // An 'fmul' node with a single use.
318 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
319 return N->hasOneUse();
322 // An 'fadd' node which checks for single non-hazardous use.
323 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
324 return hasNoVMLxHazardUse(N);
327 // An 'fsub' node which checks for single non-hazardous use.
328 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
329 return hasNoVMLxHazardUse(N);
332 //===----------------------------------------------------------------------===//
333 // Operand Definitions.
336 // Immediate operands with a shared generic asm render method.
337 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
340 // FIXME: rename brtarget to t2_brtarget
341 def brtarget : Operand<OtherVT> {
342 let EncoderMethod = "getBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
344 let DecoderMethod = "DecodeT2BROperand";
347 // FIXME: get rid of this one?
348 def uncondbrtarget : Operand<OtherVT> {
349 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
350 let OperandType = "OPERAND_PCREL";
353 // Branch target for ARM. Handles conditional/unconditional
354 def br_target : Operand<OtherVT> {
355 let EncoderMethod = "getARMBranchTargetOpValue";
356 let OperandType = "OPERAND_PCREL";
360 // FIXME: rename bltarget to t2_bl_target?
361 def bltarget : Operand<i32> {
362 // Encoded the same as branch targets.
363 let EncoderMethod = "getBranchTargetOpValue";
364 let OperandType = "OPERAND_PCREL";
367 // Call target for ARM. Handles conditional/unconditional
368 // FIXME: rename bl_target to t2_bltarget?
369 def bl_target : Operand<i32> {
370 let EncoderMethod = "getARMBLTargetOpValue";
371 let OperandType = "OPERAND_PCREL";
374 def blx_target : Operand<i32> {
375 let EncoderMethod = "getARMBLXTargetOpValue";
376 let OperandType = "OPERAND_PCREL";
379 // A list of registers separated by comma. Used by load/store multiple.
380 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
381 def reglist : Operand<i32> {
382 let EncoderMethod = "getRegisterListOpValue";
383 let ParserMatchClass = RegListAsmOperand;
384 let PrintMethod = "printRegisterList";
385 let DecoderMethod = "DecodeRegListOperand";
388 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
389 def dpr_reglist : Operand<i32> {
390 let EncoderMethod = "getRegisterListOpValue";
391 let ParserMatchClass = DPRRegListAsmOperand;
392 let PrintMethod = "printRegisterList";
393 let DecoderMethod = "DecodeDPRRegListOperand";
396 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
397 def spr_reglist : Operand<i32> {
398 let EncoderMethod = "getRegisterListOpValue";
399 let ParserMatchClass = SPRRegListAsmOperand;
400 let PrintMethod = "printRegisterList";
401 let DecoderMethod = "DecodeSPRRegListOperand";
404 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
405 def cpinst_operand : Operand<i32> {
406 let PrintMethod = "printCPInstOperand";
410 def pclabel : Operand<i32> {
411 let PrintMethod = "printPCLabel";
414 // ADR instruction labels.
415 def adrlabel : Operand<i32> {
416 let EncoderMethod = "getAdrLabelOpValue";
419 def neon_vcvt_imm32 : Operand<i32> {
420 let EncoderMethod = "getNEONVcvtImm32OpValue";
421 let DecoderMethod = "DecodeVCVTImmOperand";
424 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
425 def rot_imm_XFORM: SDNodeXForm<imm, [{
426 switch (N->getZExtValue()){
428 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
429 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
430 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
431 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
434 def RotImmAsmOperand : AsmOperandClass {
436 let ParserMethod = "parseRotImm";
438 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
439 int32_t v = N->getZExtValue();
440 return v == 8 || v == 16 || v == 24; }],
442 let PrintMethod = "printRotImmOperand";
443 let ParserMatchClass = RotImmAsmOperand;
446 // shift_imm: An integer that encodes a shift amount and the type of shift
447 // (asr or lsl). The 6-bit immediate encodes as:
450 // {4-0} imm5 shift amount.
451 // asr #32 encoded as imm5 == 0.
452 def ShifterImmAsmOperand : AsmOperandClass {
453 let Name = "ShifterImm";
454 let ParserMethod = "parseShifterImm";
456 def shift_imm : Operand<i32> {
457 let PrintMethod = "printShiftImmOperand";
458 let ParserMatchClass = ShifterImmAsmOperand;
461 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
462 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
463 def so_reg_reg : Operand<i32>, // reg reg imm
464 ComplexPattern<i32, 3, "SelectRegShifterOperand",
465 [shl, srl, sra, rotr]> {
466 let EncoderMethod = "getSORegRegOpValue";
467 let PrintMethod = "printSORegRegOperand";
468 let DecoderMethod = "DecodeSORegRegOperand";
469 let ParserMatchClass = ShiftedRegAsmOperand;
470 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
473 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
474 def so_reg_imm : Operand<i32>, // reg imm
475 ComplexPattern<i32, 2, "SelectImmShifterOperand",
476 [shl, srl, sra, rotr]> {
477 let EncoderMethod = "getSORegImmOpValue";
478 let PrintMethod = "printSORegImmOperand";
479 let DecoderMethod = "DecodeSORegImmOperand";
480 let ParserMatchClass = ShiftedImmAsmOperand;
481 let MIOperandInfo = (ops GPR, i32imm);
484 // FIXME: Does this need to be distinct from so_reg?
485 def shift_so_reg_reg : Operand<i32>, // reg reg imm
486 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
487 [shl,srl,sra,rotr]> {
488 let EncoderMethod = "getSORegRegOpValue";
489 let PrintMethod = "printSORegRegOperand";
490 let DecoderMethod = "DecodeSORegRegOperand";
491 let ParserMatchClass = ShiftedRegAsmOperand;
492 let MIOperandInfo = (ops GPR, GPR, i32imm);
495 // FIXME: Does this need to be distinct from so_reg?
496 def shift_so_reg_imm : Operand<i32>, // reg reg imm
497 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
498 [shl,srl,sra,rotr]> {
499 let EncoderMethod = "getSORegImmOpValue";
500 let PrintMethod = "printSORegImmOperand";
501 let DecoderMethod = "DecodeSORegImmOperand";
502 let ParserMatchClass = ShiftedImmAsmOperand;
503 let MIOperandInfo = (ops GPR, i32imm);
507 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
508 // 8-bit immediate rotated by an arbitrary number of bits.
509 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
510 def so_imm : Operand<i32>, ImmLeaf<i32, [{
511 return ARM_AM::getSOImmVal(Imm) != -1;
513 let EncoderMethod = "getSOImmOpValue";
514 let ParserMatchClass = SOImmAsmOperand;
515 let DecoderMethod = "DecodeSOImmOperand";
518 // Break so_imm's up into two pieces. This handles immediates with up to 16
519 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
520 // get the first/second pieces.
521 def so_imm2part : PatLeaf<(imm), [{
522 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
525 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
527 def arm_i32imm : PatLeaf<(imm), [{
528 if (Subtarget->hasV6T2Ops())
530 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
533 /// imm0_1 predicate - Immediate in the range [0,1].
534 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
535 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
537 /// imm0_3 predicate - Immediate in the range [0,3].
538 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
539 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
541 /// imm0_7 predicate - Immediate in the range [0,7].
542 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
543 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
544 return Imm >= 0 && Imm < 8;
546 let ParserMatchClass = Imm0_7AsmOperand;
549 /// imm8 predicate - Immediate is exactly 8.
550 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
551 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
552 let ParserMatchClass = Imm8AsmOperand;
555 /// imm16 predicate - Immediate is exactly 16.
556 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
557 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
558 let ParserMatchClass = Imm16AsmOperand;
561 /// imm32 predicate - Immediate is exactly 32.
562 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
563 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
564 let ParserMatchClass = Imm32AsmOperand;
567 /// imm1_7 predicate - Immediate in the range [1,7].
568 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
569 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
570 let ParserMatchClass = Imm1_7AsmOperand;
573 /// imm1_15 predicate - Immediate in the range [1,15].
574 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
575 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
576 let ParserMatchClass = Imm1_15AsmOperand;
579 /// imm1_31 predicate - Immediate in the range [1,31].
580 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
581 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
582 let ParserMatchClass = Imm1_31AsmOperand;
585 /// imm0_15 predicate - Immediate in the range [0,15].
586 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
587 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
588 return Imm >= 0 && Imm < 16;
590 let ParserMatchClass = Imm0_15AsmOperand;
593 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
594 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
595 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
596 return Imm >= 0 && Imm < 32;
598 let ParserMatchClass = Imm0_31AsmOperand;
601 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
602 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
603 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
604 return Imm >= 0 && Imm < 32;
606 let ParserMatchClass = Imm0_32AsmOperand;
609 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
610 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
611 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
612 return Imm >= 0 && Imm < 64;
614 let ParserMatchClass = Imm0_63AsmOperand;
617 /// imm0_255 predicate - Immediate in the range [0,255].
618 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
619 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
620 let ParserMatchClass = Imm0_255AsmOperand;
623 /// imm0_65535 - An immediate is in the range [0.65535].
624 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
625 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
626 return Imm >= 0 && Imm < 65536;
628 let ParserMatchClass = Imm0_65535AsmOperand;
631 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
632 // a relocatable expression.
634 // FIXME: This really needs a Thumb version separate from the ARM version.
635 // While the range is the same, and can thus use the same match class,
636 // the encoding is different so it should have a different encoder method.
637 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
638 def imm0_65535_expr : Operand<i32> {
639 let EncoderMethod = "getHiLo16ImmOpValue";
640 let ParserMatchClass = Imm0_65535ExprAsmOperand;
643 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
644 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
645 def imm24b : Operand<i32>, ImmLeaf<i32, [{
646 return Imm >= 0 && Imm <= 0xffffff;
648 let ParserMatchClass = Imm24bitAsmOperand;
652 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
654 def BitfieldAsmOperand : AsmOperandClass {
655 let Name = "Bitfield";
656 let ParserMethod = "parseBitfield";
659 def bf_inv_mask_imm : Operand<i32>,
661 return ARM::isBitFieldInvertedMask(N->getZExtValue());
663 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
664 let PrintMethod = "printBitfieldInvMaskImmOperand";
665 let DecoderMethod = "DecodeBitfieldMaskOperand";
666 let ParserMatchClass = BitfieldAsmOperand;
669 def imm1_32_XFORM: SDNodeXForm<imm, [{
670 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
672 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
673 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
674 uint64_t Imm = N->getZExtValue();
675 return Imm > 0 && Imm <= 32;
678 let PrintMethod = "printImmPlusOneOperand";
679 let ParserMatchClass = Imm1_32AsmOperand;
682 def imm1_16_XFORM: SDNodeXForm<imm, [{
683 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
685 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
686 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
688 let PrintMethod = "printImmPlusOneOperand";
689 let ParserMatchClass = Imm1_16AsmOperand;
692 // Define ARM specific addressing modes.
693 // addrmode_imm12 := reg +/- imm12
695 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
696 def addrmode_imm12 : Operand<i32>,
697 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
698 // 12-bit immediate operand. Note that instructions using this encode
699 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
700 // immediate values are as normal.
702 let EncoderMethod = "getAddrModeImm12OpValue";
703 let PrintMethod = "printAddrModeImm12Operand";
704 let DecoderMethod = "DecodeAddrModeImm12Operand";
705 let ParserMatchClass = MemImm12OffsetAsmOperand;
706 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
708 // ldst_so_reg := reg +/- reg shop imm
710 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
711 def ldst_so_reg : Operand<i32>,
712 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
713 let EncoderMethod = "getLdStSORegOpValue";
714 // FIXME: Simplify the printer
715 let PrintMethod = "printAddrMode2Operand";
716 let DecoderMethod = "DecodeSORegMemOperand";
717 let ParserMatchClass = MemRegOffsetAsmOperand;
718 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
721 // postidx_imm8 := +/- [0,255]
724 // {8} 1 is imm8 is non-negative. 0 otherwise.
725 // {7-0} [0,255] imm8 value.
726 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
727 def postidx_imm8 : Operand<i32> {
728 let PrintMethod = "printPostIdxImm8Operand";
729 let ParserMatchClass = PostIdxImm8AsmOperand;
730 let MIOperandInfo = (ops i32imm);
733 // postidx_imm8s4 := +/- [0,1020]
736 // {8} 1 is imm8 is non-negative. 0 otherwise.
737 // {7-0} [0,255] imm8 value, scaled by 4.
738 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
739 def postidx_imm8s4 : Operand<i32> {
740 let PrintMethod = "printPostIdxImm8s4Operand";
741 let ParserMatchClass = PostIdxImm8s4AsmOperand;
742 let MIOperandInfo = (ops i32imm);
746 // postidx_reg := +/- reg
748 def PostIdxRegAsmOperand : AsmOperandClass {
749 let Name = "PostIdxReg";
750 let ParserMethod = "parsePostIdxReg";
752 def postidx_reg : Operand<i32> {
753 let EncoderMethod = "getPostIdxRegOpValue";
754 let DecoderMethod = "DecodePostIdxReg";
755 let PrintMethod = "printPostIdxRegOperand";
756 let ParserMatchClass = PostIdxRegAsmOperand;
757 let MIOperandInfo = (ops GPRnopc, i32imm);
761 // addrmode2 := reg +/- imm12
762 // := reg +/- reg shop imm
764 // FIXME: addrmode2 should be refactored the rest of the way to always
765 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
766 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
767 def addrmode2 : Operand<i32>,
768 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
769 let EncoderMethod = "getAddrMode2OpValue";
770 let PrintMethod = "printAddrMode2Operand";
771 let ParserMatchClass = AddrMode2AsmOperand;
772 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
775 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
776 let Name = "PostIdxRegShifted";
777 let ParserMethod = "parsePostIdxReg";
779 def am2offset_reg : Operand<i32>,
780 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
781 [], [SDNPWantRoot]> {
782 let EncoderMethod = "getAddrMode2OffsetOpValue";
783 let PrintMethod = "printAddrMode2OffsetOperand";
784 // When using this for assembly, it's always as a post-index offset.
785 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
786 let MIOperandInfo = (ops GPRnopc, i32imm);
789 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
790 // the GPR is purely vestigal at this point.
791 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
792 def am2offset_imm : Operand<i32>,
793 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
794 [], [SDNPWantRoot]> {
795 let EncoderMethod = "getAddrMode2OffsetOpValue";
796 let PrintMethod = "printAddrMode2OffsetOperand";
797 let ParserMatchClass = AM2OffsetImmAsmOperand;
798 let MIOperandInfo = (ops GPRnopc, i32imm);
802 // addrmode3 := reg +/- reg
803 // addrmode3 := reg +/- imm8
805 // FIXME: split into imm vs. reg versions.
806 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
807 def addrmode3 : Operand<i32>,
808 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
809 let EncoderMethod = "getAddrMode3OpValue";
810 let PrintMethod = "printAddrMode3Operand";
811 let ParserMatchClass = AddrMode3AsmOperand;
812 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
815 // FIXME: split into imm vs. reg versions.
816 // FIXME: parser method to handle +/- register.
817 def AM3OffsetAsmOperand : AsmOperandClass {
818 let Name = "AM3Offset";
819 let ParserMethod = "parseAM3Offset";
821 def am3offset : Operand<i32>,
822 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
823 [], [SDNPWantRoot]> {
824 let EncoderMethod = "getAddrMode3OffsetOpValue";
825 let PrintMethod = "printAddrMode3OffsetOperand";
826 let ParserMatchClass = AM3OffsetAsmOperand;
827 let MIOperandInfo = (ops GPR, i32imm);
830 // ldstm_mode := {ia, ib, da, db}
832 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
833 let EncoderMethod = "getLdStmModeOpValue";
834 let PrintMethod = "printLdStmModeOperand";
837 // addrmode5 := reg +/- imm8*4
839 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
840 def addrmode5 : Operand<i32>,
841 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
842 let PrintMethod = "printAddrMode5Operand";
843 let EncoderMethod = "getAddrMode5OpValue";
844 let DecoderMethod = "DecodeAddrMode5Operand";
845 let ParserMatchClass = AddrMode5AsmOperand;
846 let MIOperandInfo = (ops GPR:$base, i32imm);
849 // addrmode6 := reg with optional alignment
851 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
852 def addrmode6 : Operand<i32>,
853 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
854 let PrintMethod = "printAddrMode6Operand";
855 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
856 let EncoderMethod = "getAddrMode6AddressOpValue";
857 let DecoderMethod = "DecodeAddrMode6Operand";
858 let ParserMatchClass = AddrMode6AsmOperand;
861 def am6offset : Operand<i32>,
862 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
863 [], [SDNPWantRoot]> {
864 let PrintMethod = "printAddrMode6OffsetOperand";
865 let MIOperandInfo = (ops GPR);
866 let EncoderMethod = "getAddrMode6OffsetOpValue";
867 let DecoderMethod = "DecodeGPRRegisterClass";
870 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
871 // (single element from one lane) for size 32.
872 def addrmode6oneL32 : Operand<i32>,
873 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
874 let PrintMethod = "printAddrMode6Operand";
875 let MIOperandInfo = (ops GPR:$addr, i32imm);
876 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
879 // Special version of addrmode6 to handle alignment encoding for VLD-dup
880 // instructions, specifically VLD4-dup.
881 def addrmode6dup : Operand<i32>,
882 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
883 let PrintMethod = "printAddrMode6Operand";
884 let MIOperandInfo = (ops GPR:$addr, i32imm);
885 let EncoderMethod = "getAddrMode6DupAddressOpValue";
886 // FIXME: This is close, but not quite right. The alignment specifier is
888 let ParserMatchClass = AddrMode6AsmOperand;
891 // addrmodepc := pc + reg
893 def addrmodepc : Operand<i32>,
894 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
895 let PrintMethod = "printAddrModePCOperand";
896 let MIOperandInfo = (ops GPR, i32imm);
899 // addr_offset_none := reg
901 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
902 def addr_offset_none : Operand<i32>,
903 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
904 let PrintMethod = "printAddrMode7Operand";
905 let DecoderMethod = "DecodeAddrMode7Operand";
906 let ParserMatchClass = MemNoOffsetAsmOperand;
907 let MIOperandInfo = (ops GPR:$base);
910 def nohash_imm : Operand<i32> {
911 let PrintMethod = "printNoHashImmediate";
914 def CoprocNumAsmOperand : AsmOperandClass {
915 let Name = "CoprocNum";
916 let ParserMethod = "parseCoprocNumOperand";
918 def p_imm : Operand<i32> {
919 let PrintMethod = "printPImmediate";
920 let ParserMatchClass = CoprocNumAsmOperand;
921 let DecoderMethod = "DecodeCoprocessor";
924 def pf_imm : Operand<i32> {
925 let PrintMethod = "printPImmediate";
926 let ParserMatchClass = CoprocNumAsmOperand;
929 def CoprocRegAsmOperand : AsmOperandClass {
930 let Name = "CoprocReg";
931 let ParserMethod = "parseCoprocRegOperand";
933 def c_imm : Operand<i32> {
934 let PrintMethod = "printCImmediate";
935 let ParserMatchClass = CoprocRegAsmOperand;
937 def CoprocOptionAsmOperand : AsmOperandClass {
938 let Name = "CoprocOption";
939 let ParserMethod = "parseCoprocOptionOperand";
941 def coproc_option_imm : Operand<i32> {
942 let PrintMethod = "printCoprocOptionImm";
943 let ParserMatchClass = CoprocOptionAsmOperand;
946 //===----------------------------------------------------------------------===//
948 include "ARMInstrFormats.td"
950 //===----------------------------------------------------------------------===//
951 // Multiclass helpers...
954 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
955 /// binop that produces a value.
956 let TwoOperandAliasConstraint = "$Rn = $Rd" in
957 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
958 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
959 PatFrag opnode, string baseOpc, bit Commutable = 0> {
960 // The register-immediate version is re-materializable. This is useful
961 // in particular for taking the address of a local.
962 let isReMaterializable = 1 in {
963 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
964 iii, opc, "\t$Rd, $Rn, $imm",
965 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
970 let Inst{19-16} = Rn;
971 let Inst{15-12} = Rd;
972 let Inst{11-0} = imm;
975 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
976 iir, opc, "\t$Rd, $Rn, $Rm",
977 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
982 let isCommutable = Commutable;
983 let Inst{19-16} = Rn;
984 let Inst{15-12} = Rd;
985 let Inst{11-4} = 0b00000000;
989 def rsi : AsI1<opcod, (outs GPR:$Rd),
990 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
991 iis, opc, "\t$Rd, $Rn, $shift",
992 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
997 let Inst{19-16} = Rn;
998 let Inst{15-12} = Rd;
999 let Inst{11-5} = shift{11-5};
1001 let Inst{3-0} = shift{3-0};
1004 def rsr : AsI1<opcod, (outs GPR:$Rd),
1005 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1006 iis, opc, "\t$Rd, $Rn, $shift",
1007 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1012 let Inst{19-16} = Rn;
1013 let Inst{15-12} = Rd;
1014 let Inst{11-8} = shift{11-8};
1016 let Inst{6-5} = shift{6-5};
1018 let Inst{3-0} = shift{3-0};
1022 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1023 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1024 /// it is equivalent to the AsI1_bin_irs counterpart.
1025 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1026 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1027 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1028 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1029 // The register-immediate version is re-materializable. This is useful
1030 // in particular for taking the address of a local.
1031 let isReMaterializable = 1 in {
1032 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1033 iii, opc, "\t$Rd, $Rn, $imm",
1034 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1039 let Inst{19-16} = Rn;
1040 let Inst{15-12} = Rd;
1041 let Inst{11-0} = imm;
1044 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1045 iir, opc, "\t$Rd, $Rn, $Rm",
1046 [/* pattern left blank */]> {
1050 let Inst{11-4} = 0b00000000;
1053 let Inst{15-12} = Rd;
1054 let Inst{19-16} = Rn;
1057 def rsi : AsI1<opcod, (outs GPR:$Rd),
1058 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1059 iis, opc, "\t$Rd, $Rn, $shift",
1060 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1065 let Inst{19-16} = Rn;
1066 let Inst{15-12} = Rd;
1067 let Inst{11-5} = shift{11-5};
1069 let Inst{3-0} = shift{3-0};
1072 def rsr : AsI1<opcod, (outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1074 iis, opc, "\t$Rd, $Rn, $shift",
1075 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1080 let Inst{19-16} = Rn;
1081 let Inst{15-12} = Rd;
1082 let Inst{11-8} = shift{11-8};
1084 let Inst{6-5} = shift{6-5};
1086 let Inst{3-0} = shift{3-0};
1090 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1092 /// These opcodes will be converted to the real non-S opcodes by
1093 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1094 let hasPostISelHook = 1, Defs = [CPSR] in {
1095 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1096 InstrItinClass iis, PatFrag opnode,
1097 bit Commutable = 0> {
1098 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1100 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1102 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1104 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1105 let isCommutable = Commutable;
1107 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1108 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1110 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1111 so_reg_imm:$shift))]>;
1113 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1114 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1116 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1117 so_reg_reg:$shift))]>;
1121 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1122 /// operands are reversed.
1123 let hasPostISelHook = 1, Defs = [CPSR] in {
1124 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1125 InstrItinClass iis, PatFrag opnode,
1126 bit Commutable = 0> {
1127 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1129 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1131 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1132 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1134 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1137 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1138 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1140 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1145 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1146 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1147 /// a explicit result, only implicitly set CPSR.
1148 let isCompare = 1, Defs = [CPSR] in {
1149 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1150 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1151 PatFrag opnode, bit Commutable = 0> {
1152 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1154 [(opnode GPR:$Rn, so_imm:$imm)]> {
1159 let Inst{19-16} = Rn;
1160 let Inst{15-12} = 0b0000;
1161 let Inst{11-0} = imm;
1163 let Unpredictable{15-12} = 0b1111;
1165 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1167 [(opnode GPR:$Rn, GPR:$Rm)]> {
1170 let isCommutable = Commutable;
1173 let Inst{19-16} = Rn;
1174 let Inst{15-12} = 0b0000;
1175 let Inst{11-4} = 0b00000000;
1178 let Unpredictable{15-12} = 0b1111;
1180 def rsi : AI1<opcod, (outs),
1181 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1182 opc, "\t$Rn, $shift",
1183 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1188 let Inst{19-16} = Rn;
1189 let Inst{15-12} = 0b0000;
1190 let Inst{11-5} = shift{11-5};
1192 let Inst{3-0} = shift{3-0};
1194 let Unpredictable{15-12} = 0b1111;
1196 def rsr : AI1<opcod, (outs),
1197 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1198 opc, "\t$Rn, $shift",
1199 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1204 let Inst{19-16} = Rn;
1205 let Inst{15-12} = 0b0000;
1206 let Inst{11-8} = shift{11-8};
1208 let Inst{6-5} = shift{6-5};
1210 let Inst{3-0} = shift{3-0};
1212 let Unpredictable{15-12} = 0b1111;
1218 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1219 /// register and one whose operand is a register rotated by 8/16/24.
1220 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1221 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1222 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1223 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1224 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1225 Requires<[IsARM, HasV6]> {
1229 let Inst{19-16} = 0b1111;
1230 let Inst{15-12} = Rd;
1231 let Inst{11-10} = rot;
1235 class AI_ext_rrot_np<bits<8> opcod, string opc>
1236 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1237 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1238 Requires<[IsARM, HasV6]> {
1240 let Inst{19-16} = 0b1111;
1241 let Inst{11-10} = rot;
1244 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1245 /// register and one whose operand is a register rotated by 8/16/24.
1246 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1247 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1248 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1249 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1250 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1251 Requires<[IsARM, HasV6]> {
1256 let Inst{19-16} = Rn;
1257 let Inst{15-12} = Rd;
1258 let Inst{11-10} = rot;
1259 let Inst{9-4} = 0b000111;
1263 class AI_exta_rrot_np<bits<8> opcod, string opc>
1264 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1265 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1266 Requires<[IsARM, HasV6]> {
1269 let Inst{19-16} = Rn;
1270 let Inst{11-10} = rot;
1273 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1274 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1275 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1276 string baseOpc, bit Commutable = 0> {
1277 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1278 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1279 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1280 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1286 let Inst{15-12} = Rd;
1287 let Inst{19-16} = Rn;
1288 let Inst{11-0} = imm;
1290 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1291 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1292 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1297 let Inst{11-4} = 0b00000000;
1299 let isCommutable = Commutable;
1301 let Inst{15-12} = Rd;
1302 let Inst{19-16} = Rn;
1304 def rsi : AsI1<opcod, (outs GPR:$Rd),
1305 (ins GPR:$Rn, so_reg_imm:$shift),
1306 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1307 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1313 let Inst{19-16} = Rn;
1314 let Inst{15-12} = Rd;
1315 let Inst{11-5} = shift{11-5};
1317 let Inst{3-0} = shift{3-0};
1319 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1320 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1321 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1322 [(set GPRnopc:$Rd, CPSR,
1323 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1329 let Inst{19-16} = Rn;
1330 let Inst{15-12} = Rd;
1331 let Inst{11-8} = shift{11-8};
1333 let Inst{6-5} = shift{6-5};
1335 let Inst{3-0} = shift{3-0};
1340 /// AI1_rsc_irs - Define instructions and patterns for rsc
1341 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1342 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1344 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1345 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1346 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1347 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1353 let Inst{15-12} = Rd;
1354 let Inst{19-16} = Rn;
1355 let Inst{11-0} = imm;
1357 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1358 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1359 [/* pattern left blank */]> {
1363 let Inst{11-4} = 0b00000000;
1366 let Inst{15-12} = Rd;
1367 let Inst{19-16} = Rn;
1369 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1370 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1371 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1377 let Inst{19-16} = Rn;
1378 let Inst{15-12} = Rd;
1379 let Inst{11-5} = shift{11-5};
1381 let Inst{3-0} = shift{3-0};
1383 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1384 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1385 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1391 let Inst{19-16} = Rn;
1392 let Inst{15-12} = Rd;
1393 let Inst{11-8} = shift{11-8};
1395 let Inst{6-5} = shift{6-5};
1397 let Inst{3-0} = shift{3-0};
1402 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1403 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1404 InstrItinClass iir, PatFrag opnode> {
1405 // Note: We use the complex addrmode_imm12 rather than just an input
1406 // GPR and a constrained immediate so that we can use this to match
1407 // frame index references and avoid matching constant pool references.
1408 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1409 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1410 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1413 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1414 let Inst{19-16} = addr{16-13}; // Rn
1415 let Inst{15-12} = Rt;
1416 let Inst{11-0} = addr{11-0}; // imm12
1418 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1419 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1420 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1423 let shift{4} = 0; // Inst{4} = 0
1424 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1425 let Inst{19-16} = shift{16-13}; // Rn
1426 let Inst{15-12} = Rt;
1427 let Inst{11-0} = shift{11-0};
1432 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1433 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1434 InstrItinClass iir, PatFrag opnode> {
1435 // Note: We use the complex addrmode_imm12 rather than just an input
1436 // GPR and a constrained immediate so that we can use this to match
1437 // frame index references and avoid matching constant pool references.
1438 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1439 (ins addrmode_imm12:$addr),
1440 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1441 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1444 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1445 let Inst{19-16} = addr{16-13}; // Rn
1446 let Inst{15-12} = Rt;
1447 let Inst{11-0} = addr{11-0}; // imm12
1449 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1450 (ins ldst_so_reg:$shift),
1451 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1452 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1455 let shift{4} = 0; // Inst{4} = 0
1456 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1457 let Inst{19-16} = shift{16-13}; // Rn
1458 let Inst{15-12} = Rt;
1459 let Inst{11-0} = shift{11-0};
1465 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1466 InstrItinClass iir, PatFrag opnode> {
1467 // Note: We use the complex addrmode_imm12 rather than just an input
1468 // GPR and a constrained immediate so that we can use this to match
1469 // frame index references and avoid matching constant pool references.
1470 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1471 (ins GPR:$Rt, addrmode_imm12:$addr),
1472 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1473 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1476 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1477 let Inst{19-16} = addr{16-13}; // Rn
1478 let Inst{15-12} = Rt;
1479 let Inst{11-0} = addr{11-0}; // imm12
1481 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1482 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1483 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1486 let shift{4} = 0; // Inst{4} = 0
1487 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1488 let Inst{19-16} = shift{16-13}; // Rn
1489 let Inst{15-12} = Rt;
1490 let Inst{11-0} = shift{11-0};
1494 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1495 InstrItinClass iir, PatFrag opnode> {
1496 // Note: We use the complex addrmode_imm12 rather than just an input
1497 // GPR and a constrained immediate so that we can use this to match
1498 // frame index references and avoid matching constant pool references.
1499 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1500 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1501 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1502 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1505 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1506 let Inst{19-16} = addr{16-13}; // Rn
1507 let Inst{15-12} = Rt;
1508 let Inst{11-0} = addr{11-0}; // imm12
1510 def rs : AI2ldst<0b011, 0, isByte, (outs),
1511 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1512 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1513 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1516 let shift{4} = 0; // Inst{4} = 0
1517 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1518 let Inst{19-16} = shift{16-13}; // Rn
1519 let Inst{15-12} = Rt;
1520 let Inst{11-0} = shift{11-0};
1525 //===----------------------------------------------------------------------===//
1527 //===----------------------------------------------------------------------===//
1529 //===----------------------------------------------------------------------===//
1530 // Miscellaneous Instructions.
1533 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1534 /// the function. The first operand is the ID# for this instruction, the second
1535 /// is the index into the MachineConstantPool that this is, the third is the
1536 /// size in bytes of this constant pool entry.
1537 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1538 def CONSTPOOL_ENTRY :
1539 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1540 i32imm:$size), NoItinerary, []>;
1542 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1543 // from removing one half of the matched pairs. That breaks PEI, which assumes
1544 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1545 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1546 def ADJCALLSTACKUP :
1547 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1548 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1550 def ADJCALLSTACKDOWN :
1551 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1552 [(ARMcallseq_start timm:$amt)]>;
1555 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1556 // (These pseudos use a hand-written selection code).
1557 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1558 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1559 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1561 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1562 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1564 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1565 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1567 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1568 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1570 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1571 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1573 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1574 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1576 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1577 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1579 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1580 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1581 GPR:$set1, GPR:$set2),
1585 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1586 Requires<[IsARM, HasV6T2]> {
1587 let Inst{27-16} = 0b001100100000;
1588 let Inst{15-8} = 0b11110000;
1589 let Inst{7-0} = 0b00000000;
1592 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1593 Requires<[IsARM, HasV6T2]> {
1594 let Inst{27-16} = 0b001100100000;
1595 let Inst{15-8} = 0b11110000;
1596 let Inst{7-0} = 0b00000001;
1599 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1600 Requires<[IsARM, HasV6T2]> {
1601 let Inst{27-16} = 0b001100100000;
1602 let Inst{15-8} = 0b11110000;
1603 let Inst{7-0} = 0b00000010;
1606 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1607 Requires<[IsARM, HasV6T2]> {
1608 let Inst{27-16} = 0b001100100000;
1609 let Inst{15-8} = 0b11110000;
1610 let Inst{7-0} = 0b00000011;
1613 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1614 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1619 let Inst{15-12} = Rd;
1620 let Inst{19-16} = Rn;
1621 let Inst{27-20} = 0b01101000;
1622 let Inst{7-4} = 0b1011;
1623 let Inst{11-8} = 0b1111;
1625 let Unpredictable{11-8} = 0b1111;
1628 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1629 []>, Requires<[IsARM, HasV6T2]> {
1630 let Inst{27-16} = 0b001100100000;
1631 let Inst{15-8} = 0b11110000;
1632 let Inst{7-0} = 0b00000100;
1635 // The i32imm operand $val can be used by a debugger to store more information
1636 // about the breakpoint.
1637 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1638 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1640 let Inst{3-0} = val{3-0};
1641 let Inst{19-8} = val{15-4};
1642 let Inst{27-20} = 0b00010010;
1643 let Inst{7-4} = 0b0111;
1646 // Change Processor State
1647 // FIXME: We should use InstAlias to handle the optional operands.
1648 class CPS<dag iops, string asm_ops>
1649 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1650 []>, Requires<[IsARM]> {
1656 let Inst{31-28} = 0b1111;
1657 let Inst{27-20} = 0b00010000;
1658 let Inst{19-18} = imod;
1659 let Inst{17} = M; // Enabled if mode is set;
1660 let Inst{16-9} = 0b00000000;
1661 let Inst{8-6} = iflags;
1663 let Inst{4-0} = mode;
1666 let DecoderMethod = "DecodeCPSInstruction" in {
1668 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1669 "$imod\t$iflags, $mode">;
1670 let mode = 0, M = 0 in
1671 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1673 let imod = 0, iflags = 0, M = 1 in
1674 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1677 // Preload signals the memory system of possible future data/instruction access.
1678 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1680 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1681 !strconcat(opc, "\t$addr"),
1682 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1685 let Inst{31-26} = 0b111101;
1686 let Inst{25} = 0; // 0 for immediate form
1687 let Inst{24} = data;
1688 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1689 let Inst{22} = read;
1690 let Inst{21-20} = 0b01;
1691 let Inst{19-16} = addr{16-13}; // Rn
1692 let Inst{15-12} = 0b1111;
1693 let Inst{11-0} = addr{11-0}; // imm12
1696 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1697 !strconcat(opc, "\t$shift"),
1698 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1700 let Inst{31-26} = 0b111101;
1701 let Inst{25} = 1; // 1 for register form
1702 let Inst{24} = data;
1703 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1704 let Inst{22} = read;
1705 let Inst{21-20} = 0b01;
1706 let Inst{19-16} = shift{16-13}; // Rn
1707 let Inst{15-12} = 0b1111;
1708 let Inst{11-0} = shift{11-0};
1713 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1714 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1715 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1717 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1718 "setend\t$end", []>, Requires<[IsARM]> {
1720 let Inst{31-10} = 0b1111000100000001000000;
1725 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1726 []>, Requires<[IsARM, HasV7]> {
1728 let Inst{27-4} = 0b001100100000111100001111;
1729 let Inst{3-0} = opt;
1732 // A5.4 Permanently UNDEFINED instructions.
1733 let isBarrier = 1, isTerminator = 1 in
1734 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1737 let Inst = 0xe7ffdefe;
1740 // Address computation and loads and stores in PIC mode.
1741 let isNotDuplicable = 1 in {
1742 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1744 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1746 let AddedComplexity = 10 in {
1747 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1749 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1751 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1753 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1755 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1757 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1759 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1761 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1763 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1765 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1767 let AddedComplexity = 10 in {
1768 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1769 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1771 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1772 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1773 addrmodepc:$addr)]>;
1775 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1776 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1778 } // isNotDuplicable = 1
1781 // LEApcrel - Load a pc-relative address into a register without offending the
1783 let neverHasSideEffects = 1, isReMaterializable = 1 in
1784 // The 'adr' mnemonic encodes differently if the label is before or after
1785 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1786 // know until then which form of the instruction will be used.
1787 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1788 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1791 let Inst{27-25} = 0b001;
1793 let Inst{23-22} = label{13-12};
1796 let Inst{19-16} = 0b1111;
1797 let Inst{15-12} = Rd;
1798 let Inst{11-0} = label{11-0};
1800 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1803 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1804 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1807 //===----------------------------------------------------------------------===//
1808 // Control Flow Instructions.
1811 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1813 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1814 "bx", "\tlr", [(ARMretflag)]>,
1815 Requires<[IsARM, HasV4T]> {
1816 let Inst{27-0} = 0b0001001011111111111100011110;
1820 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1821 "mov", "\tpc, lr", [(ARMretflag)]>,
1822 Requires<[IsARM, NoV4T]> {
1823 let Inst{27-0} = 0b0001101000001111000000001110;
1827 // Indirect branches
1828 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1830 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1831 [(brind GPR:$dst)]>,
1832 Requires<[IsARM, HasV4T]> {
1834 let Inst{31-4} = 0b1110000100101111111111110001;
1835 let Inst{3-0} = dst;
1838 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1839 "bx", "\t$dst", [/* pattern left blank */]>,
1840 Requires<[IsARM, HasV4T]> {
1842 let Inst{27-4} = 0b000100101111111111110001;
1843 let Inst{3-0} = dst;
1847 // SP is marked as a use to prevent stack-pointer assignments that appear
1848 // immediately before calls from potentially appearing dead.
1850 // FIXME: Do we really need a non-predicated version? If so, it should
1851 // at least be a pseudo instruction expanding to the predicated version
1852 // at MC lowering time.
1853 Defs = [LR], Uses = [SP] in {
1854 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1855 IIC_Br, "bl\t$func",
1856 [(ARMcall tglobaladdr:$func)]>,
1858 let Inst{31-28} = 0b1110;
1860 let Inst{23-0} = func;
1861 let DecoderMethod = "DecodeBranchImmInstruction";
1864 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1865 IIC_Br, "bl", "\t$func",
1866 [(ARMcall_pred tglobaladdr:$func)]>,
1869 let Inst{23-0} = func;
1870 let DecoderMethod = "DecodeBranchImmInstruction";
1874 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1875 IIC_Br, "blx\t$func",
1876 [(ARMcall GPR:$func)]>,
1877 Requires<[IsARM, HasV5T]> {
1879 let Inst{31-4} = 0b1110000100101111111111110011;
1880 let Inst{3-0} = func;
1883 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1884 IIC_Br, "blx", "\t$func",
1885 [(ARMcall_pred GPR:$func)]>,
1886 Requires<[IsARM, HasV5T]> {
1888 let Inst{27-4} = 0b000100101111111111110011;
1889 let Inst{3-0} = func;
1893 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1894 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1895 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1896 Requires<[IsARM, HasV4T]>;
1899 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1900 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1901 Requires<[IsARM, NoV4T]>;
1903 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1904 // return stack predictor.
1905 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1906 (ins bl_target:$func, variable_ops),
1907 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1911 let isBranch = 1, isTerminator = 1 in {
1912 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1913 // a two-value operand where a dag node expects two operands. :(
1914 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1915 IIC_Br, "b", "\t$target",
1916 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1918 let Inst{23-0} = target;
1919 let DecoderMethod = "DecodeBranchImmInstruction";
1922 let isBarrier = 1 in {
1923 // B is "predicable" since it's just a Bcc with an 'always' condition.
1924 let isPredicable = 1 in
1925 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1926 // should be sufficient.
1927 // FIXME: Is B really a Barrier? That doesn't seem right.
1928 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1929 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1931 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1932 def BR_JTr : ARMPseudoInst<(outs),
1933 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1935 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1936 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1937 // into i12 and rs suffixed versions.
1938 def BR_JTm : ARMPseudoInst<(outs),
1939 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1941 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1943 def BR_JTadd : ARMPseudoInst<(outs),
1944 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1946 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1948 } // isNotDuplicable = 1, isIndirectBranch = 1
1954 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1955 "blx\t$target", []>,
1956 Requires<[IsARM, HasV5T]> {
1957 let Inst{31-25} = 0b1111101;
1959 let Inst{23-0} = target{24-1};
1960 let Inst{24} = target{0};
1963 // Branch and Exchange Jazelle
1964 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1965 [/* pattern left blank */]> {
1967 let Inst{23-20} = 0b0010;
1968 let Inst{19-8} = 0xfff;
1969 let Inst{7-4} = 0b0010;
1970 let Inst{3-0} = func;
1975 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1976 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1979 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1982 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1984 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1987 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1993 // Secure Monitor Call is a system instruction.
1994 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1997 let Inst{23-4} = 0b01100000000000000111;
1998 let Inst{3-0} = opt;
2001 // Supervisor Call (Software Interrupt)
2002 let isCall = 1, Uses = [SP] in {
2003 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2005 let Inst{23-0} = svc;
2009 // Store Return State
2010 class SRSI<bit wb, string asm>
2011 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2012 NoItinerary, asm, "", []> {
2014 let Inst{31-28} = 0b1111;
2015 let Inst{27-25} = 0b100;
2019 let Inst{19-16} = 0b1101; // SP
2020 let Inst{15-5} = 0b00000101000;
2021 let Inst{4-0} = mode;
2024 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2025 let Inst{24-23} = 0;
2027 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2028 let Inst{24-23} = 0;
2030 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2031 let Inst{24-23} = 0b10;
2033 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2034 let Inst{24-23} = 0b10;
2036 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2037 let Inst{24-23} = 0b01;
2039 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2040 let Inst{24-23} = 0b01;
2042 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2043 let Inst{24-23} = 0b11;
2045 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2046 let Inst{24-23} = 0b11;
2049 // Return From Exception
2050 class RFEI<bit wb, string asm>
2051 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2052 NoItinerary, asm, "", []> {
2054 let Inst{31-28} = 0b1111;
2055 let Inst{27-25} = 0b100;
2059 let Inst{19-16} = Rn;
2060 let Inst{15-0} = 0xa00;
2063 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2064 let Inst{24-23} = 0;
2066 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2067 let Inst{24-23} = 0;
2069 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2070 let Inst{24-23} = 0b10;
2072 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2073 let Inst{24-23} = 0b10;
2075 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2076 let Inst{24-23} = 0b01;
2078 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2079 let Inst{24-23} = 0b01;
2081 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2082 let Inst{24-23} = 0b11;
2084 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2085 let Inst{24-23} = 0b11;
2088 //===----------------------------------------------------------------------===//
2089 // Load / Store Instructions.
2095 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2096 UnOpFrag<(load node:$Src)>>;
2097 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2098 UnOpFrag<(zextloadi8 node:$Src)>>;
2099 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2100 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2101 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2102 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2104 // Special LDR for loads from non-pc-relative constpools.
2105 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2106 isReMaterializable = 1, isCodeGenOnly = 1 in
2107 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2108 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2112 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2113 let Inst{19-16} = 0b1111;
2114 let Inst{15-12} = Rt;
2115 let Inst{11-0} = addr{11-0}; // imm12
2118 // Loads with zero extension
2119 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2120 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2121 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2123 // Loads with sign extension
2124 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2125 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2126 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2128 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2129 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2130 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2132 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2134 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2135 (ins addrmode3:$addr), LdMiscFrm,
2136 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2137 []>, Requires<[IsARM, HasV5TE]>;
2141 multiclass AI2_ldridx<bit isByte, string opc,
2142 InstrItinClass iii, InstrItinClass iir> {
2143 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2144 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2145 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2148 let Inst{23} = addr{12};
2149 let Inst{19-16} = addr{16-13};
2150 let Inst{11-0} = addr{11-0};
2151 let DecoderMethod = "DecodeLDRPreImm";
2152 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2155 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2156 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2157 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2160 let Inst{23} = addr{12};
2161 let Inst{19-16} = addr{16-13};
2162 let Inst{11-0} = addr{11-0};
2164 let DecoderMethod = "DecodeLDRPreReg";
2165 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2168 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2169 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2170 IndexModePost, LdFrm, iir,
2171 opc, "\t$Rt, $addr, $offset",
2172 "$addr.base = $Rn_wb", []> {
2178 let Inst{23} = offset{12};
2179 let Inst{19-16} = addr;
2180 let Inst{11-0} = offset{11-0};
2182 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2185 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2186 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2187 IndexModePost, LdFrm, iii,
2188 opc, "\t$Rt, $addr, $offset",
2189 "$addr.base = $Rn_wb", []> {
2195 let Inst{23} = offset{12};
2196 let Inst{19-16} = addr;
2197 let Inst{11-0} = offset{11-0};
2199 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2204 let mayLoad = 1, neverHasSideEffects = 1 in {
2205 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2206 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2207 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2208 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2211 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2212 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2213 (ins addrmode3:$addr), IndexModePre,
2215 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2217 let Inst{23} = addr{8}; // U bit
2218 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2219 let Inst{19-16} = addr{12-9}; // Rn
2220 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2221 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2222 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2223 let DecoderMethod = "DecodeAddrMode3Instruction";
2225 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2226 (ins addr_offset_none:$addr, am3offset:$offset),
2227 IndexModePost, LdMiscFrm, itin,
2228 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2232 let Inst{23} = offset{8}; // U bit
2233 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2234 let Inst{19-16} = addr;
2235 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2236 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2237 let DecoderMethod = "DecodeAddrMode3Instruction";
2241 let mayLoad = 1, neverHasSideEffects = 1 in {
2242 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2243 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2244 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2245 let hasExtraDefRegAllocReq = 1 in {
2246 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2247 (ins addrmode3:$addr), IndexModePre,
2248 LdMiscFrm, IIC_iLoad_d_ru,
2249 "ldrd", "\t$Rt, $Rt2, $addr!",
2250 "$addr.base = $Rn_wb", []> {
2252 let Inst{23} = addr{8}; // U bit
2253 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2254 let Inst{19-16} = addr{12-9}; // Rn
2255 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2256 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2257 let DecoderMethod = "DecodeAddrMode3Instruction";
2258 let AsmMatchConverter = "cvtLdrdPre";
2260 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2261 (ins addr_offset_none:$addr, am3offset:$offset),
2262 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2263 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2264 "$addr.base = $Rn_wb", []> {
2267 let Inst{23} = offset{8}; // U bit
2268 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2269 let Inst{19-16} = addr;
2270 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2271 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2272 let DecoderMethod = "DecodeAddrMode3Instruction";
2274 } // hasExtraDefRegAllocReq = 1
2275 } // mayLoad = 1, neverHasSideEffects = 1
2277 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2278 let mayLoad = 1, neverHasSideEffects = 1 in {
2279 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2280 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2281 IndexModePost, LdFrm, IIC_iLoad_ru,
2282 "ldrt", "\t$Rt, $addr, $offset",
2283 "$addr.base = $Rn_wb", []> {
2289 let Inst{23} = offset{12};
2290 let Inst{21} = 1; // overwrite
2291 let Inst{19-16} = addr;
2292 let Inst{11-5} = offset{11-5};
2294 let Inst{3-0} = offset{3-0};
2295 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2298 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2299 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2300 IndexModePost, LdFrm, IIC_iLoad_ru,
2301 "ldrt", "\t$Rt, $addr, $offset",
2302 "$addr.base = $Rn_wb", []> {
2308 let Inst{23} = offset{12};
2309 let Inst{21} = 1; // overwrite
2310 let Inst{19-16} = addr;
2311 let Inst{11-0} = offset{11-0};
2312 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2315 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2316 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2317 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2318 "ldrbt", "\t$Rt, $addr, $offset",
2319 "$addr.base = $Rn_wb", []> {
2325 let Inst{23} = offset{12};
2326 let Inst{21} = 1; // overwrite
2327 let Inst{19-16} = addr;
2328 let Inst{11-5} = offset{11-5};
2330 let Inst{3-0} = offset{3-0};
2331 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2334 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2335 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2336 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2337 "ldrbt", "\t$Rt, $addr, $offset",
2338 "$addr.base = $Rn_wb", []> {
2344 let Inst{23} = offset{12};
2345 let Inst{21} = 1; // overwrite
2346 let Inst{19-16} = addr;
2347 let Inst{11-0} = offset{11-0};
2348 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2351 multiclass AI3ldrT<bits<4> op, string opc> {
2352 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2353 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2354 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2355 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2357 let Inst{23} = offset{8};
2359 let Inst{11-8} = offset{7-4};
2360 let Inst{3-0} = offset{3-0};
2361 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2363 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2364 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2365 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2366 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2368 let Inst{23} = Rm{4};
2371 let Unpredictable{11-8} = 0b1111;
2372 let Inst{3-0} = Rm{3-0};
2373 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2374 let DecoderMethod = "DecodeLDR";
2378 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2379 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2380 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2385 // Stores with truncate
2386 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2387 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2388 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2391 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2392 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2393 StMiscFrm, IIC_iStore_d_r,
2394 "strd", "\t$Rt, $src2, $addr", []>,
2395 Requires<[IsARM, HasV5TE]> {
2400 multiclass AI2_stridx<bit isByte, string opc,
2401 InstrItinClass iii, InstrItinClass iir> {
2402 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2403 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2405 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2408 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2409 let Inst{19-16} = addr{16-13}; // Rn
2410 let Inst{11-0} = addr{11-0}; // imm12
2411 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2412 let DecoderMethod = "DecodeSTRPreImm";
2415 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2416 (ins GPR:$Rt, ldst_so_reg:$addr),
2417 IndexModePre, StFrm, iir,
2418 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2421 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2422 let Inst{19-16} = addr{16-13}; // Rn
2423 let Inst{11-0} = addr{11-0};
2424 let Inst{4} = 0; // Inst{4} = 0
2425 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2426 let DecoderMethod = "DecodeSTRPreReg";
2428 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2429 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2430 IndexModePost, StFrm, iir,
2431 opc, "\t$Rt, $addr, $offset",
2432 "$addr.base = $Rn_wb", []> {
2438 let Inst{23} = offset{12};
2439 let Inst{19-16} = addr;
2440 let Inst{11-0} = offset{11-0};
2443 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2446 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2447 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2448 IndexModePost, StFrm, iii,
2449 opc, "\t$Rt, $addr, $offset",
2450 "$addr.base = $Rn_wb", []> {
2456 let Inst{23} = offset{12};
2457 let Inst{19-16} = addr;
2458 let Inst{11-0} = offset{11-0};
2460 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2464 let mayStore = 1, neverHasSideEffects = 1 in {
2465 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2466 // IIC_iStore_siu depending on whether it the offset register is shifted.
2467 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2468 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2471 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2472 am2offset_reg:$offset),
2473 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2474 am2offset_reg:$offset)>;
2475 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2476 am2offset_imm:$offset),
2477 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2478 am2offset_imm:$offset)>;
2479 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2480 am2offset_reg:$offset),
2481 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2482 am2offset_reg:$offset)>;
2483 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2484 am2offset_imm:$offset),
2485 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2486 am2offset_imm:$offset)>;
2488 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2489 // put the patterns on the instruction definitions directly as ISel wants
2490 // the address base and offset to be separate operands, not a single
2491 // complex operand like we represent the instructions themselves. The
2492 // pseudos map between the two.
2493 let usesCustomInserter = 1,
2494 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2495 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2496 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2499 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2500 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2501 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2504 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2505 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2506 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2509 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2510 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2511 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2514 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2515 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2516 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2519 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2524 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2525 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2526 StMiscFrm, IIC_iStore_bh_ru,
2527 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2529 let Inst{23} = addr{8}; // U bit
2530 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2531 let Inst{19-16} = addr{12-9}; // Rn
2532 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2533 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2534 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2535 let DecoderMethod = "DecodeAddrMode3Instruction";
2538 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2539 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2540 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2541 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2542 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2543 addr_offset_none:$addr,
2544 am3offset:$offset))]> {
2547 let Inst{23} = offset{8}; // U bit
2548 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2549 let Inst{19-16} = addr;
2550 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2551 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2552 let DecoderMethod = "DecodeAddrMode3Instruction";
2555 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2556 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2557 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2558 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2559 "strd", "\t$Rt, $Rt2, $addr!",
2560 "$addr.base = $Rn_wb", []> {
2562 let Inst{23} = addr{8}; // U bit
2563 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2564 let Inst{19-16} = addr{12-9}; // Rn
2565 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2566 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2567 let DecoderMethod = "DecodeAddrMode3Instruction";
2568 let AsmMatchConverter = "cvtStrdPre";
2571 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2574 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2575 "strd", "\t$Rt, $Rt2, $addr, $offset",
2576 "$addr.base = $Rn_wb", []> {
2579 let Inst{23} = offset{8}; // U bit
2580 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2581 let Inst{19-16} = addr;
2582 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2583 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2584 let DecoderMethod = "DecodeAddrMode3Instruction";
2586 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2588 // STRT, STRBT, and STRHT
2590 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2591 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2592 IndexModePost, StFrm, IIC_iStore_bh_ru,
2593 "strbt", "\t$Rt, $addr, $offset",
2594 "$addr.base = $Rn_wb", []> {
2600 let Inst{23} = offset{12};
2601 let Inst{21} = 1; // overwrite
2602 let Inst{19-16} = addr;
2603 let Inst{11-5} = offset{11-5};
2605 let Inst{3-0} = offset{3-0};
2606 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2609 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2610 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2611 IndexModePost, StFrm, IIC_iStore_bh_ru,
2612 "strbt", "\t$Rt, $addr, $offset",
2613 "$addr.base = $Rn_wb", []> {
2619 let Inst{23} = offset{12};
2620 let Inst{21} = 1; // overwrite
2621 let Inst{19-16} = addr;
2622 let Inst{11-0} = offset{11-0};
2623 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2626 let mayStore = 1, neverHasSideEffects = 1 in {
2627 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2628 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2629 IndexModePost, StFrm, IIC_iStore_ru,
2630 "strt", "\t$Rt, $addr, $offset",
2631 "$addr.base = $Rn_wb", []> {
2637 let Inst{23} = offset{12};
2638 let Inst{21} = 1; // overwrite
2639 let Inst{19-16} = addr;
2640 let Inst{11-5} = offset{11-5};
2642 let Inst{3-0} = offset{3-0};
2643 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2646 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2647 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2648 IndexModePost, StFrm, IIC_iStore_ru,
2649 "strt", "\t$Rt, $addr, $offset",
2650 "$addr.base = $Rn_wb", []> {
2656 let Inst{23} = offset{12};
2657 let Inst{21} = 1; // overwrite
2658 let Inst{19-16} = addr;
2659 let Inst{11-0} = offset{11-0};
2660 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2665 multiclass AI3strT<bits<4> op, string opc> {
2666 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2667 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2668 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2669 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2671 let Inst{23} = offset{8};
2673 let Inst{11-8} = offset{7-4};
2674 let Inst{3-0} = offset{3-0};
2675 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2677 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2678 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2679 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2680 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2682 let Inst{23} = Rm{4};
2685 let Inst{3-0} = Rm{3-0};
2686 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2691 defm STRHT : AI3strT<0b1011, "strht">;
2694 //===----------------------------------------------------------------------===//
2695 // Load / store multiple Instructions.
2698 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2699 InstrItinClass itin, InstrItinClass itin_upd> {
2700 // IA is the default, so no need for an explicit suffix on the
2701 // mnemonic here. Without it is the canonical spelling.
2703 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2704 IndexModeNone, f, itin,
2705 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2706 let Inst{24-23} = 0b01; // Increment After
2707 let Inst{22} = P_bit;
2708 let Inst{21} = 0; // No writeback
2709 let Inst{20} = L_bit;
2712 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2713 IndexModeUpd, f, itin_upd,
2714 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2715 let Inst{24-23} = 0b01; // Increment After
2716 let Inst{22} = P_bit;
2717 let Inst{21} = 1; // Writeback
2718 let Inst{20} = L_bit;
2720 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2723 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2724 IndexModeNone, f, itin,
2725 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2726 let Inst{24-23} = 0b00; // Decrement After
2727 let Inst{22} = P_bit;
2728 let Inst{21} = 0; // No writeback
2729 let Inst{20} = L_bit;
2732 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2733 IndexModeUpd, f, itin_upd,
2734 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2735 let Inst{24-23} = 0b00; // Decrement After
2736 let Inst{22} = P_bit;
2737 let Inst{21} = 1; // Writeback
2738 let Inst{20} = L_bit;
2740 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2743 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2744 IndexModeNone, f, itin,
2745 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2746 let Inst{24-23} = 0b10; // Decrement Before
2747 let Inst{22} = P_bit;
2748 let Inst{21} = 0; // No writeback
2749 let Inst{20} = L_bit;
2752 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2753 IndexModeUpd, f, itin_upd,
2754 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2755 let Inst{24-23} = 0b10; // Decrement Before
2756 let Inst{22} = P_bit;
2757 let Inst{21} = 1; // Writeback
2758 let Inst{20} = L_bit;
2760 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2763 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2764 IndexModeNone, f, itin,
2765 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2766 let Inst{24-23} = 0b11; // Increment Before
2767 let Inst{22} = P_bit;
2768 let Inst{21} = 0; // No writeback
2769 let Inst{20} = L_bit;
2772 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2773 IndexModeUpd, f, itin_upd,
2774 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2775 let Inst{24-23} = 0b11; // Increment Before
2776 let Inst{22} = P_bit;
2777 let Inst{21} = 1; // Writeback
2778 let Inst{20} = L_bit;
2780 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2784 let neverHasSideEffects = 1 in {
2786 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2787 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2790 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2791 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2794 } // neverHasSideEffects
2796 // FIXME: remove when we have a way to marking a MI with these properties.
2797 // FIXME: Should pc be an implicit operand like PICADD, etc?
2798 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2799 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2800 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2801 reglist:$regs, variable_ops),
2802 4, IIC_iLoad_mBr, [],
2803 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2804 RegConstraint<"$Rn = $wb">;
2806 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2807 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2810 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2811 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2816 //===----------------------------------------------------------------------===//
2817 // Move Instructions.
2820 let neverHasSideEffects = 1 in
2821 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2822 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2826 let Inst{19-16} = 0b0000;
2827 let Inst{11-4} = 0b00000000;
2830 let Inst{15-12} = Rd;
2833 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2834 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2836 // A version for the smaller set of tail call registers.
2837 let neverHasSideEffects = 1 in
2838 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2839 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2843 let Inst{11-4} = 0b00000000;
2846 let Inst{15-12} = Rd;
2849 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2850 DPSoRegRegFrm, IIC_iMOVsr,
2851 "mov", "\t$Rd, $src",
2852 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2855 let Inst{15-12} = Rd;
2856 let Inst{19-16} = 0b0000;
2857 let Inst{11-8} = src{11-8};
2859 let Inst{6-5} = src{6-5};
2861 let Inst{3-0} = src{3-0};
2865 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2866 DPSoRegImmFrm, IIC_iMOVsr,
2867 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2871 let Inst{15-12} = Rd;
2872 let Inst{19-16} = 0b0000;
2873 let Inst{11-5} = src{11-5};
2875 let Inst{3-0} = src{3-0};
2879 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2880 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2881 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2885 let Inst{15-12} = Rd;
2886 let Inst{19-16} = 0b0000;
2887 let Inst{11-0} = imm;
2890 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2891 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2893 "movw", "\t$Rd, $imm",
2894 [(set GPR:$Rd, imm0_65535:$imm)]>,
2895 Requires<[IsARM, HasV6T2]>, UnaryDP {
2898 let Inst{15-12} = Rd;
2899 let Inst{11-0} = imm{11-0};
2900 let Inst{19-16} = imm{15-12};
2903 let DecoderMethod = "DecodeArmMOVTWInstruction";
2906 def : InstAlias<"mov${p} $Rd, $imm",
2907 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2910 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2911 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2913 let Constraints = "$src = $Rd" in {
2914 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2915 (ins GPR:$src, imm0_65535_expr:$imm),
2917 "movt", "\t$Rd, $imm",
2919 (or (and GPR:$src, 0xffff),
2920 lo16AllZero:$imm))]>, UnaryDP,
2921 Requires<[IsARM, HasV6T2]> {
2924 let Inst{15-12} = Rd;
2925 let Inst{11-0} = imm{11-0};
2926 let Inst{19-16} = imm{15-12};
2929 let DecoderMethod = "DecodeArmMOVTWInstruction";
2932 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2933 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2937 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2938 Requires<[IsARM, HasV6T2]>;
2940 let Uses = [CPSR] in
2941 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2942 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2945 // These aren't really mov instructions, but we have to define them this way
2946 // due to flag operands.
2948 let Defs = [CPSR] in {
2949 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2950 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2952 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2953 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2957 //===----------------------------------------------------------------------===//
2958 // Extend Instructions.
2963 def SXTB : AI_ext_rrot<0b01101010,
2964 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2965 def SXTH : AI_ext_rrot<0b01101011,
2966 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2968 def SXTAB : AI_exta_rrot<0b01101010,
2969 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2970 def SXTAH : AI_exta_rrot<0b01101011,
2971 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2973 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2975 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2979 let AddedComplexity = 16 in {
2980 def UXTB : AI_ext_rrot<0b01101110,
2981 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2982 def UXTH : AI_ext_rrot<0b01101111,
2983 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2984 def UXTB16 : AI_ext_rrot<0b01101100,
2985 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2987 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2988 // The transformation should probably be done as a combiner action
2989 // instead so we can include a check for masking back in the upper
2990 // eight bits of the source into the lower eight bits of the result.
2991 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2992 // (UXTB16r_rot GPR:$Src, 3)>;
2993 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2994 (UXTB16 GPR:$Src, 1)>;
2996 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2997 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2998 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2999 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3002 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3003 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3006 def SBFX : I<(outs GPRnopc:$Rd),
3007 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3008 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3009 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3010 Requires<[IsARM, HasV6T2]> {
3015 let Inst{27-21} = 0b0111101;
3016 let Inst{6-4} = 0b101;
3017 let Inst{20-16} = width;
3018 let Inst{15-12} = Rd;
3019 let Inst{11-7} = lsb;
3023 def UBFX : I<(outs GPR:$Rd),
3024 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3025 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3026 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3027 Requires<[IsARM, HasV6T2]> {
3032 let Inst{27-21} = 0b0111111;
3033 let Inst{6-4} = 0b101;
3034 let Inst{20-16} = width;
3035 let Inst{15-12} = Rd;
3036 let Inst{11-7} = lsb;
3040 //===----------------------------------------------------------------------===//
3041 // Arithmetic Instructions.
3044 defm ADD : AsI1_bin_irs<0b0100, "add",
3045 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3046 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3047 defm SUB : AsI1_bin_irs<0b0010, "sub",
3048 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3049 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3051 // ADD and SUB with 's' bit set.
3053 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3054 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3055 // AdjustInstrPostInstrSelection where we determine whether or not to
3056 // set the "s" bit based on CPSR liveness.
3058 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3059 // support for an optional CPSR definition that corresponds to the DAG
3060 // node's second value. We can then eliminate the implicit def of CPSR.
3061 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3062 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3063 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3064 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3066 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3067 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3069 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3070 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3073 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3074 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3075 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3077 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3078 // CPSR and the implicit def of CPSR is not needed.
3079 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3080 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3082 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3083 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3086 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3087 // The assume-no-carry-in form uses the negation of the input since add/sub
3088 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3089 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3091 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3092 (SUBri GPR:$src, so_imm_neg:$imm)>;
3093 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3094 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3096 // The with-carry-in form matches bitwise not instead of the negation.
3097 // Effectively, the inverse interpretation of the carry flag already accounts
3098 // for part of the negation.
3099 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3100 (SBCri GPR:$src, so_imm_not:$imm)>;
3102 // Note: These are implemented in C++ code, because they have to generate
3103 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3105 // (mul X, 2^n+1) -> (add (X << n), X)
3106 // (mul X, 2^n-1) -> (rsb X, (X << n))
3108 // ARM Arithmetic Instruction
3109 // GPR:$dst = GPR:$a op GPR:$b
3110 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3111 list<dag> pattern = [],
3112 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3113 string asm = "\t$Rd, $Rn, $Rm">
3114 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3118 let Inst{27-20} = op27_20;
3119 let Inst{11-4} = op11_4;
3120 let Inst{19-16} = Rn;
3121 let Inst{15-12} = Rd;
3124 let Unpredictable{11-8} = 0b1111;
3127 // Saturating add/subtract
3129 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3130 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3131 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3132 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3133 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3134 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3135 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3136 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3138 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3139 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3142 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3143 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3144 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3145 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3146 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3147 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3148 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3149 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3150 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3151 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3152 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3153 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3155 // Signed/Unsigned add/subtract
3157 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3158 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3159 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3160 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3161 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3162 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3163 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3164 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3165 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3166 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3167 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3168 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3170 // Signed/Unsigned halving add/subtract
3172 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3173 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3174 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3175 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3176 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3177 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3178 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3179 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3180 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3181 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3182 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3183 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3185 // Unsigned Sum of Absolute Differences [and Accumulate].
3187 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3188 MulFrm /* for convenience */, NoItinerary, "usad8",
3189 "\t$Rd, $Rn, $Rm", []>,
3190 Requires<[IsARM, HasV6]> {
3194 let Inst{27-20} = 0b01111000;
3195 let Inst{15-12} = 0b1111;
3196 let Inst{7-4} = 0b0001;
3197 let Inst{19-16} = Rd;
3198 let Inst{11-8} = Rm;
3201 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3202 MulFrm /* for convenience */, NoItinerary, "usada8",
3203 "\t$Rd, $Rn, $Rm, $Ra", []>,
3204 Requires<[IsARM, HasV6]> {
3209 let Inst{27-20} = 0b01111000;
3210 let Inst{7-4} = 0b0001;
3211 let Inst{19-16} = Rd;
3212 let Inst{15-12} = Ra;
3213 let Inst{11-8} = Rm;
3217 // Signed/Unsigned saturate
3219 def SSAT : AI<(outs GPRnopc:$Rd),
3220 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3221 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3226 let Inst{27-21} = 0b0110101;
3227 let Inst{5-4} = 0b01;
3228 let Inst{20-16} = sat_imm;
3229 let Inst{15-12} = Rd;
3230 let Inst{11-7} = sh{4-0};
3231 let Inst{6} = sh{5};
3235 def SSAT16 : AI<(outs GPRnopc:$Rd),
3236 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3237 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3241 let Inst{27-20} = 0b01101010;
3242 let Inst{11-4} = 0b11110011;
3243 let Inst{15-12} = Rd;
3244 let Inst{19-16} = sat_imm;
3248 def USAT : AI<(outs GPRnopc:$Rd),
3249 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3250 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3255 let Inst{27-21} = 0b0110111;
3256 let Inst{5-4} = 0b01;
3257 let Inst{15-12} = Rd;
3258 let Inst{11-7} = sh{4-0};
3259 let Inst{6} = sh{5};
3260 let Inst{20-16} = sat_imm;
3264 def USAT16 : AI<(outs GPRnopc:$Rd),
3265 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3266 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3270 let Inst{27-20} = 0b01101110;
3271 let Inst{11-4} = 0b11110011;
3272 let Inst{15-12} = Rd;
3273 let Inst{19-16} = sat_imm;
3277 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3278 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3279 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3280 (USAT imm:$pos, GPRnopc:$a, 0)>;
3282 //===----------------------------------------------------------------------===//
3283 // Bitwise Instructions.
3286 defm AND : AsI1_bin_irs<0b0000, "and",
3287 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3288 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3289 defm ORR : AsI1_bin_irs<0b1100, "orr",
3290 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3291 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3292 defm EOR : AsI1_bin_irs<0b0001, "eor",
3293 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3294 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3295 defm BIC : AsI1_bin_irs<0b1110, "bic",
3296 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3297 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3299 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3300 // like in the actual instruction encoding. The complexity of mapping the mask
3301 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3302 // instruction description.
3303 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3304 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3305 "bfc", "\t$Rd, $imm", "$src = $Rd",
3306 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3307 Requires<[IsARM, HasV6T2]> {
3310 let Inst{27-21} = 0b0111110;
3311 let Inst{6-0} = 0b0011111;
3312 let Inst{15-12} = Rd;
3313 let Inst{11-7} = imm{4-0}; // lsb
3314 let Inst{20-16} = imm{9-5}; // msb
3317 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3318 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3319 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3320 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3321 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3322 bf_inv_mask_imm:$imm))]>,
3323 Requires<[IsARM, HasV6T2]> {
3327 let Inst{27-21} = 0b0111110;
3328 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3329 let Inst{15-12} = Rd;
3330 let Inst{11-7} = imm{4-0}; // lsb
3331 let Inst{20-16} = imm{9-5}; // width
3335 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3336 "mvn", "\t$Rd, $Rm",
3337 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3341 let Inst{19-16} = 0b0000;
3342 let Inst{11-4} = 0b00000000;
3343 let Inst{15-12} = Rd;
3346 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3347 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3348 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3352 let Inst{19-16} = 0b0000;
3353 let Inst{15-12} = Rd;
3354 let Inst{11-5} = shift{11-5};
3356 let Inst{3-0} = shift{3-0};
3358 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3359 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3360 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3364 let Inst{19-16} = 0b0000;
3365 let Inst{15-12} = Rd;
3366 let Inst{11-8} = shift{11-8};
3368 let Inst{6-5} = shift{6-5};
3370 let Inst{3-0} = shift{3-0};
3372 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3373 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3374 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3375 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3379 let Inst{19-16} = 0b0000;
3380 let Inst{15-12} = Rd;
3381 let Inst{11-0} = imm;
3384 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3385 (BICri GPR:$src, so_imm_not:$imm)>;
3387 //===----------------------------------------------------------------------===//
3388 // Multiply Instructions.
3390 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3391 string opc, string asm, list<dag> pattern>
3392 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3396 let Inst{19-16} = Rd;
3397 let Inst{11-8} = Rm;
3400 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3401 string opc, string asm, list<dag> pattern>
3402 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3407 let Inst{19-16} = RdHi;
3408 let Inst{15-12} = RdLo;
3409 let Inst{11-8} = Rm;
3413 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3414 // property. Remove them when it's possible to add those properties
3415 // on an individual MachineInstr, not just an instruction description.
3416 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3417 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3418 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3419 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3420 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3421 Requires<[IsARM, HasV6]> {
3422 let Inst{15-12} = 0b0000;
3423 let Unpredictable{15-12} = 0b1111;
3426 let Constraints = "@earlyclobber $Rd" in
3427 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3428 pred:$p, cc_out:$s),
3430 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3431 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3432 Requires<[IsARM, NoV6]>;
3435 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3436 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3437 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3438 Requires<[IsARM, HasV6]> {
3440 let Inst{15-12} = Ra;
3443 let Constraints = "@earlyclobber $Rd" in
3444 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3445 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3447 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3448 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3449 Requires<[IsARM, NoV6]>;
3451 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3452 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3453 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3454 Requires<[IsARM, HasV6T2]> {
3459 let Inst{19-16} = Rd;
3460 let Inst{15-12} = Ra;
3461 let Inst{11-8} = Rm;
3465 // Extra precision multiplies with low / high results
3466 let neverHasSideEffects = 1 in {
3467 let isCommutable = 1 in {
3468 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3469 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3470 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3471 Requires<[IsARM, HasV6]>;
3473 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3474 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3475 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3476 Requires<[IsARM, HasV6]>;
3478 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3479 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3480 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3482 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3483 Requires<[IsARM, NoV6]>;
3485 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3486 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3488 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3489 Requires<[IsARM, NoV6]>;
3493 // Multiply + accumulate
3494 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3495 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3496 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3497 Requires<[IsARM, HasV6]>;
3498 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3499 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3500 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3501 Requires<[IsARM, HasV6]>;
3503 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3504 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3505 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3506 Requires<[IsARM, HasV6]> {
3511 let Inst{19-16} = RdHi;
3512 let Inst{15-12} = RdLo;
3513 let Inst{11-8} = Rm;
3517 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3518 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3519 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3521 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3522 Requires<[IsARM, NoV6]>;
3523 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3524 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3526 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3527 Requires<[IsARM, NoV6]>;
3528 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3529 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3531 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3532 Requires<[IsARM, NoV6]>;
3535 } // neverHasSideEffects
3537 // Most significant word multiply
3538 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3539 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3540 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3541 Requires<[IsARM, HasV6]> {
3542 let Inst{15-12} = 0b1111;
3545 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3546 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3547 Requires<[IsARM, HasV6]> {
3548 let Inst{15-12} = 0b1111;
3551 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3552 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3553 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3554 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3555 Requires<[IsARM, HasV6]>;
3557 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3558 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3559 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3560 Requires<[IsARM, HasV6]>;
3562 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3563 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3564 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3565 Requires<[IsARM, HasV6]>;
3567 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3568 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3569 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3570 Requires<[IsARM, HasV6]>;
3572 multiclass AI_smul<string opc, PatFrag opnode> {
3573 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3574 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3575 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3576 (sext_inreg GPR:$Rm, i16)))]>,
3577 Requires<[IsARM, HasV5TE]>;
3579 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3580 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3581 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3582 (sra GPR:$Rm, (i32 16))))]>,
3583 Requires<[IsARM, HasV5TE]>;
3585 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3586 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3587 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3588 (sext_inreg GPR:$Rm, i16)))]>,
3589 Requires<[IsARM, HasV5TE]>;
3591 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3592 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3593 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3594 (sra GPR:$Rm, (i32 16))))]>,
3595 Requires<[IsARM, HasV5TE]>;
3597 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3598 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3599 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3600 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3601 Requires<[IsARM, HasV5TE]>;
3603 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3604 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3605 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3606 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3607 Requires<[IsARM, HasV5TE]>;
3611 multiclass AI_smla<string opc, PatFrag opnode> {
3612 let DecoderMethod = "DecodeSMLAInstruction" in {
3613 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3614 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3615 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3616 [(set GPRnopc:$Rd, (add GPR:$Ra,
3617 (opnode (sext_inreg GPRnopc:$Rn, i16),
3618 (sext_inreg GPRnopc:$Rm, i16))))]>,
3619 Requires<[IsARM, HasV5TE]>;
3621 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3622 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3623 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3625 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3626 (sra GPRnopc:$Rm, (i32 16)))))]>,
3627 Requires<[IsARM, HasV5TE]>;
3629 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3630 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3631 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3633 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3634 (sext_inreg GPRnopc:$Rm, i16))))]>,
3635 Requires<[IsARM, HasV5TE]>;
3637 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3638 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3639 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3641 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3642 (sra GPRnopc:$Rm, (i32 16)))))]>,
3643 Requires<[IsARM, HasV5TE]>;
3645 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3646 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3647 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3649 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3650 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3651 Requires<[IsARM, HasV5TE]>;
3653 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3654 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3655 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3657 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3658 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3659 Requires<[IsARM, HasV5TE]>;
3663 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3664 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3666 // Halfword multiply accumulate long: SMLAL<x><y>.
3667 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3668 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3669 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3670 Requires<[IsARM, HasV5TE]>;
3672 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3673 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3674 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3675 Requires<[IsARM, HasV5TE]>;
3677 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3678 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3679 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3680 Requires<[IsARM, HasV5TE]>;
3682 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3683 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3684 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3685 Requires<[IsARM, HasV5TE]>;
3687 // Helper class for AI_smld.
3688 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3689 InstrItinClass itin, string opc, string asm>
3690 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3693 let Inst{27-23} = 0b01110;
3694 let Inst{22} = long;
3695 let Inst{21-20} = 0b00;
3696 let Inst{11-8} = Rm;
3703 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3704 InstrItinClass itin, string opc, string asm>
3705 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3707 let Inst{15-12} = 0b1111;
3708 let Inst{19-16} = Rd;
3710 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3711 InstrItinClass itin, string opc, string asm>
3712 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3715 let Inst{19-16} = Rd;
3716 let Inst{15-12} = Ra;
3718 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3719 InstrItinClass itin, string opc, string asm>
3720 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3723 let Inst{19-16} = RdHi;
3724 let Inst{15-12} = RdLo;
3727 multiclass AI_smld<bit sub, string opc> {
3729 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3730 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3731 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3733 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3734 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3735 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3737 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3738 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3739 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3741 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3742 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3743 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3747 defm SMLA : AI_smld<0, "smla">;
3748 defm SMLS : AI_smld<1, "smls">;
3750 multiclass AI_sdml<bit sub, string opc> {
3752 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3753 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3754 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3755 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3758 defm SMUA : AI_sdml<0, "smua">;
3759 defm SMUS : AI_sdml<1, "smus">;
3761 //===----------------------------------------------------------------------===//
3762 // Misc. Arithmetic Instructions.
3765 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3766 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3767 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3769 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3770 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3771 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3772 Requires<[IsARM, HasV6T2]>;
3774 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3775 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3776 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3778 let AddedComplexity = 5 in
3779 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3780 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3781 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3782 Requires<[IsARM, HasV6]>;
3784 let AddedComplexity = 5 in
3785 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3786 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3787 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3788 Requires<[IsARM, HasV6]>;
3790 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3791 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3794 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3796 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3797 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3798 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3800 Requires<[IsARM, HasV6]>;
3802 // Alternate cases for PKHBT where identities eliminate some nodes.
3803 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3804 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3805 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3806 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3808 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3809 // will match the pattern below.
3810 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3811 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3812 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3813 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3814 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3816 Requires<[IsARM, HasV6]>;
3818 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3819 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3820 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3821 (srl GPRnopc:$src2, imm16_31:$sh)),
3822 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3823 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3824 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3825 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3827 //===----------------------------------------------------------------------===//
3828 // Comparison Instructions...
3831 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3832 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3833 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3835 // ARMcmpZ can re-use the above instruction definitions.
3836 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3837 (CMPri GPR:$src, so_imm:$imm)>;
3838 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3839 (CMPrr GPR:$src, GPR:$rhs)>;
3840 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3841 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3842 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3843 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3845 // FIXME: We have to be careful when using the CMN instruction and comparison
3846 // with 0. One would expect these two pieces of code should give identical
3862 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3863 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3864 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3865 // value of r0 and the carry bit (because the "carry bit" parameter to
3866 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3867 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3868 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3869 // parameter to AddWithCarry is defined as 0).
3871 // When x is 0 and unsigned:
3875 // ~x + 1 = 0x1 0000 0000
3876 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3878 // Therefore, we should disable CMN when comparing against zero, until we can
3879 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3880 // when it's a comparison which doesn't look at the 'carry' flag).
3882 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3884 // This is related to <rdar://problem/7569620>.
3886 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3887 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3889 // Note that TST/TEQ don't set all the same flags that CMP does!
3890 defm TST : AI1_cmp_irs<0b1000, "tst",
3891 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3892 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3893 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3894 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3895 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3897 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3898 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3899 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3901 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3902 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3904 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3905 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3907 // Pseudo i64 compares for some floating point compares.
3908 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3910 def BCCi64 : PseudoInst<(outs),
3911 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3913 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3915 def BCCZi64 : PseudoInst<(outs),
3916 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3917 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3918 } // usesCustomInserter
3921 // Conditional moves
3922 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3923 // a two-value operand where a dag node expects two operands. :(
3924 let neverHasSideEffects = 1 in {
3926 let isCommutable = 1 in
3927 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3929 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3930 RegConstraint<"$false = $Rd">;
3932 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3933 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3935 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3936 imm:$cc, CCR:$ccr))*/]>,
3937 RegConstraint<"$false = $Rd">;
3938 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3939 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3941 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3942 imm:$cc, CCR:$ccr))*/]>,
3943 RegConstraint<"$false = $Rd">;
3946 let isMoveImm = 1 in
3947 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3948 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3951 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3953 let isMoveImm = 1 in
3954 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3955 (ins GPR:$false, so_imm:$imm, pred:$p),
3957 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3958 RegConstraint<"$false = $Rd">;
3960 // Two instruction predicate mov immediate.
3961 let isMoveImm = 1 in
3962 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3963 (ins GPR:$false, i32imm:$src, pred:$p),
3964 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3966 let isMoveImm = 1 in
3967 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3968 (ins GPR:$false, so_imm:$imm, pred:$p),
3970 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3971 RegConstraint<"$false = $Rd">;
3973 // Conditional instructions
3974 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3976 InstrItinClass iii, InstrItinClass iir,
3977 InstrItinClass iis> {
3978 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3979 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
3981 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
3982 RegConstraint<"$Rn = $Rd">;
3983 def rr : ARMPseudoExpand<(outs GPR:$Rd),
3984 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3986 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3987 RegConstraint<"$Rn = $Rd">;
3988 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
3989 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
3991 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
3992 RegConstraint<"$Rn = $Rd">;
3993 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
3994 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
3996 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
3997 RegConstraint<"$Rn = $Rd">;
4000 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4001 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4002 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4003 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4004 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4005 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4007 } // neverHasSideEffects
4010 //===----------------------------------------------------------------------===//
4011 // Atomic operations intrinsics
4014 def MemBarrierOptOperand : AsmOperandClass {
4015 let Name = "MemBarrierOpt";
4016 let ParserMethod = "parseMemBarrierOptOperand";
4018 def memb_opt : Operand<i32> {
4019 let PrintMethod = "printMemBOption";
4020 let ParserMatchClass = MemBarrierOptOperand;
4021 let DecoderMethod = "DecodeMemBarrierOption";
4024 // memory barriers protect the atomic sequences
4025 let hasSideEffects = 1 in {
4026 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4027 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4028 Requires<[IsARM, HasDB]> {
4030 let Inst{31-4} = 0xf57ff05;
4031 let Inst{3-0} = opt;
4035 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4036 "dsb", "\t$opt", []>,
4037 Requires<[IsARM, HasDB]> {
4039 let Inst{31-4} = 0xf57ff04;
4040 let Inst{3-0} = opt;
4043 // ISB has only full system option
4044 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4045 "isb", "\t$opt", []>,
4046 Requires<[IsARM, HasDB]> {
4048 let Inst{31-4} = 0xf57ff06;
4049 let Inst{3-0} = opt;
4052 // Pseudo instruction that combines movs + predicated rsbmi
4053 // to implement integer ABS
4054 let usesCustomInserter = 1, Defs = [CPSR] in {
4055 def ABS : ARMPseudoInst<
4056 (outs GPR:$dst), (ins GPR:$src),
4057 8, NoItinerary, []>;
4060 let usesCustomInserter = 1 in {
4061 let Defs = [CPSR] in {
4062 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4063 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4064 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4065 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4066 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4067 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4068 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4069 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4070 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4071 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4072 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4073 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4074 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4075 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4076 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4077 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4078 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4079 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4080 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4082 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4083 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4085 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4086 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4088 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4089 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4092 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4095 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4098 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4101 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4104 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4107 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4110 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4113 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4116 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4119 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4122 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4125 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4128 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4130 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4131 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4133 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4134 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4136 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4137 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4139 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4140 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4142 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4143 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4144 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4145 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4146 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4148 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4149 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4151 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_SWAP_I8 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4155 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4156 def ATOMIC_SWAP_I16 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4158 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4159 def ATOMIC_SWAP_I32 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4161 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4163 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4165 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4166 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4168 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4169 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4171 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4175 let usesCustomInserter = 1 in {
4176 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4177 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4179 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4182 let mayLoad = 1 in {
4183 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4185 "ldrexb", "\t$Rt, $addr", []>;
4186 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4187 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4188 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4189 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4190 let hasExtraDefRegAllocReq = 1 in
4191 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4192 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4193 let DecoderMethod = "DecodeDoubleRegLoad";
4197 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4198 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4199 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4200 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4201 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4202 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4203 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4204 let hasExtraSrcRegAllocReq = 1 in
4205 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4206 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4207 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4208 let DecoderMethod = "DecodeDoubleRegStore";
4213 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4214 Requires<[IsARM, HasV7]> {
4215 let Inst{31-0} = 0b11110101011111111111000000011111;
4218 // SWP/SWPB are deprecated in V6/V7.
4219 let mayLoad = 1, mayStore = 1 in {
4220 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4221 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4222 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4223 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4226 //===----------------------------------------------------------------------===//
4227 // Coprocessor Instructions.
4230 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4231 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4232 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4233 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4234 imm:$CRm, imm:$opc2)]> {
4242 let Inst{3-0} = CRm;
4244 let Inst{7-5} = opc2;
4245 let Inst{11-8} = cop;
4246 let Inst{15-12} = CRd;
4247 let Inst{19-16} = CRn;
4248 let Inst{23-20} = opc1;
4251 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4252 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4253 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4254 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4255 imm:$CRm, imm:$opc2)]> {
4256 let Inst{31-28} = 0b1111;
4264 let Inst{3-0} = CRm;
4266 let Inst{7-5} = opc2;
4267 let Inst{11-8} = cop;
4268 let Inst{15-12} = CRd;
4269 let Inst{19-16} = CRn;
4270 let Inst{23-20} = opc1;
4273 class ACI<dag oops, dag iops, string opc, string asm,
4274 IndexMode im = IndexModeNone>
4275 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4277 let Inst{27-25} = 0b110;
4279 class ACInoP<dag oops, dag iops, string opc, string asm,
4280 IndexMode im = IndexModeNone>
4281 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4283 let Inst{31-28} = 0b1111;
4284 let Inst{27-25} = 0b110;
4286 multiclass LdStCop<bit load, bit Dbit, string asm> {
4287 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4288 asm, "\t$cop, $CRd, $addr"> {
4292 let Inst{24} = 1; // P = 1
4293 let Inst{23} = addr{8};
4294 let Inst{22} = Dbit;
4295 let Inst{21} = 0; // W = 0
4296 let Inst{20} = load;
4297 let Inst{19-16} = addr{12-9};
4298 let Inst{15-12} = CRd;
4299 let Inst{11-8} = cop;
4300 let Inst{7-0} = addr{7-0};
4301 let DecoderMethod = "DecodeCopMemInstruction";
4303 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4304 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4308 let Inst{24} = 1; // P = 1
4309 let Inst{23} = addr{8};
4310 let Inst{22} = Dbit;
4311 let Inst{21} = 1; // W = 1
4312 let Inst{20} = load;
4313 let Inst{19-16} = addr{12-9};
4314 let Inst{15-12} = CRd;
4315 let Inst{11-8} = cop;
4316 let Inst{7-0} = addr{7-0};
4317 let DecoderMethod = "DecodeCopMemInstruction";
4319 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4320 postidx_imm8s4:$offset),
4321 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4326 let Inst{24} = 0; // P = 0
4327 let Inst{23} = offset{8};
4328 let Inst{22} = Dbit;
4329 let Inst{21} = 1; // W = 1
4330 let Inst{20} = load;
4331 let Inst{19-16} = addr;
4332 let Inst{15-12} = CRd;
4333 let Inst{11-8} = cop;
4334 let Inst{7-0} = offset{7-0};
4335 let DecoderMethod = "DecodeCopMemInstruction";
4337 def _OPTION : ACI<(outs),
4338 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4339 coproc_option_imm:$option),
4340 asm, "\t$cop, $CRd, $addr, $option"> {
4345 let Inst{24} = 0; // P = 0
4346 let Inst{23} = 1; // U = 1
4347 let Inst{22} = Dbit;
4348 let Inst{21} = 0; // W = 0
4349 let Inst{20} = load;
4350 let Inst{19-16} = addr;
4351 let Inst{15-12} = CRd;
4352 let Inst{11-8} = cop;
4353 let Inst{7-0} = option;
4354 let DecoderMethod = "DecodeCopMemInstruction";
4357 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4358 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4359 asm, "\t$cop, $CRd, $addr"> {
4363 let Inst{24} = 1; // P = 1
4364 let Inst{23} = addr{8};
4365 let Inst{22} = Dbit;
4366 let Inst{21} = 0; // W = 0
4367 let Inst{20} = load;
4368 let Inst{19-16} = addr{12-9};
4369 let Inst{15-12} = CRd;
4370 let Inst{11-8} = cop;
4371 let Inst{7-0} = addr{7-0};
4372 let DecoderMethod = "DecodeCopMemInstruction";
4374 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4375 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4379 let Inst{24} = 1; // P = 1
4380 let Inst{23} = addr{8};
4381 let Inst{22} = Dbit;
4382 let Inst{21} = 1; // W = 1
4383 let Inst{20} = load;
4384 let Inst{19-16} = addr{12-9};
4385 let Inst{15-12} = CRd;
4386 let Inst{11-8} = cop;
4387 let Inst{7-0} = addr{7-0};
4388 let DecoderMethod = "DecodeCopMemInstruction";
4390 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4391 postidx_imm8s4:$offset),
4392 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4397 let Inst{24} = 0; // P = 0
4398 let Inst{23} = offset{8};
4399 let Inst{22} = Dbit;
4400 let Inst{21} = 1; // W = 1
4401 let Inst{20} = load;
4402 let Inst{19-16} = addr;
4403 let Inst{15-12} = CRd;
4404 let Inst{11-8} = cop;
4405 let Inst{7-0} = offset{7-0};
4406 let DecoderMethod = "DecodeCopMemInstruction";
4408 def _OPTION : ACInoP<(outs),
4409 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4410 coproc_option_imm:$option),
4411 asm, "\t$cop, $CRd, $addr, $option"> {
4416 let Inst{24} = 0; // P = 0
4417 let Inst{23} = 1; // U = 1
4418 let Inst{22} = Dbit;
4419 let Inst{21} = 0; // W = 0
4420 let Inst{20} = load;
4421 let Inst{19-16} = addr;
4422 let Inst{15-12} = CRd;
4423 let Inst{11-8} = cop;
4424 let Inst{7-0} = option;
4425 let DecoderMethod = "DecodeCopMemInstruction";
4429 defm LDC : LdStCop <1, 0, "ldc">;
4430 defm LDCL : LdStCop <1, 1, "ldcl">;
4431 defm STC : LdStCop <0, 0, "stc">;
4432 defm STCL : LdStCop <0, 1, "stcl">;
4433 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4434 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4435 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4436 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4438 //===----------------------------------------------------------------------===//
4439 // Move between coprocessor and ARM core register.
4442 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4444 : ABI<0b1110, oops, iops, NoItinerary, opc,
4445 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4446 let Inst{20} = direction;
4456 let Inst{15-12} = Rt;
4457 let Inst{11-8} = cop;
4458 let Inst{23-21} = opc1;
4459 let Inst{7-5} = opc2;
4460 let Inst{3-0} = CRm;
4461 let Inst{19-16} = CRn;
4464 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4466 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4467 c_imm:$CRm, imm0_7:$opc2),
4468 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4469 imm:$CRm, imm:$opc2)]>;
4470 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4471 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4472 c_imm:$CRm, 0, pred:$p)>;
4473 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4475 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4477 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4478 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4479 c_imm:$CRm, 0, pred:$p)>;
4481 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4482 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4484 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4486 : ABXI<0b1110, oops, iops, NoItinerary,
4487 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4488 let Inst{31-28} = 0b1111;
4489 let Inst{20} = direction;
4499 let Inst{15-12} = Rt;
4500 let Inst{11-8} = cop;
4501 let Inst{23-21} = opc1;
4502 let Inst{7-5} = opc2;
4503 let Inst{3-0} = CRm;
4504 let Inst{19-16} = CRn;
4507 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4509 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4510 c_imm:$CRm, imm0_7:$opc2),
4511 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4512 imm:$CRm, imm:$opc2)]>;
4513 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4514 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4516 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4518 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4520 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4521 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4524 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4525 imm:$CRm, imm:$opc2),
4526 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4528 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4529 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4530 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4531 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4532 let Inst{23-21} = 0b010;
4533 let Inst{20} = direction;
4541 let Inst{15-12} = Rt;
4542 let Inst{19-16} = Rt2;
4543 let Inst{11-8} = cop;
4544 let Inst{7-4} = opc1;
4545 let Inst{3-0} = CRm;
4548 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4549 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4550 GPRnopc:$Rt2, imm:$CRm)]>;
4551 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4553 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4554 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4555 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4556 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4557 let Inst{31-28} = 0b1111;
4558 let Inst{23-21} = 0b010;
4559 let Inst{20} = direction;
4567 let Inst{15-12} = Rt;
4568 let Inst{19-16} = Rt2;
4569 let Inst{11-8} = cop;
4570 let Inst{7-4} = opc1;
4571 let Inst{3-0} = CRm;
4573 let DecoderMethod = "DecodeMRRC2";
4576 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4577 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4578 GPRnopc:$Rt2, imm:$CRm)]>;
4579 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4581 //===----------------------------------------------------------------------===//
4582 // Move between special register and ARM core register
4585 // Move to ARM core register from Special Register
4586 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4587 "mrs", "\t$Rd, apsr", []> {
4589 let Inst{23-16} = 0b00001111;
4590 let Unpredictable{19-17} = 0b111;
4592 let Inst{15-12} = Rd;
4594 let Inst{11-0} = 0b000000000000;
4595 let Unpredictable{11-0} = 0b110100001111;
4598 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4601 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4602 // section B9.3.9, with the R bit set to 1.
4603 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4604 "mrs", "\t$Rd, spsr", []> {
4606 let Inst{23-16} = 0b01001111;
4607 let Unpredictable{19-16} = 0b1111;
4609 let Inst{15-12} = Rd;
4611 let Inst{11-0} = 0b000000000000;
4612 let Unpredictable{11-0} = 0b110100001111;
4615 // Move from ARM core register to Special Register
4617 // No need to have both system and application versions, the encodings are the
4618 // same and the assembly parser has no way to distinguish between them. The mask
4619 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4620 // the mask with the fields to be accessed in the special register.
4621 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4622 "msr", "\t$mask, $Rn", []> {
4627 let Inst{22} = mask{4}; // R bit
4628 let Inst{21-20} = 0b10;
4629 let Inst{19-16} = mask{3-0};
4630 let Inst{15-12} = 0b1111;
4631 let Inst{11-4} = 0b00000000;
4635 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4636 "msr", "\t$mask, $a", []> {
4641 let Inst{22} = mask{4}; // R bit
4642 let Inst{21-20} = 0b10;
4643 let Inst{19-16} = mask{3-0};
4644 let Inst{15-12} = 0b1111;
4648 //===----------------------------------------------------------------------===//
4652 // __aeabi_read_tp preserves the registers r1-r3.
4653 // This is a pseudo inst so that we can get the encoding right,
4654 // complete with fixup for the aeabi_read_tp function.
4656 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4657 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4658 [(set R0, ARMthread_pointer)]>;
4661 //===----------------------------------------------------------------------===//
4662 // SJLJ Exception handling intrinsics
4663 // eh_sjlj_setjmp() is an instruction sequence to store the return
4664 // address and save #0 in R0 for the non-longjmp case.
4665 // Since by its nature we may be coming from some other function to get
4666 // here, and we're using the stack frame for the containing function to
4667 // save/restore registers, we can't keep anything live in regs across
4668 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4669 // when we get here from a longjmp(). We force everything out of registers
4670 // except for our own input by listing the relevant registers in Defs. By
4671 // doing so, we also cause the prologue/epilogue code to actively preserve
4672 // all of the callee-saved resgisters, which is exactly what we want.
4673 // A constant value is passed in $val, and we use the location as a scratch.
4675 // These are pseudo-instructions and are lowered to individual MC-insts, so
4676 // no encoding information is necessary.
4678 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4679 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4680 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4681 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4683 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4684 Requires<[IsARM, HasVFP2]>;
4688 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4689 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4690 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4692 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4693 Requires<[IsARM, NoVFP]>;
4696 // FIXME: Non-IOS version(s)
4697 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4698 Defs = [ R7, LR, SP ] in {
4699 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4701 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4702 Requires<[IsARM, IsIOS]>;
4705 // eh.sjlj.dispatchsetup pseudo-instructions.
4706 // These pseudos are used for both ARM and Thumb2. Any differences are
4707 // handled when the pseudo is expanded (which happens before any passes
4708 // that need the instruction size).
4710 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4711 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4713 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4716 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4718 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4721 //===----------------------------------------------------------------------===//
4722 // Non-Instruction Patterns
4725 // ARMv4 indirect branch using (MOVr PC, dst)
4726 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4727 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4728 4, IIC_Br, [(brind GPR:$dst)],
4729 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4730 Requires<[IsARM, NoV4T]>;
4732 // Large immediate handling.
4734 // 32-bit immediate using two piece so_imms or movw + movt.
4735 // This is a single pseudo instruction, the benefit is that it can be remat'd
4736 // as a single unit instead of having to handle reg inputs.
4737 // FIXME: Remove this when we can do generalized remat.
4738 let isReMaterializable = 1, isMoveImm = 1 in
4739 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4740 [(set GPR:$dst, (arm_i32imm:$src))]>,
4743 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4744 // It also makes it possible to rematerialize the instructions.
4745 // FIXME: Remove this when we can do generalized remat and when machine licm
4746 // can properly the instructions.
4747 let isReMaterializable = 1 in {
4748 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4750 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4751 Requires<[IsARM, UseMovt]>;
4753 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4755 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4756 Requires<[IsARM, UseMovt]>;
4758 let AddedComplexity = 10 in
4759 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4761 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4762 Requires<[IsARM, UseMovt]>;
4763 } // isReMaterializable
4765 // ConstantPool, GlobalAddress, and JumpTable
4766 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4767 Requires<[IsARM, DontUseMovt]>;
4768 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4769 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4770 Requires<[IsARM, UseMovt]>;
4771 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4772 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4774 // TODO: add,sub,and, 3-instr forms?
4776 // Tail calls. These patterns also apply to Thumb mode.
4777 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4778 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4779 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4782 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4783 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4784 (BMOVPCB_CALL texternalsym:$func)>;
4786 // zextload i1 -> zextload i8
4787 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4788 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4790 // extload -> zextload
4791 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4792 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4793 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4794 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4796 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4798 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4799 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4802 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4803 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4804 (SMULBB GPR:$a, GPR:$b)>;
4805 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4806 (SMULBB GPR:$a, GPR:$b)>;
4807 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4808 (sra GPR:$b, (i32 16))),
4809 (SMULBT GPR:$a, GPR:$b)>;
4810 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4811 (SMULBT GPR:$a, GPR:$b)>;
4812 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4813 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4814 (SMULTB GPR:$a, GPR:$b)>;
4815 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4816 (SMULTB GPR:$a, GPR:$b)>;
4817 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4819 (SMULWB GPR:$a, GPR:$b)>;
4820 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4821 (SMULWB GPR:$a, GPR:$b)>;
4823 def : ARMV5TEPat<(add GPR:$acc,
4824 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4825 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4826 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4827 def : ARMV5TEPat<(add GPR:$acc,
4828 (mul sext_16_node:$a, sext_16_node:$b)),
4829 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4830 def : ARMV5TEPat<(add GPR:$acc,
4831 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4832 (sra GPR:$b, (i32 16)))),
4833 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4834 def : ARMV5TEPat<(add GPR:$acc,
4835 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4836 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4837 def : ARMV5TEPat<(add GPR:$acc,
4838 (mul (sra GPR:$a, (i32 16)),
4839 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4840 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4841 def : ARMV5TEPat<(add GPR:$acc,
4842 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4843 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4844 def : ARMV5TEPat<(add GPR:$acc,
4845 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4847 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4848 def : ARMV5TEPat<(add GPR:$acc,
4849 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4850 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4853 // Pre-v7 uses MCR for synchronization barriers.
4854 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4855 Requires<[IsARM, HasV6]>;
4857 // SXT/UXT with no rotate
4858 let AddedComplexity = 16 in {
4859 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4860 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4861 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4862 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4863 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4864 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4865 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4868 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4869 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4871 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4872 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4873 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4874 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4876 // Atomic load/store patterns
4877 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4878 (LDRBrs ldst_so_reg:$src)>;
4879 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4880 (LDRBi12 addrmode_imm12:$src)>;
4881 def : ARMPat<(atomic_load_16 addrmode3:$src),
4882 (LDRH addrmode3:$src)>;
4883 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4884 (LDRrs ldst_so_reg:$src)>;
4885 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4886 (LDRi12 addrmode_imm12:$src)>;
4887 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4888 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4889 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4890 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4891 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4892 (STRH GPR:$val, addrmode3:$ptr)>;
4893 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4894 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4895 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4896 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4899 //===----------------------------------------------------------------------===//
4903 include "ARMInstrThumb.td"
4905 //===----------------------------------------------------------------------===//
4909 include "ARMInstrThumb2.td"
4911 //===----------------------------------------------------------------------===//
4912 // Floating Point Support
4915 include "ARMInstrVFP.td"
4917 //===----------------------------------------------------------------------===//
4918 // Advanced SIMD (NEON) Support
4921 include "ARMInstrNEON.td"
4923 //===----------------------------------------------------------------------===//
4924 // Assembler aliases
4928 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4929 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4930 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4932 // System instructions
4933 def : MnemonicAlias<"swi", "svc">;
4935 // Load / Store Multiple
4936 def : MnemonicAlias<"ldmfd", "ldm">;
4937 def : MnemonicAlias<"ldmia", "ldm">;
4938 def : MnemonicAlias<"ldmea", "ldmdb">;
4939 def : MnemonicAlias<"stmfd", "stmdb">;
4940 def : MnemonicAlias<"stmia", "stm">;
4941 def : MnemonicAlias<"stmea", "stm">;
4943 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4944 // shift amount is zero (i.e., unspecified).
4945 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4946 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4947 Requires<[IsARM, HasV6]>;
4948 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4949 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4950 Requires<[IsARM, HasV6]>;
4952 // PUSH/POP aliases for STM/LDM
4953 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4954 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4956 // SSAT/USAT optional shift operand.
4957 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4958 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4959 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4960 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4963 // Extend instruction optional rotate operand.
4964 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4965 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4966 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4967 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4968 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4969 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4970 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4971 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4972 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4973 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4974 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4975 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4977 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4978 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4979 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4980 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4981 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4982 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4983 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4984 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4985 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4986 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4987 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4988 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4992 def : MnemonicAlias<"rfefa", "rfeda">;
4993 def : MnemonicAlias<"rfeea", "rfedb">;
4994 def : MnemonicAlias<"rfefd", "rfeia">;
4995 def : MnemonicAlias<"rfeed", "rfeib">;
4996 def : MnemonicAlias<"rfe", "rfeia">;
4999 def : MnemonicAlias<"srsfa", "srsda">;
5000 def : MnemonicAlias<"srsea", "srsdb">;
5001 def : MnemonicAlias<"srsfd", "srsia">;
5002 def : MnemonicAlias<"srsed", "srsib">;
5003 def : MnemonicAlias<"srs", "srsia">;
5006 def : MnemonicAlias<"qsubaddx", "qsax">;
5008 def : MnemonicAlias<"saddsubx", "sasx">;
5009 // SHASX == SHADDSUBX
5010 def : MnemonicAlias<"shaddsubx", "shasx">;
5011 // SHSAX == SHSUBADDX
5012 def : MnemonicAlias<"shsubaddx", "shsax">;
5014 def : MnemonicAlias<"ssubaddx", "ssax">;
5016 def : MnemonicAlias<"uaddsubx", "uasx">;
5017 // UHASX == UHADDSUBX
5018 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5019 // UHSAX == UHSUBADDX
5020 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5021 // UQASX == UQADDSUBX
5022 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5023 // UQSAX == UQSUBADDX
5024 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5026 def : MnemonicAlias<"usubaddx", "usax">;
5028 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5030 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5031 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5032 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5033 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5034 // Same for AND <--> BIC
5035 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5036 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5037 pred:$p, cc_out:$s)>;
5038 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5039 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5040 pred:$p, cc_out:$s)>;
5041 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5042 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5043 pred:$p, cc_out:$s)>;
5044 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5045 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5046 pred:$p, cc_out:$s)>;
5048 // Likewise, "add Rd, so_imm_neg" -> sub
5049 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5050 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5051 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5052 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5053 // Same for CMP <--> CMN via so_imm_neg
5054 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5055 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5056 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5057 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5059 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5060 // LSR, ROR, and RRX instructions.
5061 // FIXME: We need C++ parser hooks to map the alias to the MOV
5062 // encoding. It seems we should be able to do that sort of thing
5063 // in tblgen, but it could get ugly.
5064 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5065 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5066 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5068 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5069 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5071 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5072 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5074 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5075 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5078 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5079 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5080 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5081 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5082 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5084 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5085 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5087 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5088 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5090 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5091 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5095 // "neg" is and alias for "rsb rd, rn, #0"
5096 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5097 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5099 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5100 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5101 Requires<[IsARM, NoV6]>;
5103 // UMULL/SMULL are available on all arches, but the instruction definitions
5104 // need difference constraints pre-v6. Use these aliases for the assembly
5105 // parsing on pre-v6.
5106 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5107 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5108 Requires<[IsARM, NoV6]>;
5109 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5110 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5111 Requires<[IsARM, NoV6]>;
5113 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5115 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;