1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
225 AssemblerPredicate<"FeatureTrustZone",
227 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
228 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
229 def IsThumb : Predicate<"Subtarget->isThumb()">,
230 AssemblerPredicate<"ModeThumb", "thumb">;
231 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
232 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
233 AssemblerPredicate<"ModeThumb,FeatureThumb2",
235 def IsMClass : Predicate<"Subtarget->isMClass()">,
236 AssemblerPredicate<"FeatureMClass", "armv7m">;
237 def IsARClass : Predicate<"!Subtarget->isMClass()">,
238 AssemblerPredicate<"!FeatureMClass",
240 def IsARM : Predicate<"!Subtarget->isThumb()">,
241 AssemblerPredicate<"!ModeThumb", "arm-mode">;
242 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
243 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
244 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
245 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
246 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
247 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
249 // FIXME: Eventually this will be just "hasV6T2Ops".
250 def UseMovt : Predicate<"Subtarget->useMovt()">;
251 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
252 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
253 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
255 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
256 // But only select them if more precision in FP computation is allowed.
257 // Do not use them for Darwin platforms.
258 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
259 " FPOpFusion::Fast) && "
260 "!Subtarget->isTargetDarwin()">;
261 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
262 "Subtarget->isTargetDarwin()">;
264 // VGETLNi32 is microcoded on Swift - prefer VMOV.
265 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
266 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
268 // VDUP.32 is microcoded on Swift - prefer VMOV.
269 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
270 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
272 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
273 // this allows more effective execution domain optimization. See
274 // setExecutionDomain().
275 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
276 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
278 def IsLE : Predicate<"TLI.isLittleEndian()">;
279 def IsBE : Predicate<"TLI.isBigEndian()">;
281 //===----------------------------------------------------------------------===//
282 // ARM Flag Definitions.
284 class RegConstraint<string C> {
285 string Constraints = C;
288 //===----------------------------------------------------------------------===//
289 // ARM specific transformation functions and pattern fragments.
292 // imm_neg_XFORM - Return the negation of an i32 immediate value.
293 def imm_neg_XFORM : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
297 // imm_not_XFORM - Return the complement of a i32 immediate value.
298 def imm_not_XFORM : SDNodeXForm<imm, [{
299 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
302 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
303 def imm16_31 : ImmLeaf<i32, [{
304 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
307 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
308 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
309 unsigned Value = -(unsigned)N->getZExtValue();
310 return Value && ARM_AM::getSOImmVal(Value) != -1;
312 let ParserMatchClass = so_imm_neg_asmoperand;
315 // Note: this pattern doesn't require an encoder method and such, as it's
316 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
317 // is handled by the destination instructions, which use so_imm.
318 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
319 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
320 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
322 let ParserMatchClass = so_imm_not_asmoperand;
325 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
326 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
327 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
330 /// Split a 32-bit immediate into two 16 bit parts.
331 def hi16 : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
335 def lo16AllZero : PatLeaf<(i32 imm), [{
336 // Returns true if all low 16-bits are 0.
337 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
340 class BinOpWithFlagFrag<dag res> :
341 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
342 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
343 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
345 // An 'and' node with a single use.
346 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
347 return N->hasOneUse();
350 // An 'xor' node with a single use.
351 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
352 return N->hasOneUse();
355 // An 'fmul' node with a single use.
356 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
357 return N->hasOneUse();
360 // An 'fadd' node which checks for single non-hazardous use.
361 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
362 return hasNoVMLxHazardUse(N);
365 // An 'fsub' node which checks for single non-hazardous use.
366 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
367 return hasNoVMLxHazardUse(N);
370 //===----------------------------------------------------------------------===//
371 // Operand Definitions.
374 // Immediate operands with a shared generic asm render method.
375 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
378 // FIXME: rename brtarget to t2_brtarget
379 def brtarget : Operand<OtherVT> {
380 let EncoderMethod = "getBranchTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
382 let DecoderMethod = "DecodeT2BROperand";
385 // FIXME: get rid of this one?
386 def uncondbrtarget : Operand<OtherVT> {
387 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
388 let OperandType = "OPERAND_PCREL";
391 // Branch target for ARM. Handles conditional/unconditional
392 def br_target : Operand<OtherVT> {
393 let EncoderMethod = "getARMBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
398 // FIXME: rename bltarget to t2_bl_target?
399 def bltarget : Operand<i32> {
400 // Encoded the same as branch targets.
401 let EncoderMethod = "getBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
405 // Call target for ARM. Handles conditional/unconditional
406 // FIXME: rename bl_target to t2_bltarget?
407 def bl_target : Operand<i32> {
408 let EncoderMethod = "getARMBLTargetOpValue";
409 let OperandType = "OPERAND_PCREL";
412 def blx_target : Operand<i32> {
413 let EncoderMethod = "getARMBLXTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // A list of registers separated by comma. Used by load/store multiple.
418 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
419 def reglist : Operand<i32> {
420 let EncoderMethod = "getRegisterListOpValue";
421 let ParserMatchClass = RegListAsmOperand;
422 let PrintMethod = "printRegisterList";
423 let DecoderMethod = "DecodeRegListOperand";
426 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
428 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
429 def dpr_reglist : Operand<i32> {
430 let EncoderMethod = "getRegisterListOpValue";
431 let ParserMatchClass = DPRRegListAsmOperand;
432 let PrintMethod = "printRegisterList";
433 let DecoderMethod = "DecodeDPRRegListOperand";
436 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
437 def spr_reglist : Operand<i32> {
438 let EncoderMethod = "getRegisterListOpValue";
439 let ParserMatchClass = SPRRegListAsmOperand;
440 let PrintMethod = "printRegisterList";
441 let DecoderMethod = "DecodeSPRRegListOperand";
444 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
445 def cpinst_operand : Operand<i32> {
446 let PrintMethod = "printCPInstOperand";
450 def pclabel : Operand<i32> {
451 let PrintMethod = "printPCLabel";
454 // ADR instruction labels.
455 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
456 def adrlabel : Operand<i32> {
457 let EncoderMethod = "getAdrLabelOpValue";
458 let ParserMatchClass = AdrLabelAsmOperand;
459 let PrintMethod = "printAdrLabelOperand";
462 def neon_vcvt_imm32 : Operand<i32> {
463 let EncoderMethod = "getNEONVcvtImm32OpValue";
464 let DecoderMethod = "DecodeVCVTImmOperand";
467 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
468 def rot_imm_XFORM: SDNodeXForm<imm, [{
469 switch (N->getZExtValue()){
471 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
472 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
473 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
474 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
477 def RotImmAsmOperand : AsmOperandClass {
479 let ParserMethod = "parseRotImm";
481 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
482 int32_t v = N->getZExtValue();
483 return v == 8 || v == 16 || v == 24; }],
485 let PrintMethod = "printRotImmOperand";
486 let ParserMatchClass = RotImmAsmOperand;
489 // shift_imm: An integer that encodes a shift amount and the type of shift
490 // (asr or lsl). The 6-bit immediate encodes as:
493 // {4-0} imm5 shift amount.
494 // asr #32 encoded as imm5 == 0.
495 def ShifterImmAsmOperand : AsmOperandClass {
496 let Name = "ShifterImm";
497 let ParserMethod = "parseShifterImm";
499 def shift_imm : Operand<i32> {
500 let PrintMethod = "printShiftImmOperand";
501 let ParserMatchClass = ShifterImmAsmOperand;
504 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
505 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
506 def so_reg_reg : Operand<i32>, // reg reg imm
507 ComplexPattern<i32, 3, "SelectRegShifterOperand",
508 [shl, srl, sra, rotr]> {
509 let EncoderMethod = "getSORegRegOpValue";
510 let PrintMethod = "printSORegRegOperand";
511 let DecoderMethod = "DecodeSORegRegOperand";
512 let ParserMatchClass = ShiftedRegAsmOperand;
513 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
516 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
517 def so_reg_imm : Operand<i32>, // reg imm
518 ComplexPattern<i32, 2, "SelectImmShifterOperand",
519 [shl, srl, sra, rotr]> {
520 let EncoderMethod = "getSORegImmOpValue";
521 let PrintMethod = "printSORegImmOperand";
522 let DecoderMethod = "DecodeSORegImmOperand";
523 let ParserMatchClass = ShiftedImmAsmOperand;
524 let MIOperandInfo = (ops GPR, i32imm);
527 // FIXME: Does this need to be distinct from so_reg?
528 def shift_so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
530 [shl,srl,sra,rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPR, GPR, i32imm);
538 // FIXME: Does this need to be distinct from so_reg?
539 def shift_so_reg_imm : Operand<i32>, // reg reg imm
540 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
541 [shl,srl,sra,rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
550 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
551 // 8-bit immediate rotated by an arbitrary number of bits.
552 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
553 def so_imm : Operand<i32>, ImmLeaf<i32, [{
554 return ARM_AM::getSOImmVal(Imm) != -1;
556 let EncoderMethod = "getSOImmOpValue";
557 let ParserMatchClass = SOImmAsmOperand;
558 let DecoderMethod = "DecodeSOImmOperand";
561 // Break so_imm's up into two pieces. This handles immediates with up to 16
562 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
563 // get the first/second pieces.
564 def so_imm2part : PatLeaf<(imm), [{
565 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
568 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
570 def arm_i32imm : PatLeaf<(imm), [{
571 if (Subtarget->hasV6T2Ops())
573 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
576 /// imm0_1 predicate - Immediate in the range [0,1].
577 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
578 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
580 /// imm0_3 predicate - Immediate in the range [0,3].
581 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
582 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
584 /// imm0_4 predicate - Immediate in the range [0,4].
585 def Imm0_4AsmOperand : ImmAsmOperand { let Name = "Imm0_4"; }
586 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
587 let ParserMatchClass = Imm0_4AsmOperand;
588 let DecoderMethod = "DecodeImm0_4";
591 /// imm0_7 predicate - Immediate in the range [0,7].
592 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
593 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
594 return Imm >= 0 && Imm < 8;
596 let ParserMatchClass = Imm0_7AsmOperand;
599 /// imm8 predicate - Immediate is exactly 8.
600 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
601 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
602 let ParserMatchClass = Imm8AsmOperand;
605 /// imm16 predicate - Immediate is exactly 16.
606 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
607 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
608 let ParserMatchClass = Imm16AsmOperand;
611 /// imm32 predicate - Immediate is exactly 32.
612 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
613 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
614 let ParserMatchClass = Imm32AsmOperand;
617 /// imm1_7 predicate - Immediate in the range [1,7].
618 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
619 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
620 let ParserMatchClass = Imm1_7AsmOperand;
623 /// imm1_15 predicate - Immediate in the range [1,15].
624 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
625 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
626 let ParserMatchClass = Imm1_15AsmOperand;
629 /// imm1_31 predicate - Immediate in the range [1,31].
630 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
631 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
632 let ParserMatchClass = Imm1_31AsmOperand;
635 /// imm0_15 predicate - Immediate in the range [0,15].
636 def Imm0_15AsmOperand: ImmAsmOperand {
637 let Name = "Imm0_15";
638 let DiagnosticType = "ImmRange0_15";
640 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
641 return Imm >= 0 && Imm < 16;
643 let ParserMatchClass = Imm0_15AsmOperand;
646 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
647 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
648 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
649 return Imm >= 0 && Imm < 32;
651 let ParserMatchClass = Imm0_31AsmOperand;
654 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
655 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
656 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
657 return Imm >= 0 && Imm < 32;
659 let ParserMatchClass = Imm0_32AsmOperand;
662 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
663 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
664 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
665 return Imm >= 0 && Imm < 64;
667 let ParserMatchClass = Imm0_63AsmOperand;
670 /// imm0_255 predicate - Immediate in the range [0,255].
671 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
672 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
673 let ParserMatchClass = Imm0_255AsmOperand;
676 /// imm0_65535 - An immediate is in the range [0.65535].
677 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
678 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
679 return Imm >= 0 && Imm < 65536;
681 let ParserMatchClass = Imm0_65535AsmOperand;
684 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
685 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
686 return -Imm >= 0 && -Imm < 65536;
689 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
690 // a relocatable expression.
692 // FIXME: This really needs a Thumb version separate from the ARM version.
693 // While the range is the same, and can thus use the same match class,
694 // the encoding is different so it should have a different encoder method.
695 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
696 def imm0_65535_expr : Operand<i32> {
697 let EncoderMethod = "getHiLo16ImmOpValue";
698 let ParserMatchClass = Imm0_65535ExprAsmOperand;
701 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
702 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
703 def imm24b : Operand<i32>, ImmLeaf<i32, [{
704 return Imm >= 0 && Imm <= 0xffffff;
706 let ParserMatchClass = Imm24bitAsmOperand;
710 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
712 def BitfieldAsmOperand : AsmOperandClass {
713 let Name = "Bitfield";
714 let ParserMethod = "parseBitfield";
717 def bf_inv_mask_imm : Operand<i32>,
719 return ARM::isBitFieldInvertedMask(N->getZExtValue());
721 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
722 let PrintMethod = "printBitfieldInvMaskImmOperand";
723 let DecoderMethod = "DecodeBitfieldMaskOperand";
724 let ParserMatchClass = BitfieldAsmOperand;
727 def imm1_32_XFORM: SDNodeXForm<imm, [{
728 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
730 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
731 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
732 uint64_t Imm = N->getZExtValue();
733 return Imm > 0 && Imm <= 32;
736 let PrintMethod = "printImmPlusOneOperand";
737 let ParserMatchClass = Imm1_32AsmOperand;
740 def imm1_16_XFORM: SDNodeXForm<imm, [{
741 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
743 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
744 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
746 let PrintMethod = "printImmPlusOneOperand";
747 let ParserMatchClass = Imm1_16AsmOperand;
750 // Define ARM specific addressing modes.
751 // addrmode_imm12 := reg +/- imm12
753 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
754 class AddrMode_Imm12 : Operand<i32>,
755 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
756 // 12-bit immediate operand. Note that instructions using this encode
757 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
758 // immediate values are as normal.
760 let EncoderMethod = "getAddrModeImm12OpValue";
761 let DecoderMethod = "DecodeAddrModeImm12Operand";
762 let ParserMatchClass = MemImm12OffsetAsmOperand;
763 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
766 def addrmode_imm12 : AddrMode_Imm12 {
767 let PrintMethod = "printAddrModeImm12Operand<false>";
770 def addrmode_imm12_pre : AddrMode_Imm12 {
771 let PrintMethod = "printAddrModeImm12Operand<true>";
774 // ldst_so_reg := reg +/- reg shop imm
776 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
777 def ldst_so_reg : Operand<i32>,
778 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
779 let EncoderMethod = "getLdStSORegOpValue";
780 // FIXME: Simplify the printer
781 let PrintMethod = "printAddrMode2Operand";
782 let DecoderMethod = "DecodeSORegMemOperand";
783 let ParserMatchClass = MemRegOffsetAsmOperand;
784 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
787 // postidx_imm8 := +/- [0,255]
790 // {8} 1 is imm8 is non-negative. 0 otherwise.
791 // {7-0} [0,255] imm8 value.
792 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
793 def postidx_imm8 : Operand<i32> {
794 let PrintMethod = "printPostIdxImm8Operand";
795 let ParserMatchClass = PostIdxImm8AsmOperand;
796 let MIOperandInfo = (ops i32imm);
799 // postidx_imm8s4 := +/- [0,1020]
802 // {8} 1 is imm8 is non-negative. 0 otherwise.
803 // {7-0} [0,255] imm8 value, scaled by 4.
804 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
805 def postidx_imm8s4 : Operand<i32> {
806 let PrintMethod = "printPostIdxImm8s4Operand";
807 let ParserMatchClass = PostIdxImm8s4AsmOperand;
808 let MIOperandInfo = (ops i32imm);
812 // postidx_reg := +/- reg
814 def PostIdxRegAsmOperand : AsmOperandClass {
815 let Name = "PostIdxReg";
816 let ParserMethod = "parsePostIdxReg";
818 def postidx_reg : Operand<i32> {
819 let EncoderMethod = "getPostIdxRegOpValue";
820 let DecoderMethod = "DecodePostIdxReg";
821 let PrintMethod = "printPostIdxRegOperand";
822 let ParserMatchClass = PostIdxRegAsmOperand;
823 let MIOperandInfo = (ops GPRnopc, i32imm);
827 // addrmode2 := reg +/- imm12
828 // := reg +/- reg shop imm
830 // FIXME: addrmode2 should be refactored the rest of the way to always
831 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
832 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
833 def addrmode2 : Operand<i32>,
834 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
835 let EncoderMethod = "getAddrMode2OpValue";
836 let PrintMethod = "printAddrMode2Operand";
837 let ParserMatchClass = AddrMode2AsmOperand;
838 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
841 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
842 let Name = "PostIdxRegShifted";
843 let ParserMethod = "parsePostIdxReg";
845 def am2offset_reg : Operand<i32>,
846 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
847 [], [SDNPWantRoot]> {
848 let EncoderMethod = "getAddrMode2OffsetOpValue";
849 let PrintMethod = "printAddrMode2OffsetOperand";
850 // When using this for assembly, it's always as a post-index offset.
851 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
852 let MIOperandInfo = (ops GPRnopc, i32imm);
855 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
856 // the GPR is purely vestigal at this point.
857 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
858 def am2offset_imm : Operand<i32>,
859 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
860 [], [SDNPWantRoot]> {
861 let EncoderMethod = "getAddrMode2OffsetOpValue";
862 let PrintMethod = "printAddrMode2OffsetOperand";
863 let ParserMatchClass = AM2OffsetImmAsmOperand;
864 let MIOperandInfo = (ops GPRnopc, i32imm);
868 // addrmode3 := reg +/- reg
869 // addrmode3 := reg +/- imm8
871 // FIXME: split into imm vs. reg versions.
872 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
873 class AddrMode3 : Operand<i32>,
874 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
875 let EncoderMethod = "getAddrMode3OpValue";
876 let ParserMatchClass = AddrMode3AsmOperand;
877 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
880 def addrmode3 : AddrMode3
882 let PrintMethod = "printAddrMode3Operand<false>";
885 def addrmode3_pre : AddrMode3
887 let PrintMethod = "printAddrMode3Operand<true>";
890 // FIXME: split into imm vs. reg versions.
891 // FIXME: parser method to handle +/- register.
892 def AM3OffsetAsmOperand : AsmOperandClass {
893 let Name = "AM3Offset";
894 let ParserMethod = "parseAM3Offset";
896 def am3offset : Operand<i32>,
897 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
898 [], [SDNPWantRoot]> {
899 let EncoderMethod = "getAddrMode3OffsetOpValue";
900 let PrintMethod = "printAddrMode3OffsetOperand";
901 let ParserMatchClass = AM3OffsetAsmOperand;
902 let MIOperandInfo = (ops GPR, i32imm);
905 // ldstm_mode := {ia, ib, da, db}
907 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
908 let EncoderMethod = "getLdStmModeOpValue";
909 let PrintMethod = "printLdStmModeOperand";
912 // addrmode5 := reg +/- imm8*4
914 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
915 class AddrMode5 : Operand<i32>,
916 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
917 let EncoderMethod = "getAddrMode5OpValue";
918 let DecoderMethod = "DecodeAddrMode5Operand";
919 let ParserMatchClass = AddrMode5AsmOperand;
920 let MIOperandInfo = (ops GPR:$base, i32imm);
923 def addrmode5 : AddrMode5 {
924 let PrintMethod = "printAddrMode5Operand<false>";
927 def addrmode5_pre : AddrMode5 {
928 let PrintMethod = "printAddrMode5Operand<true>";
931 // addrmode6 := reg with optional alignment
933 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
934 def addrmode6 : Operand<i32>,
935 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
936 let PrintMethod = "printAddrMode6Operand";
937 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
938 let EncoderMethod = "getAddrMode6AddressOpValue";
939 let DecoderMethod = "DecodeAddrMode6Operand";
940 let ParserMatchClass = AddrMode6AsmOperand;
943 def am6offset : Operand<i32>,
944 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
945 [], [SDNPWantRoot]> {
946 let PrintMethod = "printAddrMode6OffsetOperand";
947 let MIOperandInfo = (ops GPR);
948 let EncoderMethod = "getAddrMode6OffsetOpValue";
949 let DecoderMethod = "DecodeGPRRegisterClass";
952 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
953 // (single element from one lane) for size 32.
954 def addrmode6oneL32 : Operand<i32>,
955 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
956 let PrintMethod = "printAddrMode6Operand";
957 let MIOperandInfo = (ops GPR:$addr, i32imm);
958 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
961 // Special version of addrmode6 to handle alignment encoding for VLD-dup
962 // instructions, specifically VLD4-dup.
963 def addrmode6dup : Operand<i32>,
964 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
965 let PrintMethod = "printAddrMode6Operand";
966 let MIOperandInfo = (ops GPR:$addr, i32imm);
967 let EncoderMethod = "getAddrMode6DupAddressOpValue";
968 // FIXME: This is close, but not quite right. The alignment specifier is
970 let ParserMatchClass = AddrMode6AsmOperand;
973 // addrmodepc := pc + reg
975 def addrmodepc : Operand<i32>,
976 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
977 let PrintMethod = "printAddrModePCOperand";
978 let MIOperandInfo = (ops GPR, i32imm);
981 // addr_offset_none := reg
983 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
984 def addr_offset_none : Operand<i32>,
985 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
986 let PrintMethod = "printAddrMode7Operand";
987 let DecoderMethod = "DecodeAddrMode7Operand";
988 let ParserMatchClass = MemNoOffsetAsmOperand;
989 let MIOperandInfo = (ops GPR:$base);
992 def nohash_imm : Operand<i32> {
993 let PrintMethod = "printNoHashImmediate";
996 def CoprocNumAsmOperand : AsmOperandClass {
997 let Name = "CoprocNum";
998 let ParserMethod = "parseCoprocNumOperand";
1000 def p_imm : Operand<i32> {
1001 let PrintMethod = "printPImmediate";
1002 let ParserMatchClass = CoprocNumAsmOperand;
1003 let DecoderMethod = "DecodeCoprocessor";
1006 def pf_imm : Operand<i32> {
1007 let PrintMethod = "printPImmediate";
1008 let ParserMatchClass = CoprocNumAsmOperand;
1011 def CoprocRegAsmOperand : AsmOperandClass {
1012 let Name = "CoprocReg";
1013 let ParserMethod = "parseCoprocRegOperand";
1015 def c_imm : Operand<i32> {
1016 let PrintMethod = "printCImmediate";
1017 let ParserMatchClass = CoprocRegAsmOperand;
1019 def CoprocOptionAsmOperand : AsmOperandClass {
1020 let Name = "CoprocOption";
1021 let ParserMethod = "parseCoprocOptionOperand";
1023 def coproc_option_imm : Operand<i32> {
1024 let PrintMethod = "printCoprocOptionImm";
1025 let ParserMatchClass = CoprocOptionAsmOperand;
1028 //===----------------------------------------------------------------------===//
1030 include "ARMInstrFormats.td"
1032 //===----------------------------------------------------------------------===//
1033 // Multiclass helpers...
1036 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1037 /// binop that produces a value.
1038 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1039 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1040 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1041 PatFrag opnode, bit Commutable = 0> {
1042 // The register-immediate version is re-materializable. This is useful
1043 // in particular for taking the address of a local.
1044 let isReMaterializable = 1 in {
1045 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1046 iii, opc, "\t$Rd, $Rn, $imm",
1047 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1048 Sched<[WriteALU, ReadALU]> {
1053 let Inst{19-16} = Rn;
1054 let Inst{15-12} = Rd;
1055 let Inst{11-0} = imm;
1058 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1059 iir, opc, "\t$Rd, $Rn, $Rm",
1060 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1061 Sched<[WriteALU, ReadALU, ReadALU]> {
1066 let isCommutable = Commutable;
1067 let Inst{19-16} = Rn;
1068 let Inst{15-12} = Rd;
1069 let Inst{11-4} = 0b00000000;
1073 def rsi : AsI1<opcod, (outs GPR:$Rd),
1074 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1075 iis, opc, "\t$Rd, $Rn, $shift",
1076 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1077 Sched<[WriteALUsi, ReadALU]> {
1082 let Inst{19-16} = Rn;
1083 let Inst{15-12} = Rd;
1084 let Inst{11-5} = shift{11-5};
1086 let Inst{3-0} = shift{3-0};
1089 def rsr : AsI1<opcod, (outs GPR:$Rd),
1090 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1091 iis, opc, "\t$Rd, $Rn, $shift",
1092 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1093 Sched<[WriteALUsr, ReadALUsr]> {
1098 let Inst{19-16} = Rn;
1099 let Inst{15-12} = Rd;
1100 let Inst{11-8} = shift{11-8};
1102 let Inst{6-5} = shift{6-5};
1104 let Inst{3-0} = shift{3-0};
1108 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1109 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1110 /// it is equivalent to the AsI1_bin_irs counterpart.
1111 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1112 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1113 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1114 PatFrag opnode, bit Commutable = 0> {
1115 // The register-immediate version is re-materializable. This is useful
1116 // in particular for taking the address of a local.
1117 let isReMaterializable = 1 in {
1118 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1119 iii, opc, "\t$Rd, $Rn, $imm",
1120 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1121 Sched<[WriteALU, ReadALU]> {
1126 let Inst{19-16} = Rn;
1127 let Inst{15-12} = Rd;
1128 let Inst{11-0} = imm;
1131 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1132 iir, opc, "\t$Rd, $Rn, $Rm",
1133 [/* pattern left blank */]>,
1134 Sched<[WriteALU, ReadALU, ReadALU]> {
1138 let Inst{11-4} = 0b00000000;
1141 let Inst{15-12} = Rd;
1142 let Inst{19-16} = Rn;
1145 def rsi : AsI1<opcod, (outs GPR:$Rd),
1146 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1147 iis, opc, "\t$Rd, $Rn, $shift",
1148 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1149 Sched<[WriteALUsi, ReadALU]> {
1154 let Inst{19-16} = Rn;
1155 let Inst{15-12} = Rd;
1156 let Inst{11-5} = shift{11-5};
1158 let Inst{3-0} = shift{3-0};
1161 def rsr : AsI1<opcod, (outs GPR:$Rd),
1162 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1163 iis, opc, "\t$Rd, $Rn, $shift",
1164 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1165 Sched<[WriteALUsr, ReadALUsr]> {
1170 let Inst{19-16} = Rn;
1171 let Inst{15-12} = Rd;
1172 let Inst{11-8} = shift{11-8};
1174 let Inst{6-5} = shift{6-5};
1176 let Inst{3-0} = shift{3-0};
1180 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1182 /// These opcodes will be converted to the real non-S opcodes by
1183 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1184 let hasPostISelHook = 1, Defs = [CPSR] in {
1185 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1186 InstrItinClass iis, PatFrag opnode,
1187 bit Commutable = 0> {
1188 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1190 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1191 Sched<[WriteALU, ReadALU]>;
1193 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1195 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1196 Sched<[WriteALU, ReadALU, ReadALU]> {
1197 let isCommutable = Commutable;
1199 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1200 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1202 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1203 so_reg_imm:$shift))]>,
1204 Sched<[WriteALUsi, ReadALU]>;
1206 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1207 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1209 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1210 so_reg_reg:$shift))]>,
1211 Sched<[WriteALUSsr, ReadALUsr]>;
1215 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1216 /// operands are reversed.
1217 let hasPostISelHook = 1, Defs = [CPSR] in {
1218 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1219 InstrItinClass iis, PatFrag opnode,
1220 bit Commutable = 0> {
1221 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1223 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1224 Sched<[WriteALU, ReadALU]>;
1226 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1227 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1229 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1231 Sched<[WriteALUsi, ReadALU]>;
1233 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1234 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1236 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1238 Sched<[WriteALUSsr, ReadALUsr]>;
1242 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1243 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1244 /// a explicit result, only implicitly set CPSR.
1245 let isCompare = 1, Defs = [CPSR] in {
1246 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1247 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1248 PatFrag opnode, bit Commutable = 0> {
1249 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1251 [(opnode GPR:$Rn, so_imm:$imm)]>,
1252 Sched<[WriteCMP, ReadALU]> {
1257 let Inst{19-16} = Rn;
1258 let Inst{15-12} = 0b0000;
1259 let Inst{11-0} = imm;
1261 let Unpredictable{15-12} = 0b1111;
1263 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1265 [(opnode GPR:$Rn, GPR:$Rm)]>,
1266 Sched<[WriteCMP, ReadALU, ReadALU]> {
1269 let isCommutable = Commutable;
1272 let Inst{19-16} = Rn;
1273 let Inst{15-12} = 0b0000;
1274 let Inst{11-4} = 0b00000000;
1277 let Unpredictable{15-12} = 0b1111;
1279 def rsi : AI1<opcod, (outs),
1280 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1281 opc, "\t$Rn, $shift",
1282 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1283 Sched<[WriteCMPsi, ReadALU]> {
1288 let Inst{19-16} = Rn;
1289 let Inst{15-12} = 0b0000;
1290 let Inst{11-5} = shift{11-5};
1292 let Inst{3-0} = shift{3-0};
1294 let Unpredictable{15-12} = 0b1111;
1296 def rsr : AI1<opcod, (outs),
1297 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1298 opc, "\t$Rn, $shift",
1299 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1300 Sched<[WriteCMPsr, ReadALU]> {
1305 let Inst{19-16} = Rn;
1306 let Inst{15-12} = 0b0000;
1307 let Inst{11-8} = shift{11-8};
1309 let Inst{6-5} = shift{6-5};
1311 let Inst{3-0} = shift{3-0};
1313 let Unpredictable{15-12} = 0b1111;
1319 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1320 /// register and one whose operand is a register rotated by 8/16/24.
1321 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1322 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1323 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1324 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1325 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1326 Requires<[IsARM, HasV6]> {
1330 let Inst{19-16} = 0b1111;
1331 let Inst{15-12} = Rd;
1332 let Inst{11-10} = rot;
1336 class AI_ext_rrot_np<bits<8> opcod, string opc>
1337 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1338 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1339 Requires<[IsARM, HasV6]> {
1341 let Inst{19-16} = 0b1111;
1342 let Inst{11-10} = rot;
1345 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1346 /// register and one whose operand is a register rotated by 8/16/24.
1347 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1348 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1349 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1350 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1351 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1352 Requires<[IsARM, HasV6]> {
1357 let Inst{19-16} = Rn;
1358 let Inst{15-12} = Rd;
1359 let Inst{11-10} = rot;
1360 let Inst{9-4} = 0b000111;
1364 class AI_exta_rrot_np<bits<8> opcod, string opc>
1365 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1366 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1367 Requires<[IsARM, HasV6]> {
1370 let Inst{19-16} = Rn;
1371 let Inst{11-10} = rot;
1374 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1375 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1376 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1377 bit Commutable = 0> {
1378 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1379 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1380 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1381 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1383 Sched<[WriteALU, ReadALU]> {
1388 let Inst{15-12} = Rd;
1389 let Inst{19-16} = Rn;
1390 let Inst{11-0} = imm;
1392 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1393 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1394 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1396 Sched<[WriteALU, ReadALU, ReadALU]> {
1400 let Inst{11-4} = 0b00000000;
1402 let isCommutable = Commutable;
1404 let Inst{15-12} = Rd;
1405 let Inst{19-16} = Rn;
1407 def rsi : AsI1<opcod, (outs GPR:$Rd),
1408 (ins GPR:$Rn, so_reg_imm:$shift),
1409 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1410 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1412 Sched<[WriteALUsi, ReadALU]> {
1417 let Inst{19-16} = Rn;
1418 let Inst{15-12} = Rd;
1419 let Inst{11-5} = shift{11-5};
1421 let Inst{3-0} = shift{3-0};
1423 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1424 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1425 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1426 [(set GPRnopc:$Rd, CPSR,
1427 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1429 Sched<[WriteALUsr, ReadALUsr]> {
1434 let Inst{19-16} = Rn;
1435 let Inst{15-12} = Rd;
1436 let Inst{11-8} = shift{11-8};
1438 let Inst{6-5} = shift{6-5};
1440 let Inst{3-0} = shift{3-0};
1445 /// AI1_rsc_irs - Define instructions and patterns for rsc
1446 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1447 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1448 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1449 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1450 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1451 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1453 Sched<[WriteALU, ReadALU]> {
1458 let Inst{15-12} = Rd;
1459 let Inst{19-16} = Rn;
1460 let Inst{11-0} = imm;
1462 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1463 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1464 [/* pattern left blank */]>,
1465 Sched<[WriteALU, ReadALU, ReadALU]> {
1469 let Inst{11-4} = 0b00000000;
1472 let Inst{15-12} = Rd;
1473 let Inst{19-16} = Rn;
1475 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1476 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1477 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1479 Sched<[WriteALUsi, ReadALU]> {
1484 let Inst{19-16} = Rn;
1485 let Inst{15-12} = Rd;
1486 let Inst{11-5} = shift{11-5};
1488 let Inst{3-0} = shift{3-0};
1490 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1491 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1492 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1494 Sched<[WriteALUsr, ReadALUsr]> {
1499 let Inst{19-16} = Rn;
1500 let Inst{15-12} = Rd;
1501 let Inst{11-8} = shift{11-8};
1503 let Inst{6-5} = shift{6-5};
1505 let Inst{3-0} = shift{3-0};
1510 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1511 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1512 InstrItinClass iir, PatFrag opnode> {
1513 // Note: We use the complex addrmode_imm12 rather than just an input
1514 // GPR and a constrained immediate so that we can use this to match
1515 // frame index references and avoid matching constant pool references.
1516 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1517 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1518 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1521 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1522 let Inst{19-16} = addr{16-13}; // Rn
1523 let Inst{15-12} = Rt;
1524 let Inst{11-0} = addr{11-0}; // imm12
1526 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1527 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1528 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1531 let shift{4} = 0; // Inst{4} = 0
1532 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1533 let Inst{19-16} = shift{16-13}; // Rn
1534 let Inst{15-12} = Rt;
1535 let Inst{11-0} = shift{11-0};
1540 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1541 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1542 InstrItinClass iir, PatFrag opnode> {
1543 // Note: We use the complex addrmode_imm12 rather than just an input
1544 // GPR and a constrained immediate so that we can use this to match
1545 // frame index references and avoid matching constant pool references.
1546 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1547 (ins addrmode_imm12:$addr),
1548 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1549 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1552 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1553 let Inst{19-16} = addr{16-13}; // Rn
1554 let Inst{15-12} = Rt;
1555 let Inst{11-0} = addr{11-0}; // imm12
1557 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1558 (ins ldst_so_reg:$shift),
1559 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1560 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1563 let shift{4} = 0; // Inst{4} = 0
1564 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1565 let Inst{19-16} = shift{16-13}; // Rn
1566 let Inst{15-12} = Rt;
1567 let Inst{11-0} = shift{11-0};
1573 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1574 InstrItinClass iir, PatFrag opnode> {
1575 // Note: We use the complex addrmode_imm12 rather than just an input
1576 // GPR and a constrained immediate so that we can use this to match
1577 // frame index references and avoid matching constant pool references.
1578 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1579 (ins GPR:$Rt, addrmode_imm12:$addr),
1580 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1581 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1584 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1585 let Inst{19-16} = addr{16-13}; // Rn
1586 let Inst{15-12} = Rt;
1587 let Inst{11-0} = addr{11-0}; // imm12
1589 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1590 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1591 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1594 let shift{4} = 0; // Inst{4} = 0
1595 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1596 let Inst{19-16} = shift{16-13}; // Rn
1597 let Inst{15-12} = Rt;
1598 let Inst{11-0} = shift{11-0};
1602 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1603 InstrItinClass iir, PatFrag opnode> {
1604 // Note: We use the complex addrmode_imm12 rather than just an input
1605 // GPR and a constrained immediate so that we can use this to match
1606 // frame index references and avoid matching constant pool references.
1607 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1608 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1609 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1610 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1613 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1614 let Inst{19-16} = addr{16-13}; // Rn
1615 let Inst{15-12} = Rt;
1616 let Inst{11-0} = addr{11-0}; // imm12
1618 def rs : AI2ldst<0b011, 0, isByte, (outs),
1619 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1620 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1621 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1624 let shift{4} = 0; // Inst{4} = 0
1625 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1626 let Inst{19-16} = shift{16-13}; // Rn
1627 let Inst{15-12} = Rt;
1628 let Inst{11-0} = shift{11-0};
1633 //===----------------------------------------------------------------------===//
1635 //===----------------------------------------------------------------------===//
1637 //===----------------------------------------------------------------------===//
1638 // Miscellaneous Instructions.
1641 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1642 /// the function. The first operand is the ID# for this instruction, the second
1643 /// is the index into the MachineConstantPool that this is, the third is the
1644 /// size in bytes of this constant pool entry.
1645 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1646 def CONSTPOOL_ENTRY :
1647 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1648 i32imm:$size), NoItinerary, []>;
1650 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1651 // from removing one half of the matched pairs. That breaks PEI, which assumes
1652 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1653 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1654 def ADJCALLSTACKUP :
1655 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1656 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1658 def ADJCALLSTACKDOWN :
1659 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1660 [(ARMcallseq_start timm:$amt)]>;
1663 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1664 // (These pseudos use a hand-written selection code).
1665 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1666 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1667 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1669 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1670 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1672 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1673 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1675 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1676 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1678 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1679 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1681 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1682 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1684 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1685 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1687 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1688 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1689 GPR:$set1, GPR:$set2),
1691 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1692 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1694 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1695 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1697 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1698 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1700 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1701 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1705 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1706 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1708 let Inst{27-3} = 0b0011001000001111000000000;
1709 let Inst{2-0} = imm;
1712 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1713 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1714 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1715 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1716 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1718 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1719 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1724 let Inst{15-12} = Rd;
1725 let Inst{19-16} = Rn;
1726 let Inst{27-20} = 0b01101000;
1727 let Inst{7-4} = 0b1011;
1728 let Inst{11-8} = 0b1111;
1729 let Unpredictable{11-8} = 0b1111;
1732 // The 16-bit operand $val can be used by a debugger to store more information
1733 // about the breakpoint.
1734 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1735 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1737 let Inst{3-0} = val{3-0};
1738 let Inst{19-8} = val{15-4};
1739 let Inst{27-20} = 0b00010010;
1740 let Inst{7-4} = 0b0111;
1743 // Change Processor State
1744 // FIXME: We should use InstAlias to handle the optional operands.
1745 class CPS<dag iops, string asm_ops>
1746 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1747 []>, Requires<[IsARM]> {
1753 let Inst{31-28} = 0b1111;
1754 let Inst{27-20} = 0b00010000;
1755 let Inst{19-18} = imod;
1756 let Inst{17} = M; // Enabled if mode is set;
1757 let Inst{16-9} = 0b00000000;
1758 let Inst{8-6} = iflags;
1760 let Inst{4-0} = mode;
1763 let DecoderMethod = "DecodeCPSInstruction" in {
1765 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1766 "$imod\t$iflags, $mode">;
1767 let mode = 0, M = 0 in
1768 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1770 let imod = 0, iflags = 0, M = 1 in
1771 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1774 // Preload signals the memory system of possible future data/instruction access.
1775 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1777 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1778 !strconcat(opc, "\t$addr"),
1779 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1782 let Inst{31-26} = 0b111101;
1783 let Inst{25} = 0; // 0 for immediate form
1784 let Inst{24} = data;
1785 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1786 let Inst{22} = read;
1787 let Inst{21-20} = 0b01;
1788 let Inst{19-16} = addr{16-13}; // Rn
1789 let Inst{15-12} = 0b1111;
1790 let Inst{11-0} = addr{11-0}; // imm12
1793 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1794 !strconcat(opc, "\t$shift"),
1795 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1797 let Inst{31-26} = 0b111101;
1798 let Inst{25} = 1; // 1 for register form
1799 let Inst{24} = data;
1800 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1801 let Inst{22} = read;
1802 let Inst{21-20} = 0b01;
1803 let Inst{19-16} = shift{16-13}; // Rn
1804 let Inst{15-12} = 0b1111;
1805 let Inst{11-0} = shift{11-0};
1810 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1811 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1812 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1814 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1815 "setend\t$end", []>, Requires<[IsARM]> {
1817 let Inst{31-10} = 0b1111000100000001000000;
1822 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1823 []>, Requires<[IsARM, HasV7]> {
1825 let Inst{27-4} = 0b001100100000111100001111;
1826 let Inst{3-0} = opt;
1830 * A5.4 Permanently UNDEFINED instructions.
1832 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1833 * Other UDF encodings generate SIGILL.
1835 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1837 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1839 * 1101 1110 iiii iiii
1840 * It uses the following encoding:
1841 * 1110 0111 1111 1110 1101 1110 1111 0000
1842 * - In ARM: UDF #60896;
1843 * - In Thumb: UDF #254 followed by a branch-to-self.
1845 let isBarrier = 1, isTerminator = 1 in
1846 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1848 Requires<[IsARM,UseNaClTrap]> {
1849 let Inst = 0xe7fedef0;
1851 let isBarrier = 1, isTerminator = 1 in
1852 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1854 Requires<[IsARM,DontUseNaClTrap]> {
1855 let Inst = 0xe7ffdefe;
1858 // Address computation and loads and stores in PIC mode.
1859 let isNotDuplicable = 1 in {
1860 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1862 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1864 let AddedComplexity = 10 in {
1865 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1867 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1869 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1871 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1873 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1875 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1877 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1879 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1881 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1883 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1885 let AddedComplexity = 10 in {
1886 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1887 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1889 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1890 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1891 addrmodepc:$addr)]>;
1893 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1894 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1896 } // isNotDuplicable = 1
1899 // LEApcrel - Load a pc-relative address into a register without offending the
1901 let neverHasSideEffects = 1, isReMaterializable = 1 in
1902 // The 'adr' mnemonic encodes differently if the label is before or after
1903 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1904 // know until then which form of the instruction will be used.
1905 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1906 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1907 Sched<[WriteALU, ReadALU]> {
1910 let Inst{27-25} = 0b001;
1912 let Inst{23-22} = label{13-12};
1915 let Inst{19-16} = 0b1111;
1916 let Inst{15-12} = Rd;
1917 let Inst{11-0} = label{11-0};
1920 let hasSideEffects = 1 in {
1921 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1924 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1925 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1929 //===----------------------------------------------------------------------===//
1930 // Control Flow Instructions.
1933 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1935 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1936 "bx", "\tlr", [(ARMretflag)]>,
1937 Requires<[IsARM, HasV4T]> {
1938 let Inst{27-0} = 0b0001001011111111111100011110;
1942 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1943 "mov", "\tpc, lr", [(ARMretflag)]>,
1944 Requires<[IsARM, NoV4T]> {
1945 let Inst{27-0} = 0b0001101000001111000000001110;
1949 // Indirect branches
1950 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1952 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1953 [(brind GPR:$dst)]>,
1954 Requires<[IsARM, HasV4T]> {
1956 let Inst{31-4} = 0b1110000100101111111111110001;
1957 let Inst{3-0} = dst;
1960 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1961 "bx", "\t$dst", [/* pattern left blank */]>,
1962 Requires<[IsARM, HasV4T]> {
1964 let Inst{27-4} = 0b000100101111111111110001;
1965 let Inst{3-0} = dst;
1969 // SP is marked as a use to prevent stack-pointer assignments that appear
1970 // immediately before calls from potentially appearing dead.
1972 // FIXME: Do we really need a non-predicated version? If so, it should
1973 // at least be a pseudo instruction expanding to the predicated version
1974 // at MC lowering time.
1975 Defs = [LR], Uses = [SP] in {
1976 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1977 IIC_Br, "bl\t$func",
1978 [(ARMcall tglobaladdr:$func)]>,
1980 let Inst{31-28} = 0b1110;
1982 let Inst{23-0} = func;
1983 let DecoderMethod = "DecodeBranchImmInstruction";
1986 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1987 IIC_Br, "bl", "\t$func",
1988 [(ARMcall_pred tglobaladdr:$func)]>,
1991 let Inst{23-0} = func;
1992 let DecoderMethod = "DecodeBranchImmInstruction";
1996 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1997 IIC_Br, "blx\t$func",
1998 [(ARMcall GPR:$func)]>,
1999 Requires<[IsARM, HasV5T]> {
2001 let Inst{31-4} = 0b1110000100101111111111110011;
2002 let Inst{3-0} = func;
2005 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2006 IIC_Br, "blx", "\t$func",
2007 [(ARMcall_pred GPR:$func)]>,
2008 Requires<[IsARM, HasV5T]> {
2010 let Inst{27-4} = 0b000100101111111111110011;
2011 let Inst{3-0} = func;
2015 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2016 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2017 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2018 Requires<[IsARM, HasV4T]>;
2021 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2022 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2023 Requires<[IsARM, NoV4T]>;
2025 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2026 // return stack predictor.
2027 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2028 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2032 let isBranch = 1, isTerminator = 1 in {
2033 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2034 // a two-value operand where a dag node expects two operands. :(
2035 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2036 IIC_Br, "b", "\t$target",
2037 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2039 let Inst{23-0} = target;
2040 let DecoderMethod = "DecodeBranchImmInstruction";
2043 let isBarrier = 1 in {
2044 // B is "predicable" since it's just a Bcc with an 'always' condition.
2045 let isPredicable = 1 in
2046 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2047 // should be sufficient.
2048 // FIXME: Is B really a Barrier? That doesn't seem right.
2049 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2050 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2052 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2053 def BR_JTr : ARMPseudoInst<(outs),
2054 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2056 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2057 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2058 // into i12 and rs suffixed versions.
2059 def BR_JTm : ARMPseudoInst<(outs),
2060 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2062 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2064 def BR_JTadd : ARMPseudoInst<(outs),
2065 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2067 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2069 } // isNotDuplicable = 1, isIndirectBranch = 1
2075 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2076 "blx\t$target", []>,
2077 Requires<[IsARM, HasV5T]> {
2078 let Inst{31-25} = 0b1111101;
2080 let Inst{23-0} = target{24-1};
2081 let Inst{24} = target{0};
2084 // Branch and Exchange Jazelle
2085 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2086 [/* pattern left blank */]> {
2088 let Inst{23-20} = 0b0010;
2089 let Inst{19-8} = 0xfff;
2090 let Inst{7-4} = 0b0010;
2091 let Inst{3-0} = func;
2096 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2097 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2099 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2101 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2103 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2106 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2112 // Secure Monitor Call is a system instruction.
2113 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2114 []>, Requires<[IsARM, HasTrustZone]> {
2116 let Inst{23-4} = 0b01100000000000000111;
2117 let Inst{3-0} = opt;
2120 // Supervisor Call (Software Interrupt)
2121 let isCall = 1, Uses = [SP] in {
2122 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2124 let Inst{23-0} = svc;
2128 // Store Return State
2129 class SRSI<bit wb, string asm>
2130 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2131 NoItinerary, asm, "", []> {
2133 let Inst{31-28} = 0b1111;
2134 let Inst{27-25} = 0b100;
2138 let Inst{19-16} = 0b1101; // SP
2139 let Inst{15-5} = 0b00000101000;
2140 let Inst{4-0} = mode;
2143 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2144 let Inst{24-23} = 0;
2146 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2147 let Inst{24-23} = 0;
2149 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2150 let Inst{24-23} = 0b10;
2152 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2153 let Inst{24-23} = 0b10;
2155 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2156 let Inst{24-23} = 0b01;
2158 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2159 let Inst{24-23} = 0b01;
2161 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2162 let Inst{24-23} = 0b11;
2164 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2165 let Inst{24-23} = 0b11;
2168 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2169 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2171 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2172 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2174 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2175 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2177 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2178 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2180 // Return From Exception
2181 class RFEI<bit wb, string asm>
2182 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2183 NoItinerary, asm, "", []> {
2185 let Inst{31-28} = 0b1111;
2186 let Inst{27-25} = 0b100;
2190 let Inst{19-16} = Rn;
2191 let Inst{15-0} = 0xa00;
2194 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2195 let Inst{24-23} = 0;
2197 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2198 let Inst{24-23} = 0;
2200 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2201 let Inst{24-23} = 0b10;
2203 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2204 let Inst{24-23} = 0b10;
2206 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2207 let Inst{24-23} = 0b01;
2209 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2210 let Inst{24-23} = 0b01;
2212 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2213 let Inst{24-23} = 0b11;
2215 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2216 let Inst{24-23} = 0b11;
2219 //===----------------------------------------------------------------------===//
2220 // Load / Store Instructions.
2226 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2227 UnOpFrag<(load node:$Src)>>;
2228 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2229 UnOpFrag<(zextloadi8 node:$Src)>>;
2230 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2231 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2232 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2233 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2235 // Special LDR for loads from non-pc-relative constpools.
2236 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2237 isReMaterializable = 1, isCodeGenOnly = 1 in
2238 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2239 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2243 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2244 let Inst{19-16} = 0b1111;
2245 let Inst{15-12} = Rt;
2246 let Inst{11-0} = addr{11-0}; // imm12
2249 // Loads with zero extension
2250 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2251 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2252 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2254 // Loads with sign extension
2255 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2256 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2257 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2259 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2260 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2261 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2263 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2265 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2266 (ins addrmode3:$addr), LdMiscFrm,
2267 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2268 []>, Requires<[IsARM, HasV5TE]>;
2272 multiclass AI2_ldridx<bit isByte, string opc,
2273 InstrItinClass iii, InstrItinClass iir> {
2274 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2275 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2276 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2279 let Inst{23} = addr{12};
2280 let Inst{19-16} = addr{16-13};
2281 let Inst{11-0} = addr{11-0};
2282 let DecoderMethod = "DecodeLDRPreImm";
2283 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2286 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2287 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2288 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2291 let Inst{23} = addr{12};
2292 let Inst{19-16} = addr{16-13};
2293 let Inst{11-0} = addr{11-0};
2295 let DecoderMethod = "DecodeLDRPreReg";
2296 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2299 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2300 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2301 IndexModePost, LdFrm, iir,
2302 opc, "\t$Rt, $addr, $offset",
2303 "$addr.base = $Rn_wb", []> {
2309 let Inst{23} = offset{12};
2310 let Inst{19-16} = addr;
2311 let Inst{11-0} = offset{11-0};
2313 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2316 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2317 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2318 IndexModePost, LdFrm, iii,
2319 opc, "\t$Rt, $addr, $offset",
2320 "$addr.base = $Rn_wb", []> {
2326 let Inst{23} = offset{12};
2327 let Inst{19-16} = addr;
2328 let Inst{11-0} = offset{11-0};
2330 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2335 let mayLoad = 1, neverHasSideEffects = 1 in {
2336 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2337 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2338 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2339 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2342 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2343 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2344 (ins addrmode3_pre:$addr), IndexModePre,
2346 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2348 let Inst{23} = addr{8}; // U bit
2349 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2350 let Inst{19-16} = addr{12-9}; // Rn
2351 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2352 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2353 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2354 let DecoderMethod = "DecodeAddrMode3Instruction";
2356 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2357 (ins addr_offset_none:$addr, am3offset:$offset),
2358 IndexModePost, LdMiscFrm, itin,
2359 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2363 let Inst{23} = offset{8}; // U bit
2364 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2365 let Inst{19-16} = addr;
2366 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2367 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2368 let DecoderMethod = "DecodeAddrMode3Instruction";
2372 let mayLoad = 1, neverHasSideEffects = 1 in {
2373 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2374 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2375 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2376 let hasExtraDefRegAllocReq = 1 in {
2377 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2378 (ins addrmode3_pre:$addr), IndexModePre,
2379 LdMiscFrm, IIC_iLoad_d_ru,
2380 "ldrd", "\t$Rt, $Rt2, $addr!",
2381 "$addr.base = $Rn_wb", []> {
2383 let Inst{23} = addr{8}; // U bit
2384 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2385 let Inst{19-16} = addr{12-9}; // Rn
2386 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2387 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2388 let DecoderMethod = "DecodeAddrMode3Instruction";
2389 let AsmMatchConverter = "cvtLdrdPre";
2391 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2392 (ins addr_offset_none:$addr, am3offset:$offset),
2393 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2394 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2395 "$addr.base = $Rn_wb", []> {
2398 let Inst{23} = offset{8}; // U bit
2399 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2400 let Inst{19-16} = addr;
2401 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2402 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2403 let DecoderMethod = "DecodeAddrMode3Instruction";
2405 } // hasExtraDefRegAllocReq = 1
2406 } // mayLoad = 1, neverHasSideEffects = 1
2408 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2409 let mayLoad = 1, neverHasSideEffects = 1 in {
2410 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2411 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2412 IndexModePost, LdFrm, IIC_iLoad_ru,
2413 "ldrt", "\t$Rt, $addr, $offset",
2414 "$addr.base = $Rn_wb", []> {
2420 let Inst{23} = offset{12};
2421 let Inst{21} = 1; // overwrite
2422 let Inst{19-16} = addr;
2423 let Inst{11-5} = offset{11-5};
2425 let Inst{3-0} = offset{3-0};
2426 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2429 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2430 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2431 IndexModePost, LdFrm, IIC_iLoad_ru,
2432 "ldrt", "\t$Rt, $addr, $offset",
2433 "$addr.base = $Rn_wb", []> {
2439 let Inst{23} = offset{12};
2440 let Inst{21} = 1; // overwrite
2441 let Inst{19-16} = addr;
2442 let Inst{11-0} = offset{11-0};
2443 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2446 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2447 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2448 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2449 "ldrbt", "\t$Rt, $addr, $offset",
2450 "$addr.base = $Rn_wb", []> {
2456 let Inst{23} = offset{12};
2457 let Inst{21} = 1; // overwrite
2458 let Inst{19-16} = addr;
2459 let Inst{11-5} = offset{11-5};
2461 let Inst{3-0} = offset{3-0};
2462 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2465 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2466 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2467 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2468 "ldrbt", "\t$Rt, $addr, $offset",
2469 "$addr.base = $Rn_wb", []> {
2475 let Inst{23} = offset{12};
2476 let Inst{21} = 1; // overwrite
2477 let Inst{19-16} = addr;
2478 let Inst{11-0} = offset{11-0};
2479 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2482 multiclass AI3ldrT<bits<4> op, string opc> {
2483 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2484 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2485 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2486 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2488 let Inst{23} = offset{8};
2490 let Inst{11-8} = offset{7-4};
2491 let Inst{3-0} = offset{3-0};
2492 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2494 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2495 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2496 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2497 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2499 let Inst{23} = Rm{4};
2502 let Unpredictable{11-8} = 0b1111;
2503 let Inst{3-0} = Rm{3-0};
2504 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2505 let DecoderMethod = "DecodeLDR";
2509 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2510 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2511 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2516 // Stores with truncate
2517 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2518 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2519 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2522 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2523 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2524 StMiscFrm, IIC_iStore_d_r,
2525 "strd", "\t$Rt, $src2, $addr", []>,
2526 Requires<[IsARM, HasV5TE]> {
2531 multiclass AI2_stridx<bit isByte, string opc,
2532 InstrItinClass iii, InstrItinClass iir> {
2533 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2534 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2536 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2539 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2540 let Inst{19-16} = addr{16-13}; // Rn
2541 let Inst{11-0} = addr{11-0}; // imm12
2542 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2543 let DecoderMethod = "DecodeSTRPreImm";
2546 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2547 (ins GPR:$Rt, ldst_so_reg:$addr),
2548 IndexModePre, StFrm, iir,
2549 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2552 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2553 let Inst{19-16} = addr{16-13}; // Rn
2554 let Inst{11-0} = addr{11-0};
2555 let Inst{4} = 0; // Inst{4} = 0
2556 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2557 let DecoderMethod = "DecodeSTRPreReg";
2559 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2560 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2561 IndexModePost, StFrm, iir,
2562 opc, "\t$Rt, $addr, $offset",
2563 "$addr.base = $Rn_wb", []> {
2569 let Inst{23} = offset{12};
2570 let Inst{19-16} = addr;
2571 let Inst{11-0} = offset{11-0};
2574 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2577 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2578 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2579 IndexModePost, StFrm, iii,
2580 opc, "\t$Rt, $addr, $offset",
2581 "$addr.base = $Rn_wb", []> {
2587 let Inst{23} = offset{12};
2588 let Inst{19-16} = addr;
2589 let Inst{11-0} = offset{11-0};
2591 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2595 let mayStore = 1, neverHasSideEffects = 1 in {
2596 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2597 // IIC_iStore_siu depending on whether it the offset register is shifted.
2598 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2599 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2602 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2603 am2offset_reg:$offset),
2604 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2605 am2offset_reg:$offset)>;
2606 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2607 am2offset_imm:$offset),
2608 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2609 am2offset_imm:$offset)>;
2610 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2611 am2offset_reg:$offset),
2612 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2613 am2offset_reg:$offset)>;
2614 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2615 am2offset_imm:$offset),
2616 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2617 am2offset_imm:$offset)>;
2619 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2620 // put the patterns on the instruction definitions directly as ISel wants
2621 // the address base and offset to be separate operands, not a single
2622 // complex operand like we represent the instructions themselves. The
2623 // pseudos map between the two.
2624 let usesCustomInserter = 1,
2625 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2626 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2627 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2630 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2631 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2632 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2635 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2636 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2637 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2640 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2641 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2642 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2645 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2646 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2647 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2650 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2655 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2656 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2657 StMiscFrm, IIC_iStore_bh_ru,
2658 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2660 let Inst{23} = addr{8}; // U bit
2661 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2662 let Inst{19-16} = addr{12-9}; // Rn
2663 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2664 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2665 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2666 let DecoderMethod = "DecodeAddrMode3Instruction";
2669 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2670 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2671 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2672 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2673 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2674 addr_offset_none:$addr,
2675 am3offset:$offset))]> {
2678 let Inst{23} = offset{8}; // U bit
2679 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2680 let Inst{19-16} = addr;
2681 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2682 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2683 let DecoderMethod = "DecodeAddrMode3Instruction";
2686 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2687 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2688 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2689 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2690 "strd", "\t$Rt, $Rt2, $addr!",
2691 "$addr.base = $Rn_wb", []> {
2693 let Inst{23} = addr{8}; // U bit
2694 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2695 let Inst{19-16} = addr{12-9}; // Rn
2696 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2697 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2698 let DecoderMethod = "DecodeAddrMode3Instruction";
2699 let AsmMatchConverter = "cvtStrdPre";
2702 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2703 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2705 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2706 "strd", "\t$Rt, $Rt2, $addr, $offset",
2707 "$addr.base = $Rn_wb", []> {
2710 let Inst{23} = offset{8}; // U bit
2711 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2712 let Inst{19-16} = addr;
2713 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2714 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2715 let DecoderMethod = "DecodeAddrMode3Instruction";
2717 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2719 // STRT, STRBT, and STRHT
2721 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2722 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2723 IndexModePost, StFrm, IIC_iStore_bh_ru,
2724 "strbt", "\t$Rt, $addr, $offset",
2725 "$addr.base = $Rn_wb", []> {
2731 let Inst{23} = offset{12};
2732 let Inst{21} = 1; // overwrite
2733 let Inst{19-16} = addr;
2734 let Inst{11-5} = offset{11-5};
2736 let Inst{3-0} = offset{3-0};
2737 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2740 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2741 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2742 IndexModePost, StFrm, IIC_iStore_bh_ru,
2743 "strbt", "\t$Rt, $addr, $offset",
2744 "$addr.base = $Rn_wb", []> {
2750 let Inst{23} = offset{12};
2751 let Inst{21} = 1; // overwrite
2752 let Inst{19-16} = addr;
2753 let Inst{11-0} = offset{11-0};
2754 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2757 let mayStore = 1, neverHasSideEffects = 1 in {
2758 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2759 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2760 IndexModePost, StFrm, IIC_iStore_ru,
2761 "strt", "\t$Rt, $addr, $offset",
2762 "$addr.base = $Rn_wb", []> {
2768 let Inst{23} = offset{12};
2769 let Inst{21} = 1; // overwrite
2770 let Inst{19-16} = addr;
2771 let Inst{11-5} = offset{11-5};
2773 let Inst{3-0} = offset{3-0};
2774 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2777 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2778 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2779 IndexModePost, StFrm, IIC_iStore_ru,
2780 "strt", "\t$Rt, $addr, $offset",
2781 "$addr.base = $Rn_wb", []> {
2787 let Inst{23} = offset{12};
2788 let Inst{21} = 1; // overwrite
2789 let Inst{19-16} = addr;
2790 let Inst{11-0} = offset{11-0};
2791 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2796 multiclass AI3strT<bits<4> op, string opc> {
2797 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2798 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2799 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2800 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2802 let Inst{23} = offset{8};
2804 let Inst{11-8} = offset{7-4};
2805 let Inst{3-0} = offset{3-0};
2806 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2808 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2809 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2810 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2811 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2813 let Inst{23} = Rm{4};
2816 let Inst{3-0} = Rm{3-0};
2817 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2822 defm STRHT : AI3strT<0b1011, "strht">;
2825 //===----------------------------------------------------------------------===//
2826 // Load / store multiple Instructions.
2829 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2830 InstrItinClass itin, InstrItinClass itin_upd> {
2831 // IA is the default, so no need for an explicit suffix on the
2832 // mnemonic here. Without it is the canonical spelling.
2834 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2835 IndexModeNone, f, itin,
2836 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2837 let Inst{24-23} = 0b01; // Increment After
2838 let Inst{22} = P_bit;
2839 let Inst{21} = 0; // No writeback
2840 let Inst{20} = L_bit;
2843 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2844 IndexModeUpd, f, itin_upd,
2845 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2846 let Inst{24-23} = 0b01; // Increment After
2847 let Inst{22} = P_bit;
2848 let Inst{21} = 1; // Writeback
2849 let Inst{20} = L_bit;
2851 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2854 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2855 IndexModeNone, f, itin,
2856 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2857 let Inst{24-23} = 0b00; // Decrement After
2858 let Inst{22} = P_bit;
2859 let Inst{21} = 0; // No writeback
2860 let Inst{20} = L_bit;
2863 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2864 IndexModeUpd, f, itin_upd,
2865 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2866 let Inst{24-23} = 0b00; // Decrement After
2867 let Inst{22} = P_bit;
2868 let Inst{21} = 1; // Writeback
2869 let Inst{20} = L_bit;
2871 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2874 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2875 IndexModeNone, f, itin,
2876 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2877 let Inst{24-23} = 0b10; // Decrement Before
2878 let Inst{22} = P_bit;
2879 let Inst{21} = 0; // No writeback
2880 let Inst{20} = L_bit;
2883 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2884 IndexModeUpd, f, itin_upd,
2885 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2886 let Inst{24-23} = 0b10; // Decrement Before
2887 let Inst{22} = P_bit;
2888 let Inst{21} = 1; // Writeback
2889 let Inst{20} = L_bit;
2891 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2894 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2895 IndexModeNone, f, itin,
2896 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2897 let Inst{24-23} = 0b11; // Increment Before
2898 let Inst{22} = P_bit;
2899 let Inst{21} = 0; // No writeback
2900 let Inst{20} = L_bit;
2903 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2904 IndexModeUpd, f, itin_upd,
2905 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2906 let Inst{24-23} = 0b11; // Increment Before
2907 let Inst{22} = P_bit;
2908 let Inst{21} = 1; // Writeback
2909 let Inst{20} = L_bit;
2911 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2915 let neverHasSideEffects = 1 in {
2917 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2918 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2921 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2922 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2925 } // neverHasSideEffects
2927 // FIXME: remove when we have a way to marking a MI with these properties.
2928 // FIXME: Should pc be an implicit operand like PICADD, etc?
2929 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2930 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2931 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2932 reglist:$regs, variable_ops),
2933 4, IIC_iLoad_mBr, [],
2934 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2935 RegConstraint<"$Rn = $wb">;
2937 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2938 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2941 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2942 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2947 //===----------------------------------------------------------------------===//
2948 // Move Instructions.
2951 let neverHasSideEffects = 1 in
2952 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2953 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2957 let Inst{19-16} = 0b0000;
2958 let Inst{11-4} = 0b00000000;
2961 let Inst{15-12} = Rd;
2964 // A version for the smaller set of tail call registers.
2965 let neverHasSideEffects = 1 in
2966 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2967 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2971 let Inst{11-4} = 0b00000000;
2974 let Inst{15-12} = Rd;
2977 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2978 DPSoRegRegFrm, IIC_iMOVsr,
2979 "mov", "\t$Rd, $src",
2980 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2983 let Inst{15-12} = Rd;
2984 let Inst{19-16} = 0b0000;
2985 let Inst{11-8} = src{11-8};
2987 let Inst{6-5} = src{6-5};
2989 let Inst{3-0} = src{3-0};
2993 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2994 DPSoRegImmFrm, IIC_iMOVsr,
2995 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2999 let Inst{15-12} = Rd;
3000 let Inst{19-16} = 0b0000;
3001 let Inst{11-5} = src{11-5};
3003 let Inst{3-0} = src{3-0};
3007 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3008 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3009 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
3013 let Inst{15-12} = Rd;
3014 let Inst{19-16} = 0b0000;
3015 let Inst{11-0} = imm;
3018 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3019 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3021 "movw", "\t$Rd, $imm",
3022 [(set GPR:$Rd, imm0_65535:$imm)]>,
3023 Requires<[IsARM, HasV6T2]>, UnaryDP {
3026 let Inst{15-12} = Rd;
3027 let Inst{11-0} = imm{11-0};
3028 let Inst{19-16} = imm{15-12};
3031 let DecoderMethod = "DecodeArmMOVTWInstruction";
3034 def : InstAlias<"mov${p} $Rd, $imm",
3035 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3038 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3039 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3041 let Constraints = "$src = $Rd" in {
3042 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3043 (ins GPR:$src, imm0_65535_expr:$imm),
3045 "movt", "\t$Rd, $imm",
3047 (or (and GPR:$src, 0xffff),
3048 lo16AllZero:$imm))]>, UnaryDP,
3049 Requires<[IsARM, HasV6T2]> {
3052 let Inst{15-12} = Rd;
3053 let Inst{11-0} = imm{11-0};
3054 let Inst{19-16} = imm{15-12};
3057 let DecoderMethod = "DecodeArmMOVTWInstruction";
3060 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3061 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3065 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3066 Requires<[IsARM, HasV6T2]>;
3068 let Uses = [CPSR] in
3069 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3070 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3073 // These aren't really mov instructions, but we have to define them this way
3074 // due to flag operands.
3076 let Defs = [CPSR] in {
3077 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3078 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3080 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3081 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3085 //===----------------------------------------------------------------------===//
3086 // Extend Instructions.
3091 def SXTB : AI_ext_rrot<0b01101010,
3092 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3093 def SXTH : AI_ext_rrot<0b01101011,
3094 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3096 def SXTAB : AI_exta_rrot<0b01101010,
3097 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3098 def SXTAH : AI_exta_rrot<0b01101011,
3099 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3101 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3103 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3107 let AddedComplexity = 16 in {
3108 def UXTB : AI_ext_rrot<0b01101110,
3109 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3110 def UXTH : AI_ext_rrot<0b01101111,
3111 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3112 def UXTB16 : AI_ext_rrot<0b01101100,
3113 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3115 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3116 // The transformation should probably be done as a combiner action
3117 // instead so we can include a check for masking back in the upper
3118 // eight bits of the source into the lower eight bits of the result.
3119 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3120 // (UXTB16r_rot GPR:$Src, 3)>;
3121 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3122 (UXTB16 GPR:$Src, 1)>;
3124 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3125 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3126 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3127 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3130 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3131 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3134 def SBFX : I<(outs GPRnopc:$Rd),
3135 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3136 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3137 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3138 Requires<[IsARM, HasV6T2]> {
3143 let Inst{27-21} = 0b0111101;
3144 let Inst{6-4} = 0b101;
3145 let Inst{20-16} = width;
3146 let Inst{15-12} = Rd;
3147 let Inst{11-7} = lsb;
3151 def UBFX : I<(outs GPR:$Rd),
3152 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3153 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3154 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3155 Requires<[IsARM, HasV6T2]> {
3160 let Inst{27-21} = 0b0111111;
3161 let Inst{6-4} = 0b101;
3162 let Inst{20-16} = width;
3163 let Inst{15-12} = Rd;
3164 let Inst{11-7} = lsb;
3168 //===----------------------------------------------------------------------===//
3169 // Arithmetic Instructions.
3172 defm ADD : AsI1_bin_irs<0b0100, "add",
3173 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3174 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3175 defm SUB : AsI1_bin_irs<0b0010, "sub",
3176 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3177 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3179 // ADD and SUB with 's' bit set.
3181 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3182 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3183 // AdjustInstrPostInstrSelection where we determine whether or not to
3184 // set the "s" bit based on CPSR liveness.
3186 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3187 // support for an optional CPSR definition that corresponds to the DAG
3188 // node's second value. We can then eliminate the implicit def of CPSR.
3189 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3190 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3191 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3192 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3194 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3195 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3196 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3197 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3199 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3200 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3201 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3203 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3204 // CPSR and the implicit def of CPSR is not needed.
3205 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3206 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3208 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3209 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3211 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3212 // The assume-no-carry-in form uses the negation of the input since add/sub
3213 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3214 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3216 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3217 (SUBri GPR:$src, so_imm_neg:$imm)>;
3218 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3219 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3221 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3222 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3223 Requires<[IsARM, HasV6T2]>;
3224 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3225 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3226 Requires<[IsARM, HasV6T2]>;
3228 // The with-carry-in form matches bitwise not instead of the negation.
3229 // Effectively, the inverse interpretation of the carry flag already accounts
3230 // for part of the negation.
3231 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3232 (SBCri GPR:$src, so_imm_not:$imm)>;
3233 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3234 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3236 // Note: These are implemented in C++ code, because they have to generate
3237 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3239 // (mul X, 2^n+1) -> (add (X << n), X)
3240 // (mul X, 2^n-1) -> (rsb X, (X << n))
3242 // ARM Arithmetic Instruction
3243 // GPR:$dst = GPR:$a op GPR:$b
3244 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3245 list<dag> pattern = [],
3246 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3247 string asm = "\t$Rd, $Rn, $Rm">
3248 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3252 let Inst{27-20} = op27_20;
3253 let Inst{11-4} = op11_4;
3254 let Inst{19-16} = Rn;
3255 let Inst{15-12} = Rd;
3258 let Unpredictable{11-8} = 0b1111;
3261 // Saturating add/subtract
3263 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3264 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3265 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3266 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3267 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3268 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3269 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3270 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3272 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3273 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3276 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3277 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3278 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3279 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3280 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3281 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3282 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3283 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3284 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3285 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3286 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3287 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3289 // Signed/Unsigned add/subtract
3291 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3292 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3293 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3294 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3295 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3296 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3297 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3298 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3299 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3300 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3301 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3302 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3304 // Signed/Unsigned halving add/subtract
3306 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3307 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3308 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3309 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3310 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3311 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3312 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3313 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3314 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3315 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3316 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3317 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3319 // Unsigned Sum of Absolute Differences [and Accumulate].
3321 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3322 MulFrm /* for convenience */, NoItinerary, "usad8",
3323 "\t$Rd, $Rn, $Rm", []>,
3324 Requires<[IsARM, HasV6]> {
3328 let Inst{27-20} = 0b01111000;
3329 let Inst{15-12} = 0b1111;
3330 let Inst{7-4} = 0b0001;
3331 let Inst{19-16} = Rd;
3332 let Inst{11-8} = Rm;
3335 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3336 MulFrm /* for convenience */, NoItinerary, "usada8",
3337 "\t$Rd, $Rn, $Rm, $Ra", []>,
3338 Requires<[IsARM, HasV6]> {
3343 let Inst{27-20} = 0b01111000;
3344 let Inst{7-4} = 0b0001;
3345 let Inst{19-16} = Rd;
3346 let Inst{15-12} = Ra;
3347 let Inst{11-8} = Rm;
3351 // Signed/Unsigned saturate
3353 def SSAT : AI<(outs GPRnopc:$Rd),
3354 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3355 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3360 let Inst{27-21} = 0b0110101;
3361 let Inst{5-4} = 0b01;
3362 let Inst{20-16} = sat_imm;
3363 let Inst{15-12} = Rd;
3364 let Inst{11-7} = sh{4-0};
3365 let Inst{6} = sh{5};
3369 def SSAT16 : AI<(outs GPRnopc:$Rd),
3370 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3371 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3375 let Inst{27-20} = 0b01101010;
3376 let Inst{11-4} = 0b11110011;
3377 let Inst{15-12} = Rd;
3378 let Inst{19-16} = sat_imm;
3382 def USAT : AI<(outs GPRnopc:$Rd),
3383 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3384 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3389 let Inst{27-21} = 0b0110111;
3390 let Inst{5-4} = 0b01;
3391 let Inst{15-12} = Rd;
3392 let Inst{11-7} = sh{4-0};
3393 let Inst{6} = sh{5};
3394 let Inst{20-16} = sat_imm;
3398 def USAT16 : AI<(outs GPRnopc:$Rd),
3399 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3400 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3404 let Inst{27-20} = 0b01101110;
3405 let Inst{11-4} = 0b11110011;
3406 let Inst{15-12} = Rd;
3407 let Inst{19-16} = sat_imm;
3411 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3412 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3413 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3414 (USAT imm:$pos, GPRnopc:$a, 0)>;
3416 //===----------------------------------------------------------------------===//
3417 // Bitwise Instructions.
3420 defm AND : AsI1_bin_irs<0b0000, "and",
3421 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3422 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3423 defm ORR : AsI1_bin_irs<0b1100, "orr",
3424 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3425 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3426 defm EOR : AsI1_bin_irs<0b0001, "eor",
3427 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3428 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3429 defm BIC : AsI1_bin_irs<0b1110, "bic",
3430 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3431 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3433 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3434 // like in the actual instruction encoding. The complexity of mapping the mask
3435 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3436 // instruction description.
3437 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3438 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3439 "bfc", "\t$Rd, $imm", "$src = $Rd",
3440 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3441 Requires<[IsARM, HasV6T2]> {
3444 let Inst{27-21} = 0b0111110;
3445 let Inst{6-0} = 0b0011111;
3446 let Inst{15-12} = Rd;
3447 let Inst{11-7} = imm{4-0}; // lsb
3448 let Inst{20-16} = imm{9-5}; // msb
3451 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3452 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3453 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3454 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3455 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3456 bf_inv_mask_imm:$imm))]>,
3457 Requires<[IsARM, HasV6T2]> {
3461 let Inst{27-21} = 0b0111110;
3462 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3463 let Inst{15-12} = Rd;
3464 let Inst{11-7} = imm{4-0}; // lsb
3465 let Inst{20-16} = imm{9-5}; // width
3469 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3470 "mvn", "\t$Rd, $Rm",
3471 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3475 let Inst{19-16} = 0b0000;
3476 let Inst{11-4} = 0b00000000;
3477 let Inst{15-12} = Rd;
3480 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3481 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3482 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3486 let Inst{19-16} = 0b0000;
3487 let Inst{15-12} = Rd;
3488 let Inst{11-5} = shift{11-5};
3490 let Inst{3-0} = shift{3-0};
3492 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3493 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3494 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3498 let Inst{19-16} = 0b0000;
3499 let Inst{15-12} = Rd;
3500 let Inst{11-8} = shift{11-8};
3502 let Inst{6-5} = shift{6-5};
3504 let Inst{3-0} = shift{3-0};
3506 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3507 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3508 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3509 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3513 let Inst{19-16} = 0b0000;
3514 let Inst{15-12} = Rd;
3515 let Inst{11-0} = imm;
3518 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3519 (BICri GPR:$src, so_imm_not:$imm)>;
3521 //===----------------------------------------------------------------------===//
3522 // Multiply Instructions.
3524 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3525 string opc, string asm, list<dag> pattern>
3526 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3530 let Inst{19-16} = Rd;
3531 let Inst{11-8} = Rm;
3534 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3535 string opc, string asm, list<dag> pattern>
3536 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3541 let Inst{19-16} = RdHi;
3542 let Inst{15-12} = RdLo;
3543 let Inst{11-8} = Rm;
3546 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3547 string opc, string asm, list<dag> pattern>
3548 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3553 let Inst{19-16} = RdHi;
3554 let Inst{15-12} = RdLo;
3555 let Inst{11-8} = Rm;
3559 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3560 // property. Remove them when it's possible to add those properties
3561 // on an individual MachineInstr, not just an instruction description.
3562 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3563 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3564 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3565 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3566 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3567 Requires<[IsARM, HasV6]> {
3568 let Inst{15-12} = 0b0000;
3569 let Unpredictable{15-12} = 0b1111;
3572 let Constraints = "@earlyclobber $Rd" in
3573 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3574 pred:$p, cc_out:$s),
3576 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3577 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3578 Requires<[IsARM, NoV6, UseMulOps]>;
3581 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3582 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3583 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3584 Requires<[IsARM, HasV6, UseMulOps]> {
3586 let Inst{15-12} = Ra;
3589 let Constraints = "@earlyclobber $Rd" in
3590 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3591 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3593 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3594 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3595 Requires<[IsARM, NoV6]>;
3597 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3598 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3599 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3600 Requires<[IsARM, HasV6T2, UseMulOps]> {
3605 let Inst{19-16} = Rd;
3606 let Inst{15-12} = Ra;
3607 let Inst{11-8} = Rm;
3611 // Extra precision multiplies with low / high results
3612 let neverHasSideEffects = 1 in {
3613 let isCommutable = 1 in {
3614 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3615 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3616 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3617 Requires<[IsARM, HasV6]>;
3619 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3620 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3621 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3622 Requires<[IsARM, HasV6]>;
3624 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3625 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3626 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3628 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3629 Requires<[IsARM, NoV6]>;
3631 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3632 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3634 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3635 Requires<[IsARM, NoV6]>;
3639 // Multiply + accumulate
3640 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3641 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3642 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3643 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3644 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3645 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3646 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3647 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3649 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3650 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3651 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3652 Requires<[IsARM, HasV6]> {
3657 let Inst{19-16} = RdHi;
3658 let Inst{15-12} = RdLo;
3659 let Inst{11-8} = Rm;
3663 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3664 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3665 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3667 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3668 pred:$p, cc_out:$s)>,
3669 Requires<[IsARM, NoV6]>;
3670 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3671 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3673 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3674 pred:$p, cc_out:$s)>,
3675 Requires<[IsARM, NoV6]>;
3678 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3679 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3680 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3682 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3683 Requires<[IsARM, NoV6]>;
3686 } // neverHasSideEffects
3688 // Most significant word multiply
3689 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3690 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3691 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3692 Requires<[IsARM, HasV6]> {
3693 let Inst{15-12} = 0b1111;
3696 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3697 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3698 Requires<[IsARM, HasV6]> {
3699 let Inst{15-12} = 0b1111;
3702 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3703 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3704 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3705 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3706 Requires<[IsARM, HasV6, UseMulOps]>;
3708 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3709 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3710 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3711 Requires<[IsARM, HasV6]>;
3713 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3714 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3715 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3716 Requires<[IsARM, HasV6, UseMulOps]>;
3718 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3719 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3720 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3721 Requires<[IsARM, HasV6]>;
3723 multiclass AI_smul<string opc, PatFrag opnode> {
3724 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3725 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3726 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3727 (sext_inreg GPR:$Rm, i16)))]>,
3728 Requires<[IsARM, HasV5TE]>;
3730 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3731 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3732 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3733 (sra GPR:$Rm, (i32 16))))]>,
3734 Requires<[IsARM, HasV5TE]>;
3736 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3737 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3738 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3739 (sext_inreg GPR:$Rm, i16)))]>,
3740 Requires<[IsARM, HasV5TE]>;
3742 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3743 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3744 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3745 (sra GPR:$Rm, (i32 16))))]>,
3746 Requires<[IsARM, HasV5TE]>;
3748 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3749 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3750 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3751 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3752 Requires<[IsARM, HasV5TE]>;
3754 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3755 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3756 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3757 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3758 Requires<[IsARM, HasV5TE]>;
3762 multiclass AI_smla<string opc, PatFrag opnode> {
3763 let DecoderMethod = "DecodeSMLAInstruction" in {
3764 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3765 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3766 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3767 [(set GPRnopc:$Rd, (add GPR:$Ra,
3768 (opnode (sext_inreg GPRnopc:$Rn, i16),
3769 (sext_inreg GPRnopc:$Rm, i16))))]>,
3770 Requires<[IsARM, HasV5TE, UseMulOps]>;
3772 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3773 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3774 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3776 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3777 (sra GPRnopc:$Rm, (i32 16)))))]>,
3778 Requires<[IsARM, HasV5TE, UseMulOps]>;
3780 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3781 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3782 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3784 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3785 (sext_inreg GPRnopc:$Rm, i16))))]>,
3786 Requires<[IsARM, HasV5TE, UseMulOps]>;
3788 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3790 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3792 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3793 (sra GPRnopc:$Rm, (i32 16)))))]>,
3794 Requires<[IsARM, HasV5TE, UseMulOps]>;
3796 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3797 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3798 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3800 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3801 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3802 Requires<[IsARM, HasV5TE, UseMulOps]>;
3804 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3805 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3806 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3808 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3809 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3810 Requires<[IsARM, HasV5TE, UseMulOps]>;
3814 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3815 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3817 // Halfword multiply accumulate long: SMLAL<x><y>.
3818 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3819 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3820 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3821 Requires<[IsARM, HasV5TE]>;
3823 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3824 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3825 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3826 Requires<[IsARM, HasV5TE]>;
3828 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3829 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3830 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3831 Requires<[IsARM, HasV5TE]>;
3833 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3834 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3835 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3836 Requires<[IsARM, HasV5TE]>;
3838 // Helper class for AI_smld.
3839 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3840 InstrItinClass itin, string opc, string asm>
3841 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3844 let Inst{27-23} = 0b01110;
3845 let Inst{22} = long;
3846 let Inst{21-20} = 0b00;
3847 let Inst{11-8} = Rm;
3854 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3855 InstrItinClass itin, string opc, string asm>
3856 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3858 let Inst{15-12} = 0b1111;
3859 let Inst{19-16} = Rd;
3861 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3862 InstrItinClass itin, string opc, string asm>
3863 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3866 let Inst{19-16} = Rd;
3867 let Inst{15-12} = Ra;
3869 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3870 InstrItinClass itin, string opc, string asm>
3871 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3874 let Inst{19-16} = RdHi;
3875 let Inst{15-12} = RdLo;
3878 multiclass AI_smld<bit sub, string opc> {
3880 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3881 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3882 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3884 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3885 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3886 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3888 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3889 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3890 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3892 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3893 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3894 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3898 defm SMLA : AI_smld<0, "smla">;
3899 defm SMLS : AI_smld<1, "smls">;
3901 multiclass AI_sdml<bit sub, string opc> {
3903 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3904 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3905 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3906 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3909 defm SMUA : AI_sdml<0, "smua">;
3910 defm SMUS : AI_sdml<1, "smus">;
3912 //===----------------------------------------------------------------------===//
3913 // Division Instructions (ARMv7-A with virtualization extension)
3915 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3916 "sdiv", "\t$Rd, $Rn, $Rm",
3917 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3918 Requires<[IsARM, HasDivideInARM]>;
3920 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3921 "udiv", "\t$Rd, $Rn, $Rm",
3922 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3923 Requires<[IsARM, HasDivideInARM]>;
3925 //===----------------------------------------------------------------------===//
3926 // Misc. Arithmetic Instructions.
3929 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3930 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3931 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3934 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3935 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3936 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3937 Requires<[IsARM, HasV6T2]>,
3940 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3941 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3942 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3945 let AddedComplexity = 5 in
3946 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3947 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3948 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3949 Requires<[IsARM, HasV6]>,
3952 let AddedComplexity = 5 in
3953 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3954 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3955 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3956 Requires<[IsARM, HasV6]>,
3959 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3960 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3963 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3964 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3965 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3966 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3967 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3969 Requires<[IsARM, HasV6]>,
3970 Sched<[WriteALUsi, ReadALU]>;
3972 // Alternate cases for PKHBT where identities eliminate some nodes.
3973 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3974 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3975 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3976 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3978 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3979 // will match the pattern below.
3980 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3981 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3982 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3983 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3984 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3986 Requires<[IsARM, HasV6]>,
3987 Sched<[WriteALUsi, ReadALU]>;
3989 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3990 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3991 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3992 (srl GPRnopc:$src2, imm16_31:$sh)),
3993 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3994 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3995 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3996 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3998 //===----------------------------------------------------------------------===//
3999 // Comparison Instructions...
4002 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4003 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4004 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4006 // ARMcmpZ can re-use the above instruction definitions.
4007 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4008 (CMPri GPR:$src, so_imm:$imm)>;
4009 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4010 (CMPrr GPR:$src, GPR:$rhs)>;
4011 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4012 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4013 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4014 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4016 // CMN register-integer
4017 let isCompare = 1, Defs = [CPSR] in {
4018 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4019 "cmn", "\t$Rn, $imm",
4020 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
4025 let Inst{19-16} = Rn;
4026 let Inst{15-12} = 0b0000;
4027 let Inst{11-0} = imm;
4029 let Unpredictable{15-12} = 0b1111;
4032 // CMN register-register/shift
4033 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4034 "cmn", "\t$Rn, $Rm",
4035 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4036 GPR:$Rn, GPR:$Rm)]> {
4039 let isCommutable = 1;
4042 let Inst{19-16} = Rn;
4043 let Inst{15-12} = 0b0000;
4044 let Inst{11-4} = 0b00000000;
4047 let Unpredictable{15-12} = 0b1111;
4050 def CMNzrsi : AI1<0b1011, (outs),
4051 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4052 "cmn", "\t$Rn, $shift",
4053 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4054 GPR:$Rn, so_reg_imm:$shift)]> {
4059 let Inst{19-16} = Rn;
4060 let Inst{15-12} = 0b0000;
4061 let Inst{11-5} = shift{11-5};
4063 let Inst{3-0} = shift{3-0};
4065 let Unpredictable{15-12} = 0b1111;
4068 def CMNzrsr : AI1<0b1011, (outs),
4069 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4070 "cmn", "\t$Rn, $shift",
4071 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4072 GPRnopc:$Rn, so_reg_reg:$shift)]> {
4077 let Inst{19-16} = Rn;
4078 let Inst{15-12} = 0b0000;
4079 let Inst{11-8} = shift{11-8};
4081 let Inst{6-5} = shift{6-5};
4083 let Inst{3-0} = shift{3-0};
4085 let Unpredictable{15-12} = 0b1111;
4090 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4091 (CMNri GPR:$src, so_imm_neg:$imm)>;
4093 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4094 (CMNri GPR:$src, so_imm_neg:$imm)>;
4096 // Note that TST/TEQ don't set all the same flags that CMP does!
4097 defm TST : AI1_cmp_irs<0b1000, "tst",
4098 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4099 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4100 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4101 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4102 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4104 // Pseudo i64 compares for some floating point compares.
4105 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4107 def BCCi64 : PseudoInst<(outs),
4108 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4110 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4112 def BCCZi64 : PseudoInst<(outs),
4113 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4114 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4115 } // usesCustomInserter
4118 // Conditional moves
4119 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4120 // a two-value operand where a dag node expects two operands. :(
4121 let neverHasSideEffects = 1 in {
4123 let isCommutable = 1, isSelect = 1 in
4124 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4126 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4127 RegConstraint<"$false = $Rd">;
4129 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4130 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4132 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4133 imm:$cc, CCR:$ccr))*/]>,
4134 RegConstraint<"$false = $Rd">;
4135 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4136 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4138 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4139 imm:$cc, CCR:$ccr))*/]>,
4140 RegConstraint<"$false = $Rd">;
4143 let isMoveImm = 1 in
4144 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4145 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4148 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4150 let isMoveImm = 1 in
4151 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4152 (ins GPR:$false, so_imm:$imm, pred:$p),
4154 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4155 RegConstraint<"$false = $Rd">;
4157 // Two instruction predicate mov immediate.
4158 let isMoveImm = 1 in
4159 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4160 (ins GPR:$false, i32imm:$src, pred:$p),
4161 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4163 let isMoveImm = 1 in
4164 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4165 (ins GPR:$false, so_imm:$imm, pred:$p),
4167 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4168 RegConstraint<"$false = $Rd">;
4170 } // neverHasSideEffects
4173 //===----------------------------------------------------------------------===//
4174 // Atomic operations intrinsics
4177 def MemBarrierOptOperand : AsmOperandClass {
4178 let Name = "MemBarrierOpt";
4179 let ParserMethod = "parseMemBarrierOptOperand";
4181 def memb_opt : Operand<i32> {
4182 let PrintMethod = "printMemBOption";
4183 let ParserMatchClass = MemBarrierOptOperand;
4184 let DecoderMethod = "DecodeMemBarrierOption";
4187 // memory barriers protect the atomic sequences
4188 let hasSideEffects = 1 in {
4189 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4190 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4191 Requires<[IsARM, HasDB]> {
4193 let Inst{31-4} = 0xf57ff05;
4194 let Inst{3-0} = opt;
4198 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4199 "dsb", "\t$opt", []>,
4200 Requires<[IsARM, HasDB]> {
4202 let Inst{31-4} = 0xf57ff04;
4203 let Inst{3-0} = opt;
4206 // ISB has only full system option
4207 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4208 "isb", "\t$opt", []>,
4209 Requires<[IsARM, HasDB]> {
4211 let Inst{31-4} = 0xf57ff06;
4212 let Inst{3-0} = opt;
4215 // Pseudo instruction that combines movs + predicated rsbmi
4216 // to implement integer ABS
4217 let usesCustomInserter = 1, Defs = [CPSR] in
4218 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4220 let usesCustomInserter = 1 in {
4221 let Defs = [CPSR] in {
4222 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4224 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4225 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4227 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4228 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4230 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4231 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4233 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4234 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4236 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4237 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4239 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4240 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4242 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4243 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4245 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4246 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4248 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4249 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4251 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4252 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4254 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4255 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4257 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4258 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4260 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4261 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4263 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4264 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4266 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4267 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4269 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4270 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4272 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4273 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4275 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4276 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4278 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4279 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4281 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4282 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4284 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4285 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4287 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4288 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4290 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4291 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4293 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4294 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4295 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4296 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4297 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4298 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4299 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4300 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4301 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4302 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4303 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4304 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4305 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4306 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4308 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4309 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4311 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4313 def ATOMIC_SWAP_I8 : PseudoInst<
4314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4315 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4316 def ATOMIC_SWAP_I16 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4318 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4319 def ATOMIC_SWAP_I32 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4321 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4323 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4324 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4325 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4326 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4327 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4328 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4329 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4330 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4331 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4335 let usesCustomInserter = 1 in {
4336 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4337 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4339 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4342 let mayLoad = 1 in {
4343 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4345 "ldrexb", "\t$Rt, $addr", []>;
4346 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4347 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4348 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4349 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4350 let hasExtraDefRegAllocReq = 1 in
4351 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4352 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4353 let DecoderMethod = "DecodeDoubleRegLoad";
4357 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4358 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4359 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4360 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4361 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4362 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4363 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4364 let hasExtraSrcRegAllocReq = 1 in
4365 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4366 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4367 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4368 let DecoderMethod = "DecodeDoubleRegStore";
4373 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4374 Requires<[IsARM, HasV7]> {
4375 let Inst{31-0} = 0b11110101011111111111000000011111;
4378 // SWP/SWPB are deprecated in V6/V7.
4379 let mayLoad = 1, mayStore = 1 in {
4380 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4381 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4382 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4383 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4386 //===----------------------------------------------------------------------===//
4387 // Coprocessor Instructions.
4390 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4391 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4392 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4393 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4394 imm:$CRm, imm:$opc2)]> {
4402 let Inst{3-0} = CRm;
4404 let Inst{7-5} = opc2;
4405 let Inst{11-8} = cop;
4406 let Inst{15-12} = CRd;
4407 let Inst{19-16} = CRn;
4408 let Inst{23-20} = opc1;
4411 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4412 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4413 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4414 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4415 imm:$CRm, imm:$opc2)]> {
4416 let Inst{31-28} = 0b1111;
4424 let Inst{3-0} = CRm;
4426 let Inst{7-5} = opc2;
4427 let Inst{11-8} = cop;
4428 let Inst{15-12} = CRd;
4429 let Inst{19-16} = CRn;
4430 let Inst{23-20} = opc1;
4433 class ACI<dag oops, dag iops, string opc, string asm,
4434 IndexMode im = IndexModeNone>
4435 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4437 let Inst{27-25} = 0b110;
4439 class ACInoP<dag oops, dag iops, string opc, string asm,
4440 IndexMode im = IndexModeNone>
4441 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4443 let Inst{31-28} = 0b1111;
4444 let Inst{27-25} = 0b110;
4446 multiclass LdStCop<bit load, bit Dbit, string asm> {
4447 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4448 asm, "\t$cop, $CRd, $addr"> {
4452 let Inst{24} = 1; // P = 1
4453 let Inst{23} = addr{8};
4454 let Inst{22} = Dbit;
4455 let Inst{21} = 0; // W = 0
4456 let Inst{20} = load;
4457 let Inst{19-16} = addr{12-9};
4458 let Inst{15-12} = CRd;
4459 let Inst{11-8} = cop;
4460 let Inst{7-0} = addr{7-0};
4461 let DecoderMethod = "DecodeCopMemInstruction";
4463 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4464 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4468 let Inst{24} = 1; // P = 1
4469 let Inst{23} = addr{8};
4470 let Inst{22} = Dbit;
4471 let Inst{21} = 1; // W = 1
4472 let Inst{20} = load;
4473 let Inst{19-16} = addr{12-9};
4474 let Inst{15-12} = CRd;
4475 let Inst{11-8} = cop;
4476 let Inst{7-0} = addr{7-0};
4477 let DecoderMethod = "DecodeCopMemInstruction";
4479 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4480 postidx_imm8s4:$offset),
4481 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4486 let Inst{24} = 0; // P = 0
4487 let Inst{23} = offset{8};
4488 let Inst{22} = Dbit;
4489 let Inst{21} = 1; // W = 1
4490 let Inst{20} = load;
4491 let Inst{19-16} = addr;
4492 let Inst{15-12} = CRd;
4493 let Inst{11-8} = cop;
4494 let Inst{7-0} = offset{7-0};
4495 let DecoderMethod = "DecodeCopMemInstruction";
4497 def _OPTION : ACI<(outs),
4498 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4499 coproc_option_imm:$option),
4500 asm, "\t$cop, $CRd, $addr, $option"> {
4505 let Inst{24} = 0; // P = 0
4506 let Inst{23} = 1; // U = 1
4507 let Inst{22} = Dbit;
4508 let Inst{21} = 0; // W = 0
4509 let Inst{20} = load;
4510 let Inst{19-16} = addr;
4511 let Inst{15-12} = CRd;
4512 let Inst{11-8} = cop;
4513 let Inst{7-0} = option;
4514 let DecoderMethod = "DecodeCopMemInstruction";
4517 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4518 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4519 asm, "\t$cop, $CRd, $addr"> {
4523 let Inst{24} = 1; // P = 1
4524 let Inst{23} = addr{8};
4525 let Inst{22} = Dbit;
4526 let Inst{21} = 0; // W = 0
4527 let Inst{20} = load;
4528 let Inst{19-16} = addr{12-9};
4529 let Inst{15-12} = CRd;
4530 let Inst{11-8} = cop;
4531 let Inst{7-0} = addr{7-0};
4532 let DecoderMethod = "DecodeCopMemInstruction";
4534 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4535 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4539 let Inst{24} = 1; // P = 1
4540 let Inst{23} = addr{8};
4541 let Inst{22} = Dbit;
4542 let Inst{21} = 1; // W = 1
4543 let Inst{20} = load;
4544 let Inst{19-16} = addr{12-9};
4545 let Inst{15-12} = CRd;
4546 let Inst{11-8} = cop;
4547 let Inst{7-0} = addr{7-0};
4548 let DecoderMethod = "DecodeCopMemInstruction";
4550 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4551 postidx_imm8s4:$offset),
4552 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4557 let Inst{24} = 0; // P = 0
4558 let Inst{23} = offset{8};
4559 let Inst{22} = Dbit;
4560 let Inst{21} = 1; // W = 1
4561 let Inst{20} = load;
4562 let Inst{19-16} = addr;
4563 let Inst{15-12} = CRd;
4564 let Inst{11-8} = cop;
4565 let Inst{7-0} = offset{7-0};
4566 let DecoderMethod = "DecodeCopMemInstruction";
4568 def _OPTION : ACInoP<(outs),
4569 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4570 coproc_option_imm:$option),
4571 asm, "\t$cop, $CRd, $addr, $option"> {
4576 let Inst{24} = 0; // P = 0
4577 let Inst{23} = 1; // U = 1
4578 let Inst{22} = Dbit;
4579 let Inst{21} = 0; // W = 0
4580 let Inst{20} = load;
4581 let Inst{19-16} = addr;
4582 let Inst{15-12} = CRd;
4583 let Inst{11-8} = cop;
4584 let Inst{7-0} = option;
4585 let DecoderMethod = "DecodeCopMemInstruction";
4589 defm LDC : LdStCop <1, 0, "ldc">;
4590 defm LDCL : LdStCop <1, 1, "ldcl">;
4591 defm STC : LdStCop <0, 0, "stc">;
4592 defm STCL : LdStCop <0, 1, "stcl">;
4593 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4594 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4595 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4596 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4598 //===----------------------------------------------------------------------===//
4599 // Move between coprocessor and ARM core register.
4602 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4604 : ABI<0b1110, oops, iops, NoItinerary, opc,
4605 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4606 let Inst{20} = direction;
4616 let Inst{15-12} = Rt;
4617 let Inst{11-8} = cop;
4618 let Inst{23-21} = opc1;
4619 let Inst{7-5} = opc2;
4620 let Inst{3-0} = CRm;
4621 let Inst{19-16} = CRn;
4624 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4626 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4627 c_imm:$CRm, imm0_7:$opc2),
4628 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4629 imm:$CRm, imm:$opc2)]>;
4630 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4631 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4632 c_imm:$CRm, 0, pred:$p)>;
4633 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4635 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4637 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4638 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4639 c_imm:$CRm, 0, pred:$p)>;
4641 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4642 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4644 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4646 : ABXI<0b1110, oops, iops, NoItinerary,
4647 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4648 let Inst{31-28} = 0b1111;
4649 let Inst{20} = direction;
4659 let Inst{15-12} = Rt;
4660 let Inst{11-8} = cop;
4661 let Inst{23-21} = opc1;
4662 let Inst{7-5} = opc2;
4663 let Inst{3-0} = CRm;
4664 let Inst{19-16} = CRn;
4667 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4669 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4670 c_imm:$CRm, imm0_7:$opc2),
4671 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4672 imm:$CRm, imm:$opc2)]>;
4673 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4674 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4676 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4678 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4680 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4681 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4684 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4685 imm:$CRm, imm:$opc2),
4686 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4688 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4689 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4690 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4691 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4692 let Inst{23-21} = 0b010;
4693 let Inst{20} = direction;
4701 let Inst{15-12} = Rt;
4702 let Inst{19-16} = Rt2;
4703 let Inst{11-8} = cop;
4704 let Inst{7-4} = opc1;
4705 let Inst{3-0} = CRm;
4708 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4709 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4710 GPRnopc:$Rt2, imm:$CRm)]>;
4711 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4713 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4714 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4715 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4716 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4717 let Inst{31-28} = 0b1111;
4718 let Inst{23-21} = 0b010;
4719 let Inst{20} = direction;
4727 let Inst{15-12} = Rt;
4728 let Inst{19-16} = Rt2;
4729 let Inst{11-8} = cop;
4730 let Inst{7-4} = opc1;
4731 let Inst{3-0} = CRm;
4733 let DecoderMethod = "DecodeMRRC2";
4736 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4737 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4738 GPRnopc:$Rt2, imm:$CRm)]>;
4739 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4741 //===----------------------------------------------------------------------===//
4742 // Move between special register and ARM core register
4745 // Move to ARM core register from Special Register
4746 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4747 "mrs", "\t$Rd, apsr", []> {
4749 let Inst{23-16} = 0b00001111;
4750 let Unpredictable{19-17} = 0b111;
4752 let Inst{15-12} = Rd;
4754 let Inst{11-0} = 0b000000000000;
4755 let Unpredictable{11-0} = 0b110100001111;
4758 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4761 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4762 // section B9.3.9, with the R bit set to 1.
4763 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4764 "mrs", "\t$Rd, spsr", []> {
4766 let Inst{23-16} = 0b01001111;
4767 let Unpredictable{19-16} = 0b1111;
4769 let Inst{15-12} = Rd;
4771 let Inst{11-0} = 0b000000000000;
4772 let Unpredictable{11-0} = 0b110100001111;
4775 // Move from ARM core register to Special Register
4777 // No need to have both system and application versions, the encodings are the
4778 // same and the assembly parser has no way to distinguish between them. The mask
4779 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4780 // the mask with the fields to be accessed in the special register.
4781 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4782 "msr", "\t$mask, $Rn", []> {
4787 let Inst{22} = mask{4}; // R bit
4788 let Inst{21-20} = 0b10;
4789 let Inst{19-16} = mask{3-0};
4790 let Inst{15-12} = 0b1111;
4791 let Inst{11-4} = 0b00000000;
4795 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4796 "msr", "\t$mask, $a", []> {
4801 let Inst{22} = mask{4}; // R bit
4802 let Inst{21-20} = 0b10;
4803 let Inst{19-16} = mask{3-0};
4804 let Inst{15-12} = 0b1111;
4808 //===----------------------------------------------------------------------===//
4812 // __aeabi_read_tp preserves the registers r1-r3.
4813 // This is a pseudo inst so that we can get the encoding right,
4814 // complete with fixup for the aeabi_read_tp function.
4816 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4817 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4818 [(set R0, ARMthread_pointer)]>;
4821 //===----------------------------------------------------------------------===//
4822 // SJLJ Exception handling intrinsics
4823 // eh_sjlj_setjmp() is an instruction sequence to store the return
4824 // address and save #0 in R0 for the non-longjmp case.
4825 // Since by its nature we may be coming from some other function to get
4826 // here, and we're using the stack frame for the containing function to
4827 // save/restore registers, we can't keep anything live in regs across
4828 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4829 // when we get here from a longjmp(). We force everything out of registers
4830 // except for our own input by listing the relevant registers in Defs. By
4831 // doing so, we also cause the prologue/epilogue code to actively preserve
4832 // all of the callee-saved resgisters, which is exactly what we want.
4833 // A constant value is passed in $val, and we use the location as a scratch.
4835 // These are pseudo-instructions and are lowered to individual MC-insts, so
4836 // no encoding information is necessary.
4838 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4839 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4840 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4841 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4843 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4844 Requires<[IsARM, HasVFP2]>;
4848 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4849 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4850 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4852 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4853 Requires<[IsARM, NoVFP]>;
4856 // FIXME: Non-IOS version(s)
4857 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4858 Defs = [ R7, LR, SP ] in {
4859 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4861 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4862 Requires<[IsARM, IsIOS]>;
4865 // eh.sjlj.dispatchsetup pseudo-instruction.
4866 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4867 // the pseudo is expanded (which happens before any passes that need the
4868 // instruction size).
4869 let isBarrier = 1 in
4870 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4873 //===----------------------------------------------------------------------===//
4874 // Non-Instruction Patterns
4877 // ARMv4 indirect branch using (MOVr PC, dst)
4878 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4879 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4880 4, IIC_Br, [(brind GPR:$dst)],
4881 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4882 Requires<[IsARM, NoV4T]>;
4884 // Large immediate handling.
4886 // 32-bit immediate using two piece so_imms or movw + movt.
4887 // This is a single pseudo instruction, the benefit is that it can be remat'd
4888 // as a single unit instead of having to handle reg inputs.
4889 // FIXME: Remove this when we can do generalized remat.
4890 let isReMaterializable = 1, isMoveImm = 1 in
4891 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4892 [(set GPR:$dst, (arm_i32imm:$src))]>,
4895 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4896 // It also makes it possible to rematerialize the instructions.
4897 // FIXME: Remove this when we can do generalized remat and when machine licm
4898 // can properly the instructions.
4899 let isReMaterializable = 1 in {
4900 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4902 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4903 Requires<[IsARM, UseMovt]>;
4905 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4907 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4908 Requires<[IsARM, UseMovt]>;
4910 let AddedComplexity = 10 in
4911 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4913 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4914 Requires<[IsARM, UseMovt]>;
4915 } // isReMaterializable
4917 // ConstantPool, GlobalAddress, and JumpTable
4918 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4919 Requires<[IsARM, DontUseMovt]>;
4920 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4921 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4922 Requires<[IsARM, UseMovt]>;
4923 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4924 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4926 // TODO: add,sub,and, 3-instr forms?
4928 // Tail calls. These patterns also apply to Thumb mode.
4929 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4930 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4931 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4934 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4935 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4936 (BMOVPCB_CALL texternalsym:$func)>;
4938 // zextload i1 -> zextload i8
4939 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4940 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4942 // extload -> zextload
4943 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4944 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4945 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4946 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4948 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4950 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4951 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4954 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4955 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4956 (SMULBB GPR:$a, GPR:$b)>;
4957 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4958 (SMULBB GPR:$a, GPR:$b)>;
4959 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4960 (sra GPR:$b, (i32 16))),
4961 (SMULBT GPR:$a, GPR:$b)>;
4962 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4963 (SMULBT GPR:$a, GPR:$b)>;
4964 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4965 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4966 (SMULTB GPR:$a, GPR:$b)>;
4967 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4968 (SMULTB GPR:$a, GPR:$b)>;
4969 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4971 (SMULWB GPR:$a, GPR:$b)>;
4972 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4973 (SMULWB GPR:$a, GPR:$b)>;
4975 def : ARMV5MOPat<(add GPR:$acc,
4976 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4977 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4978 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4979 def : ARMV5MOPat<(add GPR:$acc,
4980 (mul sext_16_node:$a, sext_16_node:$b)),
4981 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4982 def : ARMV5MOPat<(add GPR:$acc,
4983 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4984 (sra GPR:$b, (i32 16)))),
4985 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4986 def : ARMV5MOPat<(add GPR:$acc,
4987 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4988 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4989 def : ARMV5MOPat<(add GPR:$acc,
4990 (mul (sra GPR:$a, (i32 16)),
4991 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4992 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4993 def : ARMV5MOPat<(add GPR:$acc,
4994 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4995 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4996 def : ARMV5MOPat<(add GPR:$acc,
4997 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4999 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5000 def : ARMV5MOPat<(add GPR:$acc,
5001 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5002 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5005 // Pre-v7 uses MCR for synchronization barriers.
5006 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5007 Requires<[IsARM, HasV6]>;
5009 // SXT/UXT with no rotate
5010 let AddedComplexity = 16 in {
5011 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5012 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5013 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5014 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5015 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5016 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5017 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5020 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5021 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5023 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5024 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5025 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5026 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5028 // Atomic load/store patterns
5029 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5030 (LDRBrs ldst_so_reg:$src)>;
5031 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5032 (LDRBi12 addrmode_imm12:$src)>;
5033 def : ARMPat<(atomic_load_16 addrmode3:$src),
5034 (LDRH addrmode3:$src)>;
5035 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5036 (LDRrs ldst_so_reg:$src)>;
5037 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5038 (LDRi12 addrmode_imm12:$src)>;
5039 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5040 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5041 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5042 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5043 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5044 (STRH GPR:$val, addrmode3:$ptr)>;
5045 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5046 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5047 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5048 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5051 //===----------------------------------------------------------------------===//
5055 include "ARMInstrThumb.td"
5057 //===----------------------------------------------------------------------===//
5061 include "ARMInstrThumb2.td"
5063 //===----------------------------------------------------------------------===//
5064 // Floating Point Support
5067 include "ARMInstrVFP.td"
5069 //===----------------------------------------------------------------------===//
5070 // Advanced SIMD (NEON) Support
5073 include "ARMInstrNEON.td"
5075 //===----------------------------------------------------------------------===//
5076 // Assembler aliases
5080 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5081 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5082 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5084 // System instructions
5085 def : MnemonicAlias<"swi", "svc">;
5087 // Load / Store Multiple
5088 def : MnemonicAlias<"ldmfd", "ldm">;
5089 def : MnemonicAlias<"ldmia", "ldm">;
5090 def : MnemonicAlias<"ldmea", "ldmdb">;
5091 def : MnemonicAlias<"stmfd", "stmdb">;
5092 def : MnemonicAlias<"stmia", "stm">;
5093 def : MnemonicAlias<"stmea", "stm">;
5095 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5096 // shift amount is zero (i.e., unspecified).
5097 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5098 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5099 Requires<[IsARM, HasV6]>;
5100 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5101 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5102 Requires<[IsARM, HasV6]>;
5104 // PUSH/POP aliases for STM/LDM
5105 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5106 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5108 // SSAT/USAT optional shift operand.
5109 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5110 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5111 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5112 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5115 // Extend instruction optional rotate operand.
5116 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5117 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5118 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5119 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5120 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5121 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5122 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5123 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5124 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5125 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5126 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5127 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5129 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5130 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5131 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5132 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5133 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5134 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5135 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5136 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5137 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5138 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5139 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5140 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5144 def : MnemonicAlias<"rfefa", "rfeda">;
5145 def : MnemonicAlias<"rfeea", "rfedb">;
5146 def : MnemonicAlias<"rfefd", "rfeia">;
5147 def : MnemonicAlias<"rfeed", "rfeib">;
5148 def : MnemonicAlias<"rfe", "rfeia">;
5151 def : MnemonicAlias<"srsfa", "srsda">;
5152 def : MnemonicAlias<"srsea", "srsdb">;
5153 def : MnemonicAlias<"srsfd", "srsia">;
5154 def : MnemonicAlias<"srsed", "srsib">;
5155 def : MnemonicAlias<"srs", "srsia">;
5158 def : MnemonicAlias<"qsubaddx", "qsax">;
5160 def : MnemonicAlias<"saddsubx", "sasx">;
5161 // SHASX == SHADDSUBX
5162 def : MnemonicAlias<"shaddsubx", "shasx">;
5163 // SHSAX == SHSUBADDX
5164 def : MnemonicAlias<"shsubaddx", "shsax">;
5166 def : MnemonicAlias<"ssubaddx", "ssax">;
5168 def : MnemonicAlias<"uaddsubx", "uasx">;
5169 // UHASX == UHADDSUBX
5170 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5171 // UHSAX == UHSUBADDX
5172 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5173 // UQASX == UQADDSUBX
5174 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5175 // UQSAX == UQSUBADDX
5176 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5178 def : MnemonicAlias<"usubaddx", "usax">;
5180 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5182 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5183 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5184 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5185 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5186 // Same for AND <--> BIC
5187 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5188 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5189 pred:$p, cc_out:$s)>;
5190 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5191 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5192 pred:$p, cc_out:$s)>;
5193 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5194 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5195 pred:$p, cc_out:$s)>;
5196 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5197 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5198 pred:$p, cc_out:$s)>;
5200 // Likewise, "add Rd, so_imm_neg" -> sub
5201 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5202 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5203 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5204 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5205 // Same for CMP <--> CMN via so_imm_neg
5206 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5207 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5208 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5209 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5211 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5212 // LSR, ROR, and RRX instructions.
5213 // FIXME: We need C++ parser hooks to map the alias to the MOV
5214 // encoding. It seems we should be able to do that sort of thing
5215 // in tblgen, but it could get ugly.
5216 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5217 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5218 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5220 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5221 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5223 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5224 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5226 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5227 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5230 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5231 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5232 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5233 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5234 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5236 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5237 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5239 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5240 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5242 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5243 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5247 // "neg" is and alias for "rsb rd, rn, #0"
5248 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5249 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5251 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5252 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5253 Requires<[IsARM, NoV6]>;
5255 // UMULL/SMULL are available on all arches, but the instruction definitions
5256 // need difference constraints pre-v6. Use these aliases for the assembly
5257 // parsing on pre-v6.
5258 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5259 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5260 Requires<[IsARM, NoV6]>;
5261 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5262 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5263 Requires<[IsARM, NoV6]>;
5265 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5267 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;