1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
88 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
89 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
90 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
92 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
93 [SDNPHasChain, SDNPOutGlue]>;
94 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
99 SDNPMayStore, SDNPMayLoad]>;
101 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
107 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
108 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
112 [SDNPHasChain, SDNPOptInGlue]>;
114 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
117 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
118 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
120 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
122 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
125 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
128 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
131 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
134 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
135 [SDNPOutGlue, SDNPCommutative]>;
137 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
139 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
140 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
141 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
143 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
145 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
146 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
147 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
149 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
150 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
151 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
152 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
153 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
155 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
157 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
159 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
160 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
162 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
164 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
165 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
170 //===----------------------------------------------------------------------===//
171 // ARM Instruction Predicate Definitions.
173 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
174 AssemblerPredicate<"HasV4TOps", "armv4t">;
175 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
176 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
177 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
178 AssemblerPredicate<"HasV5TEOps", "armv5te">;
179 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
180 AssemblerPredicate<"HasV6Ops", "armv6">;
181 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
182 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
183 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
184 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
185 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
186 AssemblerPredicate<"HasV7Ops", "armv7">;
187 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
188 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
189 AssemblerPredicate<"FeatureVFP2", "VFP2">;
190 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
191 AssemblerPredicate<"FeatureVFP3", "VFP3">;
192 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
193 AssemblerPredicate<"FeatureVFP4", "VFP4">;
194 def HasNEON : Predicate<"Subtarget->hasNEON()">,
195 AssemblerPredicate<"FeatureNEON", "NEON">;
196 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
197 AssemblerPredicate<"FeatureFP16","half-float">;
198 def HasDivide : Predicate<"Subtarget->hasDivide()">,
199 AssemblerPredicate<"FeatureHWDiv", "divide">;
200 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
201 AssemblerPredicate<"FeatureT2XtPk",
203 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
204 AssemblerPredicate<"FeatureDSPThumb2",
206 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
207 AssemblerPredicate<"FeatureDB",
209 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
210 AssemblerPredicate<"FeatureMP",
212 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
213 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
214 def IsThumb : Predicate<"Subtarget->isThumb()">,
215 AssemblerPredicate<"ModeThumb", "thumb">;
216 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
217 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
218 AssemblerPredicate<"ModeThumb,FeatureThumb2",
220 def IsMClass : Predicate<"Subtarget->isMClass()">,
221 AssemblerPredicate<"FeatureMClass", "armv7m">;
222 def IsARClass : Predicate<"!Subtarget->isMClass()">,
223 AssemblerPredicate<"!FeatureMClass",
225 def IsARM : Predicate<"!Subtarget->isThumb()">,
226 AssemblerPredicate<"!ModeThumb", "arm-mode">;
227 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
228 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
229 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
231 // FIXME: Eventually this will be just "hasV6T2Ops".
232 def UseMovt : Predicate<"Subtarget->useMovt()">;
233 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
234 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
236 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
237 // But only select them if more precision in FP computation is allowed.
238 // Do not use them for Darwin platforms.
239 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
240 " FPOpFusion::Fast) && "
241 "!Subtarget->isTargetDarwin()">;
242 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
243 "Subtarget->isTargetDarwin()">;
245 //===----------------------------------------------------------------------===//
246 // ARM Flag Definitions.
248 class RegConstraint<string C> {
249 string Constraints = C;
252 //===----------------------------------------------------------------------===//
253 // ARM specific transformation functions and pattern fragments.
256 // imm_neg_XFORM - Return a imm value packed into the format described for
257 // imm_neg defs below.
258 def imm_neg_XFORM : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
262 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
263 // so_imm_not def below.
264 def so_imm_not_XFORM : SDNodeXForm<imm, [{
265 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
268 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
269 def imm16_31 : ImmLeaf<i32, [{
270 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
273 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
274 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
275 int64_t Value = -(int)N->getZExtValue();
276 return Value && ARM_AM::getSOImmVal(Value) != -1;
278 let ParserMatchClass = so_imm_neg_asmoperand;
281 // Note: this pattern doesn't require an encoder method and such, as it's
282 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
283 // is handled by the destination instructions, which use so_imm.
284 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
285 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
286 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
287 }], so_imm_not_XFORM> {
288 let ParserMatchClass = so_imm_not_asmoperand;
291 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
292 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
293 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
296 /// Split a 32-bit immediate into two 16 bit parts.
297 def hi16 : SDNodeXForm<imm, [{
298 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
301 def lo16AllZero : PatLeaf<(i32 imm), [{
302 // Returns true if all low 16-bits are 0.
303 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
306 class BinOpWithFlagFrag<dag res> :
307 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
308 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
309 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
311 // An 'and' node with a single use.
312 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
313 return N->hasOneUse();
316 // An 'xor' node with a single use.
317 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
318 return N->hasOneUse();
321 // An 'fmul' node with a single use.
322 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
323 return N->hasOneUse();
326 // An 'fadd' node which checks for single non-hazardous use.
327 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
328 return hasNoVMLxHazardUse(N);
331 // An 'fsub' node which checks for single non-hazardous use.
332 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
333 return hasNoVMLxHazardUse(N);
336 //===----------------------------------------------------------------------===//
337 // Operand Definitions.
340 // Immediate operands with a shared generic asm render method.
341 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
344 // FIXME: rename brtarget to t2_brtarget
345 def brtarget : Operand<OtherVT> {
346 let EncoderMethod = "getBranchTargetOpValue";
347 let OperandType = "OPERAND_PCREL";
348 let DecoderMethod = "DecodeT2BROperand";
351 // FIXME: get rid of this one?
352 def uncondbrtarget : Operand<OtherVT> {
353 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
357 // Branch target for ARM. Handles conditional/unconditional
358 def br_target : Operand<OtherVT> {
359 let EncoderMethod = "getARMBranchTargetOpValue";
360 let OperandType = "OPERAND_PCREL";
364 // FIXME: rename bltarget to t2_bl_target?
365 def bltarget : Operand<i32> {
366 // Encoded the same as branch targets.
367 let EncoderMethod = "getBranchTargetOpValue";
368 let OperandType = "OPERAND_PCREL";
371 // Call target for ARM. Handles conditional/unconditional
372 // FIXME: rename bl_target to t2_bltarget?
373 def bl_target : Operand<i32> {
374 let EncoderMethod = "getARMBLTargetOpValue";
375 let OperandType = "OPERAND_PCREL";
378 def blx_target : Operand<i32> {
379 let EncoderMethod = "getARMBLXTargetOpValue";
380 let OperandType = "OPERAND_PCREL";
383 // A list of registers separated by comma. Used by load/store multiple.
384 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
385 def reglist : Operand<i32> {
386 let EncoderMethod = "getRegisterListOpValue";
387 let ParserMatchClass = RegListAsmOperand;
388 let PrintMethod = "printRegisterList";
389 let DecoderMethod = "DecodeRegListOperand";
392 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
393 def dpr_reglist : Operand<i32> {
394 let EncoderMethod = "getRegisterListOpValue";
395 let ParserMatchClass = DPRRegListAsmOperand;
396 let PrintMethod = "printRegisterList";
397 let DecoderMethod = "DecodeDPRRegListOperand";
400 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
401 def spr_reglist : Operand<i32> {
402 let EncoderMethod = "getRegisterListOpValue";
403 let ParserMatchClass = SPRRegListAsmOperand;
404 let PrintMethod = "printRegisterList";
405 let DecoderMethod = "DecodeSPRRegListOperand";
408 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
409 def cpinst_operand : Operand<i32> {
410 let PrintMethod = "printCPInstOperand";
414 def pclabel : Operand<i32> {
415 let PrintMethod = "printPCLabel";
418 // ADR instruction labels.
419 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
420 def adrlabel : Operand<i32> {
421 let EncoderMethod = "getAdrLabelOpValue";
422 let ParserMatchClass = AdrLabelAsmOperand;
423 let PrintMethod = "printAdrLabelOperand";
426 def neon_vcvt_imm32 : Operand<i32> {
427 let EncoderMethod = "getNEONVcvtImm32OpValue";
428 let DecoderMethod = "DecodeVCVTImmOperand";
431 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
432 def rot_imm_XFORM: SDNodeXForm<imm, [{
433 switch (N->getZExtValue()){
435 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
436 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
437 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
438 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
441 def RotImmAsmOperand : AsmOperandClass {
443 let ParserMethod = "parseRotImm";
445 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
446 int32_t v = N->getZExtValue();
447 return v == 8 || v == 16 || v == 24; }],
449 let PrintMethod = "printRotImmOperand";
450 let ParserMatchClass = RotImmAsmOperand;
453 // shift_imm: An integer that encodes a shift amount and the type of shift
454 // (asr or lsl). The 6-bit immediate encodes as:
457 // {4-0} imm5 shift amount.
458 // asr #32 encoded as imm5 == 0.
459 def ShifterImmAsmOperand : AsmOperandClass {
460 let Name = "ShifterImm";
461 let ParserMethod = "parseShifterImm";
463 def shift_imm : Operand<i32> {
464 let PrintMethod = "printShiftImmOperand";
465 let ParserMatchClass = ShifterImmAsmOperand;
468 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
469 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
470 def so_reg_reg : Operand<i32>, // reg reg imm
471 ComplexPattern<i32, 3, "SelectRegShifterOperand",
472 [shl, srl, sra, rotr]> {
473 let EncoderMethod = "getSORegRegOpValue";
474 let PrintMethod = "printSORegRegOperand";
475 let DecoderMethod = "DecodeSORegRegOperand";
476 let ParserMatchClass = ShiftedRegAsmOperand;
477 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
480 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
481 def so_reg_imm : Operand<i32>, // reg imm
482 ComplexPattern<i32, 2, "SelectImmShifterOperand",
483 [shl, srl, sra, rotr]> {
484 let EncoderMethod = "getSORegImmOpValue";
485 let PrintMethod = "printSORegImmOperand";
486 let DecoderMethod = "DecodeSORegImmOperand";
487 let ParserMatchClass = ShiftedImmAsmOperand;
488 let MIOperandInfo = (ops GPR, i32imm);
491 // FIXME: Does this need to be distinct from so_reg?
492 def shift_so_reg_reg : Operand<i32>, // reg reg imm
493 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
494 [shl,srl,sra,rotr]> {
495 let EncoderMethod = "getSORegRegOpValue";
496 let PrintMethod = "printSORegRegOperand";
497 let DecoderMethod = "DecodeSORegRegOperand";
498 let ParserMatchClass = ShiftedRegAsmOperand;
499 let MIOperandInfo = (ops GPR, GPR, i32imm);
502 // FIXME: Does this need to be distinct from so_reg?
503 def shift_so_reg_imm : Operand<i32>, // reg reg imm
504 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
505 [shl,srl,sra,rotr]> {
506 let EncoderMethod = "getSORegImmOpValue";
507 let PrintMethod = "printSORegImmOperand";
508 let DecoderMethod = "DecodeSORegImmOperand";
509 let ParserMatchClass = ShiftedImmAsmOperand;
510 let MIOperandInfo = (ops GPR, i32imm);
514 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
515 // 8-bit immediate rotated by an arbitrary number of bits.
516 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
517 def so_imm : Operand<i32>, ImmLeaf<i32, [{
518 return ARM_AM::getSOImmVal(Imm) != -1;
520 let EncoderMethod = "getSOImmOpValue";
521 let ParserMatchClass = SOImmAsmOperand;
522 let DecoderMethod = "DecodeSOImmOperand";
525 // Break so_imm's up into two pieces. This handles immediates with up to 16
526 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
527 // get the first/second pieces.
528 def so_imm2part : PatLeaf<(imm), [{
529 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
532 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
534 def arm_i32imm : PatLeaf<(imm), [{
535 if (Subtarget->hasV6T2Ops())
537 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
540 /// imm0_1 predicate - Immediate in the range [0,1].
541 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
542 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
544 /// imm0_3 predicate - Immediate in the range [0,3].
545 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
546 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
548 /// imm0_7 predicate - Immediate in the range [0,7].
549 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
550 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
551 return Imm >= 0 && Imm < 8;
553 let ParserMatchClass = Imm0_7AsmOperand;
556 /// imm8 predicate - Immediate is exactly 8.
557 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
558 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
559 let ParserMatchClass = Imm8AsmOperand;
562 /// imm16 predicate - Immediate is exactly 16.
563 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
564 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
565 let ParserMatchClass = Imm16AsmOperand;
568 /// imm32 predicate - Immediate is exactly 32.
569 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
570 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
571 let ParserMatchClass = Imm32AsmOperand;
574 /// imm1_7 predicate - Immediate in the range [1,7].
575 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
576 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
577 let ParserMatchClass = Imm1_7AsmOperand;
580 /// imm1_15 predicate - Immediate in the range [1,15].
581 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
582 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
583 let ParserMatchClass = Imm1_15AsmOperand;
586 /// imm1_31 predicate - Immediate in the range [1,31].
587 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
588 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
589 let ParserMatchClass = Imm1_31AsmOperand;
592 /// imm0_15 predicate - Immediate in the range [0,15].
593 def Imm0_15AsmOperand: ImmAsmOperand {
594 let Name = "Imm0_15";
595 let DiagnosticType = "ImmRange0_15";
597 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
598 return Imm >= 0 && Imm < 16;
600 let ParserMatchClass = Imm0_15AsmOperand;
603 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
604 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
605 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
606 return Imm >= 0 && Imm < 32;
608 let ParserMatchClass = Imm0_31AsmOperand;
611 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
612 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
613 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
614 return Imm >= 0 && Imm < 32;
616 let ParserMatchClass = Imm0_32AsmOperand;
619 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
620 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
621 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
622 return Imm >= 0 && Imm < 64;
624 let ParserMatchClass = Imm0_63AsmOperand;
627 /// imm0_255 predicate - Immediate in the range [0,255].
628 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
629 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
630 let ParserMatchClass = Imm0_255AsmOperand;
633 /// imm0_65535 - An immediate is in the range [0.65535].
634 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
635 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
636 return Imm >= 0 && Imm < 65536;
638 let ParserMatchClass = Imm0_65535AsmOperand;
641 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
642 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
643 return -Imm >= 0 && -Imm < 65536;
646 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
647 // a relocatable expression.
649 // FIXME: This really needs a Thumb version separate from the ARM version.
650 // While the range is the same, and can thus use the same match class,
651 // the encoding is different so it should have a different encoder method.
652 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
653 def imm0_65535_expr : Operand<i32> {
654 let EncoderMethod = "getHiLo16ImmOpValue";
655 let ParserMatchClass = Imm0_65535ExprAsmOperand;
658 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
659 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
660 def imm24b : Operand<i32>, ImmLeaf<i32, [{
661 return Imm >= 0 && Imm <= 0xffffff;
663 let ParserMatchClass = Imm24bitAsmOperand;
667 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
669 def BitfieldAsmOperand : AsmOperandClass {
670 let Name = "Bitfield";
671 let ParserMethod = "parseBitfield";
674 def bf_inv_mask_imm : Operand<i32>,
676 return ARM::isBitFieldInvertedMask(N->getZExtValue());
678 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
679 let PrintMethod = "printBitfieldInvMaskImmOperand";
680 let DecoderMethod = "DecodeBitfieldMaskOperand";
681 let ParserMatchClass = BitfieldAsmOperand;
684 def imm1_32_XFORM: SDNodeXForm<imm, [{
685 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
687 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
688 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
689 uint64_t Imm = N->getZExtValue();
690 return Imm > 0 && Imm <= 32;
693 let PrintMethod = "printImmPlusOneOperand";
694 let ParserMatchClass = Imm1_32AsmOperand;
697 def imm1_16_XFORM: SDNodeXForm<imm, [{
698 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
700 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
701 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
703 let PrintMethod = "printImmPlusOneOperand";
704 let ParserMatchClass = Imm1_16AsmOperand;
707 // Define ARM specific addressing modes.
708 // addrmode_imm12 := reg +/- imm12
710 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
711 def addrmode_imm12 : Operand<i32>,
712 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
713 // 12-bit immediate operand. Note that instructions using this encode
714 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
715 // immediate values are as normal.
717 let EncoderMethod = "getAddrModeImm12OpValue";
718 let PrintMethod = "printAddrModeImm12Operand";
719 let DecoderMethod = "DecodeAddrModeImm12Operand";
720 let ParserMatchClass = MemImm12OffsetAsmOperand;
721 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
723 // ldst_so_reg := reg +/- reg shop imm
725 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
726 def ldst_so_reg : Operand<i32>,
727 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
728 let EncoderMethod = "getLdStSORegOpValue";
729 // FIXME: Simplify the printer
730 let PrintMethod = "printAddrMode2Operand";
731 let DecoderMethod = "DecodeSORegMemOperand";
732 let ParserMatchClass = MemRegOffsetAsmOperand;
733 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
736 // postidx_imm8 := +/- [0,255]
739 // {8} 1 is imm8 is non-negative. 0 otherwise.
740 // {7-0} [0,255] imm8 value.
741 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
742 def postidx_imm8 : Operand<i32> {
743 let PrintMethod = "printPostIdxImm8Operand";
744 let ParserMatchClass = PostIdxImm8AsmOperand;
745 let MIOperandInfo = (ops i32imm);
748 // postidx_imm8s4 := +/- [0,1020]
751 // {8} 1 is imm8 is non-negative. 0 otherwise.
752 // {7-0} [0,255] imm8 value, scaled by 4.
753 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
754 def postidx_imm8s4 : Operand<i32> {
755 let PrintMethod = "printPostIdxImm8s4Operand";
756 let ParserMatchClass = PostIdxImm8s4AsmOperand;
757 let MIOperandInfo = (ops i32imm);
761 // postidx_reg := +/- reg
763 def PostIdxRegAsmOperand : AsmOperandClass {
764 let Name = "PostIdxReg";
765 let ParserMethod = "parsePostIdxReg";
767 def postidx_reg : Operand<i32> {
768 let EncoderMethod = "getPostIdxRegOpValue";
769 let DecoderMethod = "DecodePostIdxReg";
770 let PrintMethod = "printPostIdxRegOperand";
771 let ParserMatchClass = PostIdxRegAsmOperand;
772 let MIOperandInfo = (ops GPRnopc, i32imm);
776 // addrmode2 := reg +/- imm12
777 // := reg +/- reg shop imm
779 // FIXME: addrmode2 should be refactored the rest of the way to always
780 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
781 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
782 def addrmode2 : Operand<i32>,
783 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
784 let EncoderMethod = "getAddrMode2OpValue";
785 let PrintMethod = "printAddrMode2Operand";
786 let ParserMatchClass = AddrMode2AsmOperand;
787 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
790 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
791 let Name = "PostIdxRegShifted";
792 let ParserMethod = "parsePostIdxReg";
794 def am2offset_reg : Operand<i32>,
795 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
796 [], [SDNPWantRoot]> {
797 let EncoderMethod = "getAddrMode2OffsetOpValue";
798 let PrintMethod = "printAddrMode2OffsetOperand";
799 // When using this for assembly, it's always as a post-index offset.
800 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
801 let MIOperandInfo = (ops GPRnopc, i32imm);
804 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
805 // the GPR is purely vestigal at this point.
806 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
807 def am2offset_imm : Operand<i32>,
808 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
809 [], [SDNPWantRoot]> {
810 let EncoderMethod = "getAddrMode2OffsetOpValue";
811 let PrintMethod = "printAddrMode2OffsetOperand";
812 let ParserMatchClass = AM2OffsetImmAsmOperand;
813 let MIOperandInfo = (ops GPRnopc, i32imm);
817 // addrmode3 := reg +/- reg
818 // addrmode3 := reg +/- imm8
820 // FIXME: split into imm vs. reg versions.
821 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
822 def addrmode3 : Operand<i32>,
823 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
824 let EncoderMethod = "getAddrMode3OpValue";
825 let PrintMethod = "printAddrMode3Operand";
826 let ParserMatchClass = AddrMode3AsmOperand;
827 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
830 // FIXME: split into imm vs. reg versions.
831 // FIXME: parser method to handle +/- register.
832 def AM3OffsetAsmOperand : AsmOperandClass {
833 let Name = "AM3Offset";
834 let ParserMethod = "parseAM3Offset";
836 def am3offset : Operand<i32>,
837 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
838 [], [SDNPWantRoot]> {
839 let EncoderMethod = "getAddrMode3OffsetOpValue";
840 let PrintMethod = "printAddrMode3OffsetOperand";
841 let ParserMatchClass = AM3OffsetAsmOperand;
842 let MIOperandInfo = (ops GPR, i32imm);
845 // ldstm_mode := {ia, ib, da, db}
847 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
848 let EncoderMethod = "getLdStmModeOpValue";
849 let PrintMethod = "printLdStmModeOperand";
852 // addrmode5 := reg +/- imm8*4
854 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
855 def addrmode5 : Operand<i32>,
856 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
857 let PrintMethod = "printAddrMode5Operand";
858 let EncoderMethod = "getAddrMode5OpValue";
859 let DecoderMethod = "DecodeAddrMode5Operand";
860 let ParserMatchClass = AddrMode5AsmOperand;
861 let MIOperandInfo = (ops GPR:$base, i32imm);
864 // addrmode6 := reg with optional alignment
866 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
867 def addrmode6 : Operand<i32>,
868 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
869 let PrintMethod = "printAddrMode6Operand";
870 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
871 let EncoderMethod = "getAddrMode6AddressOpValue";
872 let DecoderMethod = "DecodeAddrMode6Operand";
873 let ParserMatchClass = AddrMode6AsmOperand;
876 def am6offset : Operand<i32>,
877 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
878 [], [SDNPWantRoot]> {
879 let PrintMethod = "printAddrMode6OffsetOperand";
880 let MIOperandInfo = (ops GPR);
881 let EncoderMethod = "getAddrMode6OffsetOpValue";
882 let DecoderMethod = "DecodeGPRRegisterClass";
885 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
886 // (single element from one lane) for size 32.
887 def addrmode6oneL32 : Operand<i32>,
888 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
889 let PrintMethod = "printAddrMode6Operand";
890 let MIOperandInfo = (ops GPR:$addr, i32imm);
891 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
894 // Special version of addrmode6 to handle alignment encoding for VLD-dup
895 // instructions, specifically VLD4-dup.
896 def addrmode6dup : Operand<i32>,
897 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
898 let PrintMethod = "printAddrMode6Operand";
899 let MIOperandInfo = (ops GPR:$addr, i32imm);
900 let EncoderMethod = "getAddrMode6DupAddressOpValue";
901 // FIXME: This is close, but not quite right. The alignment specifier is
903 let ParserMatchClass = AddrMode6AsmOperand;
906 // addrmodepc := pc + reg
908 def addrmodepc : Operand<i32>,
909 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
910 let PrintMethod = "printAddrModePCOperand";
911 let MIOperandInfo = (ops GPR, i32imm);
914 // addr_offset_none := reg
916 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
917 def addr_offset_none : Operand<i32>,
918 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
919 let PrintMethod = "printAddrMode7Operand";
920 let DecoderMethod = "DecodeAddrMode7Operand";
921 let ParserMatchClass = MemNoOffsetAsmOperand;
922 let MIOperandInfo = (ops GPR:$base);
925 def nohash_imm : Operand<i32> {
926 let PrintMethod = "printNoHashImmediate";
929 def CoprocNumAsmOperand : AsmOperandClass {
930 let Name = "CoprocNum";
931 let ParserMethod = "parseCoprocNumOperand";
933 def p_imm : Operand<i32> {
934 let PrintMethod = "printPImmediate";
935 let ParserMatchClass = CoprocNumAsmOperand;
936 let DecoderMethod = "DecodeCoprocessor";
939 def pf_imm : Operand<i32> {
940 let PrintMethod = "printPImmediate";
941 let ParserMatchClass = CoprocNumAsmOperand;
944 def CoprocRegAsmOperand : AsmOperandClass {
945 let Name = "CoprocReg";
946 let ParserMethod = "parseCoprocRegOperand";
948 def c_imm : Operand<i32> {
949 let PrintMethod = "printCImmediate";
950 let ParserMatchClass = CoprocRegAsmOperand;
952 def CoprocOptionAsmOperand : AsmOperandClass {
953 let Name = "CoprocOption";
954 let ParserMethod = "parseCoprocOptionOperand";
956 def coproc_option_imm : Operand<i32> {
957 let PrintMethod = "printCoprocOptionImm";
958 let ParserMatchClass = CoprocOptionAsmOperand;
961 //===----------------------------------------------------------------------===//
963 include "ARMInstrFormats.td"
965 //===----------------------------------------------------------------------===//
966 // Multiclass helpers...
969 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
970 /// binop that produces a value.
971 let TwoOperandAliasConstraint = "$Rn = $Rd" in
972 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
973 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
974 PatFrag opnode, bit Commutable = 0> {
975 // The register-immediate version is re-materializable. This is useful
976 // in particular for taking the address of a local.
977 let isReMaterializable = 1 in {
978 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
979 iii, opc, "\t$Rd, $Rn, $imm",
980 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
985 let Inst{19-16} = Rn;
986 let Inst{15-12} = Rd;
987 let Inst{11-0} = imm;
990 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
991 iir, opc, "\t$Rd, $Rn, $Rm",
992 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
997 let isCommutable = Commutable;
998 let Inst{19-16} = Rn;
999 let Inst{15-12} = Rd;
1000 let Inst{11-4} = 0b00000000;
1004 def rsi : AsI1<opcod, (outs GPR:$Rd),
1005 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1006 iis, opc, "\t$Rd, $Rn, $shift",
1007 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1012 let Inst{19-16} = Rn;
1013 let Inst{15-12} = Rd;
1014 let Inst{11-5} = shift{11-5};
1016 let Inst{3-0} = shift{3-0};
1019 def rsr : AsI1<opcod, (outs GPR:$Rd),
1020 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1021 iis, opc, "\t$Rd, $Rn, $shift",
1022 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1027 let Inst{19-16} = Rn;
1028 let Inst{15-12} = Rd;
1029 let Inst{11-8} = shift{11-8};
1031 let Inst{6-5} = shift{6-5};
1033 let Inst{3-0} = shift{3-0};
1037 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1038 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1039 /// it is equivalent to the AsI1_bin_irs counterpart.
1040 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1041 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1042 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1043 PatFrag opnode, bit Commutable = 0> {
1044 // The register-immediate version is re-materializable. This is useful
1045 // in particular for taking the address of a local.
1046 let isReMaterializable = 1 in {
1047 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1048 iii, opc, "\t$Rd, $Rn, $imm",
1049 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1054 let Inst{19-16} = Rn;
1055 let Inst{15-12} = Rd;
1056 let Inst{11-0} = imm;
1059 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1060 iir, opc, "\t$Rd, $Rn, $Rm",
1061 [/* pattern left blank */]> {
1065 let Inst{11-4} = 0b00000000;
1068 let Inst{15-12} = Rd;
1069 let Inst{19-16} = Rn;
1072 def rsi : AsI1<opcod, (outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1074 iis, opc, "\t$Rd, $Rn, $shift",
1075 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1080 let Inst{19-16} = Rn;
1081 let Inst{15-12} = Rd;
1082 let Inst{11-5} = shift{11-5};
1084 let Inst{3-0} = shift{3-0};
1087 def rsr : AsI1<opcod, (outs GPR:$Rd),
1088 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1089 iis, opc, "\t$Rd, $Rn, $shift",
1090 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1095 let Inst{19-16} = Rn;
1096 let Inst{15-12} = Rd;
1097 let Inst{11-8} = shift{11-8};
1099 let Inst{6-5} = shift{6-5};
1101 let Inst{3-0} = shift{3-0};
1105 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1107 /// These opcodes will be converted to the real non-S opcodes by
1108 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1109 let hasPostISelHook = 1, Defs = [CPSR] in {
1110 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1111 InstrItinClass iis, PatFrag opnode,
1112 bit Commutable = 0> {
1113 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1115 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1117 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1119 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1120 let isCommutable = Commutable;
1122 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1123 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1125 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1126 so_reg_imm:$shift))]>;
1128 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1129 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1131 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1132 so_reg_reg:$shift))]>;
1136 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1137 /// operands are reversed.
1138 let hasPostISelHook = 1, Defs = [CPSR] in {
1139 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1140 InstrItinClass iis, PatFrag opnode,
1141 bit Commutable = 0> {
1142 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1144 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1146 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1147 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1149 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1152 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1153 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1155 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1160 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1161 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1162 /// a explicit result, only implicitly set CPSR.
1163 let isCompare = 1, Defs = [CPSR] in {
1164 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1165 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1166 PatFrag opnode, bit Commutable = 0> {
1167 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1169 [(opnode GPR:$Rn, so_imm:$imm)]> {
1174 let Inst{19-16} = Rn;
1175 let Inst{15-12} = 0b0000;
1176 let Inst{11-0} = imm;
1178 let Unpredictable{15-12} = 0b1111;
1180 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1182 [(opnode GPR:$Rn, GPR:$Rm)]> {
1185 let isCommutable = Commutable;
1188 let Inst{19-16} = Rn;
1189 let Inst{15-12} = 0b0000;
1190 let Inst{11-4} = 0b00000000;
1193 let Unpredictable{15-12} = 0b1111;
1195 def rsi : AI1<opcod, (outs),
1196 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1197 opc, "\t$Rn, $shift",
1198 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1203 let Inst{19-16} = Rn;
1204 let Inst{15-12} = 0b0000;
1205 let Inst{11-5} = shift{11-5};
1207 let Inst{3-0} = shift{3-0};
1209 let Unpredictable{15-12} = 0b1111;
1211 def rsr : AI1<opcod, (outs),
1212 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1213 opc, "\t$Rn, $shift",
1214 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1219 let Inst{19-16} = Rn;
1220 let Inst{15-12} = 0b0000;
1221 let Inst{11-8} = shift{11-8};
1223 let Inst{6-5} = shift{6-5};
1225 let Inst{3-0} = shift{3-0};
1227 let Unpredictable{15-12} = 0b1111;
1233 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1234 /// register and one whose operand is a register rotated by 8/16/24.
1235 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1236 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1237 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1238 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1239 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1240 Requires<[IsARM, HasV6]> {
1244 let Inst{19-16} = 0b1111;
1245 let Inst{15-12} = Rd;
1246 let Inst{11-10} = rot;
1250 class AI_ext_rrot_np<bits<8> opcod, string opc>
1251 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1252 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1253 Requires<[IsARM, HasV6]> {
1255 let Inst{19-16} = 0b1111;
1256 let Inst{11-10} = rot;
1259 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1260 /// register and one whose operand is a register rotated by 8/16/24.
1261 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1262 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1263 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1264 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1265 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1266 Requires<[IsARM, HasV6]> {
1271 let Inst{19-16} = Rn;
1272 let Inst{15-12} = Rd;
1273 let Inst{11-10} = rot;
1274 let Inst{9-4} = 0b000111;
1278 class AI_exta_rrot_np<bits<8> opcod, string opc>
1279 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1280 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1281 Requires<[IsARM, HasV6]> {
1284 let Inst{19-16} = Rn;
1285 let Inst{11-10} = rot;
1288 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1289 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1290 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1291 bit Commutable = 0> {
1292 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1293 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1294 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1295 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1301 let Inst{15-12} = Rd;
1302 let Inst{19-16} = Rn;
1303 let Inst{11-0} = imm;
1305 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1306 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1307 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1312 let Inst{11-4} = 0b00000000;
1314 let isCommutable = Commutable;
1316 let Inst{15-12} = Rd;
1317 let Inst{19-16} = Rn;
1319 def rsi : AsI1<opcod, (outs GPR:$Rd),
1320 (ins GPR:$Rn, so_reg_imm:$shift),
1321 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1322 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1328 let Inst{19-16} = Rn;
1329 let Inst{15-12} = Rd;
1330 let Inst{11-5} = shift{11-5};
1332 let Inst{3-0} = shift{3-0};
1334 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1335 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1336 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1337 [(set GPRnopc:$Rd, CPSR,
1338 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1344 let Inst{19-16} = Rn;
1345 let Inst{15-12} = Rd;
1346 let Inst{11-8} = shift{11-8};
1348 let Inst{6-5} = shift{6-5};
1350 let Inst{3-0} = shift{3-0};
1355 /// AI1_rsc_irs - Define instructions and patterns for rsc
1356 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1357 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1358 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1359 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1360 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1361 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1367 let Inst{15-12} = Rd;
1368 let Inst{19-16} = Rn;
1369 let Inst{11-0} = imm;
1371 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1372 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1373 [/* pattern left blank */]> {
1377 let Inst{11-4} = 0b00000000;
1380 let Inst{15-12} = Rd;
1381 let Inst{19-16} = Rn;
1383 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1384 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1385 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1391 let Inst{19-16} = Rn;
1392 let Inst{15-12} = Rd;
1393 let Inst{11-5} = shift{11-5};
1395 let Inst{3-0} = shift{3-0};
1397 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1398 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1399 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1405 let Inst{19-16} = Rn;
1406 let Inst{15-12} = Rd;
1407 let Inst{11-8} = shift{11-8};
1409 let Inst{6-5} = shift{6-5};
1411 let Inst{3-0} = shift{3-0};
1416 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1417 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1418 InstrItinClass iir, PatFrag opnode> {
1419 // Note: We use the complex addrmode_imm12 rather than just an input
1420 // GPR and a constrained immediate so that we can use this to match
1421 // frame index references and avoid matching constant pool references.
1422 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1423 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1424 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1427 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1428 let Inst{19-16} = addr{16-13}; // Rn
1429 let Inst{15-12} = Rt;
1430 let Inst{11-0} = addr{11-0}; // imm12
1432 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1433 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1434 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1437 let shift{4} = 0; // Inst{4} = 0
1438 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1439 let Inst{19-16} = shift{16-13}; // Rn
1440 let Inst{15-12} = Rt;
1441 let Inst{11-0} = shift{11-0};
1446 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1447 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1448 InstrItinClass iir, PatFrag opnode> {
1449 // Note: We use the complex addrmode_imm12 rather than just an input
1450 // GPR and a constrained immediate so that we can use this to match
1451 // frame index references and avoid matching constant pool references.
1452 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1453 (ins addrmode_imm12:$addr),
1454 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1455 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1458 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1459 let Inst{19-16} = addr{16-13}; // Rn
1460 let Inst{15-12} = Rt;
1461 let Inst{11-0} = addr{11-0}; // imm12
1463 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1464 (ins ldst_so_reg:$shift),
1465 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1466 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1469 let shift{4} = 0; // Inst{4} = 0
1470 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1471 let Inst{19-16} = shift{16-13}; // Rn
1472 let Inst{15-12} = Rt;
1473 let Inst{11-0} = shift{11-0};
1479 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1480 InstrItinClass iir, PatFrag opnode> {
1481 // Note: We use the complex addrmode_imm12 rather than just an input
1482 // GPR and a constrained immediate so that we can use this to match
1483 // frame index references and avoid matching constant pool references.
1484 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1485 (ins GPR:$Rt, addrmode_imm12:$addr),
1486 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1487 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1490 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1491 let Inst{19-16} = addr{16-13}; // Rn
1492 let Inst{15-12} = Rt;
1493 let Inst{11-0} = addr{11-0}; // imm12
1495 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1496 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1497 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1500 let shift{4} = 0; // Inst{4} = 0
1501 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1502 let Inst{19-16} = shift{16-13}; // Rn
1503 let Inst{15-12} = Rt;
1504 let Inst{11-0} = shift{11-0};
1508 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1509 InstrItinClass iir, PatFrag opnode> {
1510 // Note: We use the complex addrmode_imm12 rather than just an input
1511 // GPR and a constrained immediate so that we can use this to match
1512 // frame index references and avoid matching constant pool references.
1513 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1514 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1515 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1516 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1519 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1520 let Inst{19-16} = addr{16-13}; // Rn
1521 let Inst{15-12} = Rt;
1522 let Inst{11-0} = addr{11-0}; // imm12
1524 def rs : AI2ldst<0b011, 0, isByte, (outs),
1525 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1526 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1527 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1530 let shift{4} = 0; // Inst{4} = 0
1531 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1532 let Inst{19-16} = shift{16-13}; // Rn
1533 let Inst{15-12} = Rt;
1534 let Inst{11-0} = shift{11-0};
1539 //===----------------------------------------------------------------------===//
1541 //===----------------------------------------------------------------------===//
1543 //===----------------------------------------------------------------------===//
1544 // Miscellaneous Instructions.
1547 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1548 /// the function. The first operand is the ID# for this instruction, the second
1549 /// is the index into the MachineConstantPool that this is, the third is the
1550 /// size in bytes of this constant pool entry.
1551 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1552 def CONSTPOOL_ENTRY :
1553 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1554 i32imm:$size), NoItinerary, []>;
1556 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1557 // from removing one half of the matched pairs. That breaks PEI, which assumes
1558 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1559 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1560 def ADJCALLSTACKUP :
1561 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1562 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1564 def ADJCALLSTACKDOWN :
1565 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1566 [(ARMcallseq_start timm:$amt)]>;
1569 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1570 // (These pseudos use a hand-written selection code).
1571 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1572 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1573 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1575 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1576 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1578 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1579 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1581 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1582 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1584 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1585 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1587 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1588 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1590 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1591 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1593 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1594 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1595 GPR:$set1, GPR:$set2),
1599 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1600 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1602 let Inst{27-8} = 0b00110010000011110000;
1603 let Inst{7-0} = imm;
1606 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1607 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1608 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1609 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1610 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1612 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1613 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1618 let Inst{15-12} = Rd;
1619 let Inst{19-16} = Rn;
1620 let Inst{27-20} = 0b01101000;
1621 let Inst{7-4} = 0b1011;
1622 let Inst{11-8} = 0b1111;
1623 let Unpredictable{11-8} = 0b1111;
1626 // The 16-bit operand $val can be used by a debugger to store more information
1627 // about the breakpoint.
1628 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1629 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1631 let Inst{3-0} = val{3-0};
1632 let Inst{19-8} = val{15-4};
1633 let Inst{27-20} = 0b00010010;
1634 let Inst{7-4} = 0b0111;
1637 // Change Processor State
1638 // FIXME: We should use InstAlias to handle the optional operands.
1639 class CPS<dag iops, string asm_ops>
1640 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1641 []>, Requires<[IsARM]> {
1647 let Inst{31-28} = 0b1111;
1648 let Inst{27-20} = 0b00010000;
1649 let Inst{19-18} = imod;
1650 let Inst{17} = M; // Enabled if mode is set;
1651 let Inst{16-9} = 0b00000000;
1652 let Inst{8-6} = iflags;
1654 let Inst{4-0} = mode;
1657 let DecoderMethod = "DecodeCPSInstruction" in {
1659 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1660 "$imod\t$iflags, $mode">;
1661 let mode = 0, M = 0 in
1662 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1664 let imod = 0, iflags = 0, M = 1 in
1665 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1668 // Preload signals the memory system of possible future data/instruction access.
1669 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1671 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1672 !strconcat(opc, "\t$addr"),
1673 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1676 let Inst{31-26} = 0b111101;
1677 let Inst{25} = 0; // 0 for immediate form
1678 let Inst{24} = data;
1679 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1680 let Inst{22} = read;
1681 let Inst{21-20} = 0b01;
1682 let Inst{19-16} = addr{16-13}; // Rn
1683 let Inst{15-12} = 0b1111;
1684 let Inst{11-0} = addr{11-0}; // imm12
1687 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1688 !strconcat(opc, "\t$shift"),
1689 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1691 let Inst{31-26} = 0b111101;
1692 let Inst{25} = 1; // 1 for register form
1693 let Inst{24} = data;
1694 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1695 let Inst{22} = read;
1696 let Inst{21-20} = 0b01;
1697 let Inst{19-16} = shift{16-13}; // Rn
1698 let Inst{15-12} = 0b1111;
1699 let Inst{11-0} = shift{11-0};
1704 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1705 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1706 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1708 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1709 "setend\t$end", []>, Requires<[IsARM]> {
1711 let Inst{31-10} = 0b1111000100000001000000;
1716 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1717 []>, Requires<[IsARM, HasV7]> {
1719 let Inst{27-4} = 0b001100100000111100001111;
1720 let Inst{3-0} = opt;
1723 // A5.4 Permanently UNDEFINED instructions.
1724 let isBarrier = 1, isTerminator = 1 in
1725 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1728 let Inst = 0xe7ffdefe;
1731 // Address computation and loads and stores in PIC mode.
1732 let isNotDuplicable = 1 in {
1733 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1735 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1737 let AddedComplexity = 10 in {
1738 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1740 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1742 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1744 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1746 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1748 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1750 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1752 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1754 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1756 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1758 let AddedComplexity = 10 in {
1759 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1760 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1762 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1763 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1764 addrmodepc:$addr)]>;
1766 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1767 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1769 } // isNotDuplicable = 1
1772 // LEApcrel - Load a pc-relative address into a register without offending the
1774 let neverHasSideEffects = 1, isReMaterializable = 1 in
1775 // The 'adr' mnemonic encodes differently if the label is before or after
1776 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1777 // know until then which form of the instruction will be used.
1778 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1779 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1782 let Inst{27-25} = 0b001;
1784 let Inst{23-22} = label{13-12};
1787 let Inst{19-16} = 0b1111;
1788 let Inst{15-12} = Rd;
1789 let Inst{11-0} = label{11-0};
1791 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1794 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1795 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1798 //===----------------------------------------------------------------------===//
1799 // Control Flow Instructions.
1802 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1804 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1805 "bx", "\tlr", [(ARMretflag)]>,
1806 Requires<[IsARM, HasV4T]> {
1807 let Inst{27-0} = 0b0001001011111111111100011110;
1811 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1812 "mov", "\tpc, lr", [(ARMretflag)]>,
1813 Requires<[IsARM, NoV4T]> {
1814 let Inst{27-0} = 0b0001101000001111000000001110;
1818 // Indirect branches
1819 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1821 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1822 [(brind GPR:$dst)]>,
1823 Requires<[IsARM, HasV4T]> {
1825 let Inst{31-4} = 0b1110000100101111111111110001;
1826 let Inst{3-0} = dst;
1829 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1830 "bx", "\t$dst", [/* pattern left blank */]>,
1831 Requires<[IsARM, HasV4T]> {
1833 let Inst{27-4} = 0b000100101111111111110001;
1834 let Inst{3-0} = dst;
1838 // SP is marked as a use to prevent stack-pointer assignments that appear
1839 // immediately before calls from potentially appearing dead.
1841 // FIXME: Do we really need a non-predicated version? If so, it should
1842 // at least be a pseudo instruction expanding to the predicated version
1843 // at MC lowering time.
1844 Defs = [LR], Uses = [SP] in {
1845 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1846 IIC_Br, "bl\t$func",
1847 [(ARMcall tglobaladdr:$func)]>,
1849 let Inst{31-28} = 0b1110;
1851 let Inst{23-0} = func;
1852 let DecoderMethod = "DecodeBranchImmInstruction";
1855 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1856 IIC_Br, "bl", "\t$func",
1857 [(ARMcall_pred tglobaladdr:$func)]>,
1860 let Inst{23-0} = func;
1861 let DecoderMethod = "DecodeBranchImmInstruction";
1865 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1866 IIC_Br, "blx\t$func",
1867 [(ARMcall GPR:$func)]>,
1868 Requires<[IsARM, HasV5T]> {
1870 let Inst{31-4} = 0b1110000100101111111111110011;
1871 let Inst{3-0} = func;
1874 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1875 IIC_Br, "blx", "\t$func",
1876 [(ARMcall_pred GPR:$func)]>,
1877 Requires<[IsARM, HasV5T]> {
1879 let Inst{27-4} = 0b000100101111111111110011;
1880 let Inst{3-0} = func;
1884 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1885 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1886 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1887 Requires<[IsARM, HasV4T]>;
1890 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1891 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1892 Requires<[IsARM, NoV4T]>;
1894 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1895 // return stack predictor.
1896 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1897 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1901 let isBranch = 1, isTerminator = 1 in {
1902 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1903 // a two-value operand where a dag node expects two operands. :(
1904 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1905 IIC_Br, "b", "\t$target",
1906 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1908 let Inst{23-0} = target;
1909 let DecoderMethod = "DecodeBranchImmInstruction";
1912 let isBarrier = 1 in {
1913 // B is "predicable" since it's just a Bcc with an 'always' condition.
1914 let isPredicable = 1 in
1915 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1916 // should be sufficient.
1917 // FIXME: Is B really a Barrier? That doesn't seem right.
1918 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1919 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1921 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1922 def BR_JTr : ARMPseudoInst<(outs),
1923 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1925 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1926 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1927 // into i12 and rs suffixed versions.
1928 def BR_JTm : ARMPseudoInst<(outs),
1929 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1931 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1933 def BR_JTadd : ARMPseudoInst<(outs),
1934 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1936 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1938 } // isNotDuplicable = 1, isIndirectBranch = 1
1944 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1945 "blx\t$target", []>,
1946 Requires<[IsARM, HasV5T]> {
1947 let Inst{31-25} = 0b1111101;
1949 let Inst{23-0} = target{24-1};
1950 let Inst{24} = target{0};
1953 // Branch and Exchange Jazelle
1954 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1955 [/* pattern left blank */]> {
1957 let Inst{23-20} = 0b0010;
1958 let Inst{19-8} = 0xfff;
1959 let Inst{7-4} = 0b0010;
1960 let Inst{3-0} = func;
1965 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1966 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
1968 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
1970 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
1972 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1975 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
1981 // Secure Monitor Call is a system instruction.
1982 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1985 let Inst{23-4} = 0b01100000000000000111;
1986 let Inst{3-0} = opt;
1989 // Supervisor Call (Software Interrupt)
1990 let isCall = 1, Uses = [SP] in {
1991 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1993 let Inst{23-0} = svc;
1997 // Store Return State
1998 class SRSI<bit wb, string asm>
1999 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2000 NoItinerary, asm, "", []> {
2002 let Inst{31-28} = 0b1111;
2003 let Inst{27-25} = 0b100;
2007 let Inst{19-16} = 0b1101; // SP
2008 let Inst{15-5} = 0b00000101000;
2009 let Inst{4-0} = mode;
2012 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2013 let Inst{24-23} = 0;
2015 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2016 let Inst{24-23} = 0;
2018 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2019 let Inst{24-23} = 0b10;
2021 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2022 let Inst{24-23} = 0b10;
2024 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2025 let Inst{24-23} = 0b01;
2027 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2028 let Inst{24-23} = 0b01;
2030 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2031 let Inst{24-23} = 0b11;
2033 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2034 let Inst{24-23} = 0b11;
2037 // Return From Exception
2038 class RFEI<bit wb, string asm>
2039 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2040 NoItinerary, asm, "", []> {
2042 let Inst{31-28} = 0b1111;
2043 let Inst{27-25} = 0b100;
2047 let Inst{19-16} = Rn;
2048 let Inst{15-0} = 0xa00;
2051 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2052 let Inst{24-23} = 0;
2054 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2055 let Inst{24-23} = 0;
2057 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2058 let Inst{24-23} = 0b10;
2060 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2061 let Inst{24-23} = 0b10;
2063 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2064 let Inst{24-23} = 0b01;
2066 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2067 let Inst{24-23} = 0b01;
2069 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2070 let Inst{24-23} = 0b11;
2072 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2073 let Inst{24-23} = 0b11;
2076 //===----------------------------------------------------------------------===//
2077 // Load / Store Instructions.
2083 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2084 UnOpFrag<(load node:$Src)>>;
2085 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2086 UnOpFrag<(zextloadi8 node:$Src)>>;
2087 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2088 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2089 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2090 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2092 // Special LDR for loads from non-pc-relative constpools.
2093 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2094 isReMaterializable = 1, isCodeGenOnly = 1 in
2095 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2096 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2100 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2101 let Inst{19-16} = 0b1111;
2102 let Inst{15-12} = Rt;
2103 let Inst{11-0} = addr{11-0}; // imm12
2106 // Loads with zero extension
2107 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2108 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2109 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2111 // Loads with sign extension
2112 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2113 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2114 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2116 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2117 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2118 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2120 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2122 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2123 (ins addrmode3:$addr), LdMiscFrm,
2124 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2125 []>, Requires<[IsARM, HasV5TE]>;
2129 multiclass AI2_ldridx<bit isByte, string opc,
2130 InstrItinClass iii, InstrItinClass iir> {
2131 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2132 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2133 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2136 let Inst{23} = addr{12};
2137 let Inst{19-16} = addr{16-13};
2138 let Inst{11-0} = addr{11-0};
2139 let DecoderMethod = "DecodeLDRPreImm";
2140 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2143 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2144 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2145 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2148 let Inst{23} = addr{12};
2149 let Inst{19-16} = addr{16-13};
2150 let Inst{11-0} = addr{11-0};
2152 let DecoderMethod = "DecodeLDRPreReg";
2153 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2156 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2157 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2158 IndexModePost, LdFrm, iir,
2159 opc, "\t$Rt, $addr, $offset",
2160 "$addr.base = $Rn_wb", []> {
2166 let Inst{23} = offset{12};
2167 let Inst{19-16} = addr;
2168 let Inst{11-0} = offset{11-0};
2170 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2173 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2174 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2175 IndexModePost, LdFrm, iii,
2176 opc, "\t$Rt, $addr, $offset",
2177 "$addr.base = $Rn_wb", []> {
2183 let Inst{23} = offset{12};
2184 let Inst{19-16} = addr;
2185 let Inst{11-0} = offset{11-0};
2187 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2192 let mayLoad = 1, neverHasSideEffects = 1 in {
2193 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2194 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2195 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2196 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2199 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2200 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2201 (ins addrmode3:$addr), IndexModePre,
2203 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2205 let Inst{23} = addr{8}; // U bit
2206 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2207 let Inst{19-16} = addr{12-9}; // Rn
2208 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2209 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2210 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2211 let DecoderMethod = "DecodeAddrMode3Instruction";
2213 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2214 (ins addr_offset_none:$addr, am3offset:$offset),
2215 IndexModePost, LdMiscFrm, itin,
2216 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2220 let Inst{23} = offset{8}; // U bit
2221 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2222 let Inst{19-16} = addr;
2223 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2224 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2225 let DecoderMethod = "DecodeAddrMode3Instruction";
2229 let mayLoad = 1, neverHasSideEffects = 1 in {
2230 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2231 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2232 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2233 let hasExtraDefRegAllocReq = 1 in {
2234 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2235 (ins addrmode3:$addr), IndexModePre,
2236 LdMiscFrm, IIC_iLoad_d_ru,
2237 "ldrd", "\t$Rt, $Rt2, $addr!",
2238 "$addr.base = $Rn_wb", []> {
2240 let Inst{23} = addr{8}; // U bit
2241 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2242 let Inst{19-16} = addr{12-9}; // Rn
2243 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2244 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2245 let DecoderMethod = "DecodeAddrMode3Instruction";
2246 let AsmMatchConverter = "cvtLdrdPre";
2248 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2249 (ins addr_offset_none:$addr, am3offset:$offset),
2250 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2251 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2252 "$addr.base = $Rn_wb", []> {
2255 let Inst{23} = offset{8}; // U bit
2256 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2257 let Inst{19-16} = addr;
2258 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2259 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2260 let DecoderMethod = "DecodeAddrMode3Instruction";
2262 } // hasExtraDefRegAllocReq = 1
2263 } // mayLoad = 1, neverHasSideEffects = 1
2265 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2266 let mayLoad = 1, neverHasSideEffects = 1 in {
2267 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2268 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2269 IndexModePost, LdFrm, IIC_iLoad_ru,
2270 "ldrt", "\t$Rt, $addr, $offset",
2271 "$addr.base = $Rn_wb", []> {
2277 let Inst{23} = offset{12};
2278 let Inst{21} = 1; // overwrite
2279 let Inst{19-16} = addr;
2280 let Inst{11-5} = offset{11-5};
2282 let Inst{3-0} = offset{3-0};
2283 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2286 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2287 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2288 IndexModePost, LdFrm, IIC_iLoad_ru,
2289 "ldrt", "\t$Rt, $addr, $offset",
2290 "$addr.base = $Rn_wb", []> {
2296 let Inst{23} = offset{12};
2297 let Inst{21} = 1; // overwrite
2298 let Inst{19-16} = addr;
2299 let Inst{11-0} = offset{11-0};
2300 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2303 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2304 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2305 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2306 "ldrbt", "\t$Rt, $addr, $offset",
2307 "$addr.base = $Rn_wb", []> {
2313 let Inst{23} = offset{12};
2314 let Inst{21} = 1; // overwrite
2315 let Inst{19-16} = addr;
2316 let Inst{11-5} = offset{11-5};
2318 let Inst{3-0} = offset{3-0};
2319 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2322 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2323 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2324 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2325 "ldrbt", "\t$Rt, $addr, $offset",
2326 "$addr.base = $Rn_wb", []> {
2332 let Inst{23} = offset{12};
2333 let Inst{21} = 1; // overwrite
2334 let Inst{19-16} = addr;
2335 let Inst{11-0} = offset{11-0};
2336 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2339 multiclass AI3ldrT<bits<4> op, string opc> {
2340 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2341 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2342 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2343 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2345 let Inst{23} = offset{8};
2347 let Inst{11-8} = offset{7-4};
2348 let Inst{3-0} = offset{3-0};
2349 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2351 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2352 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2353 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2354 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2356 let Inst{23} = Rm{4};
2359 let Unpredictable{11-8} = 0b1111;
2360 let Inst{3-0} = Rm{3-0};
2361 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2362 let DecoderMethod = "DecodeLDR";
2366 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2367 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2368 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2373 // Stores with truncate
2374 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2375 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2376 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2379 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2380 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2381 StMiscFrm, IIC_iStore_d_r,
2382 "strd", "\t$Rt, $src2, $addr", []>,
2383 Requires<[IsARM, HasV5TE]> {
2388 multiclass AI2_stridx<bit isByte, string opc,
2389 InstrItinClass iii, InstrItinClass iir> {
2390 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2391 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2393 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2396 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2397 let Inst{19-16} = addr{16-13}; // Rn
2398 let Inst{11-0} = addr{11-0}; // imm12
2399 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2400 let DecoderMethod = "DecodeSTRPreImm";
2403 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2404 (ins GPR:$Rt, ldst_so_reg:$addr),
2405 IndexModePre, StFrm, iir,
2406 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2409 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2410 let Inst{19-16} = addr{16-13}; // Rn
2411 let Inst{11-0} = addr{11-0};
2412 let Inst{4} = 0; // Inst{4} = 0
2413 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2414 let DecoderMethod = "DecodeSTRPreReg";
2416 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2417 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2418 IndexModePost, StFrm, iir,
2419 opc, "\t$Rt, $addr, $offset",
2420 "$addr.base = $Rn_wb", []> {
2426 let Inst{23} = offset{12};
2427 let Inst{19-16} = addr;
2428 let Inst{11-0} = offset{11-0};
2431 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2434 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2435 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2436 IndexModePost, StFrm, iii,
2437 opc, "\t$Rt, $addr, $offset",
2438 "$addr.base = $Rn_wb", []> {
2444 let Inst{23} = offset{12};
2445 let Inst{19-16} = addr;
2446 let Inst{11-0} = offset{11-0};
2448 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2452 let mayStore = 1, neverHasSideEffects = 1 in {
2453 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2454 // IIC_iStore_siu depending on whether it the offset register is shifted.
2455 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2456 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2459 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2460 am2offset_reg:$offset),
2461 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2462 am2offset_reg:$offset)>;
2463 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2464 am2offset_imm:$offset),
2465 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2466 am2offset_imm:$offset)>;
2467 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2468 am2offset_reg:$offset),
2469 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2470 am2offset_reg:$offset)>;
2471 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2472 am2offset_imm:$offset),
2473 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2474 am2offset_imm:$offset)>;
2476 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2477 // put the patterns on the instruction definitions directly as ISel wants
2478 // the address base and offset to be separate operands, not a single
2479 // complex operand like we represent the instructions themselves. The
2480 // pseudos map between the two.
2481 let usesCustomInserter = 1,
2482 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2483 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2484 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2487 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2488 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2489 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2492 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2493 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2494 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2497 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2498 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2499 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2502 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2503 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2504 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2507 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2512 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2513 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2514 StMiscFrm, IIC_iStore_bh_ru,
2515 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2517 let Inst{23} = addr{8}; // U bit
2518 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2519 let Inst{19-16} = addr{12-9}; // Rn
2520 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2521 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2522 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2523 let DecoderMethod = "DecodeAddrMode3Instruction";
2526 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2527 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2528 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2529 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2530 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2531 addr_offset_none:$addr,
2532 am3offset:$offset))]> {
2535 let Inst{23} = offset{8}; // U bit
2536 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2537 let Inst{19-16} = addr;
2538 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2539 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2540 let DecoderMethod = "DecodeAddrMode3Instruction";
2543 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2544 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2545 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2546 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2547 "strd", "\t$Rt, $Rt2, $addr!",
2548 "$addr.base = $Rn_wb", []> {
2550 let Inst{23} = addr{8}; // U bit
2551 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2552 let Inst{19-16} = addr{12-9}; // Rn
2553 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2554 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2555 let DecoderMethod = "DecodeAddrMode3Instruction";
2556 let AsmMatchConverter = "cvtStrdPre";
2559 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2560 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2562 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2563 "strd", "\t$Rt, $Rt2, $addr, $offset",
2564 "$addr.base = $Rn_wb", []> {
2567 let Inst{23} = offset{8}; // U bit
2568 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2569 let Inst{19-16} = addr;
2570 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2571 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2572 let DecoderMethod = "DecodeAddrMode3Instruction";
2574 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2576 // STRT, STRBT, and STRHT
2578 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2579 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2580 IndexModePost, StFrm, IIC_iStore_bh_ru,
2581 "strbt", "\t$Rt, $addr, $offset",
2582 "$addr.base = $Rn_wb", []> {
2588 let Inst{23} = offset{12};
2589 let Inst{21} = 1; // overwrite
2590 let Inst{19-16} = addr;
2591 let Inst{11-5} = offset{11-5};
2593 let Inst{3-0} = offset{3-0};
2594 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2597 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2598 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2599 IndexModePost, StFrm, IIC_iStore_bh_ru,
2600 "strbt", "\t$Rt, $addr, $offset",
2601 "$addr.base = $Rn_wb", []> {
2607 let Inst{23} = offset{12};
2608 let Inst{21} = 1; // overwrite
2609 let Inst{19-16} = addr;
2610 let Inst{11-0} = offset{11-0};
2611 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2614 let mayStore = 1, neverHasSideEffects = 1 in {
2615 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2616 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2617 IndexModePost, StFrm, IIC_iStore_ru,
2618 "strt", "\t$Rt, $addr, $offset",
2619 "$addr.base = $Rn_wb", []> {
2625 let Inst{23} = offset{12};
2626 let Inst{21} = 1; // overwrite
2627 let Inst{19-16} = addr;
2628 let Inst{11-5} = offset{11-5};
2630 let Inst{3-0} = offset{3-0};
2631 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2634 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2635 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2636 IndexModePost, StFrm, IIC_iStore_ru,
2637 "strt", "\t$Rt, $addr, $offset",
2638 "$addr.base = $Rn_wb", []> {
2644 let Inst{23} = offset{12};
2645 let Inst{21} = 1; // overwrite
2646 let Inst{19-16} = addr;
2647 let Inst{11-0} = offset{11-0};
2648 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2653 multiclass AI3strT<bits<4> op, string opc> {
2654 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2655 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2656 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2657 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2659 let Inst{23} = offset{8};
2661 let Inst{11-8} = offset{7-4};
2662 let Inst{3-0} = offset{3-0};
2663 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2665 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2666 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2667 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2668 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2670 let Inst{23} = Rm{4};
2673 let Inst{3-0} = Rm{3-0};
2674 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2679 defm STRHT : AI3strT<0b1011, "strht">;
2682 //===----------------------------------------------------------------------===//
2683 // Load / store multiple Instructions.
2686 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2687 InstrItinClass itin, InstrItinClass itin_upd> {
2688 // IA is the default, so no need for an explicit suffix on the
2689 // mnemonic here. Without it is the canonical spelling.
2691 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2692 IndexModeNone, f, itin,
2693 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2694 let Inst{24-23} = 0b01; // Increment After
2695 let Inst{22} = P_bit;
2696 let Inst{21} = 0; // No writeback
2697 let Inst{20} = L_bit;
2700 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2701 IndexModeUpd, f, itin_upd,
2702 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2703 let Inst{24-23} = 0b01; // Increment After
2704 let Inst{22} = P_bit;
2705 let Inst{21} = 1; // Writeback
2706 let Inst{20} = L_bit;
2708 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2711 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2712 IndexModeNone, f, itin,
2713 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2714 let Inst{24-23} = 0b00; // Decrement After
2715 let Inst{22} = P_bit;
2716 let Inst{21} = 0; // No writeback
2717 let Inst{20} = L_bit;
2720 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2721 IndexModeUpd, f, itin_upd,
2722 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2723 let Inst{24-23} = 0b00; // Decrement After
2724 let Inst{22} = P_bit;
2725 let Inst{21} = 1; // Writeback
2726 let Inst{20} = L_bit;
2728 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2731 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2732 IndexModeNone, f, itin,
2733 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2734 let Inst{24-23} = 0b10; // Decrement Before
2735 let Inst{22} = P_bit;
2736 let Inst{21} = 0; // No writeback
2737 let Inst{20} = L_bit;
2740 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2741 IndexModeUpd, f, itin_upd,
2742 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2743 let Inst{24-23} = 0b10; // Decrement Before
2744 let Inst{22} = P_bit;
2745 let Inst{21} = 1; // Writeback
2746 let Inst{20} = L_bit;
2748 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2751 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2752 IndexModeNone, f, itin,
2753 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2754 let Inst{24-23} = 0b11; // Increment Before
2755 let Inst{22} = P_bit;
2756 let Inst{21} = 0; // No writeback
2757 let Inst{20} = L_bit;
2760 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2761 IndexModeUpd, f, itin_upd,
2762 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2763 let Inst{24-23} = 0b11; // Increment Before
2764 let Inst{22} = P_bit;
2765 let Inst{21} = 1; // Writeback
2766 let Inst{20} = L_bit;
2768 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2772 let neverHasSideEffects = 1 in {
2774 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2775 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2778 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2779 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2782 } // neverHasSideEffects
2784 // FIXME: remove when we have a way to marking a MI with these properties.
2785 // FIXME: Should pc be an implicit operand like PICADD, etc?
2786 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2787 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2788 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2789 reglist:$regs, variable_ops),
2790 4, IIC_iLoad_mBr, [],
2791 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2792 RegConstraint<"$Rn = $wb">;
2794 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2795 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2798 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2799 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2804 //===----------------------------------------------------------------------===//
2805 // Move Instructions.
2808 let neverHasSideEffects = 1 in
2809 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2810 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2814 let Inst{19-16} = 0b0000;
2815 let Inst{11-4} = 0b00000000;
2818 let Inst{15-12} = Rd;
2821 // A version for the smaller set of tail call registers.
2822 let neverHasSideEffects = 1 in
2823 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2824 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2828 let Inst{11-4} = 0b00000000;
2831 let Inst{15-12} = Rd;
2834 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2835 DPSoRegRegFrm, IIC_iMOVsr,
2836 "mov", "\t$Rd, $src",
2837 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2840 let Inst{15-12} = Rd;
2841 let Inst{19-16} = 0b0000;
2842 let Inst{11-8} = src{11-8};
2844 let Inst{6-5} = src{6-5};
2846 let Inst{3-0} = src{3-0};
2850 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2851 DPSoRegImmFrm, IIC_iMOVsr,
2852 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2856 let Inst{15-12} = Rd;
2857 let Inst{19-16} = 0b0000;
2858 let Inst{11-5} = src{11-5};
2860 let Inst{3-0} = src{3-0};
2864 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2865 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2866 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2870 let Inst{15-12} = Rd;
2871 let Inst{19-16} = 0b0000;
2872 let Inst{11-0} = imm;
2875 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2876 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2878 "movw", "\t$Rd, $imm",
2879 [(set GPR:$Rd, imm0_65535:$imm)]>,
2880 Requires<[IsARM, HasV6T2]>, UnaryDP {
2883 let Inst{15-12} = Rd;
2884 let Inst{11-0} = imm{11-0};
2885 let Inst{19-16} = imm{15-12};
2888 let DecoderMethod = "DecodeArmMOVTWInstruction";
2891 def : InstAlias<"mov${p} $Rd, $imm",
2892 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2895 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2896 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2898 let Constraints = "$src = $Rd" in {
2899 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2900 (ins GPR:$src, imm0_65535_expr:$imm),
2902 "movt", "\t$Rd, $imm",
2904 (or (and GPR:$src, 0xffff),
2905 lo16AllZero:$imm))]>, UnaryDP,
2906 Requires<[IsARM, HasV6T2]> {
2909 let Inst{15-12} = Rd;
2910 let Inst{11-0} = imm{11-0};
2911 let Inst{19-16} = imm{15-12};
2914 let DecoderMethod = "DecodeArmMOVTWInstruction";
2917 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2918 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2922 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2923 Requires<[IsARM, HasV6T2]>;
2925 let Uses = [CPSR] in
2926 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2927 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2930 // These aren't really mov instructions, but we have to define them this way
2931 // due to flag operands.
2933 let Defs = [CPSR] in {
2934 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2935 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2937 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2938 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2942 //===----------------------------------------------------------------------===//
2943 // Extend Instructions.
2948 def SXTB : AI_ext_rrot<0b01101010,
2949 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2950 def SXTH : AI_ext_rrot<0b01101011,
2951 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2953 def SXTAB : AI_exta_rrot<0b01101010,
2954 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2955 def SXTAH : AI_exta_rrot<0b01101011,
2956 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2958 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2960 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2964 let AddedComplexity = 16 in {
2965 def UXTB : AI_ext_rrot<0b01101110,
2966 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2967 def UXTH : AI_ext_rrot<0b01101111,
2968 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2969 def UXTB16 : AI_ext_rrot<0b01101100,
2970 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2972 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2973 // The transformation should probably be done as a combiner action
2974 // instead so we can include a check for masking back in the upper
2975 // eight bits of the source into the lower eight bits of the result.
2976 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2977 // (UXTB16r_rot GPR:$Src, 3)>;
2978 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2979 (UXTB16 GPR:$Src, 1)>;
2981 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2982 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2983 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2984 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2987 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2988 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2991 def SBFX : I<(outs GPRnopc:$Rd),
2992 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
2993 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2994 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2995 Requires<[IsARM, HasV6T2]> {
3000 let Inst{27-21} = 0b0111101;
3001 let Inst{6-4} = 0b101;
3002 let Inst{20-16} = width;
3003 let Inst{15-12} = Rd;
3004 let Inst{11-7} = lsb;
3008 def UBFX : I<(outs GPR:$Rd),
3009 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3010 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3011 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3012 Requires<[IsARM, HasV6T2]> {
3017 let Inst{27-21} = 0b0111111;
3018 let Inst{6-4} = 0b101;
3019 let Inst{20-16} = width;
3020 let Inst{15-12} = Rd;
3021 let Inst{11-7} = lsb;
3025 //===----------------------------------------------------------------------===//
3026 // Arithmetic Instructions.
3029 defm ADD : AsI1_bin_irs<0b0100, "add",
3030 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3031 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3032 defm SUB : AsI1_bin_irs<0b0010, "sub",
3033 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3034 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3036 // ADD and SUB with 's' bit set.
3038 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3039 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3040 // AdjustInstrPostInstrSelection where we determine whether or not to
3041 // set the "s" bit based on CPSR liveness.
3043 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3044 // support for an optional CPSR definition that corresponds to the DAG
3045 // node's second value. We can then eliminate the implicit def of CPSR.
3046 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3047 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3048 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3049 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3051 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3052 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3053 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3054 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3056 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3057 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3058 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3060 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3061 // CPSR and the implicit def of CPSR is not needed.
3062 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3063 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3065 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3066 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3068 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3069 // The assume-no-carry-in form uses the negation of the input since add/sub
3070 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3071 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3073 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3074 (SUBri GPR:$src, so_imm_neg:$imm)>;
3075 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3076 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3078 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3079 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3080 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3081 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3083 // The with-carry-in form matches bitwise not instead of the negation.
3084 // Effectively, the inverse interpretation of the carry flag already accounts
3085 // for part of the negation.
3086 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3087 (SBCri GPR:$src, so_imm_not:$imm)>;
3089 // Note: These are implemented in C++ code, because they have to generate
3090 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3092 // (mul X, 2^n+1) -> (add (X << n), X)
3093 // (mul X, 2^n-1) -> (rsb X, (X << n))
3095 // ARM Arithmetic Instruction
3096 // GPR:$dst = GPR:$a op GPR:$b
3097 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3098 list<dag> pattern = [],
3099 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3100 string asm = "\t$Rd, $Rn, $Rm">
3101 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3105 let Inst{27-20} = op27_20;
3106 let Inst{11-4} = op11_4;
3107 let Inst{19-16} = Rn;
3108 let Inst{15-12} = Rd;
3111 let Unpredictable{11-8} = 0b1111;
3114 // Saturating add/subtract
3116 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3117 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3118 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3119 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3120 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3121 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3122 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3123 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3125 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3126 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3129 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3130 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3131 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3132 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3133 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3134 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3135 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3136 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3137 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3138 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3139 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3140 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3142 // Signed/Unsigned add/subtract
3144 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3145 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3146 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3147 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3148 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3149 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3150 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3151 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3152 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3153 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3154 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3155 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3157 // Signed/Unsigned halving add/subtract
3159 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3160 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3161 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3162 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3163 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3164 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3165 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3166 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3167 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3168 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3169 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3170 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3172 // Unsigned Sum of Absolute Differences [and Accumulate].
3174 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3175 MulFrm /* for convenience */, NoItinerary, "usad8",
3176 "\t$Rd, $Rn, $Rm", []>,
3177 Requires<[IsARM, HasV6]> {
3181 let Inst{27-20} = 0b01111000;
3182 let Inst{15-12} = 0b1111;
3183 let Inst{7-4} = 0b0001;
3184 let Inst{19-16} = Rd;
3185 let Inst{11-8} = Rm;
3188 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3189 MulFrm /* for convenience */, NoItinerary, "usada8",
3190 "\t$Rd, $Rn, $Rm, $Ra", []>,
3191 Requires<[IsARM, HasV6]> {
3196 let Inst{27-20} = 0b01111000;
3197 let Inst{7-4} = 0b0001;
3198 let Inst{19-16} = Rd;
3199 let Inst{15-12} = Ra;
3200 let Inst{11-8} = Rm;
3204 // Signed/Unsigned saturate
3206 def SSAT : AI<(outs GPRnopc:$Rd),
3207 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3208 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3213 let Inst{27-21} = 0b0110101;
3214 let Inst{5-4} = 0b01;
3215 let Inst{20-16} = sat_imm;
3216 let Inst{15-12} = Rd;
3217 let Inst{11-7} = sh{4-0};
3218 let Inst{6} = sh{5};
3222 def SSAT16 : AI<(outs GPRnopc:$Rd),
3223 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3224 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3228 let Inst{27-20} = 0b01101010;
3229 let Inst{11-4} = 0b11110011;
3230 let Inst{15-12} = Rd;
3231 let Inst{19-16} = sat_imm;
3235 def USAT : AI<(outs GPRnopc:$Rd),
3236 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3237 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3242 let Inst{27-21} = 0b0110111;
3243 let Inst{5-4} = 0b01;
3244 let Inst{15-12} = Rd;
3245 let Inst{11-7} = sh{4-0};
3246 let Inst{6} = sh{5};
3247 let Inst{20-16} = sat_imm;
3251 def USAT16 : AI<(outs GPRnopc:$Rd),
3252 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3253 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3257 let Inst{27-20} = 0b01101110;
3258 let Inst{11-4} = 0b11110011;
3259 let Inst{15-12} = Rd;
3260 let Inst{19-16} = sat_imm;
3264 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3265 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3266 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3267 (USAT imm:$pos, GPRnopc:$a, 0)>;
3269 //===----------------------------------------------------------------------===//
3270 // Bitwise Instructions.
3273 defm AND : AsI1_bin_irs<0b0000, "and",
3274 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3275 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3276 defm ORR : AsI1_bin_irs<0b1100, "orr",
3277 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3278 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3279 defm EOR : AsI1_bin_irs<0b0001, "eor",
3280 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3281 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3282 defm BIC : AsI1_bin_irs<0b1110, "bic",
3283 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3284 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3286 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3287 // like in the actual instruction encoding. The complexity of mapping the mask
3288 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3289 // instruction description.
3290 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3291 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3292 "bfc", "\t$Rd, $imm", "$src = $Rd",
3293 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3294 Requires<[IsARM, HasV6T2]> {
3297 let Inst{27-21} = 0b0111110;
3298 let Inst{6-0} = 0b0011111;
3299 let Inst{15-12} = Rd;
3300 let Inst{11-7} = imm{4-0}; // lsb
3301 let Inst{20-16} = imm{9-5}; // msb
3304 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3305 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3306 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3307 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3308 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3309 bf_inv_mask_imm:$imm))]>,
3310 Requires<[IsARM, HasV6T2]> {
3314 let Inst{27-21} = 0b0111110;
3315 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3316 let Inst{15-12} = Rd;
3317 let Inst{11-7} = imm{4-0}; // lsb
3318 let Inst{20-16} = imm{9-5}; // width
3322 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3323 "mvn", "\t$Rd, $Rm",
3324 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3328 let Inst{19-16} = 0b0000;
3329 let Inst{11-4} = 0b00000000;
3330 let Inst{15-12} = Rd;
3333 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3334 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3335 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3339 let Inst{19-16} = 0b0000;
3340 let Inst{15-12} = Rd;
3341 let Inst{11-5} = shift{11-5};
3343 let Inst{3-0} = shift{3-0};
3345 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3346 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3347 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3351 let Inst{19-16} = 0b0000;
3352 let Inst{15-12} = Rd;
3353 let Inst{11-8} = shift{11-8};
3355 let Inst{6-5} = shift{6-5};
3357 let Inst{3-0} = shift{3-0};
3359 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3360 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3361 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3362 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3366 let Inst{19-16} = 0b0000;
3367 let Inst{15-12} = Rd;
3368 let Inst{11-0} = imm;
3371 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3372 (BICri GPR:$src, so_imm_not:$imm)>;
3374 //===----------------------------------------------------------------------===//
3375 // Multiply Instructions.
3377 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3378 string opc, string asm, list<dag> pattern>
3379 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3383 let Inst{19-16} = Rd;
3384 let Inst{11-8} = Rm;
3387 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3388 string opc, string asm, list<dag> pattern>
3389 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3394 let Inst{19-16} = RdHi;
3395 let Inst{15-12} = RdLo;
3396 let Inst{11-8} = Rm;
3400 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3401 // property. Remove them when it's possible to add those properties
3402 // on an individual MachineInstr, not just an instruction description.
3403 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3404 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3405 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3406 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3407 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3408 Requires<[IsARM, HasV6]> {
3409 let Inst{15-12} = 0b0000;
3410 let Unpredictable{15-12} = 0b1111;
3413 let Constraints = "@earlyclobber $Rd" in
3414 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3415 pred:$p, cc_out:$s),
3417 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3418 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3419 Requires<[IsARM, NoV6]>;
3422 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3423 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3424 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3425 Requires<[IsARM, HasV6]> {
3427 let Inst{15-12} = Ra;
3430 let Constraints = "@earlyclobber $Rd" in
3431 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3432 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3434 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3435 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3436 Requires<[IsARM, NoV6]>;
3438 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3439 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3440 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3441 Requires<[IsARM, HasV6T2]> {
3446 let Inst{19-16} = Rd;
3447 let Inst{15-12} = Ra;
3448 let Inst{11-8} = Rm;
3452 // Extra precision multiplies with low / high results
3453 let neverHasSideEffects = 1 in {
3454 let isCommutable = 1 in {
3455 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3456 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3457 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3458 Requires<[IsARM, HasV6]>;
3460 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3461 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3462 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3463 Requires<[IsARM, HasV6]>;
3465 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3466 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3467 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3469 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3470 Requires<[IsARM, NoV6]>;
3472 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3473 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3475 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3476 Requires<[IsARM, NoV6]>;
3480 // Multiply + accumulate
3481 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3482 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3483 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3484 Requires<[IsARM, HasV6]>;
3485 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3486 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3487 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3488 Requires<[IsARM, HasV6]>;
3490 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3491 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3492 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3493 Requires<[IsARM, HasV6]> {
3498 let Inst{19-16} = RdHi;
3499 let Inst{15-12} = RdLo;
3500 let Inst{11-8} = Rm;
3504 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3505 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3506 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3508 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3509 Requires<[IsARM, NoV6]>;
3510 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3511 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3513 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3514 Requires<[IsARM, NoV6]>;
3515 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3516 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3518 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3519 Requires<[IsARM, NoV6]>;
3522 } // neverHasSideEffects
3524 // Most significant word multiply
3525 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3526 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3527 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3528 Requires<[IsARM, HasV6]> {
3529 let Inst{15-12} = 0b1111;
3532 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3533 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3534 Requires<[IsARM, HasV6]> {
3535 let Inst{15-12} = 0b1111;
3538 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3539 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3540 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3541 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3542 Requires<[IsARM, HasV6]>;
3544 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3545 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3546 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3547 Requires<[IsARM, HasV6]>;
3549 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3550 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3551 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3552 Requires<[IsARM, HasV6]>;
3554 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3555 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3556 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3557 Requires<[IsARM, HasV6]>;
3559 multiclass AI_smul<string opc, PatFrag opnode> {
3560 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3561 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3562 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3563 (sext_inreg GPR:$Rm, i16)))]>,
3564 Requires<[IsARM, HasV5TE]>;
3566 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3567 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3568 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3569 (sra GPR:$Rm, (i32 16))))]>,
3570 Requires<[IsARM, HasV5TE]>;
3572 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3573 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3574 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3575 (sext_inreg GPR:$Rm, i16)))]>,
3576 Requires<[IsARM, HasV5TE]>;
3578 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3579 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3580 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3581 (sra GPR:$Rm, (i32 16))))]>,
3582 Requires<[IsARM, HasV5TE]>;
3584 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3585 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3586 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3587 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3588 Requires<[IsARM, HasV5TE]>;
3590 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3591 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3592 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3593 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3594 Requires<[IsARM, HasV5TE]>;
3598 multiclass AI_smla<string opc, PatFrag opnode> {
3599 let DecoderMethod = "DecodeSMLAInstruction" in {
3600 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3601 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3602 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3603 [(set GPRnopc:$Rd, (add GPR:$Ra,
3604 (opnode (sext_inreg GPRnopc:$Rn, i16),
3605 (sext_inreg GPRnopc:$Rm, i16))))]>,
3606 Requires<[IsARM, HasV5TE]>;
3608 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3609 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3610 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3612 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3613 (sra GPRnopc:$Rm, (i32 16)))))]>,
3614 Requires<[IsARM, HasV5TE]>;
3616 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3617 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3618 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3620 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3621 (sext_inreg GPRnopc:$Rm, i16))))]>,
3622 Requires<[IsARM, HasV5TE]>;
3624 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3625 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3626 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3628 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3629 (sra GPRnopc:$Rm, (i32 16)))))]>,
3630 Requires<[IsARM, HasV5TE]>;
3632 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3633 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3634 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3636 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3637 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3638 Requires<[IsARM, HasV5TE]>;
3640 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3641 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3642 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3644 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3645 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3646 Requires<[IsARM, HasV5TE]>;
3650 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3651 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3653 // Halfword multiply accumulate long: SMLAL<x><y>.
3654 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3655 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3656 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3657 Requires<[IsARM, HasV5TE]>;
3659 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3660 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3661 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3662 Requires<[IsARM, HasV5TE]>;
3664 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3665 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3666 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3667 Requires<[IsARM, HasV5TE]>;
3669 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3670 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3671 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3672 Requires<[IsARM, HasV5TE]>;
3674 // Helper class for AI_smld.
3675 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3676 InstrItinClass itin, string opc, string asm>
3677 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3680 let Inst{27-23} = 0b01110;
3681 let Inst{22} = long;
3682 let Inst{21-20} = 0b00;
3683 let Inst{11-8} = Rm;
3690 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3691 InstrItinClass itin, string opc, string asm>
3692 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3694 let Inst{15-12} = 0b1111;
3695 let Inst{19-16} = Rd;
3697 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3698 InstrItinClass itin, string opc, string asm>
3699 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3702 let Inst{19-16} = Rd;
3703 let Inst{15-12} = Ra;
3705 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3706 InstrItinClass itin, string opc, string asm>
3707 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3710 let Inst{19-16} = RdHi;
3711 let Inst{15-12} = RdLo;
3714 multiclass AI_smld<bit sub, string opc> {
3716 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3717 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3718 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3720 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3721 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3722 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3724 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3725 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3726 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3728 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3729 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3730 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3734 defm SMLA : AI_smld<0, "smla">;
3735 defm SMLS : AI_smld<1, "smls">;
3737 multiclass AI_sdml<bit sub, string opc> {
3739 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3740 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3741 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3742 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3745 defm SMUA : AI_sdml<0, "smua">;
3746 defm SMUS : AI_sdml<1, "smus">;
3748 //===----------------------------------------------------------------------===//
3749 // Misc. Arithmetic Instructions.
3752 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3753 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3754 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3756 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3757 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3758 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3759 Requires<[IsARM, HasV6T2]>;
3761 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3762 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3763 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3765 let AddedComplexity = 5 in
3766 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3767 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3768 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3769 Requires<[IsARM, HasV6]>;
3771 let AddedComplexity = 5 in
3772 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3773 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3774 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3775 Requires<[IsARM, HasV6]>;
3777 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3778 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3781 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3782 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3783 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3784 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3785 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3787 Requires<[IsARM, HasV6]>;
3789 // Alternate cases for PKHBT where identities eliminate some nodes.
3790 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3791 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3792 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3793 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3795 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3796 // will match the pattern below.
3797 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3798 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3799 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3800 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3801 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3803 Requires<[IsARM, HasV6]>;
3805 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3806 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3807 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3808 (srl GPRnopc:$src2, imm16_31:$sh)),
3809 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3810 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3811 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3812 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3814 //===----------------------------------------------------------------------===//
3815 // Comparison Instructions...
3818 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3819 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3820 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3822 // ARMcmpZ can re-use the above instruction definitions.
3823 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3824 (CMPri GPR:$src, so_imm:$imm)>;
3825 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3826 (CMPrr GPR:$src, GPR:$rhs)>;
3827 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3828 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3829 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3830 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3832 // CMN register-integer
3833 let isCompare = 1, Defs = [CPSR] in {
3834 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3835 "cmn", "\t$Rn, $imm",
3836 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3841 let Inst{19-16} = Rn;
3842 let Inst{15-12} = 0b0000;
3843 let Inst{11-0} = imm;
3845 let Unpredictable{15-12} = 0b1111;
3848 // CMN register-register/shift
3849 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3850 "cmn", "\t$Rn, $Rm",
3851 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3852 GPR:$Rn, GPR:$Rm)]> {
3855 let isCommutable = 1;
3858 let Inst{19-16} = Rn;
3859 let Inst{15-12} = 0b0000;
3860 let Inst{11-4} = 0b00000000;
3863 let Unpredictable{15-12} = 0b1111;
3866 def CMNzrsi : AI1<0b1011, (outs),
3867 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3868 "cmn", "\t$Rn, $shift",
3869 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3870 GPR:$Rn, so_reg_imm:$shift)]> {
3875 let Inst{19-16} = Rn;
3876 let Inst{15-12} = 0b0000;
3877 let Inst{11-5} = shift{11-5};
3879 let Inst{3-0} = shift{3-0};
3881 let Unpredictable{15-12} = 0b1111;
3884 def CMNzrsr : AI1<0b1011, (outs),
3885 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3886 "cmn", "\t$Rn, $shift",
3887 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3888 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3893 let Inst{19-16} = Rn;
3894 let Inst{15-12} = 0b0000;
3895 let Inst{11-8} = shift{11-8};
3897 let Inst{6-5} = shift{6-5};
3899 let Inst{3-0} = shift{3-0};
3901 let Unpredictable{15-12} = 0b1111;
3906 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3907 (CMNri GPR:$src, so_imm_neg:$imm)>;
3909 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3910 (CMNri GPR:$src, so_imm_neg:$imm)>;
3912 // Note that TST/TEQ don't set all the same flags that CMP does!
3913 defm TST : AI1_cmp_irs<0b1000, "tst",
3914 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3915 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3916 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3917 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3918 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3920 // Pseudo i64 compares for some floating point compares.
3921 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3923 def BCCi64 : PseudoInst<(outs),
3924 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3926 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3928 def BCCZi64 : PseudoInst<(outs),
3929 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3930 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3931 } // usesCustomInserter
3934 // Conditional moves
3935 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3936 // a two-value operand where a dag node expects two operands. :(
3937 let neverHasSideEffects = 1 in {
3939 let isCommutable = 1 in
3940 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3942 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3943 RegConstraint<"$false = $Rd">;
3945 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3946 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3948 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3949 imm:$cc, CCR:$ccr))*/]>,
3950 RegConstraint<"$false = $Rd">;
3951 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3952 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3954 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3955 imm:$cc, CCR:$ccr))*/]>,
3956 RegConstraint<"$false = $Rd">;
3959 let isMoveImm = 1 in
3960 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3961 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3964 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3966 let isMoveImm = 1 in
3967 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3968 (ins GPR:$false, so_imm:$imm, pred:$p),
3970 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3971 RegConstraint<"$false = $Rd">;
3973 // Two instruction predicate mov immediate.
3974 let isMoveImm = 1 in
3975 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3976 (ins GPR:$false, i32imm:$src, pred:$p),
3977 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3979 let isMoveImm = 1 in
3980 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3981 (ins GPR:$false, so_imm:$imm, pred:$p),
3983 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3984 RegConstraint<"$false = $Rd">;
3986 // Conditional instructions
3987 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3989 InstrItinClass iii, InstrItinClass iir,
3990 InstrItinClass iis> {
3991 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3992 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
3994 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
3995 RegConstraint<"$Rn = $Rd">;
3996 def rr : ARMPseudoExpand<(outs GPR:$Rd),
3997 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3999 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4000 RegConstraint<"$Rn = $Rd">;
4001 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4002 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
4004 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4005 RegConstraint<"$Rn = $Rd">;
4006 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4007 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
4009 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4010 RegConstraint<"$Rn = $Rd">;
4013 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4014 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4015 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4016 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4017 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4018 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4020 } // neverHasSideEffects
4023 //===----------------------------------------------------------------------===//
4024 // Atomic operations intrinsics
4027 def MemBarrierOptOperand : AsmOperandClass {
4028 let Name = "MemBarrierOpt";
4029 let ParserMethod = "parseMemBarrierOptOperand";
4031 def memb_opt : Operand<i32> {
4032 let PrintMethod = "printMemBOption";
4033 let ParserMatchClass = MemBarrierOptOperand;
4034 let DecoderMethod = "DecodeMemBarrierOption";
4037 // memory barriers protect the atomic sequences
4038 let hasSideEffects = 1 in {
4039 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4040 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4041 Requires<[IsARM, HasDB]> {
4043 let Inst{31-4} = 0xf57ff05;
4044 let Inst{3-0} = opt;
4048 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4049 "dsb", "\t$opt", []>,
4050 Requires<[IsARM, HasDB]> {
4052 let Inst{31-4} = 0xf57ff04;
4053 let Inst{3-0} = opt;
4056 // ISB has only full system option
4057 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4058 "isb", "\t$opt", []>,
4059 Requires<[IsARM, HasDB]> {
4061 let Inst{31-4} = 0xf57ff06;
4062 let Inst{3-0} = opt;
4065 // Pseudo instruction that combines movs + predicated rsbmi
4066 // to implement integer ABS
4067 let usesCustomInserter = 1, Defs = [CPSR] in
4068 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4070 let usesCustomInserter = 1 in {
4071 let Defs = [CPSR] in {
4072 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4073 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4074 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4075 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4076 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4077 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4078 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4079 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4080 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4081 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4082 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4083 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4084 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4085 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4086 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4087 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4088 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4089 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4090 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4091 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4092 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4093 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4094 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4095 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4096 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4098 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4099 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4100 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4101 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4102 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4103 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4104 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4105 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4106 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4107 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4108 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4110 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4111 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4113 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4114 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4116 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4117 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4119 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4120 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4122 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4123 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4125 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4126 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4129 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4132 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4135 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4138 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4141 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4147 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4150 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4156 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4159 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4163 def ATOMIC_SWAP_I8 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4165 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4166 def ATOMIC_SWAP_I16 : PseudoInst<
4167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4168 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4169 def ATOMIC_SWAP_I32 : PseudoInst<
4170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4171 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4173 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4175 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4176 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4178 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4179 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4181 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4185 let usesCustomInserter = 1 in {
4186 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4187 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4189 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4192 let mayLoad = 1 in {
4193 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4195 "ldrexb", "\t$Rt, $addr", []>;
4196 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4197 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4198 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4199 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4200 let hasExtraDefRegAllocReq = 1 in
4201 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4202 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4203 let DecoderMethod = "DecodeDoubleRegLoad";
4207 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4208 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4209 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4210 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4211 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4212 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4213 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4214 let hasExtraSrcRegAllocReq = 1 in
4215 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4216 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4217 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4218 let DecoderMethod = "DecodeDoubleRegStore";
4223 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4224 Requires<[IsARM, HasV7]> {
4225 let Inst{31-0} = 0b11110101011111111111000000011111;
4228 // SWP/SWPB are deprecated in V6/V7.
4229 let mayLoad = 1, mayStore = 1 in {
4230 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4231 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4232 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4233 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4236 //===----------------------------------------------------------------------===//
4237 // Coprocessor Instructions.
4240 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4241 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4242 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4243 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4244 imm:$CRm, imm:$opc2)]> {
4252 let Inst{3-0} = CRm;
4254 let Inst{7-5} = opc2;
4255 let Inst{11-8} = cop;
4256 let Inst{15-12} = CRd;
4257 let Inst{19-16} = CRn;
4258 let Inst{23-20} = opc1;
4261 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4262 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4263 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4264 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4265 imm:$CRm, imm:$opc2)]> {
4266 let Inst{31-28} = 0b1111;
4274 let Inst{3-0} = CRm;
4276 let Inst{7-5} = opc2;
4277 let Inst{11-8} = cop;
4278 let Inst{15-12} = CRd;
4279 let Inst{19-16} = CRn;
4280 let Inst{23-20} = opc1;
4283 class ACI<dag oops, dag iops, string opc, string asm,
4284 IndexMode im = IndexModeNone>
4285 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4287 let Inst{27-25} = 0b110;
4289 class ACInoP<dag oops, dag iops, string opc, string asm,
4290 IndexMode im = IndexModeNone>
4291 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4293 let Inst{31-28} = 0b1111;
4294 let Inst{27-25} = 0b110;
4296 multiclass LdStCop<bit load, bit Dbit, string asm> {
4297 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4298 asm, "\t$cop, $CRd, $addr"> {
4302 let Inst{24} = 1; // P = 1
4303 let Inst{23} = addr{8};
4304 let Inst{22} = Dbit;
4305 let Inst{21} = 0; // W = 0
4306 let Inst{20} = load;
4307 let Inst{19-16} = addr{12-9};
4308 let Inst{15-12} = CRd;
4309 let Inst{11-8} = cop;
4310 let Inst{7-0} = addr{7-0};
4311 let DecoderMethod = "DecodeCopMemInstruction";
4313 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4314 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4318 let Inst{24} = 1; // P = 1
4319 let Inst{23} = addr{8};
4320 let Inst{22} = Dbit;
4321 let Inst{21} = 1; // W = 1
4322 let Inst{20} = load;
4323 let Inst{19-16} = addr{12-9};
4324 let Inst{15-12} = CRd;
4325 let Inst{11-8} = cop;
4326 let Inst{7-0} = addr{7-0};
4327 let DecoderMethod = "DecodeCopMemInstruction";
4329 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4330 postidx_imm8s4:$offset),
4331 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4336 let Inst{24} = 0; // P = 0
4337 let Inst{23} = offset{8};
4338 let Inst{22} = Dbit;
4339 let Inst{21} = 1; // W = 1
4340 let Inst{20} = load;
4341 let Inst{19-16} = addr;
4342 let Inst{15-12} = CRd;
4343 let Inst{11-8} = cop;
4344 let Inst{7-0} = offset{7-0};
4345 let DecoderMethod = "DecodeCopMemInstruction";
4347 def _OPTION : ACI<(outs),
4348 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4349 coproc_option_imm:$option),
4350 asm, "\t$cop, $CRd, $addr, $option"> {
4355 let Inst{24} = 0; // P = 0
4356 let Inst{23} = 1; // U = 1
4357 let Inst{22} = Dbit;
4358 let Inst{21} = 0; // W = 0
4359 let Inst{20} = load;
4360 let Inst{19-16} = addr;
4361 let Inst{15-12} = CRd;
4362 let Inst{11-8} = cop;
4363 let Inst{7-0} = option;
4364 let DecoderMethod = "DecodeCopMemInstruction";
4367 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4368 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4369 asm, "\t$cop, $CRd, $addr"> {
4373 let Inst{24} = 1; // P = 1
4374 let Inst{23} = addr{8};
4375 let Inst{22} = Dbit;
4376 let Inst{21} = 0; // W = 0
4377 let Inst{20} = load;
4378 let Inst{19-16} = addr{12-9};
4379 let Inst{15-12} = CRd;
4380 let Inst{11-8} = cop;
4381 let Inst{7-0} = addr{7-0};
4382 let DecoderMethod = "DecodeCopMemInstruction";
4384 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4385 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4389 let Inst{24} = 1; // P = 1
4390 let Inst{23} = addr{8};
4391 let Inst{22} = Dbit;
4392 let Inst{21} = 1; // W = 1
4393 let Inst{20} = load;
4394 let Inst{19-16} = addr{12-9};
4395 let Inst{15-12} = CRd;
4396 let Inst{11-8} = cop;
4397 let Inst{7-0} = addr{7-0};
4398 let DecoderMethod = "DecodeCopMemInstruction";
4400 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4401 postidx_imm8s4:$offset),
4402 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4407 let Inst{24} = 0; // P = 0
4408 let Inst{23} = offset{8};
4409 let Inst{22} = Dbit;
4410 let Inst{21} = 1; // W = 1
4411 let Inst{20} = load;
4412 let Inst{19-16} = addr;
4413 let Inst{15-12} = CRd;
4414 let Inst{11-8} = cop;
4415 let Inst{7-0} = offset{7-0};
4416 let DecoderMethod = "DecodeCopMemInstruction";
4418 def _OPTION : ACInoP<(outs),
4419 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4420 coproc_option_imm:$option),
4421 asm, "\t$cop, $CRd, $addr, $option"> {
4426 let Inst{24} = 0; // P = 0
4427 let Inst{23} = 1; // U = 1
4428 let Inst{22} = Dbit;
4429 let Inst{21} = 0; // W = 0
4430 let Inst{20} = load;
4431 let Inst{19-16} = addr;
4432 let Inst{15-12} = CRd;
4433 let Inst{11-8} = cop;
4434 let Inst{7-0} = option;
4435 let DecoderMethod = "DecodeCopMemInstruction";
4439 defm LDC : LdStCop <1, 0, "ldc">;
4440 defm LDCL : LdStCop <1, 1, "ldcl">;
4441 defm STC : LdStCop <0, 0, "stc">;
4442 defm STCL : LdStCop <0, 1, "stcl">;
4443 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4444 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4445 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4446 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4448 //===----------------------------------------------------------------------===//
4449 // Move between coprocessor and ARM core register.
4452 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4454 : ABI<0b1110, oops, iops, NoItinerary, opc,
4455 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4456 let Inst{20} = direction;
4466 let Inst{15-12} = Rt;
4467 let Inst{11-8} = cop;
4468 let Inst{23-21} = opc1;
4469 let Inst{7-5} = opc2;
4470 let Inst{3-0} = CRm;
4471 let Inst{19-16} = CRn;
4474 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4476 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4477 c_imm:$CRm, imm0_7:$opc2),
4478 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4479 imm:$CRm, imm:$opc2)]>;
4480 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4481 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4482 c_imm:$CRm, 0, pred:$p)>;
4483 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4485 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4487 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4488 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4489 c_imm:$CRm, 0, pred:$p)>;
4491 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4492 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4494 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4496 : ABXI<0b1110, oops, iops, NoItinerary,
4497 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4498 let Inst{31-28} = 0b1111;
4499 let Inst{20} = direction;
4509 let Inst{15-12} = Rt;
4510 let Inst{11-8} = cop;
4511 let Inst{23-21} = opc1;
4512 let Inst{7-5} = opc2;
4513 let Inst{3-0} = CRm;
4514 let Inst{19-16} = CRn;
4517 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4519 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4520 c_imm:$CRm, imm0_7:$opc2),
4521 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4522 imm:$CRm, imm:$opc2)]>;
4523 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4524 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4526 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4528 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4530 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4531 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4534 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4535 imm:$CRm, imm:$opc2),
4536 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4538 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4539 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4540 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4541 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4542 let Inst{23-21} = 0b010;
4543 let Inst{20} = direction;
4551 let Inst{15-12} = Rt;
4552 let Inst{19-16} = Rt2;
4553 let Inst{11-8} = cop;
4554 let Inst{7-4} = opc1;
4555 let Inst{3-0} = CRm;
4558 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4559 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4560 GPRnopc:$Rt2, imm:$CRm)]>;
4561 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4563 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4564 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4565 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4566 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4567 let Inst{31-28} = 0b1111;
4568 let Inst{23-21} = 0b010;
4569 let Inst{20} = direction;
4577 let Inst{15-12} = Rt;
4578 let Inst{19-16} = Rt2;
4579 let Inst{11-8} = cop;
4580 let Inst{7-4} = opc1;
4581 let Inst{3-0} = CRm;
4583 let DecoderMethod = "DecodeMRRC2";
4586 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4587 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4588 GPRnopc:$Rt2, imm:$CRm)]>;
4589 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4591 //===----------------------------------------------------------------------===//
4592 // Move between special register and ARM core register
4595 // Move to ARM core register from Special Register
4596 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4597 "mrs", "\t$Rd, apsr", []> {
4599 let Inst{23-16} = 0b00001111;
4600 let Unpredictable{19-17} = 0b111;
4602 let Inst{15-12} = Rd;
4604 let Inst{11-0} = 0b000000000000;
4605 let Unpredictable{11-0} = 0b110100001111;
4608 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4611 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4612 // section B9.3.9, with the R bit set to 1.
4613 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4614 "mrs", "\t$Rd, spsr", []> {
4616 let Inst{23-16} = 0b01001111;
4617 let Unpredictable{19-16} = 0b1111;
4619 let Inst{15-12} = Rd;
4621 let Inst{11-0} = 0b000000000000;
4622 let Unpredictable{11-0} = 0b110100001111;
4625 // Move from ARM core register to Special Register
4627 // No need to have both system and application versions, the encodings are the
4628 // same and the assembly parser has no way to distinguish between them. The mask
4629 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4630 // the mask with the fields to be accessed in the special register.
4631 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4632 "msr", "\t$mask, $Rn", []> {
4637 let Inst{22} = mask{4}; // R bit
4638 let Inst{21-20} = 0b10;
4639 let Inst{19-16} = mask{3-0};
4640 let Inst{15-12} = 0b1111;
4641 let Inst{11-4} = 0b00000000;
4645 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4646 "msr", "\t$mask, $a", []> {
4651 let Inst{22} = mask{4}; // R bit
4652 let Inst{21-20} = 0b10;
4653 let Inst{19-16} = mask{3-0};
4654 let Inst{15-12} = 0b1111;
4658 //===----------------------------------------------------------------------===//
4662 // __aeabi_read_tp preserves the registers r1-r3.
4663 // This is a pseudo inst so that we can get the encoding right,
4664 // complete with fixup for the aeabi_read_tp function.
4666 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4667 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4668 [(set R0, ARMthread_pointer)]>;
4671 //===----------------------------------------------------------------------===//
4672 // SJLJ Exception handling intrinsics
4673 // eh_sjlj_setjmp() is an instruction sequence to store the return
4674 // address and save #0 in R0 for the non-longjmp case.
4675 // Since by its nature we may be coming from some other function to get
4676 // here, and we're using the stack frame for the containing function to
4677 // save/restore registers, we can't keep anything live in regs across
4678 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4679 // when we get here from a longjmp(). We force everything out of registers
4680 // except for our own input by listing the relevant registers in Defs. By
4681 // doing so, we also cause the prologue/epilogue code to actively preserve
4682 // all of the callee-saved resgisters, which is exactly what we want.
4683 // A constant value is passed in $val, and we use the location as a scratch.
4685 // These are pseudo-instructions and are lowered to individual MC-insts, so
4686 // no encoding information is necessary.
4688 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4689 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4690 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4691 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4693 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4694 Requires<[IsARM, HasVFP2]>;
4698 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4699 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4700 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4702 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4703 Requires<[IsARM, NoVFP]>;
4706 // FIXME: Non-IOS version(s)
4707 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4708 Defs = [ R7, LR, SP ] in {
4709 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4711 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4712 Requires<[IsARM, IsIOS]>;
4715 // eh.sjlj.dispatchsetup pseudo-instructions.
4716 // These pseudos are used for both ARM and Thumb2. Any differences are
4717 // handled when the pseudo is expanded (which happens before any passes
4718 // that need the instruction size).
4720 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4721 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4723 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4726 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4728 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4731 //===----------------------------------------------------------------------===//
4732 // Non-Instruction Patterns
4735 // ARMv4 indirect branch using (MOVr PC, dst)
4736 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4737 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4738 4, IIC_Br, [(brind GPR:$dst)],
4739 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4740 Requires<[IsARM, NoV4T]>;
4742 // Large immediate handling.
4744 // 32-bit immediate using two piece so_imms or movw + movt.
4745 // This is a single pseudo instruction, the benefit is that it can be remat'd
4746 // as a single unit instead of having to handle reg inputs.
4747 // FIXME: Remove this when we can do generalized remat.
4748 let isReMaterializable = 1, isMoveImm = 1 in
4749 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4750 [(set GPR:$dst, (arm_i32imm:$src))]>,
4753 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4754 // It also makes it possible to rematerialize the instructions.
4755 // FIXME: Remove this when we can do generalized remat and when machine licm
4756 // can properly the instructions.
4757 let isReMaterializable = 1 in {
4758 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4760 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4761 Requires<[IsARM, UseMovt]>;
4763 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4765 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4766 Requires<[IsARM, UseMovt]>;
4768 let AddedComplexity = 10 in
4769 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4771 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4772 Requires<[IsARM, UseMovt]>;
4773 } // isReMaterializable
4775 // ConstantPool, GlobalAddress, and JumpTable
4776 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4777 Requires<[IsARM, DontUseMovt]>;
4778 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4779 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4780 Requires<[IsARM, UseMovt]>;
4781 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4782 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4784 // TODO: add,sub,and, 3-instr forms?
4786 // Tail calls. These patterns also apply to Thumb mode.
4787 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4788 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4789 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4792 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4793 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4794 (BMOVPCB_CALL texternalsym:$func)>;
4796 // zextload i1 -> zextload i8
4797 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4798 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4800 // extload -> zextload
4801 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4802 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4803 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4804 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4806 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4808 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4809 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4812 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4813 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4814 (SMULBB GPR:$a, GPR:$b)>;
4815 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4816 (SMULBB GPR:$a, GPR:$b)>;
4817 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4818 (sra GPR:$b, (i32 16))),
4819 (SMULBT GPR:$a, GPR:$b)>;
4820 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4821 (SMULBT GPR:$a, GPR:$b)>;
4822 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4823 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4824 (SMULTB GPR:$a, GPR:$b)>;
4825 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4826 (SMULTB GPR:$a, GPR:$b)>;
4827 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4829 (SMULWB GPR:$a, GPR:$b)>;
4830 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4831 (SMULWB GPR:$a, GPR:$b)>;
4833 def : ARMV5TEPat<(add GPR:$acc,
4834 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4835 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4836 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4837 def : ARMV5TEPat<(add GPR:$acc,
4838 (mul sext_16_node:$a, sext_16_node:$b)),
4839 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4840 def : ARMV5TEPat<(add GPR:$acc,
4841 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4842 (sra GPR:$b, (i32 16)))),
4843 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4844 def : ARMV5TEPat<(add GPR:$acc,
4845 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4846 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4847 def : ARMV5TEPat<(add GPR:$acc,
4848 (mul (sra GPR:$a, (i32 16)),
4849 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4850 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4851 def : ARMV5TEPat<(add GPR:$acc,
4852 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4853 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4854 def : ARMV5TEPat<(add GPR:$acc,
4855 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4857 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4858 def : ARMV5TEPat<(add GPR:$acc,
4859 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4860 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4863 // Pre-v7 uses MCR for synchronization barriers.
4864 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4865 Requires<[IsARM, HasV6]>;
4867 // SXT/UXT with no rotate
4868 let AddedComplexity = 16 in {
4869 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4870 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4871 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4872 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4873 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4874 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4875 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4878 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4879 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4881 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4882 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4883 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4884 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4886 // Atomic load/store patterns
4887 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4888 (LDRBrs ldst_so_reg:$src)>;
4889 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4890 (LDRBi12 addrmode_imm12:$src)>;
4891 def : ARMPat<(atomic_load_16 addrmode3:$src),
4892 (LDRH addrmode3:$src)>;
4893 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4894 (LDRrs ldst_so_reg:$src)>;
4895 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4896 (LDRi12 addrmode_imm12:$src)>;
4897 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4898 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4899 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4900 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4901 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4902 (STRH GPR:$val, addrmode3:$ptr)>;
4903 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4904 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4905 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4906 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4909 //===----------------------------------------------------------------------===//
4913 include "ARMInstrThumb.td"
4915 //===----------------------------------------------------------------------===//
4919 include "ARMInstrThumb2.td"
4921 //===----------------------------------------------------------------------===//
4922 // Floating Point Support
4925 include "ARMInstrVFP.td"
4927 //===----------------------------------------------------------------------===//
4928 // Advanced SIMD (NEON) Support
4931 include "ARMInstrNEON.td"
4933 //===----------------------------------------------------------------------===//
4934 // Assembler aliases
4938 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4939 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4940 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4942 // System instructions
4943 def : MnemonicAlias<"swi", "svc">;
4945 // Load / Store Multiple
4946 def : MnemonicAlias<"ldmfd", "ldm">;
4947 def : MnemonicAlias<"ldmia", "ldm">;
4948 def : MnemonicAlias<"ldmea", "ldmdb">;
4949 def : MnemonicAlias<"stmfd", "stmdb">;
4950 def : MnemonicAlias<"stmia", "stm">;
4951 def : MnemonicAlias<"stmea", "stm">;
4953 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4954 // shift amount is zero (i.e., unspecified).
4955 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4956 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4957 Requires<[IsARM, HasV6]>;
4958 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4959 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4960 Requires<[IsARM, HasV6]>;
4962 // PUSH/POP aliases for STM/LDM
4963 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4964 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4966 // SSAT/USAT optional shift operand.
4967 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4968 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4969 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4970 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4973 // Extend instruction optional rotate operand.
4974 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4975 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4976 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4977 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4978 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4979 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4980 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4981 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4982 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4983 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4984 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4985 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4987 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4988 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4989 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4990 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4991 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4992 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4993 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4994 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4995 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4996 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4997 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4998 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5002 def : MnemonicAlias<"rfefa", "rfeda">;
5003 def : MnemonicAlias<"rfeea", "rfedb">;
5004 def : MnemonicAlias<"rfefd", "rfeia">;
5005 def : MnemonicAlias<"rfeed", "rfeib">;
5006 def : MnemonicAlias<"rfe", "rfeia">;
5009 def : MnemonicAlias<"srsfa", "srsda">;
5010 def : MnemonicAlias<"srsea", "srsdb">;
5011 def : MnemonicAlias<"srsfd", "srsia">;
5012 def : MnemonicAlias<"srsed", "srsib">;
5013 def : MnemonicAlias<"srs", "srsia">;
5016 def : MnemonicAlias<"qsubaddx", "qsax">;
5018 def : MnemonicAlias<"saddsubx", "sasx">;
5019 // SHASX == SHADDSUBX
5020 def : MnemonicAlias<"shaddsubx", "shasx">;
5021 // SHSAX == SHSUBADDX
5022 def : MnemonicAlias<"shsubaddx", "shsax">;
5024 def : MnemonicAlias<"ssubaddx", "ssax">;
5026 def : MnemonicAlias<"uaddsubx", "uasx">;
5027 // UHASX == UHADDSUBX
5028 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5029 // UHSAX == UHSUBADDX
5030 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5031 // UQASX == UQADDSUBX
5032 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5033 // UQSAX == UQSUBADDX
5034 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5036 def : MnemonicAlias<"usubaddx", "usax">;
5038 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5040 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5041 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5042 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5043 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5044 // Same for AND <--> BIC
5045 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5046 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5047 pred:$p, cc_out:$s)>;
5048 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5049 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5050 pred:$p, cc_out:$s)>;
5051 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5052 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5053 pred:$p, cc_out:$s)>;
5054 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5055 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5056 pred:$p, cc_out:$s)>;
5058 // Likewise, "add Rd, so_imm_neg" -> sub
5059 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5060 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5061 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5062 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5063 // Same for CMP <--> CMN via so_imm_neg
5064 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5065 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5066 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5067 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5069 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5070 // LSR, ROR, and RRX instructions.
5071 // FIXME: We need C++ parser hooks to map the alias to the MOV
5072 // encoding. It seems we should be able to do that sort of thing
5073 // in tblgen, but it could get ugly.
5074 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5075 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5076 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5078 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5079 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5081 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5082 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5084 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5085 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5088 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5089 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5090 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5091 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5092 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5094 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5095 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5097 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5098 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5100 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5101 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5105 // "neg" is and alias for "rsb rd, rn, #0"
5106 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5107 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5109 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5110 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5111 Requires<[IsARM, NoV6]>;
5113 // UMULL/SMULL are available on all arches, but the instruction definitions
5114 // need difference constraints pre-v6. Use these aliases for the assembly
5115 // parsing on pre-v6.
5116 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5117 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5118 Requires<[IsARM, NoV6]>;
5119 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5120 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5121 Requires<[IsARM, NoV6]>;
5123 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5125 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;