1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
32 //register plus/minus 12 bit offset
33 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
34 //register plus scaled register
35 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
42 let Namespace = "ARM";
44 dag OperandList = ops;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 def brtarget : Operand<OtherVT>;
51 // Operand for printing out a condition code.
52 let PrintMethod = "printCCOperand" in
53 def CCOp : Operand<i32>;
55 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
56 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
57 [SDNPHasChain, SDNPOutFlag]>;
58 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
59 [SDNPHasChain, SDNPOutFlag]>;
61 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
62 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
65 [SDNPHasChain, SDNPOptInFlag]>;
67 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
68 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
70 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
71 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
73 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
74 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
76 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
77 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
79 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
80 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
81 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
82 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
83 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
84 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
85 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
86 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
88 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
89 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
90 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
92 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
93 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
95 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
96 "!ADJCALLSTACKUP $amt",
97 [(callseq_end imm:$amt)]>;
99 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
100 "!ADJCALLSTACKDOWN $amt",
101 [(callseq_start imm:$amt)]>;
103 let isReturn = 1 in {
104 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
107 let Defs = [R0, R1, R2, R3, R14] in {
108 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
111 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
113 [(set IntRegs:$dst, (load iaddr:$addr))]>;
115 def str : InstARM<(ops IntRegs:$src, memri:$addr),
117 [(store IntRegs:$src, iaddr:$addr)]>;
119 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
120 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
122 def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
124 [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
126 def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
128 [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
130 def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
132 [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
134 // "LEA" forms of add
135 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
136 "add $dst, ${addr:arith}",
137 [(set IntRegs:$dst, iaddr:$addr)]>;
140 def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
142 [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
144 def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
146 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
148 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
150 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
152 def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
154 [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
156 let isTwoAddress = 1 in {
157 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
158 op_addr_mode1:$true, CCOp:$cc),
159 "mov$cc $dst, $true",
160 [(set IntRegs:$dst, (armselect addr_mode1:$true,
161 IntRegs:$false, imm:$cc))]>;
164 def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
166 [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
168 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
170 [(armbr bb:$dst, imm:$cc)]>;
172 def b : InstARM<(ops brtarget:$dst),
176 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
178 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
180 // Floating Point Compare
181 def fcmpes : InstARM<(ops FPRegs:$a, FPRegs:$b),
183 [(armcmp FPRegs:$a, FPRegs:$b)]>;
185 def fcmped : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
187 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
189 // Floating Point Conversion
190 // We use bitconvert for moving the data between the register classes.
191 // The format conversion is done with ARM specific nodes
193 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
194 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
196 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
197 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
199 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
200 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
202 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
203 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
205 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
206 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
208 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
209 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
211 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
212 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
214 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
215 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
217 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
218 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
220 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
221 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
223 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
224 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
226 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
227 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
229 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
230 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
232 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
233 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
235 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
237 // Floating Point Arithmetic
238 def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
239 "fadds $dst, $a, $b",
240 [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
242 def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
243 "faddd $dst, $a, $b",
244 [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
246 def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
247 "fsubs $dst, $a, $b",
248 [(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
250 def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
251 "fsubd $dst, $a, $b",
252 [(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>;
254 def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
255 "fmuls $dst, $a, $b",
256 [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
258 def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
259 "fmuld $dst, $a, $b",
260 [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
263 // Floating Point Load
264 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
266 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
268 def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
270 [(set DFPRegs:$dst, (load IntRegs:$addr))]>;