1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps", "armv4t">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps", "armv5te">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops", "armv6">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops", "armv7">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2", "VFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3", "VFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4", "VFP4">;
184 def HasNEON : Predicate<"Subtarget->hasNEON()">,
185 AssemblerPredicate<"FeatureNEON", "NEON">;
186 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
187 AssemblerPredicate<"FeatureFP16","half-float">;
188 def HasDivide : Predicate<"Subtarget->hasDivide()">,
189 AssemblerPredicate<"FeatureHWDiv", "divide">;
190 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
191 AssemblerPredicate<"FeatureT2XtPk",
193 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
194 AssemblerPredicate<"FeatureDSPThumb2",
196 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
197 AssemblerPredicate<"FeatureDB",
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP",
202 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
203 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
204 def IsThumb : Predicate<"Subtarget->isThumb()">,
205 AssemblerPredicate<"ModeThumb", "thumb">;
206 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
207 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
208 AssemblerPredicate<"ModeThumb,FeatureThumb2",
210 def IsMClass : Predicate<"Subtarget->isMClass()">,
211 AssemblerPredicate<"FeatureMClass", "armv7m">;
212 def IsARClass : Predicate<"!Subtarget->isMClass()">,
213 AssemblerPredicate<"!FeatureMClass",
215 def IsARM : Predicate<"!Subtarget->isThumb()">,
216 AssemblerPredicate<"!ModeThumb", "arm-mode">;
217 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
218 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
219 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
221 // FIXME: Eventually this will be just "hasV6T2Ops".
222 def UseMovt : Predicate<"Subtarget->useMovt()">;
223 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
224 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
226 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
227 // But only select them if more precision in FP computation is allowed.
228 // Do not use them for Darwin platforms.
229 def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision && "
230 "!Subtarget->isTargetDarwin()">;
231 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
232 "Subtarget->isTargetDarwin()">;
234 //===----------------------------------------------------------------------===//
235 // ARM Flag Definitions.
237 class RegConstraint<string C> {
238 string Constraints = C;
241 //===----------------------------------------------------------------------===//
242 // ARM specific transformation functions and pattern fragments.
245 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
246 // so_imm_neg def below.
247 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
248 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
251 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
252 // so_imm_not def below.
253 def so_imm_not_XFORM : SDNodeXForm<imm, [{
254 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
257 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
258 def imm16_31 : ImmLeaf<i32, [{
259 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
262 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
263 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
264 int64_t Value = -(int)N->getZExtValue();
265 return Value && ARM_AM::getSOImmVal(Value) != -1;
266 }], so_imm_neg_XFORM> {
267 let ParserMatchClass = so_imm_neg_asmoperand;
270 // Note: this pattern doesn't require an encoder method and such, as it's
271 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
272 // is handled by the destination instructions, which use so_imm.
273 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
274 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
275 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
276 }], so_imm_not_XFORM> {
277 let ParserMatchClass = so_imm_not_asmoperand;
280 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
281 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
282 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
285 /// Split a 32-bit immediate into two 16 bit parts.
286 def hi16 : SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
290 def lo16AllZero : PatLeaf<(i32 imm), [{
291 // Returns true if all low 16-bits are 0.
292 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
295 class BinOpWithFlagFrag<dag res> :
296 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
297 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
298 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
300 // An 'and' node with a single use.
301 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
302 return N->hasOneUse();
305 // An 'xor' node with a single use.
306 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
307 return N->hasOneUse();
310 // An 'fmul' node with a single use.
311 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
312 return N->hasOneUse();
315 // An 'fadd' node which checks for single non-hazardous use.
316 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
317 return hasNoVMLxHazardUse(N);
320 // An 'fsub' node which checks for single non-hazardous use.
321 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
322 return hasNoVMLxHazardUse(N);
325 //===----------------------------------------------------------------------===//
326 // Operand Definitions.
329 // Immediate operands with a shared generic asm render method.
330 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
333 // FIXME: rename brtarget to t2_brtarget
334 def brtarget : Operand<OtherVT> {
335 let EncoderMethod = "getBranchTargetOpValue";
336 let OperandType = "OPERAND_PCREL";
337 let DecoderMethod = "DecodeT2BROperand";
340 // FIXME: get rid of this one?
341 def uncondbrtarget : Operand<OtherVT> {
342 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
346 // Branch target for ARM. Handles conditional/unconditional
347 def br_target : Operand<OtherVT> {
348 let EncoderMethod = "getARMBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
353 // FIXME: rename bltarget to t2_bl_target?
354 def bltarget : Operand<i32> {
355 // Encoded the same as branch targets.
356 let EncoderMethod = "getBranchTargetOpValue";
357 let OperandType = "OPERAND_PCREL";
360 // Call target for ARM. Handles conditional/unconditional
361 // FIXME: rename bl_target to t2_bltarget?
362 def bl_target : Operand<i32> {
363 let EncoderMethod = "getARMBLTargetOpValue";
364 let OperandType = "OPERAND_PCREL";
367 def blx_target : Operand<i32> {
368 let EncoderMethod = "getARMBLXTargetOpValue";
369 let OperandType = "OPERAND_PCREL";
372 // A list of registers separated by comma. Used by load/store multiple.
373 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
374 def reglist : Operand<i32> {
375 let EncoderMethod = "getRegisterListOpValue";
376 let ParserMatchClass = RegListAsmOperand;
377 let PrintMethod = "printRegisterList";
378 let DecoderMethod = "DecodeRegListOperand";
381 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
382 def dpr_reglist : Operand<i32> {
383 let EncoderMethod = "getRegisterListOpValue";
384 let ParserMatchClass = DPRRegListAsmOperand;
385 let PrintMethod = "printRegisterList";
386 let DecoderMethod = "DecodeDPRRegListOperand";
389 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
390 def spr_reglist : Operand<i32> {
391 let EncoderMethod = "getRegisterListOpValue";
392 let ParserMatchClass = SPRRegListAsmOperand;
393 let PrintMethod = "printRegisterList";
394 let DecoderMethod = "DecodeSPRRegListOperand";
397 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
398 def cpinst_operand : Operand<i32> {
399 let PrintMethod = "printCPInstOperand";
403 def pclabel : Operand<i32> {
404 let PrintMethod = "printPCLabel";
407 // ADR instruction labels.
408 def adrlabel : Operand<i32> {
409 let EncoderMethod = "getAdrLabelOpValue";
412 def neon_vcvt_imm32 : Operand<i32> {
413 let EncoderMethod = "getNEONVcvtImm32OpValue";
414 let DecoderMethod = "DecodeVCVTImmOperand";
417 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
418 def rot_imm_XFORM: SDNodeXForm<imm, [{
419 switch (N->getZExtValue()){
421 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
422 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
423 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
424 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
427 def RotImmAsmOperand : AsmOperandClass {
429 let ParserMethod = "parseRotImm";
431 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
432 int32_t v = N->getZExtValue();
433 return v == 8 || v == 16 || v == 24; }],
435 let PrintMethod = "printRotImmOperand";
436 let ParserMatchClass = RotImmAsmOperand;
439 // shift_imm: An integer that encodes a shift amount and the type of shift
440 // (asr or lsl). The 6-bit immediate encodes as:
443 // {4-0} imm5 shift amount.
444 // asr #32 encoded as imm5 == 0.
445 def ShifterImmAsmOperand : AsmOperandClass {
446 let Name = "ShifterImm";
447 let ParserMethod = "parseShifterImm";
449 def shift_imm : Operand<i32> {
450 let PrintMethod = "printShiftImmOperand";
451 let ParserMatchClass = ShifterImmAsmOperand;
454 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
455 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
456 def so_reg_reg : Operand<i32>, // reg reg imm
457 ComplexPattern<i32, 3, "SelectRegShifterOperand",
458 [shl, srl, sra, rotr]> {
459 let EncoderMethod = "getSORegRegOpValue";
460 let PrintMethod = "printSORegRegOperand";
461 let DecoderMethod = "DecodeSORegRegOperand";
462 let ParserMatchClass = ShiftedRegAsmOperand;
463 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
466 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
467 def so_reg_imm : Operand<i32>, // reg imm
468 ComplexPattern<i32, 2, "SelectImmShifterOperand",
469 [shl, srl, sra, rotr]> {
470 let EncoderMethod = "getSORegImmOpValue";
471 let PrintMethod = "printSORegImmOperand";
472 let DecoderMethod = "DecodeSORegImmOperand";
473 let ParserMatchClass = ShiftedImmAsmOperand;
474 let MIOperandInfo = (ops GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_reg : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegRegOpValue";
482 let PrintMethod = "printSORegRegOperand";
483 let DecoderMethod = "DecodeSORegRegOperand";
484 let ParserMatchClass = ShiftedRegAsmOperand;
485 let MIOperandInfo = (ops GPR, GPR, i32imm);
488 // FIXME: Does this need to be distinct from so_reg?
489 def shift_so_reg_imm : Operand<i32>, // reg reg imm
490 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
491 [shl,srl,sra,rotr]> {
492 let EncoderMethod = "getSORegImmOpValue";
493 let PrintMethod = "printSORegImmOperand";
494 let DecoderMethod = "DecodeSORegImmOperand";
495 let ParserMatchClass = ShiftedImmAsmOperand;
496 let MIOperandInfo = (ops GPR, i32imm);
500 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
501 // 8-bit immediate rotated by an arbitrary number of bits.
502 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
503 def so_imm : Operand<i32>, ImmLeaf<i32, [{
504 return ARM_AM::getSOImmVal(Imm) != -1;
506 let EncoderMethod = "getSOImmOpValue";
507 let ParserMatchClass = SOImmAsmOperand;
508 let DecoderMethod = "DecodeSOImmOperand";
511 // Break so_imm's up into two pieces. This handles immediates with up to 16
512 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
513 // get the first/second pieces.
514 def so_imm2part : PatLeaf<(imm), [{
515 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
518 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
520 def arm_i32imm : PatLeaf<(imm), [{
521 if (Subtarget->hasV6T2Ops())
523 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
526 /// imm0_1 predicate - Immediate in the range [0,1].
527 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
528 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
530 /// imm0_3 predicate - Immediate in the range [0,3].
531 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
532 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
534 /// imm0_7 predicate - Immediate in the range [0,7].
535 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
536 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
537 return Imm >= 0 && Imm < 8;
539 let ParserMatchClass = Imm0_7AsmOperand;
542 /// imm8 predicate - Immediate is exactly 8.
543 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
544 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
545 let ParserMatchClass = Imm8AsmOperand;
548 /// imm16 predicate - Immediate is exactly 16.
549 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
550 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
551 let ParserMatchClass = Imm16AsmOperand;
554 /// imm32 predicate - Immediate is exactly 32.
555 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
556 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
557 let ParserMatchClass = Imm32AsmOperand;
560 /// imm1_7 predicate - Immediate in the range [1,7].
561 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
562 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
563 let ParserMatchClass = Imm1_7AsmOperand;
566 /// imm1_15 predicate - Immediate in the range [1,15].
567 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
568 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
569 let ParserMatchClass = Imm1_15AsmOperand;
572 /// imm1_31 predicate - Immediate in the range [1,31].
573 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
574 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
575 let ParserMatchClass = Imm1_31AsmOperand;
578 /// imm0_15 predicate - Immediate in the range [0,15].
579 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
580 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
581 return Imm >= 0 && Imm < 16;
583 let ParserMatchClass = Imm0_15AsmOperand;
586 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
587 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
588 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
589 return Imm >= 0 && Imm < 32;
591 let ParserMatchClass = Imm0_31AsmOperand;
594 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
595 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
596 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
597 return Imm >= 0 && Imm < 32;
599 let ParserMatchClass = Imm0_32AsmOperand;
602 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
603 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
604 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
605 return Imm >= 0 && Imm < 64;
607 let ParserMatchClass = Imm0_63AsmOperand;
610 /// imm0_255 predicate - Immediate in the range [0,255].
611 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
612 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
613 let ParserMatchClass = Imm0_255AsmOperand;
616 /// imm0_65535 - An immediate is in the range [0.65535].
617 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
618 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
619 return Imm >= 0 && Imm < 65536;
621 let ParserMatchClass = Imm0_65535AsmOperand;
624 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
625 // a relocatable expression.
627 // FIXME: This really needs a Thumb version separate from the ARM version.
628 // While the range is the same, and can thus use the same match class,
629 // the encoding is different so it should have a different encoder method.
630 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
631 def imm0_65535_expr : Operand<i32> {
632 let EncoderMethod = "getHiLo16ImmOpValue";
633 let ParserMatchClass = Imm0_65535ExprAsmOperand;
636 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
637 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
638 def imm24b : Operand<i32>, ImmLeaf<i32, [{
639 return Imm >= 0 && Imm <= 0xffffff;
641 let ParserMatchClass = Imm24bitAsmOperand;
645 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
647 def BitfieldAsmOperand : AsmOperandClass {
648 let Name = "Bitfield";
649 let ParserMethod = "parseBitfield";
652 def bf_inv_mask_imm : Operand<i32>,
654 return ARM::isBitFieldInvertedMask(N->getZExtValue());
656 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
657 let PrintMethod = "printBitfieldInvMaskImmOperand";
658 let DecoderMethod = "DecodeBitfieldMaskOperand";
659 let ParserMatchClass = BitfieldAsmOperand;
662 def imm1_32_XFORM: SDNodeXForm<imm, [{
663 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
665 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
666 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
667 uint64_t Imm = N->getZExtValue();
668 return Imm > 0 && Imm <= 32;
671 let PrintMethod = "printImmPlusOneOperand";
672 let ParserMatchClass = Imm1_32AsmOperand;
675 def imm1_16_XFORM: SDNodeXForm<imm, [{
676 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
678 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
679 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
681 let PrintMethod = "printImmPlusOneOperand";
682 let ParserMatchClass = Imm1_16AsmOperand;
685 // Define ARM specific addressing modes.
686 // addrmode_imm12 := reg +/- imm12
688 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
689 def addrmode_imm12 : Operand<i32>,
690 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
691 // 12-bit immediate operand. Note that instructions using this encode
692 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
693 // immediate values are as normal.
695 let EncoderMethod = "getAddrModeImm12OpValue";
696 let PrintMethod = "printAddrModeImm12Operand";
697 let DecoderMethod = "DecodeAddrModeImm12Operand";
698 let ParserMatchClass = MemImm12OffsetAsmOperand;
699 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
701 // ldst_so_reg := reg +/- reg shop imm
703 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
704 def ldst_so_reg : Operand<i32>,
705 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
706 let EncoderMethod = "getLdStSORegOpValue";
707 // FIXME: Simplify the printer
708 let PrintMethod = "printAddrMode2Operand";
709 let DecoderMethod = "DecodeSORegMemOperand";
710 let ParserMatchClass = MemRegOffsetAsmOperand;
711 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
714 // postidx_imm8 := +/- [0,255]
717 // {8} 1 is imm8 is non-negative. 0 otherwise.
718 // {7-0} [0,255] imm8 value.
719 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
720 def postidx_imm8 : Operand<i32> {
721 let PrintMethod = "printPostIdxImm8Operand";
722 let ParserMatchClass = PostIdxImm8AsmOperand;
723 let MIOperandInfo = (ops i32imm);
726 // postidx_imm8s4 := +/- [0,1020]
729 // {8} 1 is imm8 is non-negative. 0 otherwise.
730 // {7-0} [0,255] imm8 value, scaled by 4.
731 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
732 def postidx_imm8s4 : Operand<i32> {
733 let PrintMethod = "printPostIdxImm8s4Operand";
734 let ParserMatchClass = PostIdxImm8s4AsmOperand;
735 let MIOperandInfo = (ops i32imm);
739 // postidx_reg := +/- reg
741 def PostIdxRegAsmOperand : AsmOperandClass {
742 let Name = "PostIdxReg";
743 let ParserMethod = "parsePostIdxReg";
745 def postidx_reg : Operand<i32> {
746 let EncoderMethod = "getPostIdxRegOpValue";
747 let DecoderMethod = "DecodePostIdxReg";
748 let PrintMethod = "printPostIdxRegOperand";
749 let ParserMatchClass = PostIdxRegAsmOperand;
750 let MIOperandInfo = (ops GPRnopc, i32imm);
754 // addrmode2 := reg +/- imm12
755 // := reg +/- reg shop imm
757 // FIXME: addrmode2 should be refactored the rest of the way to always
758 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
759 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
760 def addrmode2 : Operand<i32>,
761 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
762 let EncoderMethod = "getAddrMode2OpValue";
763 let PrintMethod = "printAddrMode2Operand";
764 let ParserMatchClass = AddrMode2AsmOperand;
765 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
768 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
769 let Name = "PostIdxRegShifted";
770 let ParserMethod = "parsePostIdxReg";
772 def am2offset_reg : Operand<i32>,
773 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
774 [], [SDNPWantRoot]> {
775 let EncoderMethod = "getAddrMode2OffsetOpValue";
776 let PrintMethod = "printAddrMode2OffsetOperand";
777 // When using this for assembly, it's always as a post-index offset.
778 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
779 let MIOperandInfo = (ops GPRnopc, i32imm);
782 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
783 // the GPR is purely vestigal at this point.
784 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
785 def am2offset_imm : Operand<i32>,
786 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
787 [], [SDNPWantRoot]> {
788 let EncoderMethod = "getAddrMode2OffsetOpValue";
789 let PrintMethod = "printAddrMode2OffsetOperand";
790 let ParserMatchClass = AM2OffsetImmAsmOperand;
791 let MIOperandInfo = (ops GPRnopc, i32imm);
795 // addrmode3 := reg +/- reg
796 // addrmode3 := reg +/- imm8
798 // FIXME: split into imm vs. reg versions.
799 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
800 def addrmode3 : Operand<i32>,
801 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
802 let EncoderMethod = "getAddrMode3OpValue";
803 let PrintMethod = "printAddrMode3Operand";
804 let ParserMatchClass = AddrMode3AsmOperand;
805 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
808 // FIXME: split into imm vs. reg versions.
809 // FIXME: parser method to handle +/- register.
810 def AM3OffsetAsmOperand : AsmOperandClass {
811 let Name = "AM3Offset";
812 let ParserMethod = "parseAM3Offset";
814 def am3offset : Operand<i32>,
815 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
816 [], [SDNPWantRoot]> {
817 let EncoderMethod = "getAddrMode3OffsetOpValue";
818 let PrintMethod = "printAddrMode3OffsetOperand";
819 let ParserMatchClass = AM3OffsetAsmOperand;
820 let MIOperandInfo = (ops GPR, i32imm);
823 // ldstm_mode := {ia, ib, da, db}
825 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
826 let EncoderMethod = "getLdStmModeOpValue";
827 let PrintMethod = "printLdStmModeOperand";
830 // addrmode5 := reg +/- imm8*4
832 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
833 def addrmode5 : Operand<i32>,
834 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
835 let PrintMethod = "printAddrMode5Operand";
836 let EncoderMethod = "getAddrMode5OpValue";
837 let DecoderMethod = "DecodeAddrMode5Operand";
838 let ParserMatchClass = AddrMode5AsmOperand;
839 let MIOperandInfo = (ops GPR:$base, i32imm);
842 // addrmode6 := reg with optional alignment
844 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
845 def addrmode6 : Operand<i32>,
846 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
847 let PrintMethod = "printAddrMode6Operand";
848 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
849 let EncoderMethod = "getAddrMode6AddressOpValue";
850 let DecoderMethod = "DecodeAddrMode6Operand";
851 let ParserMatchClass = AddrMode6AsmOperand;
854 def am6offset : Operand<i32>,
855 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
856 [], [SDNPWantRoot]> {
857 let PrintMethod = "printAddrMode6OffsetOperand";
858 let MIOperandInfo = (ops GPR);
859 let EncoderMethod = "getAddrMode6OffsetOpValue";
860 let DecoderMethod = "DecodeGPRRegisterClass";
863 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
864 // (single element from one lane) for size 32.
865 def addrmode6oneL32 : Operand<i32>,
866 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
867 let PrintMethod = "printAddrMode6Operand";
868 let MIOperandInfo = (ops GPR:$addr, i32imm);
869 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
872 // Special version of addrmode6 to handle alignment encoding for VLD-dup
873 // instructions, specifically VLD4-dup.
874 def addrmode6dup : Operand<i32>,
875 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
876 let PrintMethod = "printAddrMode6Operand";
877 let MIOperandInfo = (ops GPR:$addr, i32imm);
878 let EncoderMethod = "getAddrMode6DupAddressOpValue";
879 // FIXME: This is close, but not quite right. The alignment specifier is
881 let ParserMatchClass = AddrMode6AsmOperand;
884 // addrmodepc := pc + reg
886 def addrmodepc : Operand<i32>,
887 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
888 let PrintMethod = "printAddrModePCOperand";
889 let MIOperandInfo = (ops GPR, i32imm);
892 // addr_offset_none := reg
894 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
895 def addr_offset_none : Operand<i32>,
896 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
897 let PrintMethod = "printAddrMode7Operand";
898 let DecoderMethod = "DecodeAddrMode7Operand";
899 let ParserMatchClass = MemNoOffsetAsmOperand;
900 let MIOperandInfo = (ops GPR:$base);
903 def nohash_imm : Operand<i32> {
904 let PrintMethod = "printNoHashImmediate";
907 def CoprocNumAsmOperand : AsmOperandClass {
908 let Name = "CoprocNum";
909 let ParserMethod = "parseCoprocNumOperand";
911 def p_imm : Operand<i32> {
912 let PrintMethod = "printPImmediate";
913 let ParserMatchClass = CoprocNumAsmOperand;
914 let DecoderMethod = "DecodeCoprocessor";
917 def pf_imm : Operand<i32> {
918 let PrintMethod = "printPImmediate";
919 let ParserMatchClass = CoprocNumAsmOperand;
922 def CoprocRegAsmOperand : AsmOperandClass {
923 let Name = "CoprocReg";
924 let ParserMethod = "parseCoprocRegOperand";
926 def c_imm : Operand<i32> {
927 let PrintMethod = "printCImmediate";
928 let ParserMatchClass = CoprocRegAsmOperand;
930 def CoprocOptionAsmOperand : AsmOperandClass {
931 let Name = "CoprocOption";
932 let ParserMethod = "parseCoprocOptionOperand";
934 def coproc_option_imm : Operand<i32> {
935 let PrintMethod = "printCoprocOptionImm";
936 let ParserMatchClass = CoprocOptionAsmOperand;
939 //===----------------------------------------------------------------------===//
941 include "ARMInstrFormats.td"
943 //===----------------------------------------------------------------------===//
944 // Multiclass helpers...
947 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
948 /// binop that produces a value.
949 let TwoOperandAliasConstraint = "$Rn = $Rd" in
950 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
951 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
952 PatFrag opnode, string baseOpc, bit Commutable = 0> {
953 // The register-immediate version is re-materializable. This is useful
954 // in particular for taking the address of a local.
955 let isReMaterializable = 1 in {
956 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
957 iii, opc, "\t$Rd, $Rn, $imm",
958 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
963 let Inst{19-16} = Rn;
964 let Inst{15-12} = Rd;
965 let Inst{11-0} = imm;
968 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
969 iir, opc, "\t$Rd, $Rn, $Rm",
970 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
975 let isCommutable = Commutable;
976 let Inst{19-16} = Rn;
977 let Inst{15-12} = Rd;
978 let Inst{11-4} = 0b00000000;
982 def rsi : AsI1<opcod, (outs GPR:$Rd),
983 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
984 iis, opc, "\t$Rd, $Rn, $shift",
985 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
990 let Inst{19-16} = Rn;
991 let Inst{15-12} = Rd;
992 let Inst{11-5} = shift{11-5};
994 let Inst{3-0} = shift{3-0};
997 def rsr : AsI1<opcod, (outs GPR:$Rd),
998 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
999 iis, opc, "\t$Rd, $Rn, $shift",
1000 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1005 let Inst{19-16} = Rn;
1006 let Inst{15-12} = Rd;
1007 let Inst{11-8} = shift{11-8};
1009 let Inst{6-5} = shift{6-5};
1011 let Inst{3-0} = shift{3-0};
1015 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1016 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1017 /// it is equivalent to the AsI1_bin_irs counterpart.
1018 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1019 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1020 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1021 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1022 // The register-immediate version is re-materializable. This is useful
1023 // in particular for taking the address of a local.
1024 let isReMaterializable = 1 in {
1025 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1026 iii, opc, "\t$Rd, $Rn, $imm",
1027 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1032 let Inst{19-16} = Rn;
1033 let Inst{15-12} = Rd;
1034 let Inst{11-0} = imm;
1037 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1038 iir, opc, "\t$Rd, $Rn, $Rm",
1039 [/* pattern left blank */]> {
1043 let Inst{11-4} = 0b00000000;
1046 let Inst{15-12} = Rd;
1047 let Inst{19-16} = Rn;
1050 def rsi : AsI1<opcod, (outs GPR:$Rd),
1051 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1052 iis, opc, "\t$Rd, $Rn, $shift",
1053 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1058 let Inst{19-16} = Rn;
1059 let Inst{15-12} = Rd;
1060 let Inst{11-5} = shift{11-5};
1062 let Inst{3-0} = shift{3-0};
1065 def rsr : AsI1<opcod, (outs GPR:$Rd),
1066 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1067 iis, opc, "\t$Rd, $Rn, $shift",
1068 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1073 let Inst{19-16} = Rn;
1074 let Inst{15-12} = Rd;
1075 let Inst{11-8} = shift{11-8};
1077 let Inst{6-5} = shift{6-5};
1079 let Inst{3-0} = shift{3-0};
1083 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1085 /// These opcodes will be converted to the real non-S opcodes by
1086 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1087 let hasPostISelHook = 1, Defs = [CPSR] in {
1088 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1089 InstrItinClass iis, PatFrag opnode,
1090 bit Commutable = 0> {
1091 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1093 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1095 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1097 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1098 let isCommutable = Commutable;
1100 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1101 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1103 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1104 so_reg_imm:$shift))]>;
1106 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1107 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1109 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1110 so_reg_reg:$shift))]>;
1114 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1115 /// operands are reversed.
1116 let hasPostISelHook = 1, Defs = [CPSR] in {
1117 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1118 InstrItinClass iis, PatFrag opnode,
1119 bit Commutable = 0> {
1120 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1124 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1125 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1127 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1130 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1131 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1133 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1138 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1139 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1140 /// a explicit result, only implicitly set CPSR.
1141 let isCompare = 1, Defs = [CPSR] in {
1142 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1143 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1144 PatFrag opnode, bit Commutable = 0> {
1145 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1147 [(opnode GPR:$Rn, so_imm:$imm)]> {
1152 let Inst{19-16} = Rn;
1153 let Inst{15-12} = 0b0000;
1154 let Inst{11-0} = imm;
1156 let Unpredictable{15-12} = 0b1111;
1158 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1160 [(opnode GPR:$Rn, GPR:$Rm)]> {
1163 let isCommutable = Commutable;
1166 let Inst{19-16} = Rn;
1167 let Inst{15-12} = 0b0000;
1168 let Inst{11-4} = 0b00000000;
1171 let Unpredictable{15-12} = 0b1111;
1173 def rsi : AI1<opcod, (outs),
1174 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1175 opc, "\t$Rn, $shift",
1176 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1181 let Inst{19-16} = Rn;
1182 let Inst{15-12} = 0b0000;
1183 let Inst{11-5} = shift{11-5};
1185 let Inst{3-0} = shift{3-0};
1187 let Unpredictable{15-12} = 0b1111;
1189 def rsr : AI1<opcod, (outs),
1190 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1191 opc, "\t$Rn, $shift",
1192 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1197 let Inst{19-16} = Rn;
1198 let Inst{15-12} = 0b0000;
1199 let Inst{11-8} = shift{11-8};
1201 let Inst{6-5} = shift{6-5};
1203 let Inst{3-0} = shift{3-0};
1205 let Unpredictable{15-12} = 0b1111;
1211 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1212 /// register and one whose operand is a register rotated by 8/16/24.
1213 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1214 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1215 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1216 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1217 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1218 Requires<[IsARM, HasV6]> {
1222 let Inst{19-16} = 0b1111;
1223 let Inst{15-12} = Rd;
1224 let Inst{11-10} = rot;
1228 class AI_ext_rrot_np<bits<8> opcod, string opc>
1229 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1230 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1231 Requires<[IsARM, HasV6]> {
1233 let Inst{19-16} = 0b1111;
1234 let Inst{11-10} = rot;
1237 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1238 /// register and one whose operand is a register rotated by 8/16/24.
1239 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1240 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1241 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1242 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1243 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1244 Requires<[IsARM, HasV6]> {
1249 let Inst{19-16} = Rn;
1250 let Inst{15-12} = Rd;
1251 let Inst{11-10} = rot;
1252 let Inst{9-4} = 0b000111;
1256 class AI_exta_rrot_np<bits<8> opcod, string opc>
1257 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1258 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1259 Requires<[IsARM, HasV6]> {
1262 let Inst{19-16} = Rn;
1263 let Inst{11-10} = rot;
1266 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1267 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1268 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1269 string baseOpc, bit Commutable = 0> {
1270 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1271 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1272 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1273 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1279 let Inst{15-12} = Rd;
1280 let Inst{19-16} = Rn;
1281 let Inst{11-0} = imm;
1283 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1284 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1285 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1290 let Inst{11-4} = 0b00000000;
1292 let isCommutable = Commutable;
1294 let Inst{15-12} = Rd;
1295 let Inst{19-16} = Rn;
1297 def rsi : AsI1<opcod, (outs GPR:$Rd),
1298 (ins GPR:$Rn, so_reg_imm:$shift),
1299 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1300 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1306 let Inst{19-16} = Rn;
1307 let Inst{15-12} = Rd;
1308 let Inst{11-5} = shift{11-5};
1310 let Inst{3-0} = shift{3-0};
1312 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1313 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1314 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1315 [(set GPRnopc:$Rd, CPSR,
1316 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = Rd;
1324 let Inst{11-8} = shift{11-8};
1326 let Inst{6-5} = shift{6-5};
1328 let Inst{3-0} = shift{3-0};
1333 /// AI1_rsc_irs - Define instructions and patterns for rsc
1334 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1335 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1337 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1338 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1339 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1340 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1346 let Inst{15-12} = Rd;
1347 let Inst{19-16} = Rn;
1348 let Inst{11-0} = imm;
1350 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1351 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1352 [/* pattern left blank */]> {
1356 let Inst{11-4} = 0b00000000;
1359 let Inst{15-12} = Rd;
1360 let Inst{19-16} = Rn;
1362 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1363 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1364 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1370 let Inst{19-16} = Rn;
1371 let Inst{15-12} = Rd;
1372 let Inst{11-5} = shift{11-5};
1374 let Inst{3-0} = shift{3-0};
1376 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1377 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1378 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1384 let Inst{19-16} = Rn;
1385 let Inst{15-12} = Rd;
1386 let Inst{11-8} = shift{11-8};
1388 let Inst{6-5} = shift{6-5};
1390 let Inst{3-0} = shift{3-0};
1395 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1396 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1397 InstrItinClass iir, PatFrag opnode> {
1398 // Note: We use the complex addrmode_imm12 rather than just an input
1399 // GPR and a constrained immediate so that we can use this to match
1400 // frame index references and avoid matching constant pool references.
1401 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1402 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1403 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1406 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1407 let Inst{19-16} = addr{16-13}; // Rn
1408 let Inst{15-12} = Rt;
1409 let Inst{11-0} = addr{11-0}; // imm12
1411 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1412 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1413 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1416 let shift{4} = 0; // Inst{4} = 0
1417 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1418 let Inst{19-16} = shift{16-13}; // Rn
1419 let Inst{15-12} = Rt;
1420 let Inst{11-0} = shift{11-0};
1425 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1426 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1427 InstrItinClass iir, PatFrag opnode> {
1428 // Note: We use the complex addrmode_imm12 rather than just an input
1429 // GPR and a constrained immediate so that we can use this to match
1430 // frame index references and avoid matching constant pool references.
1431 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1432 (ins addrmode_imm12:$addr),
1433 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1434 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1437 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1438 let Inst{19-16} = addr{16-13}; // Rn
1439 let Inst{15-12} = Rt;
1440 let Inst{11-0} = addr{11-0}; // imm12
1442 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1443 (ins ldst_so_reg:$shift),
1444 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1445 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1448 let shift{4} = 0; // Inst{4} = 0
1449 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1450 let Inst{19-16} = shift{16-13}; // Rn
1451 let Inst{15-12} = Rt;
1452 let Inst{11-0} = shift{11-0};
1458 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1459 InstrItinClass iir, PatFrag opnode> {
1460 // Note: We use the complex addrmode_imm12 rather than just an input
1461 // GPR and a constrained immediate so that we can use this to match
1462 // frame index references and avoid matching constant pool references.
1463 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1464 (ins GPR:$Rt, addrmode_imm12:$addr),
1465 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1466 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1469 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1470 let Inst{19-16} = addr{16-13}; // Rn
1471 let Inst{15-12} = Rt;
1472 let Inst{11-0} = addr{11-0}; // imm12
1474 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1475 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1476 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1479 let shift{4} = 0; // Inst{4} = 0
1480 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1481 let Inst{19-16} = shift{16-13}; // Rn
1482 let Inst{15-12} = Rt;
1483 let Inst{11-0} = shift{11-0};
1487 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1488 InstrItinClass iir, PatFrag opnode> {
1489 // Note: We use the complex addrmode_imm12 rather than just an input
1490 // GPR and a constrained immediate so that we can use this to match
1491 // frame index references and avoid matching constant pool references.
1492 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1493 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1494 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1495 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1498 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1499 let Inst{19-16} = addr{16-13}; // Rn
1500 let Inst{15-12} = Rt;
1501 let Inst{11-0} = addr{11-0}; // imm12
1503 def rs : AI2ldst<0b011, 0, isByte, (outs),
1504 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1505 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1506 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1509 let shift{4} = 0; // Inst{4} = 0
1510 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1511 let Inst{19-16} = shift{16-13}; // Rn
1512 let Inst{15-12} = Rt;
1513 let Inst{11-0} = shift{11-0};
1518 //===----------------------------------------------------------------------===//
1520 //===----------------------------------------------------------------------===//
1522 //===----------------------------------------------------------------------===//
1523 // Miscellaneous Instructions.
1526 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1527 /// the function. The first operand is the ID# for this instruction, the second
1528 /// is the index into the MachineConstantPool that this is, the third is the
1529 /// size in bytes of this constant pool entry.
1530 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1531 def CONSTPOOL_ENTRY :
1532 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1533 i32imm:$size), NoItinerary, []>;
1535 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1536 // from removing one half of the matched pairs. That breaks PEI, which assumes
1537 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1538 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1539 def ADJCALLSTACKUP :
1540 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1541 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1543 def ADJCALLSTACKDOWN :
1544 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1545 [(ARMcallseq_start timm:$amt)]>;
1548 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1549 // (These pseudos use a hand-written selection code).
1550 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1551 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1552 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1554 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1555 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1557 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1558 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1560 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1561 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1563 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1564 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1566 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1567 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1569 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1570 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1572 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1573 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1574 GPR:$set1, GPR:$set2),
1578 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1579 Requires<[IsARM, HasV6T2]> {
1580 let Inst{27-16} = 0b001100100000;
1581 let Inst{15-8} = 0b11110000;
1582 let Inst{7-0} = 0b00000000;
1585 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1586 Requires<[IsARM, HasV6T2]> {
1587 let Inst{27-16} = 0b001100100000;
1588 let Inst{15-8} = 0b11110000;
1589 let Inst{7-0} = 0b00000001;
1592 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1593 Requires<[IsARM, HasV6T2]> {
1594 let Inst{27-16} = 0b001100100000;
1595 let Inst{15-8} = 0b11110000;
1596 let Inst{7-0} = 0b00000010;
1599 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1600 Requires<[IsARM, HasV6T2]> {
1601 let Inst{27-16} = 0b001100100000;
1602 let Inst{15-8} = 0b11110000;
1603 let Inst{7-0} = 0b00000011;
1606 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1607 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1612 let Inst{15-12} = Rd;
1613 let Inst{19-16} = Rn;
1614 let Inst{27-20} = 0b01101000;
1615 let Inst{7-4} = 0b1011;
1616 let Inst{11-8} = 0b1111;
1618 let Unpredictable{11-8} = 0b1111;
1621 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1622 []>, Requires<[IsARM, HasV6T2]> {
1623 let Inst{27-16} = 0b001100100000;
1624 let Inst{15-8} = 0b11110000;
1625 let Inst{7-0} = 0b00000100;
1628 // The i32imm operand $val can be used by a debugger to store more information
1629 // about the breakpoint.
1630 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1631 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1633 let Inst{3-0} = val{3-0};
1634 let Inst{19-8} = val{15-4};
1635 let Inst{27-20} = 0b00010010;
1636 let Inst{7-4} = 0b0111;
1639 // Change Processor State
1640 // FIXME: We should use InstAlias to handle the optional operands.
1641 class CPS<dag iops, string asm_ops>
1642 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1643 []>, Requires<[IsARM]> {
1649 let Inst{31-28} = 0b1111;
1650 let Inst{27-20} = 0b00010000;
1651 let Inst{19-18} = imod;
1652 let Inst{17} = M; // Enabled if mode is set;
1653 let Inst{16-9} = 0b00000000;
1654 let Inst{8-6} = iflags;
1656 let Inst{4-0} = mode;
1659 let DecoderMethod = "DecodeCPSInstruction" in {
1661 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1662 "$imod\t$iflags, $mode">;
1663 let mode = 0, M = 0 in
1664 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1666 let imod = 0, iflags = 0, M = 1 in
1667 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1670 // Preload signals the memory system of possible future data/instruction access.
1671 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1673 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1674 !strconcat(opc, "\t$addr"),
1675 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1678 let Inst{31-26} = 0b111101;
1679 let Inst{25} = 0; // 0 for immediate form
1680 let Inst{24} = data;
1681 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1682 let Inst{22} = read;
1683 let Inst{21-20} = 0b01;
1684 let Inst{19-16} = addr{16-13}; // Rn
1685 let Inst{15-12} = 0b1111;
1686 let Inst{11-0} = addr{11-0}; // imm12
1689 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1690 !strconcat(opc, "\t$shift"),
1691 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1693 let Inst{31-26} = 0b111101;
1694 let Inst{25} = 1; // 1 for register form
1695 let Inst{24} = data;
1696 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1697 let Inst{22} = read;
1698 let Inst{21-20} = 0b01;
1699 let Inst{19-16} = shift{16-13}; // Rn
1700 let Inst{15-12} = 0b1111;
1701 let Inst{11-0} = shift{11-0};
1706 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1707 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1708 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1710 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1711 "setend\t$end", []>, Requires<[IsARM]> {
1713 let Inst{31-10} = 0b1111000100000001000000;
1718 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1719 []>, Requires<[IsARM, HasV7]> {
1721 let Inst{27-4} = 0b001100100000111100001111;
1722 let Inst{3-0} = opt;
1725 // A5.4 Permanently UNDEFINED instructions.
1726 let isBarrier = 1, isTerminator = 1 in
1727 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1730 let Inst = 0xe7ffdefe;
1733 // Address computation and loads and stores in PIC mode.
1734 let isNotDuplicable = 1 in {
1735 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1737 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1739 let AddedComplexity = 10 in {
1740 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1742 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1744 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1746 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1748 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1750 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1752 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1754 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1756 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1758 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1760 let AddedComplexity = 10 in {
1761 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1762 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1764 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1765 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1766 addrmodepc:$addr)]>;
1768 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1769 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1771 } // isNotDuplicable = 1
1774 // LEApcrel - Load a pc-relative address into a register without offending the
1776 let neverHasSideEffects = 1, isReMaterializable = 1 in
1777 // The 'adr' mnemonic encodes differently if the label is before or after
1778 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1779 // know until then which form of the instruction will be used.
1780 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1781 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1784 let Inst{27-25} = 0b001;
1786 let Inst{23-22} = label{13-12};
1789 let Inst{19-16} = 0b1111;
1790 let Inst{15-12} = Rd;
1791 let Inst{11-0} = label{11-0};
1793 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1796 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1797 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1800 //===----------------------------------------------------------------------===//
1801 // Control Flow Instructions.
1804 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1806 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1807 "bx", "\tlr", [(ARMretflag)]>,
1808 Requires<[IsARM, HasV4T]> {
1809 let Inst{27-0} = 0b0001001011111111111100011110;
1813 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1814 "mov", "\tpc, lr", [(ARMretflag)]>,
1815 Requires<[IsARM, NoV4T]> {
1816 let Inst{27-0} = 0b0001101000001111000000001110;
1820 // Indirect branches
1821 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1823 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1824 [(brind GPR:$dst)]>,
1825 Requires<[IsARM, HasV4T]> {
1827 let Inst{31-4} = 0b1110000100101111111111110001;
1828 let Inst{3-0} = dst;
1831 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1832 "bx", "\t$dst", [/* pattern left blank */]>,
1833 Requires<[IsARM, HasV4T]> {
1835 let Inst{27-4} = 0b000100101111111111110001;
1836 let Inst{3-0} = dst;
1840 // SP is marked as a use to prevent stack-pointer assignments that appear
1841 // immediately before calls from potentially appearing dead.
1843 // FIXME: Do we really need a non-predicated version? If so, it should
1844 // at least be a pseudo instruction expanding to the predicated version
1845 // at MC lowering time.
1846 Defs = [LR], Uses = [SP] in {
1847 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1848 IIC_Br, "bl\t$func",
1849 [(ARMcall tglobaladdr:$func)]>,
1851 let Inst{31-28} = 0b1110;
1853 let Inst{23-0} = func;
1854 let DecoderMethod = "DecodeBranchImmInstruction";
1857 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1858 IIC_Br, "bl", "\t$func",
1859 [(ARMcall_pred tglobaladdr:$func)]>,
1862 let Inst{23-0} = func;
1863 let DecoderMethod = "DecodeBranchImmInstruction";
1867 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1868 IIC_Br, "blx\t$func",
1869 [(ARMcall GPR:$func)]>,
1870 Requires<[IsARM, HasV5T]> {
1872 let Inst{31-4} = 0b1110000100101111111111110011;
1873 let Inst{3-0} = func;
1876 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1877 IIC_Br, "blx", "\t$func",
1878 [(ARMcall_pred GPR:$func)]>,
1879 Requires<[IsARM, HasV5T]> {
1881 let Inst{27-4} = 0b000100101111111111110011;
1882 let Inst{3-0} = func;
1886 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1887 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1888 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1889 Requires<[IsARM, HasV4T]>;
1892 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1893 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1894 Requires<[IsARM, NoV4T]>;
1896 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1897 // return stack predictor.
1898 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1899 (ins bl_target:$func, variable_ops),
1900 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1904 let isBranch = 1, isTerminator = 1 in {
1905 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1906 // a two-value operand where a dag node expects two operands. :(
1907 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1908 IIC_Br, "b", "\t$target",
1909 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1911 let Inst{23-0} = target;
1912 let DecoderMethod = "DecodeBranchImmInstruction";
1915 let isBarrier = 1 in {
1916 // B is "predicable" since it's just a Bcc with an 'always' condition.
1917 let isPredicable = 1 in
1918 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1919 // should be sufficient.
1920 // FIXME: Is B really a Barrier? That doesn't seem right.
1921 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1922 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1924 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1925 def BR_JTr : ARMPseudoInst<(outs),
1926 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1928 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1929 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1930 // into i12 and rs suffixed versions.
1931 def BR_JTm : ARMPseudoInst<(outs),
1932 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1934 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1936 def BR_JTadd : ARMPseudoInst<(outs),
1937 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1939 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1941 } // isNotDuplicable = 1, isIndirectBranch = 1
1947 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1948 "blx\t$target", []>,
1949 Requires<[IsARM, HasV5T]> {
1950 let Inst{31-25} = 0b1111101;
1952 let Inst{23-0} = target{24-1};
1953 let Inst{24} = target{0};
1956 // Branch and Exchange Jazelle
1957 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1958 [/* pattern left blank */]> {
1960 let Inst{23-20} = 0b0010;
1961 let Inst{19-8} = 0xfff;
1962 let Inst{7-4} = 0b0010;
1963 let Inst{3-0} = func;
1968 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1969 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1972 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1975 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1977 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1980 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1986 // Secure Monitor Call is a system instruction.
1987 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1990 let Inst{23-4} = 0b01100000000000000111;
1991 let Inst{3-0} = opt;
1994 // Supervisor Call (Software Interrupt)
1995 let isCall = 1, Uses = [SP] in {
1996 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1998 let Inst{23-0} = svc;
2002 // Store Return State
2003 class SRSI<bit wb, string asm>
2004 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2005 NoItinerary, asm, "", []> {
2007 let Inst{31-28} = 0b1111;
2008 let Inst{27-25} = 0b100;
2012 let Inst{19-16} = 0b1101; // SP
2013 let Inst{15-5} = 0b00000101000;
2014 let Inst{4-0} = mode;
2017 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2018 let Inst{24-23} = 0;
2020 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2021 let Inst{24-23} = 0;
2023 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2024 let Inst{24-23} = 0b10;
2026 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2027 let Inst{24-23} = 0b10;
2029 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2030 let Inst{24-23} = 0b01;
2032 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2033 let Inst{24-23} = 0b01;
2035 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2036 let Inst{24-23} = 0b11;
2038 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2039 let Inst{24-23} = 0b11;
2042 // Return From Exception
2043 class RFEI<bit wb, string asm>
2044 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2045 NoItinerary, asm, "", []> {
2047 let Inst{31-28} = 0b1111;
2048 let Inst{27-25} = 0b100;
2052 let Inst{19-16} = Rn;
2053 let Inst{15-0} = 0xa00;
2056 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2057 let Inst{24-23} = 0;
2059 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2060 let Inst{24-23} = 0;
2062 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2063 let Inst{24-23} = 0b10;
2065 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2066 let Inst{24-23} = 0b10;
2068 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2069 let Inst{24-23} = 0b01;
2071 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2072 let Inst{24-23} = 0b01;
2074 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2075 let Inst{24-23} = 0b11;
2077 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2078 let Inst{24-23} = 0b11;
2081 //===----------------------------------------------------------------------===//
2082 // Load / Store Instructions.
2088 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2089 UnOpFrag<(load node:$Src)>>;
2090 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2091 UnOpFrag<(zextloadi8 node:$Src)>>;
2092 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2093 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2094 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2095 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2097 // Special LDR for loads from non-pc-relative constpools.
2098 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2099 isReMaterializable = 1, isCodeGenOnly = 1 in
2100 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2101 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2105 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2106 let Inst{19-16} = 0b1111;
2107 let Inst{15-12} = Rt;
2108 let Inst{11-0} = addr{11-0}; // imm12
2111 // Loads with zero extension
2112 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2113 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2114 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2116 // Loads with sign extension
2117 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2118 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2119 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2121 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2122 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2123 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2125 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2127 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2128 (ins addrmode3:$addr), LdMiscFrm,
2129 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2130 []>, Requires<[IsARM, HasV5TE]>;
2134 multiclass AI2_ldridx<bit isByte, string opc,
2135 InstrItinClass iii, InstrItinClass iir> {
2136 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2137 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2138 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2141 let Inst{23} = addr{12};
2142 let Inst{19-16} = addr{16-13};
2143 let Inst{11-0} = addr{11-0};
2144 let DecoderMethod = "DecodeLDRPreImm";
2145 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2148 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2149 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2150 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2153 let Inst{23} = addr{12};
2154 let Inst{19-16} = addr{16-13};
2155 let Inst{11-0} = addr{11-0};
2157 let DecoderMethod = "DecodeLDRPreReg";
2158 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2161 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2162 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2163 IndexModePost, LdFrm, iir,
2164 opc, "\t$Rt, $addr, $offset",
2165 "$addr.base = $Rn_wb", []> {
2171 let Inst{23} = offset{12};
2172 let Inst{19-16} = addr;
2173 let Inst{11-0} = offset{11-0};
2175 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2178 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2179 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2180 IndexModePost, LdFrm, iii,
2181 opc, "\t$Rt, $addr, $offset",
2182 "$addr.base = $Rn_wb", []> {
2188 let Inst{23} = offset{12};
2189 let Inst{19-16} = addr;
2190 let Inst{11-0} = offset{11-0};
2192 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2197 let mayLoad = 1, neverHasSideEffects = 1 in {
2198 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2199 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2200 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2201 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2204 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2205 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2206 (ins addrmode3:$addr), IndexModePre,
2208 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2210 let Inst{23} = addr{8}; // U bit
2211 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2212 let Inst{19-16} = addr{12-9}; // Rn
2213 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2214 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2215 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2216 let DecoderMethod = "DecodeAddrMode3Instruction";
2218 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2219 (ins addr_offset_none:$addr, am3offset:$offset),
2220 IndexModePost, LdMiscFrm, itin,
2221 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2225 let Inst{23} = offset{8}; // U bit
2226 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2227 let Inst{19-16} = addr;
2228 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2229 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2230 let DecoderMethod = "DecodeAddrMode3Instruction";
2234 let mayLoad = 1, neverHasSideEffects = 1 in {
2235 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2236 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2237 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2238 let hasExtraDefRegAllocReq = 1 in {
2239 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2240 (ins addrmode3:$addr), IndexModePre,
2241 LdMiscFrm, IIC_iLoad_d_ru,
2242 "ldrd", "\t$Rt, $Rt2, $addr!",
2243 "$addr.base = $Rn_wb", []> {
2245 let Inst{23} = addr{8}; // U bit
2246 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2247 let Inst{19-16} = addr{12-9}; // Rn
2248 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2249 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2250 let DecoderMethod = "DecodeAddrMode3Instruction";
2251 let AsmMatchConverter = "cvtLdrdPre";
2253 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2254 (ins addr_offset_none:$addr, am3offset:$offset),
2255 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2256 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2257 "$addr.base = $Rn_wb", []> {
2260 let Inst{23} = offset{8}; // U bit
2261 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2262 let Inst{19-16} = addr;
2263 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2264 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2265 let DecoderMethod = "DecodeAddrMode3Instruction";
2267 } // hasExtraDefRegAllocReq = 1
2268 } // mayLoad = 1, neverHasSideEffects = 1
2270 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2271 let mayLoad = 1, neverHasSideEffects = 1 in {
2272 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2273 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2274 IndexModePost, LdFrm, IIC_iLoad_ru,
2275 "ldrt", "\t$Rt, $addr, $offset",
2276 "$addr.base = $Rn_wb", []> {
2282 let Inst{23} = offset{12};
2283 let Inst{21} = 1; // overwrite
2284 let Inst{19-16} = addr;
2285 let Inst{11-5} = offset{11-5};
2287 let Inst{3-0} = offset{3-0};
2288 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2291 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2292 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2293 IndexModePost, LdFrm, IIC_iLoad_ru,
2294 "ldrt", "\t$Rt, $addr, $offset",
2295 "$addr.base = $Rn_wb", []> {
2301 let Inst{23} = offset{12};
2302 let Inst{21} = 1; // overwrite
2303 let Inst{19-16} = addr;
2304 let Inst{11-0} = offset{11-0};
2305 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2308 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2309 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2310 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2311 "ldrbt", "\t$Rt, $addr, $offset",
2312 "$addr.base = $Rn_wb", []> {
2318 let Inst{23} = offset{12};
2319 let Inst{21} = 1; // overwrite
2320 let Inst{19-16} = addr;
2321 let Inst{11-5} = offset{11-5};
2323 let Inst{3-0} = offset{3-0};
2324 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2327 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2328 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2329 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2330 "ldrbt", "\t$Rt, $addr, $offset",
2331 "$addr.base = $Rn_wb", []> {
2337 let Inst{23} = offset{12};
2338 let Inst{21} = 1; // overwrite
2339 let Inst{19-16} = addr;
2340 let Inst{11-0} = offset{11-0};
2341 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2344 multiclass AI3ldrT<bits<4> op, string opc> {
2345 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2346 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2347 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2348 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2350 let Inst{23} = offset{8};
2352 let Inst{11-8} = offset{7-4};
2353 let Inst{3-0} = offset{3-0};
2354 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2356 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2357 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2358 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2359 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2361 let Inst{23} = Rm{4};
2364 let Unpredictable{11-8} = 0b1111;
2365 let Inst{3-0} = Rm{3-0};
2366 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2367 let DecoderMethod = "DecodeLDR";
2371 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2372 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2373 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2378 // Stores with truncate
2379 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2380 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2381 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2384 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2385 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2386 StMiscFrm, IIC_iStore_d_r,
2387 "strd", "\t$Rt, $src2, $addr", []>,
2388 Requires<[IsARM, HasV5TE]> {
2393 multiclass AI2_stridx<bit isByte, string opc,
2394 InstrItinClass iii, InstrItinClass iir> {
2395 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2396 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2398 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2401 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2402 let Inst{19-16} = addr{16-13}; // Rn
2403 let Inst{11-0} = addr{11-0}; // imm12
2404 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2405 let DecoderMethod = "DecodeSTRPreImm";
2408 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2409 (ins GPR:$Rt, ldst_so_reg:$addr),
2410 IndexModePre, StFrm, iir,
2411 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2414 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2415 let Inst{19-16} = addr{16-13}; // Rn
2416 let Inst{11-0} = addr{11-0};
2417 let Inst{4} = 0; // Inst{4} = 0
2418 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2419 let DecoderMethod = "DecodeSTRPreReg";
2421 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2422 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2423 IndexModePost, StFrm, iir,
2424 opc, "\t$Rt, $addr, $offset",
2425 "$addr.base = $Rn_wb", []> {
2431 let Inst{23} = offset{12};
2432 let Inst{19-16} = addr;
2433 let Inst{11-0} = offset{11-0};
2436 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2439 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2440 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2441 IndexModePost, StFrm, iii,
2442 opc, "\t$Rt, $addr, $offset",
2443 "$addr.base = $Rn_wb", []> {
2449 let Inst{23} = offset{12};
2450 let Inst{19-16} = addr;
2451 let Inst{11-0} = offset{11-0};
2453 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2457 let mayStore = 1, neverHasSideEffects = 1 in {
2458 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2459 // IIC_iStore_siu depending on whether it the offset register is shifted.
2460 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2461 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2464 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2465 am2offset_reg:$offset),
2466 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2467 am2offset_reg:$offset)>;
2468 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2469 am2offset_imm:$offset),
2470 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2471 am2offset_imm:$offset)>;
2472 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2473 am2offset_reg:$offset),
2474 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2475 am2offset_reg:$offset)>;
2476 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2477 am2offset_imm:$offset),
2478 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2479 am2offset_imm:$offset)>;
2481 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2482 // put the patterns on the instruction definitions directly as ISel wants
2483 // the address base and offset to be separate operands, not a single
2484 // complex operand like we represent the instructions themselves. The
2485 // pseudos map between the two.
2486 let usesCustomInserter = 1,
2487 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2488 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2489 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2492 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2493 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2494 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2497 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2498 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2499 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2502 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2503 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2504 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2507 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2508 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2509 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2512 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2517 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2518 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2519 StMiscFrm, IIC_iStore_bh_ru,
2520 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2522 let Inst{23} = addr{8}; // U bit
2523 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2524 let Inst{19-16} = addr{12-9}; // Rn
2525 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2526 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2527 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2528 let DecoderMethod = "DecodeAddrMode3Instruction";
2531 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2532 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2533 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2534 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2535 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2536 addr_offset_none:$addr,
2537 am3offset:$offset))]> {
2540 let Inst{23} = offset{8}; // U bit
2541 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2542 let Inst{19-16} = addr;
2543 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2544 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2545 let DecoderMethod = "DecodeAddrMode3Instruction";
2548 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2549 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2550 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2551 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2552 "strd", "\t$Rt, $Rt2, $addr!",
2553 "$addr.base = $Rn_wb", []> {
2555 let Inst{23} = addr{8}; // U bit
2556 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2557 let Inst{19-16} = addr{12-9}; // Rn
2558 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2559 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2560 let DecoderMethod = "DecodeAddrMode3Instruction";
2561 let AsmMatchConverter = "cvtStrdPre";
2564 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2565 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2567 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2568 "strd", "\t$Rt, $Rt2, $addr, $offset",
2569 "$addr.base = $Rn_wb", []> {
2572 let Inst{23} = offset{8}; // U bit
2573 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2574 let Inst{19-16} = addr;
2575 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2576 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2577 let DecoderMethod = "DecodeAddrMode3Instruction";
2579 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2581 // STRT, STRBT, and STRHT
2583 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2584 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2585 IndexModePost, StFrm, IIC_iStore_bh_ru,
2586 "strbt", "\t$Rt, $addr, $offset",
2587 "$addr.base = $Rn_wb", []> {
2593 let Inst{23} = offset{12};
2594 let Inst{21} = 1; // overwrite
2595 let Inst{19-16} = addr;
2596 let Inst{11-5} = offset{11-5};
2598 let Inst{3-0} = offset{3-0};
2599 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2602 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2603 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2604 IndexModePost, StFrm, IIC_iStore_bh_ru,
2605 "strbt", "\t$Rt, $addr, $offset",
2606 "$addr.base = $Rn_wb", []> {
2612 let Inst{23} = offset{12};
2613 let Inst{21} = 1; // overwrite
2614 let Inst{19-16} = addr;
2615 let Inst{11-0} = offset{11-0};
2616 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2619 let mayStore = 1, neverHasSideEffects = 1 in {
2620 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2621 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2622 IndexModePost, StFrm, IIC_iStore_ru,
2623 "strt", "\t$Rt, $addr, $offset",
2624 "$addr.base = $Rn_wb", []> {
2630 let Inst{23} = offset{12};
2631 let Inst{21} = 1; // overwrite
2632 let Inst{19-16} = addr;
2633 let Inst{11-5} = offset{11-5};
2635 let Inst{3-0} = offset{3-0};
2636 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2639 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2640 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2641 IndexModePost, StFrm, IIC_iStore_ru,
2642 "strt", "\t$Rt, $addr, $offset",
2643 "$addr.base = $Rn_wb", []> {
2649 let Inst{23} = offset{12};
2650 let Inst{21} = 1; // overwrite
2651 let Inst{19-16} = addr;
2652 let Inst{11-0} = offset{11-0};
2653 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2658 multiclass AI3strT<bits<4> op, string opc> {
2659 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2660 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2661 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2662 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2664 let Inst{23} = offset{8};
2666 let Inst{11-8} = offset{7-4};
2667 let Inst{3-0} = offset{3-0};
2668 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2670 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2671 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2672 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2673 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2675 let Inst{23} = Rm{4};
2678 let Inst{3-0} = Rm{3-0};
2679 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2684 defm STRHT : AI3strT<0b1011, "strht">;
2687 //===----------------------------------------------------------------------===//
2688 // Load / store multiple Instructions.
2691 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2692 InstrItinClass itin, InstrItinClass itin_upd> {
2693 // IA is the default, so no need for an explicit suffix on the
2694 // mnemonic here. Without it is the cannonical spelling.
2696 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2697 IndexModeNone, f, itin,
2698 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2699 let Inst{24-23} = 0b01; // Increment After
2700 let Inst{22} = P_bit;
2701 let Inst{21} = 0; // No writeback
2702 let Inst{20} = L_bit;
2705 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2706 IndexModeUpd, f, itin_upd,
2707 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2708 let Inst{24-23} = 0b01; // Increment After
2709 let Inst{22} = P_bit;
2710 let Inst{21} = 1; // Writeback
2711 let Inst{20} = L_bit;
2713 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2716 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2717 IndexModeNone, f, itin,
2718 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2719 let Inst{24-23} = 0b00; // Decrement After
2720 let Inst{22} = P_bit;
2721 let Inst{21} = 0; // No writeback
2722 let Inst{20} = L_bit;
2725 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2726 IndexModeUpd, f, itin_upd,
2727 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2728 let Inst{24-23} = 0b00; // Decrement After
2729 let Inst{22} = P_bit;
2730 let Inst{21} = 1; // Writeback
2731 let Inst{20} = L_bit;
2733 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2736 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2737 IndexModeNone, f, itin,
2738 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2739 let Inst{24-23} = 0b10; // Decrement Before
2740 let Inst{22} = P_bit;
2741 let Inst{21} = 0; // No writeback
2742 let Inst{20} = L_bit;
2745 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2746 IndexModeUpd, f, itin_upd,
2747 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2748 let Inst{24-23} = 0b10; // Decrement Before
2749 let Inst{22} = P_bit;
2750 let Inst{21} = 1; // Writeback
2751 let Inst{20} = L_bit;
2753 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2756 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2757 IndexModeNone, f, itin,
2758 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2759 let Inst{24-23} = 0b11; // Increment Before
2760 let Inst{22} = P_bit;
2761 let Inst{21} = 0; // No writeback
2762 let Inst{20} = L_bit;
2765 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2766 IndexModeUpd, f, itin_upd,
2767 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2768 let Inst{24-23} = 0b11; // Increment Before
2769 let Inst{22} = P_bit;
2770 let Inst{21} = 1; // Writeback
2771 let Inst{20} = L_bit;
2773 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2777 let neverHasSideEffects = 1 in {
2779 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2780 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2783 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2784 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2787 } // neverHasSideEffects
2789 // FIXME: remove when we have a way to marking a MI with these properties.
2790 // FIXME: Should pc be an implicit operand like PICADD, etc?
2791 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2792 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2793 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2794 reglist:$regs, variable_ops),
2795 4, IIC_iLoad_mBr, [],
2796 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2797 RegConstraint<"$Rn = $wb">;
2799 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2800 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2803 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2804 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2809 //===----------------------------------------------------------------------===//
2810 // Move Instructions.
2813 let neverHasSideEffects = 1 in
2814 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2815 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2819 let Inst{19-16} = 0b0000;
2820 let Inst{11-4} = 0b00000000;
2823 let Inst{15-12} = Rd;
2826 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2827 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2829 // A version for the smaller set of tail call registers.
2830 let neverHasSideEffects = 1 in
2831 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2832 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2836 let Inst{11-4} = 0b00000000;
2839 let Inst{15-12} = Rd;
2842 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2843 DPSoRegRegFrm, IIC_iMOVsr,
2844 "mov", "\t$Rd, $src",
2845 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2848 let Inst{15-12} = Rd;
2849 let Inst{19-16} = 0b0000;
2850 let Inst{11-8} = src{11-8};
2852 let Inst{6-5} = src{6-5};
2854 let Inst{3-0} = src{3-0};
2858 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2859 DPSoRegImmFrm, IIC_iMOVsr,
2860 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2864 let Inst{15-12} = Rd;
2865 let Inst{19-16} = 0b0000;
2866 let Inst{11-5} = src{11-5};
2868 let Inst{3-0} = src{3-0};
2872 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2873 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2874 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2878 let Inst{15-12} = Rd;
2879 let Inst{19-16} = 0b0000;
2880 let Inst{11-0} = imm;
2883 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2884 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2886 "movw", "\t$Rd, $imm",
2887 [(set GPR:$Rd, imm0_65535:$imm)]>,
2888 Requires<[IsARM, HasV6T2]>, UnaryDP {
2891 let Inst{15-12} = Rd;
2892 let Inst{11-0} = imm{11-0};
2893 let Inst{19-16} = imm{15-12};
2896 let DecoderMethod = "DecodeArmMOVTWInstruction";
2899 def : InstAlias<"mov${p} $Rd, $imm",
2900 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2903 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2904 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2906 let Constraints = "$src = $Rd" in {
2907 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2908 (ins GPR:$src, imm0_65535_expr:$imm),
2910 "movt", "\t$Rd, $imm",
2912 (or (and GPR:$src, 0xffff),
2913 lo16AllZero:$imm))]>, UnaryDP,
2914 Requires<[IsARM, HasV6T2]> {
2917 let Inst{15-12} = Rd;
2918 let Inst{11-0} = imm{11-0};
2919 let Inst{19-16} = imm{15-12};
2922 let DecoderMethod = "DecodeArmMOVTWInstruction";
2925 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2926 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2930 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2931 Requires<[IsARM, HasV6T2]>;
2933 let Uses = [CPSR] in
2934 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2935 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2938 // These aren't really mov instructions, but we have to define them this way
2939 // due to flag operands.
2941 let Defs = [CPSR] in {
2942 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2943 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2945 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2946 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2950 //===----------------------------------------------------------------------===//
2951 // Extend Instructions.
2956 def SXTB : AI_ext_rrot<0b01101010,
2957 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2958 def SXTH : AI_ext_rrot<0b01101011,
2959 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2961 def SXTAB : AI_exta_rrot<0b01101010,
2962 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2963 def SXTAH : AI_exta_rrot<0b01101011,
2964 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2966 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2968 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2972 let AddedComplexity = 16 in {
2973 def UXTB : AI_ext_rrot<0b01101110,
2974 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2975 def UXTH : AI_ext_rrot<0b01101111,
2976 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2977 def UXTB16 : AI_ext_rrot<0b01101100,
2978 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2980 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2981 // The transformation should probably be done as a combiner action
2982 // instead so we can include a check for masking back in the upper
2983 // eight bits of the source into the lower eight bits of the result.
2984 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2985 // (UXTB16r_rot GPR:$Src, 3)>;
2986 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2987 (UXTB16 GPR:$Src, 1)>;
2989 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2990 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2991 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2992 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2995 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2996 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2999 def SBFX : I<(outs GPRnopc:$Rd),
3000 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3001 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3002 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3003 Requires<[IsARM, HasV6T2]> {
3008 let Inst{27-21} = 0b0111101;
3009 let Inst{6-4} = 0b101;
3010 let Inst{20-16} = width;
3011 let Inst{15-12} = Rd;
3012 let Inst{11-7} = lsb;
3016 def UBFX : I<(outs GPR:$Rd),
3017 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3018 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3019 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3020 Requires<[IsARM, HasV6T2]> {
3025 let Inst{27-21} = 0b0111111;
3026 let Inst{6-4} = 0b101;
3027 let Inst{20-16} = width;
3028 let Inst{15-12} = Rd;
3029 let Inst{11-7} = lsb;
3033 //===----------------------------------------------------------------------===//
3034 // Arithmetic Instructions.
3037 defm ADD : AsI1_bin_irs<0b0100, "add",
3038 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3039 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3040 defm SUB : AsI1_bin_irs<0b0010, "sub",
3041 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3042 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3044 // ADD and SUB with 's' bit set.
3046 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3047 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3048 // AdjustInstrPostInstrSelection where we determine whether or not to
3049 // set the "s" bit based on CPSR liveness.
3051 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3052 // support for an optional CPSR definition that corresponds to the DAG
3053 // node's second value. We can then eliminate the implicit def of CPSR.
3054 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3055 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3056 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3057 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3059 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3060 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3062 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3063 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3066 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3067 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3068 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3070 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3071 // CPSR and the implicit def of CPSR is not needed.
3072 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3073 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3075 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3076 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3079 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3080 // The assume-no-carry-in form uses the negation of the input since add/sub
3081 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3082 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3084 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3085 (SUBri GPR:$src, so_imm_neg:$imm)>;
3086 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3087 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3089 // The with-carry-in form matches bitwise not instead of the negation.
3090 // Effectively, the inverse interpretation of the carry flag already accounts
3091 // for part of the negation.
3092 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3093 (SBCri GPR:$src, so_imm_not:$imm)>;
3095 // Note: These are implemented in C++ code, because they have to generate
3096 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3098 // (mul X, 2^n+1) -> (add (X << n), X)
3099 // (mul X, 2^n-1) -> (rsb X, (X << n))
3101 // ARM Arithmetic Instruction
3102 // GPR:$dst = GPR:$a op GPR:$b
3103 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3104 list<dag> pattern = [],
3105 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3106 string asm = "\t$Rd, $Rn, $Rm">
3107 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3111 let Inst{27-20} = op27_20;
3112 let Inst{11-4} = op11_4;
3113 let Inst{19-16} = Rn;
3114 let Inst{15-12} = Rd;
3117 let Unpredictable{11-8} = 0b1111;
3120 // Saturating add/subtract
3122 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3123 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3124 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3125 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3126 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3127 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3128 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3129 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3131 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3132 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3135 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3136 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3137 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3138 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3139 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3140 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3141 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3142 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3143 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3144 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3145 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3146 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3148 // Signed/Unsigned add/subtract
3150 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3151 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3152 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3153 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3154 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3155 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3156 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3157 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3158 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3159 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3160 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3161 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3163 // Signed/Unsigned halving add/subtract
3165 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3166 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3167 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3168 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3169 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3170 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3171 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3172 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3173 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3174 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3175 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3176 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3178 // Unsigned Sum of Absolute Differences [and Accumulate].
3180 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3181 MulFrm /* for convenience */, NoItinerary, "usad8",
3182 "\t$Rd, $Rn, $Rm", []>,
3183 Requires<[IsARM, HasV6]> {
3187 let Inst{27-20} = 0b01111000;
3188 let Inst{15-12} = 0b1111;
3189 let Inst{7-4} = 0b0001;
3190 let Inst{19-16} = Rd;
3191 let Inst{11-8} = Rm;
3194 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3195 MulFrm /* for convenience */, NoItinerary, "usada8",
3196 "\t$Rd, $Rn, $Rm, $Ra", []>,
3197 Requires<[IsARM, HasV6]> {
3202 let Inst{27-20} = 0b01111000;
3203 let Inst{7-4} = 0b0001;
3204 let Inst{19-16} = Rd;
3205 let Inst{15-12} = Ra;
3206 let Inst{11-8} = Rm;
3210 // Signed/Unsigned saturate
3212 def SSAT : AI<(outs GPRnopc:$Rd),
3213 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3214 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3219 let Inst{27-21} = 0b0110101;
3220 let Inst{5-4} = 0b01;
3221 let Inst{20-16} = sat_imm;
3222 let Inst{15-12} = Rd;
3223 let Inst{11-7} = sh{4-0};
3224 let Inst{6} = sh{5};
3228 def SSAT16 : AI<(outs GPRnopc:$Rd),
3229 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3230 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3234 let Inst{27-20} = 0b01101010;
3235 let Inst{11-4} = 0b11110011;
3236 let Inst{15-12} = Rd;
3237 let Inst{19-16} = sat_imm;
3241 def USAT : AI<(outs GPRnopc:$Rd),
3242 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3243 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3248 let Inst{27-21} = 0b0110111;
3249 let Inst{5-4} = 0b01;
3250 let Inst{15-12} = Rd;
3251 let Inst{11-7} = sh{4-0};
3252 let Inst{6} = sh{5};
3253 let Inst{20-16} = sat_imm;
3257 def USAT16 : AI<(outs GPRnopc:$Rd),
3258 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3259 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3263 let Inst{27-20} = 0b01101110;
3264 let Inst{11-4} = 0b11110011;
3265 let Inst{15-12} = Rd;
3266 let Inst{19-16} = sat_imm;
3270 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3271 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3272 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3273 (USAT imm:$pos, GPRnopc:$a, 0)>;
3275 //===----------------------------------------------------------------------===//
3276 // Bitwise Instructions.
3279 defm AND : AsI1_bin_irs<0b0000, "and",
3280 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3281 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3282 defm ORR : AsI1_bin_irs<0b1100, "orr",
3283 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3284 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3285 defm EOR : AsI1_bin_irs<0b0001, "eor",
3286 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3287 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3288 defm BIC : AsI1_bin_irs<0b1110, "bic",
3289 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3290 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3292 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3293 // like in the actual instruction encoding. The complexity of mapping the mask
3294 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3295 // instruction description.
3296 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3297 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3298 "bfc", "\t$Rd, $imm", "$src = $Rd",
3299 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3300 Requires<[IsARM, HasV6T2]> {
3303 let Inst{27-21} = 0b0111110;
3304 let Inst{6-0} = 0b0011111;
3305 let Inst{15-12} = Rd;
3306 let Inst{11-7} = imm{4-0}; // lsb
3307 let Inst{20-16} = imm{9-5}; // msb
3310 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3311 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3312 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3313 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3314 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3315 bf_inv_mask_imm:$imm))]>,
3316 Requires<[IsARM, HasV6T2]> {
3320 let Inst{27-21} = 0b0111110;
3321 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3322 let Inst{15-12} = Rd;
3323 let Inst{11-7} = imm{4-0}; // lsb
3324 let Inst{20-16} = imm{9-5}; // width
3328 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3329 "mvn", "\t$Rd, $Rm",
3330 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3334 let Inst{19-16} = 0b0000;
3335 let Inst{11-4} = 0b00000000;
3336 let Inst{15-12} = Rd;
3339 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3340 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3341 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3345 let Inst{19-16} = 0b0000;
3346 let Inst{15-12} = Rd;
3347 let Inst{11-5} = shift{11-5};
3349 let Inst{3-0} = shift{3-0};
3351 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3352 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3353 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3357 let Inst{19-16} = 0b0000;
3358 let Inst{15-12} = Rd;
3359 let Inst{11-8} = shift{11-8};
3361 let Inst{6-5} = shift{6-5};
3363 let Inst{3-0} = shift{3-0};
3365 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3366 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3367 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3368 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3372 let Inst{19-16} = 0b0000;
3373 let Inst{15-12} = Rd;
3374 let Inst{11-0} = imm;
3377 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3378 (BICri GPR:$src, so_imm_not:$imm)>;
3380 //===----------------------------------------------------------------------===//
3381 // Multiply Instructions.
3383 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3384 string opc, string asm, list<dag> pattern>
3385 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3389 let Inst{19-16} = Rd;
3390 let Inst{11-8} = Rm;
3393 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3394 string opc, string asm, list<dag> pattern>
3395 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3400 let Inst{19-16} = RdHi;
3401 let Inst{15-12} = RdLo;
3402 let Inst{11-8} = Rm;
3406 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3407 // property. Remove them when it's possible to add those properties
3408 // on an individual MachineInstr, not just an instuction description.
3409 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3410 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3411 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3412 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3413 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3414 Requires<[IsARM, HasV6]> {
3415 let Inst{15-12} = 0b0000;
3416 let Unpredictable{15-12} = 0b1111;
3419 let Constraints = "@earlyclobber $Rd" in
3420 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3421 pred:$p, cc_out:$s),
3423 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3424 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3425 Requires<[IsARM, NoV6]>;
3428 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3429 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3430 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3431 Requires<[IsARM, HasV6]> {
3433 let Inst{15-12} = Ra;
3436 let Constraints = "@earlyclobber $Rd" in
3437 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3438 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3440 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3441 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3442 Requires<[IsARM, NoV6]>;
3444 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3445 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3446 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3447 Requires<[IsARM, HasV6T2]> {
3452 let Inst{19-16} = Rd;
3453 let Inst{15-12} = Ra;
3454 let Inst{11-8} = Rm;
3458 // Extra precision multiplies with low / high results
3459 let neverHasSideEffects = 1 in {
3460 let isCommutable = 1 in {
3461 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3462 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3463 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3464 Requires<[IsARM, HasV6]>;
3466 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3467 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3468 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3469 Requires<[IsARM, HasV6]>;
3471 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3472 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3473 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3475 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3476 Requires<[IsARM, NoV6]>;
3478 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3479 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3481 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3482 Requires<[IsARM, NoV6]>;
3486 // Multiply + accumulate
3487 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3488 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3489 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3490 Requires<[IsARM, HasV6]>;
3491 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3492 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3493 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3494 Requires<[IsARM, HasV6]>;
3496 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3497 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3498 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3499 Requires<[IsARM, HasV6]> {
3504 let Inst{19-16} = RdHi;
3505 let Inst{15-12} = RdLo;
3506 let Inst{11-8} = Rm;
3510 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3511 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3512 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3514 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3515 Requires<[IsARM, NoV6]>;
3516 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3517 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3519 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3520 Requires<[IsARM, NoV6]>;
3521 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3522 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3524 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3525 Requires<[IsARM, NoV6]>;
3528 } // neverHasSideEffects
3530 // Most significant word multiply
3531 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3532 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3533 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3534 Requires<[IsARM, HasV6]> {
3535 let Inst{15-12} = 0b1111;
3538 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3539 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3540 Requires<[IsARM, HasV6]> {
3541 let Inst{15-12} = 0b1111;
3544 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3545 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3546 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3547 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3548 Requires<[IsARM, HasV6]>;
3550 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3551 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3552 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3553 Requires<[IsARM, HasV6]>;
3555 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3556 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3557 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3558 Requires<[IsARM, HasV6]>;
3560 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3561 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3562 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3563 Requires<[IsARM, HasV6]>;
3565 multiclass AI_smul<string opc, PatFrag opnode> {
3566 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3567 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3568 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3569 (sext_inreg GPR:$Rm, i16)))]>,
3570 Requires<[IsARM, HasV5TE]>;
3572 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3573 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3574 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3575 (sra GPR:$Rm, (i32 16))))]>,
3576 Requires<[IsARM, HasV5TE]>;
3578 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3579 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3580 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3581 (sext_inreg GPR:$Rm, i16)))]>,
3582 Requires<[IsARM, HasV5TE]>;
3584 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3585 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3586 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3587 (sra GPR:$Rm, (i32 16))))]>,
3588 Requires<[IsARM, HasV5TE]>;
3590 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3591 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3592 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3593 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3594 Requires<[IsARM, HasV5TE]>;
3596 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3597 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3598 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3599 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3600 Requires<[IsARM, HasV5TE]>;
3604 multiclass AI_smla<string opc, PatFrag opnode> {
3605 let DecoderMethod = "DecodeSMLAInstruction" in {
3606 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3607 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3608 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3609 [(set GPRnopc:$Rd, (add GPR:$Ra,
3610 (opnode (sext_inreg GPRnopc:$Rn, i16),
3611 (sext_inreg GPRnopc:$Rm, i16))))]>,
3612 Requires<[IsARM, HasV5TE]>;
3614 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3615 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3616 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3618 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3619 (sra GPRnopc:$Rm, (i32 16)))))]>,
3620 Requires<[IsARM, HasV5TE]>;
3622 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3623 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3624 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3626 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3627 (sext_inreg GPRnopc:$Rm, i16))))]>,
3628 Requires<[IsARM, HasV5TE]>;
3630 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3631 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3632 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3634 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3635 (sra GPRnopc:$Rm, (i32 16)))))]>,
3636 Requires<[IsARM, HasV5TE]>;
3638 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3639 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3640 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3642 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3643 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3644 Requires<[IsARM, HasV5TE]>;
3646 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3647 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3648 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3650 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3651 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3652 Requires<[IsARM, HasV5TE]>;
3656 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3657 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3659 // Halfword multiply accumulate long: SMLAL<x><y>.
3660 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3661 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3662 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3663 Requires<[IsARM, HasV5TE]>;
3665 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3666 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3667 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3668 Requires<[IsARM, HasV5TE]>;
3670 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3671 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3672 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3673 Requires<[IsARM, HasV5TE]>;
3675 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3676 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3677 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3678 Requires<[IsARM, HasV5TE]>;
3680 // Helper class for AI_smld.
3681 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3682 InstrItinClass itin, string opc, string asm>
3683 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3686 let Inst{27-23} = 0b01110;
3687 let Inst{22} = long;
3688 let Inst{21-20} = 0b00;
3689 let Inst{11-8} = Rm;
3696 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3697 InstrItinClass itin, string opc, string asm>
3698 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3700 let Inst{15-12} = 0b1111;
3701 let Inst{19-16} = Rd;
3703 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3704 InstrItinClass itin, string opc, string asm>
3705 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3708 let Inst{19-16} = Rd;
3709 let Inst{15-12} = Ra;
3711 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3712 InstrItinClass itin, string opc, string asm>
3713 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3716 let Inst{19-16} = RdHi;
3717 let Inst{15-12} = RdLo;
3720 multiclass AI_smld<bit sub, string opc> {
3722 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3723 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3724 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3726 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3727 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3728 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3730 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3731 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3732 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3734 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3735 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3736 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3740 defm SMLA : AI_smld<0, "smla">;
3741 defm SMLS : AI_smld<1, "smls">;
3743 multiclass AI_sdml<bit sub, string opc> {
3745 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3746 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3747 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3748 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3751 defm SMUA : AI_sdml<0, "smua">;
3752 defm SMUS : AI_sdml<1, "smus">;
3754 //===----------------------------------------------------------------------===//
3755 // Misc. Arithmetic Instructions.
3758 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3759 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3760 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3762 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3763 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3764 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3765 Requires<[IsARM, HasV6T2]>;
3767 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3768 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3769 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3771 let AddedComplexity = 5 in
3772 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3773 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3774 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3775 Requires<[IsARM, HasV6]>;
3777 let AddedComplexity = 5 in
3778 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3779 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3780 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3781 Requires<[IsARM, HasV6]>;
3783 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3784 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3787 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3788 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3789 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3790 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3791 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3793 Requires<[IsARM, HasV6]>;
3795 // Alternate cases for PKHBT where identities eliminate some nodes.
3796 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3797 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3798 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3799 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3801 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3802 // will match the pattern below.
3803 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3804 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3805 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3806 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3807 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3809 Requires<[IsARM, HasV6]>;
3811 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3812 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3813 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3814 (srl GPRnopc:$src2, imm16_31:$sh)),
3815 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3816 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3817 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3818 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3820 //===----------------------------------------------------------------------===//
3821 // Comparison Instructions...
3824 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3825 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3826 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3828 // ARMcmpZ can re-use the above instruction definitions.
3829 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3830 (CMPri GPR:$src, so_imm:$imm)>;
3831 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3832 (CMPrr GPR:$src, GPR:$rhs)>;
3833 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3834 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3835 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3836 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3838 // FIXME: We have to be careful when using the CMN instruction and comparison
3839 // with 0. One would expect these two pieces of code should give identical
3855 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3856 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3857 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3858 // value of r0 and the carry bit (because the "carry bit" parameter to
3859 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3860 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3861 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3862 // parameter to AddWithCarry is defined as 0).
3864 // When x is 0 and unsigned:
3868 // ~x + 1 = 0x1 0000 0000
3869 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3871 // Therefore, we should disable CMN when comparing against zero, until we can
3872 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3873 // when it's a comparison which doesn't look at the 'carry' flag).
3875 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3877 // This is related to <rdar://problem/7569620>.
3879 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3880 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3882 // Note that TST/TEQ don't set all the same flags that CMP does!
3883 defm TST : AI1_cmp_irs<0b1000, "tst",
3884 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3885 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3886 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3887 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3888 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3890 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3891 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3892 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3894 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3895 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3897 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3898 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3900 // Pseudo i64 compares for some floating point compares.
3901 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3903 def BCCi64 : PseudoInst<(outs),
3904 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3906 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3908 def BCCZi64 : PseudoInst<(outs),
3909 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3910 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3911 } // usesCustomInserter
3914 // Conditional moves
3915 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3916 // a two-value operand where a dag node expects two operands. :(
3917 let neverHasSideEffects = 1 in {
3919 let isCommutable = 1 in
3920 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3922 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3923 RegConstraint<"$false = $Rd">;
3925 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3926 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3928 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3929 imm:$cc, CCR:$ccr))*/]>,
3930 RegConstraint<"$false = $Rd">;
3931 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3932 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3934 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3935 imm:$cc, CCR:$ccr))*/]>,
3936 RegConstraint<"$false = $Rd">;
3939 let isMoveImm = 1 in
3940 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3941 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3944 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3946 let isMoveImm = 1 in
3947 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3948 (ins GPR:$false, so_imm:$imm, pred:$p),
3950 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3951 RegConstraint<"$false = $Rd">;
3953 // Two instruction predicate mov immediate.
3954 let isMoveImm = 1 in
3955 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3956 (ins GPR:$false, i32imm:$src, pred:$p),
3957 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3959 let isMoveImm = 1 in
3960 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3961 (ins GPR:$false, so_imm:$imm, pred:$p),
3963 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3964 RegConstraint<"$false = $Rd">;
3966 // Conditional instructions
3967 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3969 InstrItinClass iii, InstrItinClass iir,
3970 InstrItinClass iis> {
3971 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3972 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
3974 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
3975 RegConstraint<"$Rn = $Rd">;
3976 def rr : ARMPseudoExpand<(outs GPR:$Rd),
3977 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3979 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3980 RegConstraint<"$Rn = $Rd">;
3981 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
3982 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
3984 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
3985 RegConstraint<"$Rn = $Rd">;
3986 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
3987 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
3989 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
3990 RegConstraint<"$Rn = $Rd">;
3993 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
3994 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
3995 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
3996 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
3997 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
3998 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4000 } // neverHasSideEffects
4003 //===----------------------------------------------------------------------===//
4004 // Atomic operations intrinsics
4007 def MemBarrierOptOperand : AsmOperandClass {
4008 let Name = "MemBarrierOpt";
4009 let ParserMethod = "parseMemBarrierOptOperand";
4011 def memb_opt : Operand<i32> {
4012 let PrintMethod = "printMemBOption";
4013 let ParserMatchClass = MemBarrierOptOperand;
4014 let DecoderMethod = "DecodeMemBarrierOption";
4017 // memory barriers protect the atomic sequences
4018 let hasSideEffects = 1 in {
4019 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4020 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4021 Requires<[IsARM, HasDB]> {
4023 let Inst{31-4} = 0xf57ff05;
4024 let Inst{3-0} = opt;
4028 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4029 "dsb", "\t$opt", []>,
4030 Requires<[IsARM, HasDB]> {
4032 let Inst{31-4} = 0xf57ff04;
4033 let Inst{3-0} = opt;
4036 // ISB has only full system option
4037 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4038 "isb", "\t$opt", []>,
4039 Requires<[IsARM, HasDB]> {
4041 let Inst{31-4} = 0xf57ff06;
4042 let Inst{3-0} = opt;
4045 // Pseudo instruction that combines movs + predicated rsbmi
4046 // to implement integer ABS
4047 let usesCustomInserter = 1, Defs = [CPSR] in {
4048 def ABS : ARMPseudoInst<
4049 (outs GPR:$dst), (ins GPR:$src),
4050 8, NoItinerary, []>;
4053 let usesCustomInserter = 1 in {
4054 let Defs = [CPSR] in {
4055 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4056 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4057 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4058 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4059 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4060 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4061 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4062 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4063 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4064 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4065 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4066 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4067 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4068 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4069 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4070 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4071 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4072 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4073 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4074 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4075 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4076 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4077 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4078 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4079 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4080 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4081 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4082 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4083 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4084 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4085 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4086 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4087 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4088 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4089 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4090 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4091 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4092 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4093 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4094 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4095 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4096 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4097 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4098 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4099 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4100 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4101 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4102 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4103 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4104 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4105 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4106 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4107 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4108 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4109 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4111 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4112 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4114 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4115 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4117 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4118 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4120 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4121 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4123 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4124 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4126 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4127 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4129 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4130 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4132 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4133 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4135 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4136 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4138 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4139 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4141 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4142 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4144 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4146 def ATOMIC_SWAP_I8 : PseudoInst<
4147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4148 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4149 def ATOMIC_SWAP_I16 : PseudoInst<
4150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4151 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4152 def ATOMIC_SWAP_I32 : PseudoInst<
4153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4154 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4156 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4158 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4159 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4161 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4162 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4164 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4168 let mayLoad = 1 in {
4169 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4171 "ldrexb", "\t$Rt, $addr", []>;
4172 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4173 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4174 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4175 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4176 let hasExtraDefRegAllocReq = 1 in
4177 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4178 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4179 let DecoderMethod = "DecodeDoubleRegLoad";
4183 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4184 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4185 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4186 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4187 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4188 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4189 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4190 let hasExtraSrcRegAllocReq = 1 in
4191 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4192 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4193 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4194 let DecoderMethod = "DecodeDoubleRegStore";
4199 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4200 Requires<[IsARM, HasV7]> {
4201 let Inst{31-0} = 0b11110101011111111111000000011111;
4204 // SWP/SWPB are deprecated in V6/V7.
4205 let mayLoad = 1, mayStore = 1 in {
4206 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4207 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4208 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4209 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4212 //===----------------------------------------------------------------------===//
4213 // Coprocessor Instructions.
4216 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4217 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4218 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4219 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4220 imm:$CRm, imm:$opc2)]> {
4228 let Inst{3-0} = CRm;
4230 let Inst{7-5} = opc2;
4231 let Inst{11-8} = cop;
4232 let Inst{15-12} = CRd;
4233 let Inst{19-16} = CRn;
4234 let Inst{23-20} = opc1;
4237 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4238 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4239 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4240 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4241 imm:$CRm, imm:$opc2)]> {
4242 let Inst{31-28} = 0b1111;
4250 let Inst{3-0} = CRm;
4252 let Inst{7-5} = opc2;
4253 let Inst{11-8} = cop;
4254 let Inst{15-12} = CRd;
4255 let Inst{19-16} = CRn;
4256 let Inst{23-20} = opc1;
4259 class ACI<dag oops, dag iops, string opc, string asm,
4260 IndexMode im = IndexModeNone>
4261 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4263 let Inst{27-25} = 0b110;
4265 class ACInoP<dag oops, dag iops, string opc, string asm,
4266 IndexMode im = IndexModeNone>
4267 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4269 let Inst{31-28} = 0b1111;
4270 let Inst{27-25} = 0b110;
4272 multiclass LdStCop<bit load, bit Dbit, string asm> {
4273 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4274 asm, "\t$cop, $CRd, $addr"> {
4278 let Inst{24} = 1; // P = 1
4279 let Inst{23} = addr{8};
4280 let Inst{22} = Dbit;
4281 let Inst{21} = 0; // W = 0
4282 let Inst{20} = load;
4283 let Inst{19-16} = addr{12-9};
4284 let Inst{15-12} = CRd;
4285 let Inst{11-8} = cop;
4286 let Inst{7-0} = addr{7-0};
4287 let DecoderMethod = "DecodeCopMemInstruction";
4289 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4290 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4294 let Inst{24} = 1; // P = 1
4295 let Inst{23} = addr{8};
4296 let Inst{22} = Dbit;
4297 let Inst{21} = 1; // W = 1
4298 let Inst{20} = load;
4299 let Inst{19-16} = addr{12-9};
4300 let Inst{15-12} = CRd;
4301 let Inst{11-8} = cop;
4302 let Inst{7-0} = addr{7-0};
4303 let DecoderMethod = "DecodeCopMemInstruction";
4305 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4306 postidx_imm8s4:$offset),
4307 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4312 let Inst{24} = 0; // P = 0
4313 let Inst{23} = offset{8};
4314 let Inst{22} = Dbit;
4315 let Inst{21} = 1; // W = 1
4316 let Inst{20} = load;
4317 let Inst{19-16} = addr;
4318 let Inst{15-12} = CRd;
4319 let Inst{11-8} = cop;
4320 let Inst{7-0} = offset{7-0};
4321 let DecoderMethod = "DecodeCopMemInstruction";
4323 def _OPTION : ACI<(outs),
4324 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4325 coproc_option_imm:$option),
4326 asm, "\t$cop, $CRd, $addr, $option"> {
4331 let Inst{24} = 0; // P = 0
4332 let Inst{23} = 1; // U = 1
4333 let Inst{22} = Dbit;
4334 let Inst{21} = 0; // W = 0
4335 let Inst{20} = load;
4336 let Inst{19-16} = addr;
4337 let Inst{15-12} = CRd;
4338 let Inst{11-8} = cop;
4339 let Inst{7-0} = option;
4340 let DecoderMethod = "DecodeCopMemInstruction";
4343 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4344 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4345 asm, "\t$cop, $CRd, $addr"> {
4349 let Inst{24} = 1; // P = 1
4350 let Inst{23} = addr{8};
4351 let Inst{22} = Dbit;
4352 let Inst{21} = 0; // W = 0
4353 let Inst{20} = load;
4354 let Inst{19-16} = addr{12-9};
4355 let Inst{15-12} = CRd;
4356 let Inst{11-8} = cop;
4357 let Inst{7-0} = addr{7-0};
4358 let DecoderMethod = "DecodeCopMemInstruction";
4360 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4361 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4365 let Inst{24} = 1; // P = 1
4366 let Inst{23} = addr{8};
4367 let Inst{22} = Dbit;
4368 let Inst{21} = 1; // W = 1
4369 let Inst{20} = load;
4370 let Inst{19-16} = addr{12-9};
4371 let Inst{15-12} = CRd;
4372 let Inst{11-8} = cop;
4373 let Inst{7-0} = addr{7-0};
4374 let DecoderMethod = "DecodeCopMemInstruction";
4376 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4377 postidx_imm8s4:$offset),
4378 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4383 let Inst{24} = 0; // P = 0
4384 let Inst{23} = offset{8};
4385 let Inst{22} = Dbit;
4386 let Inst{21} = 1; // W = 1
4387 let Inst{20} = load;
4388 let Inst{19-16} = addr;
4389 let Inst{15-12} = CRd;
4390 let Inst{11-8} = cop;
4391 let Inst{7-0} = offset{7-0};
4392 let DecoderMethod = "DecodeCopMemInstruction";
4394 def _OPTION : ACInoP<(outs),
4395 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4396 coproc_option_imm:$option),
4397 asm, "\t$cop, $CRd, $addr, $option"> {
4402 let Inst{24} = 0; // P = 0
4403 let Inst{23} = 1; // U = 1
4404 let Inst{22} = Dbit;
4405 let Inst{21} = 0; // W = 0
4406 let Inst{20} = load;
4407 let Inst{19-16} = addr;
4408 let Inst{15-12} = CRd;
4409 let Inst{11-8} = cop;
4410 let Inst{7-0} = option;
4411 let DecoderMethod = "DecodeCopMemInstruction";
4415 defm LDC : LdStCop <1, 0, "ldc">;
4416 defm LDCL : LdStCop <1, 1, "ldcl">;
4417 defm STC : LdStCop <0, 0, "stc">;
4418 defm STCL : LdStCop <0, 1, "stcl">;
4419 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4420 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4421 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4422 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4424 //===----------------------------------------------------------------------===//
4425 // Move between coprocessor and ARM core register.
4428 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4430 : ABI<0b1110, oops, iops, NoItinerary, opc,
4431 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4432 let Inst{20} = direction;
4442 let Inst{15-12} = Rt;
4443 let Inst{11-8} = cop;
4444 let Inst{23-21} = opc1;
4445 let Inst{7-5} = opc2;
4446 let Inst{3-0} = CRm;
4447 let Inst{19-16} = CRn;
4450 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4452 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4453 c_imm:$CRm, imm0_7:$opc2),
4454 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4455 imm:$CRm, imm:$opc2)]>;
4456 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4457 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4458 c_imm:$CRm, 0, pred:$p)>;
4459 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4461 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4463 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4464 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4465 c_imm:$CRm, 0, pred:$p)>;
4467 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4468 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4470 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4472 : ABXI<0b1110, oops, iops, NoItinerary,
4473 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4474 let Inst{31-28} = 0b1111;
4475 let Inst{20} = direction;
4485 let Inst{15-12} = Rt;
4486 let Inst{11-8} = cop;
4487 let Inst{23-21} = opc1;
4488 let Inst{7-5} = opc2;
4489 let Inst{3-0} = CRm;
4490 let Inst{19-16} = CRn;
4493 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4495 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4496 c_imm:$CRm, imm0_7:$opc2),
4497 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4498 imm:$CRm, imm:$opc2)]>;
4499 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4500 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4502 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4504 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4506 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4507 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4510 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4511 imm:$CRm, imm:$opc2),
4512 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4514 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4515 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4516 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4517 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4518 let Inst{23-21} = 0b010;
4519 let Inst{20} = direction;
4527 let Inst{15-12} = Rt;
4528 let Inst{19-16} = Rt2;
4529 let Inst{11-8} = cop;
4530 let Inst{7-4} = opc1;
4531 let Inst{3-0} = CRm;
4534 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4535 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4536 GPRnopc:$Rt2, imm:$CRm)]>;
4537 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4539 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4540 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4541 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4542 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4543 let Inst{31-28} = 0b1111;
4544 let Inst{23-21} = 0b010;
4545 let Inst{20} = direction;
4553 let Inst{15-12} = Rt;
4554 let Inst{19-16} = Rt2;
4555 let Inst{11-8} = cop;
4556 let Inst{7-4} = opc1;
4557 let Inst{3-0} = CRm;
4559 let DecoderMethod = "DecodeMRRC2";
4562 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4563 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4564 GPRnopc:$Rt2, imm:$CRm)]>;
4565 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4567 //===----------------------------------------------------------------------===//
4568 // Move between special register and ARM core register
4571 // Move to ARM core register from Special Register
4572 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4573 "mrs", "\t$Rd, apsr", []> {
4575 let Inst{23-16} = 0b00001111;
4576 let Unpredictable{19-17} = 0b111;
4578 let Inst{15-12} = Rd;
4580 let Inst{11-0} = 0b000000000000;
4581 let Unpredictable{11-0} = 0b110100001111;
4584 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4587 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4588 // section B9.3.9, with the R bit set to 1.
4589 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4590 "mrs", "\t$Rd, spsr", []> {
4592 let Inst{23-16} = 0b01001111;
4593 let Unpredictable{19-16} = 0b1111;
4595 let Inst{15-12} = Rd;
4597 let Inst{11-0} = 0b000000000000;
4598 let Unpredictable{11-0} = 0b110100001111;
4601 // Move from ARM core register to Special Register
4603 // No need to have both system and application versions, the encodings are the
4604 // same and the assembly parser has no way to distinguish between them. The mask
4605 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4606 // the mask with the fields to be accessed in the special register.
4607 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4608 "msr", "\t$mask, $Rn", []> {
4613 let Inst{22} = mask{4}; // R bit
4614 let Inst{21-20} = 0b10;
4615 let Inst{19-16} = mask{3-0};
4616 let Inst{15-12} = 0b1111;
4617 let Inst{11-4} = 0b00000000;
4621 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4622 "msr", "\t$mask, $a", []> {
4627 let Inst{22} = mask{4}; // R bit
4628 let Inst{21-20} = 0b10;
4629 let Inst{19-16} = mask{3-0};
4630 let Inst{15-12} = 0b1111;
4634 //===----------------------------------------------------------------------===//
4638 // __aeabi_read_tp preserves the registers r1-r3.
4639 // This is a pseudo inst so that we can get the encoding right,
4640 // complete with fixup for the aeabi_read_tp function.
4642 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4643 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4644 [(set R0, ARMthread_pointer)]>;
4647 //===----------------------------------------------------------------------===//
4648 // SJLJ Exception handling intrinsics
4649 // eh_sjlj_setjmp() is an instruction sequence to store the return
4650 // address and save #0 in R0 for the non-longjmp case.
4651 // Since by its nature we may be coming from some other function to get
4652 // here, and we're using the stack frame for the containing function to
4653 // save/restore registers, we can't keep anything live in regs across
4654 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4655 // when we get here from a longjmp(). We force everything out of registers
4656 // except for our own input by listing the relevant registers in Defs. By
4657 // doing so, we also cause the prologue/epilogue code to actively preserve
4658 // all of the callee-saved resgisters, which is exactly what we want.
4659 // A constant value is passed in $val, and we use the location as a scratch.
4661 // These are pseudo-instructions and are lowered to individual MC-insts, so
4662 // no encoding information is necessary.
4664 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4665 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4666 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4667 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4669 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4670 Requires<[IsARM, HasVFP2]>;
4674 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4675 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4676 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4678 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4679 Requires<[IsARM, NoVFP]>;
4682 // FIXME: Non-IOS version(s)
4683 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4684 Defs = [ R7, LR, SP ] in {
4685 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4687 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4688 Requires<[IsARM, IsIOS]>;
4691 // eh.sjlj.dispatchsetup pseudo-instructions.
4692 // These pseudos are used for both ARM and Thumb2. Any differences are
4693 // handled when the pseudo is expanded (which happens before any passes
4694 // that need the instruction size).
4696 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4697 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4699 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4702 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4704 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4707 //===----------------------------------------------------------------------===//
4708 // Non-Instruction Patterns
4711 // ARMv4 indirect branch using (MOVr PC, dst)
4712 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4713 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4714 4, IIC_Br, [(brind GPR:$dst)],
4715 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4716 Requires<[IsARM, NoV4T]>;
4718 // Large immediate handling.
4720 // 32-bit immediate using two piece so_imms or movw + movt.
4721 // This is a single pseudo instruction, the benefit is that it can be remat'd
4722 // as a single unit instead of having to handle reg inputs.
4723 // FIXME: Remove this when we can do generalized remat.
4724 let isReMaterializable = 1, isMoveImm = 1 in
4725 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4726 [(set GPR:$dst, (arm_i32imm:$src))]>,
4729 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4730 // It also makes it possible to rematerialize the instructions.
4731 // FIXME: Remove this when we can do generalized remat and when machine licm
4732 // can properly the instructions.
4733 let isReMaterializable = 1 in {
4734 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4736 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4737 Requires<[IsARM, UseMovt]>;
4739 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4741 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4742 Requires<[IsARM, UseMovt]>;
4744 let AddedComplexity = 10 in
4745 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4747 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4748 Requires<[IsARM, UseMovt]>;
4749 } // isReMaterializable
4751 // ConstantPool, GlobalAddress, and JumpTable
4752 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4753 Requires<[IsARM, DontUseMovt]>;
4754 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4755 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4756 Requires<[IsARM, UseMovt]>;
4757 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4758 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4760 // TODO: add,sub,and, 3-instr forms?
4762 // Tail calls. These patterns also apply to Thumb mode.
4763 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4764 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4765 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4768 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4769 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4770 (BMOVPCB_CALL texternalsym:$func)>;
4772 // zextload i1 -> zextload i8
4773 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4774 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4776 // extload -> zextload
4777 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4778 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4779 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4780 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4782 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4784 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4785 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4788 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4789 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4790 (SMULBB GPR:$a, GPR:$b)>;
4791 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4792 (SMULBB GPR:$a, GPR:$b)>;
4793 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4794 (sra GPR:$b, (i32 16))),
4795 (SMULBT GPR:$a, GPR:$b)>;
4796 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4797 (SMULBT GPR:$a, GPR:$b)>;
4798 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4799 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4800 (SMULTB GPR:$a, GPR:$b)>;
4801 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4802 (SMULTB GPR:$a, GPR:$b)>;
4803 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4805 (SMULWB GPR:$a, GPR:$b)>;
4806 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4807 (SMULWB GPR:$a, GPR:$b)>;
4809 def : ARMV5TEPat<(add GPR:$acc,
4810 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4811 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4812 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4813 def : ARMV5TEPat<(add GPR:$acc,
4814 (mul sext_16_node:$a, sext_16_node:$b)),
4815 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4816 def : ARMV5TEPat<(add GPR:$acc,
4817 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4818 (sra GPR:$b, (i32 16)))),
4819 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4820 def : ARMV5TEPat<(add GPR:$acc,
4821 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4822 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4823 def : ARMV5TEPat<(add GPR:$acc,
4824 (mul (sra GPR:$a, (i32 16)),
4825 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4826 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4827 def : ARMV5TEPat<(add GPR:$acc,
4828 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4829 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4830 def : ARMV5TEPat<(add GPR:$acc,
4831 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4833 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4834 def : ARMV5TEPat<(add GPR:$acc,
4835 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4836 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4839 // Pre-v7 uses MCR for synchronization barriers.
4840 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4841 Requires<[IsARM, HasV6]>;
4843 // SXT/UXT with no rotate
4844 let AddedComplexity = 16 in {
4845 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4846 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4847 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4848 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4849 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4850 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4851 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4854 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4855 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4857 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4858 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4859 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4860 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4862 // Atomic load/store patterns
4863 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4864 (LDRBrs ldst_so_reg:$src)>;
4865 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4866 (LDRBi12 addrmode_imm12:$src)>;
4867 def : ARMPat<(atomic_load_16 addrmode3:$src),
4868 (LDRH addrmode3:$src)>;
4869 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4870 (LDRrs ldst_so_reg:$src)>;
4871 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4872 (LDRi12 addrmode_imm12:$src)>;
4873 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4874 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4875 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4876 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4877 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4878 (STRH GPR:$val, addrmode3:$ptr)>;
4879 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4880 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4881 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4882 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4885 //===----------------------------------------------------------------------===//
4889 include "ARMInstrThumb.td"
4891 //===----------------------------------------------------------------------===//
4895 include "ARMInstrThumb2.td"
4897 //===----------------------------------------------------------------------===//
4898 // Floating Point Support
4901 include "ARMInstrVFP.td"
4903 //===----------------------------------------------------------------------===//
4904 // Advanced SIMD (NEON) Support
4907 include "ARMInstrNEON.td"
4909 //===----------------------------------------------------------------------===//
4910 // Assembler aliases
4914 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4915 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4916 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4918 // System instructions
4919 def : MnemonicAlias<"swi", "svc">;
4921 // Load / Store Multiple
4922 def : MnemonicAlias<"ldmfd", "ldm">;
4923 def : MnemonicAlias<"ldmia", "ldm">;
4924 def : MnemonicAlias<"ldmea", "ldmdb">;
4925 def : MnemonicAlias<"stmfd", "stmdb">;
4926 def : MnemonicAlias<"stmia", "stm">;
4927 def : MnemonicAlias<"stmea", "stm">;
4929 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4930 // shift amount is zero (i.e., unspecified).
4931 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4932 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4933 Requires<[IsARM, HasV6]>;
4934 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4935 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4936 Requires<[IsARM, HasV6]>;
4938 // PUSH/POP aliases for STM/LDM
4939 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4940 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4942 // SSAT/USAT optional shift operand.
4943 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4944 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4945 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4946 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4949 // Extend instruction optional rotate operand.
4950 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4951 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4952 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4953 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4954 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4955 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4956 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4957 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4958 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4959 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4960 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4961 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4963 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4964 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4965 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4966 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4967 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4968 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4969 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4970 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4971 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4972 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4973 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4974 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4978 def : MnemonicAlias<"rfefa", "rfeda">;
4979 def : MnemonicAlias<"rfeea", "rfedb">;
4980 def : MnemonicAlias<"rfefd", "rfeia">;
4981 def : MnemonicAlias<"rfeed", "rfeib">;
4982 def : MnemonicAlias<"rfe", "rfeia">;
4985 def : MnemonicAlias<"srsfa", "srsda">;
4986 def : MnemonicAlias<"srsea", "srsdb">;
4987 def : MnemonicAlias<"srsfd", "srsia">;
4988 def : MnemonicAlias<"srsed", "srsib">;
4989 def : MnemonicAlias<"srs", "srsia">;
4992 def : MnemonicAlias<"qsubaddx", "qsax">;
4994 def : MnemonicAlias<"saddsubx", "sasx">;
4995 // SHASX == SHADDSUBX
4996 def : MnemonicAlias<"shaddsubx", "shasx">;
4997 // SHSAX == SHSUBADDX
4998 def : MnemonicAlias<"shsubaddx", "shsax">;
5000 def : MnemonicAlias<"ssubaddx", "ssax">;
5002 def : MnemonicAlias<"uaddsubx", "uasx">;
5003 // UHASX == UHADDSUBX
5004 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5005 // UHSAX == UHSUBADDX
5006 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5007 // UQASX == UQADDSUBX
5008 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5009 // UQSAX == UQSUBADDX
5010 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5012 def : MnemonicAlias<"usubaddx", "usax">;
5014 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5016 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5017 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5018 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5019 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5020 // Same for AND <--> BIC
5021 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5022 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5023 pred:$p, cc_out:$s)>;
5024 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5025 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5026 pred:$p, cc_out:$s)>;
5027 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5028 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5029 pred:$p, cc_out:$s)>;
5030 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5031 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5032 pred:$p, cc_out:$s)>;
5034 // Likewise, "add Rd, so_imm_neg" -> sub
5035 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5036 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5037 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5038 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5039 // Same for CMP <--> CMN via so_imm_neg
5040 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5041 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5042 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5043 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5045 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5046 // LSR, ROR, and RRX instructions.
5047 // FIXME: We need C++ parser hooks to map the alias to the MOV
5048 // encoding. It seems we should be able to do that sort of thing
5049 // in tblgen, but it could get ugly.
5050 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5051 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5052 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5054 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5055 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5057 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5058 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5060 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5061 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5064 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5065 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5066 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5067 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5068 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5070 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5071 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5073 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5074 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5076 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5077 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5081 // "neg" is and alias for "rsb rd, rn, #0"
5082 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5083 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5085 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5086 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5087 Requires<[IsARM, NoV6]>;
5089 // UMULL/SMULL are available on all arches, but the instruction definitions
5090 // need difference constraints pre-v6. Use these aliases for the assembly
5091 // parsing on pre-v6.
5092 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5093 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5094 Requires<[IsARM, NoV6]>;
5095 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5096 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5097 Requires<[IsARM, NoV6]>;
5099 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5101 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;