1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107 def HasNEON : Predicate<"Subtarget->hasNEON()">;
108 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110 def IsThumb : Predicate<"Subtarget->isThumb()">;
111 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113 def IsARM : Predicate<"!Subtarget->isThumb()">;
114 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
119 //===----------------------------------------------------------------------===//
120 // ARM Flag Definitions.
122 class RegConstraint<string C> {
123 string Constraints = C;
126 //===----------------------------------------------------------------------===//
127 // ARM specific transformation functions and pattern fragments.
130 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131 // so_imm_neg def below.
132 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
136 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
137 // so_imm_not def below.
138 def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
142 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143 def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
148 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149 def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
153 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154 def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
168 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
173 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
175 def bf_inv_mask_imm : Operand<i32>,
177 uint32_t v = (uint32_t)N->getZExtValue();
180 // there can be 1's on either or both "outsides", all the "inside"
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
194 /// Split a 32-bit immediate into two 16 bit parts.
195 def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
200 def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
204 def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
209 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
211 def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
215 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
218 //===----------------------------------------------------------------------===//
219 // Operand Definitions.
223 def brtarget : Operand<OtherVT>;
225 // A list of registers separated by comma. Used by load/store multiple.
226 def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
230 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231 def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
235 def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
238 def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
243 def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
247 // shifter_operand operands: so_reg and so_imm.
248 def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
255 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257 // represented in the imm field in the same 12-bit form that they are encoded
258 // into so_imm instructions: the 8-bit immediate is the least significant bits
259 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260 def so_imm : Operand<i32>,
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
264 let PrintMethod = "printSOImmOperand";
267 // Break so_imm's up into two pieces. This handles immediates with up to 16
268 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269 // get the first/second pieces.
270 def so_imm2part : Operand<i32>,
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
274 let PrintMethod = "printSOImm2PartOperand";
277 def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
282 def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
287 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
292 // Define ARM specific addressing modes.
294 // addrmode2 := reg +/- reg shop imm
295 // addrmode2 := reg +/- imm12
297 def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
303 def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
309 // addrmode3 := reg +/- reg
310 // addrmode3 := reg +/- imm8
312 def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
318 def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
324 // addrmode4 := reg, <mode|W>
326 def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
332 // addrmode5 := reg +/- imm8*4
334 def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
340 // addrmode6 := reg with optional writeback
342 def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
348 // addrmodepc := pc + reg
350 def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
356 def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
360 //===----------------------------------------------------------------------===//
362 include "ARMInstrFormats.td"
364 //===----------------------------------------------------------------------===//
365 // Multiclass helpers...
368 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369 /// binop that produces a value.
370 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, " $dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, " $dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
382 let isCommutable = Commutable;
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, " $dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
393 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
394 /// instruction modifies the CPSR register.
395 let Defs = [CPSR] in {
396 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
397 bit Commutable = 0> {
398 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
399 IIC_iALUi, opc, "s $dst, $a, $b",
400 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
403 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
404 IIC_iALUr, opc, "s $dst, $a, $b",
405 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
406 let isCommutable = Commutable;
410 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
411 IIC_iALUsr, opc, "s $dst, $a, $b",
412 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
420 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
421 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
422 /// a explicit result, only implicitly set CPSR.
423 let Defs = [CPSR] in {
424 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
425 bit Commutable = 0> {
426 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
428 [(opnode GPR:$a, so_imm:$b)]> {
432 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
434 [(opnode GPR:$a, GPR:$b)]> {
438 let isCommutable = Commutable;
440 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
442 [(opnode GPR:$a, so_reg:$b)]> {
451 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
452 /// register and one whose operand is a register rotated by 8/16/24.
453 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
454 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
455 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
456 IIC_iUNAr, opc, " $dst, $src",
457 [(set GPR:$dst, (opnode GPR:$src))]>,
458 Requires<[IsARM, HasV6]> {
459 let Inst{19-16} = 0b1111;
461 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
462 IIC_iUNAsi, opc, " $dst, $src, ror $rot",
463 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
464 Requires<[IsARM, HasV6]> {
465 let Inst{19-16} = 0b1111;
469 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
470 /// register and one whose operand is a register rotated by 8/16/24.
471 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
472 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
473 IIC_iALUr, opc, " $dst, $LHS, $RHS",
474 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
475 Requires<[IsARM, HasV6]>;
476 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
477 IIC_iALUsi, opc, " $dst, $LHS, $RHS, ror $rot",
478 [(set GPR:$dst, (opnode GPR:$LHS,
479 (rotr GPR:$RHS, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
483 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
484 let Uses = [CPSR] in {
485 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
486 bit Commutable = 0> {
487 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
488 DPFrm, IIC_iALUi, opc, " $dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
490 Requires<[IsARM, CarryDefIsUnused]> {
493 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
494 DPFrm, IIC_iALUr, opc, " $dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
497 let isCommutable = Commutable;
501 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
502 DPSoRegFrm, IIC_iALUsr, opc, " $dst, $a, $b",
503 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
504 Requires<[IsARM, CarryDefIsUnused]> {
509 // Carry setting variants
510 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
511 DPFrm, IIC_iALUi, !strconcat(opc, "s $dst, $a, $b"),
512 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
513 Requires<[IsARM, CarryDefIsUsed]> {
517 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
518 DPFrm, IIC_iALUr, !strconcat(opc, "s $dst, $a, $b"),
519 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
520 Requires<[IsARM, CarryDefIsUsed]> {
525 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
526 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s $dst, $a, $b"),
527 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
528 Requires<[IsARM, CarryDefIsUsed]> {
537 //===----------------------------------------------------------------------===//
539 //===----------------------------------------------------------------------===//
541 //===----------------------------------------------------------------------===//
542 // Miscellaneous Instructions.
545 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
546 /// the function. The first operand is the ID# for this instruction, the second
547 /// is the index into the MachineConstantPool that this is, the third is the
548 /// size in bytes of this constant pool entry.
549 let neverHasSideEffects = 1, isNotDuplicable = 1 in
550 def CONSTPOOL_ENTRY :
551 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
552 i32imm:$size), NoItinerary,
553 "${instid:label} ${cpidx:cpentry}", []>;
555 let Defs = [SP], Uses = [SP] in {
557 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
558 "@ ADJCALLSTACKUP $amt1",
559 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
561 def ADJCALLSTACKDOWN :
562 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
563 "@ ADJCALLSTACKDOWN $amt",
564 [(ARMcallseq_start timm:$amt)]>;
568 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
569 ".loc $file, $line, $col",
570 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
573 // Address computation and loads and stores in PIC mode.
574 let isNotDuplicable = 1 in {
575 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
576 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p $dst, pc, $a",
577 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
579 let AddedComplexity = 10 in {
580 let canFoldAsLoad = 1 in
581 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
582 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p $dst, $addr",
583 [(set GPR:$dst, (load addrmodepc:$addr))]>;
585 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
586 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h $dst, $addr",
587 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
589 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
590 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b $dst, $addr",
591 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
593 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
594 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh $dst, $addr",
595 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
597 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
598 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb $dst, $addr",
599 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
601 let AddedComplexity = 10 in {
602 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
603 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p $src, $addr",
604 [(store GPR:$src, addrmodepc:$addr)]>;
606 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h $src, $addr",
608 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
610 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
611 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b $src, $addr",
612 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
614 } // isNotDuplicable = 1
617 // LEApcrel - Load a pc-relative address into a register without offending the
619 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
621 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
622 "${:private}PCRELL${:uid}+8))\n"),
623 !strconcat("${:private}PCRELL${:uid}:\n\t",
624 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
627 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
628 (ins i32imm:$label, nohash_imm:$id, pred:$p),
630 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
632 "${:private}PCRELL${:uid}+8))\n"),
633 !strconcat("${:private}PCRELL${:uid}:\n\t",
634 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
639 //===----------------------------------------------------------------------===//
640 // Control Flow Instructions.
643 let isReturn = 1, isTerminator = 1, isBarrier = 1 in
644 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
645 "bx", " lr", [(ARMretflag)]> {
646 let Inst{7-4} = 0b0001;
647 let Inst{19-8} = 0b111111111111;
648 let Inst{27-20} = 0b00010010;
651 // FIXME: remove when we have a way to marking a MI with these properties.
652 // FIXME: Should pc be an implicit operand like PICADD, etc?
653 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
654 hasExtraDefRegAllocReq = 1 in
655 def LDM_RET : AXI4ld<(outs),
656 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
657 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
660 // On non-Darwin platforms R9 is callee-saved.
662 Defs = [R0, R1, R2, R3, R12, LR,
663 D0, D1, D2, D3, D4, D5, D6, D7,
664 D16, D17, D18, D19, D20, D21, D22, D23,
665 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
666 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
667 IIC_Br, "bl ${func:call}",
668 [(ARMcall tglobaladdr:$func)]>,
669 Requires<[IsARM, IsNotDarwin]>;
671 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
672 IIC_Br, "bl", " ${func:call}",
673 [(ARMcall_pred tglobaladdr:$func)]>,
674 Requires<[IsARM, IsNotDarwin]>;
677 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
679 [(ARMcall GPR:$func)]>,
680 Requires<[IsARM, HasV5T, IsNotDarwin]> {
681 let Inst{7-4} = 0b0011;
682 let Inst{19-8} = 0b111111111111;
683 let Inst{27-20} = 0b00010010;
687 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
688 IIC_Br, "mov lr, pc\n\tbx $func",
689 [(ARMcall_nolink GPR:$func)]>,
690 Requires<[IsARM, IsNotDarwin]> {
691 let Inst{7-4} = 0b0001;
692 let Inst{19-8} = 0b111111111111;
693 let Inst{27-20} = 0b00010010;
697 // On Darwin R9 is call-clobbered.
699 Defs = [R0, R1, R2, R3, R9, R12, LR,
700 D0, D1, D2, D3, D4, D5, D6, D7,
701 D16, D17, D18, D19, D20, D21, D22, D23,
702 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
703 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
704 IIC_Br, "bl ${func:call}",
705 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
707 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
708 IIC_Br, "bl", " ${func:call}",
709 [(ARMcall_pred tglobaladdr:$func)]>,
710 Requires<[IsARM, IsDarwin]>;
713 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
715 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
716 let Inst{7-4} = 0b0011;
717 let Inst{19-8} = 0b111111111111;
718 let Inst{27-20} = 0b00010010;
722 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
723 IIC_Br, "mov lr, pc\n\tbx $func",
724 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
725 let Inst{7-4} = 0b0001;
726 let Inst{19-8} = 0b111111111111;
727 let Inst{27-20} = 0b00010010;
731 let isBranch = 1, isTerminator = 1 in {
732 // B is "predicable" since it can be xformed into a Bcc.
733 let isBarrier = 1 in {
734 let isPredicable = 1 in
735 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
736 "b $target", [(br bb:$target)]>;
738 let isNotDuplicable = 1, isIndirectBranch = 1 in {
739 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
740 IIC_Br, "mov pc, $target \n$jt",
741 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
742 let Inst{20} = 0; // S Bit
743 let Inst{24-21} = 0b1101;
744 let Inst{27-25} = 0b000;
746 def BR_JTm : JTI<(outs),
747 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
748 IIC_Br, "ldr pc, $target \n$jt",
749 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
751 let Inst{20} = 1; // L bit
752 let Inst{21} = 0; // W bit
753 let Inst{22} = 0; // B bit
754 let Inst{24} = 1; // P bit
755 let Inst{27-25} = 0b011;
757 def BR_JTadd : JTI<(outs),
758 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
759 IIC_Br, "add pc, $target, $idx \n$jt",
760 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
762 let Inst{20} = 0; // S bit
763 let Inst{24-21} = 0b0100;
764 let Inst{27-25} = 0b000;
766 } // isNotDuplicable = 1, isIndirectBranch = 1
769 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
770 // a two-value operand where a dag node expects two operands. :(
771 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
772 IIC_Br, "b", " $target",
773 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
776 //===----------------------------------------------------------------------===//
777 // Load / store Instructions.
781 let canFoldAsLoad = 1, isReMaterializable = 1 in
782 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
783 "ldr", " $dst, $addr",
784 [(set GPR:$dst, (load addrmode2:$addr))]>;
786 // Special LDR for loads from non-pc-relative constpools.
787 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
788 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
789 "ldr", " $dst, $addr", []>;
791 // Loads with zero extension
792 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
793 IIC_iLoadr, "ldr", "h $dst, $addr",
794 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
796 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
797 IIC_iLoadr, "ldr", "b $dst, $addr",
798 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
800 // Loads with sign extension
801 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
802 IIC_iLoadr, "ldr", "sh $dst, $addr",
803 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
805 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
806 IIC_iLoadr, "ldr", "sb $dst, $addr",
807 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
809 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
811 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
812 IIC_iLoadr, "ldr", "d $dst1, $addr",
813 []>, Requires<[IsARM, HasV5TE]>;
816 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
817 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
818 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
820 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
821 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
822 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
824 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
825 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
826 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
828 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
829 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
830 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
832 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
833 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
834 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
836 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
837 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
838 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
840 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
841 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
842 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
844 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
845 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
846 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
848 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
849 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
850 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
852 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
853 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
854 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
858 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
859 "str", " $src, $addr",
860 [(store GPR:$src, addrmode2:$addr)]>;
862 // Stores with truncate
863 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
864 "str", "h $src, $addr",
865 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
867 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
868 "str", "b $src, $addr",
869 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
872 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
873 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
874 StMiscFrm, IIC_iStorer,
875 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
878 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
879 (ins GPR:$src, GPR:$base, am2offset:$offset),
881 "str", " $src, [$base, $offset]!", "$base = $base_wb",
883 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
885 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
886 (ins GPR:$src, GPR:$base,am2offset:$offset),
888 "str", " $src, [$base], $offset", "$base = $base_wb",
890 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
892 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
893 (ins GPR:$src, GPR:$base,am3offset:$offset),
894 StMiscFrm, IIC_iStoreru,
895 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
897 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
899 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
900 (ins GPR:$src, GPR:$base,am3offset:$offset),
901 StMiscFrm, IIC_iStoreru,
902 "str", "h $src, [$base], $offset", "$base = $base_wb",
903 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
904 GPR:$base, am3offset:$offset))]>;
906 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
907 (ins GPR:$src, GPR:$base,am2offset:$offset),
909 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
910 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
911 GPR:$base, am2offset:$offset))]>;
913 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
914 (ins GPR:$src, GPR:$base,am2offset:$offset),
916 "str", "b $src, [$base], $offset", "$base = $base_wb",
917 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
918 GPR:$base, am2offset:$offset))]>;
920 //===----------------------------------------------------------------------===//
921 // Load / store multiple Instructions.
924 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
925 def LDM : AXI4ld<(outs),
926 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
927 LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
930 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
931 def STM : AXI4st<(outs),
932 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
933 LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
936 //===----------------------------------------------------------------------===//
937 // Move Instructions.
940 let neverHasSideEffects = 1 in
941 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
942 "mov", " $dst, $src", []>, UnaryDP {
947 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
948 DPSoRegFrm, IIC_iMOVsr,
949 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
955 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
956 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
957 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
961 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
962 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
964 "movw", " $dst, $src",
965 [(set GPR:$dst, imm0_65535:$src)]>,
966 Requires<[IsARM, HasV6T2]> {
971 let Constraints = "$src = $dst" in
972 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
974 "movt", " $dst, $imm",
976 (or (and GPR:$src, 0xffff),
977 lo16AllZero:$imm))]>, UnaryDP,
978 Requires<[IsARM, HasV6T2]> {
983 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
984 Requires<[IsARM, HasV6T2]>;
987 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
988 "mov", " $dst, $src, rrx",
989 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
991 // These aren't really mov instructions, but we have to define them this way
992 // due to flag operands.
994 let Defs = [CPSR] in {
995 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
996 IIC_iMOVsi, "mov", "s $dst, $src, lsr #1",
997 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
998 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
999 IIC_iMOVsi, "mov", "s $dst, $src, asr #1",
1000 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1003 //===----------------------------------------------------------------------===//
1004 // Extend Instructions.
1009 defm SXTB : AI_unary_rrot<0b01101010,
1010 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1011 defm SXTH : AI_unary_rrot<0b01101011,
1012 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1014 defm SXTAB : AI_bin_rrot<0b01101010,
1015 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1016 defm SXTAH : AI_bin_rrot<0b01101011,
1017 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1019 // TODO: SXT(A){B|H}16
1023 let AddedComplexity = 16 in {
1024 defm UXTB : AI_unary_rrot<0b01101110,
1025 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1026 defm UXTH : AI_unary_rrot<0b01101111,
1027 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1028 defm UXTB16 : AI_unary_rrot<0b01101100,
1029 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1031 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1032 (UXTB16r_rot GPR:$Src, 24)>;
1033 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1034 (UXTB16r_rot GPR:$Src, 8)>;
1036 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1037 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1038 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1039 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1042 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1043 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1045 // TODO: UXT(A){B|H}16
1047 def SBFX : I<(outs GPR:$dst),
1048 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1049 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1050 "sbfx", " $dst, $src, $lsb, $width", "", []>,
1051 Requires<[IsARM, HasV6T2]> {
1052 let Inst{27-21} = 0b0111101;
1053 let Inst{6-4} = 0b101;
1056 def UBFX : I<(outs GPR:$dst),
1057 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1058 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1059 "ubfx", " $dst, $src, $lsb, $width", "", []>,
1060 Requires<[IsARM, HasV6T2]> {
1061 let Inst{27-21} = 0b0111111;
1062 let Inst{6-4} = 0b101;
1065 //===----------------------------------------------------------------------===//
1066 // Arithmetic Instructions.
1069 defm ADD : AsI1_bin_irs<0b0100, "add",
1070 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1071 defm SUB : AsI1_bin_irs<0b0010, "sub",
1072 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1074 // ADD and SUB with 's' bit set.
1075 defm ADDS : AI1_bin_s_irs<0b0100, "add",
1076 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1077 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
1078 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1080 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1081 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1082 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1083 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1085 // These don't define reg/reg forms, because they are handled above.
1086 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1087 IIC_iALUi, "rsb", " $dst, $a, $b",
1088 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1092 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1093 IIC_iALUsr, "rsb", " $dst, $a, $b",
1094 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1096 // RSB with 's' bit set.
1097 let Defs = [CPSR] in {
1098 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1099 IIC_iALUi, "rsb", "s $dst, $a, $b",
1100 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1103 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1104 IIC_iALUsr, "rsb", "s $dst, $a, $b",
1105 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1108 let Uses = [CPSR] in {
1109 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1110 DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
1111 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1112 Requires<[IsARM, CarryDefIsUnused]> {
1115 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1116 DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
1117 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1118 Requires<[IsARM, CarryDefIsUnused]>;
1121 // FIXME: Allow these to be predicated.
1122 let Defs = [CPSR], Uses = [CPSR] in {
1123 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1124 DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
1125 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1126 Requires<[IsARM, CarryDefIsUnused]> {
1129 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1130 DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
1131 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1132 Requires<[IsARM, CarryDefIsUnused]>;
1135 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1136 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1137 (SUBri GPR:$src, so_imm_neg:$imm)>;
1139 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1140 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1141 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1142 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1144 // Note: These are implemented in C++ code, because they have to generate
1145 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1147 // (mul X, 2^n+1) -> (add (X << n), X)
1148 // (mul X, 2^n-1) -> (rsb X, (X << n))
1151 //===----------------------------------------------------------------------===//
1152 // Bitwise Instructions.
1155 defm AND : AsI1_bin_irs<0b0000, "and",
1156 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1157 defm ORR : AsI1_bin_irs<0b1100, "orr",
1158 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1159 defm EOR : AsI1_bin_irs<0b0001, "eor",
1160 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1161 defm BIC : AsI1_bin_irs<0b1110, "bic",
1162 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1164 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1165 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1166 "bfc", " $dst, $imm", "$src = $dst",
1167 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1168 Requires<[IsARM, HasV6T2]> {
1169 let Inst{27-21} = 0b0111110;
1170 let Inst{6-0} = 0b0011111;
1173 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1174 "mvn", " $dst, $src",
1175 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1178 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1179 IIC_iMOVsr, "mvn", " $dst, $src",
1180 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1184 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1185 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1186 IIC_iMOVi, "mvn", " $dst, $imm",
1187 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1191 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1192 (BICri GPR:$src, so_imm_not:$imm)>;
1194 //===----------------------------------------------------------------------===//
1195 // Multiply Instructions.
1198 let isCommutable = 1 in
1199 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1200 IIC_iMUL32, "mul", " $dst, $a, $b",
1201 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1203 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1204 IIC_iMAC32, "mla", " $dst, $a, $b, $c",
1205 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1207 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1208 IIC_iMAC32, "mls", " $dst, $a, $b, $c",
1209 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1210 Requires<[IsARM, HasV6T2]>;
1212 // Extra precision multiplies with low / high results
1213 let neverHasSideEffects = 1 in {
1214 let isCommutable = 1 in {
1215 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1216 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1217 "smull", " $ldst, $hdst, $a, $b", []>;
1219 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1220 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1221 "umull", " $ldst, $hdst, $a, $b", []>;
1224 // Multiply + accumulate
1225 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1226 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1227 "smlal", " $ldst, $hdst, $a, $b", []>;
1229 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1230 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1231 "umlal", " $ldst, $hdst, $a, $b", []>;
1233 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1234 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1235 "umaal", " $ldst, $hdst, $a, $b", []>,
1236 Requires<[IsARM, HasV6]>;
1237 } // neverHasSideEffects
1239 // Most significant word multiply
1240 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1241 IIC_iMUL32, "smmul", " $dst, $a, $b",
1242 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1243 Requires<[IsARM, HasV6]> {
1244 let Inst{7-4} = 0b0001;
1245 let Inst{15-12} = 0b1111;
1248 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1249 IIC_iMAC32, "smmla", " $dst, $a, $b, $c",
1250 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1251 Requires<[IsARM, HasV6]> {
1252 let Inst{7-4} = 0b0001;
1256 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1257 IIC_iMAC32, "smmls", " $dst, $a, $b, $c",
1258 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1259 Requires<[IsARM, HasV6]> {
1260 let Inst{7-4} = 0b1101;
1263 multiclass AI_smul<string opc, PatFrag opnode> {
1264 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1265 IIC_iMUL32, !strconcat(opc, "bb"), " $dst, $a, $b",
1266 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1267 (sext_inreg GPR:$b, i16)))]>,
1268 Requires<[IsARM, HasV5TE]> {
1273 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1274 IIC_iMUL32, !strconcat(opc, "bt"), " $dst, $a, $b",
1275 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1276 (sra GPR:$b, (i32 16))))]>,
1277 Requires<[IsARM, HasV5TE]> {
1282 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1283 IIC_iMUL32, !strconcat(opc, "tb"), " $dst, $a, $b",
1284 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1285 (sext_inreg GPR:$b, i16)))]>,
1286 Requires<[IsARM, HasV5TE]> {
1291 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1292 IIC_iMUL32, !strconcat(opc, "tt"), " $dst, $a, $b",
1293 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1294 (sra GPR:$b, (i32 16))))]>,
1295 Requires<[IsARM, HasV5TE]> {
1300 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1301 IIC_iMUL16, !strconcat(opc, "wb"), " $dst, $a, $b",
1302 [(set GPR:$dst, (sra (opnode GPR:$a,
1303 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1304 Requires<[IsARM, HasV5TE]> {
1309 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1310 IIC_iMUL16, !strconcat(opc, "wt"), " $dst, $a, $b",
1311 [(set GPR:$dst, (sra (opnode GPR:$a,
1312 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1313 Requires<[IsARM, HasV5TE]> {
1320 multiclass AI_smla<string opc, PatFrag opnode> {
1321 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1322 IIC_iMAC16, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1323 [(set GPR:$dst, (add GPR:$acc,
1324 (opnode (sext_inreg GPR:$a, i16),
1325 (sext_inreg GPR:$b, i16))))]>,
1326 Requires<[IsARM, HasV5TE]> {
1331 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1332 IIC_iMAC16, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1333 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1334 (sra GPR:$b, (i32 16)))))]>,
1335 Requires<[IsARM, HasV5TE]> {
1340 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1341 IIC_iMAC16, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1342 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1343 (sext_inreg GPR:$b, i16))))]>,
1344 Requires<[IsARM, HasV5TE]> {
1349 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1350 IIC_iMAC16, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1351 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1352 (sra GPR:$b, (i32 16)))))]>,
1353 Requires<[IsARM, HasV5TE]> {
1358 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1359 IIC_iMAC16, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1360 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1361 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1362 Requires<[IsARM, HasV5TE]> {
1367 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1368 IIC_iMAC16, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1369 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1370 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1371 Requires<[IsARM, HasV5TE]> {
1377 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1378 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1380 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1381 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1383 //===----------------------------------------------------------------------===//
1384 // Misc. Arithmetic Instructions.
1387 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1388 "clz", " $dst, $src",
1389 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1390 let Inst{7-4} = 0b0001;
1391 let Inst{11-8} = 0b1111;
1392 let Inst{19-16} = 0b1111;
1395 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1396 "rev", " $dst, $src",
1397 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1398 let Inst{7-4} = 0b0011;
1399 let Inst{11-8} = 0b1111;
1400 let Inst{19-16} = 0b1111;
1403 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1404 "rev16", " $dst, $src",
1406 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1407 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1408 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1409 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1410 Requires<[IsARM, HasV6]> {
1411 let Inst{7-4} = 0b1011;
1412 let Inst{11-8} = 0b1111;
1413 let Inst{19-16} = 0b1111;
1416 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1417 "revsh", " $dst, $src",
1420 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1421 (shl GPR:$src, (i32 8))), i16))]>,
1422 Requires<[IsARM, HasV6]> {
1423 let Inst{7-4} = 0b1011;
1424 let Inst{11-8} = 0b1111;
1425 let Inst{19-16} = 0b1111;
1428 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1429 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1430 IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1431 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1432 (and (shl GPR:$src2, (i32 imm:$shamt)),
1434 Requires<[IsARM, HasV6]> {
1435 let Inst{6-4} = 0b001;
1438 // Alternate cases for PKHBT where identities eliminate some nodes.
1439 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1440 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1441 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1442 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1445 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1446 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1447 IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1448 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1449 (and (sra GPR:$src2, imm16_31:$shamt),
1450 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1451 let Inst{6-4} = 0b101;
1454 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1455 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1456 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1457 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1458 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1459 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1460 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1462 //===----------------------------------------------------------------------===//
1463 // Comparison Instructions...
1466 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1467 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1468 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1469 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1471 // Note that TST/TEQ don't set all the same flags that CMP does!
1472 defm TST : AI1_cmp_irs<0b1000, "tst",
1473 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1474 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1475 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1477 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1478 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1479 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1480 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1482 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1483 (CMNri GPR:$src, so_imm_neg:$imm)>;
1485 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1486 (CMNri GPR:$src, so_imm_neg:$imm)>;
1489 // Conditional moves
1490 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1491 // a two-value operand where a dag node expects two operands. :(
1492 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1493 IIC_iCMOVr, "mov", " $dst, $true",
1494 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1495 RegConstraint<"$false = $dst">, UnaryDP {
1500 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1501 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1502 "mov", " $dst, $true",
1503 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1504 RegConstraint<"$false = $dst">, UnaryDP {
1510 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1511 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1512 "mov", " $dst, $true",
1513 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1514 RegConstraint<"$false = $dst">, UnaryDP {
1519 //===----------------------------------------------------------------------===//
1523 // __aeabi_read_tp preserves the registers r1-r3.
1525 Defs = [R0, R12, LR, CPSR] in {
1526 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1527 "bl __aeabi_read_tp",
1528 [(set R0, ARMthread_pointer)]>;
1531 //===----------------------------------------------------------------------===//
1532 // SJLJ Exception handling intrinsics
1533 // eh_sjlj_setjmp() is an instruction sequence to store the return
1534 // address and save #0 in R0 for the non-longjmp case.
1535 // Since by its nature we may be coming from some other function to get
1536 // here, and we're using the stack frame for the containing function to
1537 // save/restore registers, we can't keep anything live in regs across
1538 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1539 // when we get here from a longjmp(). We force everthing out of registers
1540 // except for our own input by listing the relevant registers in Defs. By
1541 // doing so, we also cause the prologue/epilogue code to actively preserve
1542 // all of the callee-saved resgisters, which is exactly what we want.
1544 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1545 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1546 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1548 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1549 AddrModeNone, SizeSpecial, IndexModeNone,
1550 Pseudo, NoItinerary,
1551 "str sp, [$src, #+8] @ eh_setjmp begin\n\t"
1552 "add r12, pc, #8\n\t"
1553 "str r12, [$src, #+4]\n\t"
1555 "add pc, pc, #0\n\t"
1556 "mov r0, #1 @ eh_setjmp end", "",
1557 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1560 //===----------------------------------------------------------------------===//
1561 // Non-Instruction Patterns
1564 // ConstantPool, GlobalAddress, and JumpTable
1565 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1566 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1567 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1568 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1570 // Large immediate handling.
1572 // Two piece so_imms.
1573 let isReMaterializable = 1 in
1574 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1576 "mov", " $dst, $src",
1577 [(set GPR:$dst, so_imm2part:$src)]>,
1578 Requires<[IsARM, NoV6T2]>;
1580 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1581 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1582 (so_imm2part_2 imm:$RHS))>;
1583 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1584 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1585 (so_imm2part_2 imm:$RHS))>;
1587 // 32-bit immediate using movw + movt.
1588 // This is a single pseudo instruction, the benefit is that it can be remat'd
1589 // as a single unit instead of having to handle reg inputs.
1590 // FIXME: Remove this when we can do generalized remat.
1591 let isReMaterializable = 1 in
1592 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1593 "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1594 [(set GPR:$dst, (i32 imm:$src))]>,
1595 Requires<[IsARM, HasV6T2]>;
1597 // TODO: add,sub,and, 3-instr forms?
1601 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1602 Requires<[IsARM, IsNotDarwin]>;
1603 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1604 Requires<[IsARM, IsDarwin]>;
1606 // zextload i1 -> zextload i8
1607 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1609 // extload -> zextload
1610 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1611 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1612 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1614 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1615 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1618 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1619 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1620 (SMULBB GPR:$a, GPR:$b)>;
1621 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1622 (SMULBB GPR:$a, GPR:$b)>;
1623 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1624 (sra GPR:$b, (i32 16))),
1625 (SMULBT GPR:$a, GPR:$b)>;
1626 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1627 (SMULBT GPR:$a, GPR:$b)>;
1628 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1629 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1630 (SMULTB GPR:$a, GPR:$b)>;
1631 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1632 (SMULTB GPR:$a, GPR:$b)>;
1633 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1635 (SMULWB GPR:$a, GPR:$b)>;
1636 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1637 (SMULWB GPR:$a, GPR:$b)>;
1639 def : ARMV5TEPat<(add GPR:$acc,
1640 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1641 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1642 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1643 def : ARMV5TEPat<(add GPR:$acc,
1644 (mul sext_16_node:$a, sext_16_node:$b)),
1645 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1646 def : ARMV5TEPat<(add GPR:$acc,
1647 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1648 (sra GPR:$b, (i32 16)))),
1649 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1650 def : ARMV5TEPat<(add GPR:$acc,
1651 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1652 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1653 def : ARMV5TEPat<(add GPR:$acc,
1654 (mul (sra GPR:$a, (i32 16)),
1655 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1656 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1657 def : ARMV5TEPat<(add GPR:$acc,
1658 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1659 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1660 def : ARMV5TEPat<(add GPR:$acc,
1661 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1663 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1664 def : ARMV5TEPat<(add GPR:$acc,
1665 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1666 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1668 //===----------------------------------------------------------------------===//
1672 include "ARMInstrThumb.td"
1674 //===----------------------------------------------------------------------===//
1678 include "ARMInstrThumb2.td"
1680 //===----------------------------------------------------------------------===//
1681 // Floating Point Support
1684 include "ARMInstrVFP.td"
1686 //===----------------------------------------------------------------------===//
1687 // Advanced SIMD (NEON) Support
1690 include "ARMInstrNEON.td"