1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
88 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
89 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
90 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
92 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
93 [SDNPHasChain, SDNPOutGlue]>;
94 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
99 SDNPMayStore, SDNPMayLoad]>;
101 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
107 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
108 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
112 [SDNPHasChain, SDNPOptInGlue]>;
114 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
117 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
118 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
120 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
122 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
125 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
128 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
131 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
134 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
135 [SDNPOutGlue, SDNPCommutative]>;
137 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
139 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
140 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
141 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
143 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
145 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
146 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
147 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
149 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
150 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
151 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
152 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
153 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
155 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
157 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
159 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
160 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
162 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
164 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
165 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
170 //===----------------------------------------------------------------------===//
171 // ARM Instruction Predicate Definitions.
173 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
174 AssemblerPredicate<"HasV4TOps", "armv4t">;
175 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
176 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
177 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
178 AssemblerPredicate<"HasV5TEOps", "armv5te">;
179 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
180 AssemblerPredicate<"HasV6Ops", "armv6">;
181 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
182 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
183 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
184 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
185 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
186 AssemblerPredicate<"HasV7Ops", "armv7">;
187 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
188 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
189 AssemblerPredicate<"FeatureVFP2", "VFP2">;
190 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
191 AssemblerPredicate<"FeatureVFP3", "VFP3">;
192 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
193 AssemblerPredicate<"FeatureVFP4", "VFP4">;
194 def HasNEON : Predicate<"Subtarget->hasNEON()">,
195 AssemblerPredicate<"FeatureNEON", "NEON">;
196 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
197 AssemblerPredicate<"FeatureFP16","half-float">;
198 def HasDivide : Predicate<"Subtarget->hasDivide()">,
199 AssemblerPredicate<"FeatureHWDiv", "divide">;
200 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
201 AssemblerPredicate<"FeatureT2XtPk",
203 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
204 AssemblerPredicate<"FeatureDSPThumb2",
206 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
207 AssemblerPredicate<"FeatureDB",
209 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
210 AssemblerPredicate<"FeatureMP",
212 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
213 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
214 def IsThumb : Predicate<"Subtarget->isThumb()">,
215 AssemblerPredicate<"ModeThumb", "thumb">;
216 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
217 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
218 AssemblerPredicate<"ModeThumb,FeatureThumb2",
220 def IsMClass : Predicate<"Subtarget->isMClass()">,
221 AssemblerPredicate<"FeatureMClass", "armv7m">;
222 def IsARClass : Predicate<"!Subtarget->isMClass()">,
223 AssemblerPredicate<"!FeatureMClass",
225 def IsARM : Predicate<"!Subtarget->isThumb()">,
226 AssemblerPredicate<"!ModeThumb", "arm-mode">;
227 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
228 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
229 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
231 // FIXME: Eventually this will be just "hasV6T2Ops".
232 def UseMovt : Predicate<"Subtarget->useMovt()">;
233 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
234 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
236 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
237 // But only select them if more precision in FP computation is allowed.
238 // Do not use them for Darwin platforms.
239 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
240 " FPOpFusion::Fast) && "
241 "!Subtarget->isTargetDarwin()">;
242 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
243 "Subtarget->isTargetDarwin()">;
245 def IsLE : Predicate<"TLI.isLittleEndian()">;
246 def IsBE : Predicate<"TLI.isBigEndian()">;
248 //===----------------------------------------------------------------------===//
249 // ARM Flag Definitions.
251 class RegConstraint<string C> {
252 string Constraints = C;
255 //===----------------------------------------------------------------------===//
256 // ARM specific transformation functions and pattern fragments.
259 // imm_neg_XFORM - Return a imm value packed into the format described for
260 // imm_neg defs below.
261 def imm_neg_XFORM : SDNodeXForm<imm, [{
262 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
265 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
266 // so_imm_not def below.
267 def so_imm_not_XFORM : SDNodeXForm<imm, [{
268 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
271 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
272 def imm16_31 : ImmLeaf<i32, [{
273 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
276 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
277 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
278 int64_t Value = -(int)N->getZExtValue();
279 return Value && ARM_AM::getSOImmVal(Value) != -1;
281 let ParserMatchClass = so_imm_neg_asmoperand;
284 // Note: this pattern doesn't require an encoder method and such, as it's
285 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
286 // is handled by the destination instructions, which use so_imm.
287 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
288 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
289 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
290 }], so_imm_not_XFORM> {
291 let ParserMatchClass = so_imm_not_asmoperand;
294 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
295 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
296 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
299 /// Split a 32-bit immediate into two 16 bit parts.
300 def hi16 : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
304 def lo16AllZero : PatLeaf<(i32 imm), [{
305 // Returns true if all low 16-bits are 0.
306 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
309 class BinOpWithFlagFrag<dag res> :
310 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
311 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
312 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
314 // An 'and' node with a single use.
315 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
316 return N->hasOneUse();
319 // An 'xor' node with a single use.
320 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
321 return N->hasOneUse();
324 // An 'fmul' node with a single use.
325 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
326 return N->hasOneUse();
329 // An 'fadd' node which checks for single non-hazardous use.
330 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
331 return hasNoVMLxHazardUse(N);
334 // An 'fsub' node which checks for single non-hazardous use.
335 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
336 return hasNoVMLxHazardUse(N);
339 //===----------------------------------------------------------------------===//
340 // Operand Definitions.
343 // Immediate operands with a shared generic asm render method.
344 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
347 // FIXME: rename brtarget to t2_brtarget
348 def brtarget : Operand<OtherVT> {
349 let EncoderMethod = "getBranchTargetOpValue";
350 let OperandType = "OPERAND_PCREL";
351 let DecoderMethod = "DecodeT2BROperand";
354 // FIXME: get rid of this one?
355 def uncondbrtarget : Operand<OtherVT> {
356 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
357 let OperandType = "OPERAND_PCREL";
360 // Branch target for ARM. Handles conditional/unconditional
361 def br_target : Operand<OtherVT> {
362 let EncoderMethod = "getARMBranchTargetOpValue";
363 let OperandType = "OPERAND_PCREL";
367 // FIXME: rename bltarget to t2_bl_target?
368 def bltarget : Operand<i32> {
369 // Encoded the same as branch targets.
370 let EncoderMethod = "getBranchTargetOpValue";
371 let OperandType = "OPERAND_PCREL";
374 // Call target for ARM. Handles conditional/unconditional
375 // FIXME: rename bl_target to t2_bltarget?
376 def bl_target : Operand<i32> {
377 let EncoderMethod = "getARMBLTargetOpValue";
378 let OperandType = "OPERAND_PCREL";
381 def blx_target : Operand<i32> {
382 let EncoderMethod = "getARMBLXTargetOpValue";
383 let OperandType = "OPERAND_PCREL";
386 // A list of registers separated by comma. Used by load/store multiple.
387 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
388 def reglist : Operand<i32> {
389 let EncoderMethod = "getRegisterListOpValue";
390 let ParserMatchClass = RegListAsmOperand;
391 let PrintMethod = "printRegisterList";
392 let DecoderMethod = "DecodeRegListOperand";
395 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
396 def dpr_reglist : Operand<i32> {
397 let EncoderMethod = "getRegisterListOpValue";
398 let ParserMatchClass = DPRRegListAsmOperand;
399 let PrintMethod = "printRegisterList";
400 let DecoderMethod = "DecodeDPRRegListOperand";
403 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
404 def spr_reglist : Operand<i32> {
405 let EncoderMethod = "getRegisterListOpValue";
406 let ParserMatchClass = SPRRegListAsmOperand;
407 let PrintMethod = "printRegisterList";
408 let DecoderMethod = "DecodeSPRRegListOperand";
411 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
412 def cpinst_operand : Operand<i32> {
413 let PrintMethod = "printCPInstOperand";
417 def pclabel : Operand<i32> {
418 let PrintMethod = "printPCLabel";
421 // ADR instruction labels.
422 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
423 def adrlabel : Operand<i32> {
424 let EncoderMethod = "getAdrLabelOpValue";
425 let ParserMatchClass = AdrLabelAsmOperand;
426 let PrintMethod = "printAdrLabelOperand";
429 def neon_vcvt_imm32 : Operand<i32> {
430 let EncoderMethod = "getNEONVcvtImm32OpValue";
431 let DecoderMethod = "DecodeVCVTImmOperand";
434 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
435 def rot_imm_XFORM: SDNodeXForm<imm, [{
436 switch (N->getZExtValue()){
438 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
439 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
440 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
441 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
444 def RotImmAsmOperand : AsmOperandClass {
446 let ParserMethod = "parseRotImm";
448 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
449 int32_t v = N->getZExtValue();
450 return v == 8 || v == 16 || v == 24; }],
452 let PrintMethod = "printRotImmOperand";
453 let ParserMatchClass = RotImmAsmOperand;
456 // shift_imm: An integer that encodes a shift amount and the type of shift
457 // (asr or lsl). The 6-bit immediate encodes as:
460 // {4-0} imm5 shift amount.
461 // asr #32 encoded as imm5 == 0.
462 def ShifterImmAsmOperand : AsmOperandClass {
463 let Name = "ShifterImm";
464 let ParserMethod = "parseShifterImm";
466 def shift_imm : Operand<i32> {
467 let PrintMethod = "printShiftImmOperand";
468 let ParserMatchClass = ShifterImmAsmOperand;
471 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
472 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
473 def so_reg_reg : Operand<i32>, // reg reg imm
474 ComplexPattern<i32, 3, "SelectRegShifterOperand",
475 [shl, srl, sra, rotr]> {
476 let EncoderMethod = "getSORegRegOpValue";
477 let PrintMethod = "printSORegRegOperand";
478 let DecoderMethod = "DecodeSORegRegOperand";
479 let ParserMatchClass = ShiftedRegAsmOperand;
480 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
483 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
484 def so_reg_imm : Operand<i32>, // reg imm
485 ComplexPattern<i32, 2, "SelectImmShifterOperand",
486 [shl, srl, sra, rotr]> {
487 let EncoderMethod = "getSORegImmOpValue";
488 let PrintMethod = "printSORegImmOperand";
489 let DecoderMethod = "DecodeSORegImmOperand";
490 let ParserMatchClass = ShiftedImmAsmOperand;
491 let MIOperandInfo = (ops GPR, i32imm);
494 // FIXME: Does this need to be distinct from so_reg?
495 def shift_so_reg_reg : Operand<i32>, // reg reg imm
496 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
497 [shl,srl,sra,rotr]> {
498 let EncoderMethod = "getSORegRegOpValue";
499 let PrintMethod = "printSORegRegOperand";
500 let DecoderMethod = "DecodeSORegRegOperand";
501 let ParserMatchClass = ShiftedRegAsmOperand;
502 let MIOperandInfo = (ops GPR, GPR, i32imm);
505 // FIXME: Does this need to be distinct from so_reg?
506 def shift_so_reg_imm : Operand<i32>, // reg reg imm
507 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
508 [shl,srl,sra,rotr]> {
509 let EncoderMethod = "getSORegImmOpValue";
510 let PrintMethod = "printSORegImmOperand";
511 let DecoderMethod = "DecodeSORegImmOperand";
512 let ParserMatchClass = ShiftedImmAsmOperand;
513 let MIOperandInfo = (ops GPR, i32imm);
517 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
518 // 8-bit immediate rotated by an arbitrary number of bits.
519 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
520 def so_imm : Operand<i32>, ImmLeaf<i32, [{
521 return ARM_AM::getSOImmVal(Imm) != -1;
523 let EncoderMethod = "getSOImmOpValue";
524 let ParserMatchClass = SOImmAsmOperand;
525 let DecoderMethod = "DecodeSOImmOperand";
528 // Break so_imm's up into two pieces. This handles immediates with up to 16
529 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
530 // get the first/second pieces.
531 def so_imm2part : PatLeaf<(imm), [{
532 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
535 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
537 def arm_i32imm : PatLeaf<(imm), [{
538 if (Subtarget->hasV6T2Ops())
540 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
543 /// imm0_1 predicate - Immediate in the range [0,1].
544 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
545 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
547 /// imm0_3 predicate - Immediate in the range [0,3].
548 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
549 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
551 /// imm0_7 predicate - Immediate in the range [0,7].
552 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
553 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
554 return Imm >= 0 && Imm < 8;
556 let ParserMatchClass = Imm0_7AsmOperand;
559 /// imm8 predicate - Immediate is exactly 8.
560 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
561 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
562 let ParserMatchClass = Imm8AsmOperand;
565 /// imm16 predicate - Immediate is exactly 16.
566 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
567 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
568 let ParserMatchClass = Imm16AsmOperand;
571 /// imm32 predicate - Immediate is exactly 32.
572 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
573 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
574 let ParserMatchClass = Imm32AsmOperand;
577 /// imm1_7 predicate - Immediate in the range [1,7].
578 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
579 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
580 let ParserMatchClass = Imm1_7AsmOperand;
583 /// imm1_15 predicate - Immediate in the range [1,15].
584 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
585 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
586 let ParserMatchClass = Imm1_15AsmOperand;
589 /// imm1_31 predicate - Immediate in the range [1,31].
590 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
591 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
592 let ParserMatchClass = Imm1_31AsmOperand;
595 /// imm0_15 predicate - Immediate in the range [0,15].
596 def Imm0_15AsmOperand: ImmAsmOperand {
597 let Name = "Imm0_15";
598 let DiagnosticType = "ImmRange0_15";
600 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
601 return Imm >= 0 && Imm < 16;
603 let ParserMatchClass = Imm0_15AsmOperand;
606 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
607 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
608 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
609 return Imm >= 0 && Imm < 32;
611 let ParserMatchClass = Imm0_31AsmOperand;
614 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
615 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
616 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
617 return Imm >= 0 && Imm < 32;
619 let ParserMatchClass = Imm0_32AsmOperand;
622 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
623 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
624 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
625 return Imm >= 0 && Imm < 64;
627 let ParserMatchClass = Imm0_63AsmOperand;
630 /// imm0_255 predicate - Immediate in the range [0,255].
631 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
632 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
633 let ParserMatchClass = Imm0_255AsmOperand;
636 /// imm0_65535 - An immediate is in the range [0.65535].
637 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
638 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
639 return Imm >= 0 && Imm < 65536;
641 let ParserMatchClass = Imm0_65535AsmOperand;
644 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
645 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
646 return -Imm >= 0 && -Imm < 65536;
649 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
650 // a relocatable expression.
652 // FIXME: This really needs a Thumb version separate from the ARM version.
653 // While the range is the same, and can thus use the same match class,
654 // the encoding is different so it should have a different encoder method.
655 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
656 def imm0_65535_expr : Operand<i32> {
657 let EncoderMethod = "getHiLo16ImmOpValue";
658 let ParserMatchClass = Imm0_65535ExprAsmOperand;
661 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
662 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
663 def imm24b : Operand<i32>, ImmLeaf<i32, [{
664 return Imm >= 0 && Imm <= 0xffffff;
666 let ParserMatchClass = Imm24bitAsmOperand;
670 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
672 def BitfieldAsmOperand : AsmOperandClass {
673 let Name = "Bitfield";
674 let ParserMethod = "parseBitfield";
677 def bf_inv_mask_imm : Operand<i32>,
679 return ARM::isBitFieldInvertedMask(N->getZExtValue());
681 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
682 let PrintMethod = "printBitfieldInvMaskImmOperand";
683 let DecoderMethod = "DecodeBitfieldMaskOperand";
684 let ParserMatchClass = BitfieldAsmOperand;
687 def imm1_32_XFORM: SDNodeXForm<imm, [{
688 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
690 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
691 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
692 uint64_t Imm = N->getZExtValue();
693 return Imm > 0 && Imm <= 32;
696 let PrintMethod = "printImmPlusOneOperand";
697 let ParserMatchClass = Imm1_32AsmOperand;
700 def imm1_16_XFORM: SDNodeXForm<imm, [{
701 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
703 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
704 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
706 let PrintMethod = "printImmPlusOneOperand";
707 let ParserMatchClass = Imm1_16AsmOperand;
710 // Define ARM specific addressing modes.
711 // addrmode_imm12 := reg +/- imm12
713 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
714 def addrmode_imm12 : Operand<i32>,
715 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
716 // 12-bit immediate operand. Note that instructions using this encode
717 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
718 // immediate values are as normal.
720 let EncoderMethod = "getAddrModeImm12OpValue";
721 let PrintMethod = "printAddrModeImm12Operand";
722 let DecoderMethod = "DecodeAddrModeImm12Operand";
723 let ParserMatchClass = MemImm12OffsetAsmOperand;
724 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
726 // ldst_so_reg := reg +/- reg shop imm
728 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
729 def ldst_so_reg : Operand<i32>,
730 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
731 let EncoderMethod = "getLdStSORegOpValue";
732 // FIXME: Simplify the printer
733 let PrintMethod = "printAddrMode2Operand";
734 let DecoderMethod = "DecodeSORegMemOperand";
735 let ParserMatchClass = MemRegOffsetAsmOperand;
736 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
739 // postidx_imm8 := +/- [0,255]
742 // {8} 1 is imm8 is non-negative. 0 otherwise.
743 // {7-0} [0,255] imm8 value.
744 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
745 def postidx_imm8 : Operand<i32> {
746 let PrintMethod = "printPostIdxImm8Operand";
747 let ParserMatchClass = PostIdxImm8AsmOperand;
748 let MIOperandInfo = (ops i32imm);
751 // postidx_imm8s4 := +/- [0,1020]
754 // {8} 1 is imm8 is non-negative. 0 otherwise.
755 // {7-0} [0,255] imm8 value, scaled by 4.
756 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
757 def postidx_imm8s4 : Operand<i32> {
758 let PrintMethod = "printPostIdxImm8s4Operand";
759 let ParserMatchClass = PostIdxImm8s4AsmOperand;
760 let MIOperandInfo = (ops i32imm);
764 // postidx_reg := +/- reg
766 def PostIdxRegAsmOperand : AsmOperandClass {
767 let Name = "PostIdxReg";
768 let ParserMethod = "parsePostIdxReg";
770 def postidx_reg : Operand<i32> {
771 let EncoderMethod = "getPostIdxRegOpValue";
772 let DecoderMethod = "DecodePostIdxReg";
773 let PrintMethod = "printPostIdxRegOperand";
774 let ParserMatchClass = PostIdxRegAsmOperand;
775 let MIOperandInfo = (ops GPRnopc, i32imm);
779 // addrmode2 := reg +/- imm12
780 // := reg +/- reg shop imm
782 // FIXME: addrmode2 should be refactored the rest of the way to always
783 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
784 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
785 def addrmode2 : Operand<i32>,
786 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
787 let EncoderMethod = "getAddrMode2OpValue";
788 let PrintMethod = "printAddrMode2Operand";
789 let ParserMatchClass = AddrMode2AsmOperand;
790 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
793 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
794 let Name = "PostIdxRegShifted";
795 let ParserMethod = "parsePostIdxReg";
797 def am2offset_reg : Operand<i32>,
798 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
799 [], [SDNPWantRoot]> {
800 let EncoderMethod = "getAddrMode2OffsetOpValue";
801 let PrintMethod = "printAddrMode2OffsetOperand";
802 // When using this for assembly, it's always as a post-index offset.
803 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
804 let MIOperandInfo = (ops GPRnopc, i32imm);
807 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
808 // the GPR is purely vestigal at this point.
809 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
810 def am2offset_imm : Operand<i32>,
811 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
812 [], [SDNPWantRoot]> {
813 let EncoderMethod = "getAddrMode2OffsetOpValue";
814 let PrintMethod = "printAddrMode2OffsetOperand";
815 let ParserMatchClass = AM2OffsetImmAsmOperand;
816 let MIOperandInfo = (ops GPRnopc, i32imm);
820 // addrmode3 := reg +/- reg
821 // addrmode3 := reg +/- imm8
823 // FIXME: split into imm vs. reg versions.
824 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
825 def addrmode3 : Operand<i32>,
826 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
827 let EncoderMethod = "getAddrMode3OpValue";
828 let PrintMethod = "printAddrMode3Operand";
829 let ParserMatchClass = AddrMode3AsmOperand;
830 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
833 // FIXME: split into imm vs. reg versions.
834 // FIXME: parser method to handle +/- register.
835 def AM3OffsetAsmOperand : AsmOperandClass {
836 let Name = "AM3Offset";
837 let ParserMethod = "parseAM3Offset";
839 def am3offset : Operand<i32>,
840 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
841 [], [SDNPWantRoot]> {
842 let EncoderMethod = "getAddrMode3OffsetOpValue";
843 let PrintMethod = "printAddrMode3OffsetOperand";
844 let ParserMatchClass = AM3OffsetAsmOperand;
845 let MIOperandInfo = (ops GPR, i32imm);
848 // ldstm_mode := {ia, ib, da, db}
850 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
851 let EncoderMethod = "getLdStmModeOpValue";
852 let PrintMethod = "printLdStmModeOperand";
855 // addrmode5 := reg +/- imm8*4
857 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
858 def addrmode5 : Operand<i32>,
859 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
860 let PrintMethod = "printAddrMode5Operand";
861 let EncoderMethod = "getAddrMode5OpValue";
862 let DecoderMethod = "DecodeAddrMode5Operand";
863 let ParserMatchClass = AddrMode5AsmOperand;
864 let MIOperandInfo = (ops GPR:$base, i32imm);
867 // addrmode6 := reg with optional alignment
869 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
870 def addrmode6 : Operand<i32>,
871 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
872 let PrintMethod = "printAddrMode6Operand";
873 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
874 let EncoderMethod = "getAddrMode6AddressOpValue";
875 let DecoderMethod = "DecodeAddrMode6Operand";
876 let ParserMatchClass = AddrMode6AsmOperand;
879 def am6offset : Operand<i32>,
880 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
881 [], [SDNPWantRoot]> {
882 let PrintMethod = "printAddrMode6OffsetOperand";
883 let MIOperandInfo = (ops GPR);
884 let EncoderMethod = "getAddrMode6OffsetOpValue";
885 let DecoderMethod = "DecodeGPRRegisterClass";
888 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
889 // (single element from one lane) for size 32.
890 def addrmode6oneL32 : Operand<i32>,
891 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
892 let PrintMethod = "printAddrMode6Operand";
893 let MIOperandInfo = (ops GPR:$addr, i32imm);
894 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
897 // Special version of addrmode6 to handle alignment encoding for VLD-dup
898 // instructions, specifically VLD4-dup.
899 def addrmode6dup : Operand<i32>,
900 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
901 let PrintMethod = "printAddrMode6Operand";
902 let MIOperandInfo = (ops GPR:$addr, i32imm);
903 let EncoderMethod = "getAddrMode6DupAddressOpValue";
904 // FIXME: This is close, but not quite right. The alignment specifier is
906 let ParserMatchClass = AddrMode6AsmOperand;
909 // addrmodepc := pc + reg
911 def addrmodepc : Operand<i32>,
912 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
913 let PrintMethod = "printAddrModePCOperand";
914 let MIOperandInfo = (ops GPR, i32imm);
917 // addr_offset_none := reg
919 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
920 def addr_offset_none : Operand<i32>,
921 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
922 let PrintMethod = "printAddrMode7Operand";
923 let DecoderMethod = "DecodeAddrMode7Operand";
924 let ParserMatchClass = MemNoOffsetAsmOperand;
925 let MIOperandInfo = (ops GPR:$base);
928 def nohash_imm : Operand<i32> {
929 let PrintMethod = "printNoHashImmediate";
932 def CoprocNumAsmOperand : AsmOperandClass {
933 let Name = "CoprocNum";
934 let ParserMethod = "parseCoprocNumOperand";
936 def p_imm : Operand<i32> {
937 let PrintMethod = "printPImmediate";
938 let ParserMatchClass = CoprocNumAsmOperand;
939 let DecoderMethod = "DecodeCoprocessor";
942 def pf_imm : Operand<i32> {
943 let PrintMethod = "printPImmediate";
944 let ParserMatchClass = CoprocNumAsmOperand;
947 def CoprocRegAsmOperand : AsmOperandClass {
948 let Name = "CoprocReg";
949 let ParserMethod = "parseCoprocRegOperand";
951 def c_imm : Operand<i32> {
952 let PrintMethod = "printCImmediate";
953 let ParserMatchClass = CoprocRegAsmOperand;
955 def CoprocOptionAsmOperand : AsmOperandClass {
956 let Name = "CoprocOption";
957 let ParserMethod = "parseCoprocOptionOperand";
959 def coproc_option_imm : Operand<i32> {
960 let PrintMethod = "printCoprocOptionImm";
961 let ParserMatchClass = CoprocOptionAsmOperand;
964 //===----------------------------------------------------------------------===//
966 include "ARMInstrFormats.td"
968 //===----------------------------------------------------------------------===//
969 // Multiclass helpers...
972 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
973 /// binop that produces a value.
974 let TwoOperandAliasConstraint = "$Rn = $Rd" in
975 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
976 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
977 PatFrag opnode, bit Commutable = 0> {
978 // The register-immediate version is re-materializable. This is useful
979 // in particular for taking the address of a local.
980 let isReMaterializable = 1 in {
981 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
982 iii, opc, "\t$Rd, $Rn, $imm",
983 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
988 let Inst{19-16} = Rn;
989 let Inst{15-12} = Rd;
990 let Inst{11-0} = imm;
993 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
994 iir, opc, "\t$Rd, $Rn, $Rm",
995 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1000 let isCommutable = Commutable;
1001 let Inst{19-16} = Rn;
1002 let Inst{15-12} = Rd;
1003 let Inst{11-4} = 0b00000000;
1007 def rsi : AsI1<opcod, (outs GPR:$Rd),
1008 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1009 iis, opc, "\t$Rd, $Rn, $shift",
1010 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1015 let Inst{19-16} = Rn;
1016 let Inst{15-12} = Rd;
1017 let Inst{11-5} = shift{11-5};
1019 let Inst{3-0} = shift{3-0};
1022 def rsr : AsI1<opcod, (outs GPR:$Rd),
1023 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1024 iis, opc, "\t$Rd, $Rn, $shift",
1025 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1030 let Inst{19-16} = Rn;
1031 let Inst{15-12} = Rd;
1032 let Inst{11-8} = shift{11-8};
1034 let Inst{6-5} = shift{6-5};
1036 let Inst{3-0} = shift{3-0};
1040 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1041 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1042 /// it is equivalent to the AsI1_bin_irs counterpart.
1043 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1044 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1045 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1046 PatFrag opnode, bit Commutable = 0> {
1047 // The register-immediate version is re-materializable. This is useful
1048 // in particular for taking the address of a local.
1049 let isReMaterializable = 1 in {
1050 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1051 iii, opc, "\t$Rd, $Rn, $imm",
1052 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1057 let Inst{19-16} = Rn;
1058 let Inst{15-12} = Rd;
1059 let Inst{11-0} = imm;
1062 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1063 iir, opc, "\t$Rd, $Rn, $Rm",
1064 [/* pattern left blank */]> {
1068 let Inst{11-4} = 0b00000000;
1071 let Inst{15-12} = Rd;
1072 let Inst{19-16} = Rn;
1075 def rsi : AsI1<opcod, (outs GPR:$Rd),
1076 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1077 iis, opc, "\t$Rd, $Rn, $shift",
1078 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1083 let Inst{19-16} = Rn;
1084 let Inst{15-12} = Rd;
1085 let Inst{11-5} = shift{11-5};
1087 let Inst{3-0} = shift{3-0};
1090 def rsr : AsI1<opcod, (outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1092 iis, opc, "\t$Rd, $Rn, $shift",
1093 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1098 let Inst{19-16} = Rn;
1099 let Inst{15-12} = Rd;
1100 let Inst{11-8} = shift{11-8};
1102 let Inst{6-5} = shift{6-5};
1104 let Inst{3-0} = shift{3-0};
1108 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1110 /// These opcodes will be converted to the real non-S opcodes by
1111 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1112 let hasPostISelHook = 1, Defs = [CPSR] in {
1113 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1114 InstrItinClass iis, PatFrag opnode,
1115 bit Commutable = 0> {
1116 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1118 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1120 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1123 let isCommutable = Commutable;
1125 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1126 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1128 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1129 so_reg_imm:$shift))]>;
1131 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1132 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1134 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1135 so_reg_reg:$shift))]>;
1139 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1140 /// operands are reversed.
1141 let hasPostISelHook = 1, Defs = [CPSR] in {
1142 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1143 InstrItinClass iis, PatFrag opnode,
1144 bit Commutable = 0> {
1145 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1147 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1149 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1150 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1155 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1156 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1158 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1163 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1164 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1165 /// a explicit result, only implicitly set CPSR.
1166 let isCompare = 1, Defs = [CPSR] in {
1167 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1168 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1169 PatFrag opnode, bit Commutable = 0> {
1170 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1172 [(opnode GPR:$Rn, so_imm:$imm)]> {
1177 let Inst{19-16} = Rn;
1178 let Inst{15-12} = 0b0000;
1179 let Inst{11-0} = imm;
1181 let Unpredictable{15-12} = 0b1111;
1183 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1185 [(opnode GPR:$Rn, GPR:$Rm)]> {
1188 let isCommutable = Commutable;
1191 let Inst{19-16} = Rn;
1192 let Inst{15-12} = 0b0000;
1193 let Inst{11-4} = 0b00000000;
1196 let Unpredictable{15-12} = 0b1111;
1198 def rsi : AI1<opcod, (outs),
1199 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1200 opc, "\t$Rn, $shift",
1201 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1206 let Inst{19-16} = Rn;
1207 let Inst{15-12} = 0b0000;
1208 let Inst{11-5} = shift{11-5};
1210 let Inst{3-0} = shift{3-0};
1212 let Unpredictable{15-12} = 0b1111;
1214 def rsr : AI1<opcod, (outs),
1215 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1216 opc, "\t$Rn, $shift",
1217 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1222 let Inst{19-16} = Rn;
1223 let Inst{15-12} = 0b0000;
1224 let Inst{11-8} = shift{11-8};
1226 let Inst{6-5} = shift{6-5};
1228 let Inst{3-0} = shift{3-0};
1230 let Unpredictable{15-12} = 0b1111;
1236 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1237 /// register and one whose operand is a register rotated by 8/16/24.
1238 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1239 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1240 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1241 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1242 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1243 Requires<[IsARM, HasV6]> {
1247 let Inst{19-16} = 0b1111;
1248 let Inst{15-12} = Rd;
1249 let Inst{11-10} = rot;
1253 class AI_ext_rrot_np<bits<8> opcod, string opc>
1254 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1255 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1256 Requires<[IsARM, HasV6]> {
1258 let Inst{19-16} = 0b1111;
1259 let Inst{11-10} = rot;
1262 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1263 /// register and one whose operand is a register rotated by 8/16/24.
1264 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1265 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1266 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1267 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1268 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1269 Requires<[IsARM, HasV6]> {
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = Rd;
1276 let Inst{11-10} = rot;
1277 let Inst{9-4} = 0b000111;
1281 class AI_exta_rrot_np<bits<8> opcod, string opc>
1282 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1283 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1284 Requires<[IsARM, HasV6]> {
1287 let Inst{19-16} = Rn;
1288 let Inst{11-10} = rot;
1291 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1292 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1293 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1294 bit Commutable = 0> {
1295 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1296 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1297 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1298 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1304 let Inst{15-12} = Rd;
1305 let Inst{19-16} = Rn;
1306 let Inst{11-0} = imm;
1308 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1309 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1310 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1315 let Inst{11-4} = 0b00000000;
1317 let isCommutable = Commutable;
1319 let Inst{15-12} = Rd;
1320 let Inst{19-16} = Rn;
1322 def rsi : AsI1<opcod, (outs GPR:$Rd),
1323 (ins GPR:$Rn, so_reg_imm:$shift),
1324 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1325 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1331 let Inst{19-16} = Rn;
1332 let Inst{15-12} = Rd;
1333 let Inst{11-5} = shift{11-5};
1335 let Inst{3-0} = shift{3-0};
1337 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1338 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1339 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1340 [(set GPRnopc:$Rd, CPSR,
1341 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1347 let Inst{19-16} = Rn;
1348 let Inst{15-12} = Rd;
1349 let Inst{11-8} = shift{11-8};
1351 let Inst{6-5} = shift{6-5};
1353 let Inst{3-0} = shift{3-0};
1358 /// AI1_rsc_irs - Define instructions and patterns for rsc
1359 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1360 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1361 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1362 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1363 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1364 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1370 let Inst{15-12} = Rd;
1371 let Inst{19-16} = Rn;
1372 let Inst{11-0} = imm;
1374 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1375 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1376 [/* pattern left blank */]> {
1380 let Inst{11-4} = 0b00000000;
1383 let Inst{15-12} = Rd;
1384 let Inst{19-16} = Rn;
1386 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1387 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1388 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1394 let Inst{19-16} = Rn;
1395 let Inst{15-12} = Rd;
1396 let Inst{11-5} = shift{11-5};
1398 let Inst{3-0} = shift{3-0};
1400 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1401 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1402 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1408 let Inst{19-16} = Rn;
1409 let Inst{15-12} = Rd;
1410 let Inst{11-8} = shift{11-8};
1412 let Inst{6-5} = shift{6-5};
1414 let Inst{3-0} = shift{3-0};
1419 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1420 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1421 InstrItinClass iir, PatFrag opnode> {
1422 // Note: We use the complex addrmode_imm12 rather than just an input
1423 // GPR and a constrained immediate so that we can use this to match
1424 // frame index references and avoid matching constant pool references.
1425 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1426 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1427 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1430 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1431 let Inst{19-16} = addr{16-13}; // Rn
1432 let Inst{15-12} = Rt;
1433 let Inst{11-0} = addr{11-0}; // imm12
1435 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1436 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1437 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1440 let shift{4} = 0; // Inst{4} = 0
1441 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1442 let Inst{19-16} = shift{16-13}; // Rn
1443 let Inst{15-12} = Rt;
1444 let Inst{11-0} = shift{11-0};
1449 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1450 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1451 InstrItinClass iir, PatFrag opnode> {
1452 // Note: We use the complex addrmode_imm12 rather than just an input
1453 // GPR and a constrained immediate so that we can use this to match
1454 // frame index references and avoid matching constant pool references.
1455 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1456 (ins addrmode_imm12:$addr),
1457 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1458 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1461 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1462 let Inst{19-16} = addr{16-13}; // Rn
1463 let Inst{15-12} = Rt;
1464 let Inst{11-0} = addr{11-0}; // imm12
1466 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1467 (ins ldst_so_reg:$shift),
1468 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1469 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1472 let shift{4} = 0; // Inst{4} = 0
1473 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1474 let Inst{19-16} = shift{16-13}; // Rn
1475 let Inst{15-12} = Rt;
1476 let Inst{11-0} = shift{11-0};
1482 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1483 InstrItinClass iir, PatFrag opnode> {
1484 // Note: We use the complex addrmode_imm12 rather than just an input
1485 // GPR and a constrained immediate so that we can use this to match
1486 // frame index references and avoid matching constant pool references.
1487 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1488 (ins GPR:$Rt, addrmode_imm12:$addr),
1489 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1490 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1493 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1494 let Inst{19-16} = addr{16-13}; // Rn
1495 let Inst{15-12} = Rt;
1496 let Inst{11-0} = addr{11-0}; // imm12
1498 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1499 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1500 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1503 let shift{4} = 0; // Inst{4} = 0
1504 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1505 let Inst{19-16} = shift{16-13}; // Rn
1506 let Inst{15-12} = Rt;
1507 let Inst{11-0} = shift{11-0};
1511 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1512 InstrItinClass iir, PatFrag opnode> {
1513 // Note: We use the complex addrmode_imm12 rather than just an input
1514 // GPR and a constrained immediate so that we can use this to match
1515 // frame index references and avoid matching constant pool references.
1516 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1517 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1518 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1519 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1522 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1523 let Inst{19-16} = addr{16-13}; // Rn
1524 let Inst{15-12} = Rt;
1525 let Inst{11-0} = addr{11-0}; // imm12
1527 def rs : AI2ldst<0b011, 0, isByte, (outs),
1528 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1529 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1530 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1533 let shift{4} = 0; // Inst{4} = 0
1534 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1535 let Inst{19-16} = shift{16-13}; // Rn
1536 let Inst{15-12} = Rt;
1537 let Inst{11-0} = shift{11-0};
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1546 //===----------------------------------------------------------------------===//
1547 // Miscellaneous Instructions.
1550 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1551 /// the function. The first operand is the ID# for this instruction, the second
1552 /// is the index into the MachineConstantPool that this is, the third is the
1553 /// size in bytes of this constant pool entry.
1554 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1555 def CONSTPOOL_ENTRY :
1556 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1557 i32imm:$size), NoItinerary, []>;
1559 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1560 // from removing one half of the matched pairs. That breaks PEI, which assumes
1561 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1562 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1563 def ADJCALLSTACKUP :
1564 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1565 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1567 def ADJCALLSTACKDOWN :
1568 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1569 [(ARMcallseq_start timm:$amt)]>;
1572 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1573 // (These pseudos use a hand-written selection code).
1574 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1575 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1576 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1578 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1579 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1581 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1582 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1584 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1585 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1587 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1588 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1590 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1591 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1593 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1594 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1596 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1597 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1598 GPR:$set1, GPR:$set2),
1602 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1603 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1605 let Inst{27-8} = 0b00110010000011110000;
1606 let Inst{7-0} = imm;
1609 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1610 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1611 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1612 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1613 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1615 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1616 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1621 let Inst{15-12} = Rd;
1622 let Inst{19-16} = Rn;
1623 let Inst{27-20} = 0b01101000;
1624 let Inst{7-4} = 0b1011;
1625 let Inst{11-8} = 0b1111;
1626 let Unpredictable{11-8} = 0b1111;
1629 // The 16-bit operand $val can be used by a debugger to store more information
1630 // about the breakpoint.
1631 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1632 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1634 let Inst{3-0} = val{3-0};
1635 let Inst{19-8} = val{15-4};
1636 let Inst{27-20} = 0b00010010;
1637 let Inst{7-4} = 0b0111;
1640 // Change Processor State
1641 // FIXME: We should use InstAlias to handle the optional operands.
1642 class CPS<dag iops, string asm_ops>
1643 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1644 []>, Requires<[IsARM]> {
1650 let Inst{31-28} = 0b1111;
1651 let Inst{27-20} = 0b00010000;
1652 let Inst{19-18} = imod;
1653 let Inst{17} = M; // Enabled if mode is set;
1654 let Inst{16-9} = 0b00000000;
1655 let Inst{8-6} = iflags;
1657 let Inst{4-0} = mode;
1660 let DecoderMethod = "DecodeCPSInstruction" in {
1662 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1663 "$imod\t$iflags, $mode">;
1664 let mode = 0, M = 0 in
1665 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1667 let imod = 0, iflags = 0, M = 1 in
1668 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1671 // Preload signals the memory system of possible future data/instruction access.
1672 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1674 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1675 !strconcat(opc, "\t$addr"),
1676 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1679 let Inst{31-26} = 0b111101;
1680 let Inst{25} = 0; // 0 for immediate form
1681 let Inst{24} = data;
1682 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1683 let Inst{22} = read;
1684 let Inst{21-20} = 0b01;
1685 let Inst{19-16} = addr{16-13}; // Rn
1686 let Inst{15-12} = 0b1111;
1687 let Inst{11-0} = addr{11-0}; // imm12
1690 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1691 !strconcat(opc, "\t$shift"),
1692 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1694 let Inst{31-26} = 0b111101;
1695 let Inst{25} = 1; // 1 for register form
1696 let Inst{24} = data;
1697 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1698 let Inst{22} = read;
1699 let Inst{21-20} = 0b01;
1700 let Inst{19-16} = shift{16-13}; // Rn
1701 let Inst{15-12} = 0b1111;
1702 let Inst{11-0} = shift{11-0};
1707 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1708 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1709 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1711 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1712 "setend\t$end", []>, Requires<[IsARM]> {
1714 let Inst{31-10} = 0b1111000100000001000000;
1719 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1720 []>, Requires<[IsARM, HasV7]> {
1722 let Inst{27-4} = 0b001100100000111100001111;
1723 let Inst{3-0} = opt;
1726 // A5.4 Permanently UNDEFINED instructions.
1727 let isBarrier = 1, isTerminator = 1 in
1728 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1731 let Inst = 0xe7ffdefe;
1734 // Address computation and loads and stores in PIC mode.
1735 let isNotDuplicable = 1 in {
1736 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1738 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1740 let AddedComplexity = 10 in {
1741 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1743 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1745 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1747 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1749 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1751 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1753 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1755 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1757 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1759 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1761 let AddedComplexity = 10 in {
1762 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1763 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1765 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1766 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1767 addrmodepc:$addr)]>;
1769 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1770 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1772 } // isNotDuplicable = 1
1775 // LEApcrel - Load a pc-relative address into a register without offending the
1777 let neverHasSideEffects = 1, isReMaterializable = 1 in
1778 // The 'adr' mnemonic encodes differently if the label is before or after
1779 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1780 // know until then which form of the instruction will be used.
1781 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1782 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1785 let Inst{27-25} = 0b001;
1787 let Inst{23-22} = label{13-12};
1790 let Inst{19-16} = 0b1111;
1791 let Inst{15-12} = Rd;
1792 let Inst{11-0} = label{11-0};
1794 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1797 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1798 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1801 //===----------------------------------------------------------------------===//
1802 // Control Flow Instructions.
1805 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1807 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1808 "bx", "\tlr", [(ARMretflag)]>,
1809 Requires<[IsARM, HasV4T]> {
1810 let Inst{27-0} = 0b0001001011111111111100011110;
1814 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1815 "mov", "\tpc, lr", [(ARMretflag)]>,
1816 Requires<[IsARM, NoV4T]> {
1817 let Inst{27-0} = 0b0001101000001111000000001110;
1821 // Indirect branches
1822 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1824 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1825 [(brind GPR:$dst)]>,
1826 Requires<[IsARM, HasV4T]> {
1828 let Inst{31-4} = 0b1110000100101111111111110001;
1829 let Inst{3-0} = dst;
1832 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1833 "bx", "\t$dst", [/* pattern left blank */]>,
1834 Requires<[IsARM, HasV4T]> {
1836 let Inst{27-4} = 0b000100101111111111110001;
1837 let Inst{3-0} = dst;
1841 // SP is marked as a use to prevent stack-pointer assignments that appear
1842 // immediately before calls from potentially appearing dead.
1844 // FIXME: Do we really need a non-predicated version? If so, it should
1845 // at least be a pseudo instruction expanding to the predicated version
1846 // at MC lowering time.
1847 Defs = [LR], Uses = [SP] in {
1848 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1849 IIC_Br, "bl\t$func",
1850 [(ARMcall tglobaladdr:$func)]>,
1852 let Inst{31-28} = 0b1110;
1854 let Inst{23-0} = func;
1855 let DecoderMethod = "DecodeBranchImmInstruction";
1858 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1859 IIC_Br, "bl", "\t$func",
1860 [(ARMcall_pred tglobaladdr:$func)]>,
1863 let Inst{23-0} = func;
1864 let DecoderMethod = "DecodeBranchImmInstruction";
1868 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1869 IIC_Br, "blx\t$func",
1870 [(ARMcall GPR:$func)]>,
1871 Requires<[IsARM, HasV5T]> {
1873 let Inst{31-4} = 0b1110000100101111111111110011;
1874 let Inst{3-0} = func;
1877 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1878 IIC_Br, "blx", "\t$func",
1879 [(ARMcall_pred GPR:$func)]>,
1880 Requires<[IsARM, HasV5T]> {
1882 let Inst{27-4} = 0b000100101111111111110011;
1883 let Inst{3-0} = func;
1887 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1888 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1889 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1890 Requires<[IsARM, HasV4T]>;
1893 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1894 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1895 Requires<[IsARM, NoV4T]>;
1897 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1898 // return stack predictor.
1899 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1900 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1904 let isBranch = 1, isTerminator = 1 in {
1905 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1906 // a two-value operand where a dag node expects two operands. :(
1907 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1908 IIC_Br, "b", "\t$target",
1909 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1911 let Inst{23-0} = target;
1912 let DecoderMethod = "DecodeBranchImmInstruction";
1915 let isBarrier = 1 in {
1916 // B is "predicable" since it's just a Bcc with an 'always' condition.
1917 let isPredicable = 1 in
1918 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1919 // should be sufficient.
1920 // FIXME: Is B really a Barrier? That doesn't seem right.
1921 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1922 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1924 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1925 def BR_JTr : ARMPseudoInst<(outs),
1926 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1928 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1929 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1930 // into i12 and rs suffixed versions.
1931 def BR_JTm : ARMPseudoInst<(outs),
1932 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1934 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1936 def BR_JTadd : ARMPseudoInst<(outs),
1937 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1939 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1941 } // isNotDuplicable = 1, isIndirectBranch = 1
1947 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1948 "blx\t$target", []>,
1949 Requires<[IsARM, HasV5T]> {
1950 let Inst{31-25} = 0b1111101;
1952 let Inst{23-0} = target{24-1};
1953 let Inst{24} = target{0};
1956 // Branch and Exchange Jazelle
1957 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1958 [/* pattern left blank */]> {
1960 let Inst{23-20} = 0b0010;
1961 let Inst{19-8} = 0xfff;
1962 let Inst{7-4} = 0b0010;
1963 let Inst{3-0} = func;
1968 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1969 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
1971 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
1973 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
1975 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1978 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
1984 // Secure Monitor Call is a system instruction.
1985 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1988 let Inst{23-4} = 0b01100000000000000111;
1989 let Inst{3-0} = opt;
1992 // Supervisor Call (Software Interrupt)
1993 let isCall = 1, Uses = [SP] in {
1994 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1996 let Inst{23-0} = svc;
2000 // Store Return State
2001 class SRSI<bit wb, string asm>
2002 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2003 NoItinerary, asm, "", []> {
2005 let Inst{31-28} = 0b1111;
2006 let Inst{27-25} = 0b100;
2010 let Inst{19-16} = 0b1101; // SP
2011 let Inst{15-5} = 0b00000101000;
2012 let Inst{4-0} = mode;
2015 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2016 let Inst{24-23} = 0;
2018 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2019 let Inst{24-23} = 0;
2021 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2022 let Inst{24-23} = 0b10;
2024 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2025 let Inst{24-23} = 0b10;
2027 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2028 let Inst{24-23} = 0b01;
2030 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2031 let Inst{24-23} = 0b01;
2033 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2034 let Inst{24-23} = 0b11;
2036 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2037 let Inst{24-23} = 0b11;
2040 // Return From Exception
2041 class RFEI<bit wb, string asm>
2042 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2043 NoItinerary, asm, "", []> {
2045 let Inst{31-28} = 0b1111;
2046 let Inst{27-25} = 0b100;
2050 let Inst{19-16} = Rn;
2051 let Inst{15-0} = 0xa00;
2054 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2055 let Inst{24-23} = 0;
2057 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2058 let Inst{24-23} = 0;
2060 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2061 let Inst{24-23} = 0b10;
2063 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2064 let Inst{24-23} = 0b10;
2066 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2067 let Inst{24-23} = 0b01;
2069 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2070 let Inst{24-23} = 0b01;
2072 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2073 let Inst{24-23} = 0b11;
2075 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2076 let Inst{24-23} = 0b11;
2079 //===----------------------------------------------------------------------===//
2080 // Load / Store Instructions.
2086 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2087 UnOpFrag<(load node:$Src)>>;
2088 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2089 UnOpFrag<(zextloadi8 node:$Src)>>;
2090 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2091 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2092 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2093 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2095 // Special LDR for loads from non-pc-relative constpools.
2096 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2097 isReMaterializable = 1, isCodeGenOnly = 1 in
2098 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2099 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2103 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2104 let Inst{19-16} = 0b1111;
2105 let Inst{15-12} = Rt;
2106 let Inst{11-0} = addr{11-0}; // imm12
2109 // Loads with zero extension
2110 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2111 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2112 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2114 // Loads with sign extension
2115 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2116 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2117 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2119 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2120 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2121 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2123 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2125 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2126 (ins addrmode3:$addr), LdMiscFrm,
2127 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2128 []>, Requires<[IsARM, HasV5TE]>;
2132 multiclass AI2_ldridx<bit isByte, string opc,
2133 InstrItinClass iii, InstrItinClass iir> {
2134 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2135 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2136 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2139 let Inst{23} = addr{12};
2140 let Inst{19-16} = addr{16-13};
2141 let Inst{11-0} = addr{11-0};
2142 let DecoderMethod = "DecodeLDRPreImm";
2143 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2146 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2147 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2148 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2151 let Inst{23} = addr{12};
2152 let Inst{19-16} = addr{16-13};
2153 let Inst{11-0} = addr{11-0};
2155 let DecoderMethod = "DecodeLDRPreReg";
2156 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2159 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2160 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2161 IndexModePost, LdFrm, iir,
2162 opc, "\t$Rt, $addr, $offset",
2163 "$addr.base = $Rn_wb", []> {
2169 let Inst{23} = offset{12};
2170 let Inst{19-16} = addr;
2171 let Inst{11-0} = offset{11-0};
2173 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2176 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2177 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2178 IndexModePost, LdFrm, iii,
2179 opc, "\t$Rt, $addr, $offset",
2180 "$addr.base = $Rn_wb", []> {
2186 let Inst{23} = offset{12};
2187 let Inst{19-16} = addr;
2188 let Inst{11-0} = offset{11-0};
2190 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2195 let mayLoad = 1, neverHasSideEffects = 1 in {
2196 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2197 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2198 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2199 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2202 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2203 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2204 (ins addrmode3:$addr), IndexModePre,
2206 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2208 let Inst{23} = addr{8}; // U bit
2209 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2210 let Inst{19-16} = addr{12-9}; // Rn
2211 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2212 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2213 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2214 let DecoderMethod = "DecodeAddrMode3Instruction";
2216 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2217 (ins addr_offset_none:$addr, am3offset:$offset),
2218 IndexModePost, LdMiscFrm, itin,
2219 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2223 let Inst{23} = offset{8}; // U bit
2224 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2225 let Inst{19-16} = addr;
2226 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2227 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2228 let DecoderMethod = "DecodeAddrMode3Instruction";
2232 let mayLoad = 1, neverHasSideEffects = 1 in {
2233 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2234 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2235 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2236 let hasExtraDefRegAllocReq = 1 in {
2237 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2238 (ins addrmode3:$addr), IndexModePre,
2239 LdMiscFrm, IIC_iLoad_d_ru,
2240 "ldrd", "\t$Rt, $Rt2, $addr!",
2241 "$addr.base = $Rn_wb", []> {
2243 let Inst{23} = addr{8}; // U bit
2244 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2245 let Inst{19-16} = addr{12-9}; // Rn
2246 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2247 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2248 let DecoderMethod = "DecodeAddrMode3Instruction";
2249 let AsmMatchConverter = "cvtLdrdPre";
2251 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2252 (ins addr_offset_none:$addr, am3offset:$offset),
2253 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2254 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2255 "$addr.base = $Rn_wb", []> {
2258 let Inst{23} = offset{8}; // U bit
2259 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2260 let Inst{19-16} = addr;
2261 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2262 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2263 let DecoderMethod = "DecodeAddrMode3Instruction";
2265 } // hasExtraDefRegAllocReq = 1
2266 } // mayLoad = 1, neverHasSideEffects = 1
2268 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2269 let mayLoad = 1, neverHasSideEffects = 1 in {
2270 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2271 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2272 IndexModePost, LdFrm, IIC_iLoad_ru,
2273 "ldrt", "\t$Rt, $addr, $offset",
2274 "$addr.base = $Rn_wb", []> {
2280 let Inst{23} = offset{12};
2281 let Inst{21} = 1; // overwrite
2282 let Inst{19-16} = addr;
2283 let Inst{11-5} = offset{11-5};
2285 let Inst{3-0} = offset{3-0};
2286 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2289 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2290 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2291 IndexModePost, LdFrm, IIC_iLoad_ru,
2292 "ldrt", "\t$Rt, $addr, $offset",
2293 "$addr.base = $Rn_wb", []> {
2299 let Inst{23} = offset{12};
2300 let Inst{21} = 1; // overwrite
2301 let Inst{19-16} = addr;
2302 let Inst{11-0} = offset{11-0};
2303 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2306 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2307 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2308 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2309 "ldrbt", "\t$Rt, $addr, $offset",
2310 "$addr.base = $Rn_wb", []> {
2316 let Inst{23} = offset{12};
2317 let Inst{21} = 1; // overwrite
2318 let Inst{19-16} = addr;
2319 let Inst{11-5} = offset{11-5};
2321 let Inst{3-0} = offset{3-0};
2322 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2325 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2326 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2327 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2328 "ldrbt", "\t$Rt, $addr, $offset",
2329 "$addr.base = $Rn_wb", []> {
2335 let Inst{23} = offset{12};
2336 let Inst{21} = 1; // overwrite
2337 let Inst{19-16} = addr;
2338 let Inst{11-0} = offset{11-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 multiclass AI3ldrT<bits<4> op, string opc> {
2343 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2344 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2345 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2346 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2348 let Inst{23} = offset{8};
2350 let Inst{11-8} = offset{7-4};
2351 let Inst{3-0} = offset{3-0};
2352 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2354 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2355 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2356 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2357 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2359 let Inst{23} = Rm{4};
2362 let Unpredictable{11-8} = 0b1111;
2363 let Inst{3-0} = Rm{3-0};
2364 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2365 let DecoderMethod = "DecodeLDR";
2369 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2370 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2371 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2376 // Stores with truncate
2377 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2378 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2379 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2382 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2383 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2384 StMiscFrm, IIC_iStore_d_r,
2385 "strd", "\t$Rt, $src2, $addr", []>,
2386 Requires<[IsARM, HasV5TE]> {
2391 multiclass AI2_stridx<bit isByte, string opc,
2392 InstrItinClass iii, InstrItinClass iir> {
2393 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2394 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2396 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2399 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2400 let Inst{19-16} = addr{16-13}; // Rn
2401 let Inst{11-0} = addr{11-0}; // imm12
2402 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2403 let DecoderMethod = "DecodeSTRPreImm";
2406 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2407 (ins GPR:$Rt, ldst_so_reg:$addr),
2408 IndexModePre, StFrm, iir,
2409 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2413 let Inst{19-16} = addr{16-13}; // Rn
2414 let Inst{11-0} = addr{11-0};
2415 let Inst{4} = 0; // Inst{4} = 0
2416 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2417 let DecoderMethod = "DecodeSTRPreReg";
2419 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2420 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2421 IndexModePost, StFrm, iir,
2422 opc, "\t$Rt, $addr, $offset",
2423 "$addr.base = $Rn_wb", []> {
2429 let Inst{23} = offset{12};
2430 let Inst{19-16} = addr;
2431 let Inst{11-0} = offset{11-0};
2434 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2437 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2438 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2439 IndexModePost, StFrm, iii,
2440 opc, "\t$Rt, $addr, $offset",
2441 "$addr.base = $Rn_wb", []> {
2447 let Inst{23} = offset{12};
2448 let Inst{19-16} = addr;
2449 let Inst{11-0} = offset{11-0};
2451 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2455 let mayStore = 1, neverHasSideEffects = 1 in {
2456 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2457 // IIC_iStore_siu depending on whether it the offset register is shifted.
2458 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2459 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2462 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2463 am2offset_reg:$offset),
2464 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2465 am2offset_reg:$offset)>;
2466 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2467 am2offset_imm:$offset),
2468 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2469 am2offset_imm:$offset)>;
2470 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2471 am2offset_reg:$offset),
2472 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2473 am2offset_reg:$offset)>;
2474 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2475 am2offset_imm:$offset),
2476 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2477 am2offset_imm:$offset)>;
2479 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2480 // put the patterns on the instruction definitions directly as ISel wants
2481 // the address base and offset to be separate operands, not a single
2482 // complex operand like we represent the instructions themselves. The
2483 // pseudos map between the two.
2484 let usesCustomInserter = 1,
2485 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2486 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2487 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2490 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2491 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2492 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2495 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2496 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2497 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2500 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2501 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2502 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2505 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2506 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2507 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2510 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2515 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2516 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2517 StMiscFrm, IIC_iStore_bh_ru,
2518 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2520 let Inst{23} = addr{8}; // U bit
2521 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2522 let Inst{19-16} = addr{12-9}; // Rn
2523 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2524 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2525 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2526 let DecoderMethod = "DecodeAddrMode3Instruction";
2529 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2530 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2531 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2532 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2533 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2534 addr_offset_none:$addr,
2535 am3offset:$offset))]> {
2538 let Inst{23} = offset{8}; // U bit
2539 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2540 let Inst{19-16} = addr;
2541 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2542 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2543 let DecoderMethod = "DecodeAddrMode3Instruction";
2546 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2547 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2548 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2549 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2550 "strd", "\t$Rt, $Rt2, $addr!",
2551 "$addr.base = $Rn_wb", []> {
2553 let Inst{23} = addr{8}; // U bit
2554 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2555 let Inst{19-16} = addr{12-9}; // Rn
2556 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2557 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2558 let DecoderMethod = "DecodeAddrMode3Instruction";
2559 let AsmMatchConverter = "cvtStrdPre";
2562 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2563 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2565 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2566 "strd", "\t$Rt, $Rt2, $addr, $offset",
2567 "$addr.base = $Rn_wb", []> {
2570 let Inst{23} = offset{8}; // U bit
2571 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2572 let Inst{19-16} = addr;
2573 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2574 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2575 let DecoderMethod = "DecodeAddrMode3Instruction";
2577 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2579 // STRT, STRBT, and STRHT
2581 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2582 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2583 IndexModePost, StFrm, IIC_iStore_bh_ru,
2584 "strbt", "\t$Rt, $addr, $offset",
2585 "$addr.base = $Rn_wb", []> {
2591 let Inst{23} = offset{12};
2592 let Inst{21} = 1; // overwrite
2593 let Inst{19-16} = addr;
2594 let Inst{11-5} = offset{11-5};
2596 let Inst{3-0} = offset{3-0};
2597 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2600 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2601 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2602 IndexModePost, StFrm, IIC_iStore_bh_ru,
2603 "strbt", "\t$Rt, $addr, $offset",
2604 "$addr.base = $Rn_wb", []> {
2610 let Inst{23} = offset{12};
2611 let Inst{21} = 1; // overwrite
2612 let Inst{19-16} = addr;
2613 let Inst{11-0} = offset{11-0};
2614 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2617 let mayStore = 1, neverHasSideEffects = 1 in {
2618 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2619 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2620 IndexModePost, StFrm, IIC_iStore_ru,
2621 "strt", "\t$Rt, $addr, $offset",
2622 "$addr.base = $Rn_wb", []> {
2628 let Inst{23} = offset{12};
2629 let Inst{21} = 1; // overwrite
2630 let Inst{19-16} = addr;
2631 let Inst{11-5} = offset{11-5};
2633 let Inst{3-0} = offset{3-0};
2634 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2637 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2638 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2639 IndexModePost, StFrm, IIC_iStore_ru,
2640 "strt", "\t$Rt, $addr, $offset",
2641 "$addr.base = $Rn_wb", []> {
2647 let Inst{23} = offset{12};
2648 let Inst{21} = 1; // overwrite
2649 let Inst{19-16} = addr;
2650 let Inst{11-0} = offset{11-0};
2651 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2656 multiclass AI3strT<bits<4> op, string opc> {
2657 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2658 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2659 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2660 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2662 let Inst{23} = offset{8};
2664 let Inst{11-8} = offset{7-4};
2665 let Inst{3-0} = offset{3-0};
2666 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2668 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2669 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2670 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2671 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2673 let Inst{23} = Rm{4};
2676 let Inst{3-0} = Rm{3-0};
2677 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2682 defm STRHT : AI3strT<0b1011, "strht">;
2685 //===----------------------------------------------------------------------===//
2686 // Load / store multiple Instructions.
2689 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2690 InstrItinClass itin, InstrItinClass itin_upd> {
2691 // IA is the default, so no need for an explicit suffix on the
2692 // mnemonic here. Without it is the canonical spelling.
2694 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2695 IndexModeNone, f, itin,
2696 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2697 let Inst{24-23} = 0b01; // Increment After
2698 let Inst{22} = P_bit;
2699 let Inst{21} = 0; // No writeback
2700 let Inst{20} = L_bit;
2703 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2704 IndexModeUpd, f, itin_upd,
2705 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2706 let Inst{24-23} = 0b01; // Increment After
2707 let Inst{22} = P_bit;
2708 let Inst{21} = 1; // Writeback
2709 let Inst{20} = L_bit;
2711 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2714 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2715 IndexModeNone, f, itin,
2716 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2717 let Inst{24-23} = 0b00; // Decrement After
2718 let Inst{22} = P_bit;
2719 let Inst{21} = 0; // No writeback
2720 let Inst{20} = L_bit;
2723 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2724 IndexModeUpd, f, itin_upd,
2725 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2726 let Inst{24-23} = 0b00; // Decrement After
2727 let Inst{22} = P_bit;
2728 let Inst{21} = 1; // Writeback
2729 let Inst{20} = L_bit;
2731 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2734 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2735 IndexModeNone, f, itin,
2736 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2737 let Inst{24-23} = 0b10; // Decrement Before
2738 let Inst{22} = P_bit;
2739 let Inst{21} = 0; // No writeback
2740 let Inst{20} = L_bit;
2743 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2744 IndexModeUpd, f, itin_upd,
2745 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2746 let Inst{24-23} = 0b10; // Decrement Before
2747 let Inst{22} = P_bit;
2748 let Inst{21} = 1; // Writeback
2749 let Inst{20} = L_bit;
2751 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2754 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2755 IndexModeNone, f, itin,
2756 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2757 let Inst{24-23} = 0b11; // Increment Before
2758 let Inst{22} = P_bit;
2759 let Inst{21} = 0; // No writeback
2760 let Inst{20} = L_bit;
2763 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2764 IndexModeUpd, f, itin_upd,
2765 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2766 let Inst{24-23} = 0b11; // Increment Before
2767 let Inst{22} = P_bit;
2768 let Inst{21} = 1; // Writeback
2769 let Inst{20} = L_bit;
2771 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2775 let neverHasSideEffects = 1 in {
2777 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2778 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2781 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2782 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2785 } // neverHasSideEffects
2787 // FIXME: remove when we have a way to marking a MI with these properties.
2788 // FIXME: Should pc be an implicit operand like PICADD, etc?
2789 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2790 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2791 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2792 reglist:$regs, variable_ops),
2793 4, IIC_iLoad_mBr, [],
2794 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2795 RegConstraint<"$Rn = $wb">;
2797 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2798 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2801 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2802 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2807 //===----------------------------------------------------------------------===//
2808 // Move Instructions.
2811 let neverHasSideEffects = 1 in
2812 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2813 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2817 let Inst{19-16} = 0b0000;
2818 let Inst{11-4} = 0b00000000;
2821 let Inst{15-12} = Rd;
2824 // A version for the smaller set of tail call registers.
2825 let neverHasSideEffects = 1 in
2826 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2827 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2831 let Inst{11-4} = 0b00000000;
2834 let Inst{15-12} = Rd;
2837 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2838 DPSoRegRegFrm, IIC_iMOVsr,
2839 "mov", "\t$Rd, $src",
2840 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2843 let Inst{15-12} = Rd;
2844 let Inst{19-16} = 0b0000;
2845 let Inst{11-8} = src{11-8};
2847 let Inst{6-5} = src{6-5};
2849 let Inst{3-0} = src{3-0};
2853 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2854 DPSoRegImmFrm, IIC_iMOVsr,
2855 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2859 let Inst{15-12} = Rd;
2860 let Inst{19-16} = 0b0000;
2861 let Inst{11-5} = src{11-5};
2863 let Inst{3-0} = src{3-0};
2867 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2868 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2869 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2873 let Inst{15-12} = Rd;
2874 let Inst{19-16} = 0b0000;
2875 let Inst{11-0} = imm;
2878 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2879 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2881 "movw", "\t$Rd, $imm",
2882 [(set GPR:$Rd, imm0_65535:$imm)]>,
2883 Requires<[IsARM, HasV6T2]>, UnaryDP {
2886 let Inst{15-12} = Rd;
2887 let Inst{11-0} = imm{11-0};
2888 let Inst{19-16} = imm{15-12};
2891 let DecoderMethod = "DecodeArmMOVTWInstruction";
2894 def : InstAlias<"mov${p} $Rd, $imm",
2895 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2898 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2899 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2901 let Constraints = "$src = $Rd" in {
2902 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2903 (ins GPR:$src, imm0_65535_expr:$imm),
2905 "movt", "\t$Rd, $imm",
2907 (or (and GPR:$src, 0xffff),
2908 lo16AllZero:$imm))]>, UnaryDP,
2909 Requires<[IsARM, HasV6T2]> {
2912 let Inst{15-12} = Rd;
2913 let Inst{11-0} = imm{11-0};
2914 let Inst{19-16} = imm{15-12};
2917 let DecoderMethod = "DecodeArmMOVTWInstruction";
2920 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2921 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2925 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2926 Requires<[IsARM, HasV6T2]>;
2928 let Uses = [CPSR] in
2929 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2930 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2933 // These aren't really mov instructions, but we have to define them this way
2934 // due to flag operands.
2936 let Defs = [CPSR] in {
2937 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2938 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2940 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2941 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2945 //===----------------------------------------------------------------------===//
2946 // Extend Instructions.
2951 def SXTB : AI_ext_rrot<0b01101010,
2952 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2953 def SXTH : AI_ext_rrot<0b01101011,
2954 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2956 def SXTAB : AI_exta_rrot<0b01101010,
2957 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2958 def SXTAH : AI_exta_rrot<0b01101011,
2959 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2961 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2963 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2967 let AddedComplexity = 16 in {
2968 def UXTB : AI_ext_rrot<0b01101110,
2969 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2970 def UXTH : AI_ext_rrot<0b01101111,
2971 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2972 def UXTB16 : AI_ext_rrot<0b01101100,
2973 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2975 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2976 // The transformation should probably be done as a combiner action
2977 // instead so we can include a check for masking back in the upper
2978 // eight bits of the source into the lower eight bits of the result.
2979 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2980 // (UXTB16r_rot GPR:$Src, 3)>;
2981 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2982 (UXTB16 GPR:$Src, 1)>;
2984 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2985 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2986 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2987 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2990 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2991 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2994 def SBFX : I<(outs GPRnopc:$Rd),
2995 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
2996 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2997 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2998 Requires<[IsARM, HasV6T2]> {
3003 let Inst{27-21} = 0b0111101;
3004 let Inst{6-4} = 0b101;
3005 let Inst{20-16} = width;
3006 let Inst{15-12} = Rd;
3007 let Inst{11-7} = lsb;
3011 def UBFX : I<(outs GPR:$Rd),
3012 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3013 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3014 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3015 Requires<[IsARM, HasV6T2]> {
3020 let Inst{27-21} = 0b0111111;
3021 let Inst{6-4} = 0b101;
3022 let Inst{20-16} = width;
3023 let Inst{15-12} = Rd;
3024 let Inst{11-7} = lsb;
3028 //===----------------------------------------------------------------------===//
3029 // Arithmetic Instructions.
3032 defm ADD : AsI1_bin_irs<0b0100, "add",
3033 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3034 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3035 defm SUB : AsI1_bin_irs<0b0010, "sub",
3036 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3037 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3039 // ADD and SUB with 's' bit set.
3041 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3042 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3043 // AdjustInstrPostInstrSelection where we determine whether or not to
3044 // set the "s" bit based on CPSR liveness.
3046 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3047 // support for an optional CPSR definition that corresponds to the DAG
3048 // node's second value. We can then eliminate the implicit def of CPSR.
3049 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3050 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3051 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3052 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3054 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3055 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3056 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3057 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3059 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3060 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3061 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3063 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3064 // CPSR and the implicit def of CPSR is not needed.
3065 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3066 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3068 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3069 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3071 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3072 // The assume-no-carry-in form uses the negation of the input since add/sub
3073 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3074 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3076 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3077 (SUBri GPR:$src, so_imm_neg:$imm)>;
3078 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3079 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3081 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3082 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3083 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3084 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3086 // The with-carry-in form matches bitwise not instead of the negation.
3087 // Effectively, the inverse interpretation of the carry flag already accounts
3088 // for part of the negation.
3089 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3090 (SBCri GPR:$src, so_imm_not:$imm)>;
3092 // Note: These are implemented in C++ code, because they have to generate
3093 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3095 // (mul X, 2^n+1) -> (add (X << n), X)
3096 // (mul X, 2^n-1) -> (rsb X, (X << n))
3098 // ARM Arithmetic Instruction
3099 // GPR:$dst = GPR:$a op GPR:$b
3100 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3101 list<dag> pattern = [],
3102 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3103 string asm = "\t$Rd, $Rn, $Rm">
3104 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3108 let Inst{27-20} = op27_20;
3109 let Inst{11-4} = op11_4;
3110 let Inst{19-16} = Rn;
3111 let Inst{15-12} = Rd;
3114 let Unpredictable{11-8} = 0b1111;
3117 // Saturating add/subtract
3119 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3120 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3121 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3122 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3123 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3124 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3125 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3126 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3128 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3129 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3132 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3133 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3134 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3135 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3136 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3137 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3138 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3139 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3140 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3141 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3142 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3143 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3145 // Signed/Unsigned add/subtract
3147 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3148 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3149 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3150 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3151 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3152 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3153 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3154 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3155 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3156 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3157 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3158 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3160 // Signed/Unsigned halving add/subtract
3162 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3163 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3164 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3165 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3166 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3167 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3168 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3169 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3170 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3171 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3172 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3173 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3175 // Unsigned Sum of Absolute Differences [and Accumulate].
3177 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3178 MulFrm /* for convenience */, NoItinerary, "usad8",
3179 "\t$Rd, $Rn, $Rm", []>,
3180 Requires<[IsARM, HasV6]> {
3184 let Inst{27-20} = 0b01111000;
3185 let Inst{15-12} = 0b1111;
3186 let Inst{7-4} = 0b0001;
3187 let Inst{19-16} = Rd;
3188 let Inst{11-8} = Rm;
3191 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3192 MulFrm /* for convenience */, NoItinerary, "usada8",
3193 "\t$Rd, $Rn, $Rm, $Ra", []>,
3194 Requires<[IsARM, HasV6]> {
3199 let Inst{27-20} = 0b01111000;
3200 let Inst{7-4} = 0b0001;
3201 let Inst{19-16} = Rd;
3202 let Inst{15-12} = Ra;
3203 let Inst{11-8} = Rm;
3207 // Signed/Unsigned saturate
3209 def SSAT : AI<(outs GPRnopc:$Rd),
3210 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3211 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3216 let Inst{27-21} = 0b0110101;
3217 let Inst{5-4} = 0b01;
3218 let Inst{20-16} = sat_imm;
3219 let Inst{15-12} = Rd;
3220 let Inst{11-7} = sh{4-0};
3221 let Inst{6} = sh{5};
3225 def SSAT16 : AI<(outs GPRnopc:$Rd),
3226 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3227 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3231 let Inst{27-20} = 0b01101010;
3232 let Inst{11-4} = 0b11110011;
3233 let Inst{15-12} = Rd;
3234 let Inst{19-16} = sat_imm;
3238 def USAT : AI<(outs GPRnopc:$Rd),
3239 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3240 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3245 let Inst{27-21} = 0b0110111;
3246 let Inst{5-4} = 0b01;
3247 let Inst{15-12} = Rd;
3248 let Inst{11-7} = sh{4-0};
3249 let Inst{6} = sh{5};
3250 let Inst{20-16} = sat_imm;
3254 def USAT16 : AI<(outs GPRnopc:$Rd),
3255 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3256 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3260 let Inst{27-20} = 0b01101110;
3261 let Inst{11-4} = 0b11110011;
3262 let Inst{15-12} = Rd;
3263 let Inst{19-16} = sat_imm;
3267 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3268 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3269 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3270 (USAT imm:$pos, GPRnopc:$a, 0)>;
3272 //===----------------------------------------------------------------------===//
3273 // Bitwise Instructions.
3276 defm AND : AsI1_bin_irs<0b0000, "and",
3277 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3278 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3279 defm ORR : AsI1_bin_irs<0b1100, "orr",
3280 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3281 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3282 defm EOR : AsI1_bin_irs<0b0001, "eor",
3283 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3284 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3285 defm BIC : AsI1_bin_irs<0b1110, "bic",
3286 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3287 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3289 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3290 // like in the actual instruction encoding. The complexity of mapping the mask
3291 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3292 // instruction description.
3293 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3294 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3295 "bfc", "\t$Rd, $imm", "$src = $Rd",
3296 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3297 Requires<[IsARM, HasV6T2]> {
3300 let Inst{27-21} = 0b0111110;
3301 let Inst{6-0} = 0b0011111;
3302 let Inst{15-12} = Rd;
3303 let Inst{11-7} = imm{4-0}; // lsb
3304 let Inst{20-16} = imm{9-5}; // msb
3307 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3308 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3309 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3310 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3311 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3312 bf_inv_mask_imm:$imm))]>,
3313 Requires<[IsARM, HasV6T2]> {
3317 let Inst{27-21} = 0b0111110;
3318 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3319 let Inst{15-12} = Rd;
3320 let Inst{11-7} = imm{4-0}; // lsb
3321 let Inst{20-16} = imm{9-5}; // width
3325 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3326 "mvn", "\t$Rd, $Rm",
3327 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3331 let Inst{19-16} = 0b0000;
3332 let Inst{11-4} = 0b00000000;
3333 let Inst{15-12} = Rd;
3336 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3337 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3338 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3342 let Inst{19-16} = 0b0000;
3343 let Inst{15-12} = Rd;
3344 let Inst{11-5} = shift{11-5};
3346 let Inst{3-0} = shift{3-0};
3348 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3349 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3350 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3354 let Inst{19-16} = 0b0000;
3355 let Inst{15-12} = Rd;
3356 let Inst{11-8} = shift{11-8};
3358 let Inst{6-5} = shift{6-5};
3360 let Inst{3-0} = shift{3-0};
3362 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3363 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3364 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3365 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3369 let Inst{19-16} = 0b0000;
3370 let Inst{15-12} = Rd;
3371 let Inst{11-0} = imm;
3374 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3375 (BICri GPR:$src, so_imm_not:$imm)>;
3377 //===----------------------------------------------------------------------===//
3378 // Multiply Instructions.
3380 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3381 string opc, string asm, list<dag> pattern>
3382 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3386 let Inst{19-16} = Rd;
3387 let Inst{11-8} = Rm;
3390 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3391 string opc, string asm, list<dag> pattern>
3392 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3397 let Inst{19-16} = RdHi;
3398 let Inst{15-12} = RdLo;
3399 let Inst{11-8} = Rm;
3403 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3404 // property. Remove them when it's possible to add those properties
3405 // on an individual MachineInstr, not just an instruction description.
3406 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3407 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3408 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3409 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3410 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3411 Requires<[IsARM, HasV6]> {
3412 let Inst{15-12} = 0b0000;
3413 let Unpredictable{15-12} = 0b1111;
3416 let Constraints = "@earlyclobber $Rd" in
3417 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3418 pred:$p, cc_out:$s),
3420 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3421 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3422 Requires<[IsARM, NoV6]>;
3425 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3426 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3427 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3428 Requires<[IsARM, HasV6]> {
3430 let Inst{15-12} = Ra;
3433 let Constraints = "@earlyclobber $Rd" in
3434 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3435 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3437 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3438 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3439 Requires<[IsARM, NoV6]>;
3441 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3442 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3443 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3444 Requires<[IsARM, HasV6T2]> {
3449 let Inst{19-16} = Rd;
3450 let Inst{15-12} = Ra;
3451 let Inst{11-8} = Rm;
3455 // Extra precision multiplies with low / high results
3456 let neverHasSideEffects = 1 in {
3457 let isCommutable = 1 in {
3458 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3459 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3460 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3461 Requires<[IsARM, HasV6]>;
3463 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3464 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3465 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3466 Requires<[IsARM, HasV6]>;
3468 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3469 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3470 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3472 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3473 Requires<[IsARM, NoV6]>;
3475 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3476 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3478 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3479 Requires<[IsARM, NoV6]>;
3483 // Multiply + accumulate
3484 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3485 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3486 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3487 Requires<[IsARM, HasV6]>;
3488 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3489 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3490 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3491 Requires<[IsARM, HasV6]>;
3493 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3494 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3495 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3496 Requires<[IsARM, HasV6]> {
3501 let Inst{19-16} = RdHi;
3502 let Inst{15-12} = RdLo;
3503 let Inst{11-8} = Rm;
3507 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3508 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3509 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3511 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3512 Requires<[IsARM, NoV6]>;
3513 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3514 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3516 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3517 Requires<[IsARM, NoV6]>;
3518 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3519 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3521 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3522 Requires<[IsARM, NoV6]>;
3525 } // neverHasSideEffects
3527 // Most significant word multiply
3528 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3529 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3530 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3531 Requires<[IsARM, HasV6]> {
3532 let Inst{15-12} = 0b1111;
3535 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3536 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3537 Requires<[IsARM, HasV6]> {
3538 let Inst{15-12} = 0b1111;
3541 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3542 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3543 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3544 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3545 Requires<[IsARM, HasV6]>;
3547 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3548 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3549 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3550 Requires<[IsARM, HasV6]>;
3552 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3553 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3554 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3555 Requires<[IsARM, HasV6]>;
3557 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3558 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3559 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3560 Requires<[IsARM, HasV6]>;
3562 multiclass AI_smul<string opc, PatFrag opnode> {
3563 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3564 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3565 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3566 (sext_inreg GPR:$Rm, i16)))]>,
3567 Requires<[IsARM, HasV5TE]>;
3569 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3570 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3571 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3572 (sra GPR:$Rm, (i32 16))))]>,
3573 Requires<[IsARM, HasV5TE]>;
3575 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3576 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3577 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3578 (sext_inreg GPR:$Rm, i16)))]>,
3579 Requires<[IsARM, HasV5TE]>;
3581 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3582 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3583 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3584 (sra GPR:$Rm, (i32 16))))]>,
3585 Requires<[IsARM, HasV5TE]>;
3587 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3588 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3589 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3590 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3591 Requires<[IsARM, HasV5TE]>;
3593 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3594 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3595 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3596 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3597 Requires<[IsARM, HasV5TE]>;
3601 multiclass AI_smla<string opc, PatFrag opnode> {
3602 let DecoderMethod = "DecodeSMLAInstruction" in {
3603 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3604 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3605 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3606 [(set GPRnopc:$Rd, (add GPR:$Ra,
3607 (opnode (sext_inreg GPRnopc:$Rn, i16),
3608 (sext_inreg GPRnopc:$Rm, i16))))]>,
3609 Requires<[IsARM, HasV5TE]>;
3611 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3612 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3613 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3615 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3616 (sra GPRnopc:$Rm, (i32 16)))))]>,
3617 Requires<[IsARM, HasV5TE]>;
3619 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3620 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3621 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3623 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3624 (sext_inreg GPRnopc:$Rm, i16))))]>,
3625 Requires<[IsARM, HasV5TE]>;
3627 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3628 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3629 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3631 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3632 (sra GPRnopc:$Rm, (i32 16)))))]>,
3633 Requires<[IsARM, HasV5TE]>;
3635 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3636 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3637 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3639 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3640 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3641 Requires<[IsARM, HasV5TE]>;
3643 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3644 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3645 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3647 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3648 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3649 Requires<[IsARM, HasV5TE]>;
3653 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3654 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3656 // Halfword multiply accumulate long: SMLAL<x><y>.
3657 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3658 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3659 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3660 Requires<[IsARM, HasV5TE]>;
3662 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3663 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3664 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3665 Requires<[IsARM, HasV5TE]>;
3667 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3668 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3669 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3670 Requires<[IsARM, HasV5TE]>;
3672 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3673 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3674 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3675 Requires<[IsARM, HasV5TE]>;
3677 // Helper class for AI_smld.
3678 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3679 InstrItinClass itin, string opc, string asm>
3680 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3683 let Inst{27-23} = 0b01110;
3684 let Inst{22} = long;
3685 let Inst{21-20} = 0b00;
3686 let Inst{11-8} = Rm;
3693 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3694 InstrItinClass itin, string opc, string asm>
3695 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3697 let Inst{15-12} = 0b1111;
3698 let Inst{19-16} = Rd;
3700 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3701 InstrItinClass itin, string opc, string asm>
3702 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3705 let Inst{19-16} = Rd;
3706 let Inst{15-12} = Ra;
3708 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3709 InstrItinClass itin, string opc, string asm>
3710 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3713 let Inst{19-16} = RdHi;
3714 let Inst{15-12} = RdLo;
3717 multiclass AI_smld<bit sub, string opc> {
3719 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3720 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3721 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3723 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3724 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3725 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3727 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3728 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3729 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3731 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3732 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3733 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3737 defm SMLA : AI_smld<0, "smla">;
3738 defm SMLS : AI_smld<1, "smls">;
3740 multiclass AI_sdml<bit sub, string opc> {
3742 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3743 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3744 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3745 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3748 defm SMUA : AI_sdml<0, "smua">;
3749 defm SMUS : AI_sdml<1, "smus">;
3751 //===----------------------------------------------------------------------===//
3752 // Misc. Arithmetic Instructions.
3755 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3756 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3757 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3759 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3760 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3761 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3762 Requires<[IsARM, HasV6T2]>;
3764 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3765 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3766 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3768 let AddedComplexity = 5 in
3769 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3770 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3771 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3772 Requires<[IsARM, HasV6]>;
3774 let AddedComplexity = 5 in
3775 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3776 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3777 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3778 Requires<[IsARM, HasV6]>;
3780 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3781 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3784 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3785 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3786 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3787 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3788 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3790 Requires<[IsARM, HasV6]>;
3792 // Alternate cases for PKHBT where identities eliminate some nodes.
3793 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3794 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3795 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3796 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3798 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3799 // will match the pattern below.
3800 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3801 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3802 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3803 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3804 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3806 Requires<[IsARM, HasV6]>;
3808 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3809 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3810 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3811 (srl GPRnopc:$src2, imm16_31:$sh)),
3812 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3813 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3814 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3815 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3817 //===----------------------------------------------------------------------===//
3818 // Comparison Instructions...
3821 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3822 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3823 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3825 // ARMcmpZ can re-use the above instruction definitions.
3826 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3827 (CMPri GPR:$src, so_imm:$imm)>;
3828 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3829 (CMPrr GPR:$src, GPR:$rhs)>;
3830 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3831 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3832 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3833 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3835 // CMN register-integer
3836 let isCompare = 1, Defs = [CPSR] in {
3837 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3838 "cmn", "\t$Rn, $imm",
3839 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3844 let Inst{19-16} = Rn;
3845 let Inst{15-12} = 0b0000;
3846 let Inst{11-0} = imm;
3848 let Unpredictable{15-12} = 0b1111;
3851 // CMN register-register/shift
3852 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3853 "cmn", "\t$Rn, $Rm",
3854 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3855 GPR:$Rn, GPR:$Rm)]> {
3858 let isCommutable = 1;
3861 let Inst{19-16} = Rn;
3862 let Inst{15-12} = 0b0000;
3863 let Inst{11-4} = 0b00000000;
3866 let Unpredictable{15-12} = 0b1111;
3869 def CMNzrsi : AI1<0b1011, (outs),
3870 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3871 "cmn", "\t$Rn, $shift",
3872 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3873 GPR:$Rn, so_reg_imm:$shift)]> {
3878 let Inst{19-16} = Rn;
3879 let Inst{15-12} = 0b0000;
3880 let Inst{11-5} = shift{11-5};
3882 let Inst{3-0} = shift{3-0};
3884 let Unpredictable{15-12} = 0b1111;
3887 def CMNzrsr : AI1<0b1011, (outs),
3888 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3889 "cmn", "\t$Rn, $shift",
3890 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3891 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3896 let Inst{19-16} = Rn;
3897 let Inst{15-12} = 0b0000;
3898 let Inst{11-8} = shift{11-8};
3900 let Inst{6-5} = shift{6-5};
3902 let Inst{3-0} = shift{3-0};
3904 let Unpredictable{15-12} = 0b1111;
3909 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3910 (CMNri GPR:$src, so_imm_neg:$imm)>;
3912 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3913 (CMNri GPR:$src, so_imm_neg:$imm)>;
3915 // Note that TST/TEQ don't set all the same flags that CMP does!
3916 defm TST : AI1_cmp_irs<0b1000, "tst",
3917 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3918 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3919 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3920 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3921 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3923 // Pseudo i64 compares for some floating point compares.
3924 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3926 def BCCi64 : PseudoInst<(outs),
3927 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3929 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3931 def BCCZi64 : PseudoInst<(outs),
3932 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3933 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3934 } // usesCustomInserter
3937 // Conditional moves
3938 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3939 // a two-value operand where a dag node expects two operands. :(
3940 let neverHasSideEffects = 1 in {
3942 let isCommutable = 1, isSelect = 1 in
3943 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3945 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3946 RegConstraint<"$false = $Rd">;
3948 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3949 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3951 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3952 imm:$cc, CCR:$ccr))*/]>,
3953 RegConstraint<"$false = $Rd">;
3954 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3955 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3957 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3958 imm:$cc, CCR:$ccr))*/]>,
3959 RegConstraint<"$false = $Rd">;
3962 let isMoveImm = 1 in
3963 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3964 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3967 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3969 let isMoveImm = 1 in
3970 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3971 (ins GPR:$false, so_imm:$imm, pred:$p),
3973 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3974 RegConstraint<"$false = $Rd">;
3976 // Two instruction predicate mov immediate.
3977 let isMoveImm = 1 in
3978 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3979 (ins GPR:$false, i32imm:$src, pred:$p),
3980 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3982 let isMoveImm = 1 in
3983 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3984 (ins GPR:$false, so_imm:$imm, pred:$p),
3986 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3987 RegConstraint<"$false = $Rd">;
3989 // Conditional instructions
3990 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
3992 InstrItinClass iii, InstrItinClass iir,
3993 InstrItinClass iis> {
3994 def ri : ARMPseudoExpand<(outs GPR:$Rd),
3995 (ins GPR:$Rfalse, GPR:$Rn, so_imm:$imm,
3996 pred:$p, cc_out:$s),
3998 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
3999 RegConstraint<"$Rfalse = $Rd">;
4000 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4001 (ins GPR:$Rfalse, GPR:$Rn, GPR:$Rm,
4002 pred:$p, cc_out:$s),
4004 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4005 RegConstraint<"$Rfalse = $Rd">;
4006 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4007 (ins GPR:$Rfalse, GPR:$Rn, so_reg_imm:$shift,
4008 pred:$p, cc_out:$s),
4010 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4011 RegConstraint<"$Rfalse = $Rd">;
4012 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4013 (ins GPRnopc:$Rfalse, GPRnopc:$Rn, so_reg_reg:$shift,
4014 pred:$p, cc_out:$s),
4016 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4017 RegConstraint<"$Rfalse = $Rd">;
4020 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4021 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4022 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4023 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4024 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4025 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4027 } // neverHasSideEffects
4030 //===----------------------------------------------------------------------===//
4031 // Atomic operations intrinsics
4034 def MemBarrierOptOperand : AsmOperandClass {
4035 let Name = "MemBarrierOpt";
4036 let ParserMethod = "parseMemBarrierOptOperand";
4038 def memb_opt : Operand<i32> {
4039 let PrintMethod = "printMemBOption";
4040 let ParserMatchClass = MemBarrierOptOperand;
4041 let DecoderMethod = "DecodeMemBarrierOption";
4044 // memory barriers protect the atomic sequences
4045 let hasSideEffects = 1 in {
4046 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4047 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4048 Requires<[IsARM, HasDB]> {
4050 let Inst{31-4} = 0xf57ff05;
4051 let Inst{3-0} = opt;
4055 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4056 "dsb", "\t$opt", []>,
4057 Requires<[IsARM, HasDB]> {
4059 let Inst{31-4} = 0xf57ff04;
4060 let Inst{3-0} = opt;
4063 // ISB has only full system option
4064 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4065 "isb", "\t$opt", []>,
4066 Requires<[IsARM, HasDB]> {
4068 let Inst{31-4} = 0xf57ff06;
4069 let Inst{3-0} = opt;
4072 // Pseudo instruction that combines movs + predicated rsbmi
4073 // to implement integer ABS
4074 let usesCustomInserter = 1, Defs = [CPSR] in
4075 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4077 let usesCustomInserter = 1 in {
4078 let Defs = [CPSR] in {
4079 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4080 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4081 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4082 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4083 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4084 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4085 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4086 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4087 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4088 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4089 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4090 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4091 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4092 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4093 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4094 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4095 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4096 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4097 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4098 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4099 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4100 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4101 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4102 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4103 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4104 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4105 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4106 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4107 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4108 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4109 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4110 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4111 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4112 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4113 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4114 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4115 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4117 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4118 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4120 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4121 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4123 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4124 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4126 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4127 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4129 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4130 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4132 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4133 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4135 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4136 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4138 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4139 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4141 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4142 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4144 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4145 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4147 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4148 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4150 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4151 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4153 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4154 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4156 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4157 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4159 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4160 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4162 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4163 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4165 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4166 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4168 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4170 def ATOMIC_SWAP_I8 : PseudoInst<
4171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4172 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4173 def ATOMIC_SWAP_I16 : PseudoInst<
4174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4175 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4176 def ATOMIC_SWAP_I32 : PseudoInst<
4177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4178 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4180 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4182 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4183 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4185 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4186 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4188 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4192 let usesCustomInserter = 1 in {
4193 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4194 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4196 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4199 let mayLoad = 1 in {
4200 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4202 "ldrexb", "\t$Rt, $addr", []>;
4203 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4204 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4205 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4206 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4207 let hasExtraDefRegAllocReq = 1 in
4208 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4209 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4210 let DecoderMethod = "DecodeDoubleRegLoad";
4214 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4215 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4216 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4217 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4218 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4219 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4220 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4221 let hasExtraSrcRegAllocReq = 1 in
4222 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4223 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4224 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4225 let DecoderMethod = "DecodeDoubleRegStore";
4230 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4231 Requires<[IsARM, HasV7]> {
4232 let Inst{31-0} = 0b11110101011111111111000000011111;
4235 // SWP/SWPB are deprecated in V6/V7.
4236 let mayLoad = 1, mayStore = 1 in {
4237 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4238 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4239 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4240 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4243 //===----------------------------------------------------------------------===//
4244 // Coprocessor Instructions.
4247 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4248 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4249 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4250 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4251 imm:$CRm, imm:$opc2)]> {
4259 let Inst{3-0} = CRm;
4261 let Inst{7-5} = opc2;
4262 let Inst{11-8} = cop;
4263 let Inst{15-12} = CRd;
4264 let Inst{19-16} = CRn;
4265 let Inst{23-20} = opc1;
4268 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4269 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4270 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4271 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4272 imm:$CRm, imm:$opc2)]> {
4273 let Inst{31-28} = 0b1111;
4281 let Inst{3-0} = CRm;
4283 let Inst{7-5} = opc2;
4284 let Inst{11-8} = cop;
4285 let Inst{15-12} = CRd;
4286 let Inst{19-16} = CRn;
4287 let Inst{23-20} = opc1;
4290 class ACI<dag oops, dag iops, string opc, string asm,
4291 IndexMode im = IndexModeNone>
4292 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4294 let Inst{27-25} = 0b110;
4296 class ACInoP<dag oops, dag iops, string opc, string asm,
4297 IndexMode im = IndexModeNone>
4298 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4300 let Inst{31-28} = 0b1111;
4301 let Inst{27-25} = 0b110;
4303 multiclass LdStCop<bit load, bit Dbit, string asm> {
4304 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4305 asm, "\t$cop, $CRd, $addr"> {
4309 let Inst{24} = 1; // P = 1
4310 let Inst{23} = addr{8};
4311 let Inst{22} = Dbit;
4312 let Inst{21} = 0; // W = 0
4313 let Inst{20} = load;
4314 let Inst{19-16} = addr{12-9};
4315 let Inst{15-12} = CRd;
4316 let Inst{11-8} = cop;
4317 let Inst{7-0} = addr{7-0};
4318 let DecoderMethod = "DecodeCopMemInstruction";
4320 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4321 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4325 let Inst{24} = 1; // P = 1
4326 let Inst{23} = addr{8};
4327 let Inst{22} = Dbit;
4328 let Inst{21} = 1; // W = 1
4329 let Inst{20} = load;
4330 let Inst{19-16} = addr{12-9};
4331 let Inst{15-12} = CRd;
4332 let Inst{11-8} = cop;
4333 let Inst{7-0} = addr{7-0};
4334 let DecoderMethod = "DecodeCopMemInstruction";
4336 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4337 postidx_imm8s4:$offset),
4338 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4343 let Inst{24} = 0; // P = 0
4344 let Inst{23} = offset{8};
4345 let Inst{22} = Dbit;
4346 let Inst{21} = 1; // W = 1
4347 let Inst{20} = load;
4348 let Inst{19-16} = addr;
4349 let Inst{15-12} = CRd;
4350 let Inst{11-8} = cop;
4351 let Inst{7-0} = offset{7-0};
4352 let DecoderMethod = "DecodeCopMemInstruction";
4354 def _OPTION : ACI<(outs),
4355 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4356 coproc_option_imm:$option),
4357 asm, "\t$cop, $CRd, $addr, $option"> {
4362 let Inst{24} = 0; // P = 0
4363 let Inst{23} = 1; // U = 1
4364 let Inst{22} = Dbit;
4365 let Inst{21} = 0; // W = 0
4366 let Inst{20} = load;
4367 let Inst{19-16} = addr;
4368 let Inst{15-12} = CRd;
4369 let Inst{11-8} = cop;
4370 let Inst{7-0} = option;
4371 let DecoderMethod = "DecodeCopMemInstruction";
4374 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4375 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4376 asm, "\t$cop, $CRd, $addr"> {
4380 let Inst{24} = 1; // P = 1
4381 let Inst{23} = addr{8};
4382 let Inst{22} = Dbit;
4383 let Inst{21} = 0; // W = 0
4384 let Inst{20} = load;
4385 let Inst{19-16} = addr{12-9};
4386 let Inst{15-12} = CRd;
4387 let Inst{11-8} = cop;
4388 let Inst{7-0} = addr{7-0};
4389 let DecoderMethod = "DecodeCopMemInstruction";
4391 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4392 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4396 let Inst{24} = 1; // P = 1
4397 let Inst{23} = addr{8};
4398 let Inst{22} = Dbit;
4399 let Inst{21} = 1; // W = 1
4400 let Inst{20} = load;
4401 let Inst{19-16} = addr{12-9};
4402 let Inst{15-12} = CRd;
4403 let Inst{11-8} = cop;
4404 let Inst{7-0} = addr{7-0};
4405 let DecoderMethod = "DecodeCopMemInstruction";
4407 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4408 postidx_imm8s4:$offset),
4409 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4414 let Inst{24} = 0; // P = 0
4415 let Inst{23} = offset{8};
4416 let Inst{22} = Dbit;
4417 let Inst{21} = 1; // W = 1
4418 let Inst{20} = load;
4419 let Inst{19-16} = addr;
4420 let Inst{15-12} = CRd;
4421 let Inst{11-8} = cop;
4422 let Inst{7-0} = offset{7-0};
4423 let DecoderMethod = "DecodeCopMemInstruction";
4425 def _OPTION : ACInoP<(outs),
4426 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4427 coproc_option_imm:$option),
4428 asm, "\t$cop, $CRd, $addr, $option"> {
4433 let Inst{24} = 0; // P = 0
4434 let Inst{23} = 1; // U = 1
4435 let Inst{22} = Dbit;
4436 let Inst{21} = 0; // W = 0
4437 let Inst{20} = load;
4438 let Inst{19-16} = addr;
4439 let Inst{15-12} = CRd;
4440 let Inst{11-8} = cop;
4441 let Inst{7-0} = option;
4442 let DecoderMethod = "DecodeCopMemInstruction";
4446 defm LDC : LdStCop <1, 0, "ldc">;
4447 defm LDCL : LdStCop <1, 1, "ldcl">;
4448 defm STC : LdStCop <0, 0, "stc">;
4449 defm STCL : LdStCop <0, 1, "stcl">;
4450 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4451 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4452 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4453 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4455 //===----------------------------------------------------------------------===//
4456 // Move between coprocessor and ARM core register.
4459 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4461 : ABI<0b1110, oops, iops, NoItinerary, opc,
4462 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4463 let Inst{20} = direction;
4473 let Inst{15-12} = Rt;
4474 let Inst{11-8} = cop;
4475 let Inst{23-21} = opc1;
4476 let Inst{7-5} = opc2;
4477 let Inst{3-0} = CRm;
4478 let Inst{19-16} = CRn;
4481 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4483 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4484 c_imm:$CRm, imm0_7:$opc2),
4485 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4486 imm:$CRm, imm:$opc2)]>;
4487 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4488 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4489 c_imm:$CRm, 0, pred:$p)>;
4490 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4492 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4494 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4495 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4496 c_imm:$CRm, 0, pred:$p)>;
4498 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4499 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4501 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4503 : ABXI<0b1110, oops, iops, NoItinerary,
4504 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4505 let Inst{31-28} = 0b1111;
4506 let Inst{20} = direction;
4516 let Inst{15-12} = Rt;
4517 let Inst{11-8} = cop;
4518 let Inst{23-21} = opc1;
4519 let Inst{7-5} = opc2;
4520 let Inst{3-0} = CRm;
4521 let Inst{19-16} = CRn;
4524 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4526 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4527 c_imm:$CRm, imm0_7:$opc2),
4528 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4529 imm:$CRm, imm:$opc2)]>;
4530 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4531 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4533 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4535 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4537 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4538 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4541 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4542 imm:$CRm, imm:$opc2),
4543 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4545 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4546 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4547 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4548 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4549 let Inst{23-21} = 0b010;
4550 let Inst{20} = direction;
4558 let Inst{15-12} = Rt;
4559 let Inst{19-16} = Rt2;
4560 let Inst{11-8} = cop;
4561 let Inst{7-4} = opc1;
4562 let Inst{3-0} = CRm;
4565 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4566 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4567 GPRnopc:$Rt2, imm:$CRm)]>;
4568 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4570 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4571 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4572 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4573 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4574 let Inst{31-28} = 0b1111;
4575 let Inst{23-21} = 0b010;
4576 let Inst{20} = direction;
4584 let Inst{15-12} = Rt;
4585 let Inst{19-16} = Rt2;
4586 let Inst{11-8} = cop;
4587 let Inst{7-4} = opc1;
4588 let Inst{3-0} = CRm;
4590 let DecoderMethod = "DecodeMRRC2";
4593 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4594 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4595 GPRnopc:$Rt2, imm:$CRm)]>;
4596 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4598 //===----------------------------------------------------------------------===//
4599 // Move between special register and ARM core register
4602 // Move to ARM core register from Special Register
4603 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4604 "mrs", "\t$Rd, apsr", []> {
4606 let Inst{23-16} = 0b00001111;
4607 let Unpredictable{19-17} = 0b111;
4609 let Inst{15-12} = Rd;
4611 let Inst{11-0} = 0b000000000000;
4612 let Unpredictable{11-0} = 0b110100001111;
4615 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4618 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4619 // section B9.3.9, with the R bit set to 1.
4620 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4621 "mrs", "\t$Rd, spsr", []> {
4623 let Inst{23-16} = 0b01001111;
4624 let Unpredictable{19-16} = 0b1111;
4626 let Inst{15-12} = Rd;
4628 let Inst{11-0} = 0b000000000000;
4629 let Unpredictable{11-0} = 0b110100001111;
4632 // Move from ARM core register to Special Register
4634 // No need to have both system and application versions, the encodings are the
4635 // same and the assembly parser has no way to distinguish between them. The mask
4636 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4637 // the mask with the fields to be accessed in the special register.
4638 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4639 "msr", "\t$mask, $Rn", []> {
4644 let Inst{22} = mask{4}; // R bit
4645 let Inst{21-20} = 0b10;
4646 let Inst{19-16} = mask{3-0};
4647 let Inst{15-12} = 0b1111;
4648 let Inst{11-4} = 0b00000000;
4652 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4653 "msr", "\t$mask, $a", []> {
4658 let Inst{22} = mask{4}; // R bit
4659 let Inst{21-20} = 0b10;
4660 let Inst{19-16} = mask{3-0};
4661 let Inst{15-12} = 0b1111;
4665 //===----------------------------------------------------------------------===//
4669 // __aeabi_read_tp preserves the registers r1-r3.
4670 // This is a pseudo inst so that we can get the encoding right,
4671 // complete with fixup for the aeabi_read_tp function.
4673 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4674 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4675 [(set R0, ARMthread_pointer)]>;
4678 //===----------------------------------------------------------------------===//
4679 // SJLJ Exception handling intrinsics
4680 // eh_sjlj_setjmp() is an instruction sequence to store the return
4681 // address and save #0 in R0 for the non-longjmp case.
4682 // Since by its nature we may be coming from some other function to get
4683 // here, and we're using the stack frame for the containing function to
4684 // save/restore registers, we can't keep anything live in regs across
4685 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4686 // when we get here from a longjmp(). We force everything out of registers
4687 // except for our own input by listing the relevant registers in Defs. By
4688 // doing so, we also cause the prologue/epilogue code to actively preserve
4689 // all of the callee-saved resgisters, which is exactly what we want.
4690 // A constant value is passed in $val, and we use the location as a scratch.
4692 // These are pseudo-instructions and are lowered to individual MC-insts, so
4693 // no encoding information is necessary.
4695 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4696 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4697 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4698 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4700 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4701 Requires<[IsARM, HasVFP2]>;
4705 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4706 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4707 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4709 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4710 Requires<[IsARM, NoVFP]>;
4713 // FIXME: Non-IOS version(s)
4714 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4715 Defs = [ R7, LR, SP ] in {
4716 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4718 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4719 Requires<[IsARM, IsIOS]>;
4722 // eh.sjlj.dispatchsetup pseudo-instructions.
4723 // These pseudos are used for both ARM and Thumb2. Any differences are
4724 // handled when the pseudo is expanded (which happens before any passes
4725 // that need the instruction size).
4727 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4728 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4730 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4733 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4735 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4738 //===----------------------------------------------------------------------===//
4739 // Non-Instruction Patterns
4742 // ARMv4 indirect branch using (MOVr PC, dst)
4743 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4744 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4745 4, IIC_Br, [(brind GPR:$dst)],
4746 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4747 Requires<[IsARM, NoV4T]>;
4749 // Large immediate handling.
4751 // 32-bit immediate using two piece so_imms or movw + movt.
4752 // This is a single pseudo instruction, the benefit is that it can be remat'd
4753 // as a single unit instead of having to handle reg inputs.
4754 // FIXME: Remove this when we can do generalized remat.
4755 let isReMaterializable = 1, isMoveImm = 1 in
4756 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4757 [(set GPR:$dst, (arm_i32imm:$src))]>,
4760 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4761 // It also makes it possible to rematerialize the instructions.
4762 // FIXME: Remove this when we can do generalized remat and when machine licm
4763 // can properly the instructions.
4764 let isReMaterializable = 1 in {
4765 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4767 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4768 Requires<[IsARM, UseMovt]>;
4770 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4772 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4773 Requires<[IsARM, UseMovt]>;
4775 let AddedComplexity = 10 in
4776 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4778 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4779 Requires<[IsARM, UseMovt]>;
4780 } // isReMaterializable
4782 // ConstantPool, GlobalAddress, and JumpTable
4783 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4784 Requires<[IsARM, DontUseMovt]>;
4785 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4786 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4787 Requires<[IsARM, UseMovt]>;
4788 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4789 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4791 // TODO: add,sub,and, 3-instr forms?
4793 // Tail calls. These patterns also apply to Thumb mode.
4794 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4795 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4796 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4799 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4800 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4801 (BMOVPCB_CALL texternalsym:$func)>;
4803 // zextload i1 -> zextload i8
4804 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4805 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4807 // extload -> zextload
4808 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4809 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4810 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4811 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4813 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4815 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4816 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4819 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4820 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4821 (SMULBB GPR:$a, GPR:$b)>;
4822 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4823 (SMULBB GPR:$a, GPR:$b)>;
4824 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4825 (sra GPR:$b, (i32 16))),
4826 (SMULBT GPR:$a, GPR:$b)>;
4827 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4828 (SMULBT GPR:$a, GPR:$b)>;
4829 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4830 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4831 (SMULTB GPR:$a, GPR:$b)>;
4832 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4833 (SMULTB GPR:$a, GPR:$b)>;
4834 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4836 (SMULWB GPR:$a, GPR:$b)>;
4837 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4838 (SMULWB GPR:$a, GPR:$b)>;
4840 def : ARMV5TEPat<(add GPR:$acc,
4841 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4842 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4843 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4844 def : ARMV5TEPat<(add GPR:$acc,
4845 (mul sext_16_node:$a, sext_16_node:$b)),
4846 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4847 def : ARMV5TEPat<(add GPR:$acc,
4848 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4849 (sra GPR:$b, (i32 16)))),
4850 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4851 def : ARMV5TEPat<(add GPR:$acc,
4852 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4853 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4854 def : ARMV5TEPat<(add GPR:$acc,
4855 (mul (sra GPR:$a, (i32 16)),
4856 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4857 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4858 def : ARMV5TEPat<(add GPR:$acc,
4859 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4860 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4861 def : ARMV5TEPat<(add GPR:$acc,
4862 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4864 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4865 def : ARMV5TEPat<(add GPR:$acc,
4866 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4867 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4870 // Pre-v7 uses MCR for synchronization barriers.
4871 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4872 Requires<[IsARM, HasV6]>;
4874 // SXT/UXT with no rotate
4875 let AddedComplexity = 16 in {
4876 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4877 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4878 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4879 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4880 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4881 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4882 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4885 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4886 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4888 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4889 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4890 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4891 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4893 // Atomic load/store patterns
4894 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4895 (LDRBrs ldst_so_reg:$src)>;
4896 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4897 (LDRBi12 addrmode_imm12:$src)>;
4898 def : ARMPat<(atomic_load_16 addrmode3:$src),
4899 (LDRH addrmode3:$src)>;
4900 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4901 (LDRrs ldst_so_reg:$src)>;
4902 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4903 (LDRi12 addrmode_imm12:$src)>;
4904 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4905 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4906 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4907 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4908 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4909 (STRH GPR:$val, addrmode3:$ptr)>;
4910 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4911 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4912 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4913 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4916 //===----------------------------------------------------------------------===//
4920 include "ARMInstrThumb.td"
4922 //===----------------------------------------------------------------------===//
4926 include "ARMInstrThumb2.td"
4928 //===----------------------------------------------------------------------===//
4929 // Floating Point Support
4932 include "ARMInstrVFP.td"
4934 //===----------------------------------------------------------------------===//
4935 // Advanced SIMD (NEON) Support
4938 include "ARMInstrNEON.td"
4940 //===----------------------------------------------------------------------===//
4941 // Assembler aliases
4945 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4946 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4947 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4949 // System instructions
4950 def : MnemonicAlias<"swi", "svc">;
4952 // Load / Store Multiple
4953 def : MnemonicAlias<"ldmfd", "ldm">;
4954 def : MnemonicAlias<"ldmia", "ldm">;
4955 def : MnemonicAlias<"ldmea", "ldmdb">;
4956 def : MnemonicAlias<"stmfd", "stmdb">;
4957 def : MnemonicAlias<"stmia", "stm">;
4958 def : MnemonicAlias<"stmea", "stm">;
4960 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4961 // shift amount is zero (i.e., unspecified).
4962 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4963 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4964 Requires<[IsARM, HasV6]>;
4965 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4966 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4967 Requires<[IsARM, HasV6]>;
4969 // PUSH/POP aliases for STM/LDM
4970 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4971 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4973 // SSAT/USAT optional shift operand.
4974 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4975 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4976 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4977 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4980 // Extend instruction optional rotate operand.
4981 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4982 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4983 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4984 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4985 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4986 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4987 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4988 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4989 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4990 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4991 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4992 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4994 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4995 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4996 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4997 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4998 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4999 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5000 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5001 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5002 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5003 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5004 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5005 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5009 def : MnemonicAlias<"rfefa", "rfeda">;
5010 def : MnemonicAlias<"rfeea", "rfedb">;
5011 def : MnemonicAlias<"rfefd", "rfeia">;
5012 def : MnemonicAlias<"rfeed", "rfeib">;
5013 def : MnemonicAlias<"rfe", "rfeia">;
5016 def : MnemonicAlias<"srsfa", "srsda">;
5017 def : MnemonicAlias<"srsea", "srsdb">;
5018 def : MnemonicAlias<"srsfd", "srsia">;
5019 def : MnemonicAlias<"srsed", "srsib">;
5020 def : MnemonicAlias<"srs", "srsia">;
5023 def : MnemonicAlias<"qsubaddx", "qsax">;
5025 def : MnemonicAlias<"saddsubx", "sasx">;
5026 // SHASX == SHADDSUBX
5027 def : MnemonicAlias<"shaddsubx", "shasx">;
5028 // SHSAX == SHSUBADDX
5029 def : MnemonicAlias<"shsubaddx", "shsax">;
5031 def : MnemonicAlias<"ssubaddx", "ssax">;
5033 def : MnemonicAlias<"uaddsubx", "uasx">;
5034 // UHASX == UHADDSUBX
5035 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5036 // UHSAX == UHSUBADDX
5037 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5038 // UQASX == UQADDSUBX
5039 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5040 // UQSAX == UQSUBADDX
5041 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5043 def : MnemonicAlias<"usubaddx", "usax">;
5045 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5047 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5048 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5049 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5050 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5051 // Same for AND <--> BIC
5052 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5053 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5054 pred:$p, cc_out:$s)>;
5055 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5056 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5057 pred:$p, cc_out:$s)>;
5058 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5059 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5060 pred:$p, cc_out:$s)>;
5061 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5062 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5063 pred:$p, cc_out:$s)>;
5065 // Likewise, "add Rd, so_imm_neg" -> sub
5066 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5067 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5068 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5069 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5070 // Same for CMP <--> CMN via so_imm_neg
5071 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5072 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5073 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5074 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5076 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5077 // LSR, ROR, and RRX instructions.
5078 // FIXME: We need C++ parser hooks to map the alias to the MOV
5079 // encoding. It seems we should be able to do that sort of thing
5080 // in tblgen, but it could get ugly.
5081 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5082 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5083 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5085 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5086 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5088 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5089 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5091 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5092 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5095 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5096 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5097 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5098 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5099 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5101 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5102 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5104 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5105 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5107 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5108 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5112 // "neg" is and alias for "rsb rd, rn, #0"
5113 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5114 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5116 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5117 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5118 Requires<[IsARM, NoV6]>;
5120 // UMULL/SMULL are available on all arches, but the instruction definitions
5121 // need difference constraints pre-v6. Use these aliases for the assembly
5122 // parsing on pre-v6.
5123 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5124 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5125 Requires<[IsARM, NoV6]>;
5126 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5127 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5128 Requires<[IsARM, NoV6]>;
5130 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5132 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;