1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
74 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
76 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
79 SDTCisInt<0>, SDTCisVT<1, i32>]>;
81 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
82 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
89 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
90 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
91 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
92 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
93 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
96 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
97 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
98 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
100 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
101 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
102 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
103 [SDNPHasChain, SDNPSideEffect,
104 SDNPOptInGlue, SDNPOutGlue]>;
105 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
107 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
108 SDNPMayStore, SDNPMayLoad]>;
110 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
111 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
113 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
121 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
124 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
127 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
130 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
132 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
135 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
138 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
141 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
144 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
145 [SDNPOutGlue, SDNPCommutative]>;
147 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
149 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
150 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
153 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
155 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
156 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
157 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
159 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
160 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
161 SDT_ARMEH_SJLJ_Setjmp,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
164 SDT_ARMEH_SJLJ_Longjmp,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
177 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
179 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
180 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
182 //===----------------------------------------------------------------------===//
183 // ARM Instruction Predicate Definitions.
185 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
186 AssemblerPredicate<"HasV4TOps", "armv4t">;
187 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
188 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
189 AssemblerPredicate<"HasV5TOps", "armv5t">;
190 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
191 AssemblerPredicate<"HasV5TEOps", "armv5te">;
192 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
193 AssemblerPredicate<"HasV6Ops", "armv6">;
194 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
195 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
196 AssemblerPredicate<"HasV6MOps",
197 "armv6m or armv6t2">;
198 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
199 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
200 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
201 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
202 AssemblerPredicate<"HasV6KOps", "armv6k">;
203 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
204 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
205 AssemblerPredicate<"HasV7Ops", "armv7">;
206 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"HasV8Ops", "armv8">;
208 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
209 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
210 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
211 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
212 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
213 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
214 AssemblerPredicate<"FeatureVFP2", "VFP2">;
215 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
216 AssemblerPredicate<"FeatureVFP3", "VFP3">;
217 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
218 AssemblerPredicate<"FeatureVFP4", "VFP4">;
219 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
220 AssemblerPredicate<"!FeatureVFPOnlySP",
221 "double precision VFP">;
222 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
223 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
224 def HasNEON : Predicate<"Subtarget->hasNEON()">,
225 AssemblerPredicate<"FeatureNEON", "NEON">;
226 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
227 AssemblerPredicate<"FeatureCrypto", "crypto">;
228 def HasCRC : Predicate<"Subtarget->hasCRC()">,
229 AssemblerPredicate<"FeatureCRC", "crc">;
230 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
231 AssemblerPredicate<"FeatureFP16","half-float">;
232 def HasDivide : Predicate<"Subtarget->hasDivide()">,
233 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
234 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
235 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
236 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
237 AssemblerPredicate<"FeatureT2XtPk",
239 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
240 AssemblerPredicate<"FeatureDSPThumb2",
242 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
243 AssemblerPredicate<"FeatureDB",
245 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
246 AssemblerPredicate<"FeatureMP",
248 def HasVirtualization: Predicate<"false">,
249 AssemblerPredicate<"FeatureVirtualization",
250 "virtualization-extensions">;
251 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
252 AssemblerPredicate<"FeatureTrustZone",
254 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
255 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
256 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
257 def IsThumb : Predicate<"Subtarget->isThumb()">,
258 AssemblerPredicate<"ModeThumb", "thumb">;
259 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
260 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
261 AssemblerPredicate<"ModeThumb,FeatureThumb2",
263 def IsMClass : Predicate<"Subtarget->isMClass()">,
264 AssemblerPredicate<"FeatureMClass", "armv*m">;
265 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
266 AssemblerPredicate<"!FeatureMClass",
268 def IsARM : Predicate<"!Subtarget->isThumb()">,
269 AssemblerPredicate<"!ModeThumb", "arm-mode">;
270 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
271 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
272 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
273 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
274 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
275 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
277 // FIXME: Eventually this will be just "hasV6T2Ops".
278 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
279 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
280 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
281 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
283 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
284 // But only select them if more precision in FP computation is allowed.
285 // Do not use them for Darwin platforms.
286 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
287 " FPOpFusion::Fast && "
288 " Subtarget->hasVFP4()) && "
289 "!Subtarget->isTargetDarwin()">;
290 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
291 " FPOpFusion::Fast &&"
292 " Subtarget->hasVFP4()) || "
293 "Subtarget->isTargetDarwin()">;
295 // VGETLNi32 is microcoded on Swift - prefer VMOV.
296 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
297 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
299 // VDUP.32 is microcoded on Swift - prefer VMOV.
300 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
301 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
303 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
304 // this allows more effective execution domain optimization. See
305 // setExecutionDomain().
306 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
307 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
309 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
310 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
312 //===----------------------------------------------------------------------===//
313 // ARM Flag Definitions.
315 class RegConstraint<string C> {
316 string Constraints = C;
319 //===----------------------------------------------------------------------===//
320 // ARM specific transformation functions and pattern fragments.
323 // imm_neg_XFORM - Return the negation of an i32 immediate value.
324 def imm_neg_XFORM : SDNodeXForm<imm, [{
325 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
328 // imm_not_XFORM - Return the complement of a i32 immediate value.
329 def imm_not_XFORM : SDNodeXForm<imm, [{
330 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
333 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
334 def imm16_31 : ImmLeaf<i32, [{
335 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
338 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
339 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
340 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
343 /// Split a 32-bit immediate into two 16 bit parts.
344 def hi16 : SDNodeXForm<imm, [{
345 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
349 def lo16AllZero : PatLeaf<(i32 imm), [{
350 // Returns true if all low 16-bits are 0.
351 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
354 class BinOpWithFlagFrag<dag res> :
355 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
356 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
357 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
359 // An 'and' node with a single use.
360 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
361 return N->hasOneUse();
364 // An 'xor' node with a single use.
365 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
366 return N->hasOneUse();
369 // An 'fmul' node with a single use.
370 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
371 return N->hasOneUse();
374 // An 'fadd' node which checks for single non-hazardous use.
375 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
376 return hasNoVMLxHazardUse(N);
379 // An 'fsub' node which checks for single non-hazardous use.
380 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
381 return hasNoVMLxHazardUse(N);
384 //===----------------------------------------------------------------------===//
385 // Operand Definitions.
388 // Immediate operands with a shared generic asm render method.
389 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
391 // Operands that are part of a memory addressing mode.
392 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
395 // FIXME: rename brtarget to t2_brtarget
396 def brtarget : Operand<OtherVT> {
397 let EncoderMethod = "getBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
399 let DecoderMethod = "DecodeT2BROperand";
402 // FIXME: get rid of this one?
403 def uncondbrtarget : Operand<OtherVT> {
404 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
408 // Branch target for ARM. Handles conditional/unconditional
409 def br_target : Operand<OtherVT> {
410 let EncoderMethod = "getARMBranchTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
415 // FIXME: rename bltarget to t2_bl_target?
416 def bltarget : Operand<i32> {
417 // Encoded the same as branch targets.
418 let EncoderMethod = "getBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
422 // Call target for ARM. Handles conditional/unconditional
423 // FIXME: rename bl_target to t2_bltarget?
424 def bl_target : Operand<i32> {
425 let EncoderMethod = "getARMBLTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 def blx_target : Operand<i32> {
430 let EncoderMethod = "getARMBLXTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 // A list of registers separated by comma. Used by load/store multiple.
435 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
436 def reglist : Operand<i32> {
437 let EncoderMethod = "getRegisterListOpValue";
438 let ParserMatchClass = RegListAsmOperand;
439 let PrintMethod = "printRegisterList";
440 let DecoderMethod = "DecodeRegListOperand";
443 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
445 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
446 def dpr_reglist : Operand<i32> {
447 let EncoderMethod = "getRegisterListOpValue";
448 let ParserMatchClass = DPRRegListAsmOperand;
449 let PrintMethod = "printRegisterList";
450 let DecoderMethod = "DecodeDPRRegListOperand";
453 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
454 def spr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = SPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeSPRRegListOperand";
461 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
462 def cpinst_operand : Operand<i32> {
463 let PrintMethod = "printCPInstOperand";
467 def pclabel : Operand<i32> {
468 let PrintMethod = "printPCLabel";
471 // ADR instruction labels.
472 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
473 def adrlabel : Operand<i32> {
474 let EncoderMethod = "getAdrLabelOpValue";
475 let ParserMatchClass = AdrLabelAsmOperand;
476 let PrintMethod = "printAdrLabelOperand<0>";
479 def neon_vcvt_imm32 : Operand<i32> {
480 let EncoderMethod = "getNEONVcvtImm32OpValue";
481 let DecoderMethod = "DecodeVCVTImmOperand";
484 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
485 def rot_imm_XFORM: SDNodeXForm<imm, [{
486 switch (N->getZExtValue()){
487 default: llvm_unreachable(nullptr);
488 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
489 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
490 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
491 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
494 def RotImmAsmOperand : AsmOperandClass {
496 let ParserMethod = "parseRotImm";
498 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
499 int32_t v = N->getZExtValue();
500 return v == 8 || v == 16 || v == 24; }],
502 let PrintMethod = "printRotImmOperand";
503 let ParserMatchClass = RotImmAsmOperand;
506 // shift_imm: An integer that encodes a shift amount and the type of shift
507 // (asr or lsl). The 6-bit immediate encodes as:
510 // {4-0} imm5 shift amount.
511 // asr #32 encoded as imm5 == 0.
512 def ShifterImmAsmOperand : AsmOperandClass {
513 let Name = "ShifterImm";
514 let ParserMethod = "parseShifterImm";
516 def shift_imm : Operand<i32> {
517 let PrintMethod = "printShiftImmOperand";
518 let ParserMatchClass = ShifterImmAsmOperand;
521 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
522 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
523 def so_reg_reg : Operand<i32>, // reg reg imm
524 ComplexPattern<i32, 3, "SelectRegShifterOperand",
525 [shl, srl, sra, rotr]> {
526 let EncoderMethod = "getSORegRegOpValue";
527 let PrintMethod = "printSORegRegOperand";
528 let DecoderMethod = "DecodeSORegRegOperand";
529 let ParserMatchClass = ShiftedRegAsmOperand;
530 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
533 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
534 def so_reg_imm : Operand<i32>, // reg imm
535 ComplexPattern<i32, 2, "SelectImmShifterOperand",
536 [shl, srl, sra, rotr]> {
537 let EncoderMethod = "getSORegImmOpValue";
538 let PrintMethod = "printSORegImmOperand";
539 let DecoderMethod = "DecodeSORegImmOperand";
540 let ParserMatchClass = ShiftedImmAsmOperand;
541 let MIOperandInfo = (ops GPR, i32imm);
544 // FIXME: Does this need to be distinct from so_reg?
545 def shift_so_reg_reg : Operand<i32>, // reg reg imm
546 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
547 [shl,srl,sra,rotr]> {
548 let EncoderMethod = "getSORegRegOpValue";
549 let PrintMethod = "printSORegRegOperand";
550 let DecoderMethod = "DecodeSORegRegOperand";
551 let ParserMatchClass = ShiftedRegAsmOperand;
552 let MIOperandInfo = (ops GPR, GPR, i32imm);
555 // FIXME: Does this need to be distinct from so_reg?
556 def shift_so_reg_imm : Operand<i32>, // reg reg imm
557 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
558 [shl,srl,sra,rotr]> {
559 let EncoderMethod = "getSORegImmOpValue";
560 let PrintMethod = "printSORegImmOperand";
561 let DecoderMethod = "DecodeSORegImmOperand";
562 let ParserMatchClass = ShiftedImmAsmOperand;
563 let MIOperandInfo = (ops GPR, i32imm);
566 // mod_imm: match a 32-bit immediate operand, which can be encoded into
567 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
568 // - "Modified Immediate Constants"). Within the MC layer we keep this
569 // immediate in its encoded form.
570 def ModImmAsmOperand: AsmOperandClass {
572 let ParserMethod = "parseModImm";
574 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
575 return ARM_AM::getSOImmVal(Imm) != -1;
577 let EncoderMethod = "getModImmOpValue";
578 let PrintMethod = "printModImmOperand";
579 let ParserMatchClass = ModImmAsmOperand;
582 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
583 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
584 // The actual parsing, encoding, decoding are handled by the destination
585 // instructions, which use mod_imm.
587 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
588 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
589 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
591 let ParserMatchClass = ModImmNotAsmOperand;
594 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
595 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
596 unsigned Value = -(unsigned)N->getZExtValue();
597 return Value && ARM_AM::getSOImmVal(Value) != -1;
599 let ParserMatchClass = ModImmNegAsmOperand;
602 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
603 def arm_i32imm : PatLeaf<(imm), [{
604 if (Subtarget->useMovt(*MF))
606 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
609 /// imm0_1 predicate - Immediate in the range [0,1].
610 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
611 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
613 /// imm0_3 predicate - Immediate in the range [0,3].
614 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
615 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
617 /// imm0_7 predicate - Immediate in the range [0,7].
618 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
619 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
620 return Imm >= 0 && Imm < 8;
622 let ParserMatchClass = Imm0_7AsmOperand;
625 /// imm8 predicate - Immediate is exactly 8.
626 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
627 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
628 let ParserMatchClass = Imm8AsmOperand;
631 /// imm16 predicate - Immediate is exactly 16.
632 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
633 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
634 let ParserMatchClass = Imm16AsmOperand;
637 /// imm32 predicate - Immediate is exactly 32.
638 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
639 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
640 let ParserMatchClass = Imm32AsmOperand;
643 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
645 /// imm1_7 predicate - Immediate in the range [1,7].
646 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
647 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
648 let ParserMatchClass = Imm1_7AsmOperand;
651 /// imm1_15 predicate - Immediate in the range [1,15].
652 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
653 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
654 let ParserMatchClass = Imm1_15AsmOperand;
657 /// imm1_31 predicate - Immediate in the range [1,31].
658 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
659 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
660 let ParserMatchClass = Imm1_31AsmOperand;
663 /// imm0_15 predicate - Immediate in the range [0,15].
664 def Imm0_15AsmOperand: ImmAsmOperand {
665 let Name = "Imm0_15";
666 let DiagnosticType = "ImmRange0_15";
668 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 16;
671 let ParserMatchClass = Imm0_15AsmOperand;
674 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
675 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
676 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 32;
679 let ParserMatchClass = Imm0_31AsmOperand;
682 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
683 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
684 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 32;
687 let ParserMatchClass = Imm0_32AsmOperand;
690 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
691 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
692 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
693 return Imm >= 0 && Imm < 64;
695 let ParserMatchClass = Imm0_63AsmOperand;
698 /// imm0_239 predicate - Immediate in the range [0,239].
699 def Imm0_239AsmOperand : ImmAsmOperand {
700 let Name = "Imm0_239";
701 let DiagnosticType = "ImmRange0_239";
703 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
704 let ParserMatchClass = Imm0_239AsmOperand;
707 /// imm0_255 predicate - Immediate in the range [0,255].
708 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
709 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
710 let ParserMatchClass = Imm0_255AsmOperand;
713 /// imm0_65535 - An immediate is in the range [0.65535].
714 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
715 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
716 return Imm >= 0 && Imm < 65536;
718 let ParserMatchClass = Imm0_65535AsmOperand;
721 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
722 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
723 return -Imm >= 0 && -Imm < 65536;
726 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
727 // a relocatable expression.
729 // FIXME: This really needs a Thumb version separate from the ARM version.
730 // While the range is the same, and can thus use the same match class,
731 // the encoding is different so it should have a different encoder method.
732 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
733 def imm0_65535_expr : Operand<i32> {
734 let EncoderMethod = "getHiLo16ImmOpValue";
735 let ParserMatchClass = Imm0_65535ExprAsmOperand;
738 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
739 def imm256_65535_expr : Operand<i32> {
740 let ParserMatchClass = Imm256_65535ExprAsmOperand;
743 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
744 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
745 def imm24b : Operand<i32>, ImmLeaf<i32, [{
746 return Imm >= 0 && Imm <= 0xffffff;
748 let ParserMatchClass = Imm24bitAsmOperand;
752 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
754 def BitfieldAsmOperand : AsmOperandClass {
755 let Name = "Bitfield";
756 let ParserMethod = "parseBitfield";
759 def bf_inv_mask_imm : Operand<i32>,
761 return ARM::isBitFieldInvertedMask(N->getZExtValue());
763 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
764 let PrintMethod = "printBitfieldInvMaskImmOperand";
765 let DecoderMethod = "DecodeBitfieldMaskOperand";
766 let ParserMatchClass = BitfieldAsmOperand;
769 def imm1_32_XFORM: SDNodeXForm<imm, [{
770 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
773 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
774 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
775 uint64_t Imm = N->getZExtValue();
776 return Imm > 0 && Imm <= 32;
779 let PrintMethod = "printImmPlusOneOperand";
780 let ParserMatchClass = Imm1_32AsmOperand;
783 def imm1_16_XFORM: SDNodeXForm<imm, [{
784 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
787 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
788 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
790 let PrintMethod = "printImmPlusOneOperand";
791 let ParserMatchClass = Imm1_16AsmOperand;
794 // Define ARM specific addressing modes.
795 // addrmode_imm12 := reg +/- imm12
797 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
798 class AddrMode_Imm12 : MemOperand,
799 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
800 // 12-bit immediate operand. Note that instructions using this encode
801 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
802 // immediate values are as normal.
804 let EncoderMethod = "getAddrModeImm12OpValue";
805 let DecoderMethod = "DecodeAddrModeImm12Operand";
806 let ParserMatchClass = MemImm12OffsetAsmOperand;
807 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
810 def addrmode_imm12 : AddrMode_Imm12 {
811 let PrintMethod = "printAddrModeImm12Operand<false>";
814 def addrmode_imm12_pre : AddrMode_Imm12 {
815 let PrintMethod = "printAddrModeImm12Operand<true>";
818 // ldst_so_reg := reg +/- reg shop imm
820 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
821 def ldst_so_reg : MemOperand,
822 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
823 let EncoderMethod = "getLdStSORegOpValue";
824 // FIXME: Simplify the printer
825 let PrintMethod = "printAddrMode2Operand";
826 let DecoderMethod = "DecodeSORegMemOperand";
827 let ParserMatchClass = MemRegOffsetAsmOperand;
828 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
831 // postidx_imm8 := +/- [0,255]
834 // {8} 1 is imm8 is non-negative. 0 otherwise.
835 // {7-0} [0,255] imm8 value.
836 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
837 def postidx_imm8 : MemOperand {
838 let PrintMethod = "printPostIdxImm8Operand";
839 let ParserMatchClass = PostIdxImm8AsmOperand;
840 let MIOperandInfo = (ops i32imm);
843 // postidx_imm8s4 := +/- [0,1020]
846 // {8} 1 is imm8 is non-negative. 0 otherwise.
847 // {7-0} [0,255] imm8 value, scaled by 4.
848 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
849 def postidx_imm8s4 : MemOperand {
850 let PrintMethod = "printPostIdxImm8s4Operand";
851 let ParserMatchClass = PostIdxImm8s4AsmOperand;
852 let MIOperandInfo = (ops i32imm);
856 // postidx_reg := +/- reg
858 def PostIdxRegAsmOperand : AsmOperandClass {
859 let Name = "PostIdxReg";
860 let ParserMethod = "parsePostIdxReg";
862 def postidx_reg : MemOperand {
863 let EncoderMethod = "getPostIdxRegOpValue";
864 let DecoderMethod = "DecodePostIdxReg";
865 let PrintMethod = "printPostIdxRegOperand";
866 let ParserMatchClass = PostIdxRegAsmOperand;
867 let MIOperandInfo = (ops GPRnopc, i32imm);
871 // addrmode2 := reg +/- imm12
872 // := reg +/- reg shop imm
874 // FIXME: addrmode2 should be refactored the rest of the way to always
875 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
876 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
877 def addrmode2 : MemOperand,
878 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
879 let EncoderMethod = "getAddrMode2OpValue";
880 let PrintMethod = "printAddrMode2Operand";
881 let ParserMatchClass = AddrMode2AsmOperand;
882 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
885 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
886 let Name = "PostIdxRegShifted";
887 let ParserMethod = "parsePostIdxReg";
889 def am2offset_reg : MemOperand,
890 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
891 [], [SDNPWantRoot]> {
892 let EncoderMethod = "getAddrMode2OffsetOpValue";
893 let PrintMethod = "printAddrMode2OffsetOperand";
894 // When using this for assembly, it's always as a post-index offset.
895 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
896 let MIOperandInfo = (ops GPRnopc, i32imm);
899 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
900 // the GPR is purely vestigal at this point.
901 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
902 def am2offset_imm : MemOperand,
903 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
904 [], [SDNPWantRoot]> {
905 let EncoderMethod = "getAddrMode2OffsetOpValue";
906 let PrintMethod = "printAddrMode2OffsetOperand";
907 let ParserMatchClass = AM2OffsetImmAsmOperand;
908 let MIOperandInfo = (ops GPRnopc, i32imm);
912 // addrmode3 := reg +/- reg
913 // addrmode3 := reg +/- imm8
915 // FIXME: split into imm vs. reg versions.
916 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
917 class AddrMode3 : MemOperand,
918 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
919 let EncoderMethod = "getAddrMode3OpValue";
920 let ParserMatchClass = AddrMode3AsmOperand;
921 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
924 def addrmode3 : AddrMode3
926 let PrintMethod = "printAddrMode3Operand<false>";
929 def addrmode3_pre : AddrMode3
931 let PrintMethod = "printAddrMode3Operand<true>";
934 // FIXME: split into imm vs. reg versions.
935 // FIXME: parser method to handle +/- register.
936 def AM3OffsetAsmOperand : AsmOperandClass {
937 let Name = "AM3Offset";
938 let ParserMethod = "parseAM3Offset";
940 def am3offset : MemOperand,
941 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
942 [], [SDNPWantRoot]> {
943 let EncoderMethod = "getAddrMode3OffsetOpValue";
944 let PrintMethod = "printAddrMode3OffsetOperand";
945 let ParserMatchClass = AM3OffsetAsmOperand;
946 let MIOperandInfo = (ops GPR, i32imm);
949 // ldstm_mode := {ia, ib, da, db}
951 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
952 let EncoderMethod = "getLdStmModeOpValue";
953 let PrintMethod = "printLdStmModeOperand";
956 // addrmode5 := reg +/- imm8*4
958 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
959 class AddrMode5 : MemOperand,
960 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
961 let EncoderMethod = "getAddrMode5OpValue";
962 let DecoderMethod = "DecodeAddrMode5Operand";
963 let ParserMatchClass = AddrMode5AsmOperand;
964 let MIOperandInfo = (ops GPR:$base, i32imm);
967 def addrmode5 : AddrMode5 {
968 let PrintMethod = "printAddrMode5Operand<false>";
971 def addrmode5_pre : AddrMode5 {
972 let PrintMethod = "printAddrMode5Operand<true>";
975 // addrmode6 := reg with optional alignment
977 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
978 def addrmode6 : MemOperand,
979 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
980 let PrintMethod = "printAddrMode6Operand";
981 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
982 let EncoderMethod = "getAddrMode6AddressOpValue";
983 let DecoderMethod = "DecodeAddrMode6Operand";
984 let ParserMatchClass = AddrMode6AsmOperand;
987 def am6offset : MemOperand,
988 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
989 [], [SDNPWantRoot]> {
990 let PrintMethod = "printAddrMode6OffsetOperand";
991 let MIOperandInfo = (ops GPR);
992 let EncoderMethod = "getAddrMode6OffsetOpValue";
993 let DecoderMethod = "DecodeGPRRegisterClass";
996 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
997 // (single element from one lane) for size 32.
998 def addrmode6oneL32 : MemOperand,
999 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1000 let PrintMethod = "printAddrMode6Operand";
1001 let MIOperandInfo = (ops GPR:$addr, i32imm);
1002 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1005 // Base class for addrmode6 with specific alignment restrictions.
1006 class AddrMode6Align : MemOperand,
1007 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1008 let PrintMethod = "printAddrMode6Operand";
1009 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1010 let EncoderMethod = "getAddrMode6AddressOpValue";
1011 let DecoderMethod = "DecodeAddrMode6Operand";
1014 // Special version of addrmode6 to handle no allowed alignment encoding for
1015 // VLD/VST instructions and checking the alignment is not specified.
1016 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1017 let Name = "AlignedMemoryNone";
1018 let DiagnosticType = "AlignedMemoryRequiresNone";
1020 def addrmode6alignNone : AddrMode6Align {
1021 // The alignment specifier can only be omitted.
1022 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1025 // Special version of addrmode6 to handle 16-bit alignment encoding for
1026 // VLD/VST instructions and checking the alignment value.
1027 def AddrMode6Align16AsmOperand : AsmOperandClass {
1028 let Name = "AlignedMemory16";
1029 let DiagnosticType = "AlignedMemoryRequires16";
1031 def addrmode6align16 : AddrMode6Align {
1032 // The alignment specifier can only be 16 or omitted.
1033 let ParserMatchClass = AddrMode6Align16AsmOperand;
1036 // Special version of addrmode6 to handle 32-bit alignment encoding for
1037 // VLD/VST instructions and checking the alignment value.
1038 def AddrMode6Align32AsmOperand : AsmOperandClass {
1039 let Name = "AlignedMemory32";
1040 let DiagnosticType = "AlignedMemoryRequires32";
1042 def addrmode6align32 : AddrMode6Align {
1043 // The alignment specifier can only be 32 or omitted.
1044 let ParserMatchClass = AddrMode6Align32AsmOperand;
1047 // Special version of addrmode6 to handle 64-bit alignment encoding for
1048 // VLD/VST instructions and checking the alignment value.
1049 def AddrMode6Align64AsmOperand : AsmOperandClass {
1050 let Name = "AlignedMemory64";
1051 let DiagnosticType = "AlignedMemoryRequires64";
1053 def addrmode6align64 : AddrMode6Align {
1054 // The alignment specifier can only be 64 or omitted.
1055 let ParserMatchClass = AddrMode6Align64AsmOperand;
1058 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1059 // for VLD/VST instructions and checking the alignment value.
1060 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1061 let Name = "AlignedMemory64or128";
1062 let DiagnosticType = "AlignedMemoryRequires64or128";
1064 def addrmode6align64or128 : AddrMode6Align {
1065 // The alignment specifier can only be 64, 128 or omitted.
1066 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1069 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1070 // encoding for VLD/VST instructions and checking the alignment value.
1071 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1072 let Name = "AlignedMemory64or128or256";
1073 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1075 def addrmode6align64or128or256 : AddrMode6Align {
1076 // The alignment specifier can only be 64, 128, 256 or omitted.
1077 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1080 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1081 // instructions, specifically VLD4-dup.
1082 def addrmode6dup : MemOperand,
1083 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1084 let PrintMethod = "printAddrMode6Operand";
1085 let MIOperandInfo = (ops GPR:$addr, i32imm);
1086 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1087 // FIXME: This is close, but not quite right. The alignment specifier is
1089 let ParserMatchClass = AddrMode6AsmOperand;
1092 // Base class for addrmode6dup with specific alignment restrictions.
1093 class AddrMode6DupAlign : MemOperand,
1094 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1095 let PrintMethod = "printAddrMode6Operand";
1096 let MIOperandInfo = (ops GPR:$addr, i32imm);
1097 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1100 // Special version of addrmode6 to handle no allowed alignment encoding for
1101 // VLD-dup instruction and checking the alignment is not specified.
1102 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1103 let Name = "DupAlignedMemoryNone";
1104 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1106 def addrmode6dupalignNone : AddrMode6DupAlign {
1107 // The alignment specifier can only be omitted.
1108 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1111 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1112 // instruction and checking the alignment value.
1113 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1114 let Name = "DupAlignedMemory16";
1115 let DiagnosticType = "DupAlignedMemoryRequires16";
1117 def addrmode6dupalign16 : AddrMode6DupAlign {
1118 // The alignment specifier can only be 16 or omitted.
1119 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1122 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1123 // instruction and checking the alignment value.
1124 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1125 let Name = "DupAlignedMemory32";
1126 let DiagnosticType = "DupAlignedMemoryRequires32";
1128 def addrmode6dupalign32 : AddrMode6DupAlign {
1129 // The alignment specifier can only be 32 or omitted.
1130 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1133 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1134 // instructions and checking the alignment value.
1135 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1136 let Name = "DupAlignedMemory64";
1137 let DiagnosticType = "DupAlignedMemoryRequires64";
1139 def addrmode6dupalign64 : AddrMode6DupAlign {
1140 // The alignment specifier can only be 64 or omitted.
1141 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1144 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1145 // for VLD instructions and checking the alignment value.
1146 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1147 let Name = "DupAlignedMemory64or128";
1148 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1150 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1151 // The alignment specifier can only be 64, 128 or omitted.
1152 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1155 // addrmodepc := pc + reg
1157 def addrmodepc : MemOperand,
1158 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1159 let PrintMethod = "printAddrModePCOperand";
1160 let MIOperandInfo = (ops GPR, i32imm);
1163 // addr_offset_none := reg
1165 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1166 def addr_offset_none : MemOperand,
1167 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1168 let PrintMethod = "printAddrMode7Operand";
1169 let DecoderMethod = "DecodeAddrMode7Operand";
1170 let ParserMatchClass = MemNoOffsetAsmOperand;
1171 let MIOperandInfo = (ops GPR:$base);
1174 def nohash_imm : Operand<i32> {
1175 let PrintMethod = "printNoHashImmediate";
1178 def CoprocNumAsmOperand : AsmOperandClass {
1179 let Name = "CoprocNum";
1180 let ParserMethod = "parseCoprocNumOperand";
1182 def p_imm : Operand<i32> {
1183 let PrintMethod = "printPImmediate";
1184 let ParserMatchClass = CoprocNumAsmOperand;
1185 let DecoderMethod = "DecodeCoprocessor";
1188 def CoprocRegAsmOperand : AsmOperandClass {
1189 let Name = "CoprocReg";
1190 let ParserMethod = "parseCoprocRegOperand";
1192 def c_imm : Operand<i32> {
1193 let PrintMethod = "printCImmediate";
1194 let ParserMatchClass = CoprocRegAsmOperand;
1196 def CoprocOptionAsmOperand : AsmOperandClass {
1197 let Name = "CoprocOption";
1198 let ParserMethod = "parseCoprocOptionOperand";
1200 def coproc_option_imm : Operand<i32> {
1201 let PrintMethod = "printCoprocOptionImm";
1202 let ParserMatchClass = CoprocOptionAsmOperand;
1205 //===----------------------------------------------------------------------===//
1207 include "ARMInstrFormats.td"
1209 //===----------------------------------------------------------------------===//
1210 // Multiclass helpers...
1213 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1214 /// binop that produces a value.
1215 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1216 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1217 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1218 PatFrag opnode, bit Commutable = 0> {
1219 // The register-immediate version is re-materializable. This is useful
1220 // in particular for taking the address of a local.
1221 let isReMaterializable = 1 in {
1222 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1223 iii, opc, "\t$Rd, $Rn, $imm",
1224 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1225 Sched<[WriteALU, ReadALU]> {
1230 let Inst{19-16} = Rn;
1231 let Inst{15-12} = Rd;
1232 let Inst{11-0} = imm;
1235 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1236 iir, opc, "\t$Rd, $Rn, $Rm",
1237 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1238 Sched<[WriteALU, ReadALU, ReadALU]> {
1243 let isCommutable = Commutable;
1244 let Inst{19-16} = Rn;
1245 let Inst{15-12} = Rd;
1246 let Inst{11-4} = 0b00000000;
1250 def rsi : AsI1<opcod, (outs GPR:$Rd),
1251 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1252 iis, opc, "\t$Rd, $Rn, $shift",
1253 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1254 Sched<[WriteALUsi, ReadALU]> {
1259 let Inst{19-16} = Rn;
1260 let Inst{15-12} = Rd;
1261 let Inst{11-5} = shift{11-5};
1263 let Inst{3-0} = shift{3-0};
1266 def rsr : AsI1<opcod, (outs GPR:$Rd),
1267 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1268 iis, opc, "\t$Rd, $Rn, $shift",
1269 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1270 Sched<[WriteALUsr, ReadALUsr]> {
1275 let Inst{19-16} = Rn;
1276 let Inst{15-12} = Rd;
1277 let Inst{11-8} = shift{11-8};
1279 let Inst{6-5} = shift{6-5};
1281 let Inst{3-0} = shift{3-0};
1285 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1286 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1287 /// it is equivalent to the AsI1_bin_irs counterpart.
1288 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1289 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1290 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1291 PatFrag opnode, bit Commutable = 0> {
1292 // The register-immediate version is re-materializable. This is useful
1293 // in particular for taking the address of a local.
1294 let isReMaterializable = 1 in {
1295 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1296 iii, opc, "\t$Rd, $Rn, $imm",
1297 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1298 Sched<[WriteALU, ReadALU]> {
1303 let Inst{19-16} = Rn;
1304 let Inst{15-12} = Rd;
1305 let Inst{11-0} = imm;
1308 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1309 iir, opc, "\t$Rd, $Rn, $Rm",
1310 [/* pattern left blank */]>,
1311 Sched<[WriteALU, ReadALU, ReadALU]> {
1315 let Inst{11-4} = 0b00000000;
1318 let Inst{15-12} = Rd;
1319 let Inst{19-16} = Rn;
1322 def rsi : AsI1<opcod, (outs GPR:$Rd),
1323 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1324 iis, opc, "\t$Rd, $Rn, $shift",
1325 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1326 Sched<[WriteALUsi, ReadALU]> {
1331 let Inst{19-16} = Rn;
1332 let Inst{15-12} = Rd;
1333 let Inst{11-5} = shift{11-5};
1335 let Inst{3-0} = shift{3-0};
1338 def rsr : AsI1<opcod, (outs GPR:$Rd),
1339 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1340 iis, opc, "\t$Rd, $Rn, $shift",
1341 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1342 Sched<[WriteALUsr, ReadALUsr]> {
1347 let Inst{19-16} = Rn;
1348 let Inst{15-12} = Rd;
1349 let Inst{11-8} = shift{11-8};
1351 let Inst{6-5} = shift{6-5};
1353 let Inst{3-0} = shift{3-0};
1357 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1359 /// These opcodes will be converted to the real non-S opcodes by
1360 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1361 let hasPostISelHook = 1, Defs = [CPSR] in {
1362 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1363 InstrItinClass iis, PatFrag opnode,
1364 bit Commutable = 0> {
1365 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1367 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1368 Sched<[WriteALU, ReadALU]>;
1370 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1372 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1373 Sched<[WriteALU, ReadALU, ReadALU]> {
1374 let isCommutable = Commutable;
1376 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1377 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1379 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1380 so_reg_imm:$shift))]>,
1381 Sched<[WriteALUsi, ReadALU]>;
1383 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1384 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1386 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1387 so_reg_reg:$shift))]>,
1388 Sched<[WriteALUSsr, ReadALUsr]>;
1392 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1393 /// operands are reversed.
1394 let hasPostISelHook = 1, Defs = [CPSR] in {
1395 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1396 InstrItinClass iis, PatFrag opnode,
1397 bit Commutable = 0> {
1398 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1400 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1401 Sched<[WriteALU, ReadALU]>;
1403 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1404 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1406 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1408 Sched<[WriteALUsi, ReadALU]>;
1410 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1411 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1413 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1415 Sched<[WriteALUSsr, ReadALUsr]>;
1419 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1420 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1421 /// a explicit result, only implicitly set CPSR.
1422 let isCompare = 1, Defs = [CPSR] in {
1423 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1424 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1425 PatFrag opnode, bit Commutable = 0,
1426 string rrDecoderMethod = ""> {
1427 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1429 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1430 Sched<[WriteCMP, ReadALU]> {
1435 let Inst{19-16} = Rn;
1436 let Inst{15-12} = 0b0000;
1437 let Inst{11-0} = imm;
1439 let Unpredictable{15-12} = 0b1111;
1441 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1443 [(opnode GPR:$Rn, GPR:$Rm)]>,
1444 Sched<[WriteCMP, ReadALU, ReadALU]> {
1447 let isCommutable = Commutable;
1450 let Inst{19-16} = Rn;
1451 let Inst{15-12} = 0b0000;
1452 let Inst{11-4} = 0b00000000;
1454 let DecoderMethod = rrDecoderMethod;
1456 let Unpredictable{15-12} = 0b1111;
1458 def rsi : AI1<opcod, (outs),
1459 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1460 opc, "\t$Rn, $shift",
1461 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1462 Sched<[WriteCMPsi, ReadALU]> {
1467 let Inst{19-16} = Rn;
1468 let Inst{15-12} = 0b0000;
1469 let Inst{11-5} = shift{11-5};
1471 let Inst{3-0} = shift{3-0};
1473 let Unpredictable{15-12} = 0b1111;
1475 def rsr : AI1<opcod, (outs),
1476 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1477 opc, "\t$Rn, $shift",
1478 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1479 Sched<[WriteCMPsr, ReadALU]> {
1484 let Inst{19-16} = Rn;
1485 let Inst{15-12} = 0b0000;
1486 let Inst{11-8} = shift{11-8};
1488 let Inst{6-5} = shift{6-5};
1490 let Inst{3-0} = shift{3-0};
1492 let Unpredictable{15-12} = 0b1111;
1498 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1499 /// register and one whose operand is a register rotated by 8/16/24.
1500 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1501 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1502 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1503 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1504 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1505 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1509 let Inst{19-16} = 0b1111;
1510 let Inst{15-12} = Rd;
1511 let Inst{11-10} = rot;
1515 class AI_ext_rrot_np<bits<8> opcod, string opc>
1516 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1517 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1518 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1520 let Inst{19-16} = 0b1111;
1521 let Inst{11-10} = rot;
1524 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1525 /// register and one whose operand is a register rotated by 8/16/24.
1526 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1527 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1528 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1529 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1530 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1531 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1536 let Inst{19-16} = Rn;
1537 let Inst{15-12} = Rd;
1538 let Inst{11-10} = rot;
1539 let Inst{9-4} = 0b000111;
1543 class AI_exta_rrot_np<bits<8> opcod, string opc>
1544 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1545 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1546 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1549 let Inst{19-16} = Rn;
1550 let Inst{11-10} = rot;
1553 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1554 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1555 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1556 bit Commutable = 0> {
1557 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1558 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1559 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1560 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1562 Sched<[WriteALU, ReadALU]> {
1567 let Inst{15-12} = Rd;
1568 let Inst{19-16} = Rn;
1569 let Inst{11-0} = imm;
1571 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1572 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1573 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1575 Sched<[WriteALU, ReadALU, ReadALU]> {
1579 let Inst{11-4} = 0b00000000;
1581 let isCommutable = Commutable;
1583 let Inst{15-12} = Rd;
1584 let Inst{19-16} = Rn;
1586 def rsi : AsI1<opcod, (outs GPR:$Rd),
1587 (ins GPR:$Rn, so_reg_imm:$shift),
1588 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1589 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1591 Sched<[WriteALUsi, ReadALU]> {
1596 let Inst{19-16} = Rn;
1597 let Inst{15-12} = Rd;
1598 let Inst{11-5} = shift{11-5};
1600 let Inst{3-0} = shift{3-0};
1602 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1603 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1604 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1605 [(set GPRnopc:$Rd, CPSR,
1606 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1608 Sched<[WriteALUsr, ReadALUsr]> {
1613 let Inst{19-16} = Rn;
1614 let Inst{15-12} = Rd;
1615 let Inst{11-8} = shift{11-8};
1617 let Inst{6-5} = shift{6-5};
1619 let Inst{3-0} = shift{3-0};
1624 /// AI1_rsc_irs - Define instructions and patterns for rsc
1625 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1626 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1627 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1628 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1629 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1630 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1632 Sched<[WriteALU, ReadALU]> {
1637 let Inst{15-12} = Rd;
1638 let Inst{19-16} = Rn;
1639 let Inst{11-0} = imm;
1641 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1642 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1643 [/* pattern left blank */]>,
1644 Sched<[WriteALU, ReadALU, ReadALU]> {
1648 let Inst{11-4} = 0b00000000;
1651 let Inst{15-12} = Rd;
1652 let Inst{19-16} = Rn;
1654 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1655 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1656 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1658 Sched<[WriteALUsi, ReadALU]> {
1663 let Inst{19-16} = Rn;
1664 let Inst{15-12} = Rd;
1665 let Inst{11-5} = shift{11-5};
1667 let Inst{3-0} = shift{3-0};
1669 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1670 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1671 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1673 Sched<[WriteALUsr, ReadALUsr]> {
1678 let Inst{19-16} = Rn;
1679 let Inst{15-12} = Rd;
1680 let Inst{11-8} = shift{11-8};
1682 let Inst{6-5} = shift{6-5};
1684 let Inst{3-0} = shift{3-0};
1689 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1690 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1691 InstrItinClass iir, PatFrag opnode> {
1692 // Note: We use the complex addrmode_imm12 rather than just an input
1693 // GPR and a constrained immediate so that we can use this to match
1694 // frame index references and avoid matching constant pool references.
1695 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1696 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1697 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1700 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1701 let Inst{19-16} = addr{16-13}; // Rn
1702 let Inst{15-12} = Rt;
1703 let Inst{11-0} = addr{11-0}; // imm12
1705 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1706 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1707 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1710 let shift{4} = 0; // Inst{4} = 0
1711 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1712 let Inst{19-16} = shift{16-13}; // Rn
1713 let Inst{15-12} = Rt;
1714 let Inst{11-0} = shift{11-0};
1719 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1720 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1721 InstrItinClass iir, PatFrag opnode> {
1722 // Note: We use the complex addrmode_imm12 rather than just an input
1723 // GPR and a constrained immediate so that we can use this to match
1724 // frame index references and avoid matching constant pool references.
1725 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1726 (ins addrmode_imm12:$addr),
1727 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1728 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1731 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1732 let Inst{19-16} = addr{16-13}; // Rn
1733 let Inst{15-12} = Rt;
1734 let Inst{11-0} = addr{11-0}; // imm12
1736 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1737 (ins ldst_so_reg:$shift),
1738 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1739 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1742 let shift{4} = 0; // Inst{4} = 0
1743 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1744 let Inst{19-16} = shift{16-13}; // Rn
1745 let Inst{15-12} = Rt;
1746 let Inst{11-0} = shift{11-0};
1752 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1753 InstrItinClass iir, PatFrag opnode> {
1754 // Note: We use the complex addrmode_imm12 rather than just an input
1755 // GPR and a constrained immediate so that we can use this to match
1756 // frame index references and avoid matching constant pool references.
1757 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1758 (ins GPR:$Rt, addrmode_imm12:$addr),
1759 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1760 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1763 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1764 let Inst{19-16} = addr{16-13}; // Rn
1765 let Inst{15-12} = Rt;
1766 let Inst{11-0} = addr{11-0}; // imm12
1768 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1769 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1770 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1773 let shift{4} = 0; // Inst{4} = 0
1774 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1775 let Inst{19-16} = shift{16-13}; // Rn
1776 let Inst{15-12} = Rt;
1777 let Inst{11-0} = shift{11-0};
1781 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1782 InstrItinClass iir, PatFrag opnode> {
1783 // Note: We use the complex addrmode_imm12 rather than just an input
1784 // GPR and a constrained immediate so that we can use this to match
1785 // frame index references and avoid matching constant pool references.
1786 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1787 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1788 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1789 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1792 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1793 let Inst{19-16} = addr{16-13}; // Rn
1794 let Inst{15-12} = Rt;
1795 let Inst{11-0} = addr{11-0}; // imm12
1797 def rs : AI2ldst<0b011, 0, isByte, (outs),
1798 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1799 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1800 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1803 let shift{4} = 0; // Inst{4} = 0
1804 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1805 let Inst{19-16} = shift{16-13}; // Rn
1806 let Inst{15-12} = Rt;
1807 let Inst{11-0} = shift{11-0};
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1816 //===----------------------------------------------------------------------===//
1817 // Miscellaneous Instructions.
1820 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1821 /// the function. The first operand is the ID# for this instruction, the second
1822 /// is the index into the MachineConstantPool that this is, the third is the
1823 /// size in bytes of this constant pool entry.
1824 let hasSideEffects = 0, isNotDuplicable = 1 in
1825 def CONSTPOOL_ENTRY :
1826 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1827 i32imm:$size), NoItinerary, []>;
1829 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1830 // from removing one half of the matched pairs. That breaks PEI, which assumes
1831 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1832 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1833 def ADJCALLSTACKUP :
1834 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1835 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1837 def ADJCALLSTACKDOWN :
1838 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1839 [(ARMcallseq_start timm:$amt)]>;
1842 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1843 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1844 Requires<[IsARM, HasV6]> {
1846 let Inst{27-8} = 0b00110010000011110000;
1847 let Inst{7-0} = imm;
1850 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1851 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1852 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1853 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1854 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1855 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1857 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1858 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1863 let Inst{15-12} = Rd;
1864 let Inst{19-16} = Rn;
1865 let Inst{27-20} = 0b01101000;
1866 let Inst{7-4} = 0b1011;
1867 let Inst{11-8} = 0b1111;
1868 let Unpredictable{11-8} = 0b1111;
1871 // The 16-bit operand $val can be used by a debugger to store more information
1872 // about the breakpoint.
1873 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1874 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1876 let Inst{3-0} = val{3-0};
1877 let Inst{19-8} = val{15-4};
1878 let Inst{27-20} = 0b00010010;
1879 let Inst{31-28} = 0xe; // AL
1880 let Inst{7-4} = 0b0111;
1882 // default immediate for breakpoint mnemonic
1883 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1885 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1886 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1888 let Inst{3-0} = val{3-0};
1889 let Inst{19-8} = val{15-4};
1890 let Inst{27-20} = 0b00010000;
1891 let Inst{31-28} = 0xe; // AL
1892 let Inst{7-4} = 0b0111;
1895 // Change Processor State
1896 // FIXME: We should use InstAlias to handle the optional operands.
1897 class CPS<dag iops, string asm_ops>
1898 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1899 []>, Requires<[IsARM]> {
1905 let Inst{31-28} = 0b1111;
1906 let Inst{27-20} = 0b00010000;
1907 let Inst{19-18} = imod;
1908 let Inst{17} = M; // Enabled if mode is set;
1909 let Inst{16-9} = 0b00000000;
1910 let Inst{8-6} = iflags;
1912 let Inst{4-0} = mode;
1915 let DecoderMethod = "DecodeCPSInstruction" in {
1917 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1918 "$imod\t$iflags, $mode">;
1919 let mode = 0, M = 0 in
1920 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1922 let imod = 0, iflags = 0, M = 1 in
1923 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1926 // Preload signals the memory system of possible future data/instruction access.
1927 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1929 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1930 IIC_Preload, !strconcat(opc, "\t$addr"),
1931 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1932 Sched<[WritePreLd]> {
1935 let Inst{31-26} = 0b111101;
1936 let Inst{25} = 0; // 0 for immediate form
1937 let Inst{24} = data;
1938 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1939 let Inst{22} = read;
1940 let Inst{21-20} = 0b01;
1941 let Inst{19-16} = addr{16-13}; // Rn
1942 let Inst{15-12} = 0b1111;
1943 let Inst{11-0} = addr{11-0}; // imm12
1946 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1947 !strconcat(opc, "\t$shift"),
1948 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1949 Sched<[WritePreLd]> {
1951 let Inst{31-26} = 0b111101;
1952 let Inst{25} = 1; // 1 for register form
1953 let Inst{24} = data;
1954 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1955 let Inst{22} = read;
1956 let Inst{21-20} = 0b01;
1957 let Inst{19-16} = shift{16-13}; // Rn
1958 let Inst{15-12} = 0b1111;
1959 let Inst{11-0} = shift{11-0};
1964 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1965 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1966 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1968 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1969 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1971 let Inst{31-10} = 0b1111000100000001000000;
1976 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1977 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
1979 let Inst{27-4} = 0b001100100000111100001111;
1980 let Inst{3-0} = opt;
1983 // A8.8.247 UDF - Undefined (Encoding A1)
1984 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1985 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1987 let Inst{31-28} = 0b1110; // AL
1988 let Inst{27-25} = 0b011;
1989 let Inst{24-20} = 0b11111;
1990 let Inst{19-8} = imm16{15-4};
1991 let Inst{7-4} = 0b1111;
1992 let Inst{3-0} = imm16{3-0};
1996 * A5.4 Permanently UNDEFINED instructions.
1998 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1999 * Other UDF encodings generate SIGILL.
2001 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2003 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2005 * 1101 1110 iiii iiii
2006 * It uses the following encoding:
2007 * 1110 0111 1111 1110 1101 1110 1111 0000
2008 * - In ARM: UDF #60896;
2009 * - In Thumb: UDF #254 followed by a branch-to-self.
2011 let isBarrier = 1, isTerminator = 1 in
2012 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2014 Requires<[IsARM,UseNaClTrap]> {
2015 let Inst = 0xe7fedef0;
2017 let isBarrier = 1, isTerminator = 1 in
2018 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2020 Requires<[IsARM,DontUseNaClTrap]> {
2021 let Inst = 0xe7ffdefe;
2024 // Address computation and loads and stores in PIC mode.
2025 let isNotDuplicable = 1 in {
2026 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2028 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2029 Sched<[WriteALU, ReadALU]>;
2031 let AddedComplexity = 10 in {
2032 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2034 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2036 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2038 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2040 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2042 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2044 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2046 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2048 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2050 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2052 let AddedComplexity = 10 in {
2053 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2054 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2056 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2057 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2058 addrmodepc:$addr)]>;
2060 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2061 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2063 } // isNotDuplicable = 1
2066 // LEApcrel - Load a pc-relative address into a register without offending the
2068 let hasSideEffects = 0, isReMaterializable = 1 in
2069 // The 'adr' mnemonic encodes differently if the label is before or after
2070 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2071 // know until then which form of the instruction will be used.
2072 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2073 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2074 Sched<[WriteALU, ReadALU]> {
2077 let Inst{27-25} = 0b001;
2079 let Inst{23-22} = label{13-12};
2082 let Inst{19-16} = 0b1111;
2083 let Inst{15-12} = Rd;
2084 let Inst{11-0} = label{11-0};
2087 let hasSideEffects = 1 in {
2088 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2089 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2091 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2092 (ins i32imm:$label, pred:$p),
2093 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2096 //===----------------------------------------------------------------------===//
2097 // Control Flow Instructions.
2100 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2102 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2103 "bx", "\tlr", [(ARMretflag)]>,
2104 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2105 let Inst{27-0} = 0b0001001011111111111100011110;
2109 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2110 "mov", "\tpc, lr", [(ARMretflag)]>,
2111 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2112 let Inst{27-0} = 0b0001101000001111000000001110;
2115 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2116 // the user-space one).
2117 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2119 [(ARMintretflag imm:$offset)]>;
2122 // Indirect branches
2123 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2125 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2126 [(brind GPR:$dst)]>,
2127 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2129 let Inst{31-4} = 0b1110000100101111111111110001;
2130 let Inst{3-0} = dst;
2133 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2134 "bx", "\t$dst", [/* pattern left blank */]>,
2135 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2137 let Inst{27-4} = 0b000100101111111111110001;
2138 let Inst{3-0} = dst;
2142 // SP is marked as a use to prevent stack-pointer assignments that appear
2143 // immediately before calls from potentially appearing dead.
2145 // FIXME: Do we really need a non-predicated version? If so, it should
2146 // at least be a pseudo instruction expanding to the predicated version
2147 // at MC lowering time.
2148 Defs = [LR], Uses = [SP] in {
2149 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2150 IIC_Br, "bl\t$func",
2151 [(ARMcall tglobaladdr:$func)]>,
2152 Requires<[IsARM]>, Sched<[WriteBrL]> {
2153 let Inst{31-28} = 0b1110;
2155 let Inst{23-0} = func;
2156 let DecoderMethod = "DecodeBranchImmInstruction";
2159 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2160 IIC_Br, "bl", "\t$func",
2161 [(ARMcall_pred tglobaladdr:$func)]>,
2162 Requires<[IsARM]>, Sched<[WriteBrL]> {
2164 let Inst{23-0} = func;
2165 let DecoderMethod = "DecodeBranchImmInstruction";
2169 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2170 IIC_Br, "blx\t$func",
2171 [(ARMcall GPR:$func)]>,
2172 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2174 let Inst{31-4} = 0b1110000100101111111111110011;
2175 let Inst{3-0} = func;
2178 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2179 IIC_Br, "blx", "\t$func",
2180 [(ARMcall_pred GPR:$func)]>,
2181 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2183 let Inst{27-4} = 0b000100101111111111110011;
2184 let Inst{3-0} = func;
2188 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2189 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2190 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2191 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2194 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2195 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2196 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2198 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2199 // return stack predictor.
2200 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2201 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2202 Requires<[IsARM]>, Sched<[WriteBr]>;
2205 let isBranch = 1, isTerminator = 1 in {
2206 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2207 // a two-value operand where a dag node expects two operands. :(
2208 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2209 IIC_Br, "b", "\t$target",
2210 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2213 let Inst{23-0} = target;
2214 let DecoderMethod = "DecodeBranchImmInstruction";
2217 let isBarrier = 1 in {
2218 // B is "predicable" since it's just a Bcc with an 'always' condition.
2219 let isPredicable = 1 in
2220 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2221 // should be sufficient.
2222 // FIXME: Is B really a Barrier? That doesn't seem right.
2223 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2224 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2227 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2228 def BR_JTr : ARMPseudoInst<(outs),
2229 (ins GPR:$target, i32imm:$jt),
2231 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2233 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2234 // into i12 and rs suffixed versions.
2235 def BR_JTm : ARMPseudoInst<(outs),
2236 (ins addrmode2:$target, i32imm:$jt),
2238 [(ARMbrjt (i32 (load addrmode2:$target)),
2239 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2240 def BR_JTadd : ARMPseudoInst<(outs),
2241 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2243 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2244 Sched<[WriteBrTbl]>;
2245 } // isNotDuplicable = 1, isIndirectBranch = 1
2251 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2252 "blx\t$target", []>,
2253 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2254 let Inst{31-25} = 0b1111101;
2256 let Inst{23-0} = target{24-1};
2257 let Inst{24} = target{0};
2261 // Branch and Exchange Jazelle
2262 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2263 [/* pattern left blank */]>, Sched<[WriteBr]> {
2265 let Inst{23-20} = 0b0010;
2266 let Inst{19-8} = 0xfff;
2267 let Inst{7-4} = 0b0010;
2268 let Inst{3-0} = func;
2274 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2275 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2278 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2281 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2283 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2284 Requires<[IsARM]>, Sched<[WriteBr]>;
2286 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2288 (BX GPR:$dst)>, Sched<[WriteBr]>,
2292 // Secure Monitor Call is a system instruction.
2293 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2294 []>, Requires<[IsARM, HasTrustZone]> {
2296 let Inst{23-4} = 0b01100000000000000111;
2297 let Inst{3-0} = opt;
2300 // Supervisor Call (Software Interrupt)
2301 let isCall = 1, Uses = [SP] in {
2302 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2305 let Inst{23-0} = svc;
2309 // Store Return State
2310 class SRSI<bit wb, string asm>
2311 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2312 NoItinerary, asm, "", []> {
2314 let Inst{31-28} = 0b1111;
2315 let Inst{27-25} = 0b100;
2319 let Inst{19-16} = 0b1101; // SP
2320 let Inst{15-5} = 0b00000101000;
2321 let Inst{4-0} = mode;
2324 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2325 let Inst{24-23} = 0;
2327 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2328 let Inst{24-23} = 0;
2330 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2331 let Inst{24-23} = 0b10;
2333 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2334 let Inst{24-23} = 0b10;
2336 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2337 let Inst{24-23} = 0b01;
2339 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2340 let Inst{24-23} = 0b01;
2342 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2343 let Inst{24-23} = 0b11;
2345 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2346 let Inst{24-23} = 0b11;
2349 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2350 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2352 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2353 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2355 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2356 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2358 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2359 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2361 // Return From Exception
2362 class RFEI<bit wb, string asm>
2363 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2364 NoItinerary, asm, "", []> {
2366 let Inst{31-28} = 0b1111;
2367 let Inst{27-25} = 0b100;
2371 let Inst{19-16} = Rn;
2372 let Inst{15-0} = 0xa00;
2375 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2376 let Inst{24-23} = 0;
2378 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2379 let Inst{24-23} = 0;
2381 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2382 let Inst{24-23} = 0b10;
2384 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2385 let Inst{24-23} = 0b10;
2387 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2388 let Inst{24-23} = 0b01;
2390 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2391 let Inst{24-23} = 0b01;
2393 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2394 let Inst{24-23} = 0b11;
2396 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2397 let Inst{24-23} = 0b11;
2400 // Hypervisor Call is a system instruction
2402 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2403 "hvc", "\t$imm", []>,
2404 Requires<[IsARM, HasVirtualization]> {
2407 // Even though HVC isn't predicable, it's encoding includes a condition field.
2408 // The instruction is undefined if the condition field is 0xf otherwise it is
2409 // unpredictable if it isn't condition AL (0xe).
2410 let Inst{31-28} = 0b1110;
2411 let Unpredictable{31-28} = 0b1111;
2412 let Inst{27-24} = 0b0001;
2413 let Inst{23-20} = 0b0100;
2414 let Inst{19-8} = imm{15-4};
2415 let Inst{7-4} = 0b0111;
2416 let Inst{3-0} = imm{3-0};
2420 // Return from exception in Hypervisor mode.
2421 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2422 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2423 Requires<[IsARM, HasVirtualization]> {
2424 let Inst{23-0} = 0b011000000000000001101110;
2427 //===----------------------------------------------------------------------===//
2428 // Load / Store Instructions.
2434 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2435 UnOpFrag<(load node:$Src)>>;
2436 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2437 UnOpFrag<(zextloadi8 node:$Src)>>;
2438 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2439 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2440 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2441 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2443 // Special LDR for loads from non-pc-relative constpools.
2444 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2445 isReMaterializable = 1, isCodeGenOnly = 1 in
2446 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2447 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2451 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2452 let Inst{19-16} = 0b1111;
2453 let Inst{15-12} = Rt;
2454 let Inst{11-0} = addr{11-0}; // imm12
2457 // Loads with zero extension
2458 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2459 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2460 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2462 // Loads with sign extension
2463 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2464 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2465 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2467 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2468 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2469 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2471 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2473 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2474 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2475 Requires<[IsARM, HasV5TE]>;
2478 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2479 NoItinerary, "lda", "\t$Rt, $addr", []>;
2480 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2481 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2482 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2483 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2486 multiclass AI2_ldridx<bit isByte, string opc,
2487 InstrItinClass iii, InstrItinClass iir> {
2488 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2489 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2490 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2493 let Inst{23} = addr{12};
2494 let Inst{19-16} = addr{16-13};
2495 let Inst{11-0} = addr{11-0};
2496 let DecoderMethod = "DecodeLDRPreImm";
2499 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2500 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2501 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2504 let Inst{23} = addr{12};
2505 let Inst{19-16} = addr{16-13};
2506 let Inst{11-0} = addr{11-0};
2508 let DecoderMethod = "DecodeLDRPreReg";
2511 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2512 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2513 IndexModePost, LdFrm, iir,
2514 opc, "\t$Rt, $addr, $offset",
2515 "$addr.base = $Rn_wb", []> {
2521 let Inst{23} = offset{12};
2522 let Inst{19-16} = addr;
2523 let Inst{11-0} = offset{11-0};
2526 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2529 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2530 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2531 IndexModePost, LdFrm, iii,
2532 opc, "\t$Rt, $addr, $offset",
2533 "$addr.base = $Rn_wb", []> {
2539 let Inst{23} = offset{12};
2540 let Inst{19-16} = addr;
2541 let Inst{11-0} = offset{11-0};
2543 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2548 let mayLoad = 1, hasSideEffects = 0 in {
2549 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2550 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2551 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2552 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2555 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2556 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2557 (ins addrmode3_pre:$addr), IndexModePre,
2559 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2561 let Inst{23} = addr{8}; // U bit
2562 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2563 let Inst{19-16} = addr{12-9}; // Rn
2564 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2565 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2566 let DecoderMethod = "DecodeAddrMode3Instruction";
2568 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2569 (ins addr_offset_none:$addr, am3offset:$offset),
2570 IndexModePost, LdMiscFrm, itin,
2571 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2575 let Inst{23} = offset{8}; // U bit
2576 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2577 let Inst{19-16} = addr;
2578 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2579 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2580 let DecoderMethod = "DecodeAddrMode3Instruction";
2584 let mayLoad = 1, hasSideEffects = 0 in {
2585 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2586 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2587 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2588 let hasExtraDefRegAllocReq = 1 in {
2589 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2590 (ins addrmode3_pre:$addr), IndexModePre,
2591 LdMiscFrm, IIC_iLoad_d_ru,
2592 "ldrd", "\t$Rt, $Rt2, $addr!",
2593 "$addr.base = $Rn_wb", []> {
2595 let Inst{23} = addr{8}; // U bit
2596 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2597 let Inst{19-16} = addr{12-9}; // Rn
2598 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2599 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2600 let DecoderMethod = "DecodeAddrMode3Instruction";
2602 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2603 (ins addr_offset_none:$addr, am3offset:$offset),
2604 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2605 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2606 "$addr.base = $Rn_wb", []> {
2609 let Inst{23} = offset{8}; // U bit
2610 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2611 let Inst{19-16} = addr;
2612 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2613 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2614 let DecoderMethod = "DecodeAddrMode3Instruction";
2616 } // hasExtraDefRegAllocReq = 1
2617 } // mayLoad = 1, hasSideEffects = 0
2619 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2620 let mayLoad = 1, hasSideEffects = 0 in {
2621 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2622 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2623 IndexModePost, LdFrm, IIC_iLoad_ru,
2624 "ldrt", "\t$Rt, $addr, $offset",
2625 "$addr.base = $Rn_wb", []> {
2631 let Inst{23} = offset{12};
2632 let Inst{21} = 1; // overwrite
2633 let Inst{19-16} = addr;
2634 let Inst{11-5} = offset{11-5};
2636 let Inst{3-0} = offset{3-0};
2637 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2641 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2642 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2643 IndexModePost, LdFrm, IIC_iLoad_ru,
2644 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2650 let Inst{23} = offset{12};
2651 let Inst{21} = 1; // overwrite
2652 let Inst{19-16} = addr;
2653 let Inst{11-0} = offset{11-0};
2654 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2657 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2658 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2659 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2660 "ldrbt", "\t$Rt, $addr, $offset",
2661 "$addr.base = $Rn_wb", []> {
2667 let Inst{23} = offset{12};
2668 let Inst{21} = 1; // overwrite
2669 let Inst{19-16} = addr;
2670 let Inst{11-5} = offset{11-5};
2672 let Inst{3-0} = offset{3-0};
2673 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2677 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2678 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2679 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2680 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2686 let Inst{23} = offset{12};
2687 let Inst{21} = 1; // overwrite
2688 let Inst{19-16} = addr;
2689 let Inst{11-0} = offset{11-0};
2690 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2693 multiclass AI3ldrT<bits<4> op, string opc> {
2694 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2695 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2696 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2697 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2699 let Inst{23} = offset{8};
2701 let Inst{11-8} = offset{7-4};
2702 let Inst{3-0} = offset{3-0};
2704 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2705 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2706 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2707 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2709 let Inst{23} = Rm{4};
2712 let Unpredictable{11-8} = 0b1111;
2713 let Inst{3-0} = Rm{3-0};
2714 let DecoderMethod = "DecodeLDR";
2718 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2719 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2720 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2724 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2728 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2733 // Stores with truncate
2734 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2735 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2736 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2739 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2740 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2741 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2742 Requires<[IsARM, HasV5TE]> {
2748 multiclass AI2_stridx<bit isByte, string opc,
2749 InstrItinClass iii, InstrItinClass iir> {
2750 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2751 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2753 opc, "\t$Rt, $addr!",
2754 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2757 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2758 let Inst{19-16} = addr{16-13}; // Rn
2759 let Inst{11-0} = addr{11-0}; // imm12
2760 let DecoderMethod = "DecodeSTRPreImm";
2763 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2764 (ins GPR:$Rt, ldst_so_reg:$addr),
2765 IndexModePre, StFrm, iir,
2766 opc, "\t$Rt, $addr!",
2767 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2770 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2771 let Inst{19-16} = addr{16-13}; // Rn
2772 let Inst{11-0} = addr{11-0};
2773 let Inst{4} = 0; // Inst{4} = 0
2774 let DecoderMethod = "DecodeSTRPreReg";
2776 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2777 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2778 IndexModePost, StFrm, iir,
2779 opc, "\t$Rt, $addr, $offset",
2780 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2786 let Inst{23} = offset{12};
2787 let Inst{19-16} = addr;
2788 let Inst{11-0} = offset{11-0};
2791 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2794 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2795 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2796 IndexModePost, StFrm, iii,
2797 opc, "\t$Rt, $addr, $offset",
2798 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2804 let Inst{23} = offset{12};
2805 let Inst{19-16} = addr;
2806 let Inst{11-0} = offset{11-0};
2808 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2812 let mayStore = 1, hasSideEffects = 0 in {
2813 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2814 // IIC_iStore_siu depending on whether it the offset register is shifted.
2815 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2816 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2819 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2820 am2offset_reg:$offset),
2821 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2822 am2offset_reg:$offset)>;
2823 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2824 am2offset_imm:$offset),
2825 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2826 am2offset_imm:$offset)>;
2827 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2828 am2offset_reg:$offset),
2829 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2830 am2offset_reg:$offset)>;
2831 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2832 am2offset_imm:$offset),
2833 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2834 am2offset_imm:$offset)>;
2836 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2837 // put the patterns on the instruction definitions directly as ISel wants
2838 // the address base and offset to be separate operands, not a single
2839 // complex operand like we represent the instructions themselves. The
2840 // pseudos map between the two.
2841 let usesCustomInserter = 1,
2842 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2843 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2844 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2847 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2848 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2849 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2852 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2853 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2854 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2857 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2858 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2859 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2862 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2863 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2864 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2867 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2872 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2873 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2874 StMiscFrm, IIC_iStore_bh_ru,
2875 "strh", "\t$Rt, $addr!",
2876 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2878 let Inst{23} = addr{8}; // U bit
2879 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2880 let Inst{19-16} = addr{12-9}; // Rn
2881 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2882 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2883 let DecoderMethod = "DecodeAddrMode3Instruction";
2886 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2887 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2888 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2889 "strh", "\t$Rt, $addr, $offset",
2890 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2891 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2892 addr_offset_none:$addr,
2893 am3offset:$offset))]> {
2896 let Inst{23} = offset{8}; // U bit
2897 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2898 let Inst{19-16} = addr;
2899 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2900 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2901 let DecoderMethod = "DecodeAddrMode3Instruction";
2904 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2905 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2906 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2907 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2908 "strd", "\t$Rt, $Rt2, $addr!",
2909 "$addr.base = $Rn_wb", []> {
2911 let Inst{23} = addr{8}; // U bit
2912 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2913 let Inst{19-16} = addr{12-9}; // Rn
2914 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2915 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2916 let DecoderMethod = "DecodeAddrMode3Instruction";
2919 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2920 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2922 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2923 "strd", "\t$Rt, $Rt2, $addr, $offset",
2924 "$addr.base = $Rn_wb", []> {
2927 let Inst{23} = offset{8}; // U bit
2928 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2929 let Inst{19-16} = addr;
2930 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2931 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2932 let DecoderMethod = "DecodeAddrMode3Instruction";
2934 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2936 // STRT, STRBT, and STRHT
2938 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2939 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2940 IndexModePost, StFrm, IIC_iStore_bh_ru,
2941 "strbt", "\t$Rt, $addr, $offset",
2942 "$addr.base = $Rn_wb", []> {
2948 let Inst{23} = offset{12};
2949 let Inst{21} = 1; // overwrite
2950 let Inst{19-16} = addr;
2951 let Inst{11-5} = offset{11-5};
2953 let Inst{3-0} = offset{3-0};
2954 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2958 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2959 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2960 IndexModePost, StFrm, IIC_iStore_bh_ru,
2961 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2967 let Inst{23} = offset{12};
2968 let Inst{21} = 1; // overwrite
2969 let Inst{19-16} = addr;
2970 let Inst{11-0} = offset{11-0};
2971 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2975 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2976 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2978 let mayStore = 1, hasSideEffects = 0 in {
2979 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2980 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2981 IndexModePost, StFrm, IIC_iStore_ru,
2982 "strt", "\t$Rt, $addr, $offset",
2983 "$addr.base = $Rn_wb", []> {
2989 let Inst{23} = offset{12};
2990 let Inst{21} = 1; // overwrite
2991 let Inst{19-16} = addr;
2992 let Inst{11-5} = offset{11-5};
2994 let Inst{3-0} = offset{3-0};
2995 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2999 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3000 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3001 IndexModePost, StFrm, IIC_iStore_ru,
3002 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3008 let Inst{23} = offset{12};
3009 let Inst{21} = 1; // overwrite
3010 let Inst{19-16} = addr;
3011 let Inst{11-0} = offset{11-0};
3012 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3017 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3018 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3020 multiclass AI3strT<bits<4> op, string opc> {
3021 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3022 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3023 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3024 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3026 let Inst{23} = offset{8};
3028 let Inst{11-8} = offset{7-4};
3029 let Inst{3-0} = offset{3-0};
3031 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3032 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3033 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3034 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3036 let Inst{23} = Rm{4};
3039 let Inst{3-0} = Rm{3-0};
3044 defm STRHT : AI3strT<0b1011, "strht">;
3046 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3047 NoItinerary, "stl", "\t$Rt, $addr", []>;
3048 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3049 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3050 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3051 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3053 //===----------------------------------------------------------------------===//
3054 // Load / store multiple Instructions.
3057 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3058 InstrItinClass itin, InstrItinClass itin_upd> {
3059 // IA is the default, so no need for an explicit suffix on the
3060 // mnemonic here. Without it is the canonical spelling.
3062 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3063 IndexModeNone, f, itin,
3064 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3065 let Inst{24-23} = 0b01; // Increment After
3066 let Inst{22} = P_bit;
3067 let Inst{21} = 0; // No writeback
3068 let Inst{20} = L_bit;
3071 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3072 IndexModeUpd, f, itin_upd,
3073 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3074 let Inst{24-23} = 0b01; // Increment After
3075 let Inst{22} = P_bit;
3076 let Inst{21} = 1; // Writeback
3077 let Inst{20} = L_bit;
3079 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3082 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3083 IndexModeNone, f, itin,
3084 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3085 let Inst{24-23} = 0b00; // Decrement After
3086 let Inst{22} = P_bit;
3087 let Inst{21} = 0; // No writeback
3088 let Inst{20} = L_bit;
3091 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3092 IndexModeUpd, f, itin_upd,
3093 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3094 let Inst{24-23} = 0b00; // Decrement After
3095 let Inst{22} = P_bit;
3096 let Inst{21} = 1; // Writeback
3097 let Inst{20} = L_bit;
3099 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3102 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3103 IndexModeNone, f, itin,
3104 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3105 let Inst{24-23} = 0b10; // Decrement Before
3106 let Inst{22} = P_bit;
3107 let Inst{21} = 0; // No writeback
3108 let Inst{20} = L_bit;
3111 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3112 IndexModeUpd, f, itin_upd,
3113 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3114 let Inst{24-23} = 0b10; // Decrement Before
3115 let Inst{22} = P_bit;
3116 let Inst{21} = 1; // Writeback
3117 let Inst{20} = L_bit;
3119 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3122 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3123 IndexModeNone, f, itin,
3124 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3125 let Inst{24-23} = 0b11; // Increment Before
3126 let Inst{22} = P_bit;
3127 let Inst{21} = 0; // No writeback
3128 let Inst{20} = L_bit;
3131 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3132 IndexModeUpd, f, itin_upd,
3133 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3134 let Inst{24-23} = 0b11; // Increment Before
3135 let Inst{22} = P_bit;
3136 let Inst{21} = 1; // Writeback
3137 let Inst{20} = L_bit;
3139 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3143 let hasSideEffects = 0 in {
3145 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3146 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3147 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3149 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3150 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3152 ComplexDeprecationPredicate<"ARMStore">;
3156 // FIXME: remove when we have a way to marking a MI with these properties.
3157 // FIXME: Should pc be an implicit operand like PICADD, etc?
3158 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3159 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3160 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3161 reglist:$regs, variable_ops),
3162 4, IIC_iLoad_mBr, [],
3163 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3164 RegConstraint<"$Rn = $wb">;
3166 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3167 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3170 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3171 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3176 //===----------------------------------------------------------------------===//
3177 // Move Instructions.
3180 let hasSideEffects = 0 in
3181 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3182 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3186 let Inst{19-16} = 0b0000;
3187 let Inst{11-4} = 0b00000000;
3190 let Inst{15-12} = Rd;
3193 // A version for the smaller set of tail call registers.
3194 let hasSideEffects = 0 in
3195 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3196 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3200 let Inst{11-4} = 0b00000000;
3203 let Inst{15-12} = Rd;
3206 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3207 DPSoRegRegFrm, IIC_iMOVsr,
3208 "mov", "\t$Rd, $src",
3209 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3213 let Inst{15-12} = Rd;
3214 let Inst{19-16} = 0b0000;
3215 let Inst{11-8} = src{11-8};
3217 let Inst{6-5} = src{6-5};
3219 let Inst{3-0} = src{3-0};
3223 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3224 DPSoRegImmFrm, IIC_iMOVsr,
3225 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3226 UnaryDP, Sched<[WriteALU]> {
3229 let Inst{15-12} = Rd;
3230 let Inst{19-16} = 0b0000;
3231 let Inst{11-5} = src{11-5};
3233 let Inst{3-0} = src{3-0};
3237 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3238 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3239 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3244 let Inst{15-12} = Rd;
3245 let Inst{19-16} = 0b0000;
3246 let Inst{11-0} = imm;
3249 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3250 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3252 "movw", "\t$Rd, $imm",
3253 [(set GPR:$Rd, imm0_65535:$imm)]>,
3254 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3257 let Inst{15-12} = Rd;
3258 let Inst{11-0} = imm{11-0};
3259 let Inst{19-16} = imm{15-12};
3262 let DecoderMethod = "DecodeArmMOVTWInstruction";
3265 def : InstAlias<"mov${p} $Rd, $imm",
3266 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3269 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3270 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3273 let Constraints = "$src = $Rd" in {
3274 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3275 (ins GPR:$src, imm0_65535_expr:$imm),
3277 "movt", "\t$Rd, $imm",
3279 (or (and GPR:$src, 0xffff),
3280 lo16AllZero:$imm))]>, UnaryDP,
3281 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3284 let Inst{15-12} = Rd;
3285 let Inst{11-0} = imm{11-0};
3286 let Inst{19-16} = imm{15-12};
3289 let DecoderMethod = "DecodeArmMOVTWInstruction";
3292 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3293 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3298 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3299 Requires<[IsARM, HasV6T2]>;
3301 let Uses = [CPSR] in
3302 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3303 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3304 Requires<[IsARM]>, Sched<[WriteALU]>;
3306 // These aren't really mov instructions, but we have to define them this way
3307 // due to flag operands.
3309 let Defs = [CPSR] in {
3310 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3311 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3312 Sched<[WriteALU]>, Requires<[IsARM]>;
3313 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3314 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3315 Sched<[WriteALU]>, Requires<[IsARM]>;
3318 //===----------------------------------------------------------------------===//
3319 // Extend Instructions.
3324 def SXTB : AI_ext_rrot<0b01101010,
3325 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3326 def SXTH : AI_ext_rrot<0b01101011,
3327 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3329 def SXTAB : AI_exta_rrot<0b01101010,
3330 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3331 def SXTAH : AI_exta_rrot<0b01101011,
3332 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3334 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3336 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3340 let AddedComplexity = 16 in {
3341 def UXTB : AI_ext_rrot<0b01101110,
3342 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3343 def UXTH : AI_ext_rrot<0b01101111,
3344 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3345 def UXTB16 : AI_ext_rrot<0b01101100,
3346 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3348 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3349 // The transformation should probably be done as a combiner action
3350 // instead so we can include a check for masking back in the upper
3351 // eight bits of the source into the lower eight bits of the result.
3352 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3353 // (UXTB16r_rot GPR:$Src, 3)>;
3354 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3355 (UXTB16 GPR:$Src, 1)>;
3357 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3358 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3359 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3360 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3363 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3364 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3367 def SBFX : I<(outs GPRnopc:$Rd),
3368 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3369 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3370 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3371 Requires<[IsARM, HasV6T2]> {
3376 let Inst{27-21} = 0b0111101;
3377 let Inst{6-4} = 0b101;
3378 let Inst{20-16} = width;
3379 let Inst{15-12} = Rd;
3380 let Inst{11-7} = lsb;
3384 def UBFX : I<(outs GPRnopc:$Rd),
3385 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3386 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3387 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3388 Requires<[IsARM, HasV6T2]> {
3393 let Inst{27-21} = 0b0111111;
3394 let Inst{6-4} = 0b101;
3395 let Inst{20-16} = width;
3396 let Inst{15-12} = Rd;
3397 let Inst{11-7} = lsb;
3401 //===----------------------------------------------------------------------===//
3402 // Arithmetic Instructions.
3405 defm ADD : AsI1_bin_irs<0b0100, "add",
3406 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3407 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3408 defm SUB : AsI1_bin_irs<0b0010, "sub",
3409 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3410 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3412 // ADD and SUB with 's' bit set.
3414 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3415 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3416 // AdjustInstrPostInstrSelection where we determine whether or not to
3417 // set the "s" bit based on CPSR liveness.
3419 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3420 // support for an optional CPSR definition that corresponds to the DAG
3421 // node's second value. We can then eliminate the implicit def of CPSR.
3422 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3423 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3424 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3425 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3427 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3428 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3429 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3430 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3432 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3433 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3434 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3436 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3437 // CPSR and the implicit def of CPSR is not needed.
3438 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3439 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3441 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3442 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3444 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3445 // The assume-no-carry-in form uses the negation of the input since add/sub
3446 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3447 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3449 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3450 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3451 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3452 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3454 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3455 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3456 Requires<[IsARM, HasV6T2]>;
3457 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3458 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3459 Requires<[IsARM, HasV6T2]>;
3461 // The with-carry-in form matches bitwise not instead of the negation.
3462 // Effectively, the inverse interpretation of the carry flag already accounts
3463 // for part of the negation.
3464 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3465 (SBCri GPR:$src, mod_imm_not:$imm)>;
3466 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3467 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3468 Requires<[IsARM, HasV6T2]>;
3470 // Note: These are implemented in C++ code, because they have to generate
3471 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3473 // (mul X, 2^n+1) -> (add (X << n), X)
3474 // (mul X, 2^n-1) -> (rsb X, (X << n))
3476 // ARM Arithmetic Instruction
3477 // GPR:$dst = GPR:$a op GPR:$b
3478 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3479 list<dag> pattern = [],
3480 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3481 string asm = "\t$Rd, $Rn, $Rm">
3482 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3483 Sched<[WriteALU, ReadALU, ReadALU]> {
3487 let Inst{27-20} = op27_20;
3488 let Inst{11-4} = op11_4;
3489 let Inst{19-16} = Rn;
3490 let Inst{15-12} = Rd;
3493 let Unpredictable{11-8} = 0b1111;
3496 // Saturating add/subtract
3498 let DecoderMethod = "DecodeQADDInstruction" in
3499 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3500 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3501 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3503 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3504 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3505 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3506 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3507 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3509 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3510 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3513 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3514 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3515 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3516 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3517 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3518 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3519 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3520 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3521 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3522 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3523 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3524 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3526 // Signed/Unsigned add/subtract
3528 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3529 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3530 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3531 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3532 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3533 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3534 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3535 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3536 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3537 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3538 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3539 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3541 // Signed/Unsigned halving add/subtract
3543 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3544 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3545 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3546 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3547 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3548 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3549 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3550 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3551 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3552 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3553 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3554 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3556 // Unsigned Sum of Absolute Differences [and Accumulate].
3558 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3559 MulFrm /* for convenience */, NoItinerary, "usad8",
3560 "\t$Rd, $Rn, $Rm", []>,
3561 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3565 let Inst{27-20} = 0b01111000;
3566 let Inst{15-12} = 0b1111;
3567 let Inst{7-4} = 0b0001;
3568 let Inst{19-16} = Rd;
3569 let Inst{11-8} = Rm;
3572 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3573 MulFrm /* for convenience */, NoItinerary, "usada8",
3574 "\t$Rd, $Rn, $Rm, $Ra", []>,
3575 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3580 let Inst{27-20} = 0b01111000;
3581 let Inst{7-4} = 0b0001;
3582 let Inst{19-16} = Rd;
3583 let Inst{15-12} = Ra;
3584 let Inst{11-8} = Rm;
3588 // Signed/Unsigned saturate
3590 def SSAT : AI<(outs GPRnopc:$Rd),
3591 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3592 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3597 let Inst{27-21} = 0b0110101;
3598 let Inst{5-4} = 0b01;
3599 let Inst{20-16} = sat_imm;
3600 let Inst{15-12} = Rd;
3601 let Inst{11-7} = sh{4-0};
3602 let Inst{6} = sh{5};
3606 def SSAT16 : AI<(outs GPRnopc:$Rd),
3607 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3608 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3612 let Inst{27-20} = 0b01101010;
3613 let Inst{11-4} = 0b11110011;
3614 let Inst{15-12} = Rd;
3615 let Inst{19-16} = sat_imm;
3619 def USAT : AI<(outs GPRnopc:$Rd),
3620 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3621 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3626 let Inst{27-21} = 0b0110111;
3627 let Inst{5-4} = 0b01;
3628 let Inst{15-12} = Rd;
3629 let Inst{11-7} = sh{4-0};
3630 let Inst{6} = sh{5};
3631 let Inst{20-16} = sat_imm;
3635 def USAT16 : AI<(outs GPRnopc:$Rd),
3636 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3637 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3641 let Inst{27-20} = 0b01101110;
3642 let Inst{11-4} = 0b11110011;
3643 let Inst{15-12} = Rd;
3644 let Inst{19-16} = sat_imm;
3648 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3649 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3650 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3651 (USAT imm:$pos, GPRnopc:$a, 0)>;
3653 //===----------------------------------------------------------------------===//
3654 // Bitwise Instructions.
3657 defm AND : AsI1_bin_irs<0b0000, "and",
3658 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3659 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3660 defm ORR : AsI1_bin_irs<0b1100, "orr",
3661 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3662 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3663 defm EOR : AsI1_bin_irs<0b0001, "eor",
3664 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3665 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3666 defm BIC : AsI1_bin_irs<0b1110, "bic",
3667 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3668 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3670 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3671 // like in the actual instruction encoding. The complexity of mapping the mask
3672 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3673 // instruction description.
3674 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3675 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3676 "bfc", "\t$Rd, $imm", "$src = $Rd",
3677 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3678 Requires<[IsARM, HasV6T2]> {
3681 let Inst{27-21} = 0b0111110;
3682 let Inst{6-0} = 0b0011111;
3683 let Inst{15-12} = Rd;
3684 let Inst{11-7} = imm{4-0}; // lsb
3685 let Inst{20-16} = imm{9-5}; // msb
3688 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3689 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3690 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3691 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3692 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3693 bf_inv_mask_imm:$imm))]>,
3694 Requires<[IsARM, HasV6T2]> {
3698 let Inst{27-21} = 0b0111110;
3699 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3700 let Inst{15-12} = Rd;
3701 let Inst{11-7} = imm{4-0}; // lsb
3702 let Inst{20-16} = imm{9-5}; // width
3706 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3707 "mvn", "\t$Rd, $Rm",
3708 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3712 let Inst{19-16} = 0b0000;
3713 let Inst{11-4} = 0b00000000;
3714 let Inst{15-12} = Rd;
3717 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3718 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3719 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3724 let Inst{19-16} = 0b0000;
3725 let Inst{15-12} = Rd;
3726 let Inst{11-5} = shift{11-5};
3728 let Inst{3-0} = shift{3-0};
3730 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3731 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3732 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3737 let Inst{19-16} = 0b0000;
3738 let Inst{15-12} = Rd;
3739 let Inst{11-8} = shift{11-8};
3741 let Inst{6-5} = shift{6-5};
3743 let Inst{3-0} = shift{3-0};
3745 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3746 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3747 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3748 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3752 let Inst{19-16} = 0b0000;
3753 let Inst{15-12} = Rd;
3754 let Inst{11-0} = imm;
3757 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3758 (BICri GPR:$src, mod_imm_not:$imm)>;
3760 //===----------------------------------------------------------------------===//
3761 // Multiply Instructions.
3763 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3764 string opc, string asm, list<dag> pattern>
3765 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3769 let Inst{19-16} = Rd;
3770 let Inst{11-8} = Rm;
3773 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3774 string opc, string asm, list<dag> pattern>
3775 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3780 let Inst{19-16} = RdHi;
3781 let Inst{15-12} = RdLo;
3782 let Inst{11-8} = Rm;
3785 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3786 string opc, string asm, list<dag> pattern>
3787 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3792 let Inst{19-16} = RdHi;
3793 let Inst{15-12} = RdLo;
3794 let Inst{11-8} = Rm;
3798 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3799 // property. Remove them when it's possible to add those properties
3800 // on an individual MachineInstr, not just an instruction description.
3801 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3802 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3803 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3804 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3805 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3806 Requires<[IsARM, HasV6]> {
3807 let Inst{15-12} = 0b0000;
3808 let Unpredictable{15-12} = 0b1111;
3811 let Constraints = "@earlyclobber $Rd" in
3812 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3813 pred:$p, cc_out:$s),
3815 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3816 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3817 Requires<[IsARM, NoV6, UseMulOps]>;
3820 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3821 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3822 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3823 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3824 Requires<[IsARM, HasV6, UseMulOps]> {
3826 let Inst{15-12} = Ra;
3829 let Constraints = "@earlyclobber $Rd" in
3830 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3831 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3832 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3833 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3834 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3835 Requires<[IsARM, NoV6]>;
3837 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3838 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3839 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3840 Requires<[IsARM, HasV6T2, UseMulOps]> {
3845 let Inst{19-16} = Rd;
3846 let Inst{15-12} = Ra;
3847 let Inst{11-8} = Rm;
3851 // Extra precision multiplies with low / high results
3852 let hasSideEffects = 0 in {
3853 let isCommutable = 1 in {
3854 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3855 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3856 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3857 Requires<[IsARM, HasV6]>;
3859 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3860 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3861 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3862 Requires<[IsARM, HasV6]>;
3864 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3865 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3866 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3868 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3869 Requires<[IsARM, NoV6]>;
3871 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3872 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3874 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3875 Requires<[IsARM, NoV6]>;
3879 // Multiply + accumulate
3880 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3881 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3882 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3883 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3884 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3885 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3886 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3887 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3889 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3890 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3891 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3892 Requires<[IsARM, HasV6]> {
3897 let Inst{19-16} = RdHi;
3898 let Inst{15-12} = RdLo;
3899 let Inst{11-8} = Rm;
3904 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3905 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3906 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3908 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3909 pred:$p, cc_out:$s)>,
3910 Requires<[IsARM, NoV6]>;
3911 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3912 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3914 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3915 pred:$p, cc_out:$s)>,
3916 Requires<[IsARM, NoV6]>;
3921 // Most significant word multiply
3922 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3923 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3924 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3925 Requires<[IsARM, HasV6]> {
3926 let Inst{15-12} = 0b1111;
3929 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3930 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3931 Requires<[IsARM, HasV6]> {
3932 let Inst{15-12} = 0b1111;
3935 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3936 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3937 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3938 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3939 Requires<[IsARM, HasV6, UseMulOps]>;
3941 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3942 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3943 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3944 Requires<[IsARM, HasV6]>;
3946 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3947 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3948 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3949 Requires<[IsARM, HasV6, UseMulOps]>;
3951 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3952 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3953 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3954 Requires<[IsARM, HasV6]>;
3956 multiclass AI_smul<string opc, PatFrag opnode> {
3957 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3958 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3959 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3960 (sext_inreg GPR:$Rm, i16)))]>,
3961 Requires<[IsARM, HasV5TE]>;
3963 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3964 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3965 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3966 (sra GPR:$Rm, (i32 16))))]>,
3967 Requires<[IsARM, HasV5TE]>;
3969 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3970 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3971 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3972 (sext_inreg GPR:$Rm, i16)))]>,
3973 Requires<[IsARM, HasV5TE]>;
3975 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3976 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3977 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3978 (sra GPR:$Rm, (i32 16))))]>,
3979 Requires<[IsARM, HasV5TE]>;
3981 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3982 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3984 Requires<[IsARM, HasV5TE]>;
3986 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3987 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3989 Requires<[IsARM, HasV5TE]>;
3993 multiclass AI_smla<string opc, PatFrag opnode> {
3994 let DecoderMethod = "DecodeSMLAInstruction" in {
3995 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3996 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3997 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3998 [(set GPRnopc:$Rd, (add GPR:$Ra,
3999 (opnode (sext_inreg GPRnopc:$Rn, i16),
4000 (sext_inreg GPRnopc:$Rm, i16))))]>,
4001 Requires<[IsARM, HasV5TE, UseMulOps]>;
4003 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4004 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4005 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4007 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4008 (sra GPRnopc:$Rm, (i32 16)))))]>,
4009 Requires<[IsARM, HasV5TE, UseMulOps]>;
4011 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4012 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4013 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4015 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4016 (sext_inreg GPRnopc:$Rm, i16))))]>,
4017 Requires<[IsARM, HasV5TE, UseMulOps]>;
4019 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4020 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4021 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4023 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4024 (sra GPRnopc:$Rm, (i32 16)))))]>,
4025 Requires<[IsARM, HasV5TE, UseMulOps]>;
4027 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4028 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4029 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4031 Requires<[IsARM, HasV5TE, UseMulOps]>;
4033 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4034 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4035 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4037 Requires<[IsARM, HasV5TE, UseMulOps]>;
4041 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4042 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4044 // Halfword multiply accumulate long: SMLAL<x><y>.
4045 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4046 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4047 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4048 Requires<[IsARM, HasV5TE]>;
4050 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4051 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4052 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4053 Requires<[IsARM, HasV5TE]>;
4055 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4056 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4057 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4058 Requires<[IsARM, HasV5TE]>;
4060 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4061 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4062 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4063 Requires<[IsARM, HasV5TE]>;
4065 // Helper class for AI_smld.
4066 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4067 InstrItinClass itin, string opc, string asm>
4068 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4071 let Inst{27-23} = 0b01110;
4072 let Inst{22} = long;
4073 let Inst{21-20} = 0b00;
4074 let Inst{11-8} = Rm;
4081 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4082 InstrItinClass itin, string opc, string asm>
4083 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4085 let Inst{15-12} = 0b1111;
4086 let Inst{19-16} = Rd;
4088 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4089 InstrItinClass itin, string opc, string asm>
4090 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4093 let Inst{19-16} = Rd;
4094 let Inst{15-12} = Ra;
4096 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4097 InstrItinClass itin, string opc, string asm>
4098 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4101 let Inst{19-16} = RdHi;
4102 let Inst{15-12} = RdLo;
4105 multiclass AI_smld<bit sub, string opc> {
4107 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4108 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4109 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4111 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4112 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4113 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4115 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4116 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4117 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4119 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4120 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4121 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4125 defm SMLA : AI_smld<0, "smla">;
4126 defm SMLS : AI_smld<1, "smls">;
4128 multiclass AI_sdml<bit sub, string opc> {
4130 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4131 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4132 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4133 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4136 defm SMUA : AI_sdml<0, "smua">;
4137 defm SMUS : AI_sdml<1, "smus">;
4139 //===----------------------------------------------------------------------===//
4140 // Division Instructions (ARMv7-A with virtualization extension)
4142 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4143 "sdiv", "\t$Rd, $Rn, $Rm",
4144 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4145 Requires<[IsARM, HasDivideInARM]>;
4147 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4148 "udiv", "\t$Rd, $Rn, $Rm",
4149 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4150 Requires<[IsARM, HasDivideInARM]>;
4152 //===----------------------------------------------------------------------===//
4153 // Misc. Arithmetic Instructions.
4156 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4157 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4158 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4161 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4162 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4163 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4164 Requires<[IsARM, HasV6T2]>,
4167 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4168 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4169 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4172 let AddedComplexity = 5 in
4173 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4174 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4175 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4176 Requires<[IsARM, HasV6]>,
4179 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4180 (REV16 (LDRH addrmode3:$addr))>;
4181 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4182 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4184 let AddedComplexity = 5 in
4185 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4186 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4187 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4188 Requires<[IsARM, HasV6]>,
4191 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4192 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4195 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4196 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4197 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4198 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4199 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4201 Requires<[IsARM, HasV6]>,
4202 Sched<[WriteALUsi, ReadALU]>;
4204 // Alternate cases for PKHBT where identities eliminate some nodes.
4205 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4206 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4207 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4208 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4210 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4211 // will match the pattern below.
4212 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4213 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4214 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4215 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4216 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4218 Requires<[IsARM, HasV6]>,
4219 Sched<[WriteALUsi, ReadALU]>;
4221 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4222 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4223 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4224 // pkhtb src1, src2, asr (17..31).
4225 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4226 (srl GPRnopc:$src2, imm16:$sh)),
4227 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4228 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4229 (sra GPRnopc:$src2, imm16_31:$sh)),
4230 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4231 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4232 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4233 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4235 //===----------------------------------------------------------------------===//
4239 // + CRC32{B,H,W} 0x04C11DB7
4240 // + CRC32C{B,H,W} 0x1EDC6F41
4243 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4244 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4245 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4246 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4247 Requires<[IsARM, HasV8, HasCRC]> {
4252 let Inst{31-28} = 0b1110;
4253 let Inst{27-23} = 0b00010;
4254 let Inst{22-21} = sz;
4256 let Inst{19-16} = Rn;
4257 let Inst{15-12} = Rd;
4258 let Inst{11-10} = 0b00;
4261 let Inst{7-4} = 0b0100;
4264 let Unpredictable{11-8} = 0b1101;
4267 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4268 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4269 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4270 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4271 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4272 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4274 //===----------------------------------------------------------------------===//
4275 // ARMv8.1a Privilege Access Never extension
4279 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4280 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4283 let Inst{31-28} = 0b1111;
4284 let Inst{27-20} = 0b00010001;
4285 let Inst{19-16} = 0b0000;
4286 let Inst{15-10} = 0b000000;
4289 let Inst{7-4} = 0b0000;
4290 let Inst{3-0} = 0b0000;
4292 let Unpredictable{19-16} = 0b1111;
4293 let Unpredictable{15-10} = 0b111111;
4294 let Unpredictable{8} = 0b1;
4295 let Unpredictable{3-0} = 0b1111;
4298 //===----------------------------------------------------------------------===//
4299 // Comparison Instructions...
4302 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4303 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4304 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4306 // ARMcmpZ can re-use the above instruction definitions.
4307 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4308 (CMPri GPR:$src, mod_imm:$imm)>;
4309 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4310 (CMPrr GPR:$src, GPR:$rhs)>;
4311 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4312 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4313 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4314 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4316 // CMN register-integer
4317 let isCompare = 1, Defs = [CPSR] in {
4318 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4319 "cmn", "\t$Rn, $imm",
4320 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4321 Sched<[WriteCMP, ReadALU]> {
4326 let Inst{19-16} = Rn;
4327 let Inst{15-12} = 0b0000;
4328 let Inst{11-0} = imm;
4330 let Unpredictable{15-12} = 0b1111;
4333 // CMN register-register/shift
4334 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4335 "cmn", "\t$Rn, $Rm",
4336 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4337 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4340 let isCommutable = 1;
4343 let Inst{19-16} = Rn;
4344 let Inst{15-12} = 0b0000;
4345 let Inst{11-4} = 0b00000000;
4348 let Unpredictable{15-12} = 0b1111;
4351 def CMNzrsi : AI1<0b1011, (outs),
4352 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4353 "cmn", "\t$Rn, $shift",
4354 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4355 GPR:$Rn, so_reg_imm:$shift)]>,
4356 Sched<[WriteCMPsi, ReadALU]> {
4361 let Inst{19-16} = Rn;
4362 let Inst{15-12} = 0b0000;
4363 let Inst{11-5} = shift{11-5};
4365 let Inst{3-0} = shift{3-0};
4367 let Unpredictable{15-12} = 0b1111;
4370 def CMNzrsr : AI1<0b1011, (outs),
4371 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4372 "cmn", "\t$Rn, $shift",
4373 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4374 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4375 Sched<[WriteCMPsr, ReadALU]> {
4380 let Inst{19-16} = Rn;
4381 let Inst{15-12} = 0b0000;
4382 let Inst{11-8} = shift{11-8};
4384 let Inst{6-5} = shift{6-5};
4386 let Inst{3-0} = shift{3-0};
4388 let Unpredictable{15-12} = 0b1111;
4393 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4394 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4396 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4397 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4399 // Note that TST/TEQ don't set all the same flags that CMP does!
4400 defm TST : AI1_cmp_irs<0b1000, "tst",
4401 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4402 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4403 "DecodeTSTInstruction">;
4404 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4405 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4406 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4408 // Pseudo i64 compares for some floating point compares.
4409 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4411 def BCCi64 : PseudoInst<(outs),
4412 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4414 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4417 def BCCZi64 : PseudoInst<(outs),
4418 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4419 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4421 } // usesCustomInserter
4424 // Conditional moves
4425 let hasSideEffects = 0 in {
4427 let isCommutable = 1, isSelect = 1 in
4428 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4429 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4431 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4433 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4435 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4436 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4439 (ARMcmov GPR:$false, so_reg_imm:$shift,
4441 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4442 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4443 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4445 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4447 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4450 let isMoveImm = 1 in
4452 : ARMPseudoInst<(outs GPR:$Rd),
4453 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4455 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4457 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4460 let isMoveImm = 1 in
4461 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4462 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4464 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4466 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4468 // Two instruction predicate mov immediate.
4469 let isMoveImm = 1 in
4471 : ARMPseudoInst<(outs GPR:$Rd),
4472 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4474 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4476 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4478 let isMoveImm = 1 in
4479 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4480 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4482 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4484 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4489 //===----------------------------------------------------------------------===//
4490 // Atomic operations intrinsics
4493 def MemBarrierOptOperand : AsmOperandClass {
4494 let Name = "MemBarrierOpt";
4495 let ParserMethod = "parseMemBarrierOptOperand";
4497 def memb_opt : Operand<i32> {
4498 let PrintMethod = "printMemBOption";
4499 let ParserMatchClass = MemBarrierOptOperand;
4500 let DecoderMethod = "DecodeMemBarrierOption";
4503 def InstSyncBarrierOptOperand : AsmOperandClass {
4504 let Name = "InstSyncBarrierOpt";
4505 let ParserMethod = "parseInstSyncBarrierOptOperand";
4507 def instsyncb_opt : Operand<i32> {
4508 let PrintMethod = "printInstSyncBOption";
4509 let ParserMatchClass = InstSyncBarrierOptOperand;
4510 let DecoderMethod = "DecodeInstSyncBarrierOption";
4513 // Memory barriers protect the atomic sequences
4514 let hasSideEffects = 1 in {
4515 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4516 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4517 Requires<[IsARM, HasDB]> {
4519 let Inst{31-4} = 0xf57ff05;
4520 let Inst{3-0} = opt;
4523 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4524 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4525 Requires<[IsARM, HasDB]> {
4527 let Inst{31-4} = 0xf57ff04;
4528 let Inst{3-0} = opt;
4531 // ISB has only full system option
4532 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4533 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4534 Requires<[IsARM, HasDB]> {
4536 let Inst{31-4} = 0xf57ff06;
4537 let Inst{3-0} = opt;
4541 let usesCustomInserter = 1, Defs = [CPSR] in {
4543 // Pseudo instruction that combines movs + predicated rsbmi
4544 // to implement integer ABS
4545 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4548 let usesCustomInserter = 1 in {
4549 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4550 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4552 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4555 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4556 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4559 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4560 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4563 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4564 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4567 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4568 (int_arm_strex node:$val, node:$ptr), [{
4569 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4572 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4573 (int_arm_strex node:$val, node:$ptr), [{
4574 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4577 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4578 (int_arm_strex node:$val, node:$ptr), [{
4579 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4582 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4583 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4586 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4587 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4590 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4591 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4594 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4595 (int_arm_stlex node:$val, node:$ptr), [{
4596 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4599 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4600 (int_arm_stlex node:$val, node:$ptr), [{
4601 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4604 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4605 (int_arm_stlex node:$val, node:$ptr), [{
4606 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4609 let mayLoad = 1 in {
4610 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4611 NoItinerary, "ldrexb", "\t$Rt, $addr",
4612 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4613 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4614 NoItinerary, "ldrexh", "\t$Rt, $addr",
4615 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4616 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4617 NoItinerary, "ldrex", "\t$Rt, $addr",
4618 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4619 let hasExtraDefRegAllocReq = 1 in
4620 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4621 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4622 let DecoderMethod = "DecodeDoubleRegLoad";
4625 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4626 NoItinerary, "ldaexb", "\t$Rt, $addr",
4627 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4628 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4629 NoItinerary, "ldaexh", "\t$Rt, $addr",
4630 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4631 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4632 NoItinerary, "ldaex", "\t$Rt, $addr",
4633 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4634 let hasExtraDefRegAllocReq = 1 in
4635 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4636 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4637 let DecoderMethod = "DecodeDoubleRegLoad";
4641 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4642 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4643 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4644 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4645 addr_offset_none:$addr))]>;
4646 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4647 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4648 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4649 addr_offset_none:$addr))]>;
4650 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4651 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4652 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4653 addr_offset_none:$addr))]>;
4654 let hasExtraSrcRegAllocReq = 1 in
4655 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4656 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4657 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4658 let DecoderMethod = "DecodeDoubleRegStore";
4660 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4661 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4663 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4664 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4665 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4667 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4668 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4669 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4671 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4672 let hasExtraSrcRegAllocReq = 1 in
4673 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4674 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4675 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4676 let DecoderMethod = "DecodeDoubleRegStore";
4680 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4682 Requires<[IsARM, HasV7]> {
4683 let Inst{31-0} = 0b11110101011111111111000000011111;
4686 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4687 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4688 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4689 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4691 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4692 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4693 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4694 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4696 class acquiring_load<PatFrag base>
4697 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4698 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4699 return isAtLeastAcquire(Ordering);
4702 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4703 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4704 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4706 class releasing_store<PatFrag base>
4707 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4708 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4709 return isAtLeastRelease(Ordering);
4712 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4713 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4714 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4716 let AddedComplexity = 8 in {
4717 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4718 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4719 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4720 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4721 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4722 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4725 // SWP/SWPB are deprecated in V6/V7.
4726 let mayLoad = 1, mayStore = 1 in {
4727 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4728 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4730 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4731 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4735 //===----------------------------------------------------------------------===//
4736 // Coprocessor Instructions.
4739 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4740 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4741 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4742 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4743 imm:$CRm, imm:$opc2)]>,
4752 let Inst{3-0} = CRm;
4754 let Inst{7-5} = opc2;
4755 let Inst{11-8} = cop;
4756 let Inst{15-12} = CRd;
4757 let Inst{19-16} = CRn;
4758 let Inst{23-20} = opc1;
4761 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4762 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4763 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4764 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4765 imm:$CRm, imm:$opc2)]>,
4767 let Inst{31-28} = 0b1111;
4775 let Inst{3-0} = CRm;
4777 let Inst{7-5} = opc2;
4778 let Inst{11-8} = cop;
4779 let Inst{15-12} = CRd;
4780 let Inst{19-16} = CRn;
4781 let Inst{23-20} = opc1;
4784 class ACI<dag oops, dag iops, string opc, string asm,
4785 IndexMode im = IndexModeNone>
4786 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4788 let Inst{27-25} = 0b110;
4790 class ACInoP<dag oops, dag iops, string opc, string asm,
4791 IndexMode im = IndexModeNone>
4792 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4794 let Inst{31-28} = 0b1111;
4795 let Inst{27-25} = 0b110;
4797 multiclass LdStCop<bit load, bit Dbit, string asm> {
4798 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4799 asm, "\t$cop, $CRd, $addr"> {
4803 let Inst{24} = 1; // P = 1
4804 let Inst{23} = addr{8};
4805 let Inst{22} = Dbit;
4806 let Inst{21} = 0; // W = 0
4807 let Inst{20} = load;
4808 let Inst{19-16} = addr{12-9};
4809 let Inst{15-12} = CRd;
4810 let Inst{11-8} = cop;
4811 let Inst{7-0} = addr{7-0};
4812 let DecoderMethod = "DecodeCopMemInstruction";
4814 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4815 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4819 let Inst{24} = 1; // P = 1
4820 let Inst{23} = addr{8};
4821 let Inst{22} = Dbit;
4822 let Inst{21} = 1; // W = 1
4823 let Inst{20} = load;
4824 let Inst{19-16} = addr{12-9};
4825 let Inst{15-12} = CRd;
4826 let Inst{11-8} = cop;
4827 let Inst{7-0} = addr{7-0};
4828 let DecoderMethod = "DecodeCopMemInstruction";
4830 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4831 postidx_imm8s4:$offset),
4832 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4837 let Inst{24} = 0; // P = 0
4838 let Inst{23} = offset{8};
4839 let Inst{22} = Dbit;
4840 let Inst{21} = 1; // W = 1
4841 let Inst{20} = load;
4842 let Inst{19-16} = addr;
4843 let Inst{15-12} = CRd;
4844 let Inst{11-8} = cop;
4845 let Inst{7-0} = offset{7-0};
4846 let DecoderMethod = "DecodeCopMemInstruction";
4848 def _OPTION : ACI<(outs),
4849 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4850 coproc_option_imm:$option),
4851 asm, "\t$cop, $CRd, $addr, $option"> {
4856 let Inst{24} = 0; // P = 0
4857 let Inst{23} = 1; // U = 1
4858 let Inst{22} = Dbit;
4859 let Inst{21} = 0; // W = 0
4860 let Inst{20} = load;
4861 let Inst{19-16} = addr;
4862 let Inst{15-12} = CRd;
4863 let Inst{11-8} = cop;
4864 let Inst{7-0} = option;
4865 let DecoderMethod = "DecodeCopMemInstruction";
4868 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4869 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4870 asm, "\t$cop, $CRd, $addr"> {
4874 let Inst{24} = 1; // P = 1
4875 let Inst{23} = addr{8};
4876 let Inst{22} = Dbit;
4877 let Inst{21} = 0; // W = 0
4878 let Inst{20} = load;
4879 let Inst{19-16} = addr{12-9};
4880 let Inst{15-12} = CRd;
4881 let Inst{11-8} = cop;
4882 let Inst{7-0} = addr{7-0};
4883 let DecoderMethod = "DecodeCopMemInstruction";
4885 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4886 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4890 let Inst{24} = 1; // P = 1
4891 let Inst{23} = addr{8};
4892 let Inst{22} = Dbit;
4893 let Inst{21} = 1; // W = 1
4894 let Inst{20} = load;
4895 let Inst{19-16} = addr{12-9};
4896 let Inst{15-12} = CRd;
4897 let Inst{11-8} = cop;
4898 let Inst{7-0} = addr{7-0};
4899 let DecoderMethod = "DecodeCopMemInstruction";
4901 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4902 postidx_imm8s4:$offset),
4903 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4908 let Inst{24} = 0; // P = 0
4909 let Inst{23} = offset{8};
4910 let Inst{22} = Dbit;
4911 let Inst{21} = 1; // W = 1
4912 let Inst{20} = load;
4913 let Inst{19-16} = addr;
4914 let Inst{15-12} = CRd;
4915 let Inst{11-8} = cop;
4916 let Inst{7-0} = offset{7-0};
4917 let DecoderMethod = "DecodeCopMemInstruction";
4919 def _OPTION : ACInoP<(outs),
4920 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4921 coproc_option_imm:$option),
4922 asm, "\t$cop, $CRd, $addr, $option"> {
4927 let Inst{24} = 0; // P = 0
4928 let Inst{23} = 1; // U = 1
4929 let Inst{22} = Dbit;
4930 let Inst{21} = 0; // W = 0
4931 let Inst{20} = load;
4932 let Inst{19-16} = addr;
4933 let Inst{15-12} = CRd;
4934 let Inst{11-8} = cop;
4935 let Inst{7-0} = option;
4936 let DecoderMethod = "DecodeCopMemInstruction";
4940 defm LDC : LdStCop <1, 0, "ldc">;
4941 defm LDCL : LdStCop <1, 1, "ldcl">;
4942 defm STC : LdStCop <0, 0, "stc">;
4943 defm STCL : LdStCop <0, 1, "stcl">;
4944 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4945 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4946 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4947 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4949 //===----------------------------------------------------------------------===//
4950 // Move between coprocessor and ARM core register.
4953 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4955 : ABI<0b1110, oops, iops, NoItinerary, opc,
4956 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4957 let Inst{20} = direction;
4967 let Inst{15-12} = Rt;
4968 let Inst{11-8} = cop;
4969 let Inst{23-21} = opc1;
4970 let Inst{7-5} = opc2;
4971 let Inst{3-0} = CRm;
4972 let Inst{19-16} = CRn;
4975 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4977 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4978 c_imm:$CRm, imm0_7:$opc2),
4979 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4980 imm:$CRm, imm:$opc2)]>,
4981 ComplexDeprecationPredicate<"MCR">;
4982 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4983 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4984 c_imm:$CRm, 0, pred:$p)>;
4985 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4986 (outs GPRwithAPSR:$Rt),
4987 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4989 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4990 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4991 c_imm:$CRm, 0, pred:$p)>;
4993 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4994 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4996 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4998 : ABXI<0b1110, oops, iops, NoItinerary,
4999 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5000 let Inst{31-24} = 0b11111110;
5001 let Inst{20} = direction;
5011 let Inst{15-12} = Rt;
5012 let Inst{11-8} = cop;
5013 let Inst{23-21} = opc1;
5014 let Inst{7-5} = opc2;
5015 let Inst{3-0} = CRm;
5016 let Inst{19-16} = CRn;
5019 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5021 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5022 c_imm:$CRm, imm0_7:$opc2),
5023 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5024 imm:$CRm, imm:$opc2)]>,
5026 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5027 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5029 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5030 (outs GPRwithAPSR:$Rt),
5031 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5034 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5035 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5038 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5039 imm:$CRm, imm:$opc2),
5040 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5042 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5043 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5044 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5045 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5046 let Inst{23-21} = 0b010;
5047 let Inst{20} = direction;
5055 let Inst{15-12} = Rt;
5056 let Inst{19-16} = Rt2;
5057 let Inst{11-8} = cop;
5058 let Inst{7-4} = opc1;
5059 let Inst{3-0} = CRm;
5062 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5063 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5064 GPRnopc:$Rt2, imm:$CRm)]>;
5065 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5067 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5068 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5069 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5070 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5072 let Inst{31-28} = 0b1111;
5073 let Inst{23-21} = 0b010;
5074 let Inst{20} = direction;
5082 let Inst{15-12} = Rt;
5083 let Inst{19-16} = Rt2;
5084 let Inst{11-8} = cop;
5085 let Inst{7-4} = opc1;
5086 let Inst{3-0} = CRm;
5088 let DecoderMethod = "DecodeMRRC2";
5091 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5092 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5093 GPRnopc:$Rt2, imm:$CRm)]>;
5094 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5096 //===----------------------------------------------------------------------===//
5097 // Move between special register and ARM core register
5100 // Move to ARM core register from Special Register
5101 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5102 "mrs", "\t$Rd, apsr", []> {
5104 let Inst{23-16} = 0b00001111;
5105 let Unpredictable{19-17} = 0b111;
5107 let Inst{15-12} = Rd;
5109 let Inst{11-0} = 0b000000000000;
5110 let Unpredictable{11-0} = 0b110100001111;
5113 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5116 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5117 // section B9.3.9, with the R bit set to 1.
5118 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5119 "mrs", "\t$Rd, spsr", []> {
5121 let Inst{23-16} = 0b01001111;
5122 let Unpredictable{19-16} = 0b1111;
5124 let Inst{15-12} = Rd;
5126 let Inst{11-0} = 0b000000000000;
5127 let Unpredictable{11-0} = 0b110100001111;
5130 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5131 // separate encoding (distinguished by bit 5.
5132 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5133 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5134 Requires<[IsARM, HasVirtualization]> {
5139 let Inst{22} = banked{5}; // R bit
5140 let Inst{21-20} = 0b00;
5141 let Inst{19-16} = banked{3-0};
5142 let Inst{15-12} = Rd;
5143 let Inst{11-9} = 0b001;
5144 let Inst{8} = banked{4};
5145 let Inst{7-0} = 0b00000000;
5148 // Move from ARM core register to Special Register
5150 // No need to have both system and application versions of MSR (immediate) or
5151 // MSR (register), the encodings are the same and the assembly parser has no way
5152 // to distinguish between them. The mask operand contains the special register
5153 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5154 // accessed in the special register.
5155 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5156 "msr", "\t$mask, $Rn", []> {
5161 let Inst{22} = mask{4}; // R bit
5162 let Inst{21-20} = 0b10;
5163 let Inst{19-16} = mask{3-0};
5164 let Inst{15-12} = 0b1111;
5165 let Inst{11-4} = 0b00000000;
5169 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5170 "msr", "\t$mask, $imm", []> {
5175 let Inst{22} = mask{4}; // R bit
5176 let Inst{21-20} = 0b10;
5177 let Inst{19-16} = mask{3-0};
5178 let Inst{15-12} = 0b1111;
5179 let Inst{11-0} = imm;
5182 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5183 // separate encoding (distinguished by bit 5.
5184 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5185 NoItinerary, "msr", "\t$banked, $Rn", []>,
5186 Requires<[IsARM, HasVirtualization]> {
5191 let Inst{22} = banked{5}; // R bit
5192 let Inst{21-20} = 0b10;
5193 let Inst{19-16} = banked{3-0};
5194 let Inst{15-12} = 0b1111;
5195 let Inst{11-9} = 0b001;
5196 let Inst{8} = banked{4};
5197 let Inst{7-4} = 0b0000;
5201 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5202 // are needed to probe the stack when allocating more than
5203 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5204 // ensure that the guard pages used by the OS virtual memory manager are
5205 // allocated in correct sequence.
5206 // The main point of having separate instruction are extra unmodelled effects
5207 // (compared to ordinary calls) like stack pointer change.
5209 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5210 [SDNPHasChain, SDNPSideEffect]>;
5211 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5212 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5214 //===----------------------------------------------------------------------===//
5218 // __aeabi_read_tp preserves the registers r1-r3.
5219 // This is a pseudo inst so that we can get the encoding right,
5220 // complete with fixup for the aeabi_read_tp function.
5221 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5222 // is defined in "ARMInstrThumb.td".
5224 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5225 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5226 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5229 //===----------------------------------------------------------------------===//
5230 // SJLJ Exception handling intrinsics
5231 // eh_sjlj_setjmp() is an instruction sequence to store the return
5232 // address and save #0 in R0 for the non-longjmp case.
5233 // Since by its nature we may be coming from some other function to get
5234 // here, and we're using the stack frame for the containing function to
5235 // save/restore registers, we can't keep anything live in regs across
5236 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5237 // when we get here from a longjmp(). We force everything out of registers
5238 // except for our own input by listing the relevant registers in Defs. By
5239 // doing so, we also cause the prologue/epilogue code to actively preserve
5240 // all of the callee-saved resgisters, which is exactly what we want.
5241 // A constant value is passed in $val, and we use the location as a scratch.
5243 // These are pseudo-instructions and are lowered to individual MC-insts, so
5244 // no encoding information is necessary.
5246 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5247 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5248 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5249 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5251 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5252 Requires<[IsARM, HasVFP2]>;
5256 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5257 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5258 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5260 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5261 Requires<[IsARM, NoVFP]>;
5264 // FIXME: Non-IOS version(s)
5265 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5266 Defs = [ R7, LR, SP ] in {
5267 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5269 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5273 // eh.sjlj.dispatchsetup pseudo-instruction.
5274 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5275 // the pseudo is expanded (which happens before any passes that need the
5276 // instruction size).
5277 let isBarrier = 1 in
5278 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5281 //===----------------------------------------------------------------------===//
5282 // Non-Instruction Patterns
5285 // ARMv4 indirect branch using (MOVr PC, dst)
5286 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5287 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5288 4, IIC_Br, [(brind GPR:$dst)],
5289 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5290 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5292 // Large immediate handling.
5294 // 32-bit immediate using two piece mod_imms or movw + movt.
5295 // This is a single pseudo instruction, the benefit is that it can be remat'd
5296 // as a single unit instead of having to handle reg inputs.
5297 // FIXME: Remove this when we can do generalized remat.
5298 let isReMaterializable = 1, isMoveImm = 1 in
5299 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5300 [(set GPR:$dst, (arm_i32imm:$src))]>,
5303 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5304 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5305 Requires<[IsARM, DontUseMovt]>;
5307 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5308 // It also makes it possible to rematerialize the instructions.
5309 // FIXME: Remove this when we can do generalized remat and when machine licm
5310 // can properly the instructions.
5311 let isReMaterializable = 1 in {
5312 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5314 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5315 Requires<[IsARM, UseMovt]>;
5317 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5320 (ARMWrapperPIC tglobaladdr:$addr))]>,
5321 Requires<[IsARM, DontUseMovt]>;
5323 let AddedComplexity = 10 in
5324 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5327 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5328 Requires<[IsARM, DontUseMovt]>;
5330 let AddedComplexity = 10 in
5331 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5333 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5334 Requires<[IsARM, UseMovt]>;
5335 } // isReMaterializable
5337 // ConstantPool, GlobalAddress, and JumpTable
5338 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5339 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5340 Requires<[IsARM, UseMovt]>;
5341 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5342 (LEApcrelJT tjumptable:$dst)>;
5344 // TODO: add,sub,and, 3-instr forms?
5346 // Tail calls. These patterns also apply to Thumb mode.
5347 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5348 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5349 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5352 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5353 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5354 (BMOVPCB_CALL texternalsym:$func)>;
5356 // zextload i1 -> zextload i8
5357 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5358 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5360 // extload -> zextload
5361 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5362 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5363 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5364 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5366 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5368 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5369 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5372 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5373 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5374 (SMULBB GPR:$a, GPR:$b)>;
5375 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5376 (SMULBB GPR:$a, GPR:$b)>;
5377 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5378 (sra GPR:$b, (i32 16))),
5379 (SMULBT GPR:$a, GPR:$b)>;
5380 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5381 (SMULBT GPR:$a, GPR:$b)>;
5382 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5383 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5384 (SMULTB GPR:$a, GPR:$b)>;
5385 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5386 (SMULTB GPR:$a, GPR:$b)>;
5388 def : ARMV5MOPat<(add GPR:$acc,
5389 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5390 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5391 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5392 def : ARMV5MOPat<(add GPR:$acc,
5393 (mul sext_16_node:$a, sext_16_node:$b)),
5394 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5395 def : ARMV5MOPat<(add GPR:$acc,
5396 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5397 (sra GPR:$b, (i32 16)))),
5398 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5399 def : ARMV5MOPat<(add GPR:$acc,
5400 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5401 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5402 def : ARMV5MOPat<(add GPR:$acc,
5403 (mul (sra GPR:$a, (i32 16)),
5404 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5405 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5406 def : ARMV5MOPat<(add GPR:$acc,
5407 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5408 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5411 // Pre-v7 uses MCR for synchronization barriers.
5412 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5413 Requires<[IsARM, HasV6]>;
5415 // SXT/UXT with no rotate
5416 let AddedComplexity = 16 in {
5417 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5418 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5419 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5420 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5421 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5422 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5423 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5426 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5427 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5429 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5430 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5431 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5432 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5434 // Atomic load/store patterns
5435 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5436 (LDRBrs ldst_so_reg:$src)>;
5437 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5438 (LDRBi12 addrmode_imm12:$src)>;
5439 def : ARMPat<(atomic_load_16 addrmode3:$src),
5440 (LDRH addrmode3:$src)>;
5441 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5442 (LDRrs ldst_so_reg:$src)>;
5443 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5444 (LDRi12 addrmode_imm12:$src)>;
5445 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5446 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5447 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5448 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5449 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5450 (STRH GPR:$val, addrmode3:$ptr)>;
5451 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5452 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5453 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5454 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5457 //===----------------------------------------------------------------------===//
5461 include "ARMInstrThumb.td"
5463 //===----------------------------------------------------------------------===//
5467 include "ARMInstrThumb2.td"
5469 //===----------------------------------------------------------------------===//
5470 // Floating Point Support
5473 include "ARMInstrVFP.td"
5475 //===----------------------------------------------------------------------===//
5476 // Advanced SIMD (NEON) Support
5479 include "ARMInstrNEON.td"
5481 //===----------------------------------------------------------------------===//
5482 // Assembler aliases
5486 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5487 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5488 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5490 // System instructions
5491 def : MnemonicAlias<"swi", "svc">;
5493 // Load / Store Multiple
5494 def : MnemonicAlias<"ldmfd", "ldm">;
5495 def : MnemonicAlias<"ldmia", "ldm">;
5496 def : MnemonicAlias<"ldmea", "ldmdb">;
5497 def : MnemonicAlias<"stmfd", "stmdb">;
5498 def : MnemonicAlias<"stmia", "stm">;
5499 def : MnemonicAlias<"stmea", "stm">;
5501 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5502 // shift amount is zero (i.e., unspecified).
5503 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5504 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5505 Requires<[IsARM, HasV6]>;
5506 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5507 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5508 Requires<[IsARM, HasV6]>;
5510 // PUSH/POP aliases for STM/LDM
5511 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5512 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5514 // SSAT/USAT optional shift operand.
5515 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5516 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5517 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5518 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5521 // Extend instruction optional rotate operand.
5522 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5523 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5524 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5525 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5526 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5527 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5528 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5529 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5530 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5531 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5532 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5533 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5535 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5536 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5537 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5538 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5539 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5540 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5541 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5542 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5543 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5544 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5545 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5546 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5550 def : MnemonicAlias<"rfefa", "rfeda">;
5551 def : MnemonicAlias<"rfeea", "rfedb">;
5552 def : MnemonicAlias<"rfefd", "rfeia">;
5553 def : MnemonicAlias<"rfeed", "rfeib">;
5554 def : MnemonicAlias<"rfe", "rfeia">;
5557 def : MnemonicAlias<"srsfa", "srsib">;
5558 def : MnemonicAlias<"srsea", "srsia">;
5559 def : MnemonicAlias<"srsfd", "srsdb">;
5560 def : MnemonicAlias<"srsed", "srsda">;
5561 def : MnemonicAlias<"srs", "srsia">;
5564 def : MnemonicAlias<"qsubaddx", "qsax">;
5566 def : MnemonicAlias<"saddsubx", "sasx">;
5567 // SHASX == SHADDSUBX
5568 def : MnemonicAlias<"shaddsubx", "shasx">;
5569 // SHSAX == SHSUBADDX
5570 def : MnemonicAlias<"shsubaddx", "shsax">;
5572 def : MnemonicAlias<"ssubaddx", "ssax">;
5574 def : MnemonicAlias<"uaddsubx", "uasx">;
5575 // UHASX == UHADDSUBX
5576 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5577 // UHSAX == UHSUBADDX
5578 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5579 // UQASX == UQADDSUBX
5580 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5581 // UQSAX == UQSUBADDX
5582 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5584 def : MnemonicAlias<"usubaddx", "usax">;
5586 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5588 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5589 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5590 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5591 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5592 // Same for AND <--> BIC
5593 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5594 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5595 pred:$p, cc_out:$s)>;
5596 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5597 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5598 pred:$p, cc_out:$s)>;
5599 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5600 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5601 pred:$p, cc_out:$s)>;
5602 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5603 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5604 pred:$p, cc_out:$s)>;
5606 // Likewise, "add Rd, mod_imm_neg" -> sub
5607 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5608 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5609 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5610 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5611 // Same for CMP <--> CMN via mod_imm_neg
5612 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5613 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5614 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5615 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5617 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5618 // LSR, ROR, and RRX instructions.
5619 // FIXME: We need C++ parser hooks to map the alias to the MOV
5620 // encoding. It seems we should be able to do that sort of thing
5621 // in tblgen, but it could get ugly.
5622 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5623 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5624 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5626 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5627 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5629 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5630 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5632 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5633 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5636 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5637 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5638 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5639 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5640 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5642 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5643 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5645 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5646 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5648 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5649 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5653 // "neg" is and alias for "rsb rd, rn, #0"
5654 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5655 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5657 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5658 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5659 Requires<[IsARM, NoV6]>;
5661 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5662 // the instruction definitions need difference constraints pre-v6.
5663 // Use these aliases for the assembly parsing on pre-v6.
5664 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5665 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5666 Requires<[IsARM, NoV6]>;
5667 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5668 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5669 pred:$p, cc_out:$s)>,
5670 Requires<[IsARM, NoV6]>;
5671 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5672 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5673 Requires<[IsARM, NoV6]>;
5674 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5675 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5676 Requires<[IsARM, NoV6]>;
5677 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5678 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5679 Requires<[IsARM, NoV6]>;
5680 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5681 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5682 Requires<[IsARM, NoV6]>;
5684 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5686 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5687 ComplexDeprecationPredicate<"IT">;
5689 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5690 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5692 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;