1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
21 def SDT_ARMCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
24 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
26 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
28 def SDT_ARMCMov : SDTypeProfile<1, 3,
29 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
32 def SDT_ARMBrcond : SDTypeProfile<0, 2,
33 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
35 def SDT_ARMBrJT : SDTypeProfile<0, 3,
36 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
41 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
42 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
44 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
48 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
50 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq_start,
51 [SDNPHasChain, SDNPOutFlag]>;
52 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq_end,
53 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
59 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
60 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
63 [SDNPHasChain, SDNPOptInFlag]>;
65 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
67 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
70 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
71 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
73 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
76 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
79 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
82 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
84 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
86 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
88 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def IsThumb : Predicate<"Subtarget->isThumb()">;
97 def IsARM : Predicate<"!Subtarget->isThumb()">;
99 //===----------------------------------------------------------------------===//
100 // ARM Flag Definitions.
102 class RegConstraint<string C> {
103 string Constraints = C;
106 //===----------------------------------------------------------------------===//
107 // ARM specific transformation functions and pattern fragments.
110 // so_imm_XFORM - Return a so_imm value packed into the format described for
112 def so_imm_XFORM : SDNodeXForm<imm, [{
113 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
117 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
118 // so_imm_neg def below.
119 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
120 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
124 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
125 // so_imm_not def below.
126 def so_imm_not_XFORM : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
131 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
132 def rot_imm : PatLeaf<(i32 imm), [{
133 int32_t v = (int32_t)N->getValue();
134 return v == 8 || v == 16 || v == 24;
137 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
138 def imm1_15 : PatLeaf<(i32 imm), [{
139 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
142 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
143 def imm16_31 : PatLeaf<(i32 imm), [{
144 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
148 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
152 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
155 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
156 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
157 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
162 //===----------------------------------------------------------------------===//
163 // Operand Definitions.
167 def brtarget : Operand<OtherVT>;
169 // A list of registers separated by comma. Used by load/store multiple.
170 def reglist : Operand<i32> {
171 let PrintMethod = "printRegisterList";
174 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
175 def cpinst_operand : Operand<i32> {
176 let PrintMethod = "printCPInstOperand";
179 def jtblock_operand : Operand<i32> {
180 let PrintMethod = "printJTBlockOperand";
184 def pclabel : Operand<i32> {
185 let PrintMethod = "printPCLabel";
188 // shifter_operand operands: so_reg and so_imm.
189 def so_reg : Operand<i32>, // reg reg imm
190 ComplexPattern<i32, 3, "SelectShifterOperandReg",
191 [shl,srl,sra,rotr]> {
192 let PrintMethod = "printSORegOperand";
193 let MIOperandInfo = (ops GPR, GPR, i32imm);
196 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
197 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
198 // represented in the imm field in the same 12-bit form that they are encoded
199 // into so_imm instructions: the 8-bit immediate is the least significant bits
200 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
201 def so_imm : Operand<i32>,
203 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
205 let PrintMethod = "printSOImmOperand";
208 // Break so_imm's up into two pieces. This handles immediates with up to 16
209 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
210 // get the first/second pieces.
211 def so_imm2part : Operand<i32>,
213 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
214 let PrintMethod = "printSOImm2PartOperand";
217 def so_imm2part_1 : SDNodeXForm<imm, [{
218 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
219 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
222 def so_imm2part_2 : SDNodeXForm<imm, [{
223 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
224 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
228 // Define ARM specific addressing modes.
230 // addrmode2 := reg +/- reg shop imm
231 // addrmode2 := reg +/- imm12
233 def addrmode2 : Operand<i32>,
234 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
235 let PrintMethod = "printAddrMode2Operand";
236 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
239 def am2offset : Operand<i32>,
240 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
241 let PrintMethod = "printAddrMode2OffsetOperand";
242 let MIOperandInfo = (ops GPR, i32imm);
245 // addrmode3 := reg +/- reg
246 // addrmode3 := reg +/- imm8
248 def addrmode3 : Operand<i32>,
249 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
250 let PrintMethod = "printAddrMode3Operand";
251 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
254 def am3offset : Operand<i32>,
255 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
256 let PrintMethod = "printAddrMode3OffsetOperand";
257 let MIOperandInfo = (ops GPR, i32imm);
260 // addrmode4 := reg, <mode|W>
262 def addrmode4 : Operand<i32>,
263 ComplexPattern<i32, 2, "", []> {
264 let PrintMethod = "printAddrMode4Operand";
265 let MIOperandInfo = (ops GPR, i32imm);
268 // addrmode5 := reg +/- imm8*4
270 def addrmode5 : Operand<i32>,
271 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
272 let PrintMethod = "printAddrMode5Operand";
273 let MIOperandInfo = (ops GPR, i32imm);
276 // addrmodepc := pc + reg
278 def addrmodepc : Operand<i32>,
279 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
280 let PrintMethod = "printAddrModePCOperand";
281 let MIOperandInfo = (ops GPR, i32imm);
284 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
285 // register whose default is 0 (no register).
286 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
287 (ops (i32 14), (i32 zero_reg))> {
288 let PrintMethod = "printPredicateOperand";
291 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
293 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
294 let PrintMethod = "printSBitModifierOperand";
297 //===----------------------------------------------------------------------===//
298 // ARM Instruction flags. These need to match ARMInstrInfo.h.
302 class AddrMode<bits<4> val> {
305 def AddrModeNone : AddrMode<0>;
306 def AddrMode1 : AddrMode<1>;
307 def AddrMode2 : AddrMode<2>;
308 def AddrMode3 : AddrMode<3>;
309 def AddrMode4 : AddrMode<4>;
310 def AddrMode5 : AddrMode<5>;
311 def AddrModeT1 : AddrMode<6>;
312 def AddrModeT2 : AddrMode<7>;
313 def AddrModeT4 : AddrMode<8>;
314 def AddrModeTs : AddrMode<9>;
317 class SizeFlagVal<bits<3> val> {
320 def SizeInvalid : SizeFlagVal<0>; // Unset.
321 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
322 def Size8Bytes : SizeFlagVal<2>;
323 def Size4Bytes : SizeFlagVal<3>;
324 def Size2Bytes : SizeFlagVal<4>;
326 // Load / store index mode.
327 class IndexMode<bits<2> val> {
330 def IndexModeNone : IndexMode<0>;
331 def IndexModePre : IndexMode<1>;
332 def IndexModePost : IndexMode<2>;
334 //===----------------------------------------------------------------------===//
335 // ARM Instruction Format Definitions.
338 // Format specifies the encoding used by the instruction. This is part of the
339 // ad-hoc solution used to emit machine instruction encodings by our machine
341 class Format<bits<5> val> {
345 def Pseudo : Format<1>;
346 def MulFrm : Format<2>;
347 def MulSMLAW : Format<3>;
348 def MulSMULW : Format<4>;
349 def MulSMLA : Format<5>;
350 def MulSMUL : Format<6>;
351 def Branch : Format<7>;
352 def BranchMisc : Format<8>;
354 def DPRdIm : Format<9>;
355 def DPRdReg : Format<10>;
356 def DPRdSoReg : Format<11>;
357 def DPRdMisc : Format<12>;
358 def DPRnIm : Format<13>;
359 def DPRnReg : Format<14>;
360 def DPRnSoReg : Format<15>;
361 def DPRIm : Format<16>;
362 def DPRReg : Format<17>;
363 def DPRSoReg : Format<18>;
364 def DPRImS : Format<19>;
365 def DPRRegS : Format<20>;
366 def DPRSoRegS : Format<21>;
368 def LdFrm : Format<22>;
369 def StFrm : Format<23>;
371 def ArithMisc : Format<24>;
372 def ThumbFrm : Format<25>;
373 def VFPFrm : Format<26>;
377 //===----------------------------------------------------------------------===//
379 // ARM Instruction templates.
382 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
383 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
384 list<Predicate> Predicates = [IsARM];
386 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
387 list<Predicate> Predicates = [IsARM, HasV5TE];
389 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
390 list<Predicate> Predicates = [IsARM, HasV6];
393 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
394 Format f, string cstr>
396 let Namespace = "ARM";
398 bits<4> Opcode = opcod;
400 bits<4> AddrModeBits = AM.Value;
403 bits<3> SizeFlag = SZ.Value;
406 bits<2> IndexModeBits = IM.Value;
409 bits<5> Form = F.Value;
411 let Constraints = cstr;
414 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
415 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
416 let OutOperandList = oops;
417 let InOperandList = iops;
419 let Pattern = pattern;
422 // Almost all ARM instructions are predicable.
423 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
424 IndexMode im, Format f, string opc, string asm, string cstr,
426 : InstARM<opcod, am, sz, im, f, cstr> {
427 let OutOperandList = oops;
428 let InOperandList = !con(iops, (ops pred:$p));
429 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
430 let Pattern = pattern;
431 list<Predicate> Predicates = [IsARM];
434 // Same as I except it can optionally modify CPSR. Note it's modeled as
435 // an input operand since by default it's a zero register. It will
436 // become an implicit def once it's "flipped".
437 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
438 IndexMode im, Format f, string opc, string asm, string cstr,
440 : InstARM<opcod, am, sz, im, f, cstr> {
441 let OutOperandList = oops;
442 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
443 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
444 let Pattern = pattern;
445 list<Predicate> Predicates = [IsARM];
448 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
449 string asm, list<dag> pattern>
450 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
452 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
453 string asm, list<dag> pattern>
454 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
456 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
457 string asm, list<dag> pattern>
458 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
460 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
461 string asm, list<dag> pattern>
462 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
464 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
465 string asm, list<dag> pattern>
466 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
468 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
469 string asm, list<dag> pattern>
470 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
472 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
473 string asm, list<dag> pattern>
474 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
476 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
477 string asm, list<dag> pattern>
478 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
482 class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
483 string asm, string cstr, list<dag> pattern>
484 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
486 class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
487 string asm, string cstr, list<dag> pattern>
488 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
492 class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
493 string asm, string cstr, list<dag> pattern>
494 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
496 class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
497 string asm, string cstr, list<dag> pattern>
498 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
502 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
503 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
506 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
507 /// binop that produces a value.
508 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
509 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
510 opc, " $dst, $a, $b",
511 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
512 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
513 opc, " $dst, $a, $b",
514 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
515 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
516 opc, " $dst, $a, $b",
517 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
520 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
521 /// instruction modifies the CSPR register.
522 let Defs = [CPSR] in {
523 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
524 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
525 opc, "s $dst, $a, $b",
526 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
527 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
528 opc, "s $dst, $a, $b",
529 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
530 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
531 opc, "s $dst, $a, $b",
532 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
536 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
537 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
538 /// a explicit result, only implicitly set CPSR.
539 let Defs = [CPSR] in {
540 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
541 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
543 [(opnode GPR:$a, so_imm:$b)]>;
544 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
546 [(opnode GPR:$a, GPR:$b)]>;
547 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
549 [(opnode GPR:$a, so_reg:$b)]>;
553 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
554 /// register and one whose operand is a register rotated by 8/16/24.
555 multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
556 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
558 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
559 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
560 opc, " $dst, $Src, ror $rot",
561 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
562 Requires<[IsARM, HasV6]>;
565 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
566 /// register and one whose operand is a register rotated by 8/16/24.
567 multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
568 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
569 Pseudo, opc, " $dst, $LHS, $RHS",
570 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
571 Requires<[IsARM, HasV6]>;
572 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
573 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
574 [(set GPR:$dst, (opnode GPR:$LHS,
575 (rotr GPR:$RHS, rot_imm:$rot)))]>,
576 Requires<[IsARM, HasV6]>;
580 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
581 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
582 : InstARM<opcod, am, sz, im, f, cstr> {
583 let OutOperandList = oops;
584 let InOperandList = iops;
586 let Pattern = pattern;
587 list<Predicate> Predicates = [IsARM];
590 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
592 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
594 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
596 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
598 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
600 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
602 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
604 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
606 class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
608 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
611 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
613 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
616 // BR_JT instructions
617 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
618 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
620 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
621 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
623 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
624 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
627 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
628 /// setting carry bit. But it can optionally set CPSR.
629 let Uses = [CPSR] in {
630 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
631 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
632 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
633 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
634 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
635 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
636 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
637 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
638 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
639 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
643 //===----------------------------------------------------------------------===//
645 //===----------------------------------------------------------------------===//
647 //===----------------------------------------------------------------------===//
648 // Miscellaneous Instructions.
650 def IMPLICIT_DEF_GPR :
651 PseudoInst<(outs GPR:$rD), (ins pred:$p),
652 "@ IMPLICIT_DEF_GPR $rD",
653 [(set GPR:$rD, (undef))]>;
656 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
657 /// the function. The first operand is the ID# for this instruction, the second
658 /// is the index into the MachineConstantPool that this is, the third is the
659 /// size in bytes of this constant pool entry.
660 let isNotDuplicable = 1 in
661 def CONSTPOOL_ENTRY :
662 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
664 "${instid:label} ${cpidx:cpentry}", []>;
666 let Defs = [SP], Uses = [SP] in {
668 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
669 "@ ADJCALLSTACKUP $amt1",
670 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
672 def ADJCALLSTACKDOWN :
673 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
674 "@ ADJCALLSTACKDOWN $amt",
675 [(ARMcallseq_start imm:$amt)]>;
679 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
680 ".loc $file, $line, $col",
681 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
683 let isNotDuplicable = 1 in {
684 def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
685 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
686 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
688 let isLoad = 1, AddedComplexity = 10 in {
689 def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
690 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
691 [(set GPR:$dst, (load addrmodepc:$addr))]>;
693 def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
694 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
695 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
697 def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
698 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
699 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
701 def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
702 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
703 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
705 def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
706 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
707 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
709 def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
710 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
711 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
713 def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
714 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
715 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
717 let isStore = 1, AddedComplexity = 10 in {
718 def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
719 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
720 [(store GPR:$src, addrmodepc:$addr)]>;
722 def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
723 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
724 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
726 def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
727 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
728 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
732 //===----------------------------------------------------------------------===//
733 // Control Flow Instructions.
736 let isReturn = 1, isTerminator = 1 in
737 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
739 // FIXME: remove when we have a way to marking a MI with these properties.
740 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
742 let isLoad = 1, isReturn = 1, isTerminator = 1 in
743 def LDM_RET : AXI4<0x0, (outs),
744 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
745 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
749 Defs = [R0, R1, R2, R3, R12, LR,
750 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
751 def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
753 [(ARMcall tglobaladdr:$func)]>;
755 def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops),
756 Branch, "bl", " ${func:call}",
757 [(ARMcall_pred tglobaladdr:$func)]>;
760 def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
762 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
765 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
766 BranchMisc, "mov lr, pc\n\tbx $func",
767 [(ARMcall_nolink GPR:$func)]>;
771 let isBranch = 1, isTerminator = 1 in {
772 // B is "predicable" since it can be xformed into a Bcc.
773 let isBarrier = 1 in {
774 let isPredicable = 1 in
775 def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
778 let isNotDuplicable = 1, isIndirectBranch = 1 in {
779 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
780 "mov pc, $target \n$jt",
781 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
782 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
783 "ldr pc, $target \n$jt",
784 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
786 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
788 "add pc, $target, $idx \n$jt",
789 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
794 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
795 // a two-value operand where a dag node expects two operands. :(
796 def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch,
798 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
801 //===----------------------------------------------------------------------===//
802 // Load / store Instructions.
807 def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
808 "ldr", " $dst, $addr",
809 [(set GPR:$dst, (load addrmode2:$addr))]>;
811 // Special LDR for loads from non-pc-relative constpools.
812 let isReMaterializable = 1 in
813 def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
814 "ldr", " $dst, $addr", []>;
816 // Loads with zero extension
817 def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
818 "ldr", "h $dst, $addr",
819 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
821 def LDRB : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
822 "ldr", "b $dst, $addr",
823 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
825 // Loads with sign extension
826 def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
827 "ldr", "sh $dst, $addr",
828 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
830 def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
831 "ldr", "sb $dst, $addr",
832 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
835 def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
836 "ldr", "d $dst, $addr",
837 []>, Requires<[IsARM, HasV5T]>;
840 def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb),
841 (ins addrmode2:$addr), LdFrm,
842 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
844 def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb),
845 (ins GPR:$base, am2offset:$offset), LdFrm,
846 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
848 def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
849 (ins addrmode3:$addr), LdFrm,
850 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
852 def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
853 (ins GPR:$base,am3offset:$offset), LdFrm,
854 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
856 def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb),
857 (ins addrmode2:$addr), LdFrm,
858 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
860 def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb),
861 (ins GPR:$base,am2offset:$offset), LdFrm,
862 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
864 def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
865 (ins addrmode3:$addr), LdFrm,
866 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
868 def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
869 (ins GPR:$base,am3offset:$offset), LdFrm,
870 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
872 def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
873 (ins addrmode3:$addr), LdFrm,
874 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
876 def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
877 (ins GPR:$base,am3offset:$offset), LdFrm,
878 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
883 def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
884 "str", " $src, $addr",
885 [(store GPR:$src, addrmode2:$addr)]>;
887 // Stores with truncate
888 def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
889 "str", "h $src, $addr",
890 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
892 def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
893 "str", "b $src, $addr",
894 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
897 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
898 "str", "d $src, $addr",
899 []>, Requires<[IsARM, HasV5T]>;
902 def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb),
903 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
904 "str", " $src, [$base, $offset]!", "$base = $base_wb",
906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
908 def STR_POST : AI2po<0x0, (outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
910 "str", " $src, [$base], $offset", "$base = $base_wb",
912 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
914 def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
915 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
916 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
918 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
920 def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
921 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
922 "str", "h $src, [$base], $offset", "$base = $base_wb",
923 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
924 GPR:$base, am3offset:$offset))]>;
926 def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb),
927 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
928 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
929 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
930 GPR:$base, am2offset:$offset))]>;
932 def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
933 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
934 "str", "b $src, [$base], $offset", "$base = $base_wb",
935 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
936 GPR:$base, am2offset:$offset))]>;
939 //===----------------------------------------------------------------------===//
940 // Load / store multiple Instructions.
943 // FIXME: $dst1 should be a def.
945 def LDM : AXI4<0x0, (outs),
946 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
947 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
951 def STM : AXI4<0x0, (outs),
952 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
953 StFrm, "stm${p}${addr:submode} $addr, $src1",
956 //===----------------------------------------------------------------------===//
957 // Move Instructions.
960 def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
961 "mov", " $dst, $src", []>;
962 def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
963 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
965 let isReMaterializable = 1 in
966 def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
967 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
969 def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
970 "mov", " $dst, $src, rrx",
971 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
973 // These aren't really mov instructions, but we have to define them this way
974 // due to flag operands.
976 let Defs = [CPSR] in {
977 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
978 "mov", "s $dst, $src, lsr #1",
979 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
980 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
981 "mov", "s $dst, $src, asr #1",
982 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
985 //===----------------------------------------------------------------------===//
986 // Extend Instructions.
991 defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
992 defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
994 defm SXTAB : AI_bin_rrot<0x0, "sxtab",
995 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
996 defm SXTAH : AI_bin_rrot<0x0, "sxtah",
997 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
999 // TODO: SXT(A){B|H}16
1003 let AddedComplexity = 16 in {
1004 defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1005 defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1006 defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1008 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
1009 (UXTB16r_rot GPR:$Src, 24)>;
1010 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
1011 (UXTB16r_rot GPR:$Src, 8)>;
1013 defm UXTAB : AI_bin_rrot<0x0, "uxtab",
1014 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1015 defm UXTAH : AI_bin_rrot<0x0, "uxtah",
1016 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1019 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1020 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1022 // TODO: UXT(A){B|H}16
1024 //===----------------------------------------------------------------------===//
1025 // Arithmetic Instructions.
1028 defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
1029 defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1031 // ADD and SUB with 's' bit set.
1032 defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1033 defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1035 // FIXME: Do not allow ADC / SBC to be predicated for now.
1036 defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
1037 defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1039 // These don't define reg/reg forms, because they are handled above.
1040 def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1041 "rsb", " $dst, $a, $b",
1042 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
1044 def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1045 "rsb", " $dst, $a, $b",
1046 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1048 // RSB with 's' bit set.
1049 let Defs = [CPSR] in {
1050 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
1051 "rsb", "s $dst, $a, $b",
1052 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
1053 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
1054 "rsb", "s $dst, $a, $b",
1055 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1058 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
1059 let Uses = [CPSR] in {
1060 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
1061 DPRIm, "rsc${s} $dst, $a, $b",
1062 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
1063 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
1064 DPRSoReg, "rsc${s} $dst, $a, $b",
1065 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
1068 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1069 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1070 (SUBri GPR:$src, so_imm_neg:$imm)>;
1072 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1073 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1074 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1075 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1077 // Note: These are implemented in C++ code, because they have to generate
1078 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1080 // (mul X, 2^n+1) -> (add (X << n), X)
1081 // (mul X, 2^n-1) -> (rsb X, (X << n))
1084 //===----------------------------------------------------------------------===//
1085 // Bitwise Instructions.
1088 defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
1089 defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
1090 defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
1091 defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1093 def MVNr : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
1094 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
1095 def MVNs : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
1096 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
1097 let isReMaterializable = 1 in
1098 def MVNi : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
1099 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
1101 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1102 (BICri GPR:$src, so_imm_not:$imm)>;
1104 //===----------------------------------------------------------------------===//
1105 // Multiply Instructions.
1108 def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1109 "mul", " $dst, $a, $b",
1110 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1112 def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1113 MulFrm, "mla", " $dst, $a, $b, $c",
1114 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1116 // Extra precision multiplies with low / high results
1117 def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1118 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
1120 def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1121 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
1123 // Multiply + accumulate
1124 def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1125 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
1127 def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
1128 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
1130 def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
1131 "umaal", " $ldst, $hdst, $a, $b", []>,
1132 Requires<[IsARM, HasV6]>;
1134 // Most significant word multiply
1135 def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
1136 "smmul", " $dst, $a, $b",
1137 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1138 Requires<[IsARM, HasV6]>;
1140 def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1141 "smmla", " $dst, $a, $b, $c",
1142 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1143 Requires<[IsARM, HasV6]>;
1146 def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
1147 "smmls", " $dst, $a, $b, $c",
1148 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1149 Requires<[IsARM, HasV6]>;
1151 multiclass AI_smul<string opc, PatFrag opnode> {
1152 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1153 !strconcat(opc, "bb"), " $dst, $a, $b",
1154 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1155 (sext_inreg GPR:$b, i16)))]>,
1156 Requires<[IsARM, HasV5TE]>;
1158 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1159 !strconcat(opc, "bt"), " $dst, $a, $b",
1160 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1161 (sra GPR:$b, 16)))]>,
1162 Requires<[IsARM, HasV5TE]>;
1164 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1165 !strconcat(opc, "tb"), " $dst, $a, $b",
1166 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1167 (sext_inreg GPR:$b, i16)))]>,
1168 Requires<[IsARM, HasV5TE]>;
1170 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
1171 !strconcat(opc, "tt"), " $dst, $a, $b",
1172 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1173 (sra GPR:$b, 16)))]>,
1174 Requires<[IsARM, HasV5TE]>;
1176 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1177 !strconcat(opc, "wb"), " $dst, $a, $b",
1178 [(set GPR:$dst, (sra (opnode GPR:$a,
1179 (sext_inreg GPR:$b, i16)), 16))]>,
1180 Requires<[IsARM, HasV5TE]>;
1182 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
1183 !strconcat(opc, "wt"), " $dst, $a, $b",
1184 [(set GPR:$dst, (sra (opnode GPR:$a,
1185 (sra GPR:$b, 16)), 16))]>,
1186 Requires<[IsARM, HasV5TE]>;
1190 multiclass AI_smla<string opc, PatFrag opnode> {
1191 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1192 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1193 [(set GPR:$dst, (add GPR:$acc,
1194 (opnode (sext_inreg GPR:$a, i16),
1195 (sext_inreg GPR:$b, i16))))]>,
1196 Requires<[IsARM, HasV5TE]>;
1198 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1199 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1200 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1201 (sra GPR:$b, 16))))]>,
1202 Requires<[IsARM, HasV5TE]>;
1204 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1205 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1206 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1207 (sext_inreg GPR:$b, i16))))]>,
1208 Requires<[IsARM, HasV5TE]>;
1210 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1211 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1212 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1213 (sra GPR:$b, 16))))]>,
1214 Requires<[IsARM, HasV5TE]>;
1216 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1217 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1218 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1219 (sext_inreg GPR:$b, i16)), 16)))]>,
1220 Requires<[IsARM, HasV5TE]>;
1222 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1223 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1224 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1225 (sra GPR:$b, 16)), 16)))]>,
1226 Requires<[IsARM, HasV5TE]>;
1229 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1230 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1232 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1233 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1235 //===----------------------------------------------------------------------===//
1236 // Misc. Arithmetic Instructions.
1239 def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1240 "clz", " $dst, $src",
1241 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1243 def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1244 "rev", " $dst, $src",
1245 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1247 def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1248 "rev16", " $dst, $src",
1250 (or (and (srl GPR:$src, 8), 0xFF),
1251 (or (and (shl GPR:$src, 8), 0xFF00),
1252 (or (and (srl GPR:$src, 8), 0xFF0000),
1253 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1254 Requires<[IsARM, HasV6]>;
1256 def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1257 "revsh", " $dst, $src",
1260 (or (srl (and GPR:$src, 0xFF00), 8),
1261 (shl GPR:$src, 8)), i16))]>,
1262 Requires<[IsARM, HasV6]>;
1264 def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1265 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1266 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1267 (and (shl GPR:$src2, (i32 imm:$shamt)),
1269 Requires<[IsARM, HasV6]>;
1271 // Alternate cases for PKHBT where identities eliminate some nodes.
1272 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1273 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1274 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1275 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1278 def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1279 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1280 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1281 (and (sra GPR:$src2, imm16_31:$shamt),
1282 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1284 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1285 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1286 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1287 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1288 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1289 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1290 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1293 //===----------------------------------------------------------------------===//
1294 // Comparison Instructions...
1297 defm CMP : AI1_cmp_irs<0xA, "cmp",
1298 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1299 defm CMN : AI1_cmp_irs<0xB, "cmn",
1300 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1302 // Note that TST/TEQ don't set all the same flags that CMP does!
1303 defm TST : AI1_cmp_irs<0x8, "tst",
1304 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1305 defm TEQ : AI1_cmp_irs<0x9, "teq",
1306 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1308 defm CMPnz : AI1_cmp_irs<0xA, "cmp",
1309 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1310 defm CMNnz : AI1_cmp_irs<0xA, "cmn",
1311 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1313 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1314 (CMNri GPR:$src, so_imm_neg:$imm)>;
1316 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1317 (CMNri GPR:$src, so_imm_neg:$imm)>;
1320 // Conditional moves
1321 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1322 // a two-value operand where a dag node expects two operands. :(
1323 def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
1324 DPRdReg, "mov", " $dst, $true",
1325 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1326 RegConstraint<"$false = $dst">;
1328 def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1329 DPRdSoReg, "mov", " $dst, $true",
1330 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1331 RegConstraint<"$false = $dst">;
1333 def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1334 DPRdIm, "mov", " $dst, $true",
1335 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1336 RegConstraint<"$false = $dst">;
1339 // LEApcrel - Load a pc-relative address into a register without offending the
1341 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1342 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1343 "${:private}PCRELL${:uid}+8))\n"),
1344 !strconcat("${:private}PCRELL${:uid}:\n\t",
1345 "add$p $dst, pc, #PCRELV${:uid}")),
1348 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1350 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1351 "${:private}PCRELL${:uid}+8))\n"),
1352 !strconcat("${:private}PCRELL${:uid}:\n\t",
1353 "add$p $dst, pc, #PCRELV${:uid}")),
1356 //===----------------------------------------------------------------------===//
1360 // __aeabi_read_tp preserves the registers r1-r3.
1362 Defs = [R0, R12, LR, CPSR] in {
1363 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
1364 "bl __aeabi_read_tp",
1365 [(set R0, ARMthread_pointer)]>;
1368 //===----------------------------------------------------------------------===//
1369 // Non-Instruction Patterns
1372 // ConstantPool, GlobalAddress, and JumpTable
1373 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1374 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1375 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1376 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1378 // Large immediate handling.
1380 // Two piece so_imms.
1381 let isReMaterializable = 1 in
1382 def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
1383 "mov", " $dst, $src",
1384 [(set GPR:$dst, so_imm2part:$src)]>;
1386 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1387 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1388 (so_imm2part_2 imm:$RHS))>;
1389 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1390 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1391 (so_imm2part_2 imm:$RHS))>;
1393 // TODO: add,sub,and, 3-instr forms?
1397 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1399 // zextload i1 -> zextload i8
1400 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1402 // extload -> zextload
1403 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1404 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1405 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1407 // truncstore i1 -> truncstore i8
1408 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1409 (STRB GPR:$src, addrmode2:$dst)>;
1410 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1411 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1412 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1413 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1416 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1417 (SMULBB GPR:$a, GPR:$b)>;
1418 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1419 (SMULBB GPR:$a, GPR:$b)>;
1420 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1421 (SMULBT GPR:$a, GPR:$b)>;
1422 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1423 (SMULBT GPR:$a, GPR:$b)>;
1424 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1425 (SMULTB GPR:$a, GPR:$b)>;
1426 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1427 (SMULTB GPR:$a, GPR:$b)>;
1428 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1429 (SMULWB GPR:$a, GPR:$b)>;
1430 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1431 (SMULWB GPR:$a, GPR:$b)>;
1433 def : ARMV5TEPat<(add GPR:$acc,
1434 (mul (sra (shl GPR:$a, 16), 16),
1435 (sra (shl GPR:$b, 16), 16))),
1436 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1437 def : ARMV5TEPat<(add GPR:$acc,
1438 (mul sext_16_node:$a, sext_16_node:$b)),
1439 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1440 def : ARMV5TEPat<(add GPR:$acc,
1441 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1442 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1443 def : ARMV5TEPat<(add GPR:$acc,
1444 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1445 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1446 def : ARMV5TEPat<(add GPR:$acc,
1447 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1448 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1449 def : ARMV5TEPat<(add GPR:$acc,
1450 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1451 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1452 def : ARMV5TEPat<(add GPR:$acc,
1453 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1454 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1455 def : ARMV5TEPat<(add GPR:$acc,
1456 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1457 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1459 //===----------------------------------------------------------------------===//
1463 include "ARMInstrThumb.td"
1465 //===----------------------------------------------------------------------===//
1466 // Floating Point Support
1469 include "ARMInstrVFP.td"