1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
215 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
216 AssemblerPredicate<"!FeatureVFPOnlySP",
217 "double precision VFP">;
218 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
220 def HasNEON : Predicate<"Subtarget->hasNEON()">,
221 AssemblerPredicate<"FeatureNEON", "NEON">;
222 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
223 AssemblerPredicate<"FeatureCrypto", "crypto">;
224 def HasCRC : Predicate<"Subtarget->hasCRC()">,
225 AssemblerPredicate<"FeatureCRC", "crc">;
226 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
227 AssemblerPredicate<"FeatureFP16","half-float">;
228 def HasDivide : Predicate<"Subtarget->hasDivide()">,
229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
230 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
232 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
233 AssemblerPredicate<"FeatureT2XtPk",
235 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
236 AssemblerPredicate<"FeatureDSPThumb2",
238 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
239 AssemblerPredicate<"FeatureDB",
241 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
242 AssemblerPredicate<"FeatureMP",
244 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
245 AssemblerPredicate<"FeatureTrustZone",
247 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
248 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
249 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
250 def IsThumb : Predicate<"Subtarget->isThumb()">,
251 AssemblerPredicate<"ModeThumb", "thumb">;
252 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
253 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
254 AssemblerPredicate<"ModeThumb,FeatureThumb2",
256 def IsMClass : Predicate<"Subtarget->isMClass()">,
257 AssemblerPredicate<"FeatureMClass", "armv*m">;
258 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
259 AssemblerPredicate<"!FeatureMClass",
261 def IsARM : Predicate<"!Subtarget->isThumb()">,
262 AssemblerPredicate<"!ModeThumb", "arm-mode">;
263 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
264 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
265 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
266 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
267 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
268 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
269 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
270 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
272 // FIXME: Eventually this will be just "hasV6T2Ops".
273 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
274 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
275 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
276 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
278 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
279 // But only select them if more precision in FP computation is allowed.
280 // Do not use them for Darwin platforms.
281 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
282 " FPOpFusion::Fast && "
283 " Subtarget->hasVFP4()) && "
284 "!Subtarget->isTargetDarwin()">;
285 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
286 " FPOpFusion::Fast &&"
287 " Subtarget->hasVFP4()) || "
288 "Subtarget->isTargetDarwin()">;
290 // VGETLNi32 is microcoded on Swift - prefer VMOV.
291 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
292 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
294 // VDUP.32 is microcoded on Swift - prefer VMOV.
295 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
296 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
298 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
299 // this allows more effective execution domain optimization. See
300 // setExecutionDomain().
301 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
302 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
304 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
305 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
307 //===----------------------------------------------------------------------===//
308 // ARM Flag Definitions.
310 class RegConstraint<string C> {
311 string Constraints = C;
314 //===----------------------------------------------------------------------===//
315 // ARM specific transformation functions and pattern fragments.
318 // imm_neg_XFORM - Return the negation of an i32 immediate value.
319 def imm_neg_XFORM : SDNodeXForm<imm, [{
320 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
323 // imm_not_XFORM - Return the complement of a i32 immediate value.
324 def imm_not_XFORM : SDNodeXForm<imm, [{
325 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
328 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
329 def imm16_31 : ImmLeaf<i32, [{
330 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
333 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
334 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
335 unsigned Value = -(unsigned)N->getZExtValue();
336 return Value && ARM_AM::getSOImmVal(Value) != -1;
338 let ParserMatchClass = so_imm_neg_asmoperand;
341 // Note: this pattern doesn't require an encoder method and such, as it's
342 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
343 // is handled by the destination instructions, which use so_imm.
344 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
345 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
346 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
348 let ParserMatchClass = so_imm_not_asmoperand;
351 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
352 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
353 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
356 /// Split a 32-bit immediate into two 16 bit parts.
357 def hi16 : SDNodeXForm<imm, [{
358 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
361 def lo16AllZero : PatLeaf<(i32 imm), [{
362 // Returns true if all low 16-bits are 0.
363 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
366 class BinOpWithFlagFrag<dag res> :
367 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
368 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
369 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
371 // An 'and' node with a single use.
372 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
373 return N->hasOneUse();
376 // An 'xor' node with a single use.
377 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
378 return N->hasOneUse();
381 // An 'fmul' node with a single use.
382 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
383 return N->hasOneUse();
386 // An 'fadd' node which checks for single non-hazardous use.
387 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
388 return hasNoVMLxHazardUse(N);
391 // An 'fsub' node which checks for single non-hazardous use.
392 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
393 return hasNoVMLxHazardUse(N);
396 //===----------------------------------------------------------------------===//
397 // Operand Definitions.
400 // Immediate operands with a shared generic asm render method.
401 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
404 // FIXME: rename brtarget to t2_brtarget
405 def brtarget : Operand<OtherVT> {
406 let EncoderMethod = "getBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
408 let DecoderMethod = "DecodeT2BROperand";
411 // FIXME: get rid of this one?
412 def uncondbrtarget : Operand<OtherVT> {
413 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // Branch target for ARM. Handles conditional/unconditional
418 def br_target : Operand<OtherVT> {
419 let EncoderMethod = "getARMBranchTargetOpValue";
420 let OperandType = "OPERAND_PCREL";
424 // FIXME: rename bltarget to t2_bl_target?
425 def bltarget : Operand<i32> {
426 // Encoded the same as branch targets.
427 let EncoderMethod = "getBranchTargetOpValue";
428 let OperandType = "OPERAND_PCREL";
431 // Call target for ARM. Handles conditional/unconditional
432 // FIXME: rename bl_target to t2_bltarget?
433 def bl_target : Operand<i32> {
434 let EncoderMethod = "getARMBLTargetOpValue";
435 let OperandType = "OPERAND_PCREL";
438 def blx_target : Operand<i32> {
439 let EncoderMethod = "getARMBLXTargetOpValue";
440 let OperandType = "OPERAND_PCREL";
443 // A list of registers separated by comma. Used by load/store multiple.
444 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
445 def reglist : Operand<i32> {
446 let EncoderMethod = "getRegisterListOpValue";
447 let ParserMatchClass = RegListAsmOperand;
448 let PrintMethod = "printRegisterList";
449 let DecoderMethod = "DecodeRegListOperand";
452 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
454 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
455 def dpr_reglist : Operand<i32> {
456 let EncoderMethod = "getRegisterListOpValue";
457 let ParserMatchClass = DPRRegListAsmOperand;
458 let PrintMethod = "printRegisterList";
459 let DecoderMethod = "DecodeDPRRegListOperand";
462 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
463 def spr_reglist : Operand<i32> {
464 let EncoderMethod = "getRegisterListOpValue";
465 let ParserMatchClass = SPRRegListAsmOperand;
466 let PrintMethod = "printRegisterList";
467 let DecoderMethod = "DecodeSPRRegListOperand";
470 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
471 def cpinst_operand : Operand<i32> {
472 let PrintMethod = "printCPInstOperand";
476 def pclabel : Operand<i32> {
477 let PrintMethod = "printPCLabel";
480 // ADR instruction labels.
481 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
482 def adrlabel : Operand<i32> {
483 let EncoderMethod = "getAdrLabelOpValue";
484 let ParserMatchClass = AdrLabelAsmOperand;
485 let PrintMethod = "printAdrLabelOperand<0>";
488 def neon_vcvt_imm32 : Operand<i32> {
489 let EncoderMethod = "getNEONVcvtImm32OpValue";
490 let DecoderMethod = "DecodeVCVTImmOperand";
493 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
494 def rot_imm_XFORM: SDNodeXForm<imm, [{
495 switch (N->getZExtValue()){
496 default: llvm_unreachable(nullptr);
497 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
498 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
499 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
500 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
503 def RotImmAsmOperand : AsmOperandClass {
505 let ParserMethod = "parseRotImm";
507 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
508 int32_t v = N->getZExtValue();
509 return v == 8 || v == 16 || v == 24; }],
511 let PrintMethod = "printRotImmOperand";
512 let ParserMatchClass = RotImmAsmOperand;
515 // shift_imm: An integer that encodes a shift amount and the type of shift
516 // (asr or lsl). The 6-bit immediate encodes as:
519 // {4-0} imm5 shift amount.
520 // asr #32 encoded as imm5 == 0.
521 def ShifterImmAsmOperand : AsmOperandClass {
522 let Name = "ShifterImm";
523 let ParserMethod = "parseShifterImm";
525 def shift_imm : Operand<i32> {
526 let PrintMethod = "printShiftImmOperand";
527 let ParserMatchClass = ShifterImmAsmOperand;
530 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
531 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
532 def so_reg_reg : Operand<i32>, // reg reg imm
533 ComplexPattern<i32, 3, "SelectRegShifterOperand",
534 [shl, srl, sra, rotr]> {
535 let EncoderMethod = "getSORegRegOpValue";
536 let PrintMethod = "printSORegRegOperand";
537 let DecoderMethod = "DecodeSORegRegOperand";
538 let ParserMatchClass = ShiftedRegAsmOperand;
539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
542 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
543 def so_reg_imm : Operand<i32>, // reg imm
544 ComplexPattern<i32, 2, "SelectImmShifterOperand",
545 [shl, srl, sra, rotr]> {
546 let EncoderMethod = "getSORegImmOpValue";
547 let PrintMethod = "printSORegImmOperand";
548 let DecoderMethod = "DecodeSORegImmOperand";
549 let ParserMatchClass = ShiftedImmAsmOperand;
550 let MIOperandInfo = (ops GPR, i32imm);
553 // FIXME: Does this need to be distinct from so_reg?
554 def shift_so_reg_reg : Operand<i32>, // reg reg imm
555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
556 [shl,srl,sra,rotr]> {
557 let EncoderMethod = "getSORegRegOpValue";
558 let PrintMethod = "printSORegRegOperand";
559 let DecoderMethod = "DecodeSORegRegOperand";
560 let ParserMatchClass = ShiftedRegAsmOperand;
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
564 // FIXME: Does this need to be distinct from so_reg?
565 def shift_so_reg_imm : Operand<i32>, // reg reg imm
566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
567 [shl,srl,sra,rotr]> {
568 let EncoderMethod = "getSORegImmOpValue";
569 let PrintMethod = "printSORegImmOperand";
570 let DecoderMethod = "DecodeSORegImmOperand";
571 let ParserMatchClass = ShiftedImmAsmOperand;
572 let MIOperandInfo = (ops GPR, i32imm);
576 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
577 // 8-bit immediate rotated by an arbitrary number of bits.
578 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
579 def so_imm : Operand<i32>, ImmLeaf<i32, [{
580 return ARM_AM::getSOImmVal(Imm) != -1;
582 let EncoderMethod = "getSOImmOpValue";
583 let ParserMatchClass = SOImmAsmOperand;
584 let DecoderMethod = "DecodeSOImmOperand";
587 // Break so_imm's up into two pieces. This handles immediates with up to 16
588 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
589 // get the first/second pieces.
590 def so_imm2part : PatLeaf<(imm), [{
591 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
594 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
596 def arm_i32imm : PatLeaf<(imm), [{
597 if (Subtarget->useMovt(*MF))
599 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
602 /// imm0_1 predicate - Immediate in the range [0,1].
603 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
604 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
606 /// imm0_3 predicate - Immediate in the range [0,3].
607 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
608 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
610 /// imm0_7 predicate - Immediate in the range [0,7].
611 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
612 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
613 return Imm >= 0 && Imm < 8;
615 let ParserMatchClass = Imm0_7AsmOperand;
618 /// imm8 predicate - Immediate is exactly 8.
619 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
620 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
621 let ParserMatchClass = Imm8AsmOperand;
624 /// imm16 predicate - Immediate is exactly 16.
625 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
626 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
627 let ParserMatchClass = Imm16AsmOperand;
630 /// imm32 predicate - Immediate is exactly 32.
631 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
632 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
633 let ParserMatchClass = Imm32AsmOperand;
636 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
638 /// imm1_7 predicate - Immediate in the range [1,7].
639 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
640 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
641 let ParserMatchClass = Imm1_7AsmOperand;
644 /// imm1_15 predicate - Immediate in the range [1,15].
645 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
646 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
647 let ParserMatchClass = Imm1_15AsmOperand;
650 /// imm1_31 predicate - Immediate in the range [1,31].
651 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
652 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
653 let ParserMatchClass = Imm1_31AsmOperand;
656 /// imm0_15 predicate - Immediate in the range [0,15].
657 def Imm0_15AsmOperand: ImmAsmOperand {
658 let Name = "Imm0_15";
659 let DiagnosticType = "ImmRange0_15";
661 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
662 return Imm >= 0 && Imm < 16;
664 let ParserMatchClass = Imm0_15AsmOperand;
667 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
668 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
669 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
670 return Imm >= 0 && Imm < 32;
672 let ParserMatchClass = Imm0_31AsmOperand;
675 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
676 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
677 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
678 return Imm >= 0 && Imm < 32;
680 let ParserMatchClass = Imm0_32AsmOperand;
683 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
684 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
685 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
686 return Imm >= 0 && Imm < 64;
688 let ParserMatchClass = Imm0_63AsmOperand;
691 /// imm0_239 predicate - Immediate in the range [0,239].
692 def Imm0_239AsmOperand : ImmAsmOperand {
693 let Name = "Imm0_239";
694 let DiagnosticType = "ImmRange0_239";
696 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
697 let ParserMatchClass = Imm0_239AsmOperand;
700 /// imm0_255 predicate - Immediate in the range [0,255].
701 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
702 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
703 let ParserMatchClass = Imm0_255AsmOperand;
706 /// imm0_65535 - An immediate is in the range [0.65535].
707 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
708 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
709 return Imm >= 0 && Imm < 65536;
711 let ParserMatchClass = Imm0_65535AsmOperand;
714 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
715 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
716 return -Imm >= 0 && -Imm < 65536;
719 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
720 // a relocatable expression.
722 // FIXME: This really needs a Thumb version separate from the ARM version.
723 // While the range is the same, and can thus use the same match class,
724 // the encoding is different so it should have a different encoder method.
725 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
726 def imm0_65535_expr : Operand<i32> {
727 let EncoderMethod = "getHiLo16ImmOpValue";
728 let ParserMatchClass = Imm0_65535ExprAsmOperand;
731 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
732 def imm256_65535_expr : Operand<i32> {
733 let ParserMatchClass = Imm256_65535ExprAsmOperand;
736 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
737 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
738 def imm24b : Operand<i32>, ImmLeaf<i32, [{
739 return Imm >= 0 && Imm <= 0xffffff;
741 let ParserMatchClass = Imm24bitAsmOperand;
745 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
747 def BitfieldAsmOperand : AsmOperandClass {
748 let Name = "Bitfield";
749 let ParserMethod = "parseBitfield";
752 def bf_inv_mask_imm : Operand<i32>,
754 return ARM::isBitFieldInvertedMask(N->getZExtValue());
756 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
757 let PrintMethod = "printBitfieldInvMaskImmOperand";
758 let DecoderMethod = "DecodeBitfieldMaskOperand";
759 let ParserMatchClass = BitfieldAsmOperand;
762 def imm1_32_XFORM: SDNodeXForm<imm, [{
763 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
765 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
766 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
767 uint64_t Imm = N->getZExtValue();
768 return Imm > 0 && Imm <= 32;
771 let PrintMethod = "printImmPlusOneOperand";
772 let ParserMatchClass = Imm1_32AsmOperand;
775 def imm1_16_XFORM: SDNodeXForm<imm, [{
776 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
778 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
779 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
781 let PrintMethod = "printImmPlusOneOperand";
782 let ParserMatchClass = Imm1_16AsmOperand;
785 // Define ARM specific addressing modes.
786 // addrmode_imm12 := reg +/- imm12
788 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
789 class AddrMode_Imm12 : Operand<i32>,
790 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
791 // 12-bit immediate operand. Note that instructions using this encode
792 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
793 // immediate values are as normal.
795 let EncoderMethod = "getAddrModeImm12OpValue";
796 let DecoderMethod = "DecodeAddrModeImm12Operand";
797 let ParserMatchClass = MemImm12OffsetAsmOperand;
798 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
801 def addrmode_imm12 : AddrMode_Imm12 {
802 let PrintMethod = "printAddrModeImm12Operand<false>";
805 def addrmode_imm12_pre : AddrMode_Imm12 {
806 let PrintMethod = "printAddrModeImm12Operand<true>";
809 // ldst_so_reg := reg +/- reg shop imm
811 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
812 def ldst_so_reg : Operand<i32>,
813 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
814 let EncoderMethod = "getLdStSORegOpValue";
815 // FIXME: Simplify the printer
816 let PrintMethod = "printAddrMode2Operand";
817 let DecoderMethod = "DecodeSORegMemOperand";
818 let ParserMatchClass = MemRegOffsetAsmOperand;
819 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
822 // postidx_imm8 := +/- [0,255]
825 // {8} 1 is imm8 is non-negative. 0 otherwise.
826 // {7-0} [0,255] imm8 value.
827 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
828 def postidx_imm8 : Operand<i32> {
829 let PrintMethod = "printPostIdxImm8Operand";
830 let ParserMatchClass = PostIdxImm8AsmOperand;
831 let MIOperandInfo = (ops i32imm);
834 // postidx_imm8s4 := +/- [0,1020]
837 // {8} 1 is imm8 is non-negative. 0 otherwise.
838 // {7-0} [0,255] imm8 value, scaled by 4.
839 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
840 def postidx_imm8s4 : Operand<i32> {
841 let PrintMethod = "printPostIdxImm8s4Operand";
842 let ParserMatchClass = PostIdxImm8s4AsmOperand;
843 let MIOperandInfo = (ops i32imm);
847 // postidx_reg := +/- reg
849 def PostIdxRegAsmOperand : AsmOperandClass {
850 let Name = "PostIdxReg";
851 let ParserMethod = "parsePostIdxReg";
853 def postidx_reg : Operand<i32> {
854 let EncoderMethod = "getPostIdxRegOpValue";
855 let DecoderMethod = "DecodePostIdxReg";
856 let PrintMethod = "printPostIdxRegOperand";
857 let ParserMatchClass = PostIdxRegAsmOperand;
858 let MIOperandInfo = (ops GPRnopc, i32imm);
862 // addrmode2 := reg +/- imm12
863 // := reg +/- reg shop imm
865 // FIXME: addrmode2 should be refactored the rest of the way to always
866 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
867 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
868 def addrmode2 : Operand<i32>,
869 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
870 let EncoderMethod = "getAddrMode2OpValue";
871 let PrintMethod = "printAddrMode2Operand";
872 let ParserMatchClass = AddrMode2AsmOperand;
873 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
876 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
877 let Name = "PostIdxRegShifted";
878 let ParserMethod = "parsePostIdxReg";
880 def am2offset_reg : Operand<i32>,
881 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
882 [], [SDNPWantRoot]> {
883 let EncoderMethod = "getAddrMode2OffsetOpValue";
884 let PrintMethod = "printAddrMode2OffsetOperand";
885 // When using this for assembly, it's always as a post-index offset.
886 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
887 let MIOperandInfo = (ops GPRnopc, i32imm);
890 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
891 // the GPR is purely vestigal at this point.
892 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
893 def am2offset_imm : Operand<i32>,
894 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
895 [], [SDNPWantRoot]> {
896 let EncoderMethod = "getAddrMode2OffsetOpValue";
897 let PrintMethod = "printAddrMode2OffsetOperand";
898 let ParserMatchClass = AM2OffsetImmAsmOperand;
899 let MIOperandInfo = (ops GPRnopc, i32imm);
903 // addrmode3 := reg +/- reg
904 // addrmode3 := reg +/- imm8
906 // FIXME: split into imm vs. reg versions.
907 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
908 class AddrMode3 : Operand<i32>,
909 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
910 let EncoderMethod = "getAddrMode3OpValue";
911 let ParserMatchClass = AddrMode3AsmOperand;
912 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
915 def addrmode3 : AddrMode3
917 let PrintMethod = "printAddrMode3Operand<false>";
920 def addrmode3_pre : AddrMode3
922 let PrintMethod = "printAddrMode3Operand<true>";
925 // FIXME: split into imm vs. reg versions.
926 // FIXME: parser method to handle +/- register.
927 def AM3OffsetAsmOperand : AsmOperandClass {
928 let Name = "AM3Offset";
929 let ParserMethod = "parseAM3Offset";
931 def am3offset : Operand<i32>,
932 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
933 [], [SDNPWantRoot]> {
934 let EncoderMethod = "getAddrMode3OffsetOpValue";
935 let PrintMethod = "printAddrMode3OffsetOperand";
936 let ParserMatchClass = AM3OffsetAsmOperand;
937 let MIOperandInfo = (ops GPR, i32imm);
940 // ldstm_mode := {ia, ib, da, db}
942 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
943 let EncoderMethod = "getLdStmModeOpValue";
944 let PrintMethod = "printLdStmModeOperand";
947 // addrmode5 := reg +/- imm8*4
949 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
950 class AddrMode5 : Operand<i32>,
951 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
952 let EncoderMethod = "getAddrMode5OpValue";
953 let DecoderMethod = "DecodeAddrMode5Operand";
954 let ParserMatchClass = AddrMode5AsmOperand;
955 let MIOperandInfo = (ops GPR:$base, i32imm);
958 def addrmode5 : AddrMode5 {
959 let PrintMethod = "printAddrMode5Operand<false>";
962 def addrmode5_pre : AddrMode5 {
963 let PrintMethod = "printAddrMode5Operand<true>";
966 // addrmode6 := reg with optional alignment
968 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
969 def addrmode6 : Operand<i32>,
970 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
971 let PrintMethod = "printAddrMode6Operand";
972 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
973 let EncoderMethod = "getAddrMode6AddressOpValue";
974 let DecoderMethod = "DecodeAddrMode6Operand";
975 let ParserMatchClass = AddrMode6AsmOperand;
978 def am6offset : Operand<i32>,
979 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
980 [], [SDNPWantRoot]> {
981 let PrintMethod = "printAddrMode6OffsetOperand";
982 let MIOperandInfo = (ops GPR);
983 let EncoderMethod = "getAddrMode6OffsetOpValue";
984 let DecoderMethod = "DecodeGPRRegisterClass";
987 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
988 // (single element from one lane) for size 32.
989 def addrmode6oneL32 : Operand<i32>,
990 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
991 let PrintMethod = "printAddrMode6Operand";
992 let MIOperandInfo = (ops GPR:$addr, i32imm);
993 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
996 // Base class for addrmode6 with specific alignment restrictions.
997 class AddrMode6Align : Operand<i32>,
998 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
999 let PrintMethod = "printAddrMode6Operand";
1000 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1001 let EncoderMethod = "getAddrMode6AddressOpValue";
1002 let DecoderMethod = "DecodeAddrMode6Operand";
1005 // Special version of addrmode6 to handle no allowed alignment encoding for
1006 // VLD/VST instructions and checking the alignment is not specified.
1007 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1008 let Name = "AlignedMemoryNone";
1009 let DiagnosticType = "AlignedMemoryRequiresNone";
1011 def addrmode6alignNone : AddrMode6Align {
1012 // The alignment specifier can only be omitted.
1013 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1016 // Special version of addrmode6 to handle 16-bit alignment encoding for
1017 // VLD/VST instructions and checking the alignment value.
1018 def AddrMode6Align16AsmOperand : AsmOperandClass {
1019 let Name = "AlignedMemory16";
1020 let DiagnosticType = "AlignedMemoryRequires16";
1022 def addrmode6align16 : AddrMode6Align {
1023 // The alignment specifier can only be 16 or omitted.
1024 let ParserMatchClass = AddrMode6Align16AsmOperand;
1027 // Special version of addrmode6 to handle 32-bit alignment encoding for
1028 // VLD/VST instructions and checking the alignment value.
1029 def AddrMode6Align32AsmOperand : AsmOperandClass {
1030 let Name = "AlignedMemory32";
1031 let DiagnosticType = "AlignedMemoryRequires32";
1033 def addrmode6align32 : AddrMode6Align {
1034 // The alignment specifier can only be 32 or omitted.
1035 let ParserMatchClass = AddrMode6Align32AsmOperand;
1038 // Special version of addrmode6 to handle 64-bit alignment encoding for
1039 // VLD/VST instructions and checking the alignment value.
1040 def AddrMode6Align64AsmOperand : AsmOperandClass {
1041 let Name = "AlignedMemory64";
1042 let DiagnosticType = "AlignedMemoryRequires64";
1044 def addrmode6align64 : AddrMode6Align {
1045 // The alignment specifier can only be 64 or omitted.
1046 let ParserMatchClass = AddrMode6Align64AsmOperand;
1049 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1050 // for VLD/VST instructions and checking the alignment value.
1051 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1052 let Name = "AlignedMemory64or128";
1053 let DiagnosticType = "AlignedMemoryRequires64or128";
1055 def addrmode6align64or128 : AddrMode6Align {
1056 // The alignment specifier can only be 64, 128 or omitted.
1057 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1060 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1061 // encoding for VLD/VST instructions and checking the alignment value.
1062 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1063 let Name = "AlignedMemory64or128or256";
1064 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1066 def addrmode6align64or128or256 : AddrMode6Align {
1067 // The alignment specifier can only be 64, 128, 256 or omitted.
1068 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1071 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1072 // instructions, specifically VLD4-dup.
1073 def addrmode6dup : Operand<i32>,
1074 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1075 let PrintMethod = "printAddrMode6Operand";
1076 let MIOperandInfo = (ops GPR:$addr, i32imm);
1077 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1078 // FIXME: This is close, but not quite right. The alignment specifier is
1080 let ParserMatchClass = AddrMode6AsmOperand;
1083 // Base class for addrmode6dup with specific alignment restrictions.
1084 class AddrMode6DupAlign : Operand<i32>,
1085 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1086 let PrintMethod = "printAddrMode6Operand";
1087 let MIOperandInfo = (ops GPR:$addr, i32imm);
1088 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1091 // Special version of addrmode6 to handle no allowed alignment encoding for
1092 // VLD-dup instruction and checking the alignment is not specified.
1093 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1094 let Name = "DupAlignedMemoryNone";
1095 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1097 def addrmode6dupalignNone : AddrMode6DupAlign {
1098 // The alignment specifier can only be omitted.
1099 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1102 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1103 // instruction and checking the alignment value.
1104 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1105 let Name = "DupAlignedMemory16";
1106 let DiagnosticType = "DupAlignedMemoryRequires16";
1108 def addrmode6dupalign16 : AddrMode6DupAlign {
1109 // The alignment specifier can only be 16 or omitted.
1110 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1113 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1114 // instruction and checking the alignment value.
1115 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1116 let Name = "DupAlignedMemory32";
1117 let DiagnosticType = "DupAlignedMemoryRequires32";
1119 def addrmode6dupalign32 : AddrMode6DupAlign {
1120 // The alignment specifier can only be 32 or omitted.
1121 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1124 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1125 // instructions and checking the alignment value.
1126 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1127 let Name = "DupAlignedMemory64";
1128 let DiagnosticType = "DupAlignedMemoryRequires64";
1130 def addrmode6dupalign64 : AddrMode6DupAlign {
1131 // The alignment specifier can only be 64 or omitted.
1132 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1135 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1136 // for VLD instructions and checking the alignment value.
1137 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1138 let Name = "DupAlignedMemory64or128";
1139 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1141 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1142 // The alignment specifier can only be 64, 128 or omitted.
1143 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1146 // addrmodepc := pc + reg
1148 def addrmodepc : Operand<i32>,
1149 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1150 let PrintMethod = "printAddrModePCOperand";
1151 let MIOperandInfo = (ops GPR, i32imm);
1154 // addr_offset_none := reg
1156 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1157 def addr_offset_none : Operand<i32>,
1158 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1159 let PrintMethod = "printAddrMode7Operand";
1160 let DecoderMethod = "DecodeAddrMode7Operand";
1161 let ParserMatchClass = MemNoOffsetAsmOperand;
1162 let MIOperandInfo = (ops GPR:$base);
1165 def nohash_imm : Operand<i32> {
1166 let PrintMethod = "printNoHashImmediate";
1169 def CoprocNumAsmOperand : AsmOperandClass {
1170 let Name = "CoprocNum";
1171 let ParserMethod = "parseCoprocNumOperand";
1173 def p_imm : Operand<i32> {
1174 let PrintMethod = "printPImmediate";
1175 let ParserMatchClass = CoprocNumAsmOperand;
1176 let DecoderMethod = "DecodeCoprocessor";
1179 def CoprocRegAsmOperand : AsmOperandClass {
1180 let Name = "CoprocReg";
1181 let ParserMethod = "parseCoprocRegOperand";
1183 def c_imm : Operand<i32> {
1184 let PrintMethod = "printCImmediate";
1185 let ParserMatchClass = CoprocRegAsmOperand;
1187 def CoprocOptionAsmOperand : AsmOperandClass {
1188 let Name = "CoprocOption";
1189 let ParserMethod = "parseCoprocOptionOperand";
1191 def coproc_option_imm : Operand<i32> {
1192 let PrintMethod = "printCoprocOptionImm";
1193 let ParserMatchClass = CoprocOptionAsmOperand;
1196 //===----------------------------------------------------------------------===//
1198 include "ARMInstrFormats.td"
1200 //===----------------------------------------------------------------------===//
1201 // Multiclass helpers...
1204 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1205 /// binop that produces a value.
1206 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1207 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1208 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1209 PatFrag opnode, bit Commutable = 0> {
1210 // The register-immediate version is re-materializable. This is useful
1211 // in particular for taking the address of a local.
1212 let isReMaterializable = 1 in {
1213 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1214 iii, opc, "\t$Rd, $Rn, $imm",
1215 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1216 Sched<[WriteALU, ReadALU]> {
1221 let Inst{19-16} = Rn;
1222 let Inst{15-12} = Rd;
1223 let Inst{11-0} = imm;
1226 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1227 iir, opc, "\t$Rd, $Rn, $Rm",
1228 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1229 Sched<[WriteALU, ReadALU, ReadALU]> {
1234 let isCommutable = Commutable;
1235 let Inst{19-16} = Rn;
1236 let Inst{15-12} = Rd;
1237 let Inst{11-4} = 0b00000000;
1241 def rsi : AsI1<opcod, (outs GPR:$Rd),
1242 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1243 iis, opc, "\t$Rd, $Rn, $shift",
1244 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1245 Sched<[WriteALUsi, ReadALU]> {
1250 let Inst{19-16} = Rn;
1251 let Inst{15-12} = Rd;
1252 let Inst{11-5} = shift{11-5};
1254 let Inst{3-0} = shift{3-0};
1257 def rsr : AsI1<opcod, (outs GPR:$Rd),
1258 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1259 iis, opc, "\t$Rd, $Rn, $shift",
1260 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1261 Sched<[WriteALUsr, ReadALUsr]> {
1266 let Inst{19-16} = Rn;
1267 let Inst{15-12} = Rd;
1268 let Inst{11-8} = shift{11-8};
1270 let Inst{6-5} = shift{6-5};
1272 let Inst{3-0} = shift{3-0};
1276 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1277 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1278 /// it is equivalent to the AsI1_bin_irs counterpart.
1279 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1280 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1281 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1282 PatFrag opnode, bit Commutable = 0> {
1283 // The register-immediate version is re-materializable. This is useful
1284 // in particular for taking the address of a local.
1285 let isReMaterializable = 1 in {
1286 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1287 iii, opc, "\t$Rd, $Rn, $imm",
1288 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1289 Sched<[WriteALU, ReadALU]> {
1294 let Inst{19-16} = Rn;
1295 let Inst{15-12} = Rd;
1296 let Inst{11-0} = imm;
1299 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1300 iir, opc, "\t$Rd, $Rn, $Rm",
1301 [/* pattern left blank */]>,
1302 Sched<[WriteALU, ReadALU, ReadALU]> {
1306 let Inst{11-4} = 0b00000000;
1309 let Inst{15-12} = Rd;
1310 let Inst{19-16} = Rn;
1313 def rsi : AsI1<opcod, (outs GPR:$Rd),
1314 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1315 iis, opc, "\t$Rd, $Rn, $shift",
1316 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1317 Sched<[WriteALUsi, ReadALU]> {
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = Rd;
1324 let Inst{11-5} = shift{11-5};
1326 let Inst{3-0} = shift{3-0};
1329 def rsr : AsI1<opcod, (outs GPR:$Rd),
1330 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1331 iis, opc, "\t$Rd, $Rn, $shift",
1332 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1333 Sched<[WriteALUsr, ReadALUsr]> {
1338 let Inst{19-16} = Rn;
1339 let Inst{15-12} = Rd;
1340 let Inst{11-8} = shift{11-8};
1342 let Inst{6-5} = shift{6-5};
1344 let Inst{3-0} = shift{3-0};
1348 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1350 /// These opcodes will be converted to the real non-S opcodes by
1351 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1352 let hasPostISelHook = 1, Defs = [CPSR] in {
1353 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1354 InstrItinClass iis, PatFrag opnode,
1355 bit Commutable = 0> {
1356 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1358 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1359 Sched<[WriteALU, ReadALU]>;
1361 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1363 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1364 Sched<[WriteALU, ReadALU, ReadALU]> {
1365 let isCommutable = Commutable;
1367 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1368 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1370 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1371 so_reg_imm:$shift))]>,
1372 Sched<[WriteALUsi, ReadALU]>;
1374 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1375 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1377 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1378 so_reg_reg:$shift))]>,
1379 Sched<[WriteALUSsr, ReadALUsr]>;
1383 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1384 /// operands are reversed.
1385 let hasPostISelHook = 1, Defs = [CPSR] in {
1386 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1387 InstrItinClass iis, PatFrag opnode,
1388 bit Commutable = 0> {
1389 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1391 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1392 Sched<[WriteALU, ReadALU]>;
1394 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1395 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1397 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1399 Sched<[WriteALUsi, ReadALU]>;
1401 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1402 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1404 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1406 Sched<[WriteALUSsr, ReadALUsr]>;
1410 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1411 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1412 /// a explicit result, only implicitly set CPSR.
1413 let isCompare = 1, Defs = [CPSR] in {
1414 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1415 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1416 PatFrag opnode, bit Commutable = 0> {
1417 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1419 [(opnode GPR:$Rn, so_imm:$imm)]>,
1420 Sched<[WriteCMP, ReadALU]> {
1425 let Inst{19-16} = Rn;
1426 let Inst{15-12} = 0b0000;
1427 let Inst{11-0} = imm;
1429 let Unpredictable{15-12} = 0b1111;
1431 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1433 [(opnode GPR:$Rn, GPR:$Rm)]>,
1434 Sched<[WriteCMP, ReadALU, ReadALU]> {
1437 let isCommutable = Commutable;
1440 let Inst{19-16} = Rn;
1441 let Inst{15-12} = 0b0000;
1442 let Inst{11-4} = 0b00000000;
1445 let Unpredictable{15-12} = 0b1111;
1447 def rsi : AI1<opcod, (outs),
1448 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1449 opc, "\t$Rn, $shift",
1450 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1451 Sched<[WriteCMPsi, ReadALU]> {
1456 let Inst{19-16} = Rn;
1457 let Inst{15-12} = 0b0000;
1458 let Inst{11-5} = shift{11-5};
1460 let Inst{3-0} = shift{3-0};
1462 let Unpredictable{15-12} = 0b1111;
1464 def rsr : AI1<opcod, (outs),
1465 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1466 opc, "\t$Rn, $shift",
1467 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1468 Sched<[WriteCMPsr, ReadALU]> {
1473 let Inst{19-16} = Rn;
1474 let Inst{15-12} = 0b0000;
1475 let Inst{11-8} = shift{11-8};
1477 let Inst{6-5} = shift{6-5};
1479 let Inst{3-0} = shift{3-0};
1481 let Unpredictable{15-12} = 0b1111;
1487 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1488 /// register and one whose operand is a register rotated by 8/16/24.
1489 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1490 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1491 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1492 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1493 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1494 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1498 let Inst{19-16} = 0b1111;
1499 let Inst{15-12} = Rd;
1500 let Inst{11-10} = rot;
1504 class AI_ext_rrot_np<bits<8> opcod, string opc>
1505 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1506 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1507 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1509 let Inst{19-16} = 0b1111;
1510 let Inst{11-10} = rot;
1513 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1514 /// register and one whose operand is a register rotated by 8/16/24.
1515 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1516 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1517 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1518 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1519 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1520 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1525 let Inst{19-16} = Rn;
1526 let Inst{15-12} = Rd;
1527 let Inst{11-10} = rot;
1528 let Inst{9-4} = 0b000111;
1532 class AI_exta_rrot_np<bits<8> opcod, string opc>
1533 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1534 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1535 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1538 let Inst{19-16} = Rn;
1539 let Inst{11-10} = rot;
1542 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1543 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1544 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1545 bit Commutable = 0> {
1546 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1547 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1548 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1549 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1551 Sched<[WriteALU, ReadALU]> {
1556 let Inst{15-12} = Rd;
1557 let Inst{19-16} = Rn;
1558 let Inst{11-0} = imm;
1560 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1561 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1562 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1564 Sched<[WriteALU, ReadALU, ReadALU]> {
1568 let Inst{11-4} = 0b00000000;
1570 let isCommutable = Commutable;
1572 let Inst{15-12} = Rd;
1573 let Inst{19-16} = Rn;
1575 def rsi : AsI1<opcod, (outs GPR:$Rd),
1576 (ins GPR:$Rn, so_reg_imm:$shift),
1577 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1578 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1580 Sched<[WriteALUsi, ReadALU]> {
1585 let Inst{19-16} = Rn;
1586 let Inst{15-12} = Rd;
1587 let Inst{11-5} = shift{11-5};
1589 let Inst{3-0} = shift{3-0};
1591 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1592 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1593 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1594 [(set GPRnopc:$Rd, CPSR,
1595 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1597 Sched<[WriteALUsr, ReadALUsr]> {
1602 let Inst{19-16} = Rn;
1603 let Inst{15-12} = Rd;
1604 let Inst{11-8} = shift{11-8};
1606 let Inst{6-5} = shift{6-5};
1608 let Inst{3-0} = shift{3-0};
1613 /// AI1_rsc_irs - Define instructions and patterns for rsc
1614 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1615 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1616 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1617 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1618 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1619 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1621 Sched<[WriteALU, ReadALU]> {
1626 let Inst{15-12} = Rd;
1627 let Inst{19-16} = Rn;
1628 let Inst{11-0} = imm;
1630 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1631 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1632 [/* pattern left blank */]>,
1633 Sched<[WriteALU, ReadALU, ReadALU]> {
1637 let Inst{11-4} = 0b00000000;
1640 let Inst{15-12} = Rd;
1641 let Inst{19-16} = Rn;
1643 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1644 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1645 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1647 Sched<[WriteALUsi, ReadALU]> {
1652 let Inst{19-16} = Rn;
1653 let Inst{15-12} = Rd;
1654 let Inst{11-5} = shift{11-5};
1656 let Inst{3-0} = shift{3-0};
1658 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1659 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1660 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1662 Sched<[WriteALUsr, ReadALUsr]> {
1667 let Inst{19-16} = Rn;
1668 let Inst{15-12} = Rd;
1669 let Inst{11-8} = shift{11-8};
1671 let Inst{6-5} = shift{6-5};
1673 let Inst{3-0} = shift{3-0};
1678 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1679 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1680 InstrItinClass iir, PatFrag opnode> {
1681 // Note: We use the complex addrmode_imm12 rather than just an input
1682 // GPR and a constrained immediate so that we can use this to match
1683 // frame index references and avoid matching constant pool references.
1684 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1685 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1686 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1689 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1690 let Inst{19-16} = addr{16-13}; // Rn
1691 let Inst{15-12} = Rt;
1692 let Inst{11-0} = addr{11-0}; // imm12
1694 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1695 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1696 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1699 let shift{4} = 0; // Inst{4} = 0
1700 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1701 let Inst{19-16} = shift{16-13}; // Rn
1702 let Inst{15-12} = Rt;
1703 let Inst{11-0} = shift{11-0};
1708 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1709 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1710 InstrItinClass iir, PatFrag opnode> {
1711 // Note: We use the complex addrmode_imm12 rather than just an input
1712 // GPR and a constrained immediate so that we can use this to match
1713 // frame index references and avoid matching constant pool references.
1714 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1715 (ins addrmode_imm12:$addr),
1716 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1717 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1720 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1721 let Inst{19-16} = addr{16-13}; // Rn
1722 let Inst{15-12} = Rt;
1723 let Inst{11-0} = addr{11-0}; // imm12
1725 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1726 (ins ldst_so_reg:$shift),
1727 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1728 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1731 let shift{4} = 0; // Inst{4} = 0
1732 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1733 let Inst{19-16} = shift{16-13}; // Rn
1734 let Inst{15-12} = Rt;
1735 let Inst{11-0} = shift{11-0};
1741 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1742 InstrItinClass iir, PatFrag opnode> {
1743 // Note: We use the complex addrmode_imm12 rather than just an input
1744 // GPR and a constrained immediate so that we can use this to match
1745 // frame index references and avoid matching constant pool references.
1746 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1747 (ins GPR:$Rt, addrmode_imm12:$addr),
1748 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1749 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1752 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1753 let Inst{19-16} = addr{16-13}; // Rn
1754 let Inst{15-12} = Rt;
1755 let Inst{11-0} = addr{11-0}; // imm12
1757 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1758 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1759 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1762 let shift{4} = 0; // Inst{4} = 0
1763 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1764 let Inst{19-16} = shift{16-13}; // Rn
1765 let Inst{15-12} = Rt;
1766 let Inst{11-0} = shift{11-0};
1770 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1771 InstrItinClass iir, PatFrag opnode> {
1772 // Note: We use the complex addrmode_imm12 rather than just an input
1773 // GPR and a constrained immediate so that we can use this to match
1774 // frame index references and avoid matching constant pool references.
1775 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1776 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1777 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1778 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1781 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1782 let Inst{19-16} = addr{16-13}; // Rn
1783 let Inst{15-12} = Rt;
1784 let Inst{11-0} = addr{11-0}; // imm12
1786 def rs : AI2ldst<0b011, 0, isByte, (outs),
1787 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1788 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1789 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1792 let shift{4} = 0; // Inst{4} = 0
1793 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1794 let Inst{19-16} = shift{16-13}; // Rn
1795 let Inst{15-12} = Rt;
1796 let Inst{11-0} = shift{11-0};
1801 //===----------------------------------------------------------------------===//
1803 //===----------------------------------------------------------------------===//
1805 //===----------------------------------------------------------------------===//
1806 // Miscellaneous Instructions.
1809 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1810 /// the function. The first operand is the ID# for this instruction, the second
1811 /// is the index into the MachineConstantPool that this is, the third is the
1812 /// size in bytes of this constant pool entry.
1813 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1814 def CONSTPOOL_ENTRY :
1815 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1816 i32imm:$size), NoItinerary, []>;
1818 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1819 // from removing one half of the matched pairs. That breaks PEI, which assumes
1820 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1821 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1822 def ADJCALLSTACKUP :
1823 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1824 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1826 def ADJCALLSTACKDOWN :
1827 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1828 [(ARMcallseq_start timm:$amt)]>;
1831 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1832 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1833 Requires<[IsARM, HasV6]> {
1835 let Inst{27-8} = 0b00110010000011110000;
1836 let Inst{7-0} = imm;
1839 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1840 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1841 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1842 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1843 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1844 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1846 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1847 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1852 let Inst{15-12} = Rd;
1853 let Inst{19-16} = Rn;
1854 let Inst{27-20} = 0b01101000;
1855 let Inst{7-4} = 0b1011;
1856 let Inst{11-8} = 0b1111;
1857 let Unpredictable{11-8} = 0b1111;
1860 // The 16-bit operand $val can be used by a debugger to store more information
1861 // about the breakpoint.
1862 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1863 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1865 let Inst{3-0} = val{3-0};
1866 let Inst{19-8} = val{15-4};
1867 let Inst{27-20} = 0b00010010;
1868 let Inst{31-28} = 0xe; // AL
1869 let Inst{7-4} = 0b0111;
1871 // default immediate for breakpoint mnemonic
1872 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1874 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1875 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1877 let Inst{3-0} = val{3-0};
1878 let Inst{19-8} = val{15-4};
1879 let Inst{27-20} = 0b00010000;
1880 let Inst{31-28} = 0xe; // AL
1881 let Inst{7-4} = 0b0111;
1884 // Change Processor State
1885 // FIXME: We should use InstAlias to handle the optional operands.
1886 class CPS<dag iops, string asm_ops>
1887 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1888 []>, Requires<[IsARM]> {
1894 let Inst{31-28} = 0b1111;
1895 let Inst{27-20} = 0b00010000;
1896 let Inst{19-18} = imod;
1897 let Inst{17} = M; // Enabled if mode is set;
1898 let Inst{16-9} = 0b00000000;
1899 let Inst{8-6} = iflags;
1901 let Inst{4-0} = mode;
1904 let DecoderMethod = "DecodeCPSInstruction" in {
1906 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1907 "$imod\t$iflags, $mode">;
1908 let mode = 0, M = 0 in
1909 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1911 let imod = 0, iflags = 0, M = 1 in
1912 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1915 // Preload signals the memory system of possible future data/instruction access.
1916 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1918 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1919 IIC_Preload, !strconcat(opc, "\t$addr"),
1920 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1921 Sched<[WritePreLd]> {
1924 let Inst{31-26} = 0b111101;
1925 let Inst{25} = 0; // 0 for immediate form
1926 let Inst{24} = data;
1927 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1928 let Inst{22} = read;
1929 let Inst{21-20} = 0b01;
1930 let Inst{19-16} = addr{16-13}; // Rn
1931 let Inst{15-12} = 0b1111;
1932 let Inst{11-0} = addr{11-0}; // imm12
1935 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1936 !strconcat(opc, "\t$shift"),
1937 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1938 Sched<[WritePreLd]> {
1940 let Inst{31-26} = 0b111101;
1941 let Inst{25} = 1; // 1 for register form
1942 let Inst{24} = data;
1943 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1944 let Inst{22} = read;
1945 let Inst{21-20} = 0b01;
1946 let Inst{19-16} = shift{16-13}; // Rn
1947 let Inst{15-12} = 0b1111;
1948 let Inst{11-0} = shift{11-0};
1953 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1954 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1955 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1957 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1958 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1960 let Inst{31-10} = 0b1111000100000001000000;
1965 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1966 []>, Requires<[IsARM, HasV7]> {
1968 let Inst{27-4} = 0b001100100000111100001111;
1969 let Inst{3-0} = opt;
1972 // A8.8.247 UDF - Undefined (Encoding A1)
1973 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1974 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1976 let Inst{31-28} = 0b1110; // AL
1977 let Inst{27-25} = 0b011;
1978 let Inst{24-20} = 0b11111;
1979 let Inst{19-8} = imm16{15-4};
1980 let Inst{7-4} = 0b1111;
1981 let Inst{3-0} = imm16{3-0};
1985 * A5.4 Permanently UNDEFINED instructions.
1987 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1988 * Other UDF encodings generate SIGILL.
1990 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1992 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1994 * 1101 1110 iiii iiii
1995 * It uses the following encoding:
1996 * 1110 0111 1111 1110 1101 1110 1111 0000
1997 * - In ARM: UDF #60896;
1998 * - In Thumb: UDF #254 followed by a branch-to-self.
2000 let isBarrier = 1, isTerminator = 1 in
2001 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2003 Requires<[IsARM,UseNaClTrap]> {
2004 let Inst = 0xe7fedef0;
2006 let isBarrier = 1, isTerminator = 1 in
2007 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2009 Requires<[IsARM,DontUseNaClTrap]> {
2010 let Inst = 0xe7ffdefe;
2013 // Address computation and loads and stores in PIC mode.
2014 let isNotDuplicable = 1 in {
2015 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2017 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2018 Sched<[WriteALU, ReadALU]>;
2020 let AddedComplexity = 10 in {
2021 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2023 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2025 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2027 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2029 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2031 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2033 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2035 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2037 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2039 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2041 let AddedComplexity = 10 in {
2042 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2043 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2045 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2046 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2047 addrmodepc:$addr)]>;
2049 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2050 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2052 } // isNotDuplicable = 1
2055 // LEApcrel - Load a pc-relative address into a register without offending the
2057 let neverHasSideEffects = 1, isReMaterializable = 1 in
2058 // The 'adr' mnemonic encodes differently if the label is before or after
2059 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2060 // know until then which form of the instruction will be used.
2061 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2062 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2063 Sched<[WriteALU, ReadALU]> {
2066 let Inst{27-25} = 0b001;
2068 let Inst{23-22} = label{13-12};
2071 let Inst{19-16} = 0b1111;
2072 let Inst{15-12} = Rd;
2073 let Inst{11-0} = label{11-0};
2076 let hasSideEffects = 1 in {
2077 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2078 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2080 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2081 (ins i32imm:$label, nohash_imm:$id, pred:$p),
2082 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2085 //===----------------------------------------------------------------------===//
2086 // Control Flow Instructions.
2089 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2091 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2092 "bx", "\tlr", [(ARMretflag)]>,
2093 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2094 let Inst{27-0} = 0b0001001011111111111100011110;
2098 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2099 "mov", "\tpc, lr", [(ARMretflag)]>,
2100 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2101 let Inst{27-0} = 0b0001101000001111000000001110;
2104 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2105 // the user-space one).
2106 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2108 [(ARMintretflag imm:$offset)]>;
2111 // Indirect branches
2112 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2114 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2115 [(brind GPR:$dst)]>,
2116 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2118 let Inst{31-4} = 0b1110000100101111111111110001;
2119 let Inst{3-0} = dst;
2122 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2123 "bx", "\t$dst", [/* pattern left blank */]>,
2124 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2126 let Inst{27-4} = 0b000100101111111111110001;
2127 let Inst{3-0} = dst;
2131 // SP is marked as a use to prevent stack-pointer assignments that appear
2132 // immediately before calls from potentially appearing dead.
2134 // FIXME: Do we really need a non-predicated version? If so, it should
2135 // at least be a pseudo instruction expanding to the predicated version
2136 // at MC lowering time.
2137 Defs = [LR], Uses = [SP] in {
2138 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2139 IIC_Br, "bl\t$func",
2140 [(ARMcall tglobaladdr:$func)]>,
2141 Requires<[IsARM]>, Sched<[WriteBrL]> {
2142 let Inst{31-28} = 0b1110;
2144 let Inst{23-0} = func;
2145 let DecoderMethod = "DecodeBranchImmInstruction";
2148 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2149 IIC_Br, "bl", "\t$func",
2150 [(ARMcall_pred tglobaladdr:$func)]>,
2151 Requires<[IsARM]>, Sched<[WriteBrL]> {
2153 let Inst{23-0} = func;
2154 let DecoderMethod = "DecodeBranchImmInstruction";
2158 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2159 IIC_Br, "blx\t$func",
2160 [(ARMcall GPR:$func)]>,
2161 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2163 let Inst{31-4} = 0b1110000100101111111111110011;
2164 let Inst{3-0} = func;
2167 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2168 IIC_Br, "blx", "\t$func",
2169 [(ARMcall_pred GPR:$func)]>,
2170 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2172 let Inst{27-4} = 0b000100101111111111110011;
2173 let Inst{3-0} = func;
2177 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2178 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2179 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2180 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2183 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2184 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2185 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2187 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2188 // return stack predictor.
2189 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2190 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2191 Requires<[IsARM]>, Sched<[WriteBr]>;
2194 let isBranch = 1, isTerminator = 1 in {
2195 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2196 // a two-value operand where a dag node expects two operands. :(
2197 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2198 IIC_Br, "b", "\t$target",
2199 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2202 let Inst{23-0} = target;
2203 let DecoderMethod = "DecodeBranchImmInstruction";
2206 let isBarrier = 1 in {
2207 // B is "predicable" since it's just a Bcc with an 'always' condition.
2208 let isPredicable = 1 in
2209 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2210 // should be sufficient.
2211 // FIXME: Is B really a Barrier? That doesn't seem right.
2212 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2213 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2216 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2217 def BR_JTr : ARMPseudoInst<(outs),
2218 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2220 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2222 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2223 // into i12 and rs suffixed versions.
2224 def BR_JTm : ARMPseudoInst<(outs),
2225 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2227 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2228 imm:$id)]>, Sched<[WriteBrTbl]>;
2229 def BR_JTadd : ARMPseudoInst<(outs),
2230 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2232 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2233 imm:$id)]>, Sched<[WriteBrTbl]>;
2234 } // isNotDuplicable = 1, isIndirectBranch = 1
2240 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2241 "blx\t$target", []>,
2242 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2243 let Inst{31-25} = 0b1111101;
2245 let Inst{23-0} = target{24-1};
2246 let Inst{24} = target{0};
2249 // Branch and Exchange Jazelle
2250 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2251 [/* pattern left blank */]>, Sched<[WriteBr]> {
2253 let Inst{23-20} = 0b0010;
2254 let Inst{19-8} = 0xfff;
2255 let Inst{7-4} = 0b0010;
2256 let Inst{3-0} = func;
2261 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2262 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2265 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2268 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2270 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2271 Requires<[IsARM]>, Sched<[WriteBr]>;
2273 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2275 (BX GPR:$dst)>, Sched<[WriteBr]>,
2279 // Secure Monitor Call is a system instruction.
2280 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2281 []>, Requires<[IsARM, HasTrustZone]> {
2283 let Inst{23-4} = 0b01100000000000000111;
2284 let Inst{3-0} = opt;
2287 // Supervisor Call (Software Interrupt)
2288 let isCall = 1, Uses = [SP] in {
2289 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2292 let Inst{23-0} = svc;
2296 // Store Return State
2297 class SRSI<bit wb, string asm>
2298 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2299 NoItinerary, asm, "", []> {
2301 let Inst{31-28} = 0b1111;
2302 let Inst{27-25} = 0b100;
2306 let Inst{19-16} = 0b1101; // SP
2307 let Inst{15-5} = 0b00000101000;
2308 let Inst{4-0} = mode;
2311 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2312 let Inst{24-23} = 0;
2314 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2315 let Inst{24-23} = 0;
2317 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2318 let Inst{24-23} = 0b10;
2320 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2321 let Inst{24-23} = 0b10;
2323 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2324 let Inst{24-23} = 0b01;
2326 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2327 let Inst{24-23} = 0b01;
2329 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2330 let Inst{24-23} = 0b11;
2332 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2333 let Inst{24-23} = 0b11;
2336 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2337 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2339 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2340 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2342 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2343 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2345 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2346 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2348 // Return From Exception
2349 class RFEI<bit wb, string asm>
2350 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2351 NoItinerary, asm, "", []> {
2353 let Inst{31-28} = 0b1111;
2354 let Inst{27-25} = 0b100;
2358 let Inst{19-16} = Rn;
2359 let Inst{15-0} = 0xa00;
2362 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2363 let Inst{24-23} = 0;
2365 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2366 let Inst{24-23} = 0;
2368 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2369 let Inst{24-23} = 0b10;
2371 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2372 let Inst{24-23} = 0b10;
2374 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2375 let Inst{24-23} = 0b01;
2377 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2378 let Inst{24-23} = 0b01;
2380 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2381 let Inst{24-23} = 0b11;
2383 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2384 let Inst{24-23} = 0b11;
2387 //===----------------------------------------------------------------------===//
2388 // Load / Store Instructions.
2394 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2395 UnOpFrag<(load node:$Src)>>;
2396 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2397 UnOpFrag<(zextloadi8 node:$Src)>>;
2398 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2399 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2400 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2401 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2403 // Special LDR for loads from non-pc-relative constpools.
2404 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2405 isReMaterializable = 1, isCodeGenOnly = 1 in
2406 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2407 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2411 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2412 let Inst{19-16} = 0b1111;
2413 let Inst{15-12} = Rt;
2414 let Inst{11-0} = addr{11-0}; // imm12
2417 // Loads with zero extension
2418 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2419 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2420 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2422 // Loads with sign extension
2423 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2424 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2425 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2427 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2428 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2429 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2431 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2433 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2434 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2435 Requires<[IsARM, HasV5TE]>;
2438 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2439 NoItinerary, "lda", "\t$Rt, $addr", []>;
2440 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2441 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2442 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2443 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2446 multiclass AI2_ldridx<bit isByte, string opc,
2447 InstrItinClass iii, InstrItinClass iir> {
2448 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2449 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2450 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2453 let Inst{23} = addr{12};
2454 let Inst{19-16} = addr{16-13};
2455 let Inst{11-0} = addr{11-0};
2456 let DecoderMethod = "DecodeLDRPreImm";
2459 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2460 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2461 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2464 let Inst{23} = addr{12};
2465 let Inst{19-16} = addr{16-13};
2466 let Inst{11-0} = addr{11-0};
2468 let DecoderMethod = "DecodeLDRPreReg";
2471 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2472 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2473 IndexModePost, LdFrm, iir,
2474 opc, "\t$Rt, $addr, $offset",
2475 "$addr.base = $Rn_wb", []> {
2481 let Inst{23} = offset{12};
2482 let Inst{19-16} = addr;
2483 let Inst{11-0} = offset{11-0};
2486 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2489 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2490 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2491 IndexModePost, LdFrm, iii,
2492 opc, "\t$Rt, $addr, $offset",
2493 "$addr.base = $Rn_wb", []> {
2499 let Inst{23} = offset{12};
2500 let Inst{19-16} = addr;
2501 let Inst{11-0} = offset{11-0};
2503 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2508 let mayLoad = 1, neverHasSideEffects = 1 in {
2509 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2510 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2511 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2512 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2515 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2516 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2517 (ins addrmode3_pre:$addr), IndexModePre,
2519 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2521 let Inst{23} = addr{8}; // U bit
2522 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2523 let Inst{19-16} = addr{12-9}; // Rn
2524 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2525 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2526 let DecoderMethod = "DecodeAddrMode3Instruction";
2528 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2529 (ins addr_offset_none:$addr, am3offset:$offset),
2530 IndexModePost, LdMiscFrm, itin,
2531 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2535 let Inst{23} = offset{8}; // U bit
2536 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2537 let Inst{19-16} = addr;
2538 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2539 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2540 let DecoderMethod = "DecodeAddrMode3Instruction";
2544 let mayLoad = 1, neverHasSideEffects = 1 in {
2545 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2546 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2547 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2548 let hasExtraDefRegAllocReq = 1 in {
2549 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2550 (ins addrmode3_pre:$addr), IndexModePre,
2551 LdMiscFrm, IIC_iLoad_d_ru,
2552 "ldrd", "\t$Rt, $Rt2, $addr!",
2553 "$addr.base = $Rn_wb", []> {
2555 let Inst{23} = addr{8}; // U bit
2556 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2557 let Inst{19-16} = addr{12-9}; // Rn
2558 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2559 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2560 let DecoderMethod = "DecodeAddrMode3Instruction";
2562 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2563 (ins addr_offset_none:$addr, am3offset:$offset),
2564 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2565 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2566 "$addr.base = $Rn_wb", []> {
2569 let Inst{23} = offset{8}; // U bit
2570 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2571 let Inst{19-16} = addr;
2572 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2573 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2574 let DecoderMethod = "DecodeAddrMode3Instruction";
2576 } // hasExtraDefRegAllocReq = 1
2577 } // mayLoad = 1, neverHasSideEffects = 1
2579 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2580 let mayLoad = 1, neverHasSideEffects = 1 in {
2581 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2582 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2583 IndexModePost, LdFrm, IIC_iLoad_ru,
2584 "ldrt", "\t$Rt, $addr, $offset",
2585 "$addr.base = $Rn_wb", []> {
2591 let Inst{23} = offset{12};
2592 let Inst{21} = 1; // overwrite
2593 let Inst{19-16} = addr;
2594 let Inst{11-5} = offset{11-5};
2596 let Inst{3-0} = offset{3-0};
2597 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2601 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2602 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2603 IndexModePost, LdFrm, IIC_iLoad_ru,
2604 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2610 let Inst{23} = offset{12};
2611 let Inst{21} = 1; // overwrite
2612 let Inst{19-16} = addr;
2613 let Inst{11-0} = offset{11-0};
2614 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2617 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2618 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2619 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2620 "ldrbt", "\t$Rt, $addr, $offset",
2621 "$addr.base = $Rn_wb", []> {
2627 let Inst{23} = offset{12};
2628 let Inst{21} = 1; // overwrite
2629 let Inst{19-16} = addr;
2630 let Inst{11-5} = offset{11-5};
2632 let Inst{3-0} = offset{3-0};
2633 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2637 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2638 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2639 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2640 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2646 let Inst{23} = offset{12};
2647 let Inst{21} = 1; // overwrite
2648 let Inst{19-16} = addr;
2649 let Inst{11-0} = offset{11-0};
2650 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2653 multiclass AI3ldrT<bits<4> op, string opc> {
2654 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2655 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2656 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2657 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2659 let Inst{23} = offset{8};
2661 let Inst{11-8} = offset{7-4};
2662 let Inst{3-0} = offset{3-0};
2664 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2665 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2666 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2667 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2669 let Inst{23} = Rm{4};
2672 let Unpredictable{11-8} = 0b1111;
2673 let Inst{3-0} = Rm{3-0};
2674 let DecoderMethod = "DecodeLDR";
2678 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2679 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2680 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2684 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2688 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2693 // Stores with truncate
2694 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2695 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2696 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2699 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2700 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2701 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2702 Requires<[IsARM, HasV5TE]> {
2708 multiclass AI2_stridx<bit isByte, string opc,
2709 InstrItinClass iii, InstrItinClass iir> {
2710 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2711 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2713 opc, "\t$Rt, $addr!",
2714 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2717 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2718 let Inst{19-16} = addr{16-13}; // Rn
2719 let Inst{11-0} = addr{11-0}; // imm12
2720 let DecoderMethod = "DecodeSTRPreImm";
2723 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2724 (ins GPR:$Rt, ldst_so_reg:$addr),
2725 IndexModePre, StFrm, iir,
2726 opc, "\t$Rt, $addr!",
2727 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2730 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2731 let Inst{19-16} = addr{16-13}; // Rn
2732 let Inst{11-0} = addr{11-0};
2733 let Inst{4} = 0; // Inst{4} = 0
2734 let DecoderMethod = "DecodeSTRPreReg";
2736 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2737 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2738 IndexModePost, StFrm, iir,
2739 opc, "\t$Rt, $addr, $offset",
2740 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2746 let Inst{23} = offset{12};
2747 let Inst{19-16} = addr;
2748 let Inst{11-0} = offset{11-0};
2751 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2754 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2755 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2756 IndexModePost, StFrm, iii,
2757 opc, "\t$Rt, $addr, $offset",
2758 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2764 let Inst{23} = offset{12};
2765 let Inst{19-16} = addr;
2766 let Inst{11-0} = offset{11-0};
2768 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2772 let mayStore = 1, neverHasSideEffects = 1 in {
2773 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2774 // IIC_iStore_siu depending on whether it the offset register is shifted.
2775 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2776 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2779 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2780 am2offset_reg:$offset),
2781 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2782 am2offset_reg:$offset)>;
2783 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2784 am2offset_imm:$offset),
2785 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2786 am2offset_imm:$offset)>;
2787 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2788 am2offset_reg:$offset),
2789 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2790 am2offset_reg:$offset)>;
2791 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2792 am2offset_imm:$offset),
2793 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2794 am2offset_imm:$offset)>;
2796 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2797 // put the patterns on the instruction definitions directly as ISel wants
2798 // the address base and offset to be separate operands, not a single
2799 // complex operand like we represent the instructions themselves. The
2800 // pseudos map between the two.
2801 let usesCustomInserter = 1,
2802 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2803 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2804 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2807 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2808 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2809 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2812 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2813 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2814 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2817 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2818 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2819 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2822 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2823 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2824 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2827 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2832 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2833 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2834 StMiscFrm, IIC_iStore_bh_ru,
2835 "strh", "\t$Rt, $addr!",
2836 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2838 let Inst{23} = addr{8}; // U bit
2839 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2840 let Inst{19-16} = addr{12-9}; // Rn
2841 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2842 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2843 let DecoderMethod = "DecodeAddrMode3Instruction";
2846 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2847 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2848 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2849 "strh", "\t$Rt, $addr, $offset",
2850 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2851 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2852 addr_offset_none:$addr,
2853 am3offset:$offset))]> {
2856 let Inst{23} = offset{8}; // U bit
2857 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2858 let Inst{19-16} = addr;
2859 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2860 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2861 let DecoderMethod = "DecodeAddrMode3Instruction";
2864 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2865 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2866 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2867 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2868 "strd", "\t$Rt, $Rt2, $addr!",
2869 "$addr.base = $Rn_wb", []> {
2871 let Inst{23} = addr{8}; // U bit
2872 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2873 let Inst{19-16} = addr{12-9}; // Rn
2874 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2875 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2876 let DecoderMethod = "DecodeAddrMode3Instruction";
2879 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2880 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2882 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2883 "strd", "\t$Rt, $Rt2, $addr, $offset",
2884 "$addr.base = $Rn_wb", []> {
2887 let Inst{23} = offset{8}; // U bit
2888 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2889 let Inst{19-16} = addr;
2890 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2891 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2892 let DecoderMethod = "DecodeAddrMode3Instruction";
2894 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2896 // STRT, STRBT, and STRHT
2898 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2899 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2900 IndexModePost, StFrm, IIC_iStore_bh_ru,
2901 "strbt", "\t$Rt, $addr, $offset",
2902 "$addr.base = $Rn_wb", []> {
2908 let Inst{23} = offset{12};
2909 let Inst{21} = 1; // overwrite
2910 let Inst{19-16} = addr;
2911 let Inst{11-5} = offset{11-5};
2913 let Inst{3-0} = offset{3-0};
2914 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2918 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2919 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2920 IndexModePost, StFrm, IIC_iStore_bh_ru,
2921 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2927 let Inst{23} = offset{12};
2928 let Inst{21} = 1; // overwrite
2929 let Inst{19-16} = addr;
2930 let Inst{11-0} = offset{11-0};
2931 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2935 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2936 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2938 let mayStore = 1, neverHasSideEffects = 1 in {
2939 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2940 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2941 IndexModePost, StFrm, IIC_iStore_ru,
2942 "strt", "\t$Rt, $addr, $offset",
2943 "$addr.base = $Rn_wb", []> {
2949 let Inst{23} = offset{12};
2950 let Inst{21} = 1; // overwrite
2951 let Inst{19-16} = addr;
2952 let Inst{11-5} = offset{11-5};
2954 let Inst{3-0} = offset{3-0};
2955 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2959 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2960 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2961 IndexModePost, StFrm, IIC_iStore_ru,
2962 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2968 let Inst{23} = offset{12};
2969 let Inst{21} = 1; // overwrite
2970 let Inst{19-16} = addr;
2971 let Inst{11-0} = offset{11-0};
2972 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2977 : ARMAsmPseudo<"strt${q} $Rt, $addr",
2978 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2980 multiclass AI3strT<bits<4> op, string opc> {
2981 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2982 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2983 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2984 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2986 let Inst{23} = offset{8};
2988 let Inst{11-8} = offset{7-4};
2989 let Inst{3-0} = offset{3-0};
2991 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2992 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2993 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2994 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2996 let Inst{23} = Rm{4};
2999 let Inst{3-0} = Rm{3-0};
3004 defm STRHT : AI3strT<0b1011, "strht">;
3006 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3007 NoItinerary, "stl", "\t$Rt, $addr", []>;
3008 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3009 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3010 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3011 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3013 //===----------------------------------------------------------------------===//
3014 // Load / store multiple Instructions.
3017 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3018 InstrItinClass itin, InstrItinClass itin_upd> {
3019 // IA is the default, so no need for an explicit suffix on the
3020 // mnemonic here. Without it is the canonical spelling.
3022 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3023 IndexModeNone, f, itin,
3024 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3025 let Inst{24-23} = 0b01; // Increment After
3026 let Inst{22} = P_bit;
3027 let Inst{21} = 0; // No writeback
3028 let Inst{20} = L_bit;
3031 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3032 IndexModeUpd, f, itin_upd,
3033 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3034 let Inst{24-23} = 0b01; // Increment After
3035 let Inst{22} = P_bit;
3036 let Inst{21} = 1; // Writeback
3037 let Inst{20} = L_bit;
3039 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3042 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3043 IndexModeNone, f, itin,
3044 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3045 let Inst{24-23} = 0b00; // Decrement After
3046 let Inst{22} = P_bit;
3047 let Inst{21} = 0; // No writeback
3048 let Inst{20} = L_bit;
3051 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3052 IndexModeUpd, f, itin_upd,
3053 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3054 let Inst{24-23} = 0b00; // Decrement After
3055 let Inst{22} = P_bit;
3056 let Inst{21} = 1; // Writeback
3057 let Inst{20} = L_bit;
3059 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3062 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3063 IndexModeNone, f, itin,
3064 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3065 let Inst{24-23} = 0b10; // Decrement Before
3066 let Inst{22} = P_bit;
3067 let Inst{21} = 0; // No writeback
3068 let Inst{20} = L_bit;
3071 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3072 IndexModeUpd, f, itin_upd,
3073 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3074 let Inst{24-23} = 0b10; // Decrement Before
3075 let Inst{22} = P_bit;
3076 let Inst{21} = 1; // Writeback
3077 let Inst{20} = L_bit;
3079 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3082 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3083 IndexModeNone, f, itin,
3084 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3085 let Inst{24-23} = 0b11; // Increment Before
3086 let Inst{22} = P_bit;
3087 let Inst{21} = 0; // No writeback
3088 let Inst{20} = L_bit;
3091 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3092 IndexModeUpd, f, itin_upd,
3093 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3094 let Inst{24-23} = 0b11; // Increment Before
3095 let Inst{22} = P_bit;
3096 let Inst{21} = 1; // Writeback
3097 let Inst{20} = L_bit;
3099 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3103 let neverHasSideEffects = 1 in {
3105 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3106 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3109 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3110 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3113 } // neverHasSideEffects
3115 // FIXME: remove when we have a way to marking a MI with these properties.
3116 // FIXME: Should pc be an implicit operand like PICADD, etc?
3117 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3118 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3119 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3120 reglist:$regs, variable_ops),
3121 4, IIC_iLoad_mBr, [],
3122 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3123 RegConstraint<"$Rn = $wb">;
3125 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3126 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3129 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3130 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3135 //===----------------------------------------------------------------------===//
3136 // Move Instructions.
3139 let neverHasSideEffects = 1 in
3140 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3141 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3145 let Inst{19-16} = 0b0000;
3146 let Inst{11-4} = 0b00000000;
3149 let Inst{15-12} = Rd;
3152 // A version for the smaller set of tail call registers.
3153 let neverHasSideEffects = 1 in
3154 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3155 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3159 let Inst{11-4} = 0b00000000;
3162 let Inst{15-12} = Rd;
3165 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3166 DPSoRegRegFrm, IIC_iMOVsr,
3167 "mov", "\t$Rd, $src",
3168 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3172 let Inst{15-12} = Rd;
3173 let Inst{19-16} = 0b0000;
3174 let Inst{11-8} = src{11-8};
3176 let Inst{6-5} = src{6-5};
3178 let Inst{3-0} = src{3-0};
3182 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3183 DPSoRegImmFrm, IIC_iMOVsr,
3184 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3185 UnaryDP, Sched<[WriteALU]> {
3188 let Inst{15-12} = Rd;
3189 let Inst{19-16} = 0b0000;
3190 let Inst{11-5} = src{11-5};
3192 let Inst{3-0} = src{3-0};
3196 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3197 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3198 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3203 let Inst{15-12} = Rd;
3204 let Inst{19-16} = 0b0000;
3205 let Inst{11-0} = imm;
3208 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3209 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3211 "movw", "\t$Rd, $imm",
3212 [(set GPR:$Rd, imm0_65535:$imm)]>,
3213 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3216 let Inst{15-12} = Rd;
3217 let Inst{11-0} = imm{11-0};
3218 let Inst{19-16} = imm{15-12};
3221 let DecoderMethod = "DecodeArmMOVTWInstruction";
3224 def : InstAlias<"mov${p} $Rd, $imm",
3225 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3228 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3229 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3232 let Constraints = "$src = $Rd" in {
3233 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3234 (ins GPR:$src, imm0_65535_expr:$imm),
3236 "movt", "\t$Rd, $imm",
3238 (or (and GPR:$src, 0xffff),
3239 lo16AllZero:$imm))]>, UnaryDP,
3240 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3243 let Inst{15-12} = Rd;
3244 let Inst{11-0} = imm{11-0};
3245 let Inst{19-16} = imm{15-12};
3248 let DecoderMethod = "DecodeArmMOVTWInstruction";
3251 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3252 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3257 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3258 Requires<[IsARM, HasV6T2]>;
3260 let Uses = [CPSR] in
3261 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3262 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3263 Requires<[IsARM]>, Sched<[WriteALU]>;
3265 // These aren't really mov instructions, but we have to define them this way
3266 // due to flag operands.
3268 let Defs = [CPSR] in {
3269 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3270 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3271 Sched<[WriteALU]>, Requires<[IsARM]>;
3272 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3273 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3274 Sched<[WriteALU]>, Requires<[IsARM]>;
3277 //===----------------------------------------------------------------------===//
3278 // Extend Instructions.
3283 def SXTB : AI_ext_rrot<0b01101010,
3284 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3285 def SXTH : AI_ext_rrot<0b01101011,
3286 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3288 def SXTAB : AI_exta_rrot<0b01101010,
3289 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3290 def SXTAH : AI_exta_rrot<0b01101011,
3291 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3293 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3295 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3299 let AddedComplexity = 16 in {
3300 def UXTB : AI_ext_rrot<0b01101110,
3301 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3302 def UXTH : AI_ext_rrot<0b01101111,
3303 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3304 def UXTB16 : AI_ext_rrot<0b01101100,
3305 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3307 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3308 // The transformation should probably be done as a combiner action
3309 // instead so we can include a check for masking back in the upper
3310 // eight bits of the source into the lower eight bits of the result.
3311 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3312 // (UXTB16r_rot GPR:$Src, 3)>;
3313 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3314 (UXTB16 GPR:$Src, 1)>;
3316 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3317 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3318 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3319 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3322 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3323 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3326 def SBFX : I<(outs GPRnopc:$Rd),
3327 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3328 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3329 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3330 Requires<[IsARM, HasV6T2]> {
3335 let Inst{27-21} = 0b0111101;
3336 let Inst{6-4} = 0b101;
3337 let Inst{20-16} = width;
3338 let Inst{15-12} = Rd;
3339 let Inst{11-7} = lsb;
3343 def UBFX : I<(outs GPRnopc:$Rd),
3344 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3345 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3346 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3347 Requires<[IsARM, HasV6T2]> {
3352 let Inst{27-21} = 0b0111111;
3353 let Inst{6-4} = 0b101;
3354 let Inst{20-16} = width;
3355 let Inst{15-12} = Rd;
3356 let Inst{11-7} = lsb;
3360 //===----------------------------------------------------------------------===//
3361 // Arithmetic Instructions.
3364 defm ADD : AsI1_bin_irs<0b0100, "add",
3365 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3366 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3367 defm SUB : AsI1_bin_irs<0b0010, "sub",
3368 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3369 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3371 // ADD and SUB with 's' bit set.
3373 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3374 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3375 // AdjustInstrPostInstrSelection where we determine whether or not to
3376 // set the "s" bit based on CPSR liveness.
3378 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3379 // support for an optional CPSR definition that corresponds to the DAG
3380 // node's second value. We can then eliminate the implicit def of CPSR.
3381 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3382 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3383 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3384 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3386 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3387 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3388 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3389 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3391 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3392 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3393 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3395 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3396 // CPSR and the implicit def of CPSR is not needed.
3397 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3398 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3400 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3401 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3403 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3404 // The assume-no-carry-in form uses the negation of the input since add/sub
3405 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3406 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3408 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3409 (SUBri GPR:$src, so_imm_neg:$imm)>;
3410 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3411 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3413 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3414 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3415 Requires<[IsARM, HasV6T2]>;
3416 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3417 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3418 Requires<[IsARM, HasV6T2]>;
3420 // The with-carry-in form matches bitwise not instead of the negation.
3421 // Effectively, the inverse interpretation of the carry flag already accounts
3422 // for part of the negation.
3423 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3424 (SBCri GPR:$src, so_imm_not:$imm)>;
3425 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3426 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3428 // Note: These are implemented in C++ code, because they have to generate
3429 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3431 // (mul X, 2^n+1) -> (add (X << n), X)
3432 // (mul X, 2^n-1) -> (rsb X, (X << n))
3434 // ARM Arithmetic Instruction
3435 // GPR:$dst = GPR:$a op GPR:$b
3436 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3437 list<dag> pattern = [],
3438 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3439 string asm = "\t$Rd, $Rn, $Rm">
3440 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3441 Sched<[WriteALU, ReadALU, ReadALU]> {
3445 let Inst{27-20} = op27_20;
3446 let Inst{11-4} = op11_4;
3447 let Inst{19-16} = Rn;
3448 let Inst{15-12} = Rd;
3451 let Unpredictable{11-8} = 0b1111;
3454 // Saturating add/subtract
3456 let DecoderMethod = "DecodeQADDInstruction" in
3457 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3458 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3459 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3461 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3462 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3463 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3464 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3465 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3467 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3468 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3471 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3472 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3473 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3474 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3475 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3476 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3477 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3478 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3479 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3480 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3481 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3482 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3484 // Signed/Unsigned add/subtract
3486 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3487 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3488 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3489 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3490 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3491 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3492 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3493 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3494 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3495 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3496 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3497 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3499 // Signed/Unsigned halving add/subtract
3501 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3502 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3503 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3504 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3505 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3506 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3507 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3508 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3509 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3510 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3511 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3512 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3514 // Unsigned Sum of Absolute Differences [and Accumulate].
3516 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3517 MulFrm /* for convenience */, NoItinerary, "usad8",
3518 "\t$Rd, $Rn, $Rm", []>,
3519 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3523 let Inst{27-20} = 0b01111000;
3524 let Inst{15-12} = 0b1111;
3525 let Inst{7-4} = 0b0001;
3526 let Inst{19-16} = Rd;
3527 let Inst{11-8} = Rm;
3530 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3531 MulFrm /* for convenience */, NoItinerary, "usada8",
3532 "\t$Rd, $Rn, $Rm, $Ra", []>,
3533 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3538 let Inst{27-20} = 0b01111000;
3539 let Inst{7-4} = 0b0001;
3540 let Inst{19-16} = Rd;
3541 let Inst{15-12} = Ra;
3542 let Inst{11-8} = Rm;
3546 // Signed/Unsigned saturate
3548 def SSAT : AI<(outs GPRnopc:$Rd),
3549 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3550 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3555 let Inst{27-21} = 0b0110101;
3556 let Inst{5-4} = 0b01;
3557 let Inst{20-16} = sat_imm;
3558 let Inst{15-12} = Rd;
3559 let Inst{11-7} = sh{4-0};
3560 let Inst{6} = sh{5};
3564 def SSAT16 : AI<(outs GPRnopc:$Rd),
3565 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3566 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3570 let Inst{27-20} = 0b01101010;
3571 let Inst{11-4} = 0b11110011;
3572 let Inst{15-12} = Rd;
3573 let Inst{19-16} = sat_imm;
3577 def USAT : AI<(outs GPRnopc:$Rd),
3578 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3579 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3584 let Inst{27-21} = 0b0110111;
3585 let Inst{5-4} = 0b01;
3586 let Inst{15-12} = Rd;
3587 let Inst{11-7} = sh{4-0};
3588 let Inst{6} = sh{5};
3589 let Inst{20-16} = sat_imm;
3593 def USAT16 : AI<(outs GPRnopc:$Rd),
3594 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3595 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3599 let Inst{27-20} = 0b01101110;
3600 let Inst{11-4} = 0b11110011;
3601 let Inst{15-12} = Rd;
3602 let Inst{19-16} = sat_imm;
3606 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3607 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3608 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3609 (USAT imm:$pos, GPRnopc:$a, 0)>;
3611 //===----------------------------------------------------------------------===//
3612 // Bitwise Instructions.
3615 defm AND : AsI1_bin_irs<0b0000, "and",
3616 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3617 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3618 defm ORR : AsI1_bin_irs<0b1100, "orr",
3619 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3620 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3621 defm EOR : AsI1_bin_irs<0b0001, "eor",
3622 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3623 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3624 defm BIC : AsI1_bin_irs<0b1110, "bic",
3625 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3626 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3628 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3629 // like in the actual instruction encoding. The complexity of mapping the mask
3630 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3631 // instruction description.
3632 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3633 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3634 "bfc", "\t$Rd, $imm", "$src = $Rd",
3635 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3636 Requires<[IsARM, HasV6T2]> {
3639 let Inst{27-21} = 0b0111110;
3640 let Inst{6-0} = 0b0011111;
3641 let Inst{15-12} = Rd;
3642 let Inst{11-7} = imm{4-0}; // lsb
3643 let Inst{20-16} = imm{9-5}; // msb
3646 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3647 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3648 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3649 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3650 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3651 bf_inv_mask_imm:$imm))]>,
3652 Requires<[IsARM, HasV6T2]> {
3656 let Inst{27-21} = 0b0111110;
3657 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3658 let Inst{15-12} = Rd;
3659 let Inst{11-7} = imm{4-0}; // lsb
3660 let Inst{20-16} = imm{9-5}; // width
3664 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3665 "mvn", "\t$Rd, $Rm",
3666 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3670 let Inst{19-16} = 0b0000;
3671 let Inst{11-4} = 0b00000000;
3672 let Inst{15-12} = Rd;
3675 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3676 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3677 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3682 let Inst{19-16} = 0b0000;
3683 let Inst{15-12} = Rd;
3684 let Inst{11-5} = shift{11-5};
3686 let Inst{3-0} = shift{3-0};
3688 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3689 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3690 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3695 let Inst{19-16} = 0b0000;
3696 let Inst{15-12} = Rd;
3697 let Inst{11-8} = shift{11-8};
3699 let Inst{6-5} = shift{6-5};
3701 let Inst{3-0} = shift{3-0};
3703 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3704 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3705 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3706 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3710 let Inst{19-16} = 0b0000;
3711 let Inst{15-12} = Rd;
3712 let Inst{11-0} = imm;
3715 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3716 (BICri GPR:$src, so_imm_not:$imm)>;
3718 //===----------------------------------------------------------------------===//
3719 // Multiply Instructions.
3721 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3722 string opc, string asm, list<dag> pattern>
3723 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3727 let Inst{19-16} = Rd;
3728 let Inst{11-8} = Rm;
3731 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3732 string opc, string asm, list<dag> pattern>
3733 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3738 let Inst{19-16} = RdHi;
3739 let Inst{15-12} = RdLo;
3740 let Inst{11-8} = Rm;
3743 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3744 string opc, string asm, list<dag> pattern>
3745 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3750 let Inst{19-16} = RdHi;
3751 let Inst{15-12} = RdLo;
3752 let Inst{11-8} = Rm;
3756 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3757 // property. Remove them when it's possible to add those properties
3758 // on an individual MachineInstr, not just an instruction description.
3759 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3760 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3761 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3762 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3763 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3764 Requires<[IsARM, HasV6]> {
3765 let Inst{15-12} = 0b0000;
3766 let Unpredictable{15-12} = 0b1111;
3769 let Constraints = "@earlyclobber $Rd" in
3770 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3771 pred:$p, cc_out:$s),
3773 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3774 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3775 Requires<[IsARM, NoV6, UseMulOps]>;
3778 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3779 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3780 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3781 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3782 Requires<[IsARM, HasV6, UseMulOps]> {
3784 let Inst{15-12} = Ra;
3787 let Constraints = "@earlyclobber $Rd" in
3788 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3790 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3791 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3792 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3793 Requires<[IsARM, NoV6]>;
3795 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3796 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3797 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3798 Requires<[IsARM, HasV6T2, UseMulOps]> {
3803 let Inst{19-16} = Rd;
3804 let Inst{15-12} = Ra;
3805 let Inst{11-8} = Rm;
3809 // Extra precision multiplies with low / high results
3810 let neverHasSideEffects = 1 in {
3811 let isCommutable = 1 in {
3812 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3813 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3814 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3815 Requires<[IsARM, HasV6]>;
3817 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3818 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3819 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3820 Requires<[IsARM, HasV6]>;
3822 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3823 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3824 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3826 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3827 Requires<[IsARM, NoV6]>;
3829 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3830 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3832 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3833 Requires<[IsARM, NoV6]>;
3837 // Multiply + accumulate
3838 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3839 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3840 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3841 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3842 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3843 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3844 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3845 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3847 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3848 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3849 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3850 Requires<[IsARM, HasV6]> {
3855 let Inst{19-16} = RdHi;
3856 let Inst{15-12} = RdLo;
3857 let Inst{11-8} = Rm;
3862 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3863 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3864 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3866 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3867 pred:$p, cc_out:$s)>,
3868 Requires<[IsARM, NoV6]>;
3869 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3870 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3872 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3873 pred:$p, cc_out:$s)>,
3874 Requires<[IsARM, NoV6]>;
3877 } // neverHasSideEffects
3879 // Most significant word multiply
3880 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3881 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3882 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3883 Requires<[IsARM, HasV6]> {
3884 let Inst{15-12} = 0b1111;
3887 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3888 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3889 Requires<[IsARM, HasV6]> {
3890 let Inst{15-12} = 0b1111;
3893 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3894 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3895 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3896 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3897 Requires<[IsARM, HasV6, UseMulOps]>;
3899 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3900 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3901 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3902 Requires<[IsARM, HasV6]>;
3904 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3905 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3906 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3907 Requires<[IsARM, HasV6, UseMulOps]>;
3909 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3910 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3911 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3912 Requires<[IsARM, HasV6]>;
3914 multiclass AI_smul<string opc, PatFrag opnode> {
3915 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3916 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3917 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3918 (sext_inreg GPR:$Rm, i16)))]>,
3919 Requires<[IsARM, HasV5TE]>;
3921 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3922 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3923 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3924 (sra GPR:$Rm, (i32 16))))]>,
3925 Requires<[IsARM, HasV5TE]>;
3927 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3928 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3929 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3930 (sext_inreg GPR:$Rm, i16)))]>,
3931 Requires<[IsARM, HasV5TE]>;
3933 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3934 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3935 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3936 (sra GPR:$Rm, (i32 16))))]>,
3937 Requires<[IsARM, HasV5TE]>;
3939 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3940 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3941 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3942 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3943 Requires<[IsARM, HasV5TE]>;
3945 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3946 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3947 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3948 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3949 Requires<[IsARM, HasV5TE]>;
3953 multiclass AI_smla<string opc, PatFrag opnode> {
3954 let DecoderMethod = "DecodeSMLAInstruction" in {
3955 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3956 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3957 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3958 [(set GPRnopc:$Rd, (add GPR:$Ra,
3959 (opnode (sext_inreg GPRnopc:$Rn, i16),
3960 (sext_inreg GPRnopc:$Rm, i16))))]>,
3961 Requires<[IsARM, HasV5TE, UseMulOps]>;
3963 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3964 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3965 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3967 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3968 (sra GPRnopc:$Rm, (i32 16)))))]>,
3969 Requires<[IsARM, HasV5TE, UseMulOps]>;
3971 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3972 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3973 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3975 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3976 (sext_inreg GPRnopc:$Rm, i16))))]>,
3977 Requires<[IsARM, HasV5TE, UseMulOps]>;
3979 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3980 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3981 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3983 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3984 (sra GPRnopc:$Rm, (i32 16)))))]>,
3985 Requires<[IsARM, HasV5TE, UseMulOps]>;
3987 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3988 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3989 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3991 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3992 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3993 Requires<[IsARM, HasV5TE, UseMulOps]>;
3995 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3996 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3997 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3999 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
4000 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
4001 Requires<[IsARM, HasV5TE, UseMulOps]>;
4005 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4006 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4008 // Halfword multiply accumulate long: SMLAL<x><y>.
4009 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4010 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4011 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4012 Requires<[IsARM, HasV5TE]>;
4014 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4015 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4016 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4017 Requires<[IsARM, HasV5TE]>;
4019 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4020 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4021 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4022 Requires<[IsARM, HasV5TE]>;
4024 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4025 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4026 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4027 Requires<[IsARM, HasV5TE]>;
4029 // Helper class for AI_smld.
4030 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4031 InstrItinClass itin, string opc, string asm>
4032 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4035 let Inst{27-23} = 0b01110;
4036 let Inst{22} = long;
4037 let Inst{21-20} = 0b00;
4038 let Inst{11-8} = Rm;
4045 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4046 InstrItinClass itin, string opc, string asm>
4047 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4049 let Inst{15-12} = 0b1111;
4050 let Inst{19-16} = Rd;
4052 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4053 InstrItinClass itin, string opc, string asm>
4054 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4057 let Inst{19-16} = Rd;
4058 let Inst{15-12} = Ra;
4060 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4061 InstrItinClass itin, string opc, string asm>
4062 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4065 let Inst{19-16} = RdHi;
4066 let Inst{15-12} = RdLo;
4069 multiclass AI_smld<bit sub, string opc> {
4071 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4072 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4073 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4075 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4076 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4077 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4079 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4080 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4081 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4083 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4084 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4085 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4089 defm SMLA : AI_smld<0, "smla">;
4090 defm SMLS : AI_smld<1, "smls">;
4092 multiclass AI_sdml<bit sub, string opc> {
4094 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4095 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4096 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4097 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4100 defm SMUA : AI_sdml<0, "smua">;
4101 defm SMUS : AI_sdml<1, "smus">;
4103 //===----------------------------------------------------------------------===//
4104 // Division Instructions (ARMv7-A with virtualization extension)
4106 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4107 "sdiv", "\t$Rd, $Rn, $Rm",
4108 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4109 Requires<[IsARM, HasDivideInARM]>;
4111 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4112 "udiv", "\t$Rd, $Rn, $Rm",
4113 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4114 Requires<[IsARM, HasDivideInARM]>;
4116 //===----------------------------------------------------------------------===//
4117 // Misc. Arithmetic Instructions.
4120 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4121 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4122 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4125 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4126 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4127 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4128 Requires<[IsARM, HasV6T2]>,
4131 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4132 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4133 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4136 let AddedComplexity = 5 in
4137 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4138 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4139 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4140 Requires<[IsARM, HasV6]>,
4143 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4144 (REV16 (LDRH addrmode3:$addr))>;
4145 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4146 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4148 let AddedComplexity = 5 in
4149 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4150 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4151 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4152 Requires<[IsARM, HasV6]>,
4155 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4156 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4159 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4160 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4161 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4162 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4163 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4165 Requires<[IsARM, HasV6]>,
4166 Sched<[WriteALUsi, ReadALU]>;
4168 // Alternate cases for PKHBT where identities eliminate some nodes.
4169 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4170 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4171 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4172 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4174 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4175 // will match the pattern below.
4176 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4177 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4178 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4179 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4180 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4182 Requires<[IsARM, HasV6]>,
4183 Sched<[WriteALUsi, ReadALU]>;
4185 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4186 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4187 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4188 // pkhtb src1, src2, asr (17..31).
4189 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4190 (srl GPRnopc:$src2, imm16:$sh)),
4191 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4192 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4193 (sra GPRnopc:$src2, imm16_31:$sh)),
4194 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4195 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4196 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4197 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4199 //===----------------------------------------------------------------------===//
4203 // + CRC32{B,H,W} 0x04C11DB7
4204 // + CRC32C{B,H,W} 0x1EDC6F41
4207 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4208 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4209 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4210 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4211 Requires<[IsARM, HasV8, HasCRC]> {
4216 let Inst{31-28} = 0b1110;
4217 let Inst{27-23} = 0b00010;
4218 let Inst{22-21} = sz;
4220 let Inst{19-16} = Rn;
4221 let Inst{15-12} = Rd;
4222 let Inst{11-10} = 0b00;
4225 let Inst{7-4} = 0b0100;
4228 let Unpredictable{11-8} = 0b1101;
4231 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4232 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4233 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4234 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4235 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4236 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4238 //===----------------------------------------------------------------------===//
4239 // Comparison Instructions...
4242 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4243 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4244 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4246 // ARMcmpZ can re-use the above instruction definitions.
4247 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4248 (CMPri GPR:$src, so_imm:$imm)>;
4249 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4250 (CMPrr GPR:$src, GPR:$rhs)>;
4251 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4252 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4253 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4254 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4256 // CMN register-integer
4257 let isCompare = 1, Defs = [CPSR] in {
4258 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4259 "cmn", "\t$Rn, $imm",
4260 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4261 Sched<[WriteCMP, ReadALU]> {
4266 let Inst{19-16} = Rn;
4267 let Inst{15-12} = 0b0000;
4268 let Inst{11-0} = imm;
4270 let Unpredictable{15-12} = 0b1111;
4273 // CMN register-register/shift
4274 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4275 "cmn", "\t$Rn, $Rm",
4276 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4277 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4280 let isCommutable = 1;
4283 let Inst{19-16} = Rn;
4284 let Inst{15-12} = 0b0000;
4285 let Inst{11-4} = 0b00000000;
4288 let Unpredictable{15-12} = 0b1111;
4291 def CMNzrsi : AI1<0b1011, (outs),
4292 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4293 "cmn", "\t$Rn, $shift",
4294 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4295 GPR:$Rn, so_reg_imm:$shift)]>,
4296 Sched<[WriteCMPsi, ReadALU]> {
4301 let Inst{19-16} = Rn;
4302 let Inst{15-12} = 0b0000;
4303 let Inst{11-5} = shift{11-5};
4305 let Inst{3-0} = shift{3-0};
4307 let Unpredictable{15-12} = 0b1111;
4310 def CMNzrsr : AI1<0b1011, (outs),
4311 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4312 "cmn", "\t$Rn, $shift",
4313 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4314 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4315 Sched<[WriteCMPsr, ReadALU]> {
4320 let Inst{19-16} = Rn;
4321 let Inst{15-12} = 0b0000;
4322 let Inst{11-8} = shift{11-8};
4324 let Inst{6-5} = shift{6-5};
4326 let Inst{3-0} = shift{3-0};
4328 let Unpredictable{15-12} = 0b1111;
4333 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4334 (CMNri GPR:$src, so_imm_neg:$imm)>;
4336 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4337 (CMNri GPR:$src, so_imm_neg:$imm)>;
4339 // Note that TST/TEQ don't set all the same flags that CMP does!
4340 defm TST : AI1_cmp_irs<0b1000, "tst",
4341 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4342 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4343 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4344 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4345 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4347 // Pseudo i64 compares for some floating point compares.
4348 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4350 def BCCi64 : PseudoInst<(outs),
4351 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4353 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4356 def BCCZi64 : PseudoInst<(outs),
4357 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4358 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4360 } // usesCustomInserter
4363 // Conditional moves
4364 let neverHasSideEffects = 1 in {
4366 let isCommutable = 1, isSelect = 1 in
4367 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4368 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4370 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4372 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4374 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4375 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4378 (ARMcmov GPR:$false, so_reg_imm:$shift,
4380 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4381 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4382 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4384 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4386 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4389 let isMoveImm = 1 in
4391 : ARMPseudoInst<(outs GPR:$Rd),
4392 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4394 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4396 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4399 let isMoveImm = 1 in
4400 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4401 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4403 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4405 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4407 // Two instruction predicate mov immediate.
4408 let isMoveImm = 1 in
4410 : ARMPseudoInst<(outs GPR:$Rd),
4411 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4413 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4415 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4417 let isMoveImm = 1 in
4418 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4419 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4421 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4423 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4425 } // neverHasSideEffects
4428 //===----------------------------------------------------------------------===//
4429 // Atomic operations intrinsics
4432 def MemBarrierOptOperand : AsmOperandClass {
4433 let Name = "MemBarrierOpt";
4434 let ParserMethod = "parseMemBarrierOptOperand";
4436 def memb_opt : Operand<i32> {
4437 let PrintMethod = "printMemBOption";
4438 let ParserMatchClass = MemBarrierOptOperand;
4439 let DecoderMethod = "DecodeMemBarrierOption";
4442 def InstSyncBarrierOptOperand : AsmOperandClass {
4443 let Name = "InstSyncBarrierOpt";
4444 let ParserMethod = "parseInstSyncBarrierOptOperand";
4446 def instsyncb_opt : Operand<i32> {
4447 let PrintMethod = "printInstSyncBOption";
4448 let ParserMatchClass = InstSyncBarrierOptOperand;
4449 let DecoderMethod = "DecodeInstSyncBarrierOption";
4452 // Memory barriers protect the atomic sequences
4453 let hasSideEffects = 1 in {
4454 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4455 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4456 Requires<[IsARM, HasDB]> {
4458 let Inst{31-4} = 0xf57ff05;
4459 let Inst{3-0} = opt;
4462 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4463 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4464 Requires<[IsARM, HasDB]> {
4466 let Inst{31-4} = 0xf57ff04;
4467 let Inst{3-0} = opt;
4470 // ISB has only full system option
4471 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4472 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4473 Requires<[IsARM, HasDB]> {
4475 let Inst{31-4} = 0xf57ff06;
4476 let Inst{3-0} = opt;
4480 let usesCustomInserter = 1, Defs = [CPSR] in {
4482 // Pseudo instruction that combines movs + predicated rsbmi
4483 // to implement integer ABS
4484 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4487 let usesCustomInserter = 1 in {
4488 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4489 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4491 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4494 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4495 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4498 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4499 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4502 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4503 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4506 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4507 (int_arm_strex node:$val, node:$ptr), [{
4508 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4511 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4512 (int_arm_strex node:$val, node:$ptr), [{
4513 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4516 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4517 (int_arm_strex node:$val, node:$ptr), [{
4518 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4521 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4522 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4525 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4526 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4529 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4530 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4533 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4534 (int_arm_stlex node:$val, node:$ptr), [{
4535 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4538 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4539 (int_arm_stlex node:$val, node:$ptr), [{
4540 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4543 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4544 (int_arm_stlex node:$val, node:$ptr), [{
4545 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4548 let mayLoad = 1 in {
4549 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4550 NoItinerary, "ldrexb", "\t$Rt, $addr",
4551 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4552 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4553 NoItinerary, "ldrexh", "\t$Rt, $addr",
4554 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4555 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4556 NoItinerary, "ldrex", "\t$Rt, $addr",
4557 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4558 let hasExtraDefRegAllocReq = 1 in
4559 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4560 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4561 let DecoderMethod = "DecodeDoubleRegLoad";
4564 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4565 NoItinerary, "ldaexb", "\t$Rt, $addr",
4566 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4567 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4568 NoItinerary, "ldaexh", "\t$Rt, $addr",
4569 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4570 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4571 NoItinerary, "ldaex", "\t$Rt, $addr",
4572 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4573 let hasExtraDefRegAllocReq = 1 in
4574 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4575 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4576 let DecoderMethod = "DecodeDoubleRegLoad";
4580 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4581 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4582 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4583 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4584 addr_offset_none:$addr))]>;
4585 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4586 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4587 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4588 addr_offset_none:$addr))]>;
4589 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4590 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4591 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4592 addr_offset_none:$addr))]>;
4593 let hasExtraSrcRegAllocReq = 1 in
4594 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4595 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4596 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4597 let DecoderMethod = "DecodeDoubleRegStore";
4599 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4600 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4602 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4603 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4604 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4606 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4607 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4608 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4610 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4611 let hasExtraSrcRegAllocReq = 1 in
4612 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4613 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4614 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4615 let DecoderMethod = "DecodeDoubleRegStore";
4619 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4621 Requires<[IsARM, HasV7]> {
4622 let Inst{31-0} = 0b11110101011111111111000000011111;
4625 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4626 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4627 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4628 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4630 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4631 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4632 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4633 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4635 class acquiring_load<PatFrag base>
4636 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4637 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4638 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4641 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4642 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4643 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4645 class releasing_store<PatFrag base>
4646 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4647 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4648 return Ordering == Release || Ordering == SequentiallyConsistent;
4651 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4652 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4653 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4655 let AddedComplexity = 8 in {
4656 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4657 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4658 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4659 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4660 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4661 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4664 // SWP/SWPB are deprecated in V6/V7.
4665 let mayLoad = 1, mayStore = 1 in {
4666 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4667 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4669 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4670 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4674 //===----------------------------------------------------------------------===//
4675 // Coprocessor Instructions.
4678 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4679 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4680 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4681 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4682 imm:$CRm, imm:$opc2)]>,
4691 let Inst{3-0} = CRm;
4693 let Inst{7-5} = opc2;
4694 let Inst{11-8} = cop;
4695 let Inst{15-12} = CRd;
4696 let Inst{19-16} = CRn;
4697 let Inst{23-20} = opc1;
4700 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4701 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4702 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4703 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4704 imm:$CRm, imm:$opc2)]>,
4706 let Inst{31-28} = 0b1111;
4714 let Inst{3-0} = CRm;
4716 let Inst{7-5} = opc2;
4717 let Inst{11-8} = cop;
4718 let Inst{15-12} = CRd;
4719 let Inst{19-16} = CRn;
4720 let Inst{23-20} = opc1;
4723 class ACI<dag oops, dag iops, string opc, string asm,
4724 IndexMode im = IndexModeNone>
4725 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4727 let Inst{27-25} = 0b110;
4729 class ACInoP<dag oops, dag iops, string opc, string asm,
4730 IndexMode im = IndexModeNone>
4731 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4733 let Inst{31-28} = 0b1111;
4734 let Inst{27-25} = 0b110;
4736 multiclass LdStCop<bit load, bit Dbit, string asm> {
4737 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4738 asm, "\t$cop, $CRd, $addr"> {
4742 let Inst{24} = 1; // P = 1
4743 let Inst{23} = addr{8};
4744 let Inst{22} = Dbit;
4745 let Inst{21} = 0; // W = 0
4746 let Inst{20} = load;
4747 let Inst{19-16} = addr{12-9};
4748 let Inst{15-12} = CRd;
4749 let Inst{11-8} = cop;
4750 let Inst{7-0} = addr{7-0};
4751 let DecoderMethod = "DecodeCopMemInstruction";
4753 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4754 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4758 let Inst{24} = 1; // P = 1
4759 let Inst{23} = addr{8};
4760 let Inst{22} = Dbit;
4761 let Inst{21} = 1; // W = 1
4762 let Inst{20} = load;
4763 let Inst{19-16} = addr{12-9};
4764 let Inst{15-12} = CRd;
4765 let Inst{11-8} = cop;
4766 let Inst{7-0} = addr{7-0};
4767 let DecoderMethod = "DecodeCopMemInstruction";
4769 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4770 postidx_imm8s4:$offset),
4771 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4776 let Inst{24} = 0; // P = 0
4777 let Inst{23} = offset{8};
4778 let Inst{22} = Dbit;
4779 let Inst{21} = 1; // W = 1
4780 let Inst{20} = load;
4781 let Inst{19-16} = addr;
4782 let Inst{15-12} = CRd;
4783 let Inst{11-8} = cop;
4784 let Inst{7-0} = offset{7-0};
4785 let DecoderMethod = "DecodeCopMemInstruction";
4787 def _OPTION : ACI<(outs),
4788 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4789 coproc_option_imm:$option),
4790 asm, "\t$cop, $CRd, $addr, $option"> {
4795 let Inst{24} = 0; // P = 0
4796 let Inst{23} = 1; // U = 1
4797 let Inst{22} = Dbit;
4798 let Inst{21} = 0; // W = 0
4799 let Inst{20} = load;
4800 let Inst{19-16} = addr;
4801 let Inst{15-12} = CRd;
4802 let Inst{11-8} = cop;
4803 let Inst{7-0} = option;
4804 let DecoderMethod = "DecodeCopMemInstruction";
4807 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4808 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4809 asm, "\t$cop, $CRd, $addr"> {
4813 let Inst{24} = 1; // P = 1
4814 let Inst{23} = addr{8};
4815 let Inst{22} = Dbit;
4816 let Inst{21} = 0; // W = 0
4817 let Inst{20} = load;
4818 let Inst{19-16} = addr{12-9};
4819 let Inst{15-12} = CRd;
4820 let Inst{11-8} = cop;
4821 let Inst{7-0} = addr{7-0};
4822 let DecoderMethod = "DecodeCopMemInstruction";
4824 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4825 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4829 let Inst{24} = 1; // P = 1
4830 let Inst{23} = addr{8};
4831 let Inst{22} = Dbit;
4832 let Inst{21} = 1; // W = 1
4833 let Inst{20} = load;
4834 let Inst{19-16} = addr{12-9};
4835 let Inst{15-12} = CRd;
4836 let Inst{11-8} = cop;
4837 let Inst{7-0} = addr{7-0};
4838 let DecoderMethod = "DecodeCopMemInstruction";
4840 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4841 postidx_imm8s4:$offset),
4842 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4847 let Inst{24} = 0; // P = 0
4848 let Inst{23} = offset{8};
4849 let Inst{22} = Dbit;
4850 let Inst{21} = 1; // W = 1
4851 let Inst{20} = load;
4852 let Inst{19-16} = addr;
4853 let Inst{15-12} = CRd;
4854 let Inst{11-8} = cop;
4855 let Inst{7-0} = offset{7-0};
4856 let DecoderMethod = "DecodeCopMemInstruction";
4858 def _OPTION : ACInoP<(outs),
4859 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4860 coproc_option_imm:$option),
4861 asm, "\t$cop, $CRd, $addr, $option"> {
4866 let Inst{24} = 0; // P = 0
4867 let Inst{23} = 1; // U = 1
4868 let Inst{22} = Dbit;
4869 let Inst{21} = 0; // W = 0
4870 let Inst{20} = load;
4871 let Inst{19-16} = addr;
4872 let Inst{15-12} = CRd;
4873 let Inst{11-8} = cop;
4874 let Inst{7-0} = option;
4875 let DecoderMethod = "DecodeCopMemInstruction";
4879 defm LDC : LdStCop <1, 0, "ldc">;
4880 defm LDCL : LdStCop <1, 1, "ldcl">;
4881 defm STC : LdStCop <0, 0, "stc">;
4882 defm STCL : LdStCop <0, 1, "stcl">;
4883 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4884 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4885 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4886 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4888 //===----------------------------------------------------------------------===//
4889 // Move between coprocessor and ARM core register.
4892 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4894 : ABI<0b1110, oops, iops, NoItinerary, opc,
4895 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4896 let Inst{20} = direction;
4906 let Inst{15-12} = Rt;
4907 let Inst{11-8} = cop;
4908 let Inst{23-21} = opc1;
4909 let Inst{7-5} = opc2;
4910 let Inst{3-0} = CRm;
4911 let Inst{19-16} = CRn;
4914 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4916 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4917 c_imm:$CRm, imm0_7:$opc2),
4918 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4919 imm:$CRm, imm:$opc2)]>,
4920 ComplexDeprecationPredicate<"MCR">;
4921 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4922 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4923 c_imm:$CRm, 0, pred:$p)>;
4924 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4925 (outs GPRwithAPSR:$Rt),
4926 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4928 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4929 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4930 c_imm:$CRm, 0, pred:$p)>;
4932 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4933 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4935 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4937 : ABXI<0b1110, oops, iops, NoItinerary,
4938 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4939 let Inst{31-24} = 0b11111110;
4940 let Inst{20} = direction;
4950 let Inst{15-12} = Rt;
4951 let Inst{11-8} = cop;
4952 let Inst{23-21} = opc1;
4953 let Inst{7-5} = opc2;
4954 let Inst{3-0} = CRm;
4955 let Inst{19-16} = CRn;
4958 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4960 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4961 c_imm:$CRm, imm0_7:$opc2),
4962 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4963 imm:$CRm, imm:$opc2)]>,
4965 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
4966 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4968 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4969 (outs GPRwithAPSR:$Rt),
4970 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4973 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
4974 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4977 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4978 imm:$CRm, imm:$opc2),
4979 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4981 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4982 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4983 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4984 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4985 let Inst{23-21} = 0b010;
4986 let Inst{20} = direction;
4994 let Inst{15-12} = Rt;
4995 let Inst{19-16} = Rt2;
4996 let Inst{11-8} = cop;
4997 let Inst{7-4} = opc1;
4998 let Inst{3-0} = CRm;
5001 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5002 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5003 GPRnopc:$Rt2, imm:$CRm)]>;
5004 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5006 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5007 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5008 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5009 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5011 let Inst{31-28} = 0b1111;
5012 let Inst{23-21} = 0b010;
5013 let Inst{20} = direction;
5021 let Inst{15-12} = Rt;
5022 let Inst{19-16} = Rt2;
5023 let Inst{11-8} = cop;
5024 let Inst{7-4} = opc1;
5025 let Inst{3-0} = CRm;
5027 let DecoderMethod = "DecodeMRRC2";
5030 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5031 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5032 GPRnopc:$Rt2, imm:$CRm)]>;
5033 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5035 //===----------------------------------------------------------------------===//
5036 // Move between special register and ARM core register
5039 // Move to ARM core register from Special Register
5040 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5041 "mrs", "\t$Rd, apsr", []> {
5043 let Inst{23-16} = 0b00001111;
5044 let Unpredictable{19-17} = 0b111;
5046 let Inst{15-12} = Rd;
5048 let Inst{11-0} = 0b000000000000;
5049 let Unpredictable{11-0} = 0b110100001111;
5052 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5055 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5056 // section B9.3.9, with the R bit set to 1.
5057 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5058 "mrs", "\t$Rd, spsr", []> {
5060 let Inst{23-16} = 0b01001111;
5061 let Unpredictable{19-16} = 0b1111;
5063 let Inst{15-12} = Rd;
5065 let Inst{11-0} = 0b000000000000;
5066 let Unpredictable{11-0} = 0b110100001111;
5069 // Move from ARM core register to Special Register
5071 // No need to have both system and application versions, the encodings are the
5072 // same and the assembly parser has no way to distinguish between them. The mask
5073 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
5074 // the mask with the fields to be accessed in the special register.
5075 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5076 "msr", "\t$mask, $Rn", []> {
5081 let Inst{22} = mask{4}; // R bit
5082 let Inst{21-20} = 0b10;
5083 let Inst{19-16} = mask{3-0};
5084 let Inst{15-12} = 0b1111;
5085 let Inst{11-4} = 0b00000000;
5089 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5090 "msr", "\t$mask, $a", []> {
5095 let Inst{22} = mask{4}; // R bit
5096 let Inst{21-20} = 0b10;
5097 let Inst{19-16} = mask{3-0};
5098 let Inst{15-12} = 0b1111;
5102 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5103 // are needed to probe the stack when allocating more than
5104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5105 // ensure that the guard pages used by the OS virtual memory manager are
5106 // allocated in correct sequence.
5107 // The main point of having separate instruction are extra unmodelled effects
5108 // (compared to ordinary calls) like stack pointer change.
5110 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5111 [SDNPHasChain, SDNPSideEffect]>;
5112 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5113 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5115 //===----------------------------------------------------------------------===//
5119 // __aeabi_read_tp preserves the registers r1-r3.
5120 // This is a pseudo inst so that we can get the encoding right,
5121 // complete with fixup for the aeabi_read_tp function.
5122 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5123 // is defined in "ARMInstrThumb.td".
5125 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5126 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5127 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5130 //===----------------------------------------------------------------------===//
5131 // SJLJ Exception handling intrinsics
5132 // eh_sjlj_setjmp() is an instruction sequence to store the return
5133 // address and save #0 in R0 for the non-longjmp case.
5134 // Since by its nature we may be coming from some other function to get
5135 // here, and we're using the stack frame for the containing function to
5136 // save/restore registers, we can't keep anything live in regs across
5137 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5138 // when we get here from a longjmp(). We force everything out of registers
5139 // except for our own input by listing the relevant registers in Defs. By
5140 // doing so, we also cause the prologue/epilogue code to actively preserve
5141 // all of the callee-saved resgisters, which is exactly what we want.
5142 // A constant value is passed in $val, and we use the location as a scratch.
5144 // These are pseudo-instructions and are lowered to individual MC-insts, so
5145 // no encoding information is necessary.
5147 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5148 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5149 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5150 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5152 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5153 Requires<[IsARM, HasVFP2]>;
5157 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5158 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5159 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5161 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5162 Requires<[IsARM, NoVFP]>;
5165 // FIXME: Non-IOS version(s)
5166 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5167 Defs = [ R7, LR, SP ] in {
5168 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5170 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5171 Requires<[IsARM, IsIOS]>;
5174 // eh.sjlj.dispatchsetup pseudo-instruction.
5175 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5176 // the pseudo is expanded (which happens before any passes that need the
5177 // instruction size).
5178 let isBarrier = 1 in
5179 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5182 //===----------------------------------------------------------------------===//
5183 // Non-Instruction Patterns
5186 // ARMv4 indirect branch using (MOVr PC, dst)
5187 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5188 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5189 4, IIC_Br, [(brind GPR:$dst)],
5190 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5191 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5193 // Large immediate handling.
5195 // 32-bit immediate using two piece so_imms or movw + movt.
5196 // This is a single pseudo instruction, the benefit is that it can be remat'd
5197 // as a single unit instead of having to handle reg inputs.
5198 // FIXME: Remove this when we can do generalized remat.
5199 let isReMaterializable = 1, isMoveImm = 1 in
5200 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5201 [(set GPR:$dst, (arm_i32imm:$src))]>,
5204 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5205 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5206 Requires<[IsARM, DontUseMovt]>;
5208 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5209 // It also makes it possible to rematerialize the instructions.
5210 // FIXME: Remove this when we can do generalized remat and when machine licm
5211 // can properly the instructions.
5212 let isReMaterializable = 1 in {
5213 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5215 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5216 Requires<[IsARM, UseMovt]>;
5218 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5221 (ARMWrapperPIC tglobaladdr:$addr))]>,
5222 Requires<[IsARM, DontUseMovt]>;
5224 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5227 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5228 Requires<[IsARM, DontUseMovt]>;
5230 let AddedComplexity = 10 in
5231 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5233 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5234 Requires<[IsARM, UseMovt]>;
5235 } // isReMaterializable
5237 // ConstantPool, GlobalAddress, and JumpTable
5238 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5239 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5240 Requires<[IsARM, UseMovt]>;
5241 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5242 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5244 // TODO: add,sub,and, 3-instr forms?
5246 // Tail calls. These patterns also apply to Thumb mode.
5247 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5248 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5249 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5252 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5253 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5254 (BMOVPCB_CALL texternalsym:$func)>;
5256 // zextload i1 -> zextload i8
5257 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5258 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5260 // extload -> zextload
5261 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5262 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5263 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5264 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5266 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5268 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5269 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5272 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5273 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5274 (SMULBB GPR:$a, GPR:$b)>;
5275 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5276 (SMULBB GPR:$a, GPR:$b)>;
5277 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5278 (sra GPR:$b, (i32 16))),
5279 (SMULBT GPR:$a, GPR:$b)>;
5280 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5281 (SMULBT GPR:$a, GPR:$b)>;
5282 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5283 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5284 (SMULTB GPR:$a, GPR:$b)>;
5285 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5286 (SMULTB GPR:$a, GPR:$b)>;
5287 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5289 (SMULWB GPR:$a, GPR:$b)>;
5290 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5291 (SMULWB GPR:$a, GPR:$b)>;
5293 def : ARMV5MOPat<(add GPR:$acc,
5294 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5295 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5296 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5297 def : ARMV5MOPat<(add GPR:$acc,
5298 (mul sext_16_node:$a, sext_16_node:$b)),
5299 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5300 def : ARMV5MOPat<(add GPR:$acc,
5301 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5302 (sra GPR:$b, (i32 16)))),
5303 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5304 def : ARMV5MOPat<(add GPR:$acc,
5305 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5306 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5307 def : ARMV5MOPat<(add GPR:$acc,
5308 (mul (sra GPR:$a, (i32 16)),
5309 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5310 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5311 def : ARMV5MOPat<(add GPR:$acc,
5312 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5313 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5314 def : ARMV5MOPat<(add GPR:$acc,
5315 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5317 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5318 def : ARMV5MOPat<(add GPR:$acc,
5319 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5320 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5323 // Pre-v7 uses MCR for synchronization barriers.
5324 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5325 Requires<[IsARM, HasV6]>;
5327 // SXT/UXT with no rotate
5328 let AddedComplexity = 16 in {
5329 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5330 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5331 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5332 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5333 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5334 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5335 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5338 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5339 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5341 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5342 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5343 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5344 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5346 // Atomic load/store patterns
5347 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5348 (LDRBrs ldst_so_reg:$src)>;
5349 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5350 (LDRBi12 addrmode_imm12:$src)>;
5351 def : ARMPat<(atomic_load_16 addrmode3:$src),
5352 (LDRH addrmode3:$src)>;
5353 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5354 (LDRrs ldst_so_reg:$src)>;
5355 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5356 (LDRi12 addrmode_imm12:$src)>;
5357 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5358 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5359 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5360 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5361 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5362 (STRH GPR:$val, addrmode3:$ptr)>;
5363 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5364 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5365 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5366 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5369 //===----------------------------------------------------------------------===//
5373 include "ARMInstrThumb.td"
5375 //===----------------------------------------------------------------------===//
5379 include "ARMInstrThumb2.td"
5381 //===----------------------------------------------------------------------===//
5382 // Floating Point Support
5385 include "ARMInstrVFP.td"
5387 //===----------------------------------------------------------------------===//
5388 // Advanced SIMD (NEON) Support
5391 include "ARMInstrNEON.td"
5393 //===----------------------------------------------------------------------===//
5394 // Assembler aliases
5398 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5399 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5400 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5402 // System instructions
5403 def : MnemonicAlias<"swi", "svc">;
5405 // Load / Store Multiple
5406 def : MnemonicAlias<"ldmfd", "ldm">;
5407 def : MnemonicAlias<"ldmia", "ldm">;
5408 def : MnemonicAlias<"ldmea", "ldmdb">;
5409 def : MnemonicAlias<"stmfd", "stmdb">;
5410 def : MnemonicAlias<"stmia", "stm">;
5411 def : MnemonicAlias<"stmea", "stm">;
5413 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5414 // shift amount is zero (i.e., unspecified).
5415 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5416 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5417 Requires<[IsARM, HasV6]>;
5418 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5419 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5420 Requires<[IsARM, HasV6]>;
5422 // PUSH/POP aliases for STM/LDM
5423 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5424 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5426 // SSAT/USAT optional shift operand.
5427 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5428 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5429 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5430 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5433 // Extend instruction optional rotate operand.
5434 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5435 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5436 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5437 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5438 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5439 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5440 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5441 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5442 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5443 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5444 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5445 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5447 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5448 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5449 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5450 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5451 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5452 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5453 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5454 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5455 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5456 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5457 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5458 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5462 def : MnemonicAlias<"rfefa", "rfeda">;
5463 def : MnemonicAlias<"rfeea", "rfedb">;
5464 def : MnemonicAlias<"rfefd", "rfeia">;
5465 def : MnemonicAlias<"rfeed", "rfeib">;
5466 def : MnemonicAlias<"rfe", "rfeia">;
5469 def : MnemonicAlias<"srsfa", "srsib">;
5470 def : MnemonicAlias<"srsea", "srsia">;
5471 def : MnemonicAlias<"srsfd", "srsdb">;
5472 def : MnemonicAlias<"srsed", "srsda">;
5473 def : MnemonicAlias<"srs", "srsia">;
5476 def : MnemonicAlias<"qsubaddx", "qsax">;
5478 def : MnemonicAlias<"saddsubx", "sasx">;
5479 // SHASX == SHADDSUBX
5480 def : MnemonicAlias<"shaddsubx", "shasx">;
5481 // SHSAX == SHSUBADDX
5482 def : MnemonicAlias<"shsubaddx", "shsax">;
5484 def : MnemonicAlias<"ssubaddx", "ssax">;
5486 def : MnemonicAlias<"uaddsubx", "uasx">;
5487 // UHASX == UHADDSUBX
5488 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5489 // UHSAX == UHSUBADDX
5490 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5491 // UQASX == UQADDSUBX
5492 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5493 // UQSAX == UQSUBADDX
5494 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5496 def : MnemonicAlias<"usubaddx", "usax">;
5498 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5500 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5501 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5502 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5503 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5504 // Same for AND <--> BIC
5505 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5506 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5507 pred:$p, cc_out:$s)>;
5508 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5509 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5510 pred:$p, cc_out:$s)>;
5511 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5512 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5513 pred:$p, cc_out:$s)>;
5514 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5515 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5516 pred:$p, cc_out:$s)>;
5518 // Likewise, "add Rd, so_imm_neg" -> sub
5519 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5520 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5521 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5522 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5523 // Same for CMP <--> CMN via so_imm_neg
5524 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5525 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5526 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5527 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5529 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5530 // LSR, ROR, and RRX instructions.
5531 // FIXME: We need C++ parser hooks to map the alias to the MOV
5532 // encoding. It seems we should be able to do that sort of thing
5533 // in tblgen, but it could get ugly.
5534 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5535 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5536 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5538 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5539 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5541 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5542 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5544 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5545 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5548 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5549 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5550 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5551 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5552 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5554 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5555 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5557 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5558 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5560 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5561 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5565 // "neg" is and alias for "rsb rd, rn, #0"
5566 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5567 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5569 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5570 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5571 Requires<[IsARM, NoV6]>;
5573 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5574 // the instruction definitions need difference constraints pre-v6.
5575 // Use these aliases for the assembly parsing on pre-v6.
5576 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5577 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5578 Requires<[IsARM, NoV6]>;
5579 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5580 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5581 pred:$p, cc_out:$s)>,
5582 Requires<[IsARM, NoV6]>;
5583 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5584 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5585 Requires<[IsARM, NoV6]>;
5586 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5587 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5588 Requires<[IsARM, NoV6]>;
5589 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5590 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5591 Requires<[IsARM, NoV6]>;
5592 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5593 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5594 Requires<[IsARM, NoV6]>;
5596 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5598 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5599 ComplexDeprecationPredicate<"IT">;