1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
190 AssemblerPredicate<"HasV5TOps", "armv5t">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
203 AssemblerPredicate<"HasV6KOps", "armv6k">;
204 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
205 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
206 AssemblerPredicate<"HasV7Ops", "armv7">;
207 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
208 AssemblerPredicate<"HasV8Ops", "armv8">;
209 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
210 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
211 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
212 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
213 AssemblerPredicate<"FeatureVFP2", "VFP2">;
214 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
215 AssemblerPredicate<"FeatureVFP3", "VFP3">;
216 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
217 AssemblerPredicate<"FeatureVFP4", "VFP4">;
218 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
219 AssemblerPredicate<"!FeatureVFPOnlySP",
220 "double precision VFP">;
221 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
222 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
223 def HasNEON : Predicate<"Subtarget->hasNEON()">,
224 AssemblerPredicate<"FeatureNEON", "NEON">;
225 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
226 AssemblerPredicate<"FeatureCrypto", "crypto">;
227 def HasCRC : Predicate<"Subtarget->hasCRC()">,
228 AssemblerPredicate<"FeatureCRC", "crc">;
229 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
230 AssemblerPredicate<"FeatureFP16","half-float">;
231 def HasDivide : Predicate<"Subtarget->hasDivide()">,
232 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
233 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
234 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
235 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
236 AssemblerPredicate<"FeatureT2XtPk",
238 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
239 AssemblerPredicate<"FeatureDSPThumb2",
241 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
242 AssemblerPredicate<"FeatureDB",
244 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
245 AssemblerPredicate<"FeatureMP",
247 def HasVirtualization: Predicate<"false">,
248 AssemblerPredicate<"FeatureVirtualization",
249 "virtualization-extensions">;
250 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
251 AssemblerPredicate<"FeatureTrustZone",
253 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
254 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
255 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
256 def IsThumb : Predicate<"Subtarget->isThumb()">,
257 AssemblerPredicate<"ModeThumb", "thumb">;
258 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
259 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
260 AssemblerPredicate<"ModeThumb,FeatureThumb2",
262 def IsMClass : Predicate<"Subtarget->isMClass()">,
263 AssemblerPredicate<"FeatureMClass", "armv*m">;
264 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
265 AssemblerPredicate<"!FeatureMClass",
267 def IsARM : Predicate<"!Subtarget->isThumb()">,
268 AssemblerPredicate<"!ModeThumb", "arm-mode">;
269 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
270 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
271 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
272 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
273 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
274 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
276 // FIXME: Eventually this will be just "hasV6T2Ops".
277 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
278 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
279 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
280 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
282 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
283 // But only select them if more precision in FP computation is allowed.
284 // Do not use them for Darwin platforms.
285 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
286 " FPOpFusion::Fast && "
287 " Subtarget->hasVFP4()) && "
288 "!Subtarget->isTargetDarwin()">;
289 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
290 " FPOpFusion::Fast &&"
291 " Subtarget->hasVFP4()) || "
292 "Subtarget->isTargetDarwin()">;
294 // VGETLNi32 is microcoded on Swift - prefer VMOV.
295 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
296 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
298 // VDUP.32 is microcoded on Swift - prefer VMOV.
299 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
300 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
302 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
303 // this allows more effective execution domain optimization. See
304 // setExecutionDomain().
305 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
306 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
308 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
309 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
311 //===----------------------------------------------------------------------===//
312 // ARM Flag Definitions.
314 class RegConstraint<string C> {
315 string Constraints = C;
318 //===----------------------------------------------------------------------===//
319 // ARM specific transformation functions and pattern fragments.
322 // imm_neg_XFORM - Return the negation of an i32 immediate value.
323 def imm_neg_XFORM : SDNodeXForm<imm, [{
324 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
327 // imm_not_XFORM - Return the complement of a i32 immediate value.
328 def imm_not_XFORM : SDNodeXForm<imm, [{
329 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
332 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
333 def imm16_31 : ImmLeaf<i32, [{
334 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
337 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
338 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
339 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
342 /// Split a 32-bit immediate into two 16 bit parts.
343 def hi16 : SDNodeXForm<imm, [{
344 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
347 def lo16AllZero : PatLeaf<(i32 imm), [{
348 // Returns true if all low 16-bits are 0.
349 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
352 class BinOpWithFlagFrag<dag res> :
353 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
354 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
355 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
357 // An 'and' node with a single use.
358 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
359 return N->hasOneUse();
362 // An 'xor' node with a single use.
363 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
364 return N->hasOneUse();
367 // An 'fmul' node with a single use.
368 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
369 return N->hasOneUse();
372 // An 'fadd' node which checks for single non-hazardous use.
373 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
374 return hasNoVMLxHazardUse(N);
377 // An 'fsub' node which checks for single non-hazardous use.
378 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
379 return hasNoVMLxHazardUse(N);
382 //===----------------------------------------------------------------------===//
383 // Operand Definitions.
386 // Immediate operands with a shared generic asm render method.
387 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
390 // FIXME: rename brtarget to t2_brtarget
391 def brtarget : Operand<OtherVT> {
392 let EncoderMethod = "getBranchTargetOpValue";
393 let OperandType = "OPERAND_PCREL";
394 let DecoderMethod = "DecodeT2BROperand";
397 // FIXME: get rid of this one?
398 def uncondbrtarget : Operand<OtherVT> {
399 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
400 let OperandType = "OPERAND_PCREL";
403 // Branch target for ARM. Handles conditional/unconditional
404 def br_target : Operand<OtherVT> {
405 let EncoderMethod = "getARMBranchTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
410 // FIXME: rename bltarget to t2_bl_target?
411 def bltarget : Operand<i32> {
412 // Encoded the same as branch targets.
413 let EncoderMethod = "getBranchTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // Call target for ARM. Handles conditional/unconditional
418 // FIXME: rename bl_target to t2_bltarget?
419 def bl_target : Operand<i32> {
420 let EncoderMethod = "getARMBLTargetOpValue";
421 let OperandType = "OPERAND_PCREL";
424 def blx_target : Operand<i32> {
425 let EncoderMethod = "getARMBLXTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 // A list of registers separated by comma. Used by load/store multiple.
430 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
431 def reglist : Operand<i32> {
432 let EncoderMethod = "getRegisterListOpValue";
433 let ParserMatchClass = RegListAsmOperand;
434 let PrintMethod = "printRegisterList";
435 let DecoderMethod = "DecodeRegListOperand";
438 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
440 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
441 def dpr_reglist : Operand<i32> {
442 let EncoderMethod = "getRegisterListOpValue";
443 let ParserMatchClass = DPRRegListAsmOperand;
444 let PrintMethod = "printRegisterList";
445 let DecoderMethod = "DecodeDPRRegListOperand";
448 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
449 def spr_reglist : Operand<i32> {
450 let EncoderMethod = "getRegisterListOpValue";
451 let ParserMatchClass = SPRRegListAsmOperand;
452 let PrintMethod = "printRegisterList";
453 let DecoderMethod = "DecodeSPRRegListOperand";
456 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
457 def cpinst_operand : Operand<i32> {
458 let PrintMethod = "printCPInstOperand";
462 def pclabel : Operand<i32> {
463 let PrintMethod = "printPCLabel";
466 // ADR instruction labels.
467 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
468 def adrlabel : Operand<i32> {
469 let EncoderMethod = "getAdrLabelOpValue";
470 let ParserMatchClass = AdrLabelAsmOperand;
471 let PrintMethod = "printAdrLabelOperand<0>";
474 def neon_vcvt_imm32 : Operand<i32> {
475 let EncoderMethod = "getNEONVcvtImm32OpValue";
476 let DecoderMethod = "DecodeVCVTImmOperand";
479 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
480 def rot_imm_XFORM: SDNodeXForm<imm, [{
481 switch (N->getZExtValue()){
482 default: llvm_unreachable(nullptr);
483 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
484 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
485 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
486 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
489 def RotImmAsmOperand : AsmOperandClass {
491 let ParserMethod = "parseRotImm";
493 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
494 int32_t v = N->getZExtValue();
495 return v == 8 || v == 16 || v == 24; }],
497 let PrintMethod = "printRotImmOperand";
498 let ParserMatchClass = RotImmAsmOperand;
501 // shift_imm: An integer that encodes a shift amount and the type of shift
502 // (asr or lsl). The 6-bit immediate encodes as:
505 // {4-0} imm5 shift amount.
506 // asr #32 encoded as imm5 == 0.
507 def ShifterImmAsmOperand : AsmOperandClass {
508 let Name = "ShifterImm";
509 let ParserMethod = "parseShifterImm";
511 def shift_imm : Operand<i32> {
512 let PrintMethod = "printShiftImmOperand";
513 let ParserMatchClass = ShifterImmAsmOperand;
516 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
517 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
518 def so_reg_reg : Operand<i32>, // reg reg imm
519 ComplexPattern<i32, 3, "SelectRegShifterOperand",
520 [shl, srl, sra, rotr]> {
521 let EncoderMethod = "getSORegRegOpValue";
522 let PrintMethod = "printSORegRegOperand";
523 let DecoderMethod = "DecodeSORegRegOperand";
524 let ParserMatchClass = ShiftedRegAsmOperand;
525 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
528 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
529 def so_reg_imm : Operand<i32>, // reg imm
530 ComplexPattern<i32, 2, "SelectImmShifterOperand",
531 [shl, srl, sra, rotr]> {
532 let EncoderMethod = "getSORegImmOpValue";
533 let PrintMethod = "printSORegImmOperand";
534 let DecoderMethod = "DecodeSORegImmOperand";
535 let ParserMatchClass = ShiftedImmAsmOperand;
536 let MIOperandInfo = (ops GPR, i32imm);
539 // FIXME: Does this need to be distinct from so_reg?
540 def shift_so_reg_reg : Operand<i32>, // reg reg imm
541 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
542 [shl,srl,sra,rotr]> {
543 let EncoderMethod = "getSORegRegOpValue";
544 let PrintMethod = "printSORegRegOperand";
545 let DecoderMethod = "DecodeSORegRegOperand";
546 let ParserMatchClass = ShiftedRegAsmOperand;
547 let MIOperandInfo = (ops GPR, GPR, i32imm);
550 // FIXME: Does this need to be distinct from so_reg?
551 def shift_so_reg_imm : Operand<i32>, // reg reg imm
552 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
553 [shl,srl,sra,rotr]> {
554 let EncoderMethod = "getSORegImmOpValue";
555 let PrintMethod = "printSORegImmOperand";
556 let DecoderMethod = "DecodeSORegImmOperand";
557 let ParserMatchClass = ShiftedImmAsmOperand;
558 let MIOperandInfo = (ops GPR, i32imm);
561 // mod_imm: match a 32-bit immediate operand, which can be encoded into
562 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
563 // - "Modified Immediate Constants"). Within the MC layer we keep this
564 // immediate in its encoded form.
565 def ModImmAsmOperand: AsmOperandClass {
567 let ParserMethod = "parseModImm";
569 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
570 return ARM_AM::getSOImmVal(Imm) != -1;
572 let EncoderMethod = "getModImmOpValue";
573 let PrintMethod = "printModImmOperand";
574 let ParserMatchClass = ModImmAsmOperand;
577 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
578 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
579 // The actual parsing, encoding, decoding are handled by the destination
580 // instructions, which use mod_imm.
582 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
583 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
584 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
586 let ParserMatchClass = ModImmNotAsmOperand;
589 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
590 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
591 unsigned Value = -(unsigned)N->getZExtValue();
592 return Value && ARM_AM::getSOImmVal(Value) != -1;
594 let ParserMatchClass = ModImmNegAsmOperand;
597 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
598 def arm_i32imm : PatLeaf<(imm), [{
599 if (Subtarget->useMovt(*MF))
601 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
604 /// imm0_1 predicate - Immediate in the range [0,1].
605 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
606 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
608 /// imm0_3 predicate - Immediate in the range [0,3].
609 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
610 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
612 /// imm0_7 predicate - Immediate in the range [0,7].
613 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
614 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
615 return Imm >= 0 && Imm < 8;
617 let ParserMatchClass = Imm0_7AsmOperand;
620 /// imm8 predicate - Immediate is exactly 8.
621 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
622 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
623 let ParserMatchClass = Imm8AsmOperand;
626 /// imm16 predicate - Immediate is exactly 16.
627 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
628 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
629 let ParserMatchClass = Imm16AsmOperand;
632 /// imm32 predicate - Immediate is exactly 32.
633 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
634 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
635 let ParserMatchClass = Imm32AsmOperand;
638 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
640 /// imm1_7 predicate - Immediate in the range [1,7].
641 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
642 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
643 let ParserMatchClass = Imm1_7AsmOperand;
646 /// imm1_15 predicate - Immediate in the range [1,15].
647 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
648 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
649 let ParserMatchClass = Imm1_15AsmOperand;
652 /// imm1_31 predicate - Immediate in the range [1,31].
653 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
654 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
655 let ParserMatchClass = Imm1_31AsmOperand;
658 /// imm0_15 predicate - Immediate in the range [0,15].
659 def Imm0_15AsmOperand: ImmAsmOperand {
660 let Name = "Imm0_15";
661 let DiagnosticType = "ImmRange0_15";
663 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
664 return Imm >= 0 && Imm < 16;
666 let ParserMatchClass = Imm0_15AsmOperand;
669 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
670 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
671 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
672 return Imm >= 0 && Imm < 32;
674 let ParserMatchClass = Imm0_31AsmOperand;
677 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
678 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
679 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
680 return Imm >= 0 && Imm < 32;
682 let ParserMatchClass = Imm0_32AsmOperand;
685 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
686 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
687 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
688 return Imm >= 0 && Imm < 64;
690 let ParserMatchClass = Imm0_63AsmOperand;
693 /// imm0_239 predicate - Immediate in the range [0,239].
694 def Imm0_239AsmOperand : ImmAsmOperand {
695 let Name = "Imm0_239";
696 let DiagnosticType = "ImmRange0_239";
698 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
699 let ParserMatchClass = Imm0_239AsmOperand;
702 /// imm0_255 predicate - Immediate in the range [0,255].
703 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
704 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
705 let ParserMatchClass = Imm0_255AsmOperand;
708 /// imm0_65535 - An immediate is in the range [0.65535].
709 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
710 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
711 return Imm >= 0 && Imm < 65536;
713 let ParserMatchClass = Imm0_65535AsmOperand;
716 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
717 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
718 return -Imm >= 0 && -Imm < 65536;
721 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
722 // a relocatable expression.
724 // FIXME: This really needs a Thumb version separate from the ARM version.
725 // While the range is the same, and can thus use the same match class,
726 // the encoding is different so it should have a different encoder method.
727 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
728 def imm0_65535_expr : Operand<i32> {
729 let EncoderMethod = "getHiLo16ImmOpValue";
730 let ParserMatchClass = Imm0_65535ExprAsmOperand;
733 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
734 def imm256_65535_expr : Operand<i32> {
735 let ParserMatchClass = Imm256_65535ExprAsmOperand;
738 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
739 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
740 def imm24b : Operand<i32>, ImmLeaf<i32, [{
741 return Imm >= 0 && Imm <= 0xffffff;
743 let ParserMatchClass = Imm24bitAsmOperand;
747 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
749 def BitfieldAsmOperand : AsmOperandClass {
750 let Name = "Bitfield";
751 let ParserMethod = "parseBitfield";
754 def bf_inv_mask_imm : Operand<i32>,
756 return ARM::isBitFieldInvertedMask(N->getZExtValue());
758 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
759 let PrintMethod = "printBitfieldInvMaskImmOperand";
760 let DecoderMethod = "DecodeBitfieldMaskOperand";
761 let ParserMatchClass = BitfieldAsmOperand;
764 def imm1_32_XFORM: SDNodeXForm<imm, [{
765 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
767 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
768 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
769 uint64_t Imm = N->getZExtValue();
770 return Imm > 0 && Imm <= 32;
773 let PrintMethod = "printImmPlusOneOperand";
774 let ParserMatchClass = Imm1_32AsmOperand;
777 def imm1_16_XFORM: SDNodeXForm<imm, [{
778 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
780 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
781 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
783 let PrintMethod = "printImmPlusOneOperand";
784 let ParserMatchClass = Imm1_16AsmOperand;
787 // Define ARM specific addressing modes.
788 // addrmode_imm12 := reg +/- imm12
790 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
791 class AddrMode_Imm12 : Operand<i32>,
792 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
793 // 12-bit immediate operand. Note that instructions using this encode
794 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
795 // immediate values are as normal.
797 let EncoderMethod = "getAddrModeImm12OpValue";
798 let DecoderMethod = "DecodeAddrModeImm12Operand";
799 let ParserMatchClass = MemImm12OffsetAsmOperand;
800 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
803 def addrmode_imm12 : AddrMode_Imm12 {
804 let PrintMethod = "printAddrModeImm12Operand<false>";
807 def addrmode_imm12_pre : AddrMode_Imm12 {
808 let PrintMethod = "printAddrModeImm12Operand<true>";
811 // ldst_so_reg := reg +/- reg shop imm
813 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
814 def ldst_so_reg : Operand<i32>,
815 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
816 let EncoderMethod = "getLdStSORegOpValue";
817 // FIXME: Simplify the printer
818 let PrintMethod = "printAddrMode2Operand";
819 let DecoderMethod = "DecodeSORegMemOperand";
820 let ParserMatchClass = MemRegOffsetAsmOperand;
821 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
824 // postidx_imm8 := +/- [0,255]
827 // {8} 1 is imm8 is non-negative. 0 otherwise.
828 // {7-0} [0,255] imm8 value.
829 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
830 def postidx_imm8 : Operand<i32> {
831 let PrintMethod = "printPostIdxImm8Operand";
832 let ParserMatchClass = PostIdxImm8AsmOperand;
833 let MIOperandInfo = (ops i32imm);
836 // postidx_imm8s4 := +/- [0,1020]
839 // {8} 1 is imm8 is non-negative. 0 otherwise.
840 // {7-0} [0,255] imm8 value, scaled by 4.
841 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
842 def postidx_imm8s4 : Operand<i32> {
843 let PrintMethod = "printPostIdxImm8s4Operand";
844 let ParserMatchClass = PostIdxImm8s4AsmOperand;
845 let MIOperandInfo = (ops i32imm);
849 // postidx_reg := +/- reg
851 def PostIdxRegAsmOperand : AsmOperandClass {
852 let Name = "PostIdxReg";
853 let ParserMethod = "parsePostIdxReg";
855 def postidx_reg : Operand<i32> {
856 let EncoderMethod = "getPostIdxRegOpValue";
857 let DecoderMethod = "DecodePostIdxReg";
858 let PrintMethod = "printPostIdxRegOperand";
859 let ParserMatchClass = PostIdxRegAsmOperand;
860 let MIOperandInfo = (ops GPRnopc, i32imm);
864 // addrmode2 := reg +/- imm12
865 // := reg +/- reg shop imm
867 // FIXME: addrmode2 should be refactored the rest of the way to always
868 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
869 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
870 def addrmode2 : Operand<i32>,
871 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
872 let EncoderMethod = "getAddrMode2OpValue";
873 let PrintMethod = "printAddrMode2Operand";
874 let ParserMatchClass = AddrMode2AsmOperand;
875 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
878 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
879 let Name = "PostIdxRegShifted";
880 let ParserMethod = "parsePostIdxReg";
882 def am2offset_reg : Operand<i32>,
883 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
884 [], [SDNPWantRoot]> {
885 let EncoderMethod = "getAddrMode2OffsetOpValue";
886 let PrintMethod = "printAddrMode2OffsetOperand";
887 // When using this for assembly, it's always as a post-index offset.
888 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
889 let MIOperandInfo = (ops GPRnopc, i32imm);
892 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
893 // the GPR is purely vestigal at this point.
894 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
895 def am2offset_imm : Operand<i32>,
896 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
897 [], [SDNPWantRoot]> {
898 let EncoderMethod = "getAddrMode2OffsetOpValue";
899 let PrintMethod = "printAddrMode2OffsetOperand";
900 let ParserMatchClass = AM2OffsetImmAsmOperand;
901 let MIOperandInfo = (ops GPRnopc, i32imm);
905 // addrmode3 := reg +/- reg
906 // addrmode3 := reg +/- imm8
908 // FIXME: split into imm vs. reg versions.
909 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
910 class AddrMode3 : Operand<i32>,
911 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
912 let EncoderMethod = "getAddrMode3OpValue";
913 let ParserMatchClass = AddrMode3AsmOperand;
914 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
917 def addrmode3 : AddrMode3
919 let PrintMethod = "printAddrMode3Operand<false>";
922 def addrmode3_pre : AddrMode3
924 let PrintMethod = "printAddrMode3Operand<true>";
927 // FIXME: split into imm vs. reg versions.
928 // FIXME: parser method to handle +/- register.
929 def AM3OffsetAsmOperand : AsmOperandClass {
930 let Name = "AM3Offset";
931 let ParserMethod = "parseAM3Offset";
933 def am3offset : Operand<i32>,
934 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
935 [], [SDNPWantRoot]> {
936 let EncoderMethod = "getAddrMode3OffsetOpValue";
937 let PrintMethod = "printAddrMode3OffsetOperand";
938 let ParserMatchClass = AM3OffsetAsmOperand;
939 let MIOperandInfo = (ops GPR, i32imm);
942 // ldstm_mode := {ia, ib, da, db}
944 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
945 let EncoderMethod = "getLdStmModeOpValue";
946 let PrintMethod = "printLdStmModeOperand";
949 // addrmode5 := reg +/- imm8*4
951 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
952 class AddrMode5 : Operand<i32>,
953 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
954 let EncoderMethod = "getAddrMode5OpValue";
955 let DecoderMethod = "DecodeAddrMode5Operand";
956 let ParserMatchClass = AddrMode5AsmOperand;
957 let MIOperandInfo = (ops GPR:$base, i32imm);
960 def addrmode5 : AddrMode5 {
961 let PrintMethod = "printAddrMode5Operand<false>";
964 def addrmode5_pre : AddrMode5 {
965 let PrintMethod = "printAddrMode5Operand<true>";
968 // addrmode6 := reg with optional alignment
970 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
971 def addrmode6 : Operand<i32>,
972 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
973 let PrintMethod = "printAddrMode6Operand";
974 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
975 let EncoderMethod = "getAddrMode6AddressOpValue";
976 let DecoderMethod = "DecodeAddrMode6Operand";
977 let ParserMatchClass = AddrMode6AsmOperand;
980 def am6offset : Operand<i32>,
981 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
982 [], [SDNPWantRoot]> {
983 let PrintMethod = "printAddrMode6OffsetOperand";
984 let MIOperandInfo = (ops GPR);
985 let EncoderMethod = "getAddrMode6OffsetOpValue";
986 let DecoderMethod = "DecodeGPRRegisterClass";
989 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
990 // (single element from one lane) for size 32.
991 def addrmode6oneL32 : Operand<i32>,
992 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
993 let PrintMethod = "printAddrMode6Operand";
994 let MIOperandInfo = (ops GPR:$addr, i32imm);
995 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
998 // Base class for addrmode6 with specific alignment restrictions.
999 class AddrMode6Align : Operand<i32>,
1000 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1001 let PrintMethod = "printAddrMode6Operand";
1002 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1003 let EncoderMethod = "getAddrMode6AddressOpValue";
1004 let DecoderMethod = "DecodeAddrMode6Operand";
1007 // Special version of addrmode6 to handle no allowed alignment encoding for
1008 // VLD/VST instructions and checking the alignment is not specified.
1009 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1010 let Name = "AlignedMemoryNone";
1011 let DiagnosticType = "AlignedMemoryRequiresNone";
1013 def addrmode6alignNone : AddrMode6Align {
1014 // The alignment specifier can only be omitted.
1015 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1018 // Special version of addrmode6 to handle 16-bit alignment encoding for
1019 // VLD/VST instructions and checking the alignment value.
1020 def AddrMode6Align16AsmOperand : AsmOperandClass {
1021 let Name = "AlignedMemory16";
1022 let DiagnosticType = "AlignedMemoryRequires16";
1024 def addrmode6align16 : AddrMode6Align {
1025 // The alignment specifier can only be 16 or omitted.
1026 let ParserMatchClass = AddrMode6Align16AsmOperand;
1029 // Special version of addrmode6 to handle 32-bit alignment encoding for
1030 // VLD/VST instructions and checking the alignment value.
1031 def AddrMode6Align32AsmOperand : AsmOperandClass {
1032 let Name = "AlignedMemory32";
1033 let DiagnosticType = "AlignedMemoryRequires32";
1035 def addrmode6align32 : AddrMode6Align {
1036 // The alignment specifier can only be 32 or omitted.
1037 let ParserMatchClass = AddrMode6Align32AsmOperand;
1040 // Special version of addrmode6 to handle 64-bit alignment encoding for
1041 // VLD/VST instructions and checking the alignment value.
1042 def AddrMode6Align64AsmOperand : AsmOperandClass {
1043 let Name = "AlignedMemory64";
1044 let DiagnosticType = "AlignedMemoryRequires64";
1046 def addrmode6align64 : AddrMode6Align {
1047 // The alignment specifier can only be 64 or omitted.
1048 let ParserMatchClass = AddrMode6Align64AsmOperand;
1051 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1052 // for VLD/VST instructions and checking the alignment value.
1053 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1054 let Name = "AlignedMemory64or128";
1055 let DiagnosticType = "AlignedMemoryRequires64or128";
1057 def addrmode6align64or128 : AddrMode6Align {
1058 // The alignment specifier can only be 64, 128 or omitted.
1059 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1062 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1063 // encoding for VLD/VST instructions and checking the alignment value.
1064 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1065 let Name = "AlignedMemory64or128or256";
1066 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1068 def addrmode6align64or128or256 : AddrMode6Align {
1069 // The alignment specifier can only be 64, 128, 256 or omitted.
1070 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1073 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1074 // instructions, specifically VLD4-dup.
1075 def addrmode6dup : Operand<i32>,
1076 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1077 let PrintMethod = "printAddrMode6Operand";
1078 let MIOperandInfo = (ops GPR:$addr, i32imm);
1079 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1080 // FIXME: This is close, but not quite right. The alignment specifier is
1082 let ParserMatchClass = AddrMode6AsmOperand;
1085 // Base class for addrmode6dup with specific alignment restrictions.
1086 class AddrMode6DupAlign : Operand<i32>,
1087 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1088 let PrintMethod = "printAddrMode6Operand";
1089 let MIOperandInfo = (ops GPR:$addr, i32imm);
1090 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1093 // Special version of addrmode6 to handle no allowed alignment encoding for
1094 // VLD-dup instruction and checking the alignment is not specified.
1095 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1096 let Name = "DupAlignedMemoryNone";
1097 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1099 def addrmode6dupalignNone : AddrMode6DupAlign {
1100 // The alignment specifier can only be omitted.
1101 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1104 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1105 // instruction and checking the alignment value.
1106 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1107 let Name = "DupAlignedMemory16";
1108 let DiagnosticType = "DupAlignedMemoryRequires16";
1110 def addrmode6dupalign16 : AddrMode6DupAlign {
1111 // The alignment specifier can only be 16 or omitted.
1112 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1115 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1116 // instruction and checking the alignment value.
1117 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1118 let Name = "DupAlignedMemory32";
1119 let DiagnosticType = "DupAlignedMemoryRequires32";
1121 def addrmode6dupalign32 : AddrMode6DupAlign {
1122 // The alignment specifier can only be 32 or omitted.
1123 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1126 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1127 // instructions and checking the alignment value.
1128 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1129 let Name = "DupAlignedMemory64";
1130 let DiagnosticType = "DupAlignedMemoryRequires64";
1132 def addrmode6dupalign64 : AddrMode6DupAlign {
1133 // The alignment specifier can only be 64 or omitted.
1134 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1137 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1138 // for VLD instructions and checking the alignment value.
1139 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1140 let Name = "DupAlignedMemory64or128";
1141 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1143 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1144 // The alignment specifier can only be 64, 128 or omitted.
1145 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1148 // addrmodepc := pc + reg
1150 def addrmodepc : Operand<i32>,
1151 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1152 let PrintMethod = "printAddrModePCOperand";
1153 let MIOperandInfo = (ops GPR, i32imm);
1156 // addr_offset_none := reg
1158 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1159 def addr_offset_none : Operand<i32>,
1160 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1161 let PrintMethod = "printAddrMode7Operand";
1162 let DecoderMethod = "DecodeAddrMode7Operand";
1163 let ParserMatchClass = MemNoOffsetAsmOperand;
1164 let MIOperandInfo = (ops GPR:$base);
1167 def nohash_imm : Operand<i32> {
1168 let PrintMethod = "printNoHashImmediate";
1171 def CoprocNumAsmOperand : AsmOperandClass {
1172 let Name = "CoprocNum";
1173 let ParserMethod = "parseCoprocNumOperand";
1175 def p_imm : Operand<i32> {
1176 let PrintMethod = "printPImmediate";
1177 let ParserMatchClass = CoprocNumAsmOperand;
1178 let DecoderMethod = "DecodeCoprocessor";
1181 def CoprocRegAsmOperand : AsmOperandClass {
1182 let Name = "CoprocReg";
1183 let ParserMethod = "parseCoprocRegOperand";
1185 def c_imm : Operand<i32> {
1186 let PrintMethod = "printCImmediate";
1187 let ParserMatchClass = CoprocRegAsmOperand;
1189 def CoprocOptionAsmOperand : AsmOperandClass {
1190 let Name = "CoprocOption";
1191 let ParserMethod = "parseCoprocOptionOperand";
1193 def coproc_option_imm : Operand<i32> {
1194 let PrintMethod = "printCoprocOptionImm";
1195 let ParserMatchClass = CoprocOptionAsmOperand;
1198 //===----------------------------------------------------------------------===//
1200 include "ARMInstrFormats.td"
1202 //===----------------------------------------------------------------------===//
1203 // Multiclass helpers...
1206 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1207 /// binop that produces a value.
1208 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1209 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1210 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1211 PatFrag opnode, bit Commutable = 0> {
1212 // The register-immediate version is re-materializable. This is useful
1213 // in particular for taking the address of a local.
1214 let isReMaterializable = 1 in {
1215 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1216 iii, opc, "\t$Rd, $Rn, $imm",
1217 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1218 Sched<[WriteALU, ReadALU]> {
1223 let Inst{19-16} = Rn;
1224 let Inst{15-12} = Rd;
1225 let Inst{11-0} = imm;
1228 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1229 iir, opc, "\t$Rd, $Rn, $Rm",
1230 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1231 Sched<[WriteALU, ReadALU, ReadALU]> {
1236 let isCommutable = Commutable;
1237 let Inst{19-16} = Rn;
1238 let Inst{15-12} = Rd;
1239 let Inst{11-4} = 0b00000000;
1243 def rsi : AsI1<opcod, (outs GPR:$Rd),
1244 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1245 iis, opc, "\t$Rd, $Rn, $shift",
1246 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1247 Sched<[WriteALUsi, ReadALU]> {
1252 let Inst{19-16} = Rn;
1253 let Inst{15-12} = Rd;
1254 let Inst{11-5} = shift{11-5};
1256 let Inst{3-0} = shift{3-0};
1259 def rsr : AsI1<opcod, (outs GPR:$Rd),
1260 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1261 iis, opc, "\t$Rd, $Rn, $shift",
1262 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1263 Sched<[WriteALUsr, ReadALUsr]> {
1268 let Inst{19-16} = Rn;
1269 let Inst{15-12} = Rd;
1270 let Inst{11-8} = shift{11-8};
1272 let Inst{6-5} = shift{6-5};
1274 let Inst{3-0} = shift{3-0};
1278 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1279 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1280 /// it is equivalent to the AsI1_bin_irs counterpart.
1281 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1282 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1283 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1284 PatFrag opnode, bit Commutable = 0> {
1285 // The register-immediate version is re-materializable. This is useful
1286 // in particular for taking the address of a local.
1287 let isReMaterializable = 1 in {
1288 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1289 iii, opc, "\t$Rd, $Rn, $imm",
1290 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1291 Sched<[WriteALU, ReadALU]> {
1296 let Inst{19-16} = Rn;
1297 let Inst{15-12} = Rd;
1298 let Inst{11-0} = imm;
1301 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1302 iir, opc, "\t$Rd, $Rn, $Rm",
1303 [/* pattern left blank */]>,
1304 Sched<[WriteALU, ReadALU, ReadALU]> {
1308 let Inst{11-4} = 0b00000000;
1311 let Inst{15-12} = Rd;
1312 let Inst{19-16} = Rn;
1315 def rsi : AsI1<opcod, (outs GPR:$Rd),
1316 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1317 iis, opc, "\t$Rd, $Rn, $shift",
1318 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1319 Sched<[WriteALUsi, ReadALU]> {
1324 let Inst{19-16} = Rn;
1325 let Inst{15-12} = Rd;
1326 let Inst{11-5} = shift{11-5};
1328 let Inst{3-0} = shift{3-0};
1331 def rsr : AsI1<opcod, (outs GPR:$Rd),
1332 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1333 iis, opc, "\t$Rd, $Rn, $shift",
1334 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1335 Sched<[WriteALUsr, ReadALUsr]> {
1340 let Inst{19-16} = Rn;
1341 let Inst{15-12} = Rd;
1342 let Inst{11-8} = shift{11-8};
1344 let Inst{6-5} = shift{6-5};
1346 let Inst{3-0} = shift{3-0};
1350 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1352 /// These opcodes will be converted to the real non-S opcodes by
1353 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1354 let hasPostISelHook = 1, Defs = [CPSR] in {
1355 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1356 InstrItinClass iis, PatFrag opnode,
1357 bit Commutable = 0> {
1358 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1360 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1361 Sched<[WriteALU, ReadALU]>;
1363 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1365 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1366 Sched<[WriteALU, ReadALU, ReadALU]> {
1367 let isCommutable = Commutable;
1369 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1370 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1372 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1373 so_reg_imm:$shift))]>,
1374 Sched<[WriteALUsi, ReadALU]>;
1376 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1377 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1379 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1380 so_reg_reg:$shift))]>,
1381 Sched<[WriteALUSsr, ReadALUsr]>;
1385 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1386 /// operands are reversed.
1387 let hasPostISelHook = 1, Defs = [CPSR] in {
1388 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1389 InstrItinClass iis, PatFrag opnode,
1390 bit Commutable = 0> {
1391 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1393 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1394 Sched<[WriteALU, ReadALU]>;
1396 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1397 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1399 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1401 Sched<[WriteALUsi, ReadALU]>;
1403 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1404 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1406 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1408 Sched<[WriteALUSsr, ReadALUsr]>;
1412 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1413 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1414 /// a explicit result, only implicitly set CPSR.
1415 let isCompare = 1, Defs = [CPSR] in {
1416 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1417 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1418 PatFrag opnode, bit Commutable = 0> {
1419 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1421 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1422 Sched<[WriteCMP, ReadALU]> {
1427 let Inst{19-16} = Rn;
1428 let Inst{15-12} = 0b0000;
1429 let Inst{11-0} = imm;
1431 let Unpredictable{15-12} = 0b1111;
1433 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1435 [(opnode GPR:$Rn, GPR:$Rm)]>,
1436 Sched<[WriteCMP, ReadALU, ReadALU]> {
1439 let isCommutable = Commutable;
1442 let Inst{19-16} = Rn;
1443 let Inst{15-12} = 0b0000;
1444 let Inst{11-4} = 0b00000000;
1447 let Unpredictable{15-12} = 0b1111;
1449 def rsi : AI1<opcod, (outs),
1450 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1451 opc, "\t$Rn, $shift",
1452 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1453 Sched<[WriteCMPsi, ReadALU]> {
1458 let Inst{19-16} = Rn;
1459 let Inst{15-12} = 0b0000;
1460 let Inst{11-5} = shift{11-5};
1462 let Inst{3-0} = shift{3-0};
1464 let Unpredictable{15-12} = 0b1111;
1466 def rsr : AI1<opcod, (outs),
1467 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1468 opc, "\t$Rn, $shift",
1469 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1470 Sched<[WriteCMPsr, ReadALU]> {
1475 let Inst{19-16} = Rn;
1476 let Inst{15-12} = 0b0000;
1477 let Inst{11-8} = shift{11-8};
1479 let Inst{6-5} = shift{6-5};
1481 let Inst{3-0} = shift{3-0};
1483 let Unpredictable{15-12} = 0b1111;
1489 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1490 /// register and one whose operand is a register rotated by 8/16/24.
1491 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1492 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1493 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1494 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1495 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1496 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1500 let Inst{19-16} = 0b1111;
1501 let Inst{15-12} = Rd;
1502 let Inst{11-10} = rot;
1506 class AI_ext_rrot_np<bits<8> opcod, string opc>
1507 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1508 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1509 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1511 let Inst{19-16} = 0b1111;
1512 let Inst{11-10} = rot;
1515 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1516 /// register and one whose operand is a register rotated by 8/16/24.
1517 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1518 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1519 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1520 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1521 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1522 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1527 let Inst{19-16} = Rn;
1528 let Inst{15-12} = Rd;
1529 let Inst{11-10} = rot;
1530 let Inst{9-4} = 0b000111;
1534 class AI_exta_rrot_np<bits<8> opcod, string opc>
1535 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1536 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1537 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1540 let Inst{19-16} = Rn;
1541 let Inst{11-10} = rot;
1544 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1545 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1546 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1547 bit Commutable = 0> {
1548 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1549 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1550 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1551 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1553 Sched<[WriteALU, ReadALU]> {
1558 let Inst{15-12} = Rd;
1559 let Inst{19-16} = Rn;
1560 let Inst{11-0} = imm;
1562 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1563 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1564 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1566 Sched<[WriteALU, ReadALU, ReadALU]> {
1570 let Inst{11-4} = 0b00000000;
1572 let isCommutable = Commutable;
1574 let Inst{15-12} = Rd;
1575 let Inst{19-16} = Rn;
1577 def rsi : AsI1<opcod, (outs GPR:$Rd),
1578 (ins GPR:$Rn, so_reg_imm:$shift),
1579 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1580 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1582 Sched<[WriteALUsi, ReadALU]> {
1587 let Inst{19-16} = Rn;
1588 let Inst{15-12} = Rd;
1589 let Inst{11-5} = shift{11-5};
1591 let Inst{3-0} = shift{3-0};
1593 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1594 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1595 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1596 [(set GPRnopc:$Rd, CPSR,
1597 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1599 Sched<[WriteALUsr, ReadALUsr]> {
1604 let Inst{19-16} = Rn;
1605 let Inst{15-12} = Rd;
1606 let Inst{11-8} = shift{11-8};
1608 let Inst{6-5} = shift{6-5};
1610 let Inst{3-0} = shift{3-0};
1615 /// AI1_rsc_irs - Define instructions and patterns for rsc
1616 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1617 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1618 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1619 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1620 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1621 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1623 Sched<[WriteALU, ReadALU]> {
1628 let Inst{15-12} = Rd;
1629 let Inst{19-16} = Rn;
1630 let Inst{11-0} = imm;
1632 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1633 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1634 [/* pattern left blank */]>,
1635 Sched<[WriteALU, ReadALU, ReadALU]> {
1639 let Inst{11-4} = 0b00000000;
1642 let Inst{15-12} = Rd;
1643 let Inst{19-16} = Rn;
1645 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1646 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1647 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1649 Sched<[WriteALUsi, ReadALU]> {
1654 let Inst{19-16} = Rn;
1655 let Inst{15-12} = Rd;
1656 let Inst{11-5} = shift{11-5};
1658 let Inst{3-0} = shift{3-0};
1660 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1661 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1662 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1664 Sched<[WriteALUsr, ReadALUsr]> {
1669 let Inst{19-16} = Rn;
1670 let Inst{15-12} = Rd;
1671 let Inst{11-8} = shift{11-8};
1673 let Inst{6-5} = shift{6-5};
1675 let Inst{3-0} = shift{3-0};
1680 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1681 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1682 InstrItinClass iir, PatFrag opnode> {
1683 // Note: We use the complex addrmode_imm12 rather than just an input
1684 // GPR and a constrained immediate so that we can use this to match
1685 // frame index references and avoid matching constant pool references.
1686 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1687 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1688 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1691 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1692 let Inst{19-16} = addr{16-13}; // Rn
1693 let Inst{15-12} = Rt;
1694 let Inst{11-0} = addr{11-0}; // imm12
1696 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1697 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1698 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1701 let shift{4} = 0; // Inst{4} = 0
1702 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1703 let Inst{19-16} = shift{16-13}; // Rn
1704 let Inst{15-12} = Rt;
1705 let Inst{11-0} = shift{11-0};
1710 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1711 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1712 InstrItinClass iir, PatFrag opnode> {
1713 // Note: We use the complex addrmode_imm12 rather than just an input
1714 // GPR and a constrained immediate so that we can use this to match
1715 // frame index references and avoid matching constant pool references.
1716 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1717 (ins addrmode_imm12:$addr),
1718 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1719 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1722 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1723 let Inst{19-16} = addr{16-13}; // Rn
1724 let Inst{15-12} = Rt;
1725 let Inst{11-0} = addr{11-0}; // imm12
1727 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1728 (ins ldst_so_reg:$shift),
1729 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1730 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1733 let shift{4} = 0; // Inst{4} = 0
1734 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1735 let Inst{19-16} = shift{16-13}; // Rn
1736 let Inst{15-12} = Rt;
1737 let Inst{11-0} = shift{11-0};
1743 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1744 InstrItinClass iir, PatFrag opnode> {
1745 // Note: We use the complex addrmode_imm12 rather than just an input
1746 // GPR and a constrained immediate so that we can use this to match
1747 // frame index references and avoid matching constant pool references.
1748 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1749 (ins GPR:$Rt, addrmode_imm12:$addr),
1750 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1751 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1754 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1755 let Inst{19-16} = addr{16-13}; // Rn
1756 let Inst{15-12} = Rt;
1757 let Inst{11-0} = addr{11-0}; // imm12
1759 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1760 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1761 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1764 let shift{4} = 0; // Inst{4} = 0
1765 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1766 let Inst{19-16} = shift{16-13}; // Rn
1767 let Inst{15-12} = Rt;
1768 let Inst{11-0} = shift{11-0};
1772 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1773 InstrItinClass iir, PatFrag opnode> {
1774 // Note: We use the complex addrmode_imm12 rather than just an input
1775 // GPR and a constrained immediate so that we can use this to match
1776 // frame index references and avoid matching constant pool references.
1777 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1778 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1779 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1780 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1783 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1784 let Inst{19-16} = addr{16-13}; // Rn
1785 let Inst{15-12} = Rt;
1786 let Inst{11-0} = addr{11-0}; // imm12
1788 def rs : AI2ldst<0b011, 0, isByte, (outs),
1789 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1790 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1791 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1794 let shift{4} = 0; // Inst{4} = 0
1795 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1796 let Inst{19-16} = shift{16-13}; // Rn
1797 let Inst{15-12} = Rt;
1798 let Inst{11-0} = shift{11-0};
1803 //===----------------------------------------------------------------------===//
1805 //===----------------------------------------------------------------------===//
1807 //===----------------------------------------------------------------------===//
1808 // Miscellaneous Instructions.
1811 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1812 /// the function. The first operand is the ID# for this instruction, the second
1813 /// is the index into the MachineConstantPool that this is, the third is the
1814 /// size in bytes of this constant pool entry.
1815 let hasSideEffects = 0, isNotDuplicable = 1 in
1816 def CONSTPOOL_ENTRY :
1817 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1818 i32imm:$size), NoItinerary, []>;
1820 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1821 // from removing one half of the matched pairs. That breaks PEI, which assumes
1822 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1823 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1824 def ADJCALLSTACKUP :
1825 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1826 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1828 def ADJCALLSTACKDOWN :
1829 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1830 [(ARMcallseq_start timm:$amt)]>;
1833 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1834 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1835 Requires<[IsARM, HasV6]> {
1837 let Inst{27-8} = 0b00110010000011110000;
1838 let Inst{7-0} = imm;
1841 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1842 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1843 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1844 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1845 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1846 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1848 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1849 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1854 let Inst{15-12} = Rd;
1855 let Inst{19-16} = Rn;
1856 let Inst{27-20} = 0b01101000;
1857 let Inst{7-4} = 0b1011;
1858 let Inst{11-8} = 0b1111;
1859 let Unpredictable{11-8} = 0b1111;
1862 // The 16-bit operand $val can be used by a debugger to store more information
1863 // about the breakpoint.
1864 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1865 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1867 let Inst{3-0} = val{3-0};
1868 let Inst{19-8} = val{15-4};
1869 let Inst{27-20} = 0b00010010;
1870 let Inst{31-28} = 0xe; // AL
1871 let Inst{7-4} = 0b0111;
1873 // default immediate for breakpoint mnemonic
1874 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1876 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1877 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1879 let Inst{3-0} = val{3-0};
1880 let Inst{19-8} = val{15-4};
1881 let Inst{27-20} = 0b00010000;
1882 let Inst{31-28} = 0xe; // AL
1883 let Inst{7-4} = 0b0111;
1886 // Change Processor State
1887 // FIXME: We should use InstAlias to handle the optional operands.
1888 class CPS<dag iops, string asm_ops>
1889 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1890 []>, Requires<[IsARM]> {
1896 let Inst{31-28} = 0b1111;
1897 let Inst{27-20} = 0b00010000;
1898 let Inst{19-18} = imod;
1899 let Inst{17} = M; // Enabled if mode is set;
1900 let Inst{16-9} = 0b00000000;
1901 let Inst{8-6} = iflags;
1903 let Inst{4-0} = mode;
1906 let DecoderMethod = "DecodeCPSInstruction" in {
1908 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1909 "$imod\t$iflags, $mode">;
1910 let mode = 0, M = 0 in
1911 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1913 let imod = 0, iflags = 0, M = 1 in
1914 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1917 // Preload signals the memory system of possible future data/instruction access.
1918 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1920 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1921 IIC_Preload, !strconcat(opc, "\t$addr"),
1922 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1923 Sched<[WritePreLd]> {
1926 let Inst{31-26} = 0b111101;
1927 let Inst{25} = 0; // 0 for immediate form
1928 let Inst{24} = data;
1929 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1930 let Inst{22} = read;
1931 let Inst{21-20} = 0b01;
1932 let Inst{19-16} = addr{16-13}; // Rn
1933 let Inst{15-12} = 0b1111;
1934 let Inst{11-0} = addr{11-0}; // imm12
1937 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1938 !strconcat(opc, "\t$shift"),
1939 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1940 Sched<[WritePreLd]> {
1942 let Inst{31-26} = 0b111101;
1943 let Inst{25} = 1; // 1 for register form
1944 let Inst{24} = data;
1945 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1946 let Inst{22} = read;
1947 let Inst{21-20} = 0b01;
1948 let Inst{19-16} = shift{16-13}; // Rn
1949 let Inst{15-12} = 0b1111;
1950 let Inst{11-0} = shift{11-0};
1955 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1956 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1957 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1959 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1960 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1962 let Inst{31-10} = 0b1111000100000001000000;
1967 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1968 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
1970 let Inst{27-4} = 0b001100100000111100001111;
1971 let Inst{3-0} = opt;
1974 // A8.8.247 UDF - Undefined (Encoding A1)
1975 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1976 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
1978 let Inst{31-28} = 0b1110; // AL
1979 let Inst{27-25} = 0b011;
1980 let Inst{24-20} = 0b11111;
1981 let Inst{19-8} = imm16{15-4};
1982 let Inst{7-4} = 0b1111;
1983 let Inst{3-0} = imm16{3-0};
1987 * A5.4 Permanently UNDEFINED instructions.
1989 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1990 * Other UDF encodings generate SIGILL.
1992 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1994 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1996 * 1101 1110 iiii iiii
1997 * It uses the following encoding:
1998 * 1110 0111 1111 1110 1101 1110 1111 0000
1999 * - In ARM: UDF #60896;
2000 * - In Thumb: UDF #254 followed by a branch-to-self.
2002 let isBarrier = 1, isTerminator = 1 in
2003 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2005 Requires<[IsARM,UseNaClTrap]> {
2006 let Inst = 0xe7fedef0;
2008 let isBarrier = 1, isTerminator = 1 in
2009 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2011 Requires<[IsARM,DontUseNaClTrap]> {
2012 let Inst = 0xe7ffdefe;
2015 // Address computation and loads and stores in PIC mode.
2016 let isNotDuplicable = 1 in {
2017 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2019 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2020 Sched<[WriteALU, ReadALU]>;
2022 let AddedComplexity = 10 in {
2023 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2025 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2027 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2029 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2031 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2033 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2035 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2037 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2039 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2041 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2043 let AddedComplexity = 10 in {
2044 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2045 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2047 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2048 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2049 addrmodepc:$addr)]>;
2051 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2052 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2054 } // isNotDuplicable = 1
2057 // LEApcrel - Load a pc-relative address into a register without offending the
2059 let hasSideEffects = 0, isReMaterializable = 1 in
2060 // The 'adr' mnemonic encodes differently if the label is before or after
2061 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2062 // know until then which form of the instruction will be used.
2063 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2064 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2065 Sched<[WriteALU, ReadALU]> {
2068 let Inst{27-25} = 0b001;
2070 let Inst{23-22} = label{13-12};
2073 let Inst{19-16} = 0b1111;
2074 let Inst{15-12} = Rd;
2075 let Inst{11-0} = label{11-0};
2078 let hasSideEffects = 1 in {
2079 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2080 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2082 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2083 (ins i32imm:$label, nohash_imm:$id, pred:$p),
2084 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2087 //===----------------------------------------------------------------------===//
2088 // Control Flow Instructions.
2091 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2093 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2094 "bx", "\tlr", [(ARMretflag)]>,
2095 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2096 let Inst{27-0} = 0b0001001011111111111100011110;
2100 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2101 "mov", "\tpc, lr", [(ARMretflag)]>,
2102 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2103 let Inst{27-0} = 0b0001101000001111000000001110;
2106 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2107 // the user-space one).
2108 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2110 [(ARMintretflag imm:$offset)]>;
2113 // Indirect branches
2114 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2116 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2117 [(brind GPR:$dst)]>,
2118 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2120 let Inst{31-4} = 0b1110000100101111111111110001;
2121 let Inst{3-0} = dst;
2124 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2125 "bx", "\t$dst", [/* pattern left blank */]>,
2126 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2128 let Inst{27-4} = 0b000100101111111111110001;
2129 let Inst{3-0} = dst;
2133 // SP is marked as a use to prevent stack-pointer assignments that appear
2134 // immediately before calls from potentially appearing dead.
2136 // FIXME: Do we really need a non-predicated version? If so, it should
2137 // at least be a pseudo instruction expanding to the predicated version
2138 // at MC lowering time.
2139 Defs = [LR], Uses = [SP] in {
2140 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2141 IIC_Br, "bl\t$func",
2142 [(ARMcall tglobaladdr:$func)]>,
2143 Requires<[IsARM]>, Sched<[WriteBrL]> {
2144 let Inst{31-28} = 0b1110;
2146 let Inst{23-0} = func;
2147 let DecoderMethod = "DecodeBranchImmInstruction";
2150 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2151 IIC_Br, "bl", "\t$func",
2152 [(ARMcall_pred tglobaladdr:$func)]>,
2153 Requires<[IsARM]>, Sched<[WriteBrL]> {
2155 let Inst{23-0} = func;
2156 let DecoderMethod = "DecodeBranchImmInstruction";
2160 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2161 IIC_Br, "blx\t$func",
2162 [(ARMcall GPR:$func)]>,
2163 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2165 let Inst{31-4} = 0b1110000100101111111111110011;
2166 let Inst{3-0} = func;
2169 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2170 IIC_Br, "blx", "\t$func",
2171 [(ARMcall_pred GPR:$func)]>,
2172 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2174 let Inst{27-4} = 0b000100101111111111110011;
2175 let Inst{3-0} = func;
2179 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2180 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2181 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2182 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2185 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2186 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2187 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2189 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2190 // return stack predictor.
2191 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2192 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2193 Requires<[IsARM]>, Sched<[WriteBr]>;
2196 let isBranch = 1, isTerminator = 1 in {
2197 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2198 // a two-value operand where a dag node expects two operands. :(
2199 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2200 IIC_Br, "b", "\t$target",
2201 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2204 let Inst{23-0} = target;
2205 let DecoderMethod = "DecodeBranchImmInstruction";
2208 let isBarrier = 1 in {
2209 // B is "predicable" since it's just a Bcc with an 'always' condition.
2210 let isPredicable = 1 in
2211 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2212 // should be sufficient.
2213 // FIXME: Is B really a Barrier? That doesn't seem right.
2214 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2215 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2218 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2219 def BR_JTr : ARMPseudoInst<(outs),
2220 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2222 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2224 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2225 // into i12 and rs suffixed versions.
2226 def BR_JTm : ARMPseudoInst<(outs),
2227 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2229 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2230 imm:$id)]>, Sched<[WriteBrTbl]>;
2231 def BR_JTadd : ARMPseudoInst<(outs),
2232 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2234 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2235 imm:$id)]>, Sched<[WriteBrTbl]>;
2236 } // isNotDuplicable = 1, isIndirectBranch = 1
2242 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2243 "blx\t$target", []>,
2244 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2245 let Inst{31-25} = 0b1111101;
2247 let Inst{23-0} = target{24-1};
2248 let Inst{24} = target{0};
2251 // Branch and Exchange Jazelle
2252 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2253 [/* pattern left blank */]>, Sched<[WriteBr]> {
2255 let Inst{23-20} = 0b0010;
2256 let Inst{19-8} = 0xfff;
2257 let Inst{7-4} = 0b0010;
2258 let Inst{3-0} = func;
2263 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2264 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2267 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2270 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2272 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2273 Requires<[IsARM]>, Sched<[WriteBr]>;
2275 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2277 (BX GPR:$dst)>, Sched<[WriteBr]>,
2281 // Secure Monitor Call is a system instruction.
2282 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2283 []>, Requires<[IsARM, HasTrustZone]> {
2285 let Inst{23-4} = 0b01100000000000000111;
2286 let Inst{3-0} = opt;
2289 // Supervisor Call (Software Interrupt)
2290 let isCall = 1, Uses = [SP] in {
2291 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2294 let Inst{23-0} = svc;
2298 // Store Return State
2299 class SRSI<bit wb, string asm>
2300 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2301 NoItinerary, asm, "", []> {
2303 let Inst{31-28} = 0b1111;
2304 let Inst{27-25} = 0b100;
2308 let Inst{19-16} = 0b1101; // SP
2309 let Inst{15-5} = 0b00000101000;
2310 let Inst{4-0} = mode;
2313 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2314 let Inst{24-23} = 0;
2316 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2317 let Inst{24-23} = 0;
2319 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2320 let Inst{24-23} = 0b10;
2322 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2323 let Inst{24-23} = 0b10;
2325 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2326 let Inst{24-23} = 0b01;
2328 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2329 let Inst{24-23} = 0b01;
2331 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2332 let Inst{24-23} = 0b11;
2334 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2335 let Inst{24-23} = 0b11;
2338 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2339 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2341 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2342 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2344 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2345 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2347 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2348 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2350 // Return From Exception
2351 class RFEI<bit wb, string asm>
2352 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2353 NoItinerary, asm, "", []> {
2355 let Inst{31-28} = 0b1111;
2356 let Inst{27-25} = 0b100;
2360 let Inst{19-16} = Rn;
2361 let Inst{15-0} = 0xa00;
2364 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2365 let Inst{24-23} = 0;
2367 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2368 let Inst{24-23} = 0;
2370 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2371 let Inst{24-23} = 0b10;
2373 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2374 let Inst{24-23} = 0b10;
2376 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2377 let Inst{24-23} = 0b01;
2379 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2380 let Inst{24-23} = 0b01;
2382 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2383 let Inst{24-23} = 0b11;
2385 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2386 let Inst{24-23} = 0b11;
2389 // Hypervisor Call is a system instruction
2391 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2392 "hvc", "\t$imm", []>,
2393 Requires<[IsARM, HasVirtualization]> {
2396 // Even though HVC isn't predicable, it's encoding includes a condition field.
2397 // The instruction is undefined if the condition field is 0xf otherwise it is
2398 // unpredictable if it isn't condition AL (0xe).
2399 let Inst{31-28} = 0b1110;
2400 let Unpredictable{31-28} = 0b1111;
2401 let Inst{27-24} = 0b0001;
2402 let Inst{23-20} = 0b0100;
2403 let Inst{19-8} = imm{15-4};
2404 let Inst{7-4} = 0b0111;
2405 let Inst{3-0} = imm{3-0};
2409 // Return from exception in Hypervisor mode.
2410 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2411 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2412 Requires<[IsARM, HasVirtualization]> {
2413 let Inst{23-0} = 0b011000000000000001101110;
2416 //===----------------------------------------------------------------------===//
2417 // Load / Store Instructions.
2423 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2424 UnOpFrag<(load node:$Src)>>;
2425 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2426 UnOpFrag<(zextloadi8 node:$Src)>>;
2427 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2428 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2429 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2430 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2432 // Special LDR for loads from non-pc-relative constpools.
2433 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2434 isReMaterializable = 1, isCodeGenOnly = 1 in
2435 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2436 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2440 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2441 let Inst{19-16} = 0b1111;
2442 let Inst{15-12} = Rt;
2443 let Inst{11-0} = addr{11-0}; // imm12
2446 // Loads with zero extension
2447 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2448 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2449 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2451 // Loads with sign extension
2452 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2453 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2454 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2456 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2457 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2458 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2460 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2462 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2463 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2464 Requires<[IsARM, HasV5TE]>;
2467 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2468 NoItinerary, "lda", "\t$Rt, $addr", []>;
2469 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2470 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2471 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2472 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2475 multiclass AI2_ldridx<bit isByte, string opc,
2476 InstrItinClass iii, InstrItinClass iir> {
2477 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2478 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2479 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2482 let Inst{23} = addr{12};
2483 let Inst{19-16} = addr{16-13};
2484 let Inst{11-0} = addr{11-0};
2485 let DecoderMethod = "DecodeLDRPreImm";
2488 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2489 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2490 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2493 let Inst{23} = addr{12};
2494 let Inst{19-16} = addr{16-13};
2495 let Inst{11-0} = addr{11-0};
2497 let DecoderMethod = "DecodeLDRPreReg";
2500 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2501 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2502 IndexModePost, LdFrm, iir,
2503 opc, "\t$Rt, $addr, $offset",
2504 "$addr.base = $Rn_wb", []> {
2510 let Inst{23} = offset{12};
2511 let Inst{19-16} = addr;
2512 let Inst{11-0} = offset{11-0};
2515 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2518 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2519 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2520 IndexModePost, LdFrm, iii,
2521 opc, "\t$Rt, $addr, $offset",
2522 "$addr.base = $Rn_wb", []> {
2528 let Inst{23} = offset{12};
2529 let Inst{19-16} = addr;
2530 let Inst{11-0} = offset{11-0};
2532 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2537 let mayLoad = 1, hasSideEffects = 0 in {
2538 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2539 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2540 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2541 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2544 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2545 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2546 (ins addrmode3_pre:$addr), IndexModePre,
2548 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2550 let Inst{23} = addr{8}; // U bit
2551 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2552 let Inst{19-16} = addr{12-9}; // Rn
2553 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2554 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2555 let DecoderMethod = "DecodeAddrMode3Instruction";
2557 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2558 (ins addr_offset_none:$addr, am3offset:$offset),
2559 IndexModePost, LdMiscFrm, itin,
2560 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2564 let Inst{23} = offset{8}; // U bit
2565 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2566 let Inst{19-16} = addr;
2567 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2568 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2569 let DecoderMethod = "DecodeAddrMode3Instruction";
2573 let mayLoad = 1, hasSideEffects = 0 in {
2574 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2575 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2576 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2577 let hasExtraDefRegAllocReq = 1 in {
2578 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2579 (ins addrmode3_pre:$addr), IndexModePre,
2580 LdMiscFrm, IIC_iLoad_d_ru,
2581 "ldrd", "\t$Rt, $Rt2, $addr!",
2582 "$addr.base = $Rn_wb", []> {
2584 let Inst{23} = addr{8}; // U bit
2585 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2586 let Inst{19-16} = addr{12-9}; // Rn
2587 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2588 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2589 let DecoderMethod = "DecodeAddrMode3Instruction";
2591 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2592 (ins addr_offset_none:$addr, am3offset:$offset),
2593 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2594 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2595 "$addr.base = $Rn_wb", []> {
2598 let Inst{23} = offset{8}; // U bit
2599 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2600 let Inst{19-16} = addr;
2601 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2602 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2603 let DecoderMethod = "DecodeAddrMode3Instruction";
2605 } // hasExtraDefRegAllocReq = 1
2606 } // mayLoad = 1, hasSideEffects = 0
2608 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2609 let mayLoad = 1, hasSideEffects = 0 in {
2610 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2611 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2612 IndexModePost, LdFrm, IIC_iLoad_ru,
2613 "ldrt", "\t$Rt, $addr, $offset",
2614 "$addr.base = $Rn_wb", []> {
2620 let Inst{23} = offset{12};
2621 let Inst{21} = 1; // overwrite
2622 let Inst{19-16} = addr;
2623 let Inst{11-5} = offset{11-5};
2625 let Inst{3-0} = offset{3-0};
2626 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2630 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2631 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2632 IndexModePost, LdFrm, IIC_iLoad_ru,
2633 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2639 let Inst{23} = offset{12};
2640 let Inst{21} = 1; // overwrite
2641 let Inst{19-16} = addr;
2642 let Inst{11-0} = offset{11-0};
2643 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2646 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2647 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2648 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2649 "ldrbt", "\t$Rt, $addr, $offset",
2650 "$addr.base = $Rn_wb", []> {
2656 let Inst{23} = offset{12};
2657 let Inst{21} = 1; // overwrite
2658 let Inst{19-16} = addr;
2659 let Inst{11-5} = offset{11-5};
2661 let Inst{3-0} = offset{3-0};
2662 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2666 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2667 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2668 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2669 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2675 let Inst{23} = offset{12};
2676 let Inst{21} = 1; // overwrite
2677 let Inst{19-16} = addr;
2678 let Inst{11-0} = offset{11-0};
2679 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2682 multiclass AI3ldrT<bits<4> op, string opc> {
2683 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2684 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2685 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2686 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2688 let Inst{23} = offset{8};
2690 let Inst{11-8} = offset{7-4};
2691 let Inst{3-0} = offset{3-0};
2693 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2694 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2695 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2696 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2698 let Inst{23} = Rm{4};
2701 let Unpredictable{11-8} = 0b1111;
2702 let Inst{3-0} = Rm{3-0};
2703 let DecoderMethod = "DecodeLDR";
2707 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2708 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2709 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2713 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2717 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2722 // Stores with truncate
2723 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2724 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2725 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2728 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2729 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2730 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2731 Requires<[IsARM, HasV5TE]> {
2737 multiclass AI2_stridx<bit isByte, string opc,
2738 InstrItinClass iii, InstrItinClass iir> {
2739 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2740 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2742 opc, "\t$Rt, $addr!",
2743 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2746 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2747 let Inst{19-16} = addr{16-13}; // Rn
2748 let Inst{11-0} = addr{11-0}; // imm12
2749 let DecoderMethod = "DecodeSTRPreImm";
2752 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2753 (ins GPR:$Rt, ldst_so_reg:$addr),
2754 IndexModePre, StFrm, iir,
2755 opc, "\t$Rt, $addr!",
2756 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2759 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2760 let Inst{19-16} = addr{16-13}; // Rn
2761 let Inst{11-0} = addr{11-0};
2762 let Inst{4} = 0; // Inst{4} = 0
2763 let DecoderMethod = "DecodeSTRPreReg";
2765 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2766 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2767 IndexModePost, StFrm, iir,
2768 opc, "\t$Rt, $addr, $offset",
2769 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2775 let Inst{23} = offset{12};
2776 let Inst{19-16} = addr;
2777 let Inst{11-0} = offset{11-0};
2780 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2783 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2784 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2785 IndexModePost, StFrm, iii,
2786 opc, "\t$Rt, $addr, $offset",
2787 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2793 let Inst{23} = offset{12};
2794 let Inst{19-16} = addr;
2795 let Inst{11-0} = offset{11-0};
2797 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2801 let mayStore = 1, hasSideEffects = 0 in {
2802 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2803 // IIC_iStore_siu depending on whether it the offset register is shifted.
2804 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2805 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2808 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2809 am2offset_reg:$offset),
2810 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2811 am2offset_reg:$offset)>;
2812 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2813 am2offset_imm:$offset),
2814 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2815 am2offset_imm:$offset)>;
2816 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2817 am2offset_reg:$offset),
2818 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2819 am2offset_reg:$offset)>;
2820 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2821 am2offset_imm:$offset),
2822 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2823 am2offset_imm:$offset)>;
2825 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2826 // put the patterns on the instruction definitions directly as ISel wants
2827 // the address base and offset to be separate operands, not a single
2828 // complex operand like we represent the instructions themselves. The
2829 // pseudos map between the two.
2830 let usesCustomInserter = 1,
2831 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2832 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2833 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2836 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2837 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2838 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2841 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2842 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2843 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2846 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2847 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2848 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2851 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2852 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2853 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2856 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2861 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2862 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2863 StMiscFrm, IIC_iStore_bh_ru,
2864 "strh", "\t$Rt, $addr!",
2865 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2867 let Inst{23} = addr{8}; // U bit
2868 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2869 let Inst{19-16} = addr{12-9}; // Rn
2870 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2871 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2872 let DecoderMethod = "DecodeAddrMode3Instruction";
2875 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2876 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2877 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2878 "strh", "\t$Rt, $addr, $offset",
2879 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2880 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2881 addr_offset_none:$addr,
2882 am3offset:$offset))]> {
2885 let Inst{23} = offset{8}; // U bit
2886 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2887 let Inst{19-16} = addr;
2888 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2889 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2890 let DecoderMethod = "DecodeAddrMode3Instruction";
2893 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2894 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2896 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2897 "strd", "\t$Rt, $Rt2, $addr!",
2898 "$addr.base = $Rn_wb", []> {
2900 let Inst{23} = addr{8}; // U bit
2901 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2902 let Inst{19-16} = addr{12-9}; // Rn
2903 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2904 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2905 let DecoderMethod = "DecodeAddrMode3Instruction";
2908 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2909 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2911 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2912 "strd", "\t$Rt, $Rt2, $addr, $offset",
2913 "$addr.base = $Rn_wb", []> {
2916 let Inst{23} = offset{8}; // U bit
2917 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2918 let Inst{19-16} = addr;
2919 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2920 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2921 let DecoderMethod = "DecodeAddrMode3Instruction";
2923 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2925 // STRT, STRBT, and STRHT
2927 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2928 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2929 IndexModePost, StFrm, IIC_iStore_bh_ru,
2930 "strbt", "\t$Rt, $addr, $offset",
2931 "$addr.base = $Rn_wb", []> {
2937 let Inst{23} = offset{12};
2938 let Inst{21} = 1; // overwrite
2939 let Inst{19-16} = addr;
2940 let Inst{11-5} = offset{11-5};
2942 let Inst{3-0} = offset{3-0};
2943 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2947 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2948 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2949 IndexModePost, StFrm, IIC_iStore_bh_ru,
2950 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2956 let Inst{23} = offset{12};
2957 let Inst{21} = 1; // overwrite
2958 let Inst{19-16} = addr;
2959 let Inst{11-0} = offset{11-0};
2960 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2964 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2965 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2967 let mayStore = 1, hasSideEffects = 0 in {
2968 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2969 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2970 IndexModePost, StFrm, IIC_iStore_ru,
2971 "strt", "\t$Rt, $addr, $offset",
2972 "$addr.base = $Rn_wb", []> {
2978 let Inst{23} = offset{12};
2979 let Inst{21} = 1; // overwrite
2980 let Inst{19-16} = addr;
2981 let Inst{11-5} = offset{11-5};
2983 let Inst{3-0} = offset{3-0};
2984 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2988 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2989 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2990 IndexModePost, StFrm, IIC_iStore_ru,
2991 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2997 let Inst{23} = offset{12};
2998 let Inst{21} = 1; // overwrite
2999 let Inst{19-16} = addr;
3000 let Inst{11-0} = offset{11-0};
3001 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3006 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3007 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3009 multiclass AI3strT<bits<4> op, string opc> {
3010 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3011 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3012 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3013 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3015 let Inst{23} = offset{8};
3017 let Inst{11-8} = offset{7-4};
3018 let Inst{3-0} = offset{3-0};
3020 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3021 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3022 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3023 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3025 let Inst{23} = Rm{4};
3028 let Inst{3-0} = Rm{3-0};
3033 defm STRHT : AI3strT<0b1011, "strht">;
3035 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3036 NoItinerary, "stl", "\t$Rt, $addr", []>;
3037 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3038 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3039 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3040 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3042 //===----------------------------------------------------------------------===//
3043 // Load / store multiple Instructions.
3046 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3047 InstrItinClass itin, InstrItinClass itin_upd> {
3048 // IA is the default, so no need for an explicit suffix on the
3049 // mnemonic here. Without it is the canonical spelling.
3051 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3052 IndexModeNone, f, itin,
3053 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3054 let Inst{24-23} = 0b01; // Increment After
3055 let Inst{22} = P_bit;
3056 let Inst{21} = 0; // No writeback
3057 let Inst{20} = L_bit;
3060 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3061 IndexModeUpd, f, itin_upd,
3062 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3063 let Inst{24-23} = 0b01; // Increment After
3064 let Inst{22} = P_bit;
3065 let Inst{21} = 1; // Writeback
3066 let Inst{20} = L_bit;
3068 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3071 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3072 IndexModeNone, f, itin,
3073 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3074 let Inst{24-23} = 0b00; // Decrement After
3075 let Inst{22} = P_bit;
3076 let Inst{21} = 0; // No writeback
3077 let Inst{20} = L_bit;
3080 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3081 IndexModeUpd, f, itin_upd,
3082 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3083 let Inst{24-23} = 0b00; // Decrement After
3084 let Inst{22} = P_bit;
3085 let Inst{21} = 1; // Writeback
3086 let Inst{20} = L_bit;
3088 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3091 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3092 IndexModeNone, f, itin,
3093 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3094 let Inst{24-23} = 0b10; // Decrement Before
3095 let Inst{22} = P_bit;
3096 let Inst{21} = 0; // No writeback
3097 let Inst{20} = L_bit;
3100 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3101 IndexModeUpd, f, itin_upd,
3102 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3103 let Inst{24-23} = 0b10; // Decrement Before
3104 let Inst{22} = P_bit;
3105 let Inst{21} = 1; // Writeback
3106 let Inst{20} = L_bit;
3108 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3111 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3112 IndexModeNone, f, itin,
3113 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3114 let Inst{24-23} = 0b11; // Increment Before
3115 let Inst{22} = P_bit;
3116 let Inst{21} = 0; // No writeback
3117 let Inst{20} = L_bit;
3120 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3121 IndexModeUpd, f, itin_upd,
3122 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3123 let Inst{24-23} = 0b11; // Increment Before
3124 let Inst{22} = P_bit;
3125 let Inst{21} = 1; // Writeback
3126 let Inst{20} = L_bit;
3128 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3132 let hasSideEffects = 0 in {
3134 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3135 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3136 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3138 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3139 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3141 ComplexDeprecationPredicate<"ARMStore">;
3145 // FIXME: remove when we have a way to marking a MI with these properties.
3146 // FIXME: Should pc be an implicit operand like PICADD, etc?
3147 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3148 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3149 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3150 reglist:$regs, variable_ops),
3151 4, IIC_iLoad_mBr, [],
3152 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3153 RegConstraint<"$Rn = $wb">;
3155 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3156 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3159 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3160 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3165 //===----------------------------------------------------------------------===//
3166 // Move Instructions.
3169 let hasSideEffects = 0 in
3170 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3171 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3175 let Inst{19-16} = 0b0000;
3176 let Inst{11-4} = 0b00000000;
3179 let Inst{15-12} = Rd;
3182 // A version for the smaller set of tail call registers.
3183 let hasSideEffects = 0 in
3184 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3185 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3189 let Inst{11-4} = 0b00000000;
3192 let Inst{15-12} = Rd;
3195 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3196 DPSoRegRegFrm, IIC_iMOVsr,
3197 "mov", "\t$Rd, $src",
3198 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3202 let Inst{15-12} = Rd;
3203 let Inst{19-16} = 0b0000;
3204 let Inst{11-8} = src{11-8};
3206 let Inst{6-5} = src{6-5};
3208 let Inst{3-0} = src{3-0};
3212 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3213 DPSoRegImmFrm, IIC_iMOVsr,
3214 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3215 UnaryDP, Sched<[WriteALU]> {
3218 let Inst{15-12} = Rd;
3219 let Inst{19-16} = 0b0000;
3220 let Inst{11-5} = src{11-5};
3222 let Inst{3-0} = src{3-0};
3226 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3227 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3228 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3233 let Inst{15-12} = Rd;
3234 let Inst{19-16} = 0b0000;
3235 let Inst{11-0} = imm;
3238 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3239 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3241 "movw", "\t$Rd, $imm",
3242 [(set GPR:$Rd, imm0_65535:$imm)]>,
3243 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3246 let Inst{15-12} = Rd;
3247 let Inst{11-0} = imm{11-0};
3248 let Inst{19-16} = imm{15-12};
3251 let DecoderMethod = "DecodeArmMOVTWInstruction";
3254 def : InstAlias<"mov${p} $Rd, $imm",
3255 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3258 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3259 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3262 let Constraints = "$src = $Rd" in {
3263 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3264 (ins GPR:$src, imm0_65535_expr:$imm),
3266 "movt", "\t$Rd, $imm",
3268 (or (and GPR:$src, 0xffff),
3269 lo16AllZero:$imm))]>, UnaryDP,
3270 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3273 let Inst{15-12} = Rd;
3274 let Inst{11-0} = imm{11-0};
3275 let Inst{19-16} = imm{15-12};
3278 let DecoderMethod = "DecodeArmMOVTWInstruction";
3281 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3282 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3287 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3288 Requires<[IsARM, HasV6T2]>;
3290 let Uses = [CPSR] in
3291 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3292 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3293 Requires<[IsARM]>, Sched<[WriteALU]>;
3295 // These aren't really mov instructions, but we have to define them this way
3296 // due to flag operands.
3298 let Defs = [CPSR] in {
3299 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3300 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3301 Sched<[WriteALU]>, Requires<[IsARM]>;
3302 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3303 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3304 Sched<[WriteALU]>, Requires<[IsARM]>;
3307 //===----------------------------------------------------------------------===//
3308 // Extend Instructions.
3313 def SXTB : AI_ext_rrot<0b01101010,
3314 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3315 def SXTH : AI_ext_rrot<0b01101011,
3316 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3318 def SXTAB : AI_exta_rrot<0b01101010,
3319 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3320 def SXTAH : AI_exta_rrot<0b01101011,
3321 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3323 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3325 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3329 let AddedComplexity = 16 in {
3330 def UXTB : AI_ext_rrot<0b01101110,
3331 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3332 def UXTH : AI_ext_rrot<0b01101111,
3333 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3334 def UXTB16 : AI_ext_rrot<0b01101100,
3335 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3337 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3338 // The transformation should probably be done as a combiner action
3339 // instead so we can include a check for masking back in the upper
3340 // eight bits of the source into the lower eight bits of the result.
3341 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3342 // (UXTB16r_rot GPR:$Src, 3)>;
3343 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3344 (UXTB16 GPR:$Src, 1)>;
3346 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3347 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3348 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3349 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3352 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3353 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3356 def SBFX : I<(outs GPRnopc:$Rd),
3357 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3358 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3359 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3360 Requires<[IsARM, HasV6T2]> {
3365 let Inst{27-21} = 0b0111101;
3366 let Inst{6-4} = 0b101;
3367 let Inst{20-16} = width;
3368 let Inst{15-12} = Rd;
3369 let Inst{11-7} = lsb;
3373 def UBFX : I<(outs GPRnopc:$Rd),
3374 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3375 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3376 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3377 Requires<[IsARM, HasV6T2]> {
3382 let Inst{27-21} = 0b0111111;
3383 let Inst{6-4} = 0b101;
3384 let Inst{20-16} = width;
3385 let Inst{15-12} = Rd;
3386 let Inst{11-7} = lsb;
3390 //===----------------------------------------------------------------------===//
3391 // Arithmetic Instructions.
3394 defm ADD : AsI1_bin_irs<0b0100, "add",
3395 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3396 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3397 defm SUB : AsI1_bin_irs<0b0010, "sub",
3398 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3399 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3401 // ADD and SUB with 's' bit set.
3403 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3404 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3405 // AdjustInstrPostInstrSelection where we determine whether or not to
3406 // set the "s" bit based on CPSR liveness.
3408 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3409 // support for an optional CPSR definition that corresponds to the DAG
3410 // node's second value. We can then eliminate the implicit def of CPSR.
3411 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3412 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3413 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3414 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3416 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3417 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3418 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3419 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3421 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3422 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3423 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3425 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3426 // CPSR and the implicit def of CPSR is not needed.
3427 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3428 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3430 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3431 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3433 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3434 // The assume-no-carry-in form uses the negation of the input since add/sub
3435 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3436 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3438 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3439 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3440 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3441 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3443 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3444 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3445 Requires<[IsARM, HasV6T2]>;
3446 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3447 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3448 Requires<[IsARM, HasV6T2]>;
3450 // The with-carry-in form matches bitwise not instead of the negation.
3451 // Effectively, the inverse interpretation of the carry flag already accounts
3452 // for part of the negation.
3453 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3454 (SBCri GPR:$src, mod_imm_not:$imm)>;
3455 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3456 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3457 Requires<[IsARM, HasV6T2]>;
3459 // Note: These are implemented in C++ code, because they have to generate
3460 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3462 // (mul X, 2^n+1) -> (add (X << n), X)
3463 // (mul X, 2^n-1) -> (rsb X, (X << n))
3465 // ARM Arithmetic Instruction
3466 // GPR:$dst = GPR:$a op GPR:$b
3467 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3468 list<dag> pattern = [],
3469 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3470 string asm = "\t$Rd, $Rn, $Rm">
3471 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3472 Sched<[WriteALU, ReadALU, ReadALU]> {
3476 let Inst{27-20} = op27_20;
3477 let Inst{11-4} = op11_4;
3478 let Inst{19-16} = Rn;
3479 let Inst{15-12} = Rd;
3482 let Unpredictable{11-8} = 0b1111;
3485 // Saturating add/subtract
3487 let DecoderMethod = "DecodeQADDInstruction" in
3488 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3489 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3490 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3492 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3493 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3494 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3495 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3496 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3498 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3499 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3502 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3503 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3504 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3505 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3506 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3507 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3508 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3509 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3510 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3511 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3512 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3513 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3515 // Signed/Unsigned add/subtract
3517 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3518 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3519 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3520 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3521 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3522 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3523 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3524 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3525 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3526 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3527 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3528 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3530 // Signed/Unsigned halving add/subtract
3532 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3533 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3534 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3535 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3536 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3537 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3538 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3539 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3540 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3541 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3542 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3543 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3545 // Unsigned Sum of Absolute Differences [and Accumulate].
3547 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3548 MulFrm /* for convenience */, NoItinerary, "usad8",
3549 "\t$Rd, $Rn, $Rm", []>,
3550 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3554 let Inst{27-20} = 0b01111000;
3555 let Inst{15-12} = 0b1111;
3556 let Inst{7-4} = 0b0001;
3557 let Inst{19-16} = Rd;
3558 let Inst{11-8} = Rm;
3561 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3562 MulFrm /* for convenience */, NoItinerary, "usada8",
3563 "\t$Rd, $Rn, $Rm, $Ra", []>,
3564 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3569 let Inst{27-20} = 0b01111000;
3570 let Inst{7-4} = 0b0001;
3571 let Inst{19-16} = Rd;
3572 let Inst{15-12} = Ra;
3573 let Inst{11-8} = Rm;
3577 // Signed/Unsigned saturate
3579 def SSAT : AI<(outs GPRnopc:$Rd),
3580 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3581 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3586 let Inst{27-21} = 0b0110101;
3587 let Inst{5-4} = 0b01;
3588 let Inst{20-16} = sat_imm;
3589 let Inst{15-12} = Rd;
3590 let Inst{11-7} = sh{4-0};
3591 let Inst{6} = sh{5};
3595 def SSAT16 : AI<(outs GPRnopc:$Rd),
3596 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3597 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3601 let Inst{27-20} = 0b01101010;
3602 let Inst{11-4} = 0b11110011;
3603 let Inst{15-12} = Rd;
3604 let Inst{19-16} = sat_imm;
3608 def USAT : AI<(outs GPRnopc:$Rd),
3609 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3610 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3615 let Inst{27-21} = 0b0110111;
3616 let Inst{5-4} = 0b01;
3617 let Inst{15-12} = Rd;
3618 let Inst{11-7} = sh{4-0};
3619 let Inst{6} = sh{5};
3620 let Inst{20-16} = sat_imm;
3624 def USAT16 : AI<(outs GPRnopc:$Rd),
3625 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3626 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3630 let Inst{27-20} = 0b01101110;
3631 let Inst{11-4} = 0b11110011;
3632 let Inst{15-12} = Rd;
3633 let Inst{19-16} = sat_imm;
3637 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3638 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3639 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3640 (USAT imm:$pos, GPRnopc:$a, 0)>;
3642 //===----------------------------------------------------------------------===//
3643 // Bitwise Instructions.
3646 defm AND : AsI1_bin_irs<0b0000, "and",
3647 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3648 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3649 defm ORR : AsI1_bin_irs<0b1100, "orr",
3650 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3651 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3652 defm EOR : AsI1_bin_irs<0b0001, "eor",
3653 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3654 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3655 defm BIC : AsI1_bin_irs<0b1110, "bic",
3656 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3657 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3659 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3660 // like in the actual instruction encoding. The complexity of mapping the mask
3661 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3662 // instruction description.
3663 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3664 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3665 "bfc", "\t$Rd, $imm", "$src = $Rd",
3666 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3667 Requires<[IsARM, HasV6T2]> {
3670 let Inst{27-21} = 0b0111110;
3671 let Inst{6-0} = 0b0011111;
3672 let Inst{15-12} = Rd;
3673 let Inst{11-7} = imm{4-0}; // lsb
3674 let Inst{20-16} = imm{9-5}; // msb
3677 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3678 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3679 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3680 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3681 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3682 bf_inv_mask_imm:$imm))]>,
3683 Requires<[IsARM, HasV6T2]> {
3687 let Inst{27-21} = 0b0111110;
3688 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3689 let Inst{15-12} = Rd;
3690 let Inst{11-7} = imm{4-0}; // lsb
3691 let Inst{20-16} = imm{9-5}; // width
3695 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3696 "mvn", "\t$Rd, $Rm",
3697 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3701 let Inst{19-16} = 0b0000;
3702 let Inst{11-4} = 0b00000000;
3703 let Inst{15-12} = Rd;
3706 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3707 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3708 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3713 let Inst{19-16} = 0b0000;
3714 let Inst{15-12} = Rd;
3715 let Inst{11-5} = shift{11-5};
3717 let Inst{3-0} = shift{3-0};
3719 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3720 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3721 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3726 let Inst{19-16} = 0b0000;
3727 let Inst{15-12} = Rd;
3728 let Inst{11-8} = shift{11-8};
3730 let Inst{6-5} = shift{6-5};
3732 let Inst{3-0} = shift{3-0};
3734 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3735 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3736 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3737 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3741 let Inst{19-16} = 0b0000;
3742 let Inst{15-12} = Rd;
3743 let Inst{11-0} = imm;
3746 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3747 (BICri GPR:$src, mod_imm_not:$imm)>;
3749 //===----------------------------------------------------------------------===//
3750 // Multiply Instructions.
3752 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3753 string opc, string asm, list<dag> pattern>
3754 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3758 let Inst{19-16} = Rd;
3759 let Inst{11-8} = Rm;
3762 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3763 string opc, string asm, list<dag> pattern>
3764 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3769 let Inst{19-16} = RdHi;
3770 let Inst{15-12} = RdLo;
3771 let Inst{11-8} = Rm;
3774 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3775 string opc, string asm, list<dag> pattern>
3776 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3781 let Inst{19-16} = RdHi;
3782 let Inst{15-12} = RdLo;
3783 let Inst{11-8} = Rm;
3787 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3788 // property. Remove them when it's possible to add those properties
3789 // on an individual MachineInstr, not just an instruction description.
3790 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3791 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3792 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3793 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3794 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3795 Requires<[IsARM, HasV6]> {
3796 let Inst{15-12} = 0b0000;
3797 let Unpredictable{15-12} = 0b1111;
3800 let Constraints = "@earlyclobber $Rd" in
3801 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3802 pred:$p, cc_out:$s),
3804 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3805 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3806 Requires<[IsARM, NoV6, UseMulOps]>;
3809 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3810 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3811 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3812 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3813 Requires<[IsARM, HasV6, UseMulOps]> {
3815 let Inst{15-12} = Ra;
3818 let Constraints = "@earlyclobber $Rd" in
3819 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3820 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3821 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3822 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3823 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3824 Requires<[IsARM, NoV6]>;
3826 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3827 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3828 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3829 Requires<[IsARM, HasV6T2, UseMulOps]> {
3834 let Inst{19-16} = Rd;
3835 let Inst{15-12} = Ra;
3836 let Inst{11-8} = Rm;
3840 // Extra precision multiplies with low / high results
3841 let hasSideEffects = 0 in {
3842 let isCommutable = 1 in {
3843 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3844 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3845 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3846 Requires<[IsARM, HasV6]>;
3848 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3849 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3850 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3851 Requires<[IsARM, HasV6]>;
3853 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3854 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3855 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3857 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3858 Requires<[IsARM, NoV6]>;
3860 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3861 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3863 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3864 Requires<[IsARM, NoV6]>;
3868 // Multiply + accumulate
3869 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3870 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3871 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3872 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3873 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3874 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3875 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3876 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3878 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3879 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3880 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3881 Requires<[IsARM, HasV6]> {
3886 let Inst{19-16} = RdHi;
3887 let Inst{15-12} = RdLo;
3888 let Inst{11-8} = Rm;
3893 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3894 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3895 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3897 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3898 pred:$p, cc_out:$s)>,
3899 Requires<[IsARM, NoV6]>;
3900 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3901 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3903 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3904 pred:$p, cc_out:$s)>,
3905 Requires<[IsARM, NoV6]>;
3910 // Most significant word multiply
3911 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3912 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3913 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3914 Requires<[IsARM, HasV6]> {
3915 let Inst{15-12} = 0b1111;
3918 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3919 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3920 Requires<[IsARM, HasV6]> {
3921 let Inst{15-12} = 0b1111;
3924 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3925 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3926 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3927 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3928 Requires<[IsARM, HasV6, UseMulOps]>;
3930 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3931 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3932 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3933 Requires<[IsARM, HasV6]>;
3935 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3936 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3937 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3938 Requires<[IsARM, HasV6, UseMulOps]>;
3940 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3941 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3942 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3943 Requires<[IsARM, HasV6]>;
3945 multiclass AI_smul<string opc, PatFrag opnode> {
3946 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3947 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3948 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3949 (sext_inreg GPR:$Rm, i16)))]>,
3950 Requires<[IsARM, HasV5TE]>;
3952 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3953 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3954 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3955 (sra GPR:$Rm, (i32 16))))]>,
3956 Requires<[IsARM, HasV5TE]>;
3958 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3959 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3960 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3961 (sext_inreg GPR:$Rm, i16)))]>,
3962 Requires<[IsARM, HasV5TE]>;
3964 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3965 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3966 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3967 (sra GPR:$Rm, (i32 16))))]>,
3968 Requires<[IsARM, HasV5TE]>;
3970 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3971 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3973 Requires<[IsARM, HasV5TE]>;
3975 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3976 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3978 Requires<[IsARM, HasV5TE]>;
3982 multiclass AI_smla<string opc, PatFrag opnode> {
3983 let DecoderMethod = "DecodeSMLAInstruction" in {
3984 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3985 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3986 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3987 [(set GPRnopc:$Rd, (add GPR:$Ra,
3988 (opnode (sext_inreg GPRnopc:$Rn, i16),
3989 (sext_inreg GPRnopc:$Rm, i16))))]>,
3990 Requires<[IsARM, HasV5TE, UseMulOps]>;
3992 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3993 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3994 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3996 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3997 (sra GPRnopc:$Rm, (i32 16)))))]>,
3998 Requires<[IsARM, HasV5TE, UseMulOps]>;
4000 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4001 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4002 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4004 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4005 (sext_inreg GPRnopc:$Rm, i16))))]>,
4006 Requires<[IsARM, HasV5TE, UseMulOps]>;
4008 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4009 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4010 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4012 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4013 (sra GPRnopc:$Rm, (i32 16)))))]>,
4014 Requires<[IsARM, HasV5TE, UseMulOps]>;
4016 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4017 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4018 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4020 Requires<[IsARM, HasV5TE, UseMulOps]>;
4022 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4023 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4024 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4026 Requires<[IsARM, HasV5TE, UseMulOps]>;
4030 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4031 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4033 // Halfword multiply accumulate long: SMLAL<x><y>.
4034 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4035 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4036 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4037 Requires<[IsARM, HasV5TE]>;
4039 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4040 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4041 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4042 Requires<[IsARM, HasV5TE]>;
4044 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4045 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4046 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4047 Requires<[IsARM, HasV5TE]>;
4049 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4050 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4051 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4052 Requires<[IsARM, HasV5TE]>;
4054 // Helper class for AI_smld.
4055 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4056 InstrItinClass itin, string opc, string asm>
4057 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4060 let Inst{27-23} = 0b01110;
4061 let Inst{22} = long;
4062 let Inst{21-20} = 0b00;
4063 let Inst{11-8} = Rm;
4070 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4071 InstrItinClass itin, string opc, string asm>
4072 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4074 let Inst{15-12} = 0b1111;
4075 let Inst{19-16} = Rd;
4077 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4078 InstrItinClass itin, string opc, string asm>
4079 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4082 let Inst{19-16} = Rd;
4083 let Inst{15-12} = Ra;
4085 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4086 InstrItinClass itin, string opc, string asm>
4087 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4090 let Inst{19-16} = RdHi;
4091 let Inst{15-12} = RdLo;
4094 multiclass AI_smld<bit sub, string opc> {
4096 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4097 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4098 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4100 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4101 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4102 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4104 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4105 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4106 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4108 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4109 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4110 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4114 defm SMLA : AI_smld<0, "smla">;
4115 defm SMLS : AI_smld<1, "smls">;
4117 multiclass AI_sdml<bit sub, string opc> {
4119 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4120 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4121 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4122 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4125 defm SMUA : AI_sdml<0, "smua">;
4126 defm SMUS : AI_sdml<1, "smus">;
4128 //===----------------------------------------------------------------------===//
4129 // Division Instructions (ARMv7-A with virtualization extension)
4131 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4132 "sdiv", "\t$Rd, $Rn, $Rm",
4133 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4134 Requires<[IsARM, HasDivideInARM]>;
4136 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4137 "udiv", "\t$Rd, $Rn, $Rm",
4138 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4139 Requires<[IsARM, HasDivideInARM]>;
4141 //===----------------------------------------------------------------------===//
4142 // Misc. Arithmetic Instructions.
4145 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4146 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4147 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4150 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4151 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4152 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4153 Requires<[IsARM, HasV6T2]>,
4156 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4157 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4158 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4161 let AddedComplexity = 5 in
4162 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4163 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4164 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4165 Requires<[IsARM, HasV6]>,
4168 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4169 (REV16 (LDRH addrmode3:$addr))>;
4170 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4171 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4173 let AddedComplexity = 5 in
4174 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4175 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4176 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4177 Requires<[IsARM, HasV6]>,
4180 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4181 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4184 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4185 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4186 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4187 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4188 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4190 Requires<[IsARM, HasV6]>,
4191 Sched<[WriteALUsi, ReadALU]>;
4193 // Alternate cases for PKHBT where identities eliminate some nodes.
4194 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4195 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4196 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4197 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4199 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4200 // will match the pattern below.
4201 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4202 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4203 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4204 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4205 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4207 Requires<[IsARM, HasV6]>,
4208 Sched<[WriteALUsi, ReadALU]>;
4210 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4211 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4212 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4213 // pkhtb src1, src2, asr (17..31).
4214 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4215 (srl GPRnopc:$src2, imm16:$sh)),
4216 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4217 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4218 (sra GPRnopc:$src2, imm16_31:$sh)),
4219 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4220 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4221 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4222 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4224 //===----------------------------------------------------------------------===//
4228 // + CRC32{B,H,W} 0x04C11DB7
4229 // + CRC32C{B,H,W} 0x1EDC6F41
4232 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4233 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4234 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4235 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4236 Requires<[IsARM, HasV8, HasCRC]> {
4241 let Inst{31-28} = 0b1110;
4242 let Inst{27-23} = 0b00010;
4243 let Inst{22-21} = sz;
4245 let Inst{19-16} = Rn;
4246 let Inst{15-12} = Rd;
4247 let Inst{11-10} = 0b00;
4250 let Inst{7-4} = 0b0100;
4253 let Unpredictable{11-8} = 0b1101;
4256 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4257 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4258 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4259 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4260 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4261 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4263 //===----------------------------------------------------------------------===//
4264 // Comparison Instructions...
4267 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4268 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4269 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4271 // ARMcmpZ can re-use the above instruction definitions.
4272 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4273 (CMPri GPR:$src, mod_imm:$imm)>;
4274 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4275 (CMPrr GPR:$src, GPR:$rhs)>;
4276 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4277 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4278 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4279 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4281 // CMN register-integer
4282 let isCompare = 1, Defs = [CPSR] in {
4283 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4284 "cmn", "\t$Rn, $imm",
4285 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4286 Sched<[WriteCMP, ReadALU]> {
4291 let Inst{19-16} = Rn;
4292 let Inst{15-12} = 0b0000;
4293 let Inst{11-0} = imm;
4295 let Unpredictable{15-12} = 0b1111;
4298 // CMN register-register/shift
4299 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4300 "cmn", "\t$Rn, $Rm",
4301 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4302 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4305 let isCommutable = 1;
4308 let Inst{19-16} = Rn;
4309 let Inst{15-12} = 0b0000;
4310 let Inst{11-4} = 0b00000000;
4313 let Unpredictable{15-12} = 0b1111;
4316 def CMNzrsi : AI1<0b1011, (outs),
4317 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4318 "cmn", "\t$Rn, $shift",
4319 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4320 GPR:$Rn, so_reg_imm:$shift)]>,
4321 Sched<[WriteCMPsi, ReadALU]> {
4326 let Inst{19-16} = Rn;
4327 let Inst{15-12} = 0b0000;
4328 let Inst{11-5} = shift{11-5};
4330 let Inst{3-0} = shift{3-0};
4332 let Unpredictable{15-12} = 0b1111;
4335 def CMNzrsr : AI1<0b1011, (outs),
4336 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4337 "cmn", "\t$Rn, $shift",
4338 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4339 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4340 Sched<[WriteCMPsr, ReadALU]> {
4345 let Inst{19-16} = Rn;
4346 let Inst{15-12} = 0b0000;
4347 let Inst{11-8} = shift{11-8};
4349 let Inst{6-5} = shift{6-5};
4351 let Inst{3-0} = shift{3-0};
4353 let Unpredictable{15-12} = 0b1111;
4358 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4359 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4361 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4362 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4364 // Note that TST/TEQ don't set all the same flags that CMP does!
4365 defm TST : AI1_cmp_irs<0b1000, "tst",
4366 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4367 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4368 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4369 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4370 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4372 // Pseudo i64 compares for some floating point compares.
4373 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4375 def BCCi64 : PseudoInst<(outs),
4376 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4378 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4381 def BCCZi64 : PseudoInst<(outs),
4382 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4383 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4385 } // usesCustomInserter
4388 // Conditional moves
4389 let hasSideEffects = 0 in {
4391 let isCommutable = 1, isSelect = 1 in
4392 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4393 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4395 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4397 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4399 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4400 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4403 (ARMcmov GPR:$false, so_reg_imm:$shift,
4405 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4406 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4407 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4409 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4411 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4414 let isMoveImm = 1 in
4416 : ARMPseudoInst<(outs GPR:$Rd),
4417 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4419 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4421 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4424 let isMoveImm = 1 in
4425 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4426 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4428 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4430 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4432 // Two instruction predicate mov immediate.
4433 let isMoveImm = 1 in
4435 : ARMPseudoInst<(outs GPR:$Rd),
4436 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4438 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4440 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4442 let isMoveImm = 1 in
4443 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4444 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4446 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4448 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4453 //===----------------------------------------------------------------------===//
4454 // Atomic operations intrinsics
4457 def MemBarrierOptOperand : AsmOperandClass {
4458 let Name = "MemBarrierOpt";
4459 let ParserMethod = "parseMemBarrierOptOperand";
4461 def memb_opt : Operand<i32> {
4462 let PrintMethod = "printMemBOption";
4463 let ParserMatchClass = MemBarrierOptOperand;
4464 let DecoderMethod = "DecodeMemBarrierOption";
4467 def InstSyncBarrierOptOperand : AsmOperandClass {
4468 let Name = "InstSyncBarrierOpt";
4469 let ParserMethod = "parseInstSyncBarrierOptOperand";
4471 def instsyncb_opt : Operand<i32> {
4472 let PrintMethod = "printInstSyncBOption";
4473 let ParserMatchClass = InstSyncBarrierOptOperand;
4474 let DecoderMethod = "DecodeInstSyncBarrierOption";
4477 // Memory barriers protect the atomic sequences
4478 let hasSideEffects = 1 in {
4479 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4480 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4481 Requires<[IsARM, HasDB]> {
4483 let Inst{31-4} = 0xf57ff05;
4484 let Inst{3-0} = opt;
4487 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4488 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4489 Requires<[IsARM, HasDB]> {
4491 let Inst{31-4} = 0xf57ff04;
4492 let Inst{3-0} = opt;
4495 // ISB has only full system option
4496 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4497 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4498 Requires<[IsARM, HasDB]> {
4500 let Inst{31-4} = 0xf57ff06;
4501 let Inst{3-0} = opt;
4505 let usesCustomInserter = 1, Defs = [CPSR] in {
4507 // Pseudo instruction that combines movs + predicated rsbmi
4508 // to implement integer ABS
4509 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4512 let usesCustomInserter = 1 in {
4513 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4514 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4516 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4519 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4520 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4523 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4524 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4527 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4528 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4531 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4532 (int_arm_strex node:$val, node:$ptr), [{
4533 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4536 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4537 (int_arm_strex node:$val, node:$ptr), [{
4538 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4541 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4542 (int_arm_strex node:$val, node:$ptr), [{
4543 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4546 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4547 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4550 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4551 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4554 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4555 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4558 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4559 (int_arm_stlex node:$val, node:$ptr), [{
4560 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4563 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4564 (int_arm_stlex node:$val, node:$ptr), [{
4565 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4568 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4569 (int_arm_stlex node:$val, node:$ptr), [{
4570 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4573 let mayLoad = 1 in {
4574 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4575 NoItinerary, "ldrexb", "\t$Rt, $addr",
4576 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4577 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4578 NoItinerary, "ldrexh", "\t$Rt, $addr",
4579 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4580 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4581 NoItinerary, "ldrex", "\t$Rt, $addr",
4582 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4583 let hasExtraDefRegAllocReq = 1 in
4584 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4585 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4586 let DecoderMethod = "DecodeDoubleRegLoad";
4589 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4590 NoItinerary, "ldaexb", "\t$Rt, $addr",
4591 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4592 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4593 NoItinerary, "ldaexh", "\t$Rt, $addr",
4594 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4595 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4596 NoItinerary, "ldaex", "\t$Rt, $addr",
4597 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4598 let hasExtraDefRegAllocReq = 1 in
4599 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4600 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4601 let DecoderMethod = "DecodeDoubleRegLoad";
4605 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4606 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4607 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4608 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4609 addr_offset_none:$addr))]>;
4610 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4611 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4612 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4613 addr_offset_none:$addr))]>;
4614 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4615 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4616 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4617 addr_offset_none:$addr))]>;
4618 let hasExtraSrcRegAllocReq = 1 in
4619 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4620 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4621 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4622 let DecoderMethod = "DecodeDoubleRegStore";
4624 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4625 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4627 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4628 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4629 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4631 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4632 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4633 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4635 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4636 let hasExtraSrcRegAllocReq = 1 in
4637 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4638 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4639 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4640 let DecoderMethod = "DecodeDoubleRegStore";
4644 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4646 Requires<[IsARM, HasV7]> {
4647 let Inst{31-0} = 0b11110101011111111111000000011111;
4650 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4651 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4652 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4653 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4655 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4656 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4657 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4658 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4660 class acquiring_load<PatFrag base>
4661 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4662 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4663 return isAtLeastAcquire(Ordering);
4666 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4667 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4668 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4670 class releasing_store<PatFrag base>
4671 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4672 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4673 return isAtLeastRelease(Ordering);
4676 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4677 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4678 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4680 let AddedComplexity = 8 in {
4681 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4682 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4683 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4684 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4685 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4686 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4689 // SWP/SWPB are deprecated in V6/V7.
4690 let mayLoad = 1, mayStore = 1 in {
4691 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4692 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4694 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4695 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4699 //===----------------------------------------------------------------------===//
4700 // Coprocessor Instructions.
4703 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4704 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4705 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4706 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4707 imm:$CRm, imm:$opc2)]>,
4716 let Inst{3-0} = CRm;
4718 let Inst{7-5} = opc2;
4719 let Inst{11-8} = cop;
4720 let Inst{15-12} = CRd;
4721 let Inst{19-16} = CRn;
4722 let Inst{23-20} = opc1;
4725 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4726 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4727 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4728 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4729 imm:$CRm, imm:$opc2)]>,
4731 let Inst{31-28} = 0b1111;
4739 let Inst{3-0} = CRm;
4741 let Inst{7-5} = opc2;
4742 let Inst{11-8} = cop;
4743 let Inst{15-12} = CRd;
4744 let Inst{19-16} = CRn;
4745 let Inst{23-20} = opc1;
4748 class ACI<dag oops, dag iops, string opc, string asm,
4749 IndexMode im = IndexModeNone>
4750 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4752 let Inst{27-25} = 0b110;
4754 class ACInoP<dag oops, dag iops, string opc, string asm,
4755 IndexMode im = IndexModeNone>
4756 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4758 let Inst{31-28} = 0b1111;
4759 let Inst{27-25} = 0b110;
4761 multiclass LdStCop<bit load, bit Dbit, string asm> {
4762 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4763 asm, "\t$cop, $CRd, $addr"> {
4767 let Inst{24} = 1; // P = 1
4768 let Inst{23} = addr{8};
4769 let Inst{22} = Dbit;
4770 let Inst{21} = 0; // W = 0
4771 let Inst{20} = load;
4772 let Inst{19-16} = addr{12-9};
4773 let Inst{15-12} = CRd;
4774 let Inst{11-8} = cop;
4775 let Inst{7-0} = addr{7-0};
4776 let DecoderMethod = "DecodeCopMemInstruction";
4778 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4779 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4783 let Inst{24} = 1; // P = 1
4784 let Inst{23} = addr{8};
4785 let Inst{22} = Dbit;
4786 let Inst{21} = 1; // W = 1
4787 let Inst{20} = load;
4788 let Inst{19-16} = addr{12-9};
4789 let Inst{15-12} = CRd;
4790 let Inst{11-8} = cop;
4791 let Inst{7-0} = addr{7-0};
4792 let DecoderMethod = "DecodeCopMemInstruction";
4794 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4795 postidx_imm8s4:$offset),
4796 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4801 let Inst{24} = 0; // P = 0
4802 let Inst{23} = offset{8};
4803 let Inst{22} = Dbit;
4804 let Inst{21} = 1; // W = 1
4805 let Inst{20} = load;
4806 let Inst{19-16} = addr;
4807 let Inst{15-12} = CRd;
4808 let Inst{11-8} = cop;
4809 let Inst{7-0} = offset{7-0};
4810 let DecoderMethod = "DecodeCopMemInstruction";
4812 def _OPTION : ACI<(outs),
4813 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4814 coproc_option_imm:$option),
4815 asm, "\t$cop, $CRd, $addr, $option"> {
4820 let Inst{24} = 0; // P = 0
4821 let Inst{23} = 1; // U = 1
4822 let Inst{22} = Dbit;
4823 let Inst{21} = 0; // W = 0
4824 let Inst{20} = load;
4825 let Inst{19-16} = addr;
4826 let Inst{15-12} = CRd;
4827 let Inst{11-8} = cop;
4828 let Inst{7-0} = option;
4829 let DecoderMethod = "DecodeCopMemInstruction";
4832 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4833 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4834 asm, "\t$cop, $CRd, $addr"> {
4838 let Inst{24} = 1; // P = 1
4839 let Inst{23} = addr{8};
4840 let Inst{22} = Dbit;
4841 let Inst{21} = 0; // W = 0
4842 let Inst{20} = load;
4843 let Inst{19-16} = addr{12-9};
4844 let Inst{15-12} = CRd;
4845 let Inst{11-8} = cop;
4846 let Inst{7-0} = addr{7-0};
4847 let DecoderMethod = "DecodeCopMemInstruction";
4849 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4850 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4854 let Inst{24} = 1; // P = 1
4855 let Inst{23} = addr{8};
4856 let Inst{22} = Dbit;
4857 let Inst{21} = 1; // W = 1
4858 let Inst{20} = load;
4859 let Inst{19-16} = addr{12-9};
4860 let Inst{15-12} = CRd;
4861 let Inst{11-8} = cop;
4862 let Inst{7-0} = addr{7-0};
4863 let DecoderMethod = "DecodeCopMemInstruction";
4865 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4866 postidx_imm8s4:$offset),
4867 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4872 let Inst{24} = 0; // P = 0
4873 let Inst{23} = offset{8};
4874 let Inst{22} = Dbit;
4875 let Inst{21} = 1; // W = 1
4876 let Inst{20} = load;
4877 let Inst{19-16} = addr;
4878 let Inst{15-12} = CRd;
4879 let Inst{11-8} = cop;
4880 let Inst{7-0} = offset{7-0};
4881 let DecoderMethod = "DecodeCopMemInstruction";
4883 def _OPTION : ACInoP<(outs),
4884 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4885 coproc_option_imm:$option),
4886 asm, "\t$cop, $CRd, $addr, $option"> {
4891 let Inst{24} = 0; // P = 0
4892 let Inst{23} = 1; // U = 1
4893 let Inst{22} = Dbit;
4894 let Inst{21} = 0; // W = 0
4895 let Inst{20} = load;
4896 let Inst{19-16} = addr;
4897 let Inst{15-12} = CRd;
4898 let Inst{11-8} = cop;
4899 let Inst{7-0} = option;
4900 let DecoderMethod = "DecodeCopMemInstruction";
4904 defm LDC : LdStCop <1, 0, "ldc">;
4905 defm LDCL : LdStCop <1, 1, "ldcl">;
4906 defm STC : LdStCop <0, 0, "stc">;
4907 defm STCL : LdStCop <0, 1, "stcl">;
4908 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4909 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4910 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4911 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4913 //===----------------------------------------------------------------------===//
4914 // Move between coprocessor and ARM core register.
4917 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4919 : ABI<0b1110, oops, iops, NoItinerary, opc,
4920 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4921 let Inst{20} = direction;
4931 let Inst{15-12} = Rt;
4932 let Inst{11-8} = cop;
4933 let Inst{23-21} = opc1;
4934 let Inst{7-5} = opc2;
4935 let Inst{3-0} = CRm;
4936 let Inst{19-16} = CRn;
4939 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4941 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4942 c_imm:$CRm, imm0_7:$opc2),
4943 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4944 imm:$CRm, imm:$opc2)]>,
4945 ComplexDeprecationPredicate<"MCR">;
4946 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4947 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4948 c_imm:$CRm, 0, pred:$p)>;
4949 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4950 (outs GPRwithAPSR:$Rt),
4951 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4953 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4954 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4955 c_imm:$CRm, 0, pred:$p)>;
4957 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4958 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4960 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4962 : ABXI<0b1110, oops, iops, NoItinerary,
4963 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4964 let Inst{31-24} = 0b11111110;
4965 let Inst{20} = direction;
4975 let Inst{15-12} = Rt;
4976 let Inst{11-8} = cop;
4977 let Inst{23-21} = opc1;
4978 let Inst{7-5} = opc2;
4979 let Inst{3-0} = CRm;
4980 let Inst{19-16} = CRn;
4983 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4985 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4986 c_imm:$CRm, imm0_7:$opc2),
4987 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4988 imm:$CRm, imm:$opc2)]>,
4990 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
4991 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4993 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4994 (outs GPRwithAPSR:$Rt),
4995 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4998 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
4999 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5002 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5003 imm:$CRm, imm:$opc2),
5004 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5006 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5007 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5008 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5009 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5010 let Inst{23-21} = 0b010;
5011 let Inst{20} = direction;
5019 let Inst{15-12} = Rt;
5020 let Inst{19-16} = Rt2;
5021 let Inst{11-8} = cop;
5022 let Inst{7-4} = opc1;
5023 let Inst{3-0} = CRm;
5026 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5027 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5028 GPRnopc:$Rt2, imm:$CRm)]>;
5029 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5031 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5032 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5033 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5034 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5036 let Inst{31-28} = 0b1111;
5037 let Inst{23-21} = 0b010;
5038 let Inst{20} = direction;
5046 let Inst{15-12} = Rt;
5047 let Inst{19-16} = Rt2;
5048 let Inst{11-8} = cop;
5049 let Inst{7-4} = opc1;
5050 let Inst{3-0} = CRm;
5052 let DecoderMethod = "DecodeMRRC2";
5055 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5056 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5057 GPRnopc:$Rt2, imm:$CRm)]>;
5058 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5060 //===----------------------------------------------------------------------===//
5061 // Move between special register and ARM core register
5064 // Move to ARM core register from Special Register
5065 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5066 "mrs", "\t$Rd, apsr", []> {
5068 let Inst{23-16} = 0b00001111;
5069 let Unpredictable{19-17} = 0b111;
5071 let Inst{15-12} = Rd;
5073 let Inst{11-0} = 0b000000000000;
5074 let Unpredictable{11-0} = 0b110100001111;
5077 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5080 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5081 // section B9.3.9, with the R bit set to 1.
5082 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5083 "mrs", "\t$Rd, spsr", []> {
5085 let Inst{23-16} = 0b01001111;
5086 let Unpredictable{19-16} = 0b1111;
5088 let Inst{15-12} = Rd;
5090 let Inst{11-0} = 0b000000000000;
5091 let Unpredictable{11-0} = 0b110100001111;
5094 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5095 // separate encoding (distinguished by bit 5.
5096 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5097 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5098 Requires<[IsARM, HasVirtualization]> {
5103 let Inst{22} = banked{5}; // R bit
5104 let Inst{21-20} = 0b00;
5105 let Inst{19-16} = banked{3-0};
5106 let Inst{15-12} = Rd;
5107 let Inst{11-9} = 0b001;
5108 let Inst{8} = banked{4};
5109 let Inst{7-0} = 0b00000000;
5112 // Move from ARM core register to Special Register
5114 // No need to have both system and application versions of MSR (immediate) or
5115 // MSR (register), the encodings are the same and the assembly parser has no way
5116 // to distinguish between them. The mask operand contains the special register
5117 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5118 // accessed in the special register.
5119 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5120 "msr", "\t$mask, $Rn", []> {
5125 let Inst{22} = mask{4}; // R bit
5126 let Inst{21-20} = 0b10;
5127 let Inst{19-16} = mask{3-0};
5128 let Inst{15-12} = 0b1111;
5129 let Inst{11-4} = 0b00000000;
5133 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5134 "msr", "\t$mask, $imm", []> {
5139 let Inst{22} = mask{4}; // R bit
5140 let Inst{21-20} = 0b10;
5141 let Inst{19-16} = mask{3-0};
5142 let Inst{15-12} = 0b1111;
5143 let Inst{11-0} = imm;
5146 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5147 // separate encoding (distinguished by bit 5.
5148 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5149 NoItinerary, "msr", "\t$banked, $Rn", []>,
5150 Requires<[IsARM, HasVirtualization]> {
5155 let Inst{22} = banked{5}; // R bit
5156 let Inst{21-20} = 0b10;
5157 let Inst{19-16} = banked{3-0};
5158 let Inst{15-12} = 0b1111;
5159 let Inst{11-9} = 0b001;
5160 let Inst{8} = banked{4};
5161 let Inst{7-4} = 0b0000;
5165 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5166 // are needed to probe the stack when allocating more than
5167 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5168 // ensure that the guard pages used by the OS virtual memory manager are
5169 // allocated in correct sequence.
5170 // The main point of having separate instruction are extra unmodelled effects
5171 // (compared to ordinary calls) like stack pointer change.
5173 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5174 [SDNPHasChain, SDNPSideEffect]>;
5175 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5176 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5178 //===----------------------------------------------------------------------===//
5182 // __aeabi_read_tp preserves the registers r1-r3.
5183 // This is a pseudo inst so that we can get the encoding right,
5184 // complete with fixup for the aeabi_read_tp function.
5185 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5186 // is defined in "ARMInstrThumb.td".
5188 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5189 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5190 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5193 //===----------------------------------------------------------------------===//
5194 // SJLJ Exception handling intrinsics
5195 // eh_sjlj_setjmp() is an instruction sequence to store the return
5196 // address and save #0 in R0 for the non-longjmp case.
5197 // Since by its nature we may be coming from some other function to get
5198 // here, and we're using the stack frame for the containing function to
5199 // save/restore registers, we can't keep anything live in regs across
5200 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5201 // when we get here from a longjmp(). We force everything out of registers
5202 // except for our own input by listing the relevant registers in Defs. By
5203 // doing so, we also cause the prologue/epilogue code to actively preserve
5204 // all of the callee-saved resgisters, which is exactly what we want.
5205 // A constant value is passed in $val, and we use the location as a scratch.
5207 // These are pseudo-instructions and are lowered to individual MC-insts, so
5208 // no encoding information is necessary.
5210 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5211 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5212 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5213 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5215 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5216 Requires<[IsARM, HasVFP2]>;
5220 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5221 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5222 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5224 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5225 Requires<[IsARM, NoVFP]>;
5228 // FIXME: Non-IOS version(s)
5229 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5230 Defs = [ R7, LR, SP ] in {
5231 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5233 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5237 // eh.sjlj.dispatchsetup pseudo-instruction.
5238 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5239 // the pseudo is expanded (which happens before any passes that need the
5240 // instruction size).
5241 let isBarrier = 1 in
5242 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5245 //===----------------------------------------------------------------------===//
5246 // Non-Instruction Patterns
5249 // ARMv4 indirect branch using (MOVr PC, dst)
5250 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5251 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5252 4, IIC_Br, [(brind GPR:$dst)],
5253 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5254 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5256 // Large immediate handling.
5258 // 32-bit immediate using two piece mod_imms or movw + movt.
5259 // This is a single pseudo instruction, the benefit is that it can be remat'd
5260 // as a single unit instead of having to handle reg inputs.
5261 // FIXME: Remove this when we can do generalized remat.
5262 let isReMaterializable = 1, isMoveImm = 1 in
5263 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5264 [(set GPR:$dst, (arm_i32imm:$src))]>,
5267 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5268 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5269 Requires<[IsARM, DontUseMovt]>;
5271 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5272 // It also makes it possible to rematerialize the instructions.
5273 // FIXME: Remove this when we can do generalized remat and when machine licm
5274 // can properly the instructions.
5275 let isReMaterializable = 1 in {
5276 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5278 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5279 Requires<[IsARM, UseMovt]>;
5281 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5284 (ARMWrapperPIC tglobaladdr:$addr))]>,
5285 Requires<[IsARM, DontUseMovt]>;
5287 let AddedComplexity = 10 in
5288 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5291 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5292 Requires<[IsARM, DontUseMovt]>;
5294 let AddedComplexity = 10 in
5295 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5297 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5298 Requires<[IsARM, UseMovt]>;
5299 } // isReMaterializable
5301 // ConstantPool, GlobalAddress, and JumpTable
5302 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5303 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5304 Requires<[IsARM, UseMovt]>;
5305 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5306 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5308 // TODO: add,sub,and, 3-instr forms?
5310 // Tail calls. These patterns also apply to Thumb mode.
5311 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5312 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5313 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5316 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5317 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5318 (BMOVPCB_CALL texternalsym:$func)>;
5320 // zextload i1 -> zextload i8
5321 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5322 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5324 // extload -> zextload
5325 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5326 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5327 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5328 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5330 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5332 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5333 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5336 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5337 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5338 (SMULBB GPR:$a, GPR:$b)>;
5339 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5340 (SMULBB GPR:$a, GPR:$b)>;
5341 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5342 (sra GPR:$b, (i32 16))),
5343 (SMULBT GPR:$a, GPR:$b)>;
5344 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5345 (SMULBT GPR:$a, GPR:$b)>;
5346 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5347 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5348 (SMULTB GPR:$a, GPR:$b)>;
5349 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5350 (SMULTB GPR:$a, GPR:$b)>;
5352 def : ARMV5MOPat<(add GPR:$acc,
5353 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5354 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5355 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5356 def : ARMV5MOPat<(add GPR:$acc,
5357 (mul sext_16_node:$a, sext_16_node:$b)),
5358 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5359 def : ARMV5MOPat<(add GPR:$acc,
5360 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5361 (sra GPR:$b, (i32 16)))),
5362 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5363 def : ARMV5MOPat<(add GPR:$acc,
5364 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5365 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5366 def : ARMV5MOPat<(add GPR:$acc,
5367 (mul (sra GPR:$a, (i32 16)),
5368 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5369 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5370 def : ARMV5MOPat<(add GPR:$acc,
5371 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5372 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5375 // Pre-v7 uses MCR for synchronization barriers.
5376 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5377 Requires<[IsARM, HasV6]>;
5379 // SXT/UXT with no rotate
5380 let AddedComplexity = 16 in {
5381 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5382 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5383 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5384 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5385 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5386 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5387 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5390 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5391 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5393 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5394 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5395 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5396 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5398 // Atomic load/store patterns
5399 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5400 (LDRBrs ldst_so_reg:$src)>;
5401 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5402 (LDRBi12 addrmode_imm12:$src)>;
5403 def : ARMPat<(atomic_load_16 addrmode3:$src),
5404 (LDRH addrmode3:$src)>;
5405 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5406 (LDRrs ldst_so_reg:$src)>;
5407 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5408 (LDRi12 addrmode_imm12:$src)>;
5409 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5410 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5411 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5412 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5413 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5414 (STRH GPR:$val, addrmode3:$ptr)>;
5415 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5416 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5417 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5418 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5421 //===----------------------------------------------------------------------===//
5425 include "ARMInstrThumb.td"
5427 //===----------------------------------------------------------------------===//
5431 include "ARMInstrThumb2.td"
5433 //===----------------------------------------------------------------------===//
5434 // Floating Point Support
5437 include "ARMInstrVFP.td"
5439 //===----------------------------------------------------------------------===//
5440 // Advanced SIMD (NEON) Support
5443 include "ARMInstrNEON.td"
5445 //===----------------------------------------------------------------------===//
5446 // Assembler aliases
5450 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5451 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5452 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5454 // System instructions
5455 def : MnemonicAlias<"swi", "svc">;
5457 // Load / Store Multiple
5458 def : MnemonicAlias<"ldmfd", "ldm">;
5459 def : MnemonicAlias<"ldmia", "ldm">;
5460 def : MnemonicAlias<"ldmea", "ldmdb">;
5461 def : MnemonicAlias<"stmfd", "stmdb">;
5462 def : MnemonicAlias<"stmia", "stm">;
5463 def : MnemonicAlias<"stmea", "stm">;
5465 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5466 // shift amount is zero (i.e., unspecified).
5467 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5468 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5469 Requires<[IsARM, HasV6]>;
5470 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5471 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5472 Requires<[IsARM, HasV6]>;
5474 // PUSH/POP aliases for STM/LDM
5475 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5476 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5478 // SSAT/USAT optional shift operand.
5479 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5480 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5481 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5482 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5485 // Extend instruction optional rotate operand.
5486 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5487 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5488 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5489 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5490 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5491 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5492 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5493 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5494 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5495 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5496 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5497 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5499 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5500 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5501 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5502 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5503 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5504 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5505 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5506 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5507 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5508 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5509 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5510 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5514 def : MnemonicAlias<"rfefa", "rfeda">;
5515 def : MnemonicAlias<"rfeea", "rfedb">;
5516 def : MnemonicAlias<"rfefd", "rfeia">;
5517 def : MnemonicAlias<"rfeed", "rfeib">;
5518 def : MnemonicAlias<"rfe", "rfeia">;
5521 def : MnemonicAlias<"srsfa", "srsib">;
5522 def : MnemonicAlias<"srsea", "srsia">;
5523 def : MnemonicAlias<"srsfd", "srsdb">;
5524 def : MnemonicAlias<"srsed", "srsda">;
5525 def : MnemonicAlias<"srs", "srsia">;
5528 def : MnemonicAlias<"qsubaddx", "qsax">;
5530 def : MnemonicAlias<"saddsubx", "sasx">;
5531 // SHASX == SHADDSUBX
5532 def : MnemonicAlias<"shaddsubx", "shasx">;
5533 // SHSAX == SHSUBADDX
5534 def : MnemonicAlias<"shsubaddx", "shsax">;
5536 def : MnemonicAlias<"ssubaddx", "ssax">;
5538 def : MnemonicAlias<"uaddsubx", "uasx">;
5539 // UHASX == UHADDSUBX
5540 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5541 // UHSAX == UHSUBADDX
5542 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5543 // UQASX == UQADDSUBX
5544 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5545 // UQSAX == UQSUBADDX
5546 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5548 def : MnemonicAlias<"usubaddx", "usax">;
5550 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5552 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5553 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5554 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5555 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5556 // Same for AND <--> BIC
5557 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5558 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5559 pred:$p, cc_out:$s)>;
5560 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5561 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5562 pred:$p, cc_out:$s)>;
5563 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5564 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5565 pred:$p, cc_out:$s)>;
5566 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5567 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5568 pred:$p, cc_out:$s)>;
5570 // Likewise, "add Rd, mod_imm_neg" -> sub
5571 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5572 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5573 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5574 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5575 // Same for CMP <--> CMN via mod_imm_neg
5576 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5577 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5578 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5579 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5581 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5582 // LSR, ROR, and RRX instructions.
5583 // FIXME: We need C++ parser hooks to map the alias to the MOV
5584 // encoding. It seems we should be able to do that sort of thing
5585 // in tblgen, but it could get ugly.
5586 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5587 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5588 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5590 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5591 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5593 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5594 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5596 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5597 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5600 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5601 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5602 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5603 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5604 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5606 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5607 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5609 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5610 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5612 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5613 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5617 // "neg" is and alias for "rsb rd, rn, #0"
5618 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5619 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5621 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5622 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5623 Requires<[IsARM, NoV6]>;
5625 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5626 // the instruction definitions need difference constraints pre-v6.
5627 // Use these aliases for the assembly parsing on pre-v6.
5628 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5629 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5630 Requires<[IsARM, NoV6]>;
5631 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5632 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5633 pred:$p, cc_out:$s)>,
5634 Requires<[IsARM, NoV6]>;
5635 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5636 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5637 Requires<[IsARM, NoV6]>;
5638 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5639 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5640 Requires<[IsARM, NoV6]>;
5641 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5642 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5643 Requires<[IsARM, NoV6]>;
5644 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5645 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5646 Requires<[IsARM, NoV6]>;
5648 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5650 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5651 ComplexDeprecationPredicate<"IT">;
5653 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5654 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5656 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;