1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsMClass : Predicate<"Subtarget->isMClass()">,
209 AssemblerPredicate<"FeatureMClass">;
210 def IsARClass : Predicate<"!Subtarget->isMClass()">,
211 AssemblerPredicate<"!FeatureMClass">;
212 def IsARM : Predicate<"!Subtarget->isThumb()">,
213 AssemblerPredicate<"!ModeThumb">;
214 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
215 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
216 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
217 AssemblerPredicate<"ModeNaCl">;
219 // FIXME: Eventually this will be just "hasV6T2Ops".
220 def UseMovt : Predicate<"Subtarget->useMovt()">;
221 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
222 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
224 //===----------------------------------------------------------------------===//
225 // ARM Flag Definitions.
227 class RegConstraint<string C> {
228 string Constraints = C;
231 //===----------------------------------------------------------------------===//
232 // ARM specific transformation functions and pattern fragments.
235 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_neg def below.
237 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
241 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
242 // so_imm_not def below.
243 def so_imm_not_XFORM : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
247 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
248 def imm1_15 : ImmLeaf<i32, [{
249 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
252 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
253 def imm16_31 : ImmLeaf<i32, [{
254 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
259 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
260 }], so_imm_neg_XFORM>;
264 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
265 }], so_imm_not_XFORM>;
267 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
268 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
269 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
272 /// Split a 32-bit immediate into two 16 bit parts.
273 def hi16 : SDNodeXForm<imm, [{
274 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
277 def lo16AllZero : PatLeaf<(i32 imm), [{
278 // Returns true if all low 16-bits are 0.
279 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
282 /// imm0_65535 - An immediate is in the range [0.65535].
283 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
284 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
285 return Imm >= 0 && Imm < 65536;
287 let ParserMatchClass = Imm0_65535AsmOperand;
290 class BinOpWithFlagFrag<dag res> :
291 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
292 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
293 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
295 // An 'and' node with a single use.
296 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
297 return N->hasOneUse();
300 // An 'xor' node with a single use.
301 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
302 return N->hasOneUse();
305 // An 'fmul' node with a single use.
306 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
307 return N->hasOneUse();
310 // An 'fadd' node which checks for single non-hazardous use.
311 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
312 return hasNoVMLxHazardUse(N);
315 // An 'fsub' node which checks for single non-hazardous use.
316 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
317 return hasNoVMLxHazardUse(N);
320 //===----------------------------------------------------------------------===//
321 // Operand Definitions.
325 // FIXME: rename brtarget to t2_brtarget
326 def brtarget : Operand<OtherVT> {
327 let EncoderMethod = "getBranchTargetOpValue";
328 let OperandType = "OPERAND_PCREL";
329 let DecoderMethod = "DecodeT2BROperand";
332 // FIXME: get rid of this one?
333 def uncondbrtarget : Operand<OtherVT> {
334 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
335 let OperandType = "OPERAND_PCREL";
338 // Branch target for ARM. Handles conditional/unconditional
339 def br_target : Operand<OtherVT> {
340 let EncoderMethod = "getARMBranchTargetOpValue";
341 let OperandType = "OPERAND_PCREL";
345 // FIXME: rename bltarget to t2_bl_target?
346 def bltarget : Operand<i32> {
347 // Encoded the same as branch targets.
348 let EncoderMethod = "getBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
352 // Call target for ARM. Handles conditional/unconditional
353 // FIXME: rename bl_target to t2_bltarget?
354 def bl_target : Operand<i32> {
355 // Encoded the same as branch targets.
356 let EncoderMethod = "getARMBranchTargetOpValue";
357 let OperandType = "OPERAND_PCREL";
360 def blx_target : Operand<i32> {
361 // Encoded the same as branch targets.
362 let EncoderMethod = "getARMBLXTargetOpValue";
363 let OperandType = "OPERAND_PCREL";
366 // A list of registers separated by comma. Used by load/store multiple.
367 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
368 def reglist : Operand<i32> {
369 let EncoderMethod = "getRegisterListOpValue";
370 let ParserMatchClass = RegListAsmOperand;
371 let PrintMethod = "printRegisterList";
372 let DecoderMethod = "DecodeRegListOperand";
375 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
376 def dpr_reglist : Operand<i32> {
377 let EncoderMethod = "getRegisterListOpValue";
378 let ParserMatchClass = DPRRegListAsmOperand;
379 let PrintMethod = "printRegisterList";
380 let DecoderMethod = "DecodeDPRRegListOperand";
383 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
384 def spr_reglist : Operand<i32> {
385 let EncoderMethod = "getRegisterListOpValue";
386 let ParserMatchClass = SPRRegListAsmOperand;
387 let PrintMethod = "printRegisterList";
388 let DecoderMethod = "DecodeSPRRegListOperand";
391 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
392 def cpinst_operand : Operand<i32> {
393 let PrintMethod = "printCPInstOperand";
397 def pclabel : Operand<i32> {
398 let PrintMethod = "printPCLabel";
401 // ADR instruction labels.
402 def adrlabel : Operand<i32> {
403 let EncoderMethod = "getAdrLabelOpValue";
406 def neon_vcvt_imm32 : Operand<i32> {
407 let EncoderMethod = "getNEONVcvtImm32OpValue";
408 let DecoderMethod = "DecodeVCVTImmOperand";
411 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
412 def rot_imm_XFORM: SDNodeXForm<imm, [{
413 switch (N->getZExtValue()){
415 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
416 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
417 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
418 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
421 def RotImmAsmOperand : AsmOperandClass {
423 let ParserMethod = "parseRotImm";
425 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
426 int32_t v = N->getZExtValue();
427 return v == 8 || v == 16 || v == 24; }],
429 let PrintMethod = "printRotImmOperand";
430 let ParserMatchClass = RotImmAsmOperand;
433 // shift_imm: An integer that encodes a shift amount and the type of shift
434 // (asr or lsl). The 6-bit immediate encodes as:
437 // {4-0} imm5 shift amount.
438 // asr #32 encoded as imm5 == 0.
439 def ShifterImmAsmOperand : AsmOperandClass {
440 let Name = "ShifterImm";
441 let ParserMethod = "parseShifterImm";
443 def shift_imm : Operand<i32> {
444 let PrintMethod = "printShiftImmOperand";
445 let ParserMatchClass = ShifterImmAsmOperand;
448 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
449 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
450 def so_reg_reg : Operand<i32>, // reg reg imm
451 ComplexPattern<i32, 3, "SelectRegShifterOperand",
452 [shl, srl, sra, rotr]> {
453 let EncoderMethod = "getSORegRegOpValue";
454 let PrintMethod = "printSORegRegOperand";
455 let DecoderMethod = "DecodeSORegRegOperand";
456 let ParserMatchClass = ShiftedRegAsmOperand;
457 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
460 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
461 def so_reg_imm : Operand<i32>, // reg imm
462 ComplexPattern<i32, 2, "SelectImmShifterOperand",
463 [shl, srl, sra, rotr]> {
464 let EncoderMethod = "getSORegImmOpValue";
465 let PrintMethod = "printSORegImmOperand";
466 let DecoderMethod = "DecodeSORegImmOperand";
467 let ParserMatchClass = ShiftedImmAsmOperand;
468 let MIOperandInfo = (ops GPR, i32imm);
471 // FIXME: Does this need to be distinct from so_reg?
472 def shift_so_reg_reg : Operand<i32>, // reg reg imm
473 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
474 [shl,srl,sra,rotr]> {
475 let EncoderMethod = "getSORegRegOpValue";
476 let PrintMethod = "printSORegRegOperand";
477 let DecoderMethod = "DecodeSORegRegOperand";
478 let MIOperandInfo = (ops GPR, GPR, i32imm);
481 // FIXME: Does this need to be distinct from so_reg?
482 def shift_so_reg_imm : Operand<i32>, // reg reg imm
483 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
484 [shl,srl,sra,rotr]> {
485 let EncoderMethod = "getSORegImmOpValue";
486 let PrintMethod = "printSORegImmOperand";
487 let DecoderMethod = "DecodeSORegImmOperand";
488 let MIOperandInfo = (ops GPR, i32imm);
492 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
493 // 8-bit immediate rotated by an arbitrary number of bits.
494 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
495 def so_imm : Operand<i32>, ImmLeaf<i32, [{
496 return ARM_AM::getSOImmVal(Imm) != -1;
498 let EncoderMethod = "getSOImmOpValue";
499 let ParserMatchClass = SOImmAsmOperand;
500 let DecoderMethod = "DecodeSOImmOperand";
503 // Break so_imm's up into two pieces. This handles immediates with up to 16
504 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
505 // get the first/second pieces.
506 def so_imm2part : PatLeaf<(imm), [{
507 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
510 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
512 def arm_i32imm : PatLeaf<(imm), [{
513 if (Subtarget->hasV6T2Ops())
515 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
518 /// imm0_7 predicate - Immediate in the range [0,7].
519 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
520 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
521 return Imm >= 0 && Imm < 8;
523 let ParserMatchClass = Imm0_7AsmOperand;
526 /// imm0_15 predicate - Immediate in the range [0,15].
527 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
528 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
529 return Imm >= 0 && Imm < 16;
531 let ParserMatchClass = Imm0_15AsmOperand;
534 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
535 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
536 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
537 return Imm >= 0 && Imm < 32;
539 let ParserMatchClass = Imm0_31AsmOperand;
542 /// imm0_255 predicate - Immediate in the range [0,255].
543 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
544 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
545 let ParserMatchClass = Imm0_255AsmOperand;
548 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
549 // a relocatable expression.
551 // FIXME: This really needs a Thumb version separate from the ARM version.
552 // While the range is the same, and can thus use the same match class,
553 // the encoding is different so it should have a different encoder method.
554 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
555 def imm0_65535_expr : Operand<i32> {
556 let EncoderMethod = "getHiLo16ImmOpValue";
557 let ParserMatchClass = Imm0_65535ExprAsmOperand;
560 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
561 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
562 def imm24b : Operand<i32>, ImmLeaf<i32, [{
563 return Imm >= 0 && Imm <= 0xffffff;
565 let ParserMatchClass = Imm24bitAsmOperand;
569 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
571 def BitfieldAsmOperand : AsmOperandClass {
572 let Name = "Bitfield";
573 let ParserMethod = "parseBitfield";
575 def bf_inv_mask_imm : Operand<i32>,
577 return ARM::isBitFieldInvertedMask(N->getZExtValue());
579 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
580 let PrintMethod = "printBitfieldInvMaskImmOperand";
581 let DecoderMethod = "DecodeBitfieldMaskOperand";
582 let ParserMatchClass = BitfieldAsmOperand;
585 def imm1_32_XFORM: SDNodeXForm<imm, [{
586 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
588 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
589 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
590 uint64_t Imm = N->getZExtValue();
591 return Imm > 0 && Imm <= 32;
594 let PrintMethod = "printImmPlusOneOperand";
595 let ParserMatchClass = Imm1_32AsmOperand;
598 def imm1_16_XFORM: SDNodeXForm<imm, [{
599 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
601 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
602 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
604 let PrintMethod = "printImmPlusOneOperand";
605 let ParserMatchClass = Imm1_16AsmOperand;
608 // Define ARM specific addressing modes.
609 // addrmode_imm12 := reg +/- imm12
611 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
612 def addrmode_imm12 : Operand<i32>,
613 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
614 // 12-bit immediate operand. Note that instructions using this encode
615 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
616 // immediate values are as normal.
618 let EncoderMethod = "getAddrModeImm12OpValue";
619 let PrintMethod = "printAddrModeImm12Operand";
620 let DecoderMethod = "DecodeAddrModeImm12Operand";
621 let ParserMatchClass = MemImm12OffsetAsmOperand;
622 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
624 // ldst_so_reg := reg +/- reg shop imm
626 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
627 def ldst_so_reg : Operand<i32>,
628 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
629 let EncoderMethod = "getLdStSORegOpValue";
630 // FIXME: Simplify the printer
631 let PrintMethod = "printAddrMode2Operand";
632 let DecoderMethod = "DecodeSORegMemOperand";
633 let ParserMatchClass = MemRegOffsetAsmOperand;
634 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
637 // postidx_imm8 := +/- [0,255]
640 // {8} 1 is imm8 is non-negative. 0 otherwise.
641 // {7-0} [0,255] imm8 value.
642 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
643 def postidx_imm8 : Operand<i32> {
644 let PrintMethod = "printPostIdxImm8Operand";
645 let ParserMatchClass = PostIdxImm8AsmOperand;
646 let MIOperandInfo = (ops i32imm);
649 // postidx_imm8s4 := +/- [0,1020]
652 // {8} 1 is imm8 is non-negative. 0 otherwise.
653 // {7-0} [0,255] imm8 value, scaled by 4.
654 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
655 def postidx_imm8s4 : Operand<i32> {
656 let PrintMethod = "printPostIdxImm8s4Operand";
657 let ParserMatchClass = PostIdxImm8s4AsmOperand;
658 let MIOperandInfo = (ops i32imm);
662 // postidx_reg := +/- reg
664 def PostIdxRegAsmOperand : AsmOperandClass {
665 let Name = "PostIdxReg";
666 let ParserMethod = "parsePostIdxReg";
668 def postidx_reg : Operand<i32> {
669 let EncoderMethod = "getPostIdxRegOpValue";
670 let DecoderMethod = "DecodePostIdxReg";
671 let PrintMethod = "printPostIdxRegOperand";
672 let ParserMatchClass = PostIdxRegAsmOperand;
673 let MIOperandInfo = (ops GPR, i32imm);
677 // addrmode2 := reg +/- imm12
678 // := reg +/- reg shop imm
680 // FIXME: addrmode2 should be refactored the rest of the way to always
681 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
682 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
683 def addrmode2 : Operand<i32>,
684 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
685 let EncoderMethod = "getAddrMode2OpValue";
686 let PrintMethod = "printAddrMode2Operand";
687 let ParserMatchClass = AddrMode2AsmOperand;
688 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
691 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
692 let Name = "PostIdxRegShifted";
693 let ParserMethod = "parsePostIdxReg";
695 def am2offset_reg : Operand<i32>,
696 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
697 [], [SDNPWantRoot]> {
698 let EncoderMethod = "getAddrMode2OffsetOpValue";
699 let PrintMethod = "printAddrMode2OffsetOperand";
700 // When using this for assembly, it's always as a post-index offset.
701 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
702 let MIOperandInfo = (ops GPR, i32imm);
705 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
706 // the GPR is purely vestigal at this point.
707 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
708 def am2offset_imm : Operand<i32>,
709 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
710 [], [SDNPWantRoot]> {
711 let EncoderMethod = "getAddrMode2OffsetOpValue";
712 let PrintMethod = "printAddrMode2OffsetOperand";
713 let ParserMatchClass = AM2OffsetImmAsmOperand;
714 let MIOperandInfo = (ops GPR, i32imm);
718 // addrmode3 := reg +/- reg
719 // addrmode3 := reg +/- imm8
721 // FIXME: split into imm vs. reg versions.
722 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
723 def addrmode3 : Operand<i32>,
724 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
725 let EncoderMethod = "getAddrMode3OpValue";
726 let PrintMethod = "printAddrMode3Operand";
727 let ParserMatchClass = AddrMode3AsmOperand;
728 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
731 // FIXME: split into imm vs. reg versions.
732 // FIXME: parser method to handle +/- register.
733 def AM3OffsetAsmOperand : AsmOperandClass {
734 let Name = "AM3Offset";
735 let ParserMethod = "parseAM3Offset";
737 def am3offset : Operand<i32>,
738 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
739 [], [SDNPWantRoot]> {
740 let EncoderMethod = "getAddrMode3OffsetOpValue";
741 let PrintMethod = "printAddrMode3OffsetOperand";
742 let ParserMatchClass = AM3OffsetAsmOperand;
743 let MIOperandInfo = (ops GPR, i32imm);
746 // ldstm_mode := {ia, ib, da, db}
748 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
749 let EncoderMethod = "getLdStmModeOpValue";
750 let PrintMethod = "printLdStmModeOperand";
753 // addrmode5 := reg +/- imm8*4
755 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
756 def addrmode5 : Operand<i32>,
757 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
758 let PrintMethod = "printAddrMode5Operand";
759 let EncoderMethod = "getAddrMode5OpValue";
760 let DecoderMethod = "DecodeAddrMode5Operand";
761 let ParserMatchClass = AddrMode5AsmOperand;
762 let MIOperandInfo = (ops GPR:$base, i32imm);
765 // addrmode6 := reg with optional alignment
767 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
768 def addrmode6 : Operand<i32>,
769 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
770 let PrintMethod = "printAddrMode6Operand";
771 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
772 let EncoderMethod = "getAddrMode6AddressOpValue";
773 let DecoderMethod = "DecodeAddrMode6Operand";
774 let ParserMatchClass = AddrMode6AsmOperand;
777 def am6offset : Operand<i32>,
778 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
779 [], [SDNPWantRoot]> {
780 let PrintMethod = "printAddrMode6OffsetOperand";
781 let MIOperandInfo = (ops GPR);
782 let EncoderMethod = "getAddrMode6OffsetOpValue";
783 let DecoderMethod = "DecodeGPRRegisterClass";
786 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
787 // (single element from one lane) for size 32.
788 def addrmode6oneL32 : Operand<i32>,
789 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
790 let PrintMethod = "printAddrMode6Operand";
791 let MIOperandInfo = (ops GPR:$addr, i32imm);
792 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
795 // Special version of addrmode6 to handle alignment encoding for VLD-dup
796 // instructions, specifically VLD4-dup.
797 def addrmode6dup : Operand<i32>,
798 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
799 let PrintMethod = "printAddrMode6Operand";
800 let MIOperandInfo = (ops GPR:$addr, i32imm);
801 let EncoderMethod = "getAddrMode6DupAddressOpValue";
804 // addrmodepc := pc + reg
806 def addrmodepc : Operand<i32>,
807 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
808 let PrintMethod = "printAddrModePCOperand";
809 let MIOperandInfo = (ops GPR, i32imm);
812 // addr_offset_none := reg
814 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
815 def addr_offset_none : Operand<i32>,
816 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
817 let PrintMethod = "printAddrMode7Operand";
818 let DecoderMethod = "DecodeAddrMode7Operand";
819 let ParserMatchClass = MemNoOffsetAsmOperand;
820 let MIOperandInfo = (ops GPR:$base);
823 def nohash_imm : Operand<i32> {
824 let PrintMethod = "printNoHashImmediate";
827 def CoprocNumAsmOperand : AsmOperandClass {
828 let Name = "CoprocNum";
829 let ParserMethod = "parseCoprocNumOperand";
831 def p_imm : Operand<i32> {
832 let PrintMethod = "printPImmediate";
833 let ParserMatchClass = CoprocNumAsmOperand;
834 let DecoderMethod = "DecodeCoprocessor";
837 def CoprocRegAsmOperand : AsmOperandClass {
838 let Name = "CoprocReg";
839 let ParserMethod = "parseCoprocRegOperand";
841 def c_imm : Operand<i32> {
842 let PrintMethod = "printCImmediate";
843 let ParserMatchClass = CoprocRegAsmOperand;
846 //===----------------------------------------------------------------------===//
848 include "ARMInstrFormats.td"
850 //===----------------------------------------------------------------------===//
851 // Multiclass helpers...
854 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
855 /// binop that produces a value.
856 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
857 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
858 PatFrag opnode, string baseOpc, bit Commutable = 0> {
859 // The register-immediate version is re-materializable. This is useful
860 // in particular for taking the address of a local.
861 let isReMaterializable = 1 in {
862 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
863 iii, opc, "\t$Rd, $Rn, $imm",
864 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
869 let Inst{19-16} = Rn;
870 let Inst{15-12} = Rd;
871 let Inst{11-0} = imm;
874 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
875 iir, opc, "\t$Rd, $Rn, $Rm",
876 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
881 let isCommutable = Commutable;
882 let Inst{19-16} = Rn;
883 let Inst{15-12} = Rd;
884 let Inst{11-4} = 0b00000000;
888 def rsi : AsI1<opcod, (outs GPR:$Rd),
889 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
890 iis, opc, "\t$Rd, $Rn, $shift",
891 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
896 let Inst{19-16} = Rn;
897 let Inst{15-12} = Rd;
898 let Inst{11-5} = shift{11-5};
900 let Inst{3-0} = shift{3-0};
903 def rsr : AsI1<opcod, (outs GPR:$Rd),
904 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
905 iis, opc, "\t$Rd, $Rn, $shift",
906 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
911 let Inst{19-16} = Rn;
912 let Inst{15-12} = Rd;
913 let Inst{11-8} = shift{11-8};
915 let Inst{6-5} = shift{6-5};
917 let Inst{3-0} = shift{3-0};
920 // Assembly aliases for optional destination operand when it's the same
921 // as the source operand.
922 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
923 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
924 so_imm:$imm, pred:$p,
927 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
928 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
932 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
933 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
934 so_reg_imm:$shift, pred:$p,
937 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
938 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
939 so_reg_reg:$shift, pred:$p,
945 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
946 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
947 /// it is equivalent to the AsI1_bin_irs counterpart.
948 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
949 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
950 PatFrag opnode, string baseOpc, bit Commutable = 0> {
951 // The register-immediate version is re-materializable. This is useful
952 // in particular for taking the address of a local.
953 let isReMaterializable = 1 in {
954 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
955 iii, opc, "\t$Rd, $Rn, $imm",
956 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
961 let Inst{19-16} = Rn;
962 let Inst{15-12} = Rd;
963 let Inst{11-0} = imm;
966 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
967 iir, opc, "\t$Rd, $Rn, $Rm",
968 [/* pattern left blank */]> {
972 let Inst{11-4} = 0b00000000;
975 let Inst{15-12} = Rd;
976 let Inst{19-16} = Rn;
979 def rsi : AsI1<opcod, (outs GPR:$Rd),
980 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
981 iis, opc, "\t$Rd, $Rn, $shift",
982 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
987 let Inst{19-16} = Rn;
988 let Inst{15-12} = Rd;
989 let Inst{11-5} = shift{11-5};
991 let Inst{3-0} = shift{3-0};
994 def rsr : AsI1<opcod, (outs GPR:$Rd),
995 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
996 iis, opc, "\t$Rd, $Rn, $shift",
997 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1002 let Inst{19-16} = Rn;
1003 let Inst{15-12} = Rd;
1004 let Inst{11-8} = shift{11-8};
1006 let Inst{6-5} = shift{6-5};
1008 let Inst{3-0} = shift{3-0};
1011 // Assembly aliases for optional destination operand when it's the same
1012 // as the source operand.
1013 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1014 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1015 so_imm:$imm, pred:$p,
1018 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1019 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1023 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1024 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1025 so_reg_imm:$shift, pred:$p,
1028 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1029 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1030 so_reg_reg:$shift, pred:$p,
1036 /// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
1038 /// These opcodes will be converted to the real non-S opcodes by
1039 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1040 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
1041 multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
1042 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1043 PatFrag opnode, bit Commutable = 0> {
1044 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1045 iii, opc, "\t$Rd, $Rn, $imm",
1046 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1048 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1049 iir, opc, "\t$Rd, $Rn, $Rm",
1050 [/* pattern left blank */]>;
1052 def rsi : AsI1<opcod, (outs GPR:$Rd),
1053 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1054 iis, opc, "\t$Rd, $Rn, $shift",
1055 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]>;
1057 def rsr : AsI1<opcod, (outs GPR:$Rd),
1058 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1059 iis, opc, "\t$Rd, $Rn, $shift",
1060 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1065 let Inst{19-16} = Rn;
1066 let Inst{15-12} = Rd;
1067 let Inst{11-8} = shift{11-8};
1069 let Inst{6-5} = shift{6-5};
1071 let Inst{3-0} = shift{3-0};
1076 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1078 /// These opcodes will be converted to the real non-S opcodes by
1079 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1080 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
1081 multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
1082 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1083 PatFrag opnode, bit Commutable = 0> {
1084 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1085 iii, opc, "\t$Rd, $Rn, $imm",
1086 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1087 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1088 iir, opc, "\t$Rd, $Rn, $Rm",
1089 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>;
1090 def rsi : AsI1<opcod, (outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1092 iis, opc, "\t$Rd, $Rn, $shift",
1093 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
1095 def rsr : AsI1<opcod, (outs GPR:$Rd),
1096 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1097 iis, opc, "\t$Rd, $Rn, $shift",
1098 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
1102 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1103 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1104 /// a explicit result, only implicitly set CPSR.
1105 let isCompare = 1, Defs = [CPSR] in {
1106 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1107 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1108 PatFrag opnode, bit Commutable = 0> {
1109 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1111 [(opnode GPR:$Rn, so_imm:$imm)]> {
1116 let Inst{19-16} = Rn;
1117 let Inst{15-12} = 0b0000;
1118 let Inst{11-0} = imm;
1120 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1122 [(opnode GPR:$Rn, GPR:$Rm)]> {
1125 let isCommutable = Commutable;
1128 let Inst{19-16} = Rn;
1129 let Inst{15-12} = 0b0000;
1130 let Inst{11-4} = 0b00000000;
1133 def rsi : AI1<opcod, (outs),
1134 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1135 opc, "\t$Rn, $shift",
1136 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1141 let Inst{19-16} = Rn;
1142 let Inst{15-12} = 0b0000;
1143 let Inst{11-5} = shift{11-5};
1145 let Inst{3-0} = shift{3-0};
1147 def rsr : AI1<opcod, (outs),
1148 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1149 opc, "\t$Rn, $shift",
1150 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1155 let Inst{19-16} = Rn;
1156 let Inst{15-12} = 0b0000;
1157 let Inst{11-8} = shift{11-8};
1159 let Inst{6-5} = shift{6-5};
1161 let Inst{3-0} = shift{3-0};
1167 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1168 /// register and one whose operand is a register rotated by 8/16/24.
1169 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1170 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1171 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1172 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1173 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1174 Requires<[IsARM, HasV6]> {
1178 let Inst{19-16} = 0b1111;
1179 let Inst{15-12} = Rd;
1180 let Inst{11-10} = rot;
1184 class AI_ext_rrot_np<bits<8> opcod, string opc>
1185 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1186 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1187 Requires<[IsARM, HasV6]> {
1189 let Inst{19-16} = 0b1111;
1190 let Inst{11-10} = rot;
1193 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1194 /// register and one whose operand is a register rotated by 8/16/24.
1195 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1196 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1197 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1198 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1199 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1200 Requires<[IsARM, HasV6]> {
1205 let Inst{19-16} = Rn;
1206 let Inst{15-12} = Rd;
1207 let Inst{11-10} = rot;
1208 let Inst{9-4} = 0b000111;
1212 class AI_exta_rrot_np<bits<8> opcod, string opc>
1213 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1214 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1215 Requires<[IsARM, HasV6]> {
1218 let Inst{19-16} = Rn;
1219 let Inst{11-10} = rot;
1222 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1223 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1224 string baseOpc, bit Commutable = 0> {
1225 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1226 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1227 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1228 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1234 let Inst{15-12} = Rd;
1235 let Inst{19-16} = Rn;
1236 let Inst{11-0} = imm;
1238 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1239 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1240 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1245 let Inst{11-4} = 0b00000000;
1247 let isCommutable = Commutable;
1249 let Inst{15-12} = Rd;
1250 let Inst{19-16} = Rn;
1252 def rsi : AsI1<opcod, (outs GPR:$Rd),
1253 (ins GPR:$Rn, so_reg_imm:$shift),
1254 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1255 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1261 let Inst{19-16} = Rn;
1262 let Inst{15-12} = Rd;
1263 let Inst{11-5} = shift{11-5};
1265 let Inst{3-0} = shift{3-0};
1267 def rsr : AsI1<opcod, (outs GPR:$Rd),
1268 (ins GPR:$Rn, so_reg_reg:$shift),
1269 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1270 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1276 let Inst{19-16} = Rn;
1277 let Inst{15-12} = Rd;
1278 let Inst{11-8} = shift{11-8};
1280 let Inst{6-5} = shift{6-5};
1282 let Inst{3-0} = shift{3-0};
1286 // Assembly aliases for optional destination operand when it's the same
1287 // as the source operand.
1288 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1289 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1290 so_imm:$imm, pred:$p,
1293 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1294 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1298 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1299 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1300 so_reg_imm:$shift, pred:$p,
1303 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1304 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1305 so_reg_reg:$shift, pred:$p,
1310 /// AI1_rsc_irs - Define instructions and patterns for rsc
1311 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1313 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1314 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1315 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1316 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1322 let Inst{15-12} = Rd;
1323 let Inst{19-16} = Rn;
1324 let Inst{11-0} = imm;
1326 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1327 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1328 [/* pattern left blank */]> {
1332 let Inst{11-4} = 0b00000000;
1335 let Inst{15-12} = Rd;
1336 let Inst{19-16} = Rn;
1338 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1339 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1340 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1346 let Inst{19-16} = Rn;
1347 let Inst{15-12} = Rd;
1348 let Inst{11-5} = shift{11-5};
1350 let Inst{3-0} = shift{3-0};
1352 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1353 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1354 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1360 let Inst{19-16} = Rn;
1361 let Inst{15-12} = Rd;
1362 let Inst{11-8} = shift{11-8};
1364 let Inst{6-5} = shift{6-5};
1366 let Inst{3-0} = shift{3-0};
1370 // Assembly aliases for optional destination operand when it's the same
1371 // as the source operand.
1372 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1373 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1374 so_imm:$imm, pred:$p,
1377 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1378 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1382 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1383 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1384 so_reg_imm:$shift, pred:$p,
1387 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1388 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1389 so_reg_reg:$shift, pred:$p,
1394 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1395 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1396 InstrItinClass iir, PatFrag opnode> {
1397 // Note: We use the complex addrmode_imm12 rather than just an input
1398 // GPR and a constrained immediate so that we can use this to match
1399 // frame index references and avoid matching constant pool references.
1400 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1401 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1402 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1405 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1406 let Inst{19-16} = addr{16-13}; // Rn
1407 let Inst{15-12} = Rt;
1408 let Inst{11-0} = addr{11-0}; // imm12
1410 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1411 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1412 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1415 let shift{4} = 0; // Inst{4} = 0
1416 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1417 let Inst{19-16} = shift{16-13}; // Rn
1418 let Inst{15-12} = Rt;
1419 let Inst{11-0} = shift{11-0};
1424 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1425 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1426 InstrItinClass iir, PatFrag opnode> {
1427 // Note: We use the complex addrmode_imm12 rather than just an input
1428 // GPR and a constrained immediate so that we can use this to match
1429 // frame index references and avoid matching constant pool references.
1430 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1431 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1432 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1435 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1436 let Inst{19-16} = addr{16-13}; // Rn
1437 let Inst{15-12} = Rt;
1438 let Inst{11-0} = addr{11-0}; // imm12
1440 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1441 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1442 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1445 let shift{4} = 0; // Inst{4} = 0
1446 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1447 let Inst{19-16} = shift{16-13}; // Rn
1448 let Inst{15-12} = Rt;
1449 let Inst{11-0} = shift{11-0};
1455 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1456 InstrItinClass iir, PatFrag opnode> {
1457 // Note: We use the complex addrmode_imm12 rather than just an input
1458 // GPR and a constrained immediate so that we can use this to match
1459 // frame index references and avoid matching constant pool references.
1460 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1461 (ins GPR:$Rt, addrmode_imm12:$addr),
1462 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1463 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1466 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1467 let Inst{19-16} = addr{16-13}; // Rn
1468 let Inst{15-12} = Rt;
1469 let Inst{11-0} = addr{11-0}; // imm12
1471 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1472 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1473 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1476 let shift{4} = 0; // Inst{4} = 0
1477 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1478 let Inst{19-16} = shift{16-13}; // Rn
1479 let Inst{15-12} = Rt;
1480 let Inst{11-0} = shift{11-0};
1484 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1485 InstrItinClass iir, PatFrag opnode> {
1486 // Note: We use the complex addrmode_imm12 rather than just an input
1487 // GPR and a constrained immediate so that we can use this to match
1488 // frame index references and avoid matching constant pool references.
1489 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1490 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1491 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1492 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1495 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1496 let Inst{19-16} = addr{16-13}; // Rn
1497 let Inst{15-12} = Rt;
1498 let Inst{11-0} = addr{11-0}; // imm12
1500 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1501 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1502 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1505 let shift{4} = 0; // Inst{4} = 0
1506 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1507 let Inst{19-16} = shift{16-13}; // Rn
1508 let Inst{15-12} = Rt;
1509 let Inst{11-0} = shift{11-0};
1514 //===----------------------------------------------------------------------===//
1516 //===----------------------------------------------------------------------===//
1518 //===----------------------------------------------------------------------===//
1519 // Miscellaneous Instructions.
1522 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1523 /// the function. The first operand is the ID# for this instruction, the second
1524 /// is the index into the MachineConstantPool that this is, the third is the
1525 /// size in bytes of this constant pool entry.
1526 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1527 def CONSTPOOL_ENTRY :
1528 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1529 i32imm:$size), NoItinerary, []>;
1531 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1532 // from removing one half of the matched pairs. That breaks PEI, which assumes
1533 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1534 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1535 def ADJCALLSTACKUP :
1536 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1537 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1539 def ADJCALLSTACKDOWN :
1540 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1541 [(ARMcallseq_start timm:$amt)]>;
1544 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1545 // (These psuedos use a hand-written selection code).
1546 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1547 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1548 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1550 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1551 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1553 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1554 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1556 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1557 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1559 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1560 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1562 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1563 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1565 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1566 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1568 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1569 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1570 GPR:$set1, GPR:$set2),
1574 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1575 Requires<[IsARM, HasV6T2]> {
1576 let Inst{27-16} = 0b001100100000;
1577 let Inst{15-8} = 0b11110000;
1578 let Inst{7-0} = 0b00000000;
1581 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1582 Requires<[IsARM, HasV6T2]> {
1583 let Inst{27-16} = 0b001100100000;
1584 let Inst{15-8} = 0b11110000;
1585 let Inst{7-0} = 0b00000001;
1588 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1589 Requires<[IsARM, HasV6T2]> {
1590 let Inst{27-16} = 0b001100100000;
1591 let Inst{15-8} = 0b11110000;
1592 let Inst{7-0} = 0b00000010;
1595 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1596 Requires<[IsARM, HasV6T2]> {
1597 let Inst{27-16} = 0b001100100000;
1598 let Inst{15-8} = 0b11110000;
1599 let Inst{7-0} = 0b00000011;
1602 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1603 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1608 let Inst{15-12} = Rd;
1609 let Inst{19-16} = Rn;
1610 let Inst{27-20} = 0b01101000;
1611 let Inst{7-4} = 0b1011;
1612 let Inst{11-8} = 0b1111;
1615 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1616 []>, Requires<[IsARM, HasV6T2]> {
1617 let Inst{27-16} = 0b001100100000;
1618 let Inst{15-8} = 0b11110000;
1619 let Inst{7-0} = 0b00000100;
1622 // The i32imm operand $val can be used by a debugger to store more information
1623 // about the breakpoint.
1624 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1625 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1627 let Inst{3-0} = val{3-0};
1628 let Inst{19-8} = val{15-4};
1629 let Inst{27-20} = 0b00010010;
1630 let Inst{7-4} = 0b0111;
1633 // Change Processor State
1634 // FIXME: We should use InstAlias to handle the optional operands.
1635 class CPS<dag iops, string asm_ops>
1636 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1637 []>, Requires<[IsARM]> {
1643 let Inst{31-28} = 0b1111;
1644 let Inst{27-20} = 0b00010000;
1645 let Inst{19-18} = imod;
1646 let Inst{17} = M; // Enabled if mode is set;
1648 let Inst{8-6} = iflags;
1650 let Inst{4-0} = mode;
1653 let DecoderMethod = "DecodeCPSInstruction" in {
1655 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1656 "$imod\t$iflags, $mode">;
1657 let mode = 0, M = 0 in
1658 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1660 let imod = 0, iflags = 0, M = 1 in
1661 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1664 // Preload signals the memory system of possible future data/instruction access.
1665 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1667 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1668 !strconcat(opc, "\t$addr"),
1669 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1672 let Inst{31-26} = 0b111101;
1673 let Inst{25} = 0; // 0 for immediate form
1674 let Inst{24} = data;
1675 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1676 let Inst{22} = read;
1677 let Inst{21-20} = 0b01;
1678 let Inst{19-16} = addr{16-13}; // Rn
1679 let Inst{15-12} = 0b1111;
1680 let Inst{11-0} = addr{11-0}; // imm12
1683 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1684 !strconcat(opc, "\t$shift"),
1685 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1687 let Inst{31-26} = 0b111101;
1688 let Inst{25} = 1; // 1 for register form
1689 let Inst{24} = data;
1690 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1691 let Inst{22} = read;
1692 let Inst{21-20} = 0b01;
1693 let Inst{19-16} = shift{16-13}; // Rn
1694 let Inst{15-12} = 0b1111;
1695 let Inst{11-0} = shift{11-0};
1700 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1701 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1702 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1704 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1705 "setend\t$end", []>, Requires<[IsARM]> {
1707 let Inst{31-10} = 0b1111000100000001000000;
1712 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1713 []>, Requires<[IsARM, HasV7]> {
1715 let Inst{27-4} = 0b001100100000111100001111;
1716 let Inst{3-0} = opt;
1719 // A5.4 Permanently UNDEFINED instructions.
1720 let isBarrier = 1, isTerminator = 1 in
1721 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1724 let Inst = 0xe7ffdefe;
1727 // Address computation and loads and stores in PIC mode.
1728 let isNotDuplicable = 1 in {
1729 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1731 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1733 let AddedComplexity = 10 in {
1734 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1736 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1738 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1740 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1742 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1744 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1746 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1748 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1750 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1752 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1754 let AddedComplexity = 10 in {
1755 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1756 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1758 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1759 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1760 addrmodepc:$addr)]>;
1762 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1763 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1765 } // isNotDuplicable = 1
1768 // LEApcrel - Load a pc-relative address into a register without offending the
1770 let neverHasSideEffects = 1, isReMaterializable = 1 in
1771 // The 'adr' mnemonic encodes differently if the label is before or after
1772 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1773 // know until then which form of the instruction will be used.
1774 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1775 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1778 let Inst{27-25} = 0b001;
1780 let Inst{23-22} = label{13-12};
1783 let Inst{19-16} = 0b1111;
1784 let Inst{15-12} = Rd;
1785 let Inst{11-0} = label{11-0};
1787 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1790 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1791 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1794 //===----------------------------------------------------------------------===//
1795 // Control Flow Instructions.
1798 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1800 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1801 "bx", "\tlr", [(ARMretflag)]>,
1802 Requires<[IsARM, HasV4T]> {
1803 let Inst{27-0} = 0b0001001011111111111100011110;
1807 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1808 "mov", "\tpc, lr", [(ARMretflag)]>,
1809 Requires<[IsARM, NoV4T]> {
1810 let Inst{27-0} = 0b0001101000001111000000001110;
1814 // Indirect branches
1815 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1817 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1818 [(brind GPR:$dst)]>,
1819 Requires<[IsARM, HasV4T]> {
1821 let Inst{31-4} = 0b1110000100101111111111110001;
1822 let Inst{3-0} = dst;
1825 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1826 "bx", "\t$dst", [/* pattern left blank */]>,
1827 Requires<[IsARM, HasV4T]> {
1829 let Inst{27-4} = 0b000100101111111111110001;
1830 let Inst{3-0} = dst;
1834 // All calls clobber the non-callee saved registers. SP is marked as
1835 // a use to prevent stack-pointer assignments that appear immediately
1836 // before calls from potentially appearing dead.
1838 // On non-Darwin platforms R9 is callee-saved.
1839 // FIXME: Do we really need a non-predicated version? If so, it should
1840 // at least be a pseudo instruction expanding to the predicated version
1841 // at MC lowering time.
1842 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1844 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1845 IIC_Br, "bl\t$func",
1846 [(ARMcall tglobaladdr:$func)]>,
1847 Requires<[IsARM, IsNotDarwin]> {
1848 let Inst{31-28} = 0b1110;
1850 let Inst{23-0} = func;
1851 let DecoderMethod = "DecodeBranchImmInstruction";
1854 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1855 IIC_Br, "bl", "\t$func",
1856 [(ARMcall_pred tglobaladdr:$func)]>,
1857 Requires<[IsARM, IsNotDarwin]> {
1859 let Inst{23-0} = func;
1860 let DecoderMethod = "DecodeBranchImmInstruction";
1864 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1865 IIC_Br, "blx\t$func",
1866 [(ARMcall GPR:$func)]>,
1867 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1869 let Inst{31-4} = 0b1110000100101111111111110011;
1870 let Inst{3-0} = func;
1873 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1874 IIC_Br, "blx", "\t$func",
1875 [(ARMcall_pred GPR:$func)]>,
1876 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1878 let Inst{27-4} = 0b000100101111111111110011;
1879 let Inst{3-0} = func;
1883 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1884 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1885 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1886 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1889 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1890 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1891 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1895 // On Darwin R9 is call-clobbered.
1896 // R7 is marked as a use to prevent frame-pointer assignments from being
1897 // moved above / below calls.
1898 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1899 Uses = [R7, SP] in {
1900 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1902 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1903 Requires<[IsARM, IsDarwin]>;
1905 def BLr9_pred : ARMPseudoExpand<(outs),
1906 (ins bl_target:$func, pred:$p, variable_ops),
1908 [(ARMcall_pred tglobaladdr:$func)],
1909 (BL_pred bl_target:$func, pred:$p)>,
1910 Requires<[IsARM, IsDarwin]>;
1913 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1915 [(ARMcall GPR:$func)],
1917 Requires<[IsARM, HasV5T, IsDarwin]>;
1919 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1921 [(ARMcall_pred GPR:$func)],
1922 (BLX_pred GPR:$func, pred:$p)>,
1923 Requires<[IsARM, HasV5T, IsDarwin]>;
1926 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1927 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1928 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1929 Requires<[IsARM, HasV4T, IsDarwin]>;
1932 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1933 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1934 Requires<[IsARM, NoV4T, IsDarwin]>;
1937 let isBranch = 1, isTerminator = 1 in {
1938 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1939 // a two-value operand where a dag node expects two operands. :(
1940 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1941 IIC_Br, "b", "\t$target",
1942 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1944 let Inst{23-0} = target;
1945 let DecoderMethod = "DecodeBranchImmInstruction";
1948 let isBarrier = 1 in {
1949 // B is "predicable" since it's just a Bcc with an 'always' condition.
1950 let isPredicable = 1 in
1951 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1952 // should be sufficient.
1953 // FIXME: Is B really a Barrier? That doesn't seem right.
1954 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1955 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1957 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1958 def BR_JTr : ARMPseudoInst<(outs),
1959 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1961 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1962 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1963 // into i12 and rs suffixed versions.
1964 def BR_JTm : ARMPseudoInst<(outs),
1965 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1967 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1969 def BR_JTadd : ARMPseudoInst<(outs),
1970 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1972 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1974 } // isNotDuplicable = 1, isIndirectBranch = 1
1980 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1981 "blx\t$target", []>,
1982 Requires<[IsARM, HasV5T]> {
1983 let Inst{31-25} = 0b1111101;
1985 let Inst{23-0} = target{24-1};
1986 let Inst{24} = target{0};
1989 // Branch and Exchange Jazelle
1990 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1991 [/* pattern left blank */]> {
1993 let Inst{23-20} = 0b0010;
1994 let Inst{19-8} = 0xfff;
1995 let Inst{7-4} = 0b0010;
1996 let Inst{3-0} = func;
2001 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2003 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2005 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2006 IIC_Br, []>, Requires<[IsDarwin]>;
2008 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2009 IIC_Br, []>, Requires<[IsDarwin]>;
2011 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2013 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2014 Requires<[IsARM, IsDarwin]>;
2016 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2019 Requires<[IsARM, IsDarwin]>;
2023 // Non-Darwin versions (the difference is R9).
2024 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2026 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2027 IIC_Br, []>, Requires<[IsNotDarwin]>;
2029 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2030 IIC_Br, []>, Requires<[IsNotDarwin]>;
2032 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2034 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2035 Requires<[IsARM, IsNotDarwin]>;
2037 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2040 Requires<[IsARM, IsNotDarwin]>;
2044 // Secure Monitor Call is a system instruction.
2045 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2048 let Inst{23-4} = 0b01100000000000000111;
2049 let Inst{3-0} = opt;
2052 // Supervisor Call (Software Interrupt)
2053 let isCall = 1, Uses = [SP] in {
2054 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2056 let Inst{23-0} = svc;
2060 // Store Return State
2061 class SRSI<bit wb, string asm>
2062 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2063 NoItinerary, asm, "", []> {
2065 let Inst{31-28} = 0b1111;
2066 let Inst{27-25} = 0b100;
2070 let Inst{19-16} = 0b1101; // SP
2071 let Inst{15-5} = 0b00000101000;
2072 let Inst{4-0} = mode;
2075 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2076 let Inst{24-23} = 0;
2078 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2079 let Inst{24-23} = 0;
2081 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2082 let Inst{24-23} = 0b10;
2084 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2085 let Inst{24-23} = 0b10;
2087 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2088 let Inst{24-23} = 0b01;
2090 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2091 let Inst{24-23} = 0b01;
2093 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2094 let Inst{24-23} = 0b11;
2096 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2097 let Inst{24-23} = 0b11;
2100 // Return From Exception
2101 class RFEI<bit wb, string asm>
2102 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2103 NoItinerary, asm, "", []> {
2105 let Inst{31-28} = 0b1111;
2106 let Inst{27-25} = 0b100;
2110 let Inst{19-16} = Rn;
2111 let Inst{15-0} = 0xa00;
2114 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2115 let Inst{24-23} = 0;
2117 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2118 let Inst{24-23} = 0;
2120 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2121 let Inst{24-23} = 0b10;
2123 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2124 let Inst{24-23} = 0b10;
2126 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2127 let Inst{24-23} = 0b01;
2129 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2130 let Inst{24-23} = 0b01;
2132 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2133 let Inst{24-23} = 0b11;
2135 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2136 let Inst{24-23} = 0b11;
2139 //===----------------------------------------------------------------------===//
2140 // Load / store Instructions.
2146 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2147 UnOpFrag<(load node:$Src)>>;
2148 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2149 UnOpFrag<(zextloadi8 node:$Src)>>;
2150 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2151 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2152 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2153 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2155 // Special LDR for loads from non-pc-relative constpools.
2156 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2157 isReMaterializable = 1, isCodeGenOnly = 1 in
2158 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2159 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2163 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2164 let Inst{19-16} = 0b1111;
2165 let Inst{15-12} = Rt;
2166 let Inst{11-0} = addr{11-0}; // imm12
2169 // Loads with zero extension
2170 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2171 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2172 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2174 // Loads with sign extension
2175 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2176 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2177 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2179 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2180 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2181 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2183 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2185 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2186 (ins addrmode3:$addr), LdMiscFrm,
2187 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2188 []>, Requires<[IsARM, HasV5TE]>;
2192 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2193 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2194 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2195 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2198 let Inst{23} = addr{12};
2199 let Inst{19-16} = addr{16-13};
2200 let Inst{11-0} = addr{11-0};
2201 let DecoderMethod = "DecodeLDRPreImm";
2202 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2205 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2206 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2207 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2210 let Inst{23} = addr{12};
2211 let Inst{19-16} = addr{16-13};
2212 let Inst{11-0} = addr{11-0};
2214 let DecoderMethod = "DecodeLDRPreReg";
2215 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2218 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2219 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2220 IndexModePost, LdFrm, itin,
2221 opc, "\t$Rt, $addr, $offset",
2222 "$addr.base = $Rn_wb", []> {
2228 let Inst{23} = offset{12};
2229 let Inst{19-16} = addr;
2230 let Inst{11-0} = offset{11-0};
2232 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2235 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2236 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2237 IndexModePost, LdFrm, itin,
2238 opc, "\t$Rt, $addr, $offset",
2239 "$addr.base = $Rn_wb", []> {
2245 let Inst{23} = offset{12};
2246 let Inst{19-16} = addr;
2247 let Inst{11-0} = offset{11-0};
2249 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2254 let mayLoad = 1, neverHasSideEffects = 1 in {
2255 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2256 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2259 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2260 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2261 (ins addrmode3:$addr), IndexModePre,
2263 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2265 let Inst{23} = addr{8}; // U bit
2266 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2267 let Inst{19-16} = addr{12-9}; // Rn
2268 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2269 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2270 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2271 let DecoderMethod = "DecodeAddrMode3Instruction";
2273 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2274 (ins addr_offset_none:$addr, am3offset:$offset),
2275 IndexModePost, LdMiscFrm, itin,
2276 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2280 let Inst{23} = offset{8}; // U bit
2281 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2282 let Inst{19-16} = addr;
2283 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2284 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2285 let DecoderMethod = "DecodeAddrMode3Instruction";
2289 let mayLoad = 1, neverHasSideEffects = 1 in {
2290 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2291 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2292 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2293 let hasExtraDefRegAllocReq = 1 in {
2294 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2295 (ins addrmode3:$addr), IndexModePre,
2296 LdMiscFrm, IIC_iLoad_d_ru,
2297 "ldrd", "\t$Rt, $Rt2, $addr!",
2298 "$addr.base = $Rn_wb", []> {
2300 let Inst{23} = addr{8}; // U bit
2301 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2302 let Inst{19-16} = addr{12-9}; // Rn
2303 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2304 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2305 let DecoderMethod = "DecodeAddrMode3Instruction";
2306 let AsmMatchConverter = "cvtLdrdPre";
2308 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2309 (ins addr_offset_none:$addr, am3offset:$offset),
2310 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2311 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2312 "$addr.base = $Rn_wb", []> {
2315 let Inst{23} = offset{8}; // U bit
2316 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2317 let Inst{19-16} = addr;
2318 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2319 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2320 let DecoderMethod = "DecodeAddrMode3Instruction";
2322 } // hasExtraDefRegAllocReq = 1
2323 } // mayLoad = 1, neverHasSideEffects = 1
2325 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2326 let mayLoad = 1, neverHasSideEffects = 1 in {
2327 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2328 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2329 IndexModePost, LdFrm, IIC_iLoad_ru,
2330 "ldrt", "\t$Rt, $addr, $offset",
2331 "$addr.base = $Rn_wb", []> {
2337 let Inst{23} = offset{12};
2338 let Inst{21} = 1; // overwrite
2339 let Inst{19-16} = addr;
2340 let Inst{11-5} = offset{11-5};
2342 let Inst{3-0} = offset{3-0};
2343 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2346 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2347 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2348 IndexModePost, LdFrm, IIC_iLoad_ru,
2349 "ldrt", "\t$Rt, $addr, $offset",
2350 "$addr.base = $Rn_wb", []> {
2356 let Inst{23} = offset{12};
2357 let Inst{21} = 1; // overwrite
2358 let Inst{19-16} = addr;
2359 let Inst{11-0} = offset{11-0};
2360 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2363 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2364 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2365 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2366 "ldrbt", "\t$Rt, $addr, $offset",
2367 "$addr.base = $Rn_wb", []> {
2373 let Inst{23} = offset{12};
2374 let Inst{21} = 1; // overwrite
2375 let Inst{19-16} = addr;
2376 let Inst{11-5} = offset{11-5};
2378 let Inst{3-0} = offset{3-0};
2379 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2382 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2383 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2384 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2385 "ldrbt", "\t$Rt, $addr, $offset",
2386 "$addr.base = $Rn_wb", []> {
2392 let Inst{23} = offset{12};
2393 let Inst{21} = 1; // overwrite
2394 let Inst{19-16} = addr;
2395 let Inst{11-0} = offset{11-0};
2396 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2399 multiclass AI3ldrT<bits<4> op, string opc> {
2400 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2401 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2402 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2403 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2405 let Inst{23} = offset{8};
2407 let Inst{11-8} = offset{7-4};
2408 let Inst{3-0} = offset{3-0};
2409 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2411 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2412 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2413 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2414 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2416 let Inst{23} = Rm{4};
2419 let Inst{3-0} = Rm{3-0};
2420 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2424 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2425 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2426 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2431 // Stores with truncate
2432 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2433 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2434 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2437 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2438 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2439 StMiscFrm, IIC_iStore_d_r,
2440 "strd", "\t$Rt, $src2, $addr", []>,
2441 Requires<[IsARM, HasV5TE]> {
2446 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2447 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2448 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2450 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2453 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2454 let Inst{19-16} = addr{16-13}; // Rn
2455 let Inst{11-0} = addr{11-0}; // imm12
2456 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2457 let DecoderMethod = "DecodeSTRPreImm";
2460 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2461 (ins GPR:$Rt, ldst_so_reg:$addr),
2462 IndexModePre, StFrm, itin,
2463 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2466 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2467 let Inst{19-16} = addr{16-13}; // Rn
2468 let Inst{11-0} = addr{11-0};
2469 let Inst{4} = 0; // Inst{4} = 0
2470 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2471 let DecoderMethod = "DecodeSTRPreReg";
2473 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2474 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2475 IndexModePost, StFrm, itin,
2476 opc, "\t$Rt, $addr, $offset",
2477 "$addr.base = $Rn_wb", []> {
2483 let Inst{23} = offset{12};
2484 let Inst{19-16} = addr;
2485 let Inst{11-0} = offset{11-0};
2487 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2490 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2491 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2492 IndexModePost, StFrm, itin,
2493 opc, "\t$Rt, $addr, $offset",
2494 "$addr.base = $Rn_wb", []> {
2500 let Inst{23} = offset{12};
2501 let Inst{19-16} = addr;
2502 let Inst{11-0} = offset{11-0};
2504 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2508 let mayStore = 1, neverHasSideEffects = 1 in {
2509 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2510 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2513 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2514 am2offset_reg:$offset),
2515 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2516 am2offset_reg:$offset)>;
2517 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2518 am2offset_imm:$offset),
2519 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2520 am2offset_imm:$offset)>;
2521 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2522 am2offset_reg:$offset),
2523 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2524 am2offset_reg:$offset)>;
2525 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2526 am2offset_imm:$offset),
2527 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2528 am2offset_imm:$offset)>;
2530 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2531 // put the patterns on the instruction definitions directly as ISel wants
2532 // the address base and offset to be separate operands, not a single
2533 // complex operand like we represent the instructions themselves. The
2534 // pseudos map between the two.
2535 let usesCustomInserter = 1,
2536 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2537 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2538 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2541 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2542 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2543 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2546 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2547 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2548 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2551 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2552 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2553 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2556 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2557 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2558 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2561 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2566 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2567 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2568 StMiscFrm, IIC_iStore_bh_ru,
2569 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2571 let Inst{23} = addr{8}; // U bit
2572 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2573 let Inst{19-16} = addr{12-9}; // Rn
2574 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2575 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2576 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2577 let DecoderMethod = "DecodeAddrMode3Instruction";
2580 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2581 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2582 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2583 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2584 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2585 addr_offset_none:$addr,
2586 am3offset:$offset))]> {
2589 let Inst{23} = offset{8}; // U bit
2590 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2591 let Inst{19-16} = addr;
2592 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2593 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2594 let DecoderMethod = "DecodeAddrMode3Instruction";
2597 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2598 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2599 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2600 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2601 "strd", "\t$Rt, $Rt2, $addr!",
2602 "$addr.base = $Rn_wb", []> {
2604 let Inst{23} = addr{8}; // U bit
2605 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2606 let Inst{19-16} = addr{12-9}; // Rn
2607 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2608 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2609 let DecoderMethod = "DecodeAddrMode3Instruction";
2610 let AsmMatchConverter = "cvtStrdPre";
2613 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2614 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2616 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2617 "strd", "\t$Rt, $Rt2, $addr, $offset",
2618 "$addr.base = $Rn_wb", []> {
2621 let Inst{23} = offset{8}; // U bit
2622 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2623 let Inst{19-16} = addr;
2624 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2625 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2626 let DecoderMethod = "DecodeAddrMode3Instruction";
2628 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2630 // STRT, STRBT, and STRHT
2632 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2633 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2634 IndexModePost, StFrm, IIC_iStore_bh_ru,
2635 "strbt", "\t$Rt, $addr, $offset",
2636 "$addr.base = $Rn_wb", []> {
2642 let Inst{23} = offset{12};
2643 let Inst{21} = 1; // overwrite
2644 let Inst{19-16} = addr;
2645 let Inst{11-5} = offset{11-5};
2647 let Inst{3-0} = offset{3-0};
2648 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2651 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2652 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2653 IndexModePost, StFrm, IIC_iStore_bh_ru,
2654 "strbt", "\t$Rt, $addr, $offset",
2655 "$addr.base = $Rn_wb", []> {
2661 let Inst{23} = offset{12};
2662 let Inst{21} = 1; // overwrite
2663 let Inst{19-16} = addr;
2664 let Inst{11-0} = offset{11-0};
2665 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2668 let mayStore = 1, neverHasSideEffects = 1 in {
2669 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2670 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2671 IndexModePost, StFrm, IIC_iStore_ru,
2672 "strt", "\t$Rt, $addr, $offset",
2673 "$addr.base = $Rn_wb", []> {
2679 let Inst{23} = offset{12};
2680 let Inst{21} = 1; // overwrite
2681 let Inst{19-16} = addr;
2682 let Inst{11-5} = offset{11-5};
2684 let Inst{3-0} = offset{3-0};
2685 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2688 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2689 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2690 IndexModePost, StFrm, IIC_iStore_ru,
2691 "strt", "\t$Rt, $addr, $offset",
2692 "$addr.base = $Rn_wb", []> {
2698 let Inst{23} = offset{12};
2699 let Inst{21} = 1; // overwrite
2700 let Inst{19-16} = addr;
2701 let Inst{11-0} = offset{11-0};
2702 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2707 multiclass AI3strT<bits<4> op, string opc> {
2708 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2709 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2710 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2711 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2713 let Inst{23} = offset{8};
2715 let Inst{11-8} = offset{7-4};
2716 let Inst{3-0} = offset{3-0};
2717 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2719 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2720 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2721 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2722 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2724 let Inst{23} = Rm{4};
2727 let Inst{3-0} = Rm{3-0};
2728 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2733 defm STRHT : AI3strT<0b1011, "strht">;
2736 //===----------------------------------------------------------------------===//
2737 // Load / store multiple Instructions.
2740 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2741 InstrItinClass itin, InstrItinClass itin_upd> {
2742 // IA is the default, so no need for an explicit suffix on the
2743 // mnemonic here. Without it is the cannonical spelling.
2745 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2746 IndexModeNone, f, itin,
2747 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2748 let Inst{24-23} = 0b01; // Increment After
2749 let Inst{21} = 0; // No writeback
2750 let Inst{20} = L_bit;
2753 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2754 IndexModeUpd, f, itin_upd,
2755 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2756 let Inst{24-23} = 0b01; // Increment After
2757 let Inst{21} = 1; // Writeback
2758 let Inst{20} = L_bit;
2760 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2763 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2764 IndexModeNone, f, itin,
2765 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2766 let Inst{24-23} = 0b00; // Decrement After
2767 let Inst{21} = 0; // No writeback
2768 let Inst{20} = L_bit;
2771 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2772 IndexModeUpd, f, itin_upd,
2773 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2774 let Inst{24-23} = 0b00; // Decrement After
2775 let Inst{21} = 1; // Writeback
2776 let Inst{20} = L_bit;
2778 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2781 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2782 IndexModeNone, f, itin,
2783 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2784 let Inst{24-23} = 0b10; // Decrement Before
2785 let Inst{21} = 0; // No writeback
2786 let Inst{20} = L_bit;
2789 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2790 IndexModeUpd, f, itin_upd,
2791 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2792 let Inst{24-23} = 0b10; // Decrement Before
2793 let Inst{21} = 1; // Writeback
2794 let Inst{20} = L_bit;
2796 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2799 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2800 IndexModeNone, f, itin,
2801 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2802 let Inst{24-23} = 0b11; // Increment Before
2803 let Inst{21} = 0; // No writeback
2804 let Inst{20} = L_bit;
2807 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2808 IndexModeUpd, f, itin_upd,
2809 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2810 let Inst{24-23} = 0b11; // Increment Before
2811 let Inst{21} = 1; // Writeback
2812 let Inst{20} = L_bit;
2814 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2818 let neverHasSideEffects = 1 in {
2820 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2821 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2823 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2824 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2826 } // neverHasSideEffects
2828 // FIXME: remove when we have a way to marking a MI with these properties.
2829 // FIXME: Should pc be an implicit operand like PICADD, etc?
2830 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2831 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2832 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2833 reglist:$regs, variable_ops),
2834 4, IIC_iLoad_mBr, [],
2835 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2836 RegConstraint<"$Rn = $wb">;
2838 //===----------------------------------------------------------------------===//
2839 // Move Instructions.
2842 let neverHasSideEffects = 1 in
2843 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2844 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2848 let Inst{19-16} = 0b0000;
2849 let Inst{11-4} = 0b00000000;
2852 let Inst{15-12} = Rd;
2855 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2856 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2858 // A version for the smaller set of tail call registers.
2859 let neverHasSideEffects = 1 in
2860 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2861 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2865 let Inst{11-4} = 0b00000000;
2868 let Inst{15-12} = Rd;
2871 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2872 DPSoRegRegFrm, IIC_iMOVsr,
2873 "mov", "\t$Rd, $src",
2874 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2877 let Inst{15-12} = Rd;
2878 let Inst{19-16} = 0b0000;
2879 let Inst{11-8} = src{11-8};
2881 let Inst{6-5} = src{6-5};
2883 let Inst{3-0} = src{3-0};
2887 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2888 DPSoRegImmFrm, IIC_iMOVsr,
2889 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2893 let Inst{15-12} = Rd;
2894 let Inst{19-16} = 0b0000;
2895 let Inst{11-5} = src{11-5};
2897 let Inst{3-0} = src{3-0};
2901 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2902 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2903 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2907 let Inst{15-12} = Rd;
2908 let Inst{19-16} = 0b0000;
2909 let Inst{11-0} = imm;
2912 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2913 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2915 "movw", "\t$Rd, $imm",
2916 [(set GPR:$Rd, imm0_65535:$imm)]>,
2917 Requires<[IsARM, HasV6T2]>, UnaryDP {
2920 let Inst{15-12} = Rd;
2921 let Inst{11-0} = imm{11-0};
2922 let Inst{19-16} = imm{15-12};
2925 let DecoderMethod = "DecodeArmMOVTWInstruction";
2928 def : InstAlias<"mov${p} $Rd, $imm",
2929 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2932 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2933 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2935 let Constraints = "$src = $Rd" in {
2936 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2937 (ins GPR:$src, imm0_65535_expr:$imm),
2939 "movt", "\t$Rd, $imm",
2941 (or (and GPR:$src, 0xffff),
2942 lo16AllZero:$imm))]>, UnaryDP,
2943 Requires<[IsARM, HasV6T2]> {
2946 let Inst{15-12} = Rd;
2947 let Inst{11-0} = imm{11-0};
2948 let Inst{19-16} = imm{15-12};
2951 let DecoderMethod = "DecodeArmMOVTWInstruction";
2954 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2955 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2959 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2960 Requires<[IsARM, HasV6T2]>;
2962 let Uses = [CPSR] in
2963 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2964 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2967 // These aren't really mov instructions, but we have to define them this way
2968 // due to flag operands.
2970 let Defs = [CPSR] in {
2971 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2972 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2974 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2975 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2979 //===----------------------------------------------------------------------===//
2980 // Extend Instructions.
2985 def SXTB : AI_ext_rrot<0b01101010,
2986 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2987 def SXTH : AI_ext_rrot<0b01101011,
2988 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2990 def SXTAB : AI_exta_rrot<0b01101010,
2991 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2992 def SXTAH : AI_exta_rrot<0b01101011,
2993 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2995 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2997 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3001 let AddedComplexity = 16 in {
3002 def UXTB : AI_ext_rrot<0b01101110,
3003 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3004 def UXTH : AI_ext_rrot<0b01101111,
3005 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3006 def UXTB16 : AI_ext_rrot<0b01101100,
3007 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3009 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3010 // The transformation should probably be done as a combiner action
3011 // instead so we can include a check for masking back in the upper
3012 // eight bits of the source into the lower eight bits of the result.
3013 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3014 // (UXTB16r_rot GPR:$Src, 3)>;
3015 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3016 (UXTB16 GPR:$Src, 1)>;
3018 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3019 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3020 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3021 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3024 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3025 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3028 def SBFX : I<(outs GPRnopc:$Rd),
3029 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3030 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3031 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3032 Requires<[IsARM, HasV6T2]> {
3037 let Inst{27-21} = 0b0111101;
3038 let Inst{6-4} = 0b101;
3039 let Inst{20-16} = width;
3040 let Inst{15-12} = Rd;
3041 let Inst{11-7} = lsb;
3045 def UBFX : I<(outs GPR:$Rd),
3046 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3047 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3048 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3049 Requires<[IsARM, HasV6T2]> {
3054 let Inst{27-21} = 0b0111111;
3055 let Inst{6-4} = 0b101;
3056 let Inst{20-16} = width;
3057 let Inst{15-12} = Rd;
3058 let Inst{11-7} = lsb;
3062 //===----------------------------------------------------------------------===//
3063 // Arithmetic Instructions.
3066 defm ADD : AsI1_bin_irs<0b0100, "add",
3067 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3068 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3069 defm SUB : AsI1_bin_irs<0b0010, "sub",
3070 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3071 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3073 // ADD and SUB with 's' bit set.
3075 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
3076 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
3077 // AdjustInstrPostInstrSelection where we determine whether or not to
3078 // set the "s" bit based on CPSR liveness.
3080 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3081 // support for an optional CPSR definition that corresponds to the DAG
3082 // node's second value. We can then eliminate the implicit def of CPSR.
3083 defm ADDS : AsI1_bin_s_irs<0b0100, "add",
3084 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3085 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3086 defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
3087 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3088 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3090 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3091 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3093 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3094 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3097 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3098 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3099 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3101 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3102 // CPSR and the implicit def of CPSR is not needed.
3103 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
3104 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3105 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3107 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3108 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3111 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3112 // The assume-no-carry-in form uses the negation of the input since add/sub
3113 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3114 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3116 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3117 (SUBri GPR:$src, so_imm_neg:$imm)>;
3118 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3119 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3121 // The with-carry-in form matches bitwise not instead of the negation.
3122 // Effectively, the inverse interpretation of the carry flag already accounts
3123 // for part of the negation.
3124 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3125 (SBCri GPR:$src, so_imm_not:$imm)>;
3127 // Note: These are implemented in C++ code, because they have to generate
3128 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3130 // (mul X, 2^n+1) -> (add (X << n), X)
3131 // (mul X, 2^n-1) -> (rsb X, (X << n))
3133 // ARM Arithmetic Instruction
3134 // GPR:$dst = GPR:$a op GPR:$b
3135 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3136 list<dag> pattern = [],
3137 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3138 string asm = "\t$Rd, $Rn, $Rm">
3139 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3143 let Inst{27-20} = op27_20;
3144 let Inst{11-4} = op11_4;
3145 let Inst{19-16} = Rn;
3146 let Inst{15-12} = Rd;
3150 // Saturating add/subtract
3152 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3153 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3154 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3155 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3156 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3157 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3158 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3159 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3161 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3162 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3165 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3166 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3167 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3168 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3169 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3170 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3171 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3172 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3173 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3174 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3175 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3176 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3178 // Signed/Unsigned add/subtract
3180 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3181 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3182 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3183 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3184 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3185 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3186 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3187 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3188 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3189 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3190 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3191 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3193 // Signed/Unsigned halving add/subtract
3195 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3196 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3197 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3198 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3199 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3200 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3201 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3202 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3203 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3204 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3205 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3206 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3208 // Unsigned Sum of Absolute Differences [and Accumulate].
3210 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3211 MulFrm /* for convenience */, NoItinerary, "usad8",
3212 "\t$Rd, $Rn, $Rm", []>,
3213 Requires<[IsARM, HasV6]> {
3217 let Inst{27-20} = 0b01111000;
3218 let Inst{15-12} = 0b1111;
3219 let Inst{7-4} = 0b0001;
3220 let Inst{19-16} = Rd;
3221 let Inst{11-8} = Rm;
3224 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3225 MulFrm /* for convenience */, NoItinerary, "usada8",
3226 "\t$Rd, $Rn, $Rm, $Ra", []>,
3227 Requires<[IsARM, HasV6]> {
3232 let Inst{27-20} = 0b01111000;
3233 let Inst{7-4} = 0b0001;
3234 let Inst{19-16} = Rd;
3235 let Inst{15-12} = Ra;
3236 let Inst{11-8} = Rm;
3240 // Signed/Unsigned saturate
3242 def SSAT : AI<(outs GPRnopc:$Rd),
3243 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3244 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3249 let Inst{27-21} = 0b0110101;
3250 let Inst{5-4} = 0b01;
3251 let Inst{20-16} = sat_imm;
3252 let Inst{15-12} = Rd;
3253 let Inst{11-7} = sh{4-0};
3254 let Inst{6} = sh{5};
3258 def SSAT16 : AI<(outs GPRnopc:$Rd),
3259 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3260 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3264 let Inst{27-20} = 0b01101010;
3265 let Inst{11-4} = 0b11110011;
3266 let Inst{15-12} = Rd;
3267 let Inst{19-16} = sat_imm;
3271 def USAT : AI<(outs GPRnopc:$Rd),
3272 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3273 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3278 let Inst{27-21} = 0b0110111;
3279 let Inst{5-4} = 0b01;
3280 let Inst{15-12} = Rd;
3281 let Inst{11-7} = sh{4-0};
3282 let Inst{6} = sh{5};
3283 let Inst{20-16} = sat_imm;
3287 def USAT16 : AI<(outs GPRnopc:$Rd),
3288 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3289 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3293 let Inst{27-20} = 0b01101110;
3294 let Inst{11-4} = 0b11110011;
3295 let Inst{15-12} = Rd;
3296 let Inst{19-16} = sat_imm;
3300 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3301 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3302 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3303 (USAT imm:$pos, GPRnopc:$a, 0)>;
3305 //===----------------------------------------------------------------------===//
3306 // Bitwise Instructions.
3309 defm AND : AsI1_bin_irs<0b0000, "and",
3310 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3311 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3312 defm ORR : AsI1_bin_irs<0b1100, "orr",
3313 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3314 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3315 defm EOR : AsI1_bin_irs<0b0001, "eor",
3316 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3317 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3318 defm BIC : AsI1_bin_irs<0b1110, "bic",
3319 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3320 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3322 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3323 // like in the actual instruction encoding. The complexity of mapping the mask
3324 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3325 // instruction description.
3326 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3327 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3328 "bfc", "\t$Rd, $imm", "$src = $Rd",
3329 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3330 Requires<[IsARM, HasV6T2]> {
3333 let Inst{27-21} = 0b0111110;
3334 let Inst{6-0} = 0b0011111;
3335 let Inst{15-12} = Rd;
3336 let Inst{11-7} = imm{4-0}; // lsb
3337 let Inst{20-16} = imm{9-5}; // msb
3340 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3341 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3342 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3343 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3344 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3345 bf_inv_mask_imm:$imm))]>,
3346 Requires<[IsARM, HasV6T2]> {
3350 let Inst{27-21} = 0b0111110;
3351 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3352 let Inst{15-12} = Rd;
3353 let Inst{11-7} = imm{4-0}; // lsb
3354 let Inst{20-16} = imm{9-5}; // width
3358 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3359 "mvn", "\t$Rd, $Rm",
3360 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3364 let Inst{19-16} = 0b0000;
3365 let Inst{11-4} = 0b00000000;
3366 let Inst{15-12} = Rd;
3369 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3370 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3371 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3375 let Inst{19-16} = 0b0000;
3376 let Inst{15-12} = Rd;
3377 let Inst{11-5} = shift{11-5};
3379 let Inst{3-0} = shift{3-0};
3381 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3382 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3383 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3387 let Inst{19-16} = 0b0000;
3388 let Inst{15-12} = Rd;
3389 let Inst{11-8} = shift{11-8};
3391 let Inst{6-5} = shift{6-5};
3393 let Inst{3-0} = shift{3-0};
3395 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3396 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3397 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3398 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3402 let Inst{19-16} = 0b0000;
3403 let Inst{15-12} = Rd;
3404 let Inst{11-0} = imm;
3407 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3408 (BICri GPR:$src, so_imm_not:$imm)>;
3410 //===----------------------------------------------------------------------===//
3411 // Multiply Instructions.
3413 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3414 string opc, string asm, list<dag> pattern>
3415 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3419 let Inst{19-16} = Rd;
3420 let Inst{11-8} = Rm;
3423 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3424 string opc, string asm, list<dag> pattern>
3425 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3430 let Inst{19-16} = RdHi;
3431 let Inst{15-12} = RdLo;
3432 let Inst{11-8} = Rm;
3436 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3437 // property. Remove them when it's possible to add those properties
3438 // on an individual MachineInstr, not just an instuction description.
3439 let isCommutable = 1 in {
3440 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3441 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3442 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3443 Requires<[IsARM, HasV6]> {
3444 let Inst{15-12} = 0b0000;
3447 let Constraints = "@earlyclobber $Rd" in
3448 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3449 pred:$p, cc_out:$s),
3451 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3452 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3453 Requires<[IsARM, NoV6]>;
3456 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3457 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3458 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3459 Requires<[IsARM, HasV6]> {
3461 let Inst{15-12} = Ra;
3464 let Constraints = "@earlyclobber $Rd" in
3465 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3466 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3468 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3469 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3470 Requires<[IsARM, NoV6]>;
3472 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3473 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3474 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3475 Requires<[IsARM, HasV6T2]> {
3480 let Inst{19-16} = Rd;
3481 let Inst{15-12} = Ra;
3482 let Inst{11-8} = Rm;
3486 // Extra precision multiplies with low / high results
3487 let neverHasSideEffects = 1 in {
3488 let isCommutable = 1 in {
3489 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3490 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3491 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3492 Requires<[IsARM, HasV6]>;
3494 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3495 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3496 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3497 Requires<[IsARM, HasV6]>;
3499 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3500 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3501 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3503 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3504 Requires<[IsARM, NoV6]>;
3506 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3507 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3509 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3510 Requires<[IsARM, NoV6]>;
3514 // Multiply + accumulate
3515 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3516 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3517 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3518 Requires<[IsARM, HasV6]>;
3519 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3520 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3521 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3522 Requires<[IsARM, HasV6]>;
3524 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3525 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3526 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3527 Requires<[IsARM, HasV6]> {
3532 let Inst{19-16} = RdHi;
3533 let Inst{15-12} = RdLo;
3534 let Inst{11-8} = Rm;
3538 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3539 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3540 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3542 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3543 Requires<[IsARM, NoV6]>;
3544 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3545 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3547 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3548 Requires<[IsARM, NoV6]>;
3549 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3550 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3552 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3553 Requires<[IsARM, NoV6]>;
3556 } // neverHasSideEffects
3558 // Most significant word multiply
3559 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3560 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3561 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3562 Requires<[IsARM, HasV6]> {
3563 let Inst{15-12} = 0b1111;
3566 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3567 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3568 Requires<[IsARM, HasV6]> {
3569 let Inst{15-12} = 0b1111;
3572 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3573 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3574 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3575 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3576 Requires<[IsARM, HasV6]>;
3578 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3579 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3580 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3581 Requires<[IsARM, HasV6]>;
3583 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3584 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3585 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3586 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3587 Requires<[IsARM, HasV6]>;
3589 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3590 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3591 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3592 Requires<[IsARM, HasV6]>;
3594 multiclass AI_smul<string opc, PatFrag opnode> {
3595 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3596 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3597 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3598 (sext_inreg GPR:$Rm, i16)))]>,
3599 Requires<[IsARM, HasV5TE]>;
3601 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3602 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3603 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3604 (sra GPR:$Rm, (i32 16))))]>,
3605 Requires<[IsARM, HasV5TE]>;
3607 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3608 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3609 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3610 (sext_inreg GPR:$Rm, i16)))]>,
3611 Requires<[IsARM, HasV5TE]>;
3613 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3614 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3615 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3616 (sra GPR:$Rm, (i32 16))))]>,
3617 Requires<[IsARM, HasV5TE]>;
3619 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3620 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3621 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3622 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3623 Requires<[IsARM, HasV5TE]>;
3625 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3626 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3627 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3628 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3629 Requires<[IsARM, HasV5TE]>;
3633 multiclass AI_smla<string opc, PatFrag opnode> {
3634 let DecoderMethod = "DecodeSMLAInstruction" in {
3635 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3636 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3637 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3638 [(set GPRnopc:$Rd, (add GPR:$Ra,
3639 (opnode (sext_inreg GPRnopc:$Rn, i16),
3640 (sext_inreg GPRnopc:$Rm, i16))))]>,
3641 Requires<[IsARM, HasV5TE]>;
3643 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3644 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3645 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3647 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3648 (sra GPRnopc:$Rm, (i32 16)))))]>,
3649 Requires<[IsARM, HasV5TE]>;
3651 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3652 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3653 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3655 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3656 (sext_inreg GPRnopc:$Rm, i16))))]>,
3657 Requires<[IsARM, HasV5TE]>;
3659 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3660 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3661 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3663 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3664 (sra GPRnopc:$Rm, (i32 16)))))]>,
3665 Requires<[IsARM, HasV5TE]>;
3667 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3668 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3669 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3671 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3672 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3673 Requires<[IsARM, HasV5TE]>;
3675 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3676 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3677 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3679 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3680 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3681 Requires<[IsARM, HasV5TE]>;
3685 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3686 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3688 // Halfword multiply accumulate long: SMLAL<x><y>.
3689 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3690 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3691 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3692 Requires<[IsARM, HasV5TE]>;
3694 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3695 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3696 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3697 Requires<[IsARM, HasV5TE]>;
3699 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3700 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3701 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3702 Requires<[IsARM, HasV5TE]>;
3704 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3705 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3706 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3707 Requires<[IsARM, HasV5TE]>;
3709 // Helper class for AI_smld.
3710 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3711 InstrItinClass itin, string opc, string asm>
3712 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3715 let Inst{27-23} = 0b01110;
3716 let Inst{22} = long;
3717 let Inst{21-20} = 0b00;
3718 let Inst{11-8} = Rm;
3725 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3726 InstrItinClass itin, string opc, string asm>
3727 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3729 let Inst{15-12} = 0b1111;
3730 let Inst{19-16} = Rd;
3732 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3733 InstrItinClass itin, string opc, string asm>
3734 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3737 let Inst{19-16} = Rd;
3738 let Inst{15-12} = Ra;
3740 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3741 InstrItinClass itin, string opc, string asm>
3742 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3745 let Inst{19-16} = RdHi;
3746 let Inst{15-12} = RdLo;
3749 multiclass AI_smld<bit sub, string opc> {
3751 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3752 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3753 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3755 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3756 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3757 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3759 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3760 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3761 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3763 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3764 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3765 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3769 defm SMLA : AI_smld<0, "smla">;
3770 defm SMLS : AI_smld<1, "smls">;
3772 multiclass AI_sdml<bit sub, string opc> {
3774 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3775 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3776 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3777 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3780 defm SMUA : AI_sdml<0, "smua">;
3781 defm SMUS : AI_sdml<1, "smus">;
3783 //===----------------------------------------------------------------------===//
3784 // Misc. Arithmetic Instructions.
3787 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3788 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3789 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3791 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3792 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3793 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3794 Requires<[IsARM, HasV6T2]>;
3796 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3797 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3798 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3800 let AddedComplexity = 5 in
3801 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3802 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3803 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3804 Requires<[IsARM, HasV6]>;
3806 let AddedComplexity = 5 in
3807 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3808 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3809 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3810 Requires<[IsARM, HasV6]>;
3812 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3813 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3816 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3817 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3818 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3819 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3820 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3822 Requires<[IsARM, HasV6]>;
3824 // Alternate cases for PKHBT where identities eliminate some nodes.
3825 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3826 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3827 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3828 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3830 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3831 // will match the pattern below.
3832 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3833 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3834 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3835 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3836 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3838 Requires<[IsARM, HasV6]>;
3840 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3841 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3842 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3843 (srl GPRnopc:$src2, imm16_31:$sh)),
3844 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3845 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3846 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3847 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3849 //===----------------------------------------------------------------------===//
3850 // Comparison Instructions...
3853 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3854 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3855 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3857 // ARMcmpZ can re-use the above instruction definitions.
3858 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3859 (CMPri GPR:$src, so_imm:$imm)>;
3860 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3861 (CMPrr GPR:$src, GPR:$rhs)>;
3862 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3863 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3864 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3865 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3867 // FIXME: We have to be careful when using the CMN instruction and comparison
3868 // with 0. One would expect these two pieces of code should give identical
3884 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3885 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3886 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3887 // value of r0 and the carry bit (because the "carry bit" parameter to
3888 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3889 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3890 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3891 // parameter to AddWithCarry is defined as 0).
3893 // When x is 0 and unsigned:
3897 // ~x + 1 = 0x1 0000 0000
3898 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3900 // Therefore, we should disable CMN when comparing against zero, until we can
3901 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3902 // when it's a comparison which doesn't look at the 'carry' flag).
3904 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3906 // This is related to <rdar://problem/7569620>.
3908 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3909 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3911 // Note that TST/TEQ don't set all the same flags that CMP does!
3912 defm TST : AI1_cmp_irs<0b1000, "tst",
3913 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3914 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3915 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3916 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3917 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3919 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3920 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3921 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3923 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3924 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3926 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3927 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3929 // Pseudo i64 compares for some floating point compares.
3930 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3932 def BCCi64 : PseudoInst<(outs),
3933 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3935 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3937 def BCCZi64 : PseudoInst<(outs),
3938 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3939 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3940 } // usesCustomInserter
3943 // Conditional moves
3944 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3945 // a two-value operand where a dag node expects two operands. :(
3946 let neverHasSideEffects = 1 in {
3947 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3949 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3950 RegConstraint<"$false = $Rd">;
3951 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3952 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3954 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3955 imm:$cc, CCR:$ccr))*/]>,
3956 RegConstraint<"$false = $Rd">;
3957 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3958 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3960 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3961 imm:$cc, CCR:$ccr))*/]>,
3962 RegConstraint<"$false = $Rd">;
3965 let isMoveImm = 1 in
3966 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3967 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3970 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3972 let isMoveImm = 1 in
3973 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3974 (ins GPR:$false, so_imm:$imm, pred:$p),
3976 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3977 RegConstraint<"$false = $Rd">;
3979 // Two instruction predicate mov immediate.
3980 let isMoveImm = 1 in
3981 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3982 (ins GPR:$false, i32imm:$src, pred:$p),
3983 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3985 let isMoveImm = 1 in
3986 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3987 (ins GPR:$false, so_imm:$imm, pred:$p),
3989 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3990 RegConstraint<"$false = $Rd">;
3991 } // neverHasSideEffects
3993 //===----------------------------------------------------------------------===//
3994 // Atomic operations intrinsics
3997 def MemBarrierOptOperand : AsmOperandClass {
3998 let Name = "MemBarrierOpt";
3999 let ParserMethod = "parseMemBarrierOptOperand";
4001 def memb_opt : Operand<i32> {
4002 let PrintMethod = "printMemBOption";
4003 let ParserMatchClass = MemBarrierOptOperand;
4004 let DecoderMethod = "DecodeMemBarrierOption";
4007 // memory barriers protect the atomic sequences
4008 let hasSideEffects = 1 in {
4009 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4010 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4011 Requires<[IsARM, HasDB]> {
4013 let Inst{31-4} = 0xf57ff05;
4014 let Inst{3-0} = opt;
4018 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4019 "dsb", "\t$opt", []>,
4020 Requires<[IsARM, HasDB]> {
4022 let Inst{31-4} = 0xf57ff04;
4023 let Inst{3-0} = opt;
4026 // ISB has only full system option
4027 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4028 "isb", "\t$opt", []>,
4029 Requires<[IsARM, HasDB]> {
4031 let Inst{31-4} = 0xf57ff06;
4032 let Inst{3-0} = opt;
4035 // Pseudo isntruction that combines movs + predicated rsbmi
4036 // to implement integer ABS
4037 let usesCustomInserter = 1, Defs = [CPSR] in {
4038 def ABS : ARMPseudoInst<
4039 (outs GPR:$dst), (ins GPR:$src),
4040 8, NoItinerary, []>;
4043 let usesCustomInserter = 1 in {
4044 let Defs = [CPSR] in {
4045 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4046 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4047 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4048 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4049 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4050 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4051 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4052 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4053 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4054 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4055 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4056 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4057 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4058 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4059 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4060 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4061 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4062 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4063 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4064 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4065 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4066 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4067 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4068 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4069 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4070 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4071 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4072 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4073 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4074 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4075 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4076 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4077 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4078 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4079 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4080 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4081 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4082 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4083 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4084 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4085 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4086 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4087 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4088 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4089 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4090 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4091 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4092 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4093 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4094 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4095 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4096 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4098 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4099 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4100 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4101 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4102 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4103 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4104 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4105 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4106 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4107 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4108 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4110 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4111 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4113 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4114 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4116 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4117 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4119 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4120 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4122 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4123 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4125 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4126 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4129 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4132 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4136 def ATOMIC_SWAP_I8 : PseudoInst<
4137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4138 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4139 def ATOMIC_SWAP_I16 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4141 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4142 def ATOMIC_SWAP_I32 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4144 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4146 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4148 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4149 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4151 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4152 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4154 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4158 let mayLoad = 1 in {
4159 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4161 "ldrexb", "\t$Rt, $addr", []>;
4162 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4163 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4164 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4165 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4166 let hasExtraDefRegAllocReq = 1 in
4167 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4168 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4169 let DecoderMethod = "DecodeDoubleRegLoad";
4173 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4174 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4175 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4176 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4177 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4178 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4179 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4182 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4183 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4184 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4185 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4186 let DecoderMethod = "DecodeDoubleRegStore";
4189 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4190 Requires<[IsARM, HasV7]> {
4191 let Inst{31-0} = 0b11110101011111111111000000011111;
4194 // SWP/SWPB are deprecated in V6/V7.
4195 let mayLoad = 1, mayStore = 1 in {
4196 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4198 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4202 //===----------------------------------------------------------------------===//
4203 // Coprocessor Instructions.
4206 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4207 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4208 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4209 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4210 imm:$CRm, imm:$opc2)]> {
4218 let Inst{3-0} = CRm;
4220 let Inst{7-5} = opc2;
4221 let Inst{11-8} = cop;
4222 let Inst{15-12} = CRd;
4223 let Inst{19-16} = CRn;
4224 let Inst{23-20} = opc1;
4227 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4228 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4229 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4230 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4231 imm:$CRm, imm:$opc2)]> {
4232 let Inst{31-28} = 0b1111;
4240 let Inst{3-0} = CRm;
4242 let Inst{7-5} = opc2;
4243 let Inst{11-8} = cop;
4244 let Inst{15-12} = CRd;
4245 let Inst{19-16} = CRn;
4246 let Inst{23-20} = opc1;
4249 class ACI<dag oops, dag iops, string opc, string asm,
4250 IndexMode im = IndexModeNone>
4251 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4253 let Inst{27-25} = 0b110;
4255 class ACInoP<dag oops, dag iops, string opc, string asm,
4256 IndexMode im = IndexModeNone>
4257 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4259 let Inst{31-28} = 0b1111;
4260 let Inst{27-25} = 0b110;
4262 multiclass LdStCop<bit load, bit Dbit, string asm> {
4263 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4264 asm, "\t$cop, $CRd, $addr"> {
4268 let Inst{24} = 1; // P = 1
4269 let Inst{23} = addr{8};
4270 let Inst{22} = Dbit;
4271 let Inst{21} = 0; // W = 0
4272 let Inst{20} = load;
4273 let Inst{19-16} = addr{12-9};
4274 let Inst{15-12} = CRd;
4275 let Inst{11-8} = cop;
4276 let Inst{7-0} = addr{7-0};
4277 let DecoderMethod = "DecodeCopMemInstruction";
4279 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4280 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4284 let Inst{24} = 1; // P = 1
4285 let Inst{23} = addr{8};
4286 let Inst{22} = Dbit;
4287 let Inst{21} = 1; // W = 1
4288 let Inst{20} = load;
4289 let Inst{19-16} = addr{12-9};
4290 let Inst{15-12} = CRd;
4291 let Inst{11-8} = cop;
4292 let Inst{7-0} = addr{7-0};
4293 let DecoderMethod = "DecodeCopMemInstruction";
4295 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4296 postidx_imm8s4:$offset),
4297 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4302 let Inst{24} = 0; // P = 0
4303 let Inst{23} = offset{8};
4304 let Inst{22} = Dbit;
4305 let Inst{21} = 1; // W = 1
4306 let Inst{20} = load;
4307 let Inst{19-16} = addr;
4308 let Inst{15-12} = CRd;
4309 let Inst{11-8} = cop;
4310 let Inst{7-0} = offset{7-0};
4311 let DecoderMethod = "DecodeCopMemInstruction";
4313 def _OPTION : ACI<(outs),
4314 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4315 nohash_imm:$option),
4316 asm, "\t$cop, $CRd, $addr, \\{$option\\}"> {
4321 let Inst{24} = 0; // P = 0
4322 let Inst{23} = 1; // U = 1
4323 let Inst{22} = Dbit;
4324 let Inst{21} = 0; // W = 0
4325 let Inst{20} = load;
4326 let Inst{19-16} = addr;
4327 let Inst{15-12} = CRd;
4328 let Inst{11-8} = cop;
4329 let Inst{7-0} = option;
4330 let DecoderMethod = "DecodeCopMemInstruction";
4333 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4334 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4335 asm, "\t$cop, $CRd, $addr"> {
4339 let Inst{24} = 1; // P = 1
4340 let Inst{23} = addr{8};
4341 let Inst{22} = Dbit;
4342 let Inst{21} = 0; // W = 0
4343 let Inst{20} = load;
4344 let Inst{19-16} = addr{12-9};
4345 let Inst{15-12} = CRd;
4346 let Inst{11-8} = cop;
4347 let Inst{7-0} = addr{7-0};
4348 let DecoderMethod = "DecodeCopMemInstruction";
4350 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4351 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4355 let Inst{24} = 1; // P = 1
4356 let Inst{23} = addr{8};
4357 let Inst{22} = Dbit;
4358 let Inst{21} = 1; // W = 1
4359 let Inst{20} = load;
4360 let Inst{19-16} = addr{12-9};
4361 let Inst{15-12} = CRd;
4362 let Inst{11-8} = cop;
4363 let Inst{7-0} = addr{7-0};
4364 let DecoderMethod = "DecodeCopMemInstruction";
4366 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4367 postidx_imm8s4:$offset),
4368 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4373 let Inst{24} = 0; // P = 0
4374 let Inst{23} = offset{8};
4375 let Inst{22} = Dbit;
4376 let Inst{21} = 1; // W = 1
4377 let Inst{20} = load;
4378 let Inst{19-16} = addr;
4379 let Inst{15-12} = CRd;
4380 let Inst{11-8} = cop;
4381 let Inst{7-0} = offset{7-0};
4382 let DecoderMethod = "DecodeCopMemInstruction";
4384 def _OPTION : ACInoP<(outs),
4385 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4386 nohash_imm:$option),
4387 asm, "\t$cop, $CRd, $addr, \\{$option\\}"> {
4392 let Inst{24} = 0; // P = 0
4393 let Inst{23} = 1; // U = 1
4394 let Inst{22} = Dbit;
4395 let Inst{21} = 0; // W = 0
4396 let Inst{20} = load;
4397 let Inst{19-16} = addr;
4398 let Inst{15-12} = CRd;
4399 let Inst{11-8} = cop;
4400 let Inst{7-0} = option;
4401 let DecoderMethod = "DecodeCopMemInstruction";
4405 defm LDC : LdStCop <1, 0, "ldc">;
4406 defm LDCL : LdStCop <1, 1, "ldcl">;
4407 defm STC : LdStCop <0, 0, "stc">;
4408 defm STCL : LdStCop <0, 1, "stcl">;
4409 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4410 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4411 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4412 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4414 //===----------------------------------------------------------------------===//
4415 // Move between coprocessor and ARM core register.
4418 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4420 : ABI<0b1110, oops, iops, NoItinerary, opc,
4421 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4422 let Inst{20} = direction;
4432 let Inst{15-12} = Rt;
4433 let Inst{11-8} = cop;
4434 let Inst{23-21} = opc1;
4435 let Inst{7-5} = opc2;
4436 let Inst{3-0} = CRm;
4437 let Inst{19-16} = CRn;
4440 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4442 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4443 c_imm:$CRm, imm0_7:$opc2),
4444 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4445 imm:$CRm, imm:$opc2)]>;
4446 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4448 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4451 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4452 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4454 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4456 : ABXI<0b1110, oops, iops, NoItinerary,
4457 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4458 let Inst{31-28} = 0b1111;
4459 let Inst{20} = direction;
4469 let Inst{15-12} = Rt;
4470 let Inst{11-8} = cop;
4471 let Inst{23-21} = opc1;
4472 let Inst{7-5} = opc2;
4473 let Inst{3-0} = CRm;
4474 let Inst{19-16} = CRn;
4477 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4479 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4480 c_imm:$CRm, imm0_7:$opc2),
4481 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4482 imm:$CRm, imm:$opc2)]>;
4483 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4485 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4488 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4489 imm:$CRm, imm:$opc2),
4490 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4492 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4493 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4494 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4495 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4496 let Inst{23-21} = 0b010;
4497 let Inst{20} = direction;
4505 let Inst{15-12} = Rt;
4506 let Inst{19-16} = Rt2;
4507 let Inst{11-8} = cop;
4508 let Inst{7-4} = opc1;
4509 let Inst{3-0} = CRm;
4512 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4513 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4515 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4517 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4518 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4519 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4520 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4521 let Inst{31-28} = 0b1111;
4522 let Inst{23-21} = 0b010;
4523 let Inst{20} = direction;
4531 let Inst{15-12} = Rt;
4532 let Inst{19-16} = Rt2;
4533 let Inst{11-8} = cop;
4534 let Inst{7-4} = opc1;
4535 let Inst{3-0} = CRm;
4538 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4539 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4541 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4543 //===----------------------------------------------------------------------===//
4544 // Move between special register and ARM core register
4547 // Move to ARM core register from Special Register
4548 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4549 "mrs", "\t$Rd, apsr", []> {
4551 let Inst{23-16} = 0b00001111;
4552 let Inst{15-12} = Rd;
4553 let Inst{7-4} = 0b0000;
4556 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4558 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4559 "mrs", "\t$Rd, spsr", []> {
4561 let Inst{23-16} = 0b01001111;
4562 let Inst{15-12} = Rd;
4563 let Inst{7-4} = 0b0000;
4566 // Move from ARM core register to Special Register
4568 // No need to have both system and application versions, the encodings are the
4569 // same and the assembly parser has no way to distinguish between them. The mask
4570 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4571 // the mask with the fields to be accessed in the special register.
4572 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4573 "msr", "\t$mask, $Rn", []> {
4578 let Inst{22} = mask{4}; // R bit
4579 let Inst{21-20} = 0b10;
4580 let Inst{19-16} = mask{3-0};
4581 let Inst{15-12} = 0b1111;
4582 let Inst{11-4} = 0b00000000;
4586 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4587 "msr", "\t$mask, $a", []> {
4592 let Inst{22} = mask{4}; // R bit
4593 let Inst{21-20} = 0b10;
4594 let Inst{19-16} = mask{3-0};
4595 let Inst{15-12} = 0b1111;
4599 //===----------------------------------------------------------------------===//
4603 // __aeabi_read_tp preserves the registers r1-r3.
4604 // This is a pseudo inst so that we can get the encoding right,
4605 // complete with fixup for the aeabi_read_tp function.
4607 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4608 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4609 [(set R0, ARMthread_pointer)]>;
4612 //===----------------------------------------------------------------------===//
4613 // SJLJ Exception handling intrinsics
4614 // eh_sjlj_setjmp() is an instruction sequence to store the return
4615 // address and save #0 in R0 for the non-longjmp case.
4616 // Since by its nature we may be coming from some other function to get
4617 // here, and we're using the stack frame for the containing function to
4618 // save/restore registers, we can't keep anything live in regs across
4619 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4620 // when we get here from a longjmp(). We force everything out of registers
4621 // except for our own input by listing the relevant registers in Defs. By
4622 // doing so, we also cause the prologue/epilogue code to actively preserve
4623 // all of the callee-saved resgisters, which is exactly what we want.
4624 // A constant value is passed in $val, and we use the location as a scratch.
4626 // These are pseudo-instructions and are lowered to individual MC-insts, so
4627 // no encoding information is necessary.
4629 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4630 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4631 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4633 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4634 Requires<[IsARM, HasVFP2]>;
4638 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4639 hasSideEffects = 1, isBarrier = 1 in {
4640 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4642 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4643 Requires<[IsARM, NoVFP]>;
4646 // FIXME: Non-Darwin version(s)
4647 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4648 Defs = [ R7, LR, SP ] in {
4649 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4651 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4652 Requires<[IsARM, IsDarwin]>;
4655 // eh.sjlj.dispatchsetup pseudo-instruction.
4656 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4657 // handled when the pseudo is expanded (which happens before any passes
4658 // that need the instruction size).
4659 let isBarrier = 1, hasSideEffects = 1 in
4660 def Int_eh_sjlj_dispatchsetup :
4661 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4662 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4663 Requires<[IsDarwin]>;
4665 //===----------------------------------------------------------------------===//
4666 // Non-Instruction Patterns
4669 // ARMv4 indirect branch using (MOVr PC, dst)
4670 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4671 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4672 4, IIC_Br, [(brind GPR:$dst)],
4673 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4674 Requires<[IsARM, NoV4T]>;
4676 // Large immediate handling.
4678 // 32-bit immediate using two piece so_imms or movw + movt.
4679 // This is a single pseudo instruction, the benefit is that it can be remat'd
4680 // as a single unit instead of having to handle reg inputs.
4681 // FIXME: Remove this when we can do generalized remat.
4682 let isReMaterializable = 1, isMoveImm = 1 in
4683 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4684 [(set GPR:$dst, (arm_i32imm:$src))]>,
4687 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4688 // It also makes it possible to rematerialize the instructions.
4689 // FIXME: Remove this when we can do generalized remat and when machine licm
4690 // can properly the instructions.
4691 let isReMaterializable = 1 in {
4692 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4694 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4695 Requires<[IsARM, UseMovt]>;
4697 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4699 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4700 Requires<[IsARM, UseMovt]>;
4702 let AddedComplexity = 10 in
4703 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4705 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4706 Requires<[IsARM, UseMovt]>;
4707 } // isReMaterializable
4709 // ConstantPool, GlobalAddress, and JumpTable
4710 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4711 Requires<[IsARM, DontUseMovt]>;
4712 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4713 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4714 Requires<[IsARM, UseMovt]>;
4715 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4716 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4718 // TODO: add,sub,and, 3-instr forms?
4721 def : ARMPat<(ARMtcret tcGPR:$dst),
4722 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4724 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4725 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4727 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4728 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4730 def : ARMPat<(ARMtcret tcGPR:$dst),
4731 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4733 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4734 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4736 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4737 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4740 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4741 Requires<[IsARM, IsNotDarwin]>;
4742 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4743 Requires<[IsARM, IsDarwin]>;
4745 // zextload i1 -> zextload i8
4746 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4747 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4749 // extload -> zextload
4750 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4751 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4752 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4753 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4755 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4757 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4758 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4761 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4762 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4763 (SMULBB GPR:$a, GPR:$b)>;
4764 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4765 (SMULBB GPR:$a, GPR:$b)>;
4766 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4767 (sra GPR:$b, (i32 16))),
4768 (SMULBT GPR:$a, GPR:$b)>;
4769 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4770 (SMULBT GPR:$a, GPR:$b)>;
4771 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4772 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4773 (SMULTB GPR:$a, GPR:$b)>;
4774 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4775 (SMULTB GPR:$a, GPR:$b)>;
4776 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4778 (SMULWB GPR:$a, GPR:$b)>;
4779 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4780 (SMULWB GPR:$a, GPR:$b)>;
4782 def : ARMV5TEPat<(add GPR:$acc,
4783 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4784 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4785 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4786 def : ARMV5TEPat<(add GPR:$acc,
4787 (mul sext_16_node:$a, sext_16_node:$b)),
4788 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4789 def : ARMV5TEPat<(add GPR:$acc,
4790 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4791 (sra GPR:$b, (i32 16)))),
4792 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4793 def : ARMV5TEPat<(add GPR:$acc,
4794 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4795 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4796 def : ARMV5TEPat<(add GPR:$acc,
4797 (mul (sra GPR:$a, (i32 16)),
4798 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4799 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4800 def : ARMV5TEPat<(add GPR:$acc,
4801 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4802 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4803 def : ARMV5TEPat<(add GPR:$acc,
4804 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4806 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4807 def : ARMV5TEPat<(add GPR:$acc,
4808 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4809 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4812 // Pre-v7 uses MCR for synchronization barriers.
4813 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4814 Requires<[IsARM, HasV6]>;
4816 // SXT/UXT with no rotate
4817 let AddedComplexity = 16 in {
4818 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4819 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4820 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4821 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4822 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4823 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4824 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4827 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4828 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4830 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4831 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4832 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4833 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4835 // Atomic load/store patterns
4836 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4837 (LDRBrs ldst_so_reg:$src)>;
4838 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4839 (LDRBi12 addrmode_imm12:$src)>;
4840 def : ARMPat<(atomic_load_16 addrmode3:$src),
4841 (LDRH addrmode3:$src)>;
4842 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4843 (LDRrs ldst_so_reg:$src)>;
4844 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4845 (LDRi12 addrmode_imm12:$src)>;
4846 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4847 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4848 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4849 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4850 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4851 (STRH GPR:$val, addrmode3:$ptr)>;
4852 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4853 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4854 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4855 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4858 //===----------------------------------------------------------------------===//
4862 include "ARMInstrThumb.td"
4864 //===----------------------------------------------------------------------===//
4868 include "ARMInstrThumb2.td"
4870 //===----------------------------------------------------------------------===//
4871 // Floating Point Support
4874 include "ARMInstrVFP.td"
4876 //===----------------------------------------------------------------------===//
4877 // Advanced SIMD (NEON) Support
4880 include "ARMInstrNEON.td"
4882 //===----------------------------------------------------------------------===//
4883 // Assembler aliases
4887 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4888 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4889 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4891 // System instructions
4892 def : MnemonicAlias<"swi", "svc">;
4894 // Load / Store Multiple
4895 def : MnemonicAlias<"ldmfd", "ldm">;
4896 def : MnemonicAlias<"ldmia", "ldm">;
4897 def : MnemonicAlias<"ldmea", "ldmdb">;
4898 def : MnemonicAlias<"stmfd", "stmdb">;
4899 def : MnemonicAlias<"stmia", "stm">;
4900 def : MnemonicAlias<"stmea", "stm">;
4902 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4903 // shift amount is zero (i.e., unspecified).
4904 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4905 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4906 Requires<[IsARM, HasV6]>;
4907 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4908 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4909 Requires<[IsARM, HasV6]>;
4911 // PUSH/POP aliases for STM/LDM
4912 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4913 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4915 // SSAT/USAT optional shift operand.
4916 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4917 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4918 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4919 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4922 // Extend instruction optional rotate operand.
4923 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4924 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4925 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4926 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4927 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4928 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4929 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4930 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4931 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4932 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4933 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4934 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4936 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4937 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4938 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4939 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4940 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4941 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4942 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4943 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4944 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4945 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4946 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4947 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4951 def : MnemonicAlias<"rfefa", "rfeda">;
4952 def : MnemonicAlias<"rfeea", "rfedb">;
4953 def : MnemonicAlias<"rfefd", "rfeia">;
4954 def : MnemonicAlias<"rfeed", "rfeib">;
4955 def : MnemonicAlias<"rfe", "rfeia">;
4958 def : MnemonicAlias<"srsfa", "srsda">;
4959 def : MnemonicAlias<"srsea", "srsdb">;
4960 def : MnemonicAlias<"srsfd", "srsia">;
4961 def : MnemonicAlias<"srsed", "srsib">;
4962 def : MnemonicAlias<"srs", "srsia">;
4965 def : MnemonicAlias<"qsubaddx", "qsax">;
4967 def : MnemonicAlias<"saddsubx", "sasx">;
4968 // SHASX == SHADDSUBX
4969 def : MnemonicAlias<"shaddsubx", "shasx">;
4970 // SHSAX == SHSUBADDX
4971 def : MnemonicAlias<"shsubaddx", "shsax">;
4973 def : MnemonicAlias<"ssubaddx", "ssax">;
4975 def : MnemonicAlias<"uaddsubx", "uasx">;
4976 // UHASX == UHADDSUBX
4977 def : MnemonicAlias<"uhaddsubx", "uhasx">;
4978 // UHSAX == UHSUBADDX
4979 def : MnemonicAlias<"uhsubaddx", "uhsax">;
4980 // UQASX == UQADDSUBX
4981 def : MnemonicAlias<"uqaddsubx", "uqasx">;
4982 // UQSAX == UQSUBADDX
4983 def : MnemonicAlias<"uqsubaddx", "uqsax">;
4985 def : MnemonicAlias<"usubaddx", "usax">;
4987 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4988 // Note that the write-back output register is a dummy operand for MC (it's
4989 // only meaningful for codegen), so we just pass zero here.
4990 // FIXME: tblgen not cooperating with argument conversions.
4991 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4992 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4993 //def : InstAlias<"ldrht${p} $Rt, $addr",
4994 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4995 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4996 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;