1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsMClass : Predicate<"Subtarget->isMClass()">,
209 AssemblerPredicate<"FeatureMClass">;
210 def IsARClass : Predicate<"!Subtarget->isMClass()">,
211 AssemblerPredicate<"!FeatureMClass">;
212 def IsARM : Predicate<"!Subtarget->isThumb()">,
213 AssemblerPredicate<"!ModeThumb">;
214 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
215 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
216 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
218 // FIXME: Eventually this will be just "hasV6T2Ops".
219 def UseMovt : Predicate<"Subtarget->useMovt()">;
220 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
221 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
223 //===----------------------------------------------------------------------===//
224 // ARM Flag Definitions.
226 class RegConstraint<string C> {
227 string Constraints = C;
230 //===----------------------------------------------------------------------===//
231 // ARM specific transformation functions and pattern fragments.
234 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
235 // so_imm_neg def below.
236 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
237 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
240 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
241 // so_imm_not def below.
242 def so_imm_not_XFORM : SDNodeXForm<imm, [{
243 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
246 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
247 def imm1_15 : ImmLeaf<i32, [{
248 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
251 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
252 def imm16_31 : ImmLeaf<i32, [{
253 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
258 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
259 }], so_imm_neg_XFORM>;
263 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
264 }], so_imm_not_XFORM>;
266 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
267 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
268 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
271 /// Split a 32-bit immediate into two 16 bit parts.
272 def hi16 : SDNodeXForm<imm, [{
273 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
276 def lo16AllZero : PatLeaf<(i32 imm), [{
277 // Returns true if all low 16-bits are 0.
278 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
281 /// imm0_65535 - An immediate is in the range [0.65535].
282 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
283 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
284 return Imm >= 0 && Imm < 65536;
286 let ParserMatchClass = Imm0_65535AsmOperand;
289 class BinOpWithFlagFrag<dag res> :
290 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
291 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
292 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
294 // An 'and' node with a single use.
295 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
296 return N->hasOneUse();
299 // An 'xor' node with a single use.
300 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
301 return N->hasOneUse();
304 // An 'fmul' node with a single use.
305 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
306 return N->hasOneUse();
309 // An 'fadd' node which checks for single non-hazardous use.
310 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
311 return hasNoVMLxHazardUse(N);
314 // An 'fsub' node which checks for single non-hazardous use.
315 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
316 return hasNoVMLxHazardUse(N);
319 //===----------------------------------------------------------------------===//
320 // Operand Definitions.
324 // FIXME: rename brtarget to t2_brtarget
325 def brtarget : Operand<OtherVT> {
326 let EncoderMethod = "getBranchTargetOpValue";
327 let OperandType = "OPERAND_PCREL";
328 let DecoderMethod = "DecodeT2BROperand";
331 // FIXME: get rid of this one?
332 def uncondbrtarget : Operand<OtherVT> {
333 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
334 let OperandType = "OPERAND_PCREL";
337 // Branch target for ARM. Handles conditional/unconditional
338 def br_target : Operand<OtherVT> {
339 let EncoderMethod = "getARMBranchTargetOpValue";
340 let OperandType = "OPERAND_PCREL";
344 // FIXME: rename bltarget to t2_bl_target?
345 def bltarget : Operand<i32> {
346 // Encoded the same as branch targets.
347 let EncoderMethod = "getBranchTargetOpValue";
348 let OperandType = "OPERAND_PCREL";
351 // Call target for ARM. Handles conditional/unconditional
352 // FIXME: rename bl_target to t2_bltarget?
353 def bl_target : Operand<i32> {
354 // Encoded the same as branch targets.
355 let EncoderMethod = "getARMBranchTargetOpValue";
356 let OperandType = "OPERAND_PCREL";
359 def blx_target : Operand<i32> {
360 // Encoded the same as branch targets.
361 let EncoderMethod = "getARMBLXTargetOpValue";
362 let OperandType = "OPERAND_PCREL";
365 // A list of registers separated by comma. Used by load/store multiple.
366 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
367 def reglist : Operand<i32> {
368 let EncoderMethod = "getRegisterListOpValue";
369 let ParserMatchClass = RegListAsmOperand;
370 let PrintMethod = "printRegisterList";
371 let DecoderMethod = "DecodeRegListOperand";
374 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
375 def dpr_reglist : Operand<i32> {
376 let EncoderMethod = "getRegisterListOpValue";
377 let ParserMatchClass = DPRRegListAsmOperand;
378 let PrintMethod = "printRegisterList";
379 let DecoderMethod = "DecodeDPRRegListOperand";
382 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
383 def spr_reglist : Operand<i32> {
384 let EncoderMethod = "getRegisterListOpValue";
385 let ParserMatchClass = SPRRegListAsmOperand;
386 let PrintMethod = "printRegisterList";
387 let DecoderMethod = "DecodeSPRRegListOperand";
390 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
391 def cpinst_operand : Operand<i32> {
392 let PrintMethod = "printCPInstOperand";
396 def pclabel : Operand<i32> {
397 let PrintMethod = "printPCLabel";
400 // ADR instruction labels.
401 def adrlabel : Operand<i32> {
402 let EncoderMethod = "getAdrLabelOpValue";
405 def neon_vcvt_imm32 : Operand<i32> {
406 let EncoderMethod = "getNEONVcvtImm32OpValue";
407 let DecoderMethod = "DecodeVCVTImmOperand";
410 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
411 def rot_imm_XFORM: SDNodeXForm<imm, [{
412 switch (N->getZExtValue()){
414 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
415 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
416 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
417 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
420 def RotImmAsmOperand : AsmOperandClass {
422 let ParserMethod = "parseRotImm";
424 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
425 int32_t v = N->getZExtValue();
426 return v == 8 || v == 16 || v == 24; }],
428 let PrintMethod = "printRotImmOperand";
429 let ParserMatchClass = RotImmAsmOperand;
432 // shift_imm: An integer that encodes a shift amount and the type of shift
433 // (asr or lsl). The 6-bit immediate encodes as:
436 // {4-0} imm5 shift amount.
437 // asr #32 encoded as imm5 == 0.
438 def ShifterImmAsmOperand : AsmOperandClass {
439 let Name = "ShifterImm";
440 let ParserMethod = "parseShifterImm";
442 def shift_imm : Operand<i32> {
443 let PrintMethod = "printShiftImmOperand";
444 let ParserMatchClass = ShifterImmAsmOperand;
447 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
448 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
449 def so_reg_reg : Operand<i32>, // reg reg imm
450 ComplexPattern<i32, 3, "SelectRegShifterOperand",
451 [shl, srl, sra, rotr]> {
452 let EncoderMethod = "getSORegRegOpValue";
453 let PrintMethod = "printSORegRegOperand";
454 let DecoderMethod = "DecodeSORegRegOperand";
455 let ParserMatchClass = ShiftedRegAsmOperand;
456 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
459 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
460 def so_reg_imm : Operand<i32>, // reg imm
461 ComplexPattern<i32, 2, "SelectImmShifterOperand",
462 [shl, srl, sra, rotr]> {
463 let EncoderMethod = "getSORegImmOpValue";
464 let PrintMethod = "printSORegImmOperand";
465 let DecoderMethod = "DecodeSORegImmOperand";
466 let ParserMatchClass = ShiftedImmAsmOperand;
467 let MIOperandInfo = (ops GPR, i32imm);
470 // FIXME: Does this need to be distinct from so_reg?
471 def shift_so_reg_reg : Operand<i32>, // reg reg imm
472 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
473 [shl,srl,sra,rotr]> {
474 let EncoderMethod = "getSORegRegOpValue";
475 let PrintMethod = "printSORegRegOperand";
476 let DecoderMethod = "DecodeSORegRegOperand";
477 let MIOperandInfo = (ops GPR, GPR, i32imm);
480 // FIXME: Does this need to be distinct from so_reg?
481 def shift_so_reg_imm : Operand<i32>, // reg reg imm
482 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
483 [shl,srl,sra,rotr]> {
484 let EncoderMethod = "getSORegImmOpValue";
485 let PrintMethod = "printSORegImmOperand";
486 let DecoderMethod = "DecodeSORegImmOperand";
487 let MIOperandInfo = (ops GPR, i32imm);
491 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
492 // 8-bit immediate rotated by an arbitrary number of bits.
493 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
494 def so_imm : Operand<i32>, ImmLeaf<i32, [{
495 return ARM_AM::getSOImmVal(Imm) != -1;
497 let EncoderMethod = "getSOImmOpValue";
498 let ParserMatchClass = SOImmAsmOperand;
499 let DecoderMethod = "DecodeSOImmOperand";
502 // Break so_imm's up into two pieces. This handles immediates with up to 16
503 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
504 // get the first/second pieces.
505 def so_imm2part : PatLeaf<(imm), [{
506 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
509 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
511 def arm_i32imm : PatLeaf<(imm), [{
512 if (Subtarget->hasV6T2Ops())
514 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
517 /// imm0_7 predicate - Immediate in the range [0,7].
518 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
519 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
520 return Imm >= 0 && Imm < 8;
522 let ParserMatchClass = Imm0_7AsmOperand;
525 /// imm0_15 predicate - Immediate in the range [0,15].
526 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
527 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
528 return Imm >= 0 && Imm < 16;
530 let ParserMatchClass = Imm0_15AsmOperand;
533 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
534 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
535 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
536 return Imm >= 0 && Imm < 32;
538 let ParserMatchClass = Imm0_31AsmOperand;
541 /// imm0_255 predicate - Immediate in the range [0,255].
542 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
543 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
544 let ParserMatchClass = Imm0_255AsmOperand;
547 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
548 // a relocatable expression.
550 // FIXME: This really needs a Thumb version separate from the ARM version.
551 // While the range is the same, and can thus use the same match class,
552 // the encoding is different so it should have a different encoder method.
553 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
554 def imm0_65535_expr : Operand<i32> {
555 let EncoderMethod = "getHiLo16ImmOpValue";
556 let ParserMatchClass = Imm0_65535ExprAsmOperand;
559 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
560 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
561 def imm24b : Operand<i32>, ImmLeaf<i32, [{
562 return Imm >= 0 && Imm <= 0xffffff;
564 let ParserMatchClass = Imm24bitAsmOperand;
568 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
570 def BitfieldAsmOperand : AsmOperandClass {
571 let Name = "Bitfield";
572 let ParserMethod = "parseBitfield";
574 def bf_inv_mask_imm : Operand<i32>,
576 return ARM::isBitFieldInvertedMask(N->getZExtValue());
578 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
579 let PrintMethod = "printBitfieldInvMaskImmOperand";
580 let DecoderMethod = "DecodeBitfieldMaskOperand";
581 let ParserMatchClass = BitfieldAsmOperand;
584 def imm1_32_XFORM: SDNodeXForm<imm, [{
585 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
587 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
588 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
589 uint64_t Imm = N->getZExtValue();
590 return Imm > 0 && Imm <= 32;
593 let PrintMethod = "printImmPlusOneOperand";
594 let ParserMatchClass = Imm1_32AsmOperand;
597 def imm1_16_XFORM: SDNodeXForm<imm, [{
598 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
600 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
601 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
603 let PrintMethod = "printImmPlusOneOperand";
604 let ParserMatchClass = Imm1_16AsmOperand;
607 // Define ARM specific addressing modes.
608 // addrmode_imm12 := reg +/- imm12
610 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
611 def addrmode_imm12 : Operand<i32>,
612 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
613 // 12-bit immediate operand. Note that instructions using this encode
614 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
615 // immediate values are as normal.
617 let EncoderMethod = "getAddrModeImm12OpValue";
618 let PrintMethod = "printAddrModeImm12Operand";
619 let DecoderMethod = "DecodeAddrModeImm12Operand";
620 let ParserMatchClass = MemImm12OffsetAsmOperand;
621 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
623 // ldst_so_reg := reg +/- reg shop imm
625 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
626 def ldst_so_reg : Operand<i32>,
627 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
628 let EncoderMethod = "getLdStSORegOpValue";
629 // FIXME: Simplify the printer
630 let PrintMethod = "printAddrMode2Operand";
631 let DecoderMethod = "DecodeSORegMemOperand";
632 let ParserMatchClass = MemRegOffsetAsmOperand;
633 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
636 // postidx_imm8 := +/- [0,255]
639 // {8} 1 is imm8 is non-negative. 0 otherwise.
640 // {7-0} [0,255] imm8 value.
641 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
642 def postidx_imm8 : Operand<i32> {
643 let PrintMethod = "printPostIdxImm8Operand";
644 let ParserMatchClass = PostIdxImm8AsmOperand;
645 let MIOperandInfo = (ops i32imm);
648 // postidx_imm8s4 := +/- [0,1020]
651 // {8} 1 is imm8 is non-negative. 0 otherwise.
652 // {7-0} [0,255] imm8 value, scaled by 4.
653 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
654 def postidx_imm8s4 : Operand<i32> {
655 let PrintMethod = "printPostIdxImm8s4Operand";
656 let ParserMatchClass = PostIdxImm8s4AsmOperand;
657 let MIOperandInfo = (ops i32imm);
661 // postidx_reg := +/- reg
663 def PostIdxRegAsmOperand : AsmOperandClass {
664 let Name = "PostIdxReg";
665 let ParserMethod = "parsePostIdxReg";
667 def postidx_reg : Operand<i32> {
668 let EncoderMethod = "getPostIdxRegOpValue";
669 let DecoderMethod = "DecodePostIdxReg";
670 let PrintMethod = "printPostIdxRegOperand";
671 let ParserMatchClass = PostIdxRegAsmOperand;
672 let MIOperandInfo = (ops GPR, i32imm);
676 // addrmode2 := reg +/- imm12
677 // := reg +/- reg shop imm
679 // FIXME: addrmode2 should be refactored the rest of the way to always
680 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
681 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
682 def addrmode2 : Operand<i32>,
683 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
684 let EncoderMethod = "getAddrMode2OpValue";
685 let PrintMethod = "printAddrMode2Operand";
686 let ParserMatchClass = AddrMode2AsmOperand;
687 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
690 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
691 let Name = "PostIdxRegShifted";
692 let ParserMethod = "parsePostIdxReg";
694 def am2offset_reg : Operand<i32>,
695 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
696 [], [SDNPWantRoot]> {
697 let EncoderMethod = "getAddrMode2OffsetOpValue";
698 let PrintMethod = "printAddrMode2OffsetOperand";
699 // When using this for assembly, it's always as a post-index offset.
700 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
701 let MIOperandInfo = (ops GPR, i32imm);
704 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
705 // the GPR is purely vestigal at this point.
706 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
707 def am2offset_imm : Operand<i32>,
708 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
709 [], [SDNPWantRoot]> {
710 let EncoderMethod = "getAddrMode2OffsetOpValue";
711 let PrintMethod = "printAddrMode2OffsetOperand";
712 let ParserMatchClass = AM2OffsetImmAsmOperand;
713 let MIOperandInfo = (ops GPR, i32imm);
717 // addrmode3 := reg +/- reg
718 // addrmode3 := reg +/- imm8
720 // FIXME: split into imm vs. reg versions.
721 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
722 def addrmode3 : Operand<i32>,
723 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
724 let EncoderMethod = "getAddrMode3OpValue";
725 let PrintMethod = "printAddrMode3Operand";
726 let ParserMatchClass = AddrMode3AsmOperand;
727 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
730 // FIXME: split into imm vs. reg versions.
731 // FIXME: parser method to handle +/- register.
732 def AM3OffsetAsmOperand : AsmOperandClass {
733 let Name = "AM3Offset";
734 let ParserMethod = "parseAM3Offset";
736 def am3offset : Operand<i32>,
737 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
738 [], [SDNPWantRoot]> {
739 let EncoderMethod = "getAddrMode3OffsetOpValue";
740 let PrintMethod = "printAddrMode3OffsetOperand";
741 let ParserMatchClass = AM3OffsetAsmOperand;
742 let MIOperandInfo = (ops GPR, i32imm);
745 // ldstm_mode := {ia, ib, da, db}
747 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
748 let EncoderMethod = "getLdStmModeOpValue";
749 let PrintMethod = "printLdStmModeOperand";
752 // addrmode5 := reg +/- imm8*4
754 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
755 def addrmode5 : Operand<i32>,
756 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
757 let PrintMethod = "printAddrMode5Operand";
758 let EncoderMethod = "getAddrMode5OpValue";
759 let DecoderMethod = "DecodeAddrMode5Operand";
760 let ParserMatchClass = AddrMode5AsmOperand;
761 let MIOperandInfo = (ops GPR:$base, i32imm);
764 // addrmode6 := reg with optional alignment
766 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
767 def addrmode6 : Operand<i32>,
768 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
769 let PrintMethod = "printAddrMode6Operand";
770 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
771 let EncoderMethod = "getAddrMode6AddressOpValue";
772 let DecoderMethod = "DecodeAddrMode6Operand";
773 let ParserMatchClass = AddrMode6AsmOperand;
776 def am6offset : Operand<i32>,
777 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
778 [], [SDNPWantRoot]> {
779 let PrintMethod = "printAddrMode6OffsetOperand";
780 let MIOperandInfo = (ops GPR);
781 let EncoderMethod = "getAddrMode6OffsetOpValue";
782 let DecoderMethod = "DecodeGPRRegisterClass";
785 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
786 // (single element from one lane) for size 32.
787 def addrmode6oneL32 : Operand<i32>,
788 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
789 let PrintMethod = "printAddrMode6Operand";
790 let MIOperandInfo = (ops GPR:$addr, i32imm);
791 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
794 // Special version of addrmode6 to handle alignment encoding for VLD-dup
795 // instructions, specifically VLD4-dup.
796 def addrmode6dup : Operand<i32>,
797 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
798 let PrintMethod = "printAddrMode6Operand";
799 let MIOperandInfo = (ops GPR:$addr, i32imm);
800 let EncoderMethod = "getAddrMode6DupAddressOpValue";
803 // addrmodepc := pc + reg
805 def addrmodepc : Operand<i32>,
806 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
807 let PrintMethod = "printAddrModePCOperand";
808 let MIOperandInfo = (ops GPR, i32imm);
811 // addr_offset_none := reg
813 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
814 def addr_offset_none : Operand<i32>,
815 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
816 let PrintMethod = "printAddrMode7Operand";
817 let DecoderMethod = "DecodeAddrMode7Operand";
818 let ParserMatchClass = MemNoOffsetAsmOperand;
819 let MIOperandInfo = (ops GPR:$base);
822 def nohash_imm : Operand<i32> {
823 let PrintMethod = "printNoHashImmediate";
826 def CoprocNumAsmOperand : AsmOperandClass {
827 let Name = "CoprocNum";
828 let ParserMethod = "parseCoprocNumOperand";
830 def p_imm : Operand<i32> {
831 let PrintMethod = "printPImmediate";
832 let ParserMatchClass = CoprocNumAsmOperand;
833 let DecoderMethod = "DecodeCoprocessor";
836 def CoprocRegAsmOperand : AsmOperandClass {
837 let Name = "CoprocReg";
838 let ParserMethod = "parseCoprocRegOperand";
840 def c_imm : Operand<i32> {
841 let PrintMethod = "printCImmediate";
842 let ParserMatchClass = CoprocRegAsmOperand;
844 def CoprocOptionAsmOperand : AsmOperandClass {
845 let Name = "CoprocOption";
846 let ParserMethod = "parseCoprocOptionOperand";
848 def coproc_option_imm : Operand<i32> {
849 let PrintMethod = "printCoprocOptionImm";
850 let ParserMatchClass = CoprocOptionAsmOperand;
853 //===----------------------------------------------------------------------===//
855 include "ARMInstrFormats.td"
857 //===----------------------------------------------------------------------===//
858 // Multiclass helpers...
861 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
862 /// binop that produces a value.
863 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
864 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
865 PatFrag opnode, string baseOpc, bit Commutable = 0> {
866 // The register-immediate version is re-materializable. This is useful
867 // in particular for taking the address of a local.
868 let isReMaterializable = 1 in {
869 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
870 iii, opc, "\t$Rd, $Rn, $imm",
871 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
876 let Inst{19-16} = Rn;
877 let Inst{15-12} = Rd;
878 let Inst{11-0} = imm;
881 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
882 iir, opc, "\t$Rd, $Rn, $Rm",
883 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
888 let isCommutable = Commutable;
889 let Inst{19-16} = Rn;
890 let Inst{15-12} = Rd;
891 let Inst{11-4} = 0b00000000;
895 def rsi : AsI1<opcod, (outs GPR:$Rd),
896 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
897 iis, opc, "\t$Rd, $Rn, $shift",
898 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
903 let Inst{19-16} = Rn;
904 let Inst{15-12} = Rd;
905 let Inst{11-5} = shift{11-5};
907 let Inst{3-0} = shift{3-0};
910 def rsr : AsI1<opcod, (outs GPR:$Rd),
911 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
912 iis, opc, "\t$Rd, $Rn, $shift",
913 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
918 let Inst{19-16} = Rn;
919 let Inst{15-12} = Rd;
920 let Inst{11-8} = shift{11-8};
922 let Inst{6-5} = shift{6-5};
924 let Inst{3-0} = shift{3-0};
927 // Assembly aliases for optional destination operand when it's the same
928 // as the source operand.
929 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
930 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
931 so_imm:$imm, pred:$p,
934 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
935 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
939 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
940 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
941 so_reg_imm:$shift, pred:$p,
944 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
945 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
946 so_reg_reg:$shift, pred:$p,
952 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
953 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
954 /// it is equivalent to the AsI1_bin_irs counterpart.
955 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
956 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
957 PatFrag opnode, string baseOpc, bit Commutable = 0> {
958 // The register-immediate version is re-materializable. This is useful
959 // in particular for taking the address of a local.
960 let isReMaterializable = 1 in {
961 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
962 iii, opc, "\t$Rd, $Rn, $imm",
963 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
968 let Inst{19-16} = Rn;
969 let Inst{15-12} = Rd;
970 let Inst{11-0} = imm;
973 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
974 iir, opc, "\t$Rd, $Rn, $Rm",
975 [/* pattern left blank */]> {
979 let Inst{11-4} = 0b00000000;
982 let Inst{15-12} = Rd;
983 let Inst{19-16} = Rn;
986 def rsi : AsI1<opcod, (outs GPR:$Rd),
987 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
988 iis, opc, "\t$Rd, $Rn, $shift",
989 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
994 let Inst{19-16} = Rn;
995 let Inst{15-12} = Rd;
996 let Inst{11-5} = shift{11-5};
998 let Inst{3-0} = shift{3-0};
1001 def rsr : AsI1<opcod, (outs GPR:$Rd),
1002 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1003 iis, opc, "\t$Rd, $Rn, $shift",
1004 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1009 let Inst{19-16} = Rn;
1010 let Inst{15-12} = Rd;
1011 let Inst{11-8} = shift{11-8};
1013 let Inst{6-5} = shift{6-5};
1015 let Inst{3-0} = shift{3-0};
1018 // Assembly aliases for optional destination operand when it's the same
1019 // as the source operand.
1020 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1021 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1022 so_imm:$imm, pred:$p,
1025 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1026 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1030 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1031 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1032 so_reg_imm:$shift, pred:$p,
1035 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1036 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1037 so_reg_reg:$shift, pred:$p,
1043 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1045 /// These opcodes will be converted to the real non-S opcodes by
1046 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1047 let hasPostISelHook = 1, Defs = [CPSR] in {
1048 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1049 InstrItinClass iis, PatFrag opnode,
1050 bit Commutable = 0> {
1051 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1053 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1055 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1057 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1058 let isCommutable = Commutable;
1060 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1061 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1063 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1064 so_reg_imm:$shift))]>;
1066 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1067 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1069 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1070 so_reg_reg:$shift))]>;
1074 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1075 /// operands are reversed.
1076 let hasPostISelHook = 1, Defs = [CPSR] in {
1077 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1078 InstrItinClass iis, PatFrag opnode,
1079 bit Commutable = 0> {
1080 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1082 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1084 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1085 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1087 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1090 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1093 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1098 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1099 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1100 /// a explicit result, only implicitly set CPSR.
1101 let isCompare = 1, Defs = [CPSR] in {
1102 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1103 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1104 PatFrag opnode, bit Commutable = 0> {
1105 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1107 [(opnode GPR:$Rn, so_imm:$imm)]> {
1112 let Inst{19-16} = Rn;
1113 let Inst{15-12} = 0b0000;
1114 let Inst{11-0} = imm;
1116 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1118 [(opnode GPR:$Rn, GPR:$Rm)]> {
1121 let isCommutable = Commutable;
1124 let Inst{19-16} = Rn;
1125 let Inst{15-12} = 0b0000;
1126 let Inst{11-4} = 0b00000000;
1129 def rsi : AI1<opcod, (outs),
1130 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1131 opc, "\t$Rn, $shift",
1132 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1137 let Inst{19-16} = Rn;
1138 let Inst{15-12} = 0b0000;
1139 let Inst{11-5} = shift{11-5};
1141 let Inst{3-0} = shift{3-0};
1143 def rsr : AI1<opcod, (outs),
1144 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1145 opc, "\t$Rn, $shift",
1146 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1151 let Inst{19-16} = Rn;
1152 let Inst{15-12} = 0b0000;
1153 let Inst{11-8} = shift{11-8};
1155 let Inst{6-5} = shift{6-5};
1157 let Inst{3-0} = shift{3-0};
1163 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1164 /// register and one whose operand is a register rotated by 8/16/24.
1165 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1166 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1167 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1168 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1169 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1170 Requires<[IsARM, HasV6]> {
1174 let Inst{19-16} = 0b1111;
1175 let Inst{15-12} = Rd;
1176 let Inst{11-10} = rot;
1180 class AI_ext_rrot_np<bits<8> opcod, string opc>
1181 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1182 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1183 Requires<[IsARM, HasV6]> {
1185 let Inst{19-16} = 0b1111;
1186 let Inst{11-10} = rot;
1189 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1190 /// register and one whose operand is a register rotated by 8/16/24.
1191 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1192 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1193 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1194 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1195 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1196 Requires<[IsARM, HasV6]> {
1201 let Inst{19-16} = Rn;
1202 let Inst{15-12} = Rd;
1203 let Inst{11-10} = rot;
1204 let Inst{9-4} = 0b000111;
1208 class AI_exta_rrot_np<bits<8> opcod, string opc>
1209 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1210 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1211 Requires<[IsARM, HasV6]> {
1214 let Inst{19-16} = Rn;
1215 let Inst{11-10} = rot;
1218 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1219 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1220 string baseOpc, bit Commutable = 0> {
1221 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1222 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1223 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1224 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1230 let Inst{15-12} = Rd;
1231 let Inst{19-16} = Rn;
1232 let Inst{11-0} = imm;
1234 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1235 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1236 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1241 let Inst{11-4} = 0b00000000;
1243 let isCommutable = Commutable;
1245 let Inst{15-12} = Rd;
1246 let Inst{19-16} = Rn;
1248 def rsi : AsI1<opcod, (outs GPR:$Rd),
1249 (ins GPR:$Rn, so_reg_imm:$shift),
1250 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1251 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1257 let Inst{19-16} = Rn;
1258 let Inst{15-12} = Rd;
1259 let Inst{11-5} = shift{11-5};
1261 let Inst{3-0} = shift{3-0};
1263 def rsr : AsI1<opcod, (outs GPR:$Rd),
1264 (ins GPR:$Rn, so_reg_reg:$shift),
1265 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1266 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1272 let Inst{19-16} = Rn;
1273 let Inst{15-12} = Rd;
1274 let Inst{11-8} = shift{11-8};
1276 let Inst{6-5} = shift{6-5};
1278 let Inst{3-0} = shift{3-0};
1282 // Assembly aliases for optional destination operand when it's the same
1283 // as the source operand.
1284 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1285 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1286 so_imm:$imm, pred:$p,
1289 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1290 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1294 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1295 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1296 so_reg_imm:$shift, pred:$p,
1299 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1300 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1301 so_reg_reg:$shift, pred:$p,
1306 /// AI1_rsc_irs - Define instructions and patterns for rsc
1307 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1309 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1310 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1311 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1312 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1318 let Inst{15-12} = Rd;
1319 let Inst{19-16} = Rn;
1320 let Inst{11-0} = imm;
1322 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1323 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1324 [/* pattern left blank */]> {
1328 let Inst{11-4} = 0b00000000;
1331 let Inst{15-12} = Rd;
1332 let Inst{19-16} = Rn;
1334 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1335 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1336 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1342 let Inst{19-16} = Rn;
1343 let Inst{15-12} = Rd;
1344 let Inst{11-5} = shift{11-5};
1346 let Inst{3-0} = shift{3-0};
1348 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1349 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1350 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1356 let Inst{19-16} = Rn;
1357 let Inst{15-12} = Rd;
1358 let Inst{11-8} = shift{11-8};
1360 let Inst{6-5} = shift{6-5};
1362 let Inst{3-0} = shift{3-0};
1366 // Assembly aliases for optional destination operand when it's the same
1367 // as the source operand.
1368 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1369 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1370 so_imm:$imm, pred:$p,
1373 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1374 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1378 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1379 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1380 so_reg_imm:$shift, pred:$p,
1383 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1384 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1385 so_reg_reg:$shift, pred:$p,
1390 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1391 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1392 InstrItinClass iir, PatFrag opnode> {
1393 // Note: We use the complex addrmode_imm12 rather than just an input
1394 // GPR and a constrained immediate so that we can use this to match
1395 // frame index references and avoid matching constant pool references.
1396 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1397 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1398 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1401 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1402 let Inst{19-16} = addr{16-13}; // Rn
1403 let Inst{15-12} = Rt;
1404 let Inst{11-0} = addr{11-0}; // imm12
1406 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1407 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1408 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1411 let shift{4} = 0; // Inst{4} = 0
1412 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1413 let Inst{19-16} = shift{16-13}; // Rn
1414 let Inst{15-12} = Rt;
1415 let Inst{11-0} = shift{11-0};
1420 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1421 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1422 InstrItinClass iir, PatFrag opnode> {
1423 // Note: We use the complex addrmode_imm12 rather than just an input
1424 // GPR and a constrained immediate so that we can use this to match
1425 // frame index references and avoid matching constant pool references.
1426 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1427 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1428 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1431 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1432 let Inst{19-16} = addr{16-13}; // Rn
1433 let Inst{15-12} = Rt;
1434 let Inst{11-0} = addr{11-0}; // imm12
1436 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1437 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1438 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1441 let shift{4} = 0; // Inst{4} = 0
1442 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1443 let Inst{19-16} = shift{16-13}; // Rn
1444 let Inst{15-12} = Rt;
1445 let Inst{11-0} = shift{11-0};
1451 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1452 InstrItinClass iir, PatFrag opnode> {
1453 // Note: We use the complex addrmode_imm12 rather than just an input
1454 // GPR and a constrained immediate so that we can use this to match
1455 // frame index references and avoid matching constant pool references.
1456 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1457 (ins GPR:$Rt, addrmode_imm12:$addr),
1458 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1459 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1462 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1463 let Inst{19-16} = addr{16-13}; // Rn
1464 let Inst{15-12} = Rt;
1465 let Inst{11-0} = addr{11-0}; // imm12
1467 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1468 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1469 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1472 let shift{4} = 0; // Inst{4} = 0
1473 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1474 let Inst{19-16} = shift{16-13}; // Rn
1475 let Inst{15-12} = Rt;
1476 let Inst{11-0} = shift{11-0};
1480 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1481 InstrItinClass iir, PatFrag opnode> {
1482 // Note: We use the complex addrmode_imm12 rather than just an input
1483 // GPR and a constrained immediate so that we can use this to match
1484 // frame index references and avoid matching constant pool references.
1485 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1486 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1487 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1488 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1491 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1492 let Inst{19-16} = addr{16-13}; // Rn
1493 let Inst{15-12} = Rt;
1494 let Inst{11-0} = addr{11-0}; // imm12
1496 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1497 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1498 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1501 let shift{4} = 0; // Inst{4} = 0
1502 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1503 let Inst{19-16} = shift{16-13}; // Rn
1504 let Inst{15-12} = Rt;
1505 let Inst{11-0} = shift{11-0};
1510 //===----------------------------------------------------------------------===//
1512 //===----------------------------------------------------------------------===//
1514 //===----------------------------------------------------------------------===//
1515 // Miscellaneous Instructions.
1518 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1519 /// the function. The first operand is the ID# for this instruction, the second
1520 /// is the index into the MachineConstantPool that this is, the third is the
1521 /// size in bytes of this constant pool entry.
1522 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1523 def CONSTPOOL_ENTRY :
1524 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1525 i32imm:$size), NoItinerary, []>;
1527 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1528 // from removing one half of the matched pairs. That breaks PEI, which assumes
1529 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1530 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1531 def ADJCALLSTACKUP :
1532 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1533 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1535 def ADJCALLSTACKDOWN :
1536 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1537 [(ARMcallseq_start timm:$amt)]>;
1540 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1541 // (These psuedos use a hand-written selection code).
1542 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1543 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1544 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1546 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1547 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1549 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1550 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1552 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1553 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1555 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1556 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1558 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1559 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1561 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1562 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1564 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1565 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1566 GPR:$set1, GPR:$set2),
1570 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1571 Requires<[IsARM, HasV6T2]> {
1572 let Inst{27-16} = 0b001100100000;
1573 let Inst{15-8} = 0b11110000;
1574 let Inst{7-0} = 0b00000000;
1577 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1578 Requires<[IsARM, HasV6T2]> {
1579 let Inst{27-16} = 0b001100100000;
1580 let Inst{15-8} = 0b11110000;
1581 let Inst{7-0} = 0b00000001;
1584 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1585 Requires<[IsARM, HasV6T2]> {
1586 let Inst{27-16} = 0b001100100000;
1587 let Inst{15-8} = 0b11110000;
1588 let Inst{7-0} = 0b00000010;
1591 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1592 Requires<[IsARM, HasV6T2]> {
1593 let Inst{27-16} = 0b001100100000;
1594 let Inst{15-8} = 0b11110000;
1595 let Inst{7-0} = 0b00000011;
1598 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1599 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1604 let Inst{15-12} = Rd;
1605 let Inst{19-16} = Rn;
1606 let Inst{27-20} = 0b01101000;
1607 let Inst{7-4} = 0b1011;
1608 let Inst{11-8} = 0b1111;
1611 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1612 []>, Requires<[IsARM, HasV6T2]> {
1613 let Inst{27-16} = 0b001100100000;
1614 let Inst{15-8} = 0b11110000;
1615 let Inst{7-0} = 0b00000100;
1618 // The i32imm operand $val can be used by a debugger to store more information
1619 // about the breakpoint.
1620 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1621 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1623 let Inst{3-0} = val{3-0};
1624 let Inst{19-8} = val{15-4};
1625 let Inst{27-20} = 0b00010010;
1626 let Inst{7-4} = 0b0111;
1629 // Change Processor State
1630 // FIXME: We should use InstAlias to handle the optional operands.
1631 class CPS<dag iops, string asm_ops>
1632 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1633 []>, Requires<[IsARM]> {
1639 let Inst{31-28} = 0b1111;
1640 let Inst{27-20} = 0b00010000;
1641 let Inst{19-18} = imod;
1642 let Inst{17} = M; // Enabled if mode is set;
1644 let Inst{8-6} = iflags;
1646 let Inst{4-0} = mode;
1649 let DecoderMethod = "DecodeCPSInstruction" in {
1651 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1652 "$imod\t$iflags, $mode">;
1653 let mode = 0, M = 0 in
1654 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1656 let imod = 0, iflags = 0, M = 1 in
1657 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1660 // Preload signals the memory system of possible future data/instruction access.
1661 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1663 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1664 !strconcat(opc, "\t$addr"),
1665 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1668 let Inst{31-26} = 0b111101;
1669 let Inst{25} = 0; // 0 for immediate form
1670 let Inst{24} = data;
1671 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1672 let Inst{22} = read;
1673 let Inst{21-20} = 0b01;
1674 let Inst{19-16} = addr{16-13}; // Rn
1675 let Inst{15-12} = 0b1111;
1676 let Inst{11-0} = addr{11-0}; // imm12
1679 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1680 !strconcat(opc, "\t$shift"),
1681 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1683 let Inst{31-26} = 0b111101;
1684 let Inst{25} = 1; // 1 for register form
1685 let Inst{24} = data;
1686 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1687 let Inst{22} = read;
1688 let Inst{21-20} = 0b01;
1689 let Inst{19-16} = shift{16-13}; // Rn
1690 let Inst{15-12} = 0b1111;
1691 let Inst{11-0} = shift{11-0};
1696 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1697 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1698 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1700 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1701 "setend\t$end", []>, Requires<[IsARM]> {
1703 let Inst{31-10} = 0b1111000100000001000000;
1708 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1709 []>, Requires<[IsARM, HasV7]> {
1711 let Inst{27-4} = 0b001100100000111100001111;
1712 let Inst{3-0} = opt;
1715 // A5.4 Permanently UNDEFINED instructions.
1716 let isBarrier = 1, isTerminator = 1 in
1717 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1720 let Inst = 0xe7ffdefe;
1723 // Address computation and loads and stores in PIC mode.
1724 let isNotDuplicable = 1 in {
1725 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1727 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1729 let AddedComplexity = 10 in {
1730 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1732 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1734 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1736 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1738 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1740 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1742 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1744 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1746 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1748 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1750 let AddedComplexity = 10 in {
1751 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1752 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1754 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1755 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1756 addrmodepc:$addr)]>;
1758 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1759 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1761 } // isNotDuplicable = 1
1764 // LEApcrel - Load a pc-relative address into a register without offending the
1766 let neverHasSideEffects = 1, isReMaterializable = 1 in
1767 // The 'adr' mnemonic encodes differently if the label is before or after
1768 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1769 // know until then which form of the instruction will be used.
1770 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1771 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1774 let Inst{27-25} = 0b001;
1776 let Inst{23-22} = label{13-12};
1779 let Inst{19-16} = 0b1111;
1780 let Inst{15-12} = Rd;
1781 let Inst{11-0} = label{11-0};
1783 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1786 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1787 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1790 //===----------------------------------------------------------------------===//
1791 // Control Flow Instructions.
1794 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1796 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1797 "bx", "\tlr", [(ARMretflag)]>,
1798 Requires<[IsARM, HasV4T]> {
1799 let Inst{27-0} = 0b0001001011111111111100011110;
1803 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1804 "mov", "\tpc, lr", [(ARMretflag)]>,
1805 Requires<[IsARM, NoV4T]> {
1806 let Inst{27-0} = 0b0001101000001111000000001110;
1810 // Indirect branches
1811 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1813 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1814 [(brind GPR:$dst)]>,
1815 Requires<[IsARM, HasV4T]> {
1817 let Inst{31-4} = 0b1110000100101111111111110001;
1818 let Inst{3-0} = dst;
1821 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1822 "bx", "\t$dst", [/* pattern left blank */]>,
1823 Requires<[IsARM, HasV4T]> {
1825 let Inst{27-4} = 0b000100101111111111110001;
1826 let Inst{3-0} = dst;
1830 // All calls clobber the non-callee saved registers. SP is marked as
1831 // a use to prevent stack-pointer assignments that appear immediately
1832 // before calls from potentially appearing dead.
1834 // On non-Darwin platforms R9 is callee-saved.
1835 // FIXME: Do we really need a non-predicated version? If so, it should
1836 // at least be a pseudo instruction expanding to the predicated version
1837 // at MC lowering time.
1838 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1840 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1841 IIC_Br, "bl\t$func",
1842 [(ARMcall tglobaladdr:$func)]>,
1843 Requires<[IsARM, IsNotDarwin]> {
1844 let Inst{31-28} = 0b1110;
1846 let Inst{23-0} = func;
1847 let DecoderMethod = "DecodeBranchImmInstruction";
1850 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1851 IIC_Br, "bl", "\t$func",
1852 [(ARMcall_pred tglobaladdr:$func)]>,
1853 Requires<[IsARM, IsNotDarwin]> {
1855 let Inst{23-0} = func;
1856 let DecoderMethod = "DecodeBranchImmInstruction";
1860 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1861 IIC_Br, "blx\t$func",
1862 [(ARMcall GPR:$func)]>,
1863 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1865 let Inst{31-4} = 0b1110000100101111111111110011;
1866 let Inst{3-0} = func;
1869 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1870 IIC_Br, "blx", "\t$func",
1871 [(ARMcall_pred GPR:$func)]>,
1872 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1874 let Inst{27-4} = 0b000100101111111111110011;
1875 let Inst{3-0} = func;
1879 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1880 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1881 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1882 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1885 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1886 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1887 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1891 // On Darwin R9 is call-clobbered.
1892 // R7 is marked as a use to prevent frame-pointer assignments from being
1893 // moved above / below calls.
1894 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1895 Uses = [R7, SP] in {
1896 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1898 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1899 Requires<[IsARM, IsDarwin]>;
1901 def BLr9_pred : ARMPseudoExpand<(outs),
1902 (ins bl_target:$func, pred:$p, variable_ops),
1904 [(ARMcall_pred tglobaladdr:$func)],
1905 (BL_pred bl_target:$func, pred:$p)>,
1906 Requires<[IsARM, IsDarwin]>;
1909 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1911 [(ARMcall GPR:$func)],
1913 Requires<[IsARM, HasV5T, IsDarwin]>;
1915 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1917 [(ARMcall_pred GPR:$func)],
1918 (BLX_pred GPR:$func, pred:$p)>,
1919 Requires<[IsARM, HasV5T, IsDarwin]>;
1922 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1923 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1924 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1925 Requires<[IsARM, HasV4T, IsDarwin]>;
1928 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1929 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1930 Requires<[IsARM, NoV4T, IsDarwin]>;
1933 let isBranch = 1, isTerminator = 1 in {
1934 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1935 // a two-value operand where a dag node expects two operands. :(
1936 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1937 IIC_Br, "b", "\t$target",
1938 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1940 let Inst{23-0} = target;
1941 let DecoderMethod = "DecodeBranchImmInstruction";
1944 let isBarrier = 1 in {
1945 // B is "predicable" since it's just a Bcc with an 'always' condition.
1946 let isPredicable = 1 in
1947 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1948 // should be sufficient.
1949 // FIXME: Is B really a Barrier? That doesn't seem right.
1950 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1951 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1953 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1954 def BR_JTr : ARMPseudoInst<(outs),
1955 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1957 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1958 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1959 // into i12 and rs suffixed versions.
1960 def BR_JTm : ARMPseudoInst<(outs),
1961 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1963 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1965 def BR_JTadd : ARMPseudoInst<(outs),
1966 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1968 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1970 } // isNotDuplicable = 1, isIndirectBranch = 1
1976 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1977 "blx\t$target", []>,
1978 Requires<[IsARM, HasV5T]> {
1979 let Inst{31-25} = 0b1111101;
1981 let Inst{23-0} = target{24-1};
1982 let Inst{24} = target{0};
1985 // Branch and Exchange Jazelle
1986 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1987 [/* pattern left blank */]> {
1989 let Inst{23-20} = 0b0010;
1990 let Inst{19-8} = 0xfff;
1991 let Inst{7-4} = 0b0010;
1992 let Inst{3-0} = func;
1997 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1999 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2001 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2002 IIC_Br, []>, Requires<[IsDarwin]>;
2004 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2005 IIC_Br, []>, Requires<[IsDarwin]>;
2007 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2009 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2010 Requires<[IsARM, IsDarwin]>;
2012 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2015 Requires<[IsARM, IsDarwin]>;
2019 // Non-Darwin versions (the difference is R9).
2020 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2022 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2023 IIC_Br, []>, Requires<[IsNotDarwin]>;
2025 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2026 IIC_Br, []>, Requires<[IsNotDarwin]>;
2028 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2030 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2031 Requires<[IsARM, IsNotDarwin]>;
2033 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2036 Requires<[IsARM, IsNotDarwin]>;
2040 // Secure Monitor Call is a system instruction.
2041 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2044 let Inst{23-4} = 0b01100000000000000111;
2045 let Inst{3-0} = opt;
2048 // Supervisor Call (Software Interrupt)
2049 let isCall = 1, Uses = [SP] in {
2050 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2052 let Inst{23-0} = svc;
2056 // Store Return State
2057 class SRSI<bit wb, string asm>
2058 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2059 NoItinerary, asm, "", []> {
2061 let Inst{31-28} = 0b1111;
2062 let Inst{27-25} = 0b100;
2066 let Inst{19-16} = 0b1101; // SP
2067 let Inst{15-5} = 0b00000101000;
2068 let Inst{4-0} = mode;
2071 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2072 let Inst{24-23} = 0;
2074 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2075 let Inst{24-23} = 0;
2077 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2078 let Inst{24-23} = 0b10;
2080 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2081 let Inst{24-23} = 0b10;
2083 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2084 let Inst{24-23} = 0b01;
2086 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2087 let Inst{24-23} = 0b01;
2089 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2090 let Inst{24-23} = 0b11;
2092 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2093 let Inst{24-23} = 0b11;
2096 // Return From Exception
2097 class RFEI<bit wb, string asm>
2098 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2099 NoItinerary, asm, "", []> {
2101 let Inst{31-28} = 0b1111;
2102 let Inst{27-25} = 0b100;
2106 let Inst{19-16} = Rn;
2107 let Inst{15-0} = 0xa00;
2110 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2111 let Inst{24-23} = 0;
2113 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2114 let Inst{24-23} = 0;
2116 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2117 let Inst{24-23} = 0b10;
2119 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2120 let Inst{24-23} = 0b10;
2122 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2123 let Inst{24-23} = 0b01;
2125 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2126 let Inst{24-23} = 0b01;
2128 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2129 let Inst{24-23} = 0b11;
2131 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2132 let Inst{24-23} = 0b11;
2135 //===----------------------------------------------------------------------===//
2136 // Load / Store Instructions.
2142 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2143 UnOpFrag<(load node:$Src)>>;
2144 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2145 UnOpFrag<(zextloadi8 node:$Src)>>;
2146 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2147 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2148 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2149 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2151 // Special LDR for loads from non-pc-relative constpools.
2152 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2153 isReMaterializable = 1, isCodeGenOnly = 1 in
2154 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2155 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2159 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2160 let Inst{19-16} = 0b1111;
2161 let Inst{15-12} = Rt;
2162 let Inst{11-0} = addr{11-0}; // imm12
2165 // Loads with zero extension
2166 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2167 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2168 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2170 // Loads with sign extension
2171 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2172 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2173 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2175 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2176 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2177 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2179 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2181 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2182 (ins addrmode3:$addr), LdMiscFrm,
2183 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2184 []>, Requires<[IsARM, HasV5TE]>;
2188 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2189 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2190 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2191 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2194 let Inst{23} = addr{12};
2195 let Inst{19-16} = addr{16-13};
2196 let Inst{11-0} = addr{11-0};
2197 let DecoderMethod = "DecodeLDRPreImm";
2198 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2201 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2202 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2203 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2206 let Inst{23} = addr{12};
2207 let Inst{19-16} = addr{16-13};
2208 let Inst{11-0} = addr{11-0};
2210 let DecoderMethod = "DecodeLDRPreReg";
2211 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2214 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2215 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2216 IndexModePost, LdFrm, itin,
2217 opc, "\t$Rt, $addr, $offset",
2218 "$addr.base = $Rn_wb", []> {
2224 let Inst{23} = offset{12};
2225 let Inst{19-16} = addr;
2226 let Inst{11-0} = offset{11-0};
2228 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2231 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2232 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2233 IndexModePost, LdFrm, itin,
2234 opc, "\t$Rt, $addr, $offset",
2235 "$addr.base = $Rn_wb", []> {
2241 let Inst{23} = offset{12};
2242 let Inst{19-16} = addr;
2243 let Inst{11-0} = offset{11-0};
2245 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2250 let mayLoad = 1, neverHasSideEffects = 1 in {
2251 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2252 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2255 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2256 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2257 (ins addrmode3:$addr), IndexModePre,
2259 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2261 let Inst{23} = addr{8}; // U bit
2262 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2263 let Inst{19-16} = addr{12-9}; // Rn
2264 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2265 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2266 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2267 let DecoderMethod = "DecodeAddrMode3Instruction";
2269 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2270 (ins addr_offset_none:$addr, am3offset:$offset),
2271 IndexModePost, LdMiscFrm, itin,
2272 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2276 let Inst{23} = offset{8}; // U bit
2277 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2278 let Inst{19-16} = addr;
2279 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2280 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2281 let DecoderMethod = "DecodeAddrMode3Instruction";
2285 let mayLoad = 1, neverHasSideEffects = 1 in {
2286 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2287 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2288 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2289 let hasExtraDefRegAllocReq = 1 in {
2290 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2291 (ins addrmode3:$addr), IndexModePre,
2292 LdMiscFrm, IIC_iLoad_d_ru,
2293 "ldrd", "\t$Rt, $Rt2, $addr!",
2294 "$addr.base = $Rn_wb", []> {
2296 let Inst{23} = addr{8}; // U bit
2297 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2298 let Inst{19-16} = addr{12-9}; // Rn
2299 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2300 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2301 let DecoderMethod = "DecodeAddrMode3Instruction";
2302 let AsmMatchConverter = "cvtLdrdPre";
2304 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2305 (ins addr_offset_none:$addr, am3offset:$offset),
2306 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2307 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2308 "$addr.base = $Rn_wb", []> {
2311 let Inst{23} = offset{8}; // U bit
2312 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2313 let Inst{19-16} = addr;
2314 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2315 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2316 let DecoderMethod = "DecodeAddrMode3Instruction";
2318 } // hasExtraDefRegAllocReq = 1
2319 } // mayLoad = 1, neverHasSideEffects = 1
2321 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2322 let mayLoad = 1, neverHasSideEffects = 1 in {
2323 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2324 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2325 IndexModePost, LdFrm, IIC_iLoad_ru,
2326 "ldrt", "\t$Rt, $addr, $offset",
2327 "$addr.base = $Rn_wb", []> {
2333 let Inst{23} = offset{12};
2334 let Inst{21} = 1; // overwrite
2335 let Inst{19-16} = addr;
2336 let Inst{11-5} = offset{11-5};
2338 let Inst{3-0} = offset{3-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2343 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2344 IndexModePost, LdFrm, IIC_iLoad_ru,
2345 "ldrt", "\t$Rt, $addr, $offset",
2346 "$addr.base = $Rn_wb", []> {
2352 let Inst{23} = offset{12};
2353 let Inst{21} = 1; // overwrite
2354 let Inst{19-16} = addr;
2355 let Inst{11-0} = offset{11-0};
2356 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2359 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2360 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2361 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2362 "ldrbt", "\t$Rt, $addr, $offset",
2363 "$addr.base = $Rn_wb", []> {
2369 let Inst{23} = offset{12};
2370 let Inst{21} = 1; // overwrite
2371 let Inst{19-16} = addr;
2372 let Inst{11-5} = offset{11-5};
2374 let Inst{3-0} = offset{3-0};
2375 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2378 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2379 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2380 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2381 "ldrbt", "\t$Rt, $addr, $offset",
2382 "$addr.base = $Rn_wb", []> {
2388 let Inst{23} = offset{12};
2389 let Inst{21} = 1; // overwrite
2390 let Inst{19-16} = addr;
2391 let Inst{11-0} = offset{11-0};
2392 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2395 multiclass AI3ldrT<bits<4> op, string opc> {
2396 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2397 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2398 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2399 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2401 let Inst{23} = offset{8};
2403 let Inst{11-8} = offset{7-4};
2404 let Inst{3-0} = offset{3-0};
2405 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2407 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2408 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2409 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2410 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2412 let Inst{23} = Rm{4};
2415 let Inst{3-0} = Rm{3-0};
2416 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2420 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2421 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2422 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2427 // Stores with truncate
2428 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2429 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2430 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2433 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2434 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2435 StMiscFrm, IIC_iStore_d_r,
2436 "strd", "\t$Rt, $src2, $addr", []>,
2437 Requires<[IsARM, HasV5TE]> {
2442 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2443 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2444 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2446 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2449 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2450 let Inst{19-16} = addr{16-13}; // Rn
2451 let Inst{11-0} = addr{11-0}; // imm12
2452 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2453 let DecoderMethod = "DecodeSTRPreImm";
2456 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2457 (ins GPR:$Rt, ldst_so_reg:$addr),
2458 IndexModePre, StFrm, itin,
2459 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2462 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2463 let Inst{19-16} = addr{16-13}; // Rn
2464 let Inst{11-0} = addr{11-0};
2465 let Inst{4} = 0; // Inst{4} = 0
2466 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2467 let DecoderMethod = "DecodeSTRPreReg";
2469 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2470 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2471 IndexModePost, StFrm, itin,
2472 opc, "\t$Rt, $addr, $offset",
2473 "$addr.base = $Rn_wb", []> {
2479 let Inst{23} = offset{12};
2480 let Inst{19-16} = addr;
2481 let Inst{11-0} = offset{11-0};
2483 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2486 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2487 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2488 IndexModePost, StFrm, itin,
2489 opc, "\t$Rt, $addr, $offset",
2490 "$addr.base = $Rn_wb", []> {
2496 let Inst{23} = offset{12};
2497 let Inst{19-16} = addr;
2498 let Inst{11-0} = offset{11-0};
2500 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2504 let mayStore = 1, neverHasSideEffects = 1 in {
2505 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2506 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2509 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2510 am2offset_reg:$offset),
2511 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2512 am2offset_reg:$offset)>;
2513 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2514 am2offset_imm:$offset),
2515 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2516 am2offset_imm:$offset)>;
2517 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2518 am2offset_reg:$offset),
2519 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2520 am2offset_reg:$offset)>;
2521 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2522 am2offset_imm:$offset),
2523 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2524 am2offset_imm:$offset)>;
2526 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2527 // put the patterns on the instruction definitions directly as ISel wants
2528 // the address base and offset to be separate operands, not a single
2529 // complex operand like we represent the instructions themselves. The
2530 // pseudos map between the two.
2531 let usesCustomInserter = 1,
2532 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2533 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2534 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2537 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2538 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2539 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2542 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2543 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2544 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2547 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2548 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2549 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2552 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2553 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2554 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2557 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2562 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2563 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2564 StMiscFrm, IIC_iStore_bh_ru,
2565 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2567 let Inst{23} = addr{8}; // U bit
2568 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2569 let Inst{19-16} = addr{12-9}; // Rn
2570 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2571 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2572 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2573 let DecoderMethod = "DecodeAddrMode3Instruction";
2576 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2577 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2578 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2579 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2580 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2581 addr_offset_none:$addr,
2582 am3offset:$offset))]> {
2585 let Inst{23} = offset{8}; // U bit
2586 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2587 let Inst{19-16} = addr;
2588 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2589 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2590 let DecoderMethod = "DecodeAddrMode3Instruction";
2593 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2594 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2595 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2596 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2597 "strd", "\t$Rt, $Rt2, $addr!",
2598 "$addr.base = $Rn_wb", []> {
2600 let Inst{23} = addr{8}; // U bit
2601 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2602 let Inst{19-16} = addr{12-9}; // Rn
2603 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2604 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2605 let DecoderMethod = "DecodeAddrMode3Instruction";
2606 let AsmMatchConverter = "cvtStrdPre";
2609 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2610 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2612 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2613 "strd", "\t$Rt, $Rt2, $addr, $offset",
2614 "$addr.base = $Rn_wb", []> {
2617 let Inst{23} = offset{8}; // U bit
2618 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2619 let Inst{19-16} = addr;
2620 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2621 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2622 let DecoderMethod = "DecodeAddrMode3Instruction";
2624 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2626 // STRT, STRBT, and STRHT
2628 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2629 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2630 IndexModePost, StFrm, IIC_iStore_bh_ru,
2631 "strbt", "\t$Rt, $addr, $offset",
2632 "$addr.base = $Rn_wb", []> {
2638 let Inst{23} = offset{12};
2639 let Inst{21} = 1; // overwrite
2640 let Inst{19-16} = addr;
2641 let Inst{11-5} = offset{11-5};
2643 let Inst{3-0} = offset{3-0};
2644 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2647 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2648 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2649 IndexModePost, StFrm, IIC_iStore_bh_ru,
2650 "strbt", "\t$Rt, $addr, $offset",
2651 "$addr.base = $Rn_wb", []> {
2657 let Inst{23} = offset{12};
2658 let Inst{21} = 1; // overwrite
2659 let Inst{19-16} = addr;
2660 let Inst{11-0} = offset{11-0};
2661 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2664 let mayStore = 1, neverHasSideEffects = 1 in {
2665 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2667 IndexModePost, StFrm, IIC_iStore_ru,
2668 "strt", "\t$Rt, $addr, $offset",
2669 "$addr.base = $Rn_wb", []> {
2675 let Inst{23} = offset{12};
2676 let Inst{21} = 1; // overwrite
2677 let Inst{19-16} = addr;
2678 let Inst{11-5} = offset{11-5};
2680 let Inst{3-0} = offset{3-0};
2681 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2684 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2685 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2686 IndexModePost, StFrm, IIC_iStore_ru,
2687 "strt", "\t$Rt, $addr, $offset",
2688 "$addr.base = $Rn_wb", []> {
2694 let Inst{23} = offset{12};
2695 let Inst{21} = 1; // overwrite
2696 let Inst{19-16} = addr;
2697 let Inst{11-0} = offset{11-0};
2698 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2703 multiclass AI3strT<bits<4> op, string opc> {
2704 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2705 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2706 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2707 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2709 let Inst{23} = offset{8};
2711 let Inst{11-8} = offset{7-4};
2712 let Inst{3-0} = offset{3-0};
2713 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2715 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2716 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2717 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2718 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2720 let Inst{23} = Rm{4};
2723 let Inst{3-0} = Rm{3-0};
2724 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2729 defm STRHT : AI3strT<0b1011, "strht">;
2732 //===----------------------------------------------------------------------===//
2733 // Load / store multiple Instructions.
2736 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2737 InstrItinClass itin, InstrItinClass itin_upd> {
2738 // IA is the default, so no need for an explicit suffix on the
2739 // mnemonic here. Without it is the cannonical spelling.
2741 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2742 IndexModeNone, f, itin,
2743 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2744 let Inst{24-23} = 0b01; // Increment After
2745 let Inst{21} = 0; // No writeback
2746 let Inst{20} = L_bit;
2749 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2750 IndexModeUpd, f, itin_upd,
2751 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2752 let Inst{24-23} = 0b01; // Increment After
2753 let Inst{21} = 1; // Writeback
2754 let Inst{20} = L_bit;
2756 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2759 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2760 IndexModeNone, f, itin,
2761 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2762 let Inst{24-23} = 0b00; // Decrement After
2763 let Inst{21} = 0; // No writeback
2764 let Inst{20} = L_bit;
2767 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2768 IndexModeUpd, f, itin_upd,
2769 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2770 let Inst{24-23} = 0b00; // Decrement After
2771 let Inst{21} = 1; // Writeback
2772 let Inst{20} = L_bit;
2774 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2777 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2778 IndexModeNone, f, itin,
2779 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2780 let Inst{24-23} = 0b10; // Decrement Before
2781 let Inst{21} = 0; // No writeback
2782 let Inst{20} = L_bit;
2785 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2786 IndexModeUpd, f, itin_upd,
2787 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2788 let Inst{24-23} = 0b10; // Decrement Before
2789 let Inst{21} = 1; // Writeback
2790 let Inst{20} = L_bit;
2792 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2795 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2796 IndexModeNone, f, itin,
2797 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2798 let Inst{24-23} = 0b11; // Increment Before
2799 let Inst{21} = 0; // No writeback
2800 let Inst{20} = L_bit;
2803 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2804 IndexModeUpd, f, itin_upd,
2805 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2806 let Inst{24-23} = 0b11; // Increment Before
2807 let Inst{21} = 1; // Writeback
2808 let Inst{20} = L_bit;
2810 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2814 let neverHasSideEffects = 1 in {
2816 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2817 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2819 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2820 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2822 } // neverHasSideEffects
2824 // FIXME: remove when we have a way to marking a MI with these properties.
2825 // FIXME: Should pc be an implicit operand like PICADD, etc?
2826 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2827 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2828 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2829 reglist:$regs, variable_ops),
2830 4, IIC_iLoad_mBr, [],
2831 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2832 RegConstraint<"$Rn = $wb">;
2834 //===----------------------------------------------------------------------===//
2835 // Move Instructions.
2838 let neverHasSideEffects = 1 in
2839 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2840 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2844 let Inst{19-16} = 0b0000;
2845 let Inst{11-4} = 0b00000000;
2848 let Inst{15-12} = Rd;
2851 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2852 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2854 // A version for the smaller set of tail call registers.
2855 let neverHasSideEffects = 1 in
2856 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2857 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2861 let Inst{11-4} = 0b00000000;
2864 let Inst{15-12} = Rd;
2867 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2868 DPSoRegRegFrm, IIC_iMOVsr,
2869 "mov", "\t$Rd, $src",
2870 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2873 let Inst{15-12} = Rd;
2874 let Inst{19-16} = 0b0000;
2875 let Inst{11-8} = src{11-8};
2877 let Inst{6-5} = src{6-5};
2879 let Inst{3-0} = src{3-0};
2883 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2884 DPSoRegImmFrm, IIC_iMOVsr,
2885 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2889 let Inst{15-12} = Rd;
2890 let Inst{19-16} = 0b0000;
2891 let Inst{11-5} = src{11-5};
2893 let Inst{3-0} = src{3-0};
2897 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2898 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2899 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2903 let Inst{15-12} = Rd;
2904 let Inst{19-16} = 0b0000;
2905 let Inst{11-0} = imm;
2908 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2909 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2911 "movw", "\t$Rd, $imm",
2912 [(set GPR:$Rd, imm0_65535:$imm)]>,
2913 Requires<[IsARM, HasV6T2]>, UnaryDP {
2916 let Inst{15-12} = Rd;
2917 let Inst{11-0} = imm{11-0};
2918 let Inst{19-16} = imm{15-12};
2921 let DecoderMethod = "DecodeArmMOVTWInstruction";
2924 def : InstAlias<"mov${p} $Rd, $imm",
2925 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2928 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2929 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2931 let Constraints = "$src = $Rd" in {
2932 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2933 (ins GPR:$src, imm0_65535_expr:$imm),
2935 "movt", "\t$Rd, $imm",
2937 (or (and GPR:$src, 0xffff),
2938 lo16AllZero:$imm))]>, UnaryDP,
2939 Requires<[IsARM, HasV6T2]> {
2942 let Inst{15-12} = Rd;
2943 let Inst{11-0} = imm{11-0};
2944 let Inst{19-16} = imm{15-12};
2947 let DecoderMethod = "DecodeArmMOVTWInstruction";
2950 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2951 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2955 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2956 Requires<[IsARM, HasV6T2]>;
2958 let Uses = [CPSR] in
2959 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2960 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2963 // These aren't really mov instructions, but we have to define them this way
2964 // due to flag operands.
2966 let Defs = [CPSR] in {
2967 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2968 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2970 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2971 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2975 //===----------------------------------------------------------------------===//
2976 // Extend Instructions.
2981 def SXTB : AI_ext_rrot<0b01101010,
2982 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2983 def SXTH : AI_ext_rrot<0b01101011,
2984 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2986 def SXTAB : AI_exta_rrot<0b01101010,
2987 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2988 def SXTAH : AI_exta_rrot<0b01101011,
2989 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2991 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2993 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2997 let AddedComplexity = 16 in {
2998 def UXTB : AI_ext_rrot<0b01101110,
2999 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3000 def UXTH : AI_ext_rrot<0b01101111,
3001 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3002 def UXTB16 : AI_ext_rrot<0b01101100,
3003 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3005 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3006 // The transformation should probably be done as a combiner action
3007 // instead so we can include a check for masking back in the upper
3008 // eight bits of the source into the lower eight bits of the result.
3009 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3010 // (UXTB16r_rot GPR:$Src, 3)>;
3011 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3012 (UXTB16 GPR:$Src, 1)>;
3014 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3015 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3016 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3017 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3020 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3021 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3024 def SBFX : I<(outs GPRnopc:$Rd),
3025 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3026 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3027 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3028 Requires<[IsARM, HasV6T2]> {
3033 let Inst{27-21} = 0b0111101;
3034 let Inst{6-4} = 0b101;
3035 let Inst{20-16} = width;
3036 let Inst{15-12} = Rd;
3037 let Inst{11-7} = lsb;
3041 def UBFX : I<(outs GPR:$Rd),
3042 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3043 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3044 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3045 Requires<[IsARM, HasV6T2]> {
3050 let Inst{27-21} = 0b0111111;
3051 let Inst{6-4} = 0b101;
3052 let Inst{20-16} = width;
3053 let Inst{15-12} = Rd;
3054 let Inst{11-7} = lsb;
3058 //===----------------------------------------------------------------------===//
3059 // Arithmetic Instructions.
3062 defm ADD : AsI1_bin_irs<0b0100, "add",
3063 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3064 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3065 defm SUB : AsI1_bin_irs<0b0010, "sub",
3066 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3067 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3069 // ADD and SUB with 's' bit set.
3071 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3072 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3073 // AdjustInstrPostInstrSelection where we determine whether or not to
3074 // set the "s" bit based on CPSR liveness.
3076 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3077 // support for an optional CPSR definition that corresponds to the DAG
3078 // node's second value. We can then eliminate the implicit def of CPSR.
3079 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3080 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3081 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3082 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3084 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3085 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3087 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3088 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3091 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3092 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3093 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3095 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3096 // CPSR and the implicit def of CPSR is not needed.
3097 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3098 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3100 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3101 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3104 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3105 // The assume-no-carry-in form uses the negation of the input since add/sub
3106 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3107 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3109 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3110 (SUBri GPR:$src, so_imm_neg:$imm)>;
3111 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3112 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3114 // The with-carry-in form matches bitwise not instead of the negation.
3115 // Effectively, the inverse interpretation of the carry flag already accounts
3116 // for part of the negation.
3117 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3118 (SBCri GPR:$src, so_imm_not:$imm)>;
3120 // Note: These are implemented in C++ code, because they have to generate
3121 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3123 // (mul X, 2^n+1) -> (add (X << n), X)
3124 // (mul X, 2^n-1) -> (rsb X, (X << n))
3126 // ARM Arithmetic Instruction
3127 // GPR:$dst = GPR:$a op GPR:$b
3128 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3129 list<dag> pattern = [],
3130 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3131 string asm = "\t$Rd, $Rn, $Rm">
3132 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3136 let Inst{27-20} = op27_20;
3137 let Inst{11-4} = op11_4;
3138 let Inst{19-16} = Rn;
3139 let Inst{15-12} = Rd;
3143 // Saturating add/subtract
3145 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3146 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3147 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3148 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3149 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3150 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3151 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3152 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3154 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3155 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3158 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3159 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3160 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3161 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3162 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3163 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3164 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3165 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3166 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3167 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3168 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3169 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3171 // Signed/Unsigned add/subtract
3173 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3174 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3175 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3176 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3177 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3178 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3179 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3180 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3181 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3182 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3183 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3184 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3186 // Signed/Unsigned halving add/subtract
3188 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3189 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3190 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3191 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3192 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3193 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3194 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3195 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3196 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3197 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3198 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3199 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3201 // Unsigned Sum of Absolute Differences [and Accumulate].
3203 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3204 MulFrm /* for convenience */, NoItinerary, "usad8",
3205 "\t$Rd, $Rn, $Rm", []>,
3206 Requires<[IsARM, HasV6]> {
3210 let Inst{27-20} = 0b01111000;
3211 let Inst{15-12} = 0b1111;
3212 let Inst{7-4} = 0b0001;
3213 let Inst{19-16} = Rd;
3214 let Inst{11-8} = Rm;
3217 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3218 MulFrm /* for convenience */, NoItinerary, "usada8",
3219 "\t$Rd, $Rn, $Rm, $Ra", []>,
3220 Requires<[IsARM, HasV6]> {
3225 let Inst{27-20} = 0b01111000;
3226 let Inst{7-4} = 0b0001;
3227 let Inst{19-16} = Rd;
3228 let Inst{15-12} = Ra;
3229 let Inst{11-8} = Rm;
3233 // Signed/Unsigned saturate
3235 def SSAT : AI<(outs GPRnopc:$Rd),
3236 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3237 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3242 let Inst{27-21} = 0b0110101;
3243 let Inst{5-4} = 0b01;
3244 let Inst{20-16} = sat_imm;
3245 let Inst{15-12} = Rd;
3246 let Inst{11-7} = sh{4-0};
3247 let Inst{6} = sh{5};
3251 def SSAT16 : AI<(outs GPRnopc:$Rd),
3252 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3253 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3257 let Inst{27-20} = 0b01101010;
3258 let Inst{11-4} = 0b11110011;
3259 let Inst{15-12} = Rd;
3260 let Inst{19-16} = sat_imm;
3264 def USAT : AI<(outs GPRnopc:$Rd),
3265 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3266 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3271 let Inst{27-21} = 0b0110111;
3272 let Inst{5-4} = 0b01;
3273 let Inst{15-12} = Rd;
3274 let Inst{11-7} = sh{4-0};
3275 let Inst{6} = sh{5};
3276 let Inst{20-16} = sat_imm;
3280 def USAT16 : AI<(outs GPRnopc:$Rd),
3281 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3282 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3286 let Inst{27-20} = 0b01101110;
3287 let Inst{11-4} = 0b11110011;
3288 let Inst{15-12} = Rd;
3289 let Inst{19-16} = sat_imm;
3293 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3294 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3295 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3296 (USAT imm:$pos, GPRnopc:$a, 0)>;
3298 //===----------------------------------------------------------------------===//
3299 // Bitwise Instructions.
3302 defm AND : AsI1_bin_irs<0b0000, "and",
3303 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3304 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3305 defm ORR : AsI1_bin_irs<0b1100, "orr",
3306 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3307 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3308 defm EOR : AsI1_bin_irs<0b0001, "eor",
3309 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3310 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3311 defm BIC : AsI1_bin_irs<0b1110, "bic",
3312 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3313 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3315 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3316 // like in the actual instruction encoding. The complexity of mapping the mask
3317 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3318 // instruction description.
3319 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3320 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3321 "bfc", "\t$Rd, $imm", "$src = $Rd",
3322 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3323 Requires<[IsARM, HasV6T2]> {
3326 let Inst{27-21} = 0b0111110;
3327 let Inst{6-0} = 0b0011111;
3328 let Inst{15-12} = Rd;
3329 let Inst{11-7} = imm{4-0}; // lsb
3330 let Inst{20-16} = imm{9-5}; // msb
3333 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3334 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3335 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3336 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3337 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3338 bf_inv_mask_imm:$imm))]>,
3339 Requires<[IsARM, HasV6T2]> {
3343 let Inst{27-21} = 0b0111110;
3344 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3345 let Inst{15-12} = Rd;
3346 let Inst{11-7} = imm{4-0}; // lsb
3347 let Inst{20-16} = imm{9-5}; // width
3351 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3352 "mvn", "\t$Rd, $Rm",
3353 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3357 let Inst{19-16} = 0b0000;
3358 let Inst{11-4} = 0b00000000;
3359 let Inst{15-12} = Rd;
3362 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3363 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3364 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3368 let Inst{19-16} = 0b0000;
3369 let Inst{15-12} = Rd;
3370 let Inst{11-5} = shift{11-5};
3372 let Inst{3-0} = shift{3-0};
3374 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3375 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3376 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3380 let Inst{19-16} = 0b0000;
3381 let Inst{15-12} = Rd;
3382 let Inst{11-8} = shift{11-8};
3384 let Inst{6-5} = shift{6-5};
3386 let Inst{3-0} = shift{3-0};
3388 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3389 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3390 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3391 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3395 let Inst{19-16} = 0b0000;
3396 let Inst{15-12} = Rd;
3397 let Inst{11-0} = imm;
3400 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3401 (BICri GPR:$src, so_imm_not:$imm)>;
3403 //===----------------------------------------------------------------------===//
3404 // Multiply Instructions.
3406 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3407 string opc, string asm, list<dag> pattern>
3408 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3412 let Inst{19-16} = Rd;
3413 let Inst{11-8} = Rm;
3416 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3417 string opc, string asm, list<dag> pattern>
3418 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3423 let Inst{19-16} = RdHi;
3424 let Inst{15-12} = RdLo;
3425 let Inst{11-8} = Rm;
3429 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3430 // property. Remove them when it's possible to add those properties
3431 // on an individual MachineInstr, not just an instuction description.
3432 let isCommutable = 1 in {
3433 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3434 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3435 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3436 Requires<[IsARM, HasV6]> {
3437 let Inst{15-12} = 0b0000;
3440 let Constraints = "@earlyclobber $Rd" in
3441 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3442 pred:$p, cc_out:$s),
3444 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3445 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3446 Requires<[IsARM, NoV6]>;
3449 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3450 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3451 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3452 Requires<[IsARM, HasV6]> {
3454 let Inst{15-12} = Ra;
3457 let Constraints = "@earlyclobber $Rd" in
3458 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3459 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3461 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3462 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3463 Requires<[IsARM, NoV6]>;
3465 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3466 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3467 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3468 Requires<[IsARM, HasV6T2]> {
3473 let Inst{19-16} = Rd;
3474 let Inst{15-12} = Ra;
3475 let Inst{11-8} = Rm;
3479 // Extra precision multiplies with low / high results
3480 let neverHasSideEffects = 1 in {
3481 let isCommutable = 1 in {
3482 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3483 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3484 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3485 Requires<[IsARM, HasV6]>;
3487 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3488 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3489 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3490 Requires<[IsARM, HasV6]>;
3492 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3493 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3494 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3496 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3497 Requires<[IsARM, NoV6]>;
3499 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3500 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3502 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3503 Requires<[IsARM, NoV6]>;
3507 // Multiply + accumulate
3508 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3509 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3510 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3511 Requires<[IsARM, HasV6]>;
3512 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3513 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3514 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3515 Requires<[IsARM, HasV6]>;
3517 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3518 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3519 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3520 Requires<[IsARM, HasV6]> {
3525 let Inst{19-16} = RdHi;
3526 let Inst{15-12} = RdLo;
3527 let Inst{11-8} = Rm;
3531 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3532 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3533 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3535 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3536 Requires<[IsARM, NoV6]>;
3537 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3538 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3540 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3541 Requires<[IsARM, NoV6]>;
3542 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3543 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3545 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3546 Requires<[IsARM, NoV6]>;
3549 } // neverHasSideEffects
3551 // Most significant word multiply
3552 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3553 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3554 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3555 Requires<[IsARM, HasV6]> {
3556 let Inst{15-12} = 0b1111;
3559 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3560 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3561 Requires<[IsARM, HasV6]> {
3562 let Inst{15-12} = 0b1111;
3565 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3566 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3567 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3568 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3569 Requires<[IsARM, HasV6]>;
3571 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3572 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3573 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3574 Requires<[IsARM, HasV6]>;
3576 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3577 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3578 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3579 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3580 Requires<[IsARM, HasV6]>;
3582 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3583 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3584 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3585 Requires<[IsARM, HasV6]>;
3587 multiclass AI_smul<string opc, PatFrag opnode> {
3588 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3589 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3590 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3591 (sext_inreg GPR:$Rm, i16)))]>,
3592 Requires<[IsARM, HasV5TE]>;
3594 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3595 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3596 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3597 (sra GPR:$Rm, (i32 16))))]>,
3598 Requires<[IsARM, HasV5TE]>;
3600 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3601 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3602 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3603 (sext_inreg GPR:$Rm, i16)))]>,
3604 Requires<[IsARM, HasV5TE]>;
3606 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3607 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3608 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3609 (sra GPR:$Rm, (i32 16))))]>,
3610 Requires<[IsARM, HasV5TE]>;
3612 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3613 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3614 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3615 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3616 Requires<[IsARM, HasV5TE]>;
3618 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3619 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3620 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3621 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3622 Requires<[IsARM, HasV5TE]>;
3626 multiclass AI_smla<string opc, PatFrag opnode> {
3627 let DecoderMethod = "DecodeSMLAInstruction" in {
3628 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3629 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3630 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3631 [(set GPRnopc:$Rd, (add GPR:$Ra,
3632 (opnode (sext_inreg GPRnopc:$Rn, i16),
3633 (sext_inreg GPRnopc:$Rm, i16))))]>,
3634 Requires<[IsARM, HasV5TE]>;
3636 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3637 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3638 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3640 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3641 (sra GPRnopc:$Rm, (i32 16)))))]>,
3642 Requires<[IsARM, HasV5TE]>;
3644 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3645 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3646 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3648 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3649 (sext_inreg GPRnopc:$Rm, i16))))]>,
3650 Requires<[IsARM, HasV5TE]>;
3652 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3653 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3654 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3656 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3657 (sra GPRnopc:$Rm, (i32 16)))))]>,
3658 Requires<[IsARM, HasV5TE]>;
3660 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3661 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3662 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3664 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3665 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3666 Requires<[IsARM, HasV5TE]>;
3668 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3669 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3670 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3672 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3673 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3674 Requires<[IsARM, HasV5TE]>;
3678 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3679 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3681 // Halfword multiply accumulate long: SMLAL<x><y>.
3682 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3683 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3684 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3685 Requires<[IsARM, HasV5TE]>;
3687 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3688 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3689 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3690 Requires<[IsARM, HasV5TE]>;
3692 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3693 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3694 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3695 Requires<[IsARM, HasV5TE]>;
3697 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3698 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3699 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3700 Requires<[IsARM, HasV5TE]>;
3702 // Helper class for AI_smld.
3703 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3704 InstrItinClass itin, string opc, string asm>
3705 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3708 let Inst{27-23} = 0b01110;
3709 let Inst{22} = long;
3710 let Inst{21-20} = 0b00;
3711 let Inst{11-8} = Rm;
3718 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3719 InstrItinClass itin, string opc, string asm>
3720 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3722 let Inst{15-12} = 0b1111;
3723 let Inst{19-16} = Rd;
3725 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3726 InstrItinClass itin, string opc, string asm>
3727 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3730 let Inst{19-16} = Rd;
3731 let Inst{15-12} = Ra;
3733 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3734 InstrItinClass itin, string opc, string asm>
3735 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3738 let Inst{19-16} = RdHi;
3739 let Inst{15-12} = RdLo;
3742 multiclass AI_smld<bit sub, string opc> {
3744 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3745 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3746 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3748 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3749 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3750 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3752 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3753 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3754 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3756 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3757 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3758 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3762 defm SMLA : AI_smld<0, "smla">;
3763 defm SMLS : AI_smld<1, "smls">;
3765 multiclass AI_sdml<bit sub, string opc> {
3767 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3768 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3769 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3770 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3773 defm SMUA : AI_sdml<0, "smua">;
3774 defm SMUS : AI_sdml<1, "smus">;
3776 //===----------------------------------------------------------------------===//
3777 // Misc. Arithmetic Instructions.
3780 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3781 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3782 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3784 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3785 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3786 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3787 Requires<[IsARM, HasV6T2]>;
3789 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3790 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3791 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3793 let AddedComplexity = 5 in
3794 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3795 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3796 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3797 Requires<[IsARM, HasV6]>;
3799 let AddedComplexity = 5 in
3800 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3801 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3802 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3803 Requires<[IsARM, HasV6]>;
3805 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3806 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3809 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3810 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3811 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3812 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3813 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3815 Requires<[IsARM, HasV6]>;
3817 // Alternate cases for PKHBT where identities eliminate some nodes.
3818 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3819 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3820 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3821 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3823 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3824 // will match the pattern below.
3825 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3826 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3827 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3828 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3829 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3831 Requires<[IsARM, HasV6]>;
3833 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3834 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3835 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3836 (srl GPRnopc:$src2, imm16_31:$sh)),
3837 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3838 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3839 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3840 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3842 //===----------------------------------------------------------------------===//
3843 // Comparison Instructions...
3846 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3847 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3848 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3850 // ARMcmpZ can re-use the above instruction definitions.
3851 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3852 (CMPri GPR:$src, so_imm:$imm)>;
3853 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3854 (CMPrr GPR:$src, GPR:$rhs)>;
3855 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3856 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3857 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3858 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3860 // FIXME: We have to be careful when using the CMN instruction and comparison
3861 // with 0. One would expect these two pieces of code should give identical
3877 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3878 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3879 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3880 // value of r0 and the carry bit (because the "carry bit" parameter to
3881 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3882 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3883 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3884 // parameter to AddWithCarry is defined as 0).
3886 // When x is 0 and unsigned:
3890 // ~x + 1 = 0x1 0000 0000
3891 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3893 // Therefore, we should disable CMN when comparing against zero, until we can
3894 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3895 // when it's a comparison which doesn't look at the 'carry' flag).
3897 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3899 // This is related to <rdar://problem/7569620>.
3901 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3902 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3904 // Note that TST/TEQ don't set all the same flags that CMP does!
3905 defm TST : AI1_cmp_irs<0b1000, "tst",
3906 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3907 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3908 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3909 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3910 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3912 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3913 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3914 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3916 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3917 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3919 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3920 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3922 // Pseudo i64 compares for some floating point compares.
3923 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3925 def BCCi64 : PseudoInst<(outs),
3926 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3928 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3930 def BCCZi64 : PseudoInst<(outs),
3931 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3932 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3933 } // usesCustomInserter
3936 // Conditional moves
3937 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3938 // a two-value operand where a dag node expects two operands. :(
3939 let neverHasSideEffects = 1 in {
3940 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3942 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3943 RegConstraint<"$false = $Rd">;
3944 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3945 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3947 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3948 imm:$cc, CCR:$ccr))*/]>,
3949 RegConstraint<"$false = $Rd">;
3950 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3951 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3953 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3954 imm:$cc, CCR:$ccr))*/]>,
3955 RegConstraint<"$false = $Rd">;
3958 let isMoveImm = 1 in
3959 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3960 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3963 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3965 let isMoveImm = 1 in
3966 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3967 (ins GPR:$false, so_imm:$imm, pred:$p),
3969 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3970 RegConstraint<"$false = $Rd">;
3972 // Two instruction predicate mov immediate.
3973 let isMoveImm = 1 in
3974 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3975 (ins GPR:$false, i32imm:$src, pred:$p),
3976 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3978 let isMoveImm = 1 in
3979 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3980 (ins GPR:$false, so_imm:$imm, pred:$p),
3982 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3983 RegConstraint<"$false = $Rd">;
3984 } // neverHasSideEffects
3986 //===----------------------------------------------------------------------===//
3987 // Atomic operations intrinsics
3990 def MemBarrierOptOperand : AsmOperandClass {
3991 let Name = "MemBarrierOpt";
3992 let ParserMethod = "parseMemBarrierOptOperand";
3994 def memb_opt : Operand<i32> {
3995 let PrintMethod = "printMemBOption";
3996 let ParserMatchClass = MemBarrierOptOperand;
3997 let DecoderMethod = "DecodeMemBarrierOption";
4000 // memory barriers protect the atomic sequences
4001 let hasSideEffects = 1 in {
4002 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4003 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4004 Requires<[IsARM, HasDB]> {
4006 let Inst{31-4} = 0xf57ff05;
4007 let Inst{3-0} = opt;
4011 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4012 "dsb", "\t$opt", []>,
4013 Requires<[IsARM, HasDB]> {
4015 let Inst{31-4} = 0xf57ff04;
4016 let Inst{3-0} = opt;
4019 // ISB has only full system option
4020 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4021 "isb", "\t$opt", []>,
4022 Requires<[IsARM, HasDB]> {
4024 let Inst{31-4} = 0xf57ff06;
4025 let Inst{3-0} = opt;
4028 // Pseudo isntruction that combines movs + predicated rsbmi
4029 // to implement integer ABS
4030 let usesCustomInserter = 1, Defs = [CPSR] in {
4031 def ABS : ARMPseudoInst<
4032 (outs GPR:$dst), (ins GPR:$src),
4033 8, NoItinerary, []>;
4036 let usesCustomInserter = 1 in {
4037 let Defs = [CPSR] in {
4038 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4039 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4040 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4041 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4042 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4043 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4044 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4045 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4046 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4047 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4048 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4049 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4050 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4051 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4052 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4053 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4054 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4055 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4056 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4057 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4058 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4059 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4060 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4061 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4062 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4063 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4064 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4065 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4066 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4067 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4068 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4069 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4070 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4071 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4072 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4073 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4074 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4075 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4076 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4077 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4078 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4079 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4080 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4081 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4082 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4083 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4084 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4085 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4086 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4087 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4088 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4089 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4090 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4091 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4092 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4093 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4094 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4095 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4096 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4097 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4098 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4099 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4100 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4101 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4102 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4103 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4104 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4105 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4106 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4107 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4108 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4109 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4110 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4111 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4112 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4113 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4114 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4115 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4116 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4118 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4119 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4121 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4122 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4124 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4125 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4127 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4129 def ATOMIC_SWAP_I8 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4131 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4132 def ATOMIC_SWAP_I16 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4134 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4135 def ATOMIC_SWAP_I32 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4137 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4139 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4141 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4142 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4144 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4145 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4147 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4151 let mayLoad = 1 in {
4152 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4154 "ldrexb", "\t$Rt, $addr", []>;
4155 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4156 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4157 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4158 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4159 let hasExtraDefRegAllocReq = 1 in
4160 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4161 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4162 let DecoderMethod = "DecodeDoubleRegLoad";
4166 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4167 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4168 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4169 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4170 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4171 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4172 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4175 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4176 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4177 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4178 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4179 let DecoderMethod = "DecodeDoubleRegStore";
4182 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4183 Requires<[IsARM, HasV7]> {
4184 let Inst{31-0} = 0b11110101011111111111000000011111;
4187 // SWP/SWPB are deprecated in V6/V7.
4188 let mayLoad = 1, mayStore = 1 in {
4189 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4191 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4195 //===----------------------------------------------------------------------===//
4196 // Coprocessor Instructions.
4199 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4200 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4201 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4202 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4203 imm:$CRm, imm:$opc2)]> {
4211 let Inst{3-0} = CRm;
4213 let Inst{7-5} = opc2;
4214 let Inst{11-8} = cop;
4215 let Inst{15-12} = CRd;
4216 let Inst{19-16} = CRn;
4217 let Inst{23-20} = opc1;
4220 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4221 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4222 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4223 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4224 imm:$CRm, imm:$opc2)]> {
4225 let Inst{31-28} = 0b1111;
4233 let Inst{3-0} = CRm;
4235 let Inst{7-5} = opc2;
4236 let Inst{11-8} = cop;
4237 let Inst{15-12} = CRd;
4238 let Inst{19-16} = CRn;
4239 let Inst{23-20} = opc1;
4242 class ACI<dag oops, dag iops, string opc, string asm,
4243 IndexMode im = IndexModeNone>
4244 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4246 let Inst{27-25} = 0b110;
4248 class ACInoP<dag oops, dag iops, string opc, string asm,
4249 IndexMode im = IndexModeNone>
4250 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4252 let Inst{31-28} = 0b1111;
4253 let Inst{27-25} = 0b110;
4255 multiclass LdStCop<bit load, bit Dbit, string asm> {
4256 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4257 asm, "\t$cop, $CRd, $addr"> {
4261 let Inst{24} = 1; // P = 1
4262 let Inst{23} = addr{8};
4263 let Inst{22} = Dbit;
4264 let Inst{21} = 0; // W = 0
4265 let Inst{20} = load;
4266 let Inst{19-16} = addr{12-9};
4267 let Inst{15-12} = CRd;
4268 let Inst{11-8} = cop;
4269 let Inst{7-0} = addr{7-0};
4270 let DecoderMethod = "DecodeCopMemInstruction";
4272 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4273 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4277 let Inst{24} = 1; // P = 1
4278 let Inst{23} = addr{8};
4279 let Inst{22} = Dbit;
4280 let Inst{21} = 1; // W = 1
4281 let Inst{20} = load;
4282 let Inst{19-16} = addr{12-9};
4283 let Inst{15-12} = CRd;
4284 let Inst{11-8} = cop;
4285 let Inst{7-0} = addr{7-0};
4286 let DecoderMethod = "DecodeCopMemInstruction";
4288 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4289 postidx_imm8s4:$offset),
4290 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4295 let Inst{24} = 0; // P = 0
4296 let Inst{23} = offset{8};
4297 let Inst{22} = Dbit;
4298 let Inst{21} = 1; // W = 1
4299 let Inst{20} = load;
4300 let Inst{19-16} = addr;
4301 let Inst{15-12} = CRd;
4302 let Inst{11-8} = cop;
4303 let Inst{7-0} = offset{7-0};
4304 let DecoderMethod = "DecodeCopMemInstruction";
4306 def _OPTION : ACI<(outs),
4307 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4308 coproc_option_imm:$option),
4309 asm, "\t$cop, $CRd, $addr, $option"> {
4314 let Inst{24} = 0; // P = 0
4315 let Inst{23} = 1; // U = 1
4316 let Inst{22} = Dbit;
4317 let Inst{21} = 0; // W = 0
4318 let Inst{20} = load;
4319 let Inst{19-16} = addr;
4320 let Inst{15-12} = CRd;
4321 let Inst{11-8} = cop;
4322 let Inst{7-0} = option;
4323 let DecoderMethod = "DecodeCopMemInstruction";
4326 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4327 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4328 asm, "\t$cop, $CRd, $addr"> {
4332 let Inst{24} = 1; // P = 1
4333 let Inst{23} = addr{8};
4334 let Inst{22} = Dbit;
4335 let Inst{21} = 0; // W = 0
4336 let Inst{20} = load;
4337 let Inst{19-16} = addr{12-9};
4338 let Inst{15-12} = CRd;
4339 let Inst{11-8} = cop;
4340 let Inst{7-0} = addr{7-0};
4341 let DecoderMethod = "DecodeCopMemInstruction";
4343 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4344 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4348 let Inst{24} = 1; // P = 1
4349 let Inst{23} = addr{8};
4350 let Inst{22} = Dbit;
4351 let Inst{21} = 1; // W = 1
4352 let Inst{20} = load;
4353 let Inst{19-16} = addr{12-9};
4354 let Inst{15-12} = CRd;
4355 let Inst{11-8} = cop;
4356 let Inst{7-0} = addr{7-0};
4357 let DecoderMethod = "DecodeCopMemInstruction";
4359 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4360 postidx_imm8s4:$offset),
4361 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4366 let Inst{24} = 0; // P = 0
4367 let Inst{23} = offset{8};
4368 let Inst{22} = Dbit;
4369 let Inst{21} = 1; // W = 1
4370 let Inst{20} = load;
4371 let Inst{19-16} = addr;
4372 let Inst{15-12} = CRd;
4373 let Inst{11-8} = cop;
4374 let Inst{7-0} = offset{7-0};
4375 let DecoderMethod = "DecodeCopMemInstruction";
4377 def _OPTION : ACInoP<(outs),
4378 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4379 coproc_option_imm:$option),
4380 asm, "\t$cop, $CRd, $addr, $option"> {
4385 let Inst{24} = 0; // P = 0
4386 let Inst{23} = 1; // U = 1
4387 let Inst{22} = Dbit;
4388 let Inst{21} = 0; // W = 0
4389 let Inst{20} = load;
4390 let Inst{19-16} = addr;
4391 let Inst{15-12} = CRd;
4392 let Inst{11-8} = cop;
4393 let Inst{7-0} = option;
4394 let DecoderMethod = "DecodeCopMemInstruction";
4398 defm LDC : LdStCop <1, 0, "ldc">;
4399 defm LDCL : LdStCop <1, 1, "ldcl">;
4400 defm STC : LdStCop <0, 0, "stc">;
4401 defm STCL : LdStCop <0, 1, "stcl">;
4402 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4403 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4404 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4405 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4407 //===----------------------------------------------------------------------===//
4408 // Move between coprocessor and ARM core register.
4411 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4413 : ABI<0b1110, oops, iops, NoItinerary, opc,
4414 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4415 let Inst{20} = direction;
4425 let Inst{15-12} = Rt;
4426 let Inst{11-8} = cop;
4427 let Inst{23-21} = opc1;
4428 let Inst{7-5} = opc2;
4429 let Inst{3-0} = CRm;
4430 let Inst{19-16} = CRn;
4433 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4435 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4436 c_imm:$CRm, imm0_7:$opc2),
4437 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4438 imm:$CRm, imm:$opc2)]>;
4439 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4441 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4444 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4445 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4447 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4449 : ABXI<0b1110, oops, iops, NoItinerary,
4450 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4451 let Inst{31-28} = 0b1111;
4452 let Inst{20} = direction;
4462 let Inst{15-12} = Rt;
4463 let Inst{11-8} = cop;
4464 let Inst{23-21} = opc1;
4465 let Inst{7-5} = opc2;
4466 let Inst{3-0} = CRm;
4467 let Inst{19-16} = CRn;
4470 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4472 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4473 c_imm:$CRm, imm0_7:$opc2),
4474 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4475 imm:$CRm, imm:$opc2)]>;
4476 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4478 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4481 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4482 imm:$CRm, imm:$opc2),
4483 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4485 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4486 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4487 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4488 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4489 let Inst{23-21} = 0b010;
4490 let Inst{20} = direction;
4498 let Inst{15-12} = Rt;
4499 let Inst{19-16} = Rt2;
4500 let Inst{11-8} = cop;
4501 let Inst{7-4} = opc1;
4502 let Inst{3-0} = CRm;
4505 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4506 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4508 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4510 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4511 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4512 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4513 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4514 let Inst{31-28} = 0b1111;
4515 let Inst{23-21} = 0b010;
4516 let Inst{20} = direction;
4524 let Inst{15-12} = Rt;
4525 let Inst{19-16} = Rt2;
4526 let Inst{11-8} = cop;
4527 let Inst{7-4} = opc1;
4528 let Inst{3-0} = CRm;
4531 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4532 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4534 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4536 //===----------------------------------------------------------------------===//
4537 // Move between special register and ARM core register
4540 // Move to ARM core register from Special Register
4541 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4542 "mrs", "\t$Rd, apsr", []> {
4544 let Inst{23-16} = 0b00001111;
4545 let Inst{15-12} = Rd;
4546 let Inst{7-4} = 0b0000;
4549 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4551 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4552 "mrs", "\t$Rd, spsr", []> {
4554 let Inst{23-16} = 0b01001111;
4555 let Inst{15-12} = Rd;
4556 let Inst{7-4} = 0b0000;
4559 // Move from ARM core register to Special Register
4561 // No need to have both system and application versions, the encodings are the
4562 // same and the assembly parser has no way to distinguish between them. The mask
4563 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4564 // the mask with the fields to be accessed in the special register.
4565 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4566 "msr", "\t$mask, $Rn", []> {
4571 let Inst{22} = mask{4}; // R bit
4572 let Inst{21-20} = 0b10;
4573 let Inst{19-16} = mask{3-0};
4574 let Inst{15-12} = 0b1111;
4575 let Inst{11-4} = 0b00000000;
4579 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4580 "msr", "\t$mask, $a", []> {
4585 let Inst{22} = mask{4}; // R bit
4586 let Inst{21-20} = 0b10;
4587 let Inst{19-16} = mask{3-0};
4588 let Inst{15-12} = 0b1111;
4592 //===----------------------------------------------------------------------===//
4596 // __aeabi_read_tp preserves the registers r1-r3.
4597 // This is a pseudo inst so that we can get the encoding right,
4598 // complete with fixup for the aeabi_read_tp function.
4600 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4601 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4602 [(set R0, ARMthread_pointer)]>;
4605 //===----------------------------------------------------------------------===//
4606 // SJLJ Exception handling intrinsics
4607 // eh_sjlj_setjmp() is an instruction sequence to store the return
4608 // address and save #0 in R0 for the non-longjmp case.
4609 // Since by its nature we may be coming from some other function to get
4610 // here, and we're using the stack frame for the containing function to
4611 // save/restore registers, we can't keep anything live in regs across
4612 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4613 // when we get here from a longjmp(). We force everything out of registers
4614 // except for our own input by listing the relevant registers in Defs. By
4615 // doing so, we also cause the prologue/epilogue code to actively preserve
4616 // all of the callee-saved resgisters, which is exactly what we want.
4617 // A constant value is passed in $val, and we use the location as a scratch.
4619 // These are pseudo-instructions and are lowered to individual MC-insts, so
4620 // no encoding information is necessary.
4622 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4623 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1,
4624 usesCustomInserter = 1 in {
4625 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4627 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4628 Requires<[IsARM, HasVFP2]>;
4632 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4633 hasSideEffects = 1, isBarrier = 1 in {
4634 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4636 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4637 Requires<[IsARM, NoVFP]>;
4640 // FIXME: Non-Darwin version(s)
4641 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4642 Defs = [ R7, LR, SP ] in {
4643 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4645 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4646 Requires<[IsARM, IsDarwin]>;
4649 // eh.sjlj.dispatchsetup pseudo-instruction.
4650 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4651 // handled when the pseudo is expanded (which happens before any passes
4652 // that need the instruction size).
4653 let isBarrier = 1, hasSideEffects = 1 in
4654 def Int_eh_sjlj_dispatchsetup :
4655 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4656 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4657 Requires<[IsDarwin]>;
4659 //===----------------------------------------------------------------------===//
4660 // Non-Instruction Patterns
4663 // ARMv4 indirect branch using (MOVr PC, dst)
4664 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4665 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4666 4, IIC_Br, [(brind GPR:$dst)],
4667 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4668 Requires<[IsARM, NoV4T]>;
4670 // Large immediate handling.
4672 // 32-bit immediate using two piece so_imms or movw + movt.
4673 // This is a single pseudo instruction, the benefit is that it can be remat'd
4674 // as a single unit instead of having to handle reg inputs.
4675 // FIXME: Remove this when we can do generalized remat.
4676 let isReMaterializable = 1, isMoveImm = 1 in
4677 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4678 [(set GPR:$dst, (arm_i32imm:$src))]>,
4681 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4682 // It also makes it possible to rematerialize the instructions.
4683 // FIXME: Remove this when we can do generalized remat and when machine licm
4684 // can properly the instructions.
4685 let isReMaterializable = 1 in {
4686 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4688 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4689 Requires<[IsARM, UseMovt]>;
4691 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4693 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4694 Requires<[IsARM, UseMovt]>;
4696 let AddedComplexity = 10 in
4697 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4699 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4700 Requires<[IsARM, UseMovt]>;
4701 } // isReMaterializable
4703 // ConstantPool, GlobalAddress, and JumpTable
4704 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4705 Requires<[IsARM, DontUseMovt]>;
4706 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4707 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4708 Requires<[IsARM, UseMovt]>;
4709 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4710 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4712 // TODO: add,sub,and, 3-instr forms?
4715 def : ARMPat<(ARMtcret tcGPR:$dst),
4716 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4718 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4719 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4721 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4722 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4724 def : ARMPat<(ARMtcret tcGPR:$dst),
4725 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4727 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4728 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4730 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4731 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4734 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4735 Requires<[IsARM, IsNotDarwin]>;
4736 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4737 Requires<[IsARM, IsDarwin]>;
4739 // zextload i1 -> zextload i8
4740 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4741 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4743 // extload -> zextload
4744 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4745 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4746 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4747 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4749 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4751 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4752 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4755 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4756 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4757 (SMULBB GPR:$a, GPR:$b)>;
4758 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4759 (SMULBB GPR:$a, GPR:$b)>;
4760 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4761 (sra GPR:$b, (i32 16))),
4762 (SMULBT GPR:$a, GPR:$b)>;
4763 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4764 (SMULBT GPR:$a, GPR:$b)>;
4765 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4766 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4767 (SMULTB GPR:$a, GPR:$b)>;
4768 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4769 (SMULTB GPR:$a, GPR:$b)>;
4770 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4772 (SMULWB GPR:$a, GPR:$b)>;
4773 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4774 (SMULWB GPR:$a, GPR:$b)>;
4776 def : ARMV5TEPat<(add GPR:$acc,
4777 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4778 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4779 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4780 def : ARMV5TEPat<(add GPR:$acc,
4781 (mul sext_16_node:$a, sext_16_node:$b)),
4782 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4783 def : ARMV5TEPat<(add GPR:$acc,
4784 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4785 (sra GPR:$b, (i32 16)))),
4786 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4787 def : ARMV5TEPat<(add GPR:$acc,
4788 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4789 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4790 def : ARMV5TEPat<(add GPR:$acc,
4791 (mul (sra GPR:$a, (i32 16)),
4792 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4793 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4794 def : ARMV5TEPat<(add GPR:$acc,
4795 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4796 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4797 def : ARMV5TEPat<(add GPR:$acc,
4798 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4800 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4801 def : ARMV5TEPat<(add GPR:$acc,
4802 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4803 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4806 // Pre-v7 uses MCR for synchronization barriers.
4807 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4808 Requires<[IsARM, HasV6]>;
4810 // SXT/UXT with no rotate
4811 let AddedComplexity = 16 in {
4812 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4813 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4814 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4815 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4816 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4817 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4818 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4821 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4822 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4824 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4825 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4826 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4827 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4829 // Atomic load/store patterns
4830 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4831 (LDRBrs ldst_so_reg:$src)>;
4832 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4833 (LDRBi12 addrmode_imm12:$src)>;
4834 def : ARMPat<(atomic_load_16 addrmode3:$src),
4835 (LDRH addrmode3:$src)>;
4836 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4837 (LDRrs ldst_so_reg:$src)>;
4838 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4839 (LDRi12 addrmode_imm12:$src)>;
4840 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4841 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4842 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4843 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4844 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4845 (STRH GPR:$val, addrmode3:$ptr)>;
4846 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4847 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4848 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4849 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4852 //===----------------------------------------------------------------------===//
4856 include "ARMInstrThumb.td"
4858 //===----------------------------------------------------------------------===//
4862 include "ARMInstrThumb2.td"
4864 //===----------------------------------------------------------------------===//
4865 // Floating Point Support
4868 include "ARMInstrVFP.td"
4870 //===----------------------------------------------------------------------===//
4871 // Advanced SIMD (NEON) Support
4874 include "ARMInstrNEON.td"
4876 //===----------------------------------------------------------------------===//
4877 // Assembler aliases
4881 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4882 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4883 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4885 // System instructions
4886 def : MnemonicAlias<"swi", "svc">;
4888 // Load / Store Multiple
4889 def : MnemonicAlias<"ldmfd", "ldm">;
4890 def : MnemonicAlias<"ldmia", "ldm">;
4891 def : MnemonicAlias<"ldmea", "ldmdb">;
4892 def : MnemonicAlias<"stmfd", "stmdb">;
4893 def : MnemonicAlias<"stmia", "stm">;
4894 def : MnemonicAlias<"stmea", "stm">;
4896 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4897 // shift amount is zero (i.e., unspecified).
4898 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4899 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4900 Requires<[IsARM, HasV6]>;
4901 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4902 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4903 Requires<[IsARM, HasV6]>;
4905 // PUSH/POP aliases for STM/LDM
4906 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4907 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4909 // SSAT/USAT optional shift operand.
4910 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4911 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4912 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4913 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4916 // Extend instruction optional rotate operand.
4917 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4918 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4919 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4920 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4921 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4922 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4923 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4924 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4925 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4926 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4927 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4928 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4930 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4931 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4932 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4933 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4934 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4935 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4936 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4937 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4938 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4939 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4940 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4941 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4945 def : MnemonicAlias<"rfefa", "rfeda">;
4946 def : MnemonicAlias<"rfeea", "rfedb">;
4947 def : MnemonicAlias<"rfefd", "rfeia">;
4948 def : MnemonicAlias<"rfeed", "rfeib">;
4949 def : MnemonicAlias<"rfe", "rfeia">;
4952 def : MnemonicAlias<"srsfa", "srsda">;
4953 def : MnemonicAlias<"srsea", "srsdb">;
4954 def : MnemonicAlias<"srsfd", "srsia">;
4955 def : MnemonicAlias<"srsed", "srsib">;
4956 def : MnemonicAlias<"srs", "srsia">;
4959 def : MnemonicAlias<"qsubaddx", "qsax">;
4961 def : MnemonicAlias<"saddsubx", "sasx">;
4962 // SHASX == SHADDSUBX
4963 def : MnemonicAlias<"shaddsubx", "shasx">;
4964 // SHSAX == SHSUBADDX
4965 def : MnemonicAlias<"shsubaddx", "shsax">;
4967 def : MnemonicAlias<"ssubaddx", "ssax">;
4969 def : MnemonicAlias<"uaddsubx", "uasx">;
4970 // UHASX == UHADDSUBX
4971 def : MnemonicAlias<"uhaddsubx", "uhasx">;
4972 // UHSAX == UHSUBADDX
4973 def : MnemonicAlias<"uhsubaddx", "uhsax">;
4974 // UQASX == UQADDSUBX
4975 def : MnemonicAlias<"uqaddsubx", "uqasx">;
4976 // UQSAX == UQSUBADDX
4977 def : MnemonicAlias<"uqsubaddx", "uqsax">;
4979 def : MnemonicAlias<"usubaddx", "usax">;
4981 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4982 // Note that the write-back output register is a dummy operand for MC (it's
4983 // only meaningful for codegen), so we just pass zero here.
4984 // FIXME: tblgen not cooperating with argument conversions.
4985 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4986 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4987 //def : InstAlias<"ldrht${p} $Rt, $addr",
4988 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4989 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4990 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;