1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 //===----------------------------------------------------------------------===//
273 // Operand Definitions.
277 def brtarget : Operand<OtherVT>;
279 // A list of registers separated by comma. Used by load/store multiple.
280 def reglist : Operand<i32> {
281 string EncoderMethod = "getRegisterListOpValue";
282 let PrintMethod = "printRegisterList";
285 def RegListAsmOperand : AsmOperandClass {
286 let Name = "RegList";
287 let SuperClasses = [];
290 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
291 def cpinst_operand : Operand<i32> {
292 let PrintMethod = "printCPInstOperand";
295 def jtblock_operand : Operand<i32> {
296 let PrintMethod = "printJTBlockOperand";
298 def jt2block_operand : Operand<i32> {
299 let PrintMethod = "printJT2BlockOperand";
303 def pclabel : Operand<i32> {
304 let PrintMethod = "printPCLabel";
307 def neon_vcvt_imm32 : Operand<i32> {
308 string EncoderMethod = "getNEONVcvtImm32OpValue";
311 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
312 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
313 int32_t v = (int32_t)N->getZExtValue();
314 return v == 8 || v == 16 || v == 24; }]> {
315 string EncoderMethod = "getRotImmOpValue";
318 // shift_imm: An integer that encodes a shift amount and the type of shift
319 // (currently either asr or lsl) using the same encoding used for the
320 // immediates in so_reg operands.
321 def shift_imm : Operand<i32> {
322 let PrintMethod = "printShiftImmOperand";
325 // shifter_operand operands: so_reg and so_imm.
326 def so_reg : Operand<i32>, // reg reg imm
327 ComplexPattern<i32, 3, "SelectShifterOperandReg",
328 [shl,srl,sra,rotr]> {
329 string EncoderMethod = "getSORegOpValue";
330 let PrintMethod = "printSORegOperand";
331 let MIOperandInfo = (ops GPR, GPR, i32imm);
333 def shift_so_reg : Operand<i32>, // reg reg imm
334 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
335 [shl,srl,sra,rotr]> {
336 string EncoderMethod = "getSORegOpValue";
337 let PrintMethod = "printSORegOperand";
338 let MIOperandInfo = (ops GPR, GPR, i32imm);
341 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
342 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
343 // represented in the imm field in the same 12-bit form that they are encoded
344 // into so_imm instructions: the 8-bit immediate is the least significant bits
345 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
346 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
347 string EncoderMethod = "getSOImmOpValue";
348 let PrintMethod = "printSOImmOperand";
351 // Break so_imm's up into two pieces. This handles immediates with up to 16
352 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
353 // get the first/second pieces.
354 def so_imm2part : Operand<i32>,
356 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
358 let PrintMethod = "printSOImm2PartOperand";
361 def so_imm2part_1 : SDNodeXForm<imm, [{
362 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
363 return CurDAG->getTargetConstant(V, MVT::i32);
366 def so_imm2part_2 : SDNodeXForm<imm, [{
367 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
368 return CurDAG->getTargetConstant(V, MVT::i32);
371 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
372 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
374 let PrintMethod = "printSOImm2PartOperand";
377 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
378 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
379 return CurDAG->getTargetConstant(V, MVT::i32);
382 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
383 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
384 return CurDAG->getTargetConstant(V, MVT::i32);
387 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
388 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
389 return (int32_t)N->getZExtValue() < 32;
392 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
393 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
394 return (int32_t)N->getZExtValue() < 32;
396 string EncoderMethod = "getImmMinusOneOpValue";
399 // Define ARM specific addressing modes.
402 // addrmode_imm12 := reg +/- imm12
404 def addrmode_imm12 : Operand<i32>,
405 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
406 // 12-bit immediate operand. Note that instructions using this encode
407 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
408 // immediate values are as normal.
410 string EncoderMethod = "getAddrModeImm12OpValue";
411 let PrintMethod = "printAddrModeImm12Operand";
412 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
414 // ldst_so_reg := reg +/- reg shop imm
416 def ldst_so_reg : Operand<i32>,
417 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
418 string EncoderMethod = "getLdStSORegOpValue";
419 // FIXME: Simplify the printer
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 // addrmode2 := reg +/- imm12
425 // := reg +/- reg shop imm
427 def addrmode2 : Operand<i32>,
428 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
429 let PrintMethod = "printAddrMode2Operand";
430 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
433 def am2offset : Operand<i32>,
434 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
435 [], [SDNPWantRoot]> {
436 let PrintMethod = "printAddrMode2OffsetOperand";
437 let MIOperandInfo = (ops GPR, i32imm);
440 // addrmode3 := reg +/- reg
441 // addrmode3 := reg +/- imm8
443 def addrmode3 : Operand<i32>,
444 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
445 string EncoderMethod = "getAddrMode3OpValue";
446 let PrintMethod = "printAddrMode3Operand";
447 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
450 def am3offset : Operand<i32>,
451 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
452 [], [SDNPWantRoot]> {
453 let PrintMethod = "printAddrMode3OffsetOperand";
454 let MIOperandInfo = (ops GPR, i32imm);
457 // ldstm_mode := {ia, ib, da, db}
459 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
460 string EncoderMethod = "getLdStmModeOpValue";
461 let PrintMethod = "printLdStmModeOperand";
464 def MemMode5AsmOperand : AsmOperandClass {
465 let Name = "MemMode5";
466 let SuperClasses = [];
469 // addrmode5 := reg +/- imm8*4
471 def addrmode5 : Operand<i32>,
472 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
473 let PrintMethod = "printAddrMode5Operand";
474 let MIOperandInfo = (ops GPR:$base, i32imm);
475 let ParserMatchClass = MemMode5AsmOperand;
476 string EncoderMethod = "getAddrMode5OpValue";
479 // addrmode6 := reg with optional writeback
481 def addrmode6 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
483 let PrintMethod = "printAddrMode6Operand";
484 let MIOperandInfo = (ops GPR:$addr, i32imm);
485 string EncoderMethod = "getAddrMode6AddressOpValue";
488 def am6offset : Operand<i32> {
489 let PrintMethod = "printAddrMode6OffsetOperand";
490 let MIOperandInfo = (ops GPR);
491 string EncoderMethod = "getAddrMode6OffsetOpValue";
494 // addrmodepc := pc + reg
496 def addrmodepc : Operand<i32>,
497 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
498 let PrintMethod = "printAddrModePCOperand";
499 let MIOperandInfo = (ops GPR, i32imm);
502 def nohash_imm : Operand<i32> {
503 let PrintMethod = "printNoHashImmediate";
506 //===----------------------------------------------------------------------===//
508 include "ARMInstrFormats.td"
510 //===----------------------------------------------------------------------===//
511 // Multiclass helpers...
514 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
515 /// binop that produces a value.
516 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
517 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
518 PatFrag opnode, bit Commutable = 0> {
519 // The register-immediate version is re-materializable. This is useful
520 // in particular for taking the address of a local.
521 let isReMaterializable = 1 in {
522 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
523 iii, opc, "\t$Rd, $Rn, $imm",
524 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
529 let Inst{19-16} = Rn;
530 let Inst{15-12} = Rd;
531 let Inst{11-0} = imm;
534 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
535 iir, opc, "\t$Rd, $Rn, $Rm",
536 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
541 let isCommutable = Commutable;
542 let Inst{19-16} = Rn;
543 let Inst{15-12} = Rd;
544 let Inst{11-4} = 0b00000000;
547 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
548 iis, opc, "\t$Rd, $Rn, $shift",
549 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
554 let Inst{19-16} = Rn;
555 let Inst{15-12} = Rd;
556 let Inst{11-0} = shift;
560 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
561 /// instruction modifies the CPSR register.
562 let Defs = [CPSR] in {
563 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
564 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
565 PatFrag opnode, bit Commutable = 0> {
566 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
567 iii, opc, "\t$Rd, $Rn, $imm",
568 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
574 let Inst{19-16} = Rn;
575 let Inst{15-12} = Rd;
576 let Inst{11-0} = imm;
578 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
579 iir, opc, "\t$Rd, $Rn, $Rm",
580 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
584 let isCommutable = Commutable;
587 let Inst{19-16} = Rn;
588 let Inst{15-12} = Rd;
589 let Inst{11-4} = 0b00000000;
592 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
593 iis, opc, "\t$Rd, $Rn, $shift",
594 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
600 let Inst{19-16} = Rn;
601 let Inst{15-12} = Rd;
602 let Inst{11-0} = shift;
607 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
608 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
609 /// a explicit result, only implicitly set CPSR.
610 let isCompare = 1, Defs = [CPSR] in {
611 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
612 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
613 PatFrag opnode, bit Commutable = 0> {
614 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
616 [(opnode GPR:$Rn, so_imm:$imm)]> {
621 let Inst{19-16} = Rn;
622 let Inst{15-12} = 0b0000;
623 let Inst{11-0} = imm;
625 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
627 [(opnode GPR:$Rn, GPR:$Rm)]> {
630 let isCommutable = Commutable;
633 let Inst{19-16} = Rn;
634 let Inst{15-12} = 0b0000;
635 let Inst{11-4} = 0b00000000;
638 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
639 opc, "\t$Rn, $shift",
640 [(opnode GPR:$Rn, so_reg:$shift)]> {
645 let Inst{19-16} = Rn;
646 let Inst{15-12} = 0b0000;
647 let Inst{11-0} = shift;
652 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
653 /// register and one whose operand is a register rotated by 8/16/24.
654 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
655 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
656 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
657 IIC_iEXTr, opc, "\t$Rd, $Rm",
658 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
659 Requires<[IsARM, HasV6]> {
662 let Inst{19-16} = 0b1111;
663 let Inst{15-12} = Rd;
664 let Inst{11-10} = 0b00;
667 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
668 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
669 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
670 Requires<[IsARM, HasV6]> {
674 let Inst{19-16} = 0b1111;
675 let Inst{15-12} = Rd;
676 let Inst{11-10} = rot;
681 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
682 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
683 IIC_iEXTr, opc, "\t$Rd, $Rm",
684 [/* For disassembly only; pattern left blank */]>,
685 Requires<[IsARM, HasV6]> {
686 let Inst{19-16} = 0b1111;
687 let Inst{11-10} = 0b00;
689 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
690 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
691 [/* For disassembly only; pattern left blank */]>,
692 Requires<[IsARM, HasV6]> {
694 let Inst{19-16} = 0b1111;
695 let Inst{11-10} = rot;
699 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
700 /// register and one whose operand is a register rotated by 8/16/24.
701 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
702 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
703 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
704 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
705 Requires<[IsARM, HasV6]> {
706 let Inst{11-10} = 0b00;
708 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
710 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
711 [(set GPR:$Rd, (opnode GPR:$Rn,
712 (rotr GPR:$Rm, rot_imm:$rot)))]>,
713 Requires<[IsARM, HasV6]> {
716 let Inst{19-16} = Rn;
717 let Inst{11-10} = rot;
721 // For disassembly only.
722 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
723 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
724 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
725 [/* For disassembly only; pattern left blank */]>,
726 Requires<[IsARM, HasV6]> {
727 let Inst{11-10} = 0b00;
729 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
731 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
732 [/* For disassembly only; pattern left blank */]>,
733 Requires<[IsARM, HasV6]> {
736 let Inst{19-16} = Rn;
737 let Inst{11-10} = rot;
741 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
742 let Uses = [CPSR] in {
743 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
744 bit Commutable = 0> {
745 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
746 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
747 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
753 let Inst{15-12} = Rd;
754 let Inst{19-16} = Rn;
755 let Inst{11-0} = imm;
757 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
758 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
759 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
764 let Inst{11-4} = 0b00000000;
766 let isCommutable = Commutable;
768 let Inst{15-12} = Rd;
769 let Inst{19-16} = Rn;
771 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
772 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
773 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
779 let Inst{11-0} = shift;
780 let Inst{15-12} = Rd;
781 let Inst{19-16} = Rn;
784 // Carry setting variants
785 let Defs = [CPSR] in {
786 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
787 bit Commutable = 0> {
788 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
789 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
790 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
795 let Inst{15-12} = Rd;
796 let Inst{19-16} = Rn;
797 let Inst{11-0} = imm;
801 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
802 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
803 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
808 let Inst{11-4} = 0b00000000;
809 let isCommutable = Commutable;
811 let Inst{15-12} = Rd;
812 let Inst{19-16} = Rn;
816 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
817 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
818 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
823 let Inst{11-0} = shift;
824 let Inst{15-12} = Rd;
825 let Inst{19-16} = Rn;
833 let canFoldAsLoad = 1, isReMaterializable = 1 in {
834 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
835 InstrItinClass iir, PatFrag opnode> {
836 // Note: We use the complex addrmode_imm12 rather than just an input
837 // GPR and a constrained immediate so that we can use this to match
838 // frame index references and avoid matching constant pool references.
839 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
840 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
841 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
844 let Inst{23} = addr{12}; // U (add = ('U' == 1))
845 let Inst{19-16} = addr{16-13}; // Rn
846 let Inst{15-12} = Rt;
847 let Inst{11-0} = addr{11-0}; // imm12
849 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
850 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
851 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
854 let Inst{23} = shift{12}; // U (add = ('U' == 1))
855 let Inst{19-16} = shift{16-13}; // Rn
856 let Inst{15-12} = Rt;
857 let Inst{11-0} = shift{11-0};
862 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
863 InstrItinClass iir, PatFrag opnode> {
864 // Note: We use the complex addrmode_imm12 rather than just an input
865 // GPR and a constrained immediate so that we can use this to match
866 // frame index references and avoid matching constant pool references.
867 def i12 : AIldst1<0b010, opc22, 0, (outs),
868 (ins GPR:$Rt, addrmode_imm12:$addr),
869 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
870 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
873 let Inst{23} = addr{12}; // U (add = ('U' == 1))
874 let Inst{19-16} = addr{16-13}; // Rn
875 let Inst{15-12} = Rt;
876 let Inst{11-0} = addr{11-0}; // imm12
878 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
879 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
880 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
883 let Inst{23} = shift{12}; // U (add = ('U' == 1))
884 let Inst{19-16} = shift{16-13}; // Rn
885 let Inst{15-12} = Rt;
886 let Inst{11-0} = shift{11-0};
889 //===----------------------------------------------------------------------===//
891 //===----------------------------------------------------------------------===//
893 //===----------------------------------------------------------------------===//
894 // Miscellaneous Instructions.
897 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
898 /// the function. The first operand is the ID# for this instruction, the second
899 /// is the index into the MachineConstantPool that this is, the third is the
900 /// size in bytes of this constant pool entry.
901 let neverHasSideEffects = 1, isNotDuplicable = 1 in
902 def CONSTPOOL_ENTRY :
903 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
904 i32imm:$size), NoItinerary, "", []>;
906 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
907 // from removing one half of the matched pairs. That breaks PEI, which assumes
908 // these will always be in pairs, and asserts if it finds otherwise. Better way?
909 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
911 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
912 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
914 def ADJCALLSTACKDOWN :
915 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
916 [(ARMcallseq_start timm:$amt)]>;
919 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
920 [/* For disassembly only; pattern left blank */]>,
921 Requires<[IsARM, HasV6T2]> {
922 let Inst{27-16} = 0b001100100000;
923 let Inst{15-8} = 0b11110000;
924 let Inst{7-0} = 0b00000000;
927 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
928 [/* For disassembly only; pattern left blank */]>,
929 Requires<[IsARM, HasV6T2]> {
930 let Inst{27-16} = 0b001100100000;
931 let Inst{15-8} = 0b11110000;
932 let Inst{7-0} = 0b00000001;
935 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
936 [/* For disassembly only; pattern left blank */]>,
937 Requires<[IsARM, HasV6T2]> {
938 let Inst{27-16} = 0b001100100000;
939 let Inst{15-8} = 0b11110000;
940 let Inst{7-0} = 0b00000010;
943 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
944 [/* For disassembly only; pattern left blank */]>,
945 Requires<[IsARM, HasV6T2]> {
946 let Inst{27-16} = 0b001100100000;
947 let Inst{15-8} = 0b11110000;
948 let Inst{7-0} = 0b00000011;
951 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
953 [/* For disassembly only; pattern left blank */]>,
954 Requires<[IsARM, HasV6]> {
959 let Inst{15-12} = Rd;
960 let Inst{19-16} = Rn;
961 let Inst{27-20} = 0b01101000;
962 let Inst{7-4} = 0b1011;
963 let Inst{11-8} = 0b1111;
966 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
967 [/* For disassembly only; pattern left blank */]>,
968 Requires<[IsARM, HasV6T2]> {
969 let Inst{27-16} = 0b001100100000;
970 let Inst{15-8} = 0b11110000;
971 let Inst{7-0} = 0b00000100;
974 // The i32imm operand $val can be used by a debugger to store more information
975 // about the breakpoint.
976 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
977 [/* For disassembly only; pattern left blank */]>,
980 let Inst{3-0} = val{3-0};
981 let Inst{19-8} = val{15-4};
982 let Inst{27-20} = 0b00010010;
983 let Inst{7-4} = 0b0111;
986 // Change Processor State is a system instruction -- for disassembly only.
987 // The singleton $opt operand contains the following information:
988 // opt{4-0} = mode from Inst{4-0}
989 // opt{5} = changemode from Inst{17}
990 // opt{8-6} = AIF from Inst{8-6}
991 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
992 // FIXME: Integrated assembler will need these split out.
993 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
994 [/* For disassembly only; pattern left blank */]>,
996 let Inst{31-28} = 0b1111;
997 let Inst{27-20} = 0b00010000;
1002 // Preload signals the memory system of possible future data/instruction access.
1003 // These are for disassembly only.
1004 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1006 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1007 !strconcat(opc, "\t$addr"),
1008 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1011 let Inst{31-26} = 0b111101;
1012 let Inst{25} = 0; // 0 for immediate form
1013 let Inst{24} = data;
1014 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1015 let Inst{22} = read;
1016 let Inst{21-20} = 0b01;
1017 let Inst{19-16} = addr{16-13}; // Rn
1018 let Inst{15-12} = Rt;
1019 let Inst{11-0} = addr{11-0}; // imm12
1022 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1023 !strconcat(opc, "\t$shift"),
1024 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1027 let Inst{31-26} = 0b111101;
1028 let Inst{25} = 1; // 1 for register form
1029 let Inst{24} = data;
1030 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1031 let Inst{22} = read;
1032 let Inst{21-20} = 0b01;
1033 let Inst{19-16} = shift{16-13}; // Rn
1034 let Inst{11-0} = shift{11-0};
1038 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1039 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1040 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1042 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1044 [/* For disassembly only; pattern left blank */]>,
1047 let Inst{31-10} = 0b1111000100000001000000;
1052 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1053 [/* For disassembly only; pattern left blank */]>,
1054 Requires<[IsARM, HasV7]> {
1056 let Inst{27-4} = 0b001100100000111100001111;
1057 let Inst{3-0} = opt;
1060 // A5.4 Permanently UNDEFINED instructions.
1061 let isBarrier = 1, isTerminator = 1 in
1062 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1065 let Inst{27-25} = 0b011;
1066 let Inst{24-20} = 0b11111;
1067 let Inst{7-5} = 0b111;
1071 // Address computation and loads and stores in PIC mode.
1072 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1073 // classes (AXI1, et.al.) and so have encoding information and such,
1074 // which is suboptimal. Once the rest of the code emitter (including
1075 // JIT) is MC-ized we should look at refactoring these into true
1076 // pseudos. As is, the encoding information ends up being ignored,
1077 // as these instructions are lowered to individual MC-insts.
1078 let isNotDuplicable = 1 in {
1079 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1080 Pseudo, IIC_iALUr, "",
1081 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1083 let AddedComplexity = 10 in {
1084 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1085 Pseudo, IIC_iLoad_r, "",
1086 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1088 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1089 Pseudo, IIC_iLoad_bh_r, "",
1090 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1092 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1093 Pseudo, IIC_iLoad_bh_r, "",
1094 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1096 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1097 Pseudo, IIC_iLoad_bh_r, "",
1098 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1100 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1101 Pseudo, IIC_iLoad_bh_r, "",
1102 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1104 let AddedComplexity = 10 in {
1105 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1106 Pseudo, IIC_iStore_r, "",
1107 [(store GPR:$src, addrmodepc:$addr)]>;
1109 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1110 Pseudo, IIC_iStore_bh_r, "",
1111 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1113 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1114 Pseudo, IIC_iStore_bh_r, "",
1115 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1117 } // isNotDuplicable = 1
1120 // LEApcrel - Load a pc-relative address into a register without offending the
1122 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1123 // the ADR instruction. Is this the right way to handle that? They need
1124 // encoding information regardless.
1125 let neverHasSideEffects = 1 in {
1126 let isReMaterializable = 1 in
1127 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1129 "adr$p\t$dst, #$label", []>;
1131 } // neverHasSideEffects
1132 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1133 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1135 "adr$p\t$dst, #${label}_${id}", []> {
1139 //===----------------------------------------------------------------------===//
1140 // Control Flow Instructions.
1143 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1145 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1146 "bx", "\tlr", [(ARMretflag)]>,
1147 Requires<[IsARM, HasV4T]> {
1148 let Inst{27-0} = 0b0001001011111111111100011110;
1152 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1153 "mov", "\tpc, lr", [(ARMretflag)]>,
1154 Requires<[IsARM, NoV4T]> {
1155 let Inst{27-0} = 0b0001101000001111000000001110;
1159 // Indirect branches
1160 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1162 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1163 [(brind GPR:$dst)]>,
1164 Requires<[IsARM, HasV4T]> {
1166 let Inst{31-4} = 0b1110000100101111111111110001;
1167 let Inst{3-0} = dst;
1171 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1172 [(brind GPR:$dst)]>,
1173 Requires<[IsARM, NoV4T]> {
1175 let Inst{31-4} = 0b1110000110100000111100000000;
1176 let Inst{3-0} = dst;
1180 // FIXME: remove when we have a way to marking a MI with these properties.
1181 // FIXME: Should pc be an implicit operand like PICADD, etc?
1182 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1183 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1184 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
1185 reglist:$dsts, variable_ops),
1186 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1187 "ldm${mode}${p}\t$Rn!, $dsts",
1192 // On non-Darwin platforms R9 is callee-saved.
1194 Defs = [R0, R1, R2, R3, R12, LR,
1195 D0, D1, D2, D3, D4, D5, D6, D7,
1196 D16, D17, D18, D19, D20, D21, D22, D23,
1197 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1198 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1199 IIC_Br, "bl\t$func",
1200 [(ARMcall tglobaladdr:$func)]>,
1201 Requires<[IsARM, IsNotDarwin]> {
1202 let Inst{31-28} = 0b1110;
1203 // FIXME: Encoding info for $func. Needs fixups bits.
1206 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1207 IIC_Br, "bl", "\t$func",
1208 [(ARMcall_pred tglobaladdr:$func)]>,
1209 Requires<[IsARM, IsNotDarwin]>;
1212 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1213 IIC_Br, "blx\t$func",
1214 [(ARMcall GPR:$func)]>,
1215 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1217 let Inst{27-4} = 0b000100101111111111110011;
1218 let Inst{3-0} = func;
1222 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1223 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1224 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1225 [(ARMcall_nolink tGPR:$func)]>,
1226 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1228 let Inst{27-4} = 0b000100101111111111110001;
1229 let Inst{3-0} = func;
1233 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1234 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1235 [(ARMcall_nolink tGPR:$func)]>,
1236 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1238 let Inst{27-4} = 0b000110100000111100000000;
1239 let Inst{3-0} = func;
1243 // On Darwin R9 is call-clobbered.
1245 Defs = [R0, R1, R2, R3, R9, R12, LR,
1246 D0, D1, D2, D3, D4, D5, D6, D7,
1247 D16, D17, D18, D19, D20, D21, D22, D23,
1248 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1249 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1250 IIC_Br, "bl\t$func",
1251 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1252 let Inst{31-28} = 0b1110;
1253 // FIXME: Encoding info for $func. Needs fixups bits.
1256 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1257 IIC_Br, "bl", "\t$func",
1258 [(ARMcall_pred tglobaladdr:$func)]>,
1259 Requires<[IsARM, IsDarwin]>;
1262 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1263 IIC_Br, "blx\t$func",
1264 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1266 let Inst{27-4} = 0b000100101111111111110011;
1267 let Inst{3-0} = func;
1271 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1272 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1273 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1274 [(ARMcall_nolink tGPR:$func)]>,
1275 Requires<[IsARM, HasV4T, IsDarwin]> {
1277 let Inst{27-4} = 0b000100101111111111110001;
1278 let Inst{3-0} = func;
1282 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1283 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1284 [(ARMcall_nolink tGPR:$func)]>,
1285 Requires<[IsARM, NoV4T, IsDarwin]> {
1287 let Inst{27-4} = 0b000110100000111100000000;
1288 let Inst{3-0} = func;
1294 // FIXME: These should probably be xformed into the non-TC versions of the
1295 // instructions as part of MC lowering.
1296 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1298 let Defs = [R0, R1, R2, R3, R9, R12,
1299 D0, D1, D2, D3, D4, D5, D6, D7,
1300 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1301 D27, D28, D29, D30, D31, PC],
1303 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1305 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1307 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1309 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1311 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1312 IIC_Br, "b\t$dst @ TAILCALL",
1313 []>, Requires<[IsDarwin]>;
1315 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1316 IIC_Br, "b.w\t$dst @ TAILCALL",
1317 []>, Requires<[IsDarwin]>;
1319 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1320 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1321 []>, Requires<[IsDarwin]> {
1323 let Inst{31-4} = 0b1110000100101111111111110001;
1324 let Inst{3-0} = dst;
1328 // Non-Darwin versions (the difference is R9).
1329 let Defs = [R0, R1, R2, R3, R12,
1330 D0, D1, D2, D3, D4, D5, D6, D7,
1331 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1332 D27, D28, D29, D30, D31, PC],
1334 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1336 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1338 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1340 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1342 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1343 IIC_Br, "b\t$dst @ TAILCALL",
1344 []>, Requires<[IsARM, IsNotDarwin]>;
1346 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1347 IIC_Br, "b.w\t$dst @ TAILCALL",
1348 []>, Requires<[IsThumb, IsNotDarwin]>;
1350 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1351 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1352 []>, Requires<[IsNotDarwin]> {
1354 let Inst{31-4} = 0b1110000100101111111111110001;
1355 let Inst{3-0} = dst;
1360 let isBranch = 1, isTerminator = 1 in {
1361 // B is "predicable" since it can be xformed into a Bcc.
1362 let isBarrier = 1 in {
1363 let isPredicable = 1 in
1364 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1365 "b\t$target", [(br bb:$target)]>;
1367 let isNotDuplicable = 1, isIndirectBranch = 1,
1368 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1369 isCodeGenOnly = 1 in {
1370 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1371 IIC_Br, "mov\tpc, $target$jt",
1372 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1373 let Inst{11-4} = 0b00000000;
1374 let Inst{15-12} = 0b1111;
1375 let Inst{20} = 0; // S Bit
1376 let Inst{24-21} = 0b1101;
1377 let Inst{27-25} = 0b000;
1379 def BR_JTm : JTI<(outs),
1380 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1381 IIC_Br, "ldr\tpc, $target$jt",
1382 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1384 let Inst{15-12} = 0b1111;
1385 let Inst{20} = 1; // L bit
1386 let Inst{21} = 0; // W bit
1387 let Inst{22} = 0; // B bit
1388 let Inst{24} = 1; // P bit
1389 let Inst{27-25} = 0b011;
1391 def BR_JTadd : JTI<(outs),
1392 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1393 IIC_Br, "add\tpc, $target, $idx$jt",
1394 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1396 let Inst{15-12} = 0b1111;
1397 let Inst{20} = 0; // S bit
1398 let Inst{24-21} = 0b0100;
1399 let Inst{27-25} = 0b000;
1401 } // isNotDuplicable = 1, isIndirectBranch = 1
1404 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1405 // a two-value operand where a dag node expects two operands. :(
1406 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1407 IIC_Br, "b", "\t$target",
1408 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1411 // Branch and Exchange Jazelle -- for disassembly only
1412 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1413 [/* For disassembly only; pattern left blank */]> {
1414 let Inst{23-20} = 0b0010;
1415 //let Inst{19-8} = 0xfff;
1416 let Inst{7-4} = 0b0010;
1419 // Secure Monitor Call is a system instruction -- for disassembly only
1420 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1421 [/* For disassembly only; pattern left blank */]> {
1423 let Inst{23-4} = 0b01100000000000000111;
1424 let Inst{3-0} = opt;
1427 // Supervisor Call (Software Interrupt) -- for disassembly only
1429 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1430 [/* For disassembly only; pattern left blank */]> {
1432 let Inst{23-0} = svc;
1436 // Store Return State is a system instruction -- for disassembly only
1437 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1438 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1439 NoItinerary, "srs${amode}\tsp!, $mode",
1440 [/* For disassembly only; pattern left blank */]> {
1441 let Inst{31-28} = 0b1111;
1442 let Inst{22-20} = 0b110; // W = 1
1445 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1446 NoItinerary, "srs${amode}\tsp, $mode",
1447 [/* For disassembly only; pattern left blank */]> {
1448 let Inst{31-28} = 0b1111;
1449 let Inst{22-20} = 0b100; // W = 0
1452 // Return From Exception is a system instruction -- for disassembly only
1453 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1454 NoItinerary, "rfe${amode}\t$base!",
1455 [/* For disassembly only; pattern left blank */]> {
1456 let Inst{31-28} = 0b1111;
1457 let Inst{22-20} = 0b011; // W = 1
1460 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1461 NoItinerary, "rfe${amode}\t$base",
1462 [/* For disassembly only; pattern left blank */]> {
1463 let Inst{31-28} = 0b1111;
1464 let Inst{22-20} = 0b001; // W = 0
1466 } // isCodeGenOnly = 1
1468 //===----------------------------------------------------------------------===//
1469 // Load / store Instructions.
1475 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1476 UnOpFrag<(load node:$Src)>>;
1477 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1478 UnOpFrag<(zextloadi8 node:$Src)>>;
1479 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1480 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1481 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1482 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1484 // Special LDR for loads from non-pc-relative constpools.
1485 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1486 isReMaterializable = 1 in
1487 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1488 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1491 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1492 let Inst{19-16} = 0b1111;
1493 let Inst{15-12} = Rt;
1494 let Inst{11-0} = addr{11-0}; // imm12
1497 // Loads with zero extension
1498 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1499 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1500 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1502 // Loads with sign extension
1503 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1504 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1505 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1507 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1508 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1509 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1511 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1512 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1514 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1515 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1516 []>, Requires<[IsARM, HasV5TE]>;
1519 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1520 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1521 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1523 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1524 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1525 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1527 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1528 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1529 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1531 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1532 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1533 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1535 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1536 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1537 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1539 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1540 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1541 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1543 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1544 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1545 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1547 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1548 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1549 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1551 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1552 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1553 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1555 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1556 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1557 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1559 // For disassembly only
1560 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1561 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1562 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1563 Requires<[IsARM, HasV5TE]>;
1565 // For disassembly only
1566 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1567 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1568 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1569 Requires<[IsARM, HasV5TE]>;
1571 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1573 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1575 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1576 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1577 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1578 let Inst{21} = 1; // overwrite
1581 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1582 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1583 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1584 let Inst{21} = 1; // overwrite
1587 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1588 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1589 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1590 let Inst{21} = 1; // overwrite
1593 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1594 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1595 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1596 let Inst{21} = 1; // overwrite
1599 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1600 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1601 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1602 let Inst{21} = 1; // overwrite
1607 // Stores with truncate
1608 def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1609 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1610 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1613 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1614 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1615 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1616 StMiscFrm, IIC_iStore_d_r,
1617 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1620 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1621 (ins GPR:$src, GPR:$base, am2offset:$offset),
1622 StFrm, IIC_iStore_ru,
1623 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1625 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1627 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1628 (ins GPR:$src, GPR:$base,am2offset:$offset),
1629 StFrm, IIC_iStore_ru,
1630 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1632 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1634 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1635 (ins GPR:$src, GPR:$base,am3offset:$offset),
1636 StMiscFrm, IIC_iStore_ru,
1637 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1639 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1641 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1642 (ins GPR:$src, GPR:$base,am3offset:$offset),
1643 StMiscFrm, IIC_iStore_bh_ru,
1644 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1645 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1646 GPR:$base, am3offset:$offset))]>;
1648 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1649 (ins GPR:$src, GPR:$base,am2offset:$offset),
1650 StFrm, IIC_iStore_bh_ru,
1651 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1652 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1653 GPR:$base, am2offset:$offset))]>;
1655 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1656 (ins GPR:$src, GPR:$base,am2offset:$offset),
1657 StFrm, IIC_iStore_bh_ru,
1658 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1659 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1660 GPR:$base, am2offset:$offset))]>;
1662 // For disassembly only
1663 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1664 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1665 StMiscFrm, IIC_iStore_d_ru,
1666 "strd", "\t$src1, $src2, [$base, $offset]!",
1667 "$base = $base_wb", []>;
1669 // For disassembly only
1670 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1671 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1672 StMiscFrm, IIC_iStore_d_ru,
1673 "strd", "\t$src1, $src2, [$base], $offset",
1674 "$base = $base_wb", []>;
1676 // STRT, STRBT, and STRHT are for disassembly only.
1678 def STRT : AI2stwpo<(outs GPR:$base_wb),
1679 (ins GPR:$src, GPR:$base,am2offset:$offset),
1680 StFrm, IIC_iStore_ru,
1681 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1682 [/* For disassembly only; pattern left blank */]> {
1683 let Inst{21} = 1; // overwrite
1686 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1687 (ins GPR:$src, GPR:$base,am2offset:$offset),
1688 StFrm, IIC_iStore_bh_ru,
1689 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1690 [/* For disassembly only; pattern left blank */]> {
1691 let Inst{21} = 1; // overwrite
1694 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1695 (ins GPR:$src, GPR:$base,am3offset:$offset),
1696 StMiscFrm, IIC_iStore_bh_ru,
1697 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1698 [/* For disassembly only; pattern left blank */]> {
1699 let Inst{21} = 1; // overwrite
1702 //===----------------------------------------------------------------------===//
1703 // Load / store multiple Instructions.
1706 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1707 isCodeGenOnly = 1 in {
1708 def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1709 reglist:$dsts, variable_ops),
1710 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1711 "ldm${amode}${p}\t$Rn, $dsts", "", []> {
1715 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1716 reglist:$dsts, variable_ops),
1717 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1718 "ldm${amode}${p}\t$Rn!, $dsts",
1722 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1724 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1725 isCodeGenOnly = 1 in {
1726 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1727 reglist:$srcs, variable_ops),
1728 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1729 "stm${amode}${p}\t$Rn, $srcs", "", []> {
1733 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1734 reglist:$srcs, variable_ops),
1735 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1736 "stm${amode}${p}\t$Rn!, $srcs",
1739 let Inst{31-28} = p;
1742 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1744 //===----------------------------------------------------------------------===//
1745 // Move Instructions.
1748 let neverHasSideEffects = 1 in
1749 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1750 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1754 let Inst{11-4} = 0b00000000;
1757 let Inst{15-12} = Rd;
1760 // A version for the smaller set of tail call registers.
1761 let neverHasSideEffects = 1 in
1762 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1763 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1767 let Inst{11-4} = 0b00000000;
1770 let Inst{15-12} = Rd;
1773 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1774 DPSoRegFrm, IIC_iMOVsr,
1775 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1779 let Inst{15-12} = Rd;
1780 let Inst{11-0} = src;
1784 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1785 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1786 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1790 let Inst{15-12} = Rd;
1791 let Inst{19-16} = 0b0000;
1792 let Inst{11-0} = imm;
1795 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1796 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1798 "movw", "\t$Rd, $imm",
1799 [(set GPR:$Rd, imm0_65535:$imm)]>,
1800 Requires<[IsARM, HasV6T2]>, UnaryDP {
1803 let Inst{15-12} = Rd;
1804 let Inst{11-0} = imm{11-0};
1805 let Inst{19-16} = imm{15-12};
1810 let Constraints = "$src = $Rd" in
1811 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1813 "movt", "\t$Rd, $imm",
1815 (or (and GPR:$src, 0xffff),
1816 lo16AllZero:$imm))]>, UnaryDP,
1817 Requires<[IsARM, HasV6T2]> {
1820 let Inst{15-12} = Rd;
1821 let Inst{11-0} = imm{11-0};
1822 let Inst{19-16} = imm{15-12};
1827 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1828 Requires<[IsARM, HasV6T2]>;
1830 let Uses = [CPSR] in
1831 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1832 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1835 // These aren't really mov instructions, but we have to define them this way
1836 // due to flag operands.
1838 let Defs = [CPSR] in {
1839 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1840 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1842 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1843 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1847 //===----------------------------------------------------------------------===//
1848 // Extend Instructions.
1853 defm SXTB : AI_ext_rrot<0b01101010,
1854 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1855 defm SXTH : AI_ext_rrot<0b01101011,
1856 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1858 defm SXTAB : AI_exta_rrot<0b01101010,
1859 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1860 defm SXTAH : AI_exta_rrot<0b01101011,
1861 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1863 // For disassembly only
1864 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1866 // For disassembly only
1867 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1871 let AddedComplexity = 16 in {
1872 defm UXTB : AI_ext_rrot<0b01101110,
1873 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1874 defm UXTH : AI_ext_rrot<0b01101111,
1875 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1876 defm UXTB16 : AI_ext_rrot<0b01101100,
1877 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1879 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1880 // The transformation should probably be done as a combiner action
1881 // instead so we can include a check for masking back in the upper
1882 // eight bits of the source into the lower eight bits of the result.
1883 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1884 // (UXTB16r_rot GPR:$Src, 24)>;
1885 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1886 (UXTB16r_rot GPR:$Src, 8)>;
1888 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1889 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1890 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1891 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1894 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1895 // For disassembly only
1896 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1899 def SBFX : I<(outs GPR:$Rd),
1900 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1901 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1902 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1903 Requires<[IsARM, HasV6T2]> {
1908 let Inst{27-21} = 0b0111101;
1909 let Inst{6-4} = 0b101;
1910 let Inst{20-16} = width;
1911 let Inst{15-12} = Rd;
1912 let Inst{11-7} = lsb;
1916 def UBFX : I<(outs GPR:$Rd),
1917 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1918 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1919 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1920 Requires<[IsARM, HasV6T2]> {
1925 let Inst{27-21} = 0b0111111;
1926 let Inst{6-4} = 0b101;
1927 let Inst{20-16} = width;
1928 let Inst{15-12} = Rd;
1929 let Inst{11-7} = lsb;
1933 //===----------------------------------------------------------------------===//
1934 // Arithmetic Instructions.
1937 defm ADD : AsI1_bin_irs<0b0100, "add",
1938 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1939 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1940 defm SUB : AsI1_bin_irs<0b0010, "sub",
1941 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1942 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1944 // ADD and SUB with 's' bit set.
1945 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1946 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1947 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1948 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1949 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1950 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1952 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1953 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1954 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1955 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1956 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1957 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1958 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1959 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1961 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1962 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1963 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1968 let Inst{15-12} = Rd;
1969 let Inst{19-16} = Rn;
1970 let Inst{11-0} = imm;
1973 // The reg/reg form is only defined for the disassembler; for codegen it is
1974 // equivalent to SUBrr.
1975 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1976 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1977 [/* For disassembly only; pattern left blank */]> {
1981 let Inst{11-4} = 0b00000000;
1984 let Inst{15-12} = Rd;
1985 let Inst{19-16} = Rn;
1988 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1989 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1990 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1995 let Inst{11-0} = shift;
1996 let Inst{15-12} = Rd;
1997 let Inst{19-16} = Rn;
2000 // RSB with 's' bit set.
2001 let Defs = [CPSR] in {
2002 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2003 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2004 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2010 let Inst{15-12} = Rd;
2011 let Inst{19-16} = Rn;
2012 let Inst{11-0} = imm;
2014 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2015 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2016 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2022 let Inst{11-0} = shift;
2023 let Inst{15-12} = Rd;
2024 let Inst{19-16} = Rn;
2028 let Uses = [CPSR] in {
2029 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2030 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2031 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2037 let Inst{15-12} = Rd;
2038 let Inst{19-16} = Rn;
2039 let Inst{11-0} = imm;
2041 // The reg/reg form is only defined for the disassembler; for codegen it is
2042 // equivalent to SUBrr.
2043 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2044 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2045 [/* For disassembly only; pattern left blank */]> {
2049 let Inst{11-4} = 0b00000000;
2052 let Inst{15-12} = Rd;
2053 let Inst{19-16} = Rn;
2055 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2056 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2057 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2063 let Inst{11-0} = shift;
2064 let Inst{15-12} = Rd;
2065 let Inst{19-16} = Rn;
2069 // FIXME: Allow these to be predicated.
2070 let Defs = [CPSR], Uses = [CPSR] in {
2071 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2072 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2073 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2080 let Inst{15-12} = Rd;
2081 let Inst{19-16} = Rn;
2082 let Inst{11-0} = imm;
2084 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2085 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2086 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2093 let Inst{11-0} = shift;
2094 let Inst{15-12} = Rd;
2095 let Inst{19-16} = Rn;
2099 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2100 // The assume-no-carry-in form uses the negation of the input since add/sub
2101 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2102 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2104 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2105 (SUBri GPR:$src, so_imm_neg:$imm)>;
2106 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2107 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2108 // The with-carry-in form matches bitwise not instead of the negation.
2109 // Effectively, the inverse interpretation of the carry flag already accounts
2110 // for part of the negation.
2111 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2112 (SBCri GPR:$src, so_imm_not:$imm)>;
2114 // Note: These are implemented in C++ code, because they have to generate
2115 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2117 // (mul X, 2^n+1) -> (add (X << n), X)
2118 // (mul X, 2^n-1) -> (rsb X, (X << n))
2120 // ARM Arithmetic Instruction -- for disassembly only
2121 // GPR:$dst = GPR:$a op GPR:$b
2122 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2123 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2124 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2125 opc, "\t$Rd, $Rn, $Rm", pattern> {
2129 let Inst{27-20} = op27_20;
2130 let Inst{11-4} = op11_4;
2131 let Inst{19-16} = Rn;
2132 let Inst{15-12} = Rd;
2136 // Saturating add/subtract -- for disassembly only
2138 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2139 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2140 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2141 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2142 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2143 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2145 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2146 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2147 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2148 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2149 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2150 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2151 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2152 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2153 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2154 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2155 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2156 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2158 // Signed/Unsigned add/subtract -- for disassembly only
2160 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2161 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2162 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2163 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2164 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2165 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2166 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2167 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2168 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2169 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2170 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2171 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2173 // Signed/Unsigned halving add/subtract -- for disassembly only
2175 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2176 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2177 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2178 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2179 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2180 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2181 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2182 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2183 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2184 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2185 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2186 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2188 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2190 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2191 MulFrm /* for convenience */, NoItinerary, "usad8",
2192 "\t$Rd, $Rn, $Rm", []>,
2193 Requires<[IsARM, HasV6]> {
2197 let Inst{27-20} = 0b01111000;
2198 let Inst{15-12} = 0b1111;
2199 let Inst{7-4} = 0b0001;
2200 let Inst{19-16} = Rd;
2201 let Inst{11-8} = Rm;
2204 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2205 MulFrm /* for convenience */, NoItinerary, "usada8",
2206 "\t$Rd, $Rn, $Rm, $Ra", []>,
2207 Requires<[IsARM, HasV6]> {
2212 let Inst{27-20} = 0b01111000;
2213 let Inst{7-4} = 0b0001;
2214 let Inst{19-16} = Rd;
2215 let Inst{15-12} = Ra;
2216 let Inst{11-8} = Rm;
2220 // Signed/Unsigned saturate -- for disassembly only
2222 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2223 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2224 [/* For disassembly only; pattern left blank */]> {
2229 let Inst{27-21} = 0b0110101;
2230 let Inst{5-4} = 0b01;
2231 let Inst{20-16} = sat_imm;
2232 let Inst{15-12} = Rd;
2233 let Inst{11-7} = sh{7-3};
2234 let Inst{6} = sh{0};
2238 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2239 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2240 [/* For disassembly only; pattern left blank */]> {
2244 let Inst{27-20} = 0b01101010;
2245 let Inst{11-4} = 0b11110011;
2246 let Inst{15-12} = Rd;
2247 let Inst{19-16} = sat_imm;
2251 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2252 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2253 [/* For disassembly only; pattern left blank */]> {
2258 let Inst{27-21} = 0b0110111;
2259 let Inst{5-4} = 0b01;
2260 let Inst{15-12} = Rd;
2261 let Inst{11-7} = sh{7-3};
2262 let Inst{6} = sh{0};
2263 let Inst{20-16} = sat_imm;
2267 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2268 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2269 [/* For disassembly only; pattern left blank */]> {
2273 let Inst{27-20} = 0b01101110;
2274 let Inst{11-4} = 0b11110011;
2275 let Inst{15-12} = Rd;
2276 let Inst{19-16} = sat_imm;
2280 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2281 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2283 //===----------------------------------------------------------------------===//
2284 // Bitwise Instructions.
2287 defm AND : AsI1_bin_irs<0b0000, "and",
2288 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2289 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2290 defm ORR : AsI1_bin_irs<0b1100, "orr",
2291 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2292 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2293 defm EOR : AsI1_bin_irs<0b0001, "eor",
2294 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2295 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2296 defm BIC : AsI1_bin_irs<0b1110, "bic",
2297 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2298 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2300 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2301 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2302 "bfc", "\t$Rd, $imm", "$src = $Rd",
2303 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2304 Requires<[IsARM, HasV6T2]> {
2307 let Inst{27-21} = 0b0111110;
2308 let Inst{6-0} = 0b0011111;
2309 let Inst{15-12} = Rd;
2310 let Inst{11-7} = imm{4-0}; // lsb
2311 let Inst{20-16} = imm{9-5}; // width
2314 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2315 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2316 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2317 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2318 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2319 bf_inv_mask_imm:$imm))]>,
2320 Requires<[IsARM, HasV6T2]> {
2324 let Inst{27-21} = 0b0111110;
2325 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2326 let Inst{15-12} = Rd;
2327 let Inst{11-7} = imm{4-0}; // lsb
2328 let Inst{20-16} = imm{9-5}; // width
2332 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2333 "mvn", "\t$Rd, $Rm",
2334 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2338 let Inst{19-16} = 0b0000;
2339 let Inst{11-4} = 0b00000000;
2340 let Inst{15-12} = Rd;
2343 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2344 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2345 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2350 let Inst{19-16} = 0b0000;
2351 let Inst{15-12} = Rd;
2352 let Inst{11-0} = shift;
2354 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2355 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2356 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2357 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2362 let Inst{19-16} = 0b0000;
2363 let Inst{15-12} = Rd;
2364 let Inst{11-0} = imm;
2367 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2368 (BICri GPR:$src, so_imm_not:$imm)>;
2370 //===----------------------------------------------------------------------===//
2371 // Multiply Instructions.
2373 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2374 string opc, string asm, list<dag> pattern>
2375 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2379 let Inst{19-16} = Rd;
2380 let Inst{11-8} = Rm;
2383 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2384 string opc, string asm, list<dag> pattern>
2385 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2390 let Inst{19-16} = RdHi;
2391 let Inst{15-12} = RdLo;
2392 let Inst{11-8} = Rm;
2396 let isCommutable = 1 in
2397 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2398 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2399 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2401 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2402 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2403 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2405 let Inst{15-12} = Ra;
2408 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2409 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2410 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2411 Requires<[IsARM, HasV6T2]> {
2415 let Inst{19-16} = Rd;
2416 let Inst{11-8} = Rm;
2420 // Extra precision multiplies with low / high results
2422 let neverHasSideEffects = 1 in {
2423 let isCommutable = 1 in {
2424 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2425 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2426 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2428 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2429 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2430 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2433 // Multiply + accumulate
2434 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2435 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2436 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2438 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2439 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2440 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2442 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2443 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2444 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2445 Requires<[IsARM, HasV6]> {
2450 let Inst{19-16} = RdLo;
2451 let Inst{15-12} = RdHi;
2452 let Inst{11-8} = Rm;
2455 } // neverHasSideEffects
2457 // Most significant word multiply
2458 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2459 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2460 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2461 Requires<[IsARM, HasV6]> {
2462 let Inst{15-12} = 0b1111;
2465 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2466 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2467 [/* For disassembly only; pattern left blank */]>,
2468 Requires<[IsARM, HasV6]> {
2469 let Inst{15-12} = 0b1111;
2472 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2473 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2474 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2475 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2476 Requires<[IsARM, HasV6]>;
2478 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2479 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2480 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2481 [/* For disassembly only; pattern left blank */]>,
2482 Requires<[IsARM, HasV6]>;
2484 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2485 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2486 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2487 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2488 Requires<[IsARM, HasV6]>;
2490 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2491 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2492 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2493 [/* For disassembly only; pattern left blank */]>,
2494 Requires<[IsARM, HasV6]>;
2496 multiclass AI_smul<string opc, PatFrag opnode> {
2497 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2498 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2499 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2500 (sext_inreg GPR:$Rm, i16)))]>,
2501 Requires<[IsARM, HasV5TE]>;
2503 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2504 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2505 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2506 (sra GPR:$Rm, (i32 16))))]>,
2507 Requires<[IsARM, HasV5TE]>;
2509 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2510 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2511 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2512 (sext_inreg GPR:$Rm, i16)))]>,
2513 Requires<[IsARM, HasV5TE]>;
2515 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2516 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2517 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2518 (sra GPR:$Rm, (i32 16))))]>,
2519 Requires<[IsARM, HasV5TE]>;
2521 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2522 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2523 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2524 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2525 Requires<[IsARM, HasV5TE]>;
2527 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2528 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2529 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2530 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2531 Requires<[IsARM, HasV5TE]>;
2535 multiclass AI_smla<string opc, PatFrag opnode> {
2536 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2537 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2538 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set GPR:$Rd, (add GPR:$Ra,
2540 (opnode (sext_inreg GPR:$Rn, i16),
2541 (sext_inreg GPR:$Rm, i16))))]>,
2542 Requires<[IsARM, HasV5TE]>;
2544 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2545 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2546 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2547 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2548 (sra GPR:$Rm, (i32 16)))))]>,
2549 Requires<[IsARM, HasV5TE]>;
2551 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2552 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2553 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2554 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2555 (sext_inreg GPR:$Rm, i16))))]>,
2556 Requires<[IsARM, HasV5TE]>;
2558 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2559 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2560 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2561 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2562 (sra GPR:$Rm, (i32 16)))))]>,
2563 Requires<[IsARM, HasV5TE]>;
2565 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2566 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2567 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2568 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2569 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2570 Requires<[IsARM, HasV5TE]>;
2572 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2573 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2574 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2575 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2576 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2577 Requires<[IsARM, HasV5TE]>;
2580 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2581 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2583 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2584 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2585 (ins GPR:$Rn, GPR:$Rm),
2586 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2587 [/* For disassembly only; pattern left blank */]>,
2588 Requires<[IsARM, HasV5TE]>;
2590 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2591 (ins GPR:$Rn, GPR:$Rm),
2592 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2593 [/* For disassembly only; pattern left blank */]>,
2594 Requires<[IsARM, HasV5TE]>;
2596 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2597 (ins GPR:$Rn, GPR:$Rm),
2598 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2599 [/* For disassembly only; pattern left blank */]>,
2600 Requires<[IsARM, HasV5TE]>;
2602 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2603 (ins GPR:$Rn, GPR:$Rm),
2604 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2605 [/* For disassembly only; pattern left blank */]>,
2606 Requires<[IsARM, HasV5TE]>;
2608 // Helper class for AI_smld -- for disassembly only
2609 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2610 InstrItinClass itin, string opc, string asm>
2611 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2618 let Inst{21-20} = 0b00;
2619 let Inst{22} = long;
2620 let Inst{27-23} = 0b01110;
2621 let Inst{11-8} = Rm;
2624 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2625 InstrItinClass itin, string opc, string asm>
2626 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2628 let Inst{15-12} = 0b1111;
2629 let Inst{19-16} = Rd;
2631 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2632 InstrItinClass itin, string opc, string asm>
2633 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2635 let Inst{15-12} = Ra;
2637 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2638 InstrItinClass itin, string opc, string asm>
2639 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2642 let Inst{19-16} = RdHi;
2643 let Inst{15-12} = RdLo;
2646 multiclass AI_smld<bit sub, string opc> {
2648 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2649 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2651 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2652 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2654 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2655 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2656 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2658 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2659 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2660 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2664 defm SMLA : AI_smld<0, "smla">;
2665 defm SMLS : AI_smld<1, "smls">;
2667 multiclass AI_sdml<bit sub, string opc> {
2669 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2670 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2671 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2672 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2675 defm SMUA : AI_sdml<0, "smua">;
2676 defm SMUS : AI_sdml<1, "smus">;
2678 //===----------------------------------------------------------------------===//
2679 // Misc. Arithmetic Instructions.
2682 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2683 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2684 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2686 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2687 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2688 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2689 Requires<[IsARM, HasV6T2]>;
2691 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2692 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2693 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2695 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2696 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2698 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2699 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2700 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2701 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2702 Requires<[IsARM, HasV6]>;
2704 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2705 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2708 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2709 (shl GPR:$Rm, (i32 8))), i16))]>,
2710 Requires<[IsARM, HasV6]>;
2712 def lsl_shift_imm : SDNodeXForm<imm, [{
2713 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2714 return CurDAG->getTargetConstant(Sh, MVT::i32);
2717 def lsl_amt : PatLeaf<(i32 imm), [{
2718 return (N->getZExtValue() < 32);
2721 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2722 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2723 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2724 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2725 (and (shl GPR:$Rm, lsl_amt:$sh),
2727 Requires<[IsARM, HasV6]>;
2729 // Alternate cases for PKHBT where identities eliminate some nodes.
2730 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2731 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2732 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2733 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2735 def asr_shift_imm : SDNodeXForm<imm, [{
2736 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2737 return CurDAG->getTargetConstant(Sh, MVT::i32);
2740 def asr_amt : PatLeaf<(i32 imm), [{
2741 return (N->getZExtValue() <= 32);
2744 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2745 // will match the pattern below.
2746 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2747 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2748 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2749 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2750 (and (sra GPR:$Rm, asr_amt:$sh),
2752 Requires<[IsARM, HasV6]>;
2754 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2755 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2756 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2757 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2758 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2759 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2760 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2762 //===----------------------------------------------------------------------===//
2763 // Comparison Instructions...
2766 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2767 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2768 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2770 // FIXME: We have to be careful when using the CMN instruction and comparison
2771 // with 0. One would expect these two pieces of code should give identical
2787 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2788 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2789 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2790 // value of r0 and the carry bit (because the "carry bit" parameter to
2791 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2792 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2793 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2794 // parameter to AddWithCarry is defined as 0).
2796 // When x is 0 and unsigned:
2800 // ~x + 1 = 0x1 0000 0000
2801 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2803 // Therefore, we should disable CMN when comparing against zero, until we can
2804 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2805 // when it's a comparison which doesn't look at the 'carry' flag).
2807 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2809 // This is related to <rdar://problem/7569620>.
2811 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2812 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2814 // Note that TST/TEQ don't set all the same flags that CMP does!
2815 defm TST : AI1_cmp_irs<0b1000, "tst",
2816 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2817 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2818 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2819 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2820 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2822 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2823 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2824 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2825 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2826 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2827 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2829 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2830 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2832 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2833 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2835 // Pseudo i64 compares for some floating point compares.
2836 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2838 def BCCi64 : PseudoInst<(outs),
2839 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2841 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2843 def BCCZi64 : PseudoInst<(outs),
2844 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2845 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2846 } // usesCustomInserter
2849 // Conditional moves
2850 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2851 // a two-value operand where a dag node expects two operands. :(
2852 // FIXME: These should all be pseudo-instructions that get expanded to
2853 // the normal MOV instructions. That would fix the dependency on
2854 // special casing them in tblgen.
2855 let neverHasSideEffects = 1 in {
2856 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2857 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2858 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2859 RegConstraint<"$false = $Rd">, UnaryDP {
2864 let Inst{15-12} = Rd;
2865 let Inst{11-4} = 0b00000000;
2869 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2870 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2871 "mov", "\t$Rd, $shift",
2872 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2873 RegConstraint<"$false = $Rd">, UnaryDP {
2879 let Inst{19-16} = Rn;
2880 let Inst{15-12} = Rd;
2881 let Inst{11-0} = shift;
2884 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2886 "movw", "\t$Rd, $imm",
2888 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2894 let Inst{19-16} = imm{15-12};
2895 let Inst{15-12} = Rd;
2896 let Inst{11-0} = imm{11-0};
2899 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2900 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2901 "mov", "\t$Rd, $imm",
2902 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2903 RegConstraint<"$false = $Rd">, UnaryDP {
2908 let Inst{19-16} = 0b0000;
2909 let Inst{15-12} = Rd;
2910 let Inst{11-0} = imm;
2912 } // neverHasSideEffects
2914 //===----------------------------------------------------------------------===//
2915 // Atomic operations intrinsics
2918 def memb_opt : Operand<i32> {
2919 let PrintMethod = "printMemBOption";
2922 // memory barriers protect the atomic sequences
2923 let hasSideEffects = 1 in {
2924 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2925 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2926 Requires<[IsARM, HasDB]> {
2928 let Inst{31-4} = 0xf57ff05;
2929 let Inst{3-0} = opt;
2932 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2933 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2934 [(ARMMemBarrierMCR GPR:$zero)]>,
2935 Requires<[IsARM, HasV6]> {
2936 // FIXME: add encoding
2940 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2942 [/* For disassembly only; pattern left blank */]>,
2943 Requires<[IsARM, HasDB]> {
2945 let Inst{31-4} = 0xf57ff04;
2946 let Inst{3-0} = opt;
2949 // ISB has only full system option -- for disassembly only
2950 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2951 Requires<[IsARM, HasDB]> {
2952 let Inst{31-4} = 0xf57ff06;
2953 let Inst{3-0} = 0b1111;
2956 let usesCustomInserter = 1 in {
2957 let Uses = [CPSR] in {
2958 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2959 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2960 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2961 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2962 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2963 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2964 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2965 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2966 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2967 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2968 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2969 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2970 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2971 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2972 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2973 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2974 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2975 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2976 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2977 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2978 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2979 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2980 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2981 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2982 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2983 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2984 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2985 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2986 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2987 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2988 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2989 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2990 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2991 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2992 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2993 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2994 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2995 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2996 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2997 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2998 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2999 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3000 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3001 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3002 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3003 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3004 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3005 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3006 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3007 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3008 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3009 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3010 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
3011 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3013 def ATOMIC_SWAP_I8 : PseudoInst<
3014 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3015 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3016 def ATOMIC_SWAP_I16 : PseudoInst<
3017 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3018 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3019 def ATOMIC_SWAP_I32 : PseudoInst<
3020 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3021 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3023 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3024 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3025 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3026 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3027 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3028 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3029 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3030 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3031 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3035 let mayLoad = 1 in {
3036 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3037 "ldrexb", "\t$Rt, [$Rn]",
3039 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3040 "ldrexh", "\t$Rt, [$Rn]",
3042 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3043 "ldrex", "\t$Rt, [$Rn]",
3045 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3047 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3051 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3052 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3054 "strexb", "\t$Rd, $src, [$Rn]",
3056 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3058 "strexh", "\t$Rd, $Rt, [$Rn]",
3060 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3062 "strex", "\t$Rd, $Rt, [$Rn]",
3064 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3065 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3067 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3071 // Clear-Exclusive is for disassembly only.
3072 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3073 [/* For disassembly only; pattern left blank */]>,
3074 Requires<[IsARM, HasV7]> {
3075 let Inst{31-0} = 0b11110101011111111111000000011111;
3078 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3079 let mayLoad = 1 in {
3080 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3081 [/* For disassembly only; pattern left blank */]>;
3082 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3083 [/* For disassembly only; pattern left blank */]>;
3086 //===----------------------------------------------------------------------===//
3090 // __aeabi_read_tp preserves the registers r1-r3.
3091 // FIXME: This needs to be a pseudo of some sort so that we can get the
3092 // encoding right, complete with fixup for the aeabi_read_tp function.
3094 Defs = [R0, R12, LR, CPSR] in {
3095 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3096 "bl\t__aeabi_read_tp",
3097 [(set R0, ARMthread_pointer)]>;
3100 //===----------------------------------------------------------------------===//
3101 // SJLJ Exception handling intrinsics
3102 // eh_sjlj_setjmp() is an instruction sequence to store the return
3103 // address and save #0 in R0 for the non-longjmp case.
3104 // Since by its nature we may be coming from some other function to get
3105 // here, and we're using the stack frame for the containing function to
3106 // save/restore registers, we can't keep anything live in regs across
3107 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3108 // when we get here from a longjmp(). We force everthing out of registers
3109 // except for our own input by listing the relevant registers in Defs. By
3110 // doing so, we also cause the prologue/epilogue code to actively preserve
3111 // all of the callee-saved resgisters, which is exactly what we want.
3112 // A constant value is passed in $val, and we use the location as a scratch.
3114 // These are pseudo-instructions and are lowered to individual MC-insts, so
3115 // no encoding information is necessary.
3117 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3118 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3119 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3120 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3121 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3122 AddrModeNone, SizeSpecial, IndexModeNone,
3123 Pseudo, NoItinerary, "", "",
3124 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3125 Requires<[IsARM, HasVFP2]>;
3129 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3130 hasSideEffects = 1, isBarrier = 1 in {
3131 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3132 AddrModeNone, SizeSpecial, IndexModeNone,
3133 Pseudo, NoItinerary, "", "",
3134 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3135 Requires<[IsARM, NoVFP]>;
3138 // FIXME: Non-Darwin version(s)
3139 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3140 Defs = [ R7, LR, SP ] in {
3141 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3142 AddrModeNone, SizeSpecial, IndexModeNone,
3143 Pseudo, NoItinerary, "", "",
3144 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3145 Requires<[IsARM, IsDarwin]>;
3148 // eh.sjlj.dispatchsetup pseudo-instruction.
3149 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3150 // handled when the pseudo is expanded (which happens before any passes
3151 // that need the instruction size).
3152 let isBarrier = 1, hasSideEffects = 1 in
3153 def Int_eh_sjlj_dispatchsetup :
3154 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3155 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3156 Requires<[IsDarwin]>;
3158 //===----------------------------------------------------------------------===//
3159 // Non-Instruction Patterns
3162 // Large immediate handling.
3164 // Two piece so_imms.
3165 // FIXME: Remove this when we can do generalized remat.
3166 let isReMaterializable = 1 in
3167 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3169 [(set GPR:$dst, (so_imm2part:$src))]>,
3170 Requires<[IsARM, NoV6T2]>;
3172 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3173 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3174 (so_imm2part_2 imm:$RHS))>;
3175 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3176 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3177 (so_imm2part_2 imm:$RHS))>;
3178 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3179 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3180 (so_imm2part_2 imm:$RHS))>;
3181 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3182 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3183 (so_neg_imm2part_2 imm:$RHS))>;
3185 // 32-bit immediate using movw + movt.
3186 // This is a single pseudo instruction, the benefit is that it can be remat'd
3187 // as a single unit instead of having to handle reg inputs.
3188 // FIXME: Remove this when we can do generalized remat.
3189 let isReMaterializable = 1 in
3190 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3191 [(set GPR:$dst, (i32 imm:$src))]>,
3192 Requires<[IsARM, HasV6T2]>;
3194 // ConstantPool, GlobalAddress, and JumpTable
3195 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3196 Requires<[IsARM, DontUseMovt]>;
3197 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3198 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3199 Requires<[IsARM, UseMovt]>;
3200 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3201 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3203 // TODO: add,sub,and, 3-instr forms?
3206 def : ARMPat<(ARMtcret tcGPR:$dst),
3207 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3209 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3210 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3212 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3213 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3215 def : ARMPat<(ARMtcret tcGPR:$dst),
3216 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3218 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3219 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3221 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3222 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3225 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3226 Requires<[IsARM, IsNotDarwin]>;
3227 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3228 Requires<[IsARM, IsDarwin]>;
3230 // zextload i1 -> zextload i8
3231 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3232 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3234 // extload -> zextload
3235 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3236 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3237 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3238 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3240 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3242 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3243 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3246 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3247 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3248 (SMULBB GPR:$a, GPR:$b)>;
3249 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3250 (SMULBB GPR:$a, GPR:$b)>;
3251 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3252 (sra GPR:$b, (i32 16))),
3253 (SMULBT GPR:$a, GPR:$b)>;
3254 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3255 (SMULBT GPR:$a, GPR:$b)>;
3256 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3257 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3258 (SMULTB GPR:$a, GPR:$b)>;
3259 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3260 (SMULTB GPR:$a, GPR:$b)>;
3261 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3263 (SMULWB GPR:$a, GPR:$b)>;
3264 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3265 (SMULWB GPR:$a, GPR:$b)>;
3267 def : ARMV5TEPat<(add GPR:$acc,
3268 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3269 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3270 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3271 def : ARMV5TEPat<(add GPR:$acc,
3272 (mul sext_16_node:$a, sext_16_node:$b)),
3273 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3274 def : ARMV5TEPat<(add GPR:$acc,
3275 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3276 (sra GPR:$b, (i32 16)))),
3277 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3278 def : ARMV5TEPat<(add GPR:$acc,
3279 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3280 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3281 def : ARMV5TEPat<(add GPR:$acc,
3282 (mul (sra GPR:$a, (i32 16)),
3283 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3284 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3285 def : ARMV5TEPat<(add GPR:$acc,
3286 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3287 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3288 def : ARMV5TEPat<(add GPR:$acc,
3289 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3291 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3292 def : ARMV5TEPat<(add GPR:$acc,
3293 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3294 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3296 //===----------------------------------------------------------------------===//
3300 include "ARMInstrThumb.td"
3302 //===----------------------------------------------------------------------===//
3306 include "ARMInstrThumb2.td"
3308 //===----------------------------------------------------------------------===//
3309 // Floating Point Support
3312 include "ARMInstrVFP.td"
3314 //===----------------------------------------------------------------------===//
3315 // Advanced SIMD (NEON) Support
3318 include "ARMInstrNEON.td"
3320 //===----------------------------------------------------------------------===//
3321 // Coprocessor Instructions. For disassembly only.
3324 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3325 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3326 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3327 [/* For disassembly only; pattern left blank */]> {
3331 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3332 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3333 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3334 [/* For disassembly only; pattern left blank */]> {
3335 let Inst{31-28} = 0b1111;
3339 class ACI<dag oops, dag iops, string opc, string asm>
3340 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3341 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3342 let Inst{27-25} = 0b110;
3345 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3347 def _OFFSET : ACI<(outs),
3348 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3349 opc, "\tp$cop, cr$CRd, $addr"> {
3350 let Inst{31-28} = op31_28;
3351 let Inst{24} = 1; // P = 1
3352 let Inst{21} = 0; // W = 0
3353 let Inst{22} = 0; // D = 0
3354 let Inst{20} = load;
3357 def _PRE : ACI<(outs),
3358 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3359 opc, "\tp$cop, cr$CRd, $addr!"> {
3360 let Inst{31-28} = op31_28;
3361 let Inst{24} = 1; // P = 1
3362 let Inst{21} = 1; // W = 1
3363 let Inst{22} = 0; // D = 0
3364 let Inst{20} = load;
3367 def _POST : ACI<(outs),
3368 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3369 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3370 let Inst{31-28} = op31_28;
3371 let Inst{24} = 0; // P = 0
3372 let Inst{21} = 1; // W = 1
3373 let Inst{22} = 0; // D = 0
3374 let Inst{20} = load;
3377 def _OPTION : ACI<(outs),
3378 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3379 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3380 let Inst{31-28} = op31_28;
3381 let Inst{24} = 0; // P = 0
3382 let Inst{23} = 1; // U = 1
3383 let Inst{21} = 0; // W = 0
3384 let Inst{22} = 0; // D = 0
3385 let Inst{20} = load;
3388 def L_OFFSET : ACI<(outs),
3389 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3390 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3391 let Inst{31-28} = op31_28;
3392 let Inst{24} = 1; // P = 1
3393 let Inst{21} = 0; // W = 0
3394 let Inst{22} = 1; // D = 1
3395 let Inst{20} = load;
3398 def L_PRE : ACI<(outs),
3399 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3400 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3401 let Inst{31-28} = op31_28;
3402 let Inst{24} = 1; // P = 1
3403 let Inst{21} = 1; // W = 1
3404 let Inst{22} = 1; // D = 1
3405 let Inst{20} = load;
3408 def L_POST : ACI<(outs),
3409 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3410 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3411 let Inst{31-28} = op31_28;
3412 let Inst{24} = 0; // P = 0
3413 let Inst{21} = 1; // W = 1
3414 let Inst{22} = 1; // D = 1
3415 let Inst{20} = load;
3418 def L_OPTION : ACI<(outs),
3419 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3420 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3421 let Inst{31-28} = op31_28;
3422 let Inst{24} = 0; // P = 0
3423 let Inst{23} = 1; // U = 1
3424 let Inst{21} = 0; // W = 0
3425 let Inst{22} = 1; // D = 1
3426 let Inst{20} = load;
3430 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3431 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3432 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3433 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3435 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3436 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3437 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3438 [/* For disassembly only; pattern left blank */]> {
3443 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3444 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3445 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3446 [/* For disassembly only; pattern left blank */]> {
3447 let Inst{31-28} = 0b1111;
3452 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3453 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3454 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3455 [/* For disassembly only; pattern left blank */]> {
3460 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3461 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3462 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3463 [/* For disassembly only; pattern left blank */]> {
3464 let Inst{31-28} = 0b1111;
3469 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3470 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3471 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3472 [/* For disassembly only; pattern left blank */]> {
3473 let Inst{23-20} = 0b0100;
3476 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3477 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3478 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3479 [/* For disassembly only; pattern left blank */]> {
3480 let Inst{31-28} = 0b1111;
3481 let Inst{23-20} = 0b0100;
3484 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3485 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3486 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3487 [/* For disassembly only; pattern left blank */]> {
3488 let Inst{23-20} = 0b0101;
3491 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3492 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3493 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3494 [/* For disassembly only; pattern left blank */]> {
3495 let Inst{31-28} = 0b1111;
3496 let Inst{23-20} = 0b0101;
3499 //===----------------------------------------------------------------------===//
3500 // Move between special register and ARM core register -- for disassembly only
3503 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3504 [/* For disassembly only; pattern left blank */]> {
3505 let Inst{23-20} = 0b0000;
3506 let Inst{7-4} = 0b0000;
3509 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3510 [/* For disassembly only; pattern left blank */]> {
3511 let Inst{23-20} = 0b0100;
3512 let Inst{7-4} = 0b0000;
3515 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3516 "msr", "\tcpsr$mask, $src",
3517 [/* For disassembly only; pattern left blank */]> {
3518 let Inst{23-20} = 0b0010;
3519 let Inst{7-4} = 0b0000;
3522 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3523 "msr", "\tcpsr$mask, $a",
3524 [/* For disassembly only; pattern left blank */]> {
3525 let Inst{23-20} = 0b0010;
3526 let Inst{7-4} = 0b0000;
3529 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3530 "msr", "\tspsr$mask, $src",
3531 [/* For disassembly only; pattern left blank */]> {
3532 let Inst{23-20} = 0b0110;
3533 let Inst{7-4} = 0b0000;
3536 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3537 "msr", "\tspsr$mask, $a",
3538 [/* For disassembly only; pattern left blank */]> {
3539 let Inst{23-20} = 0b0110;
3540 let Inst{7-4} = 0b0000;